drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31 #include "bnxt_tf_common.h"
  32 #include "ulp_flow_db.h"
  33
  34 #define DRV_MODULE_NAME         "bnxt"
  35 static const char bnxt_version[] =
  36         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  37
  38 /*
  39  * The set of PCI devices this driver supports
  40  */
  41 static const struct rte_pci_id bnxt_pci_id_map[] = {
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  95         { .vendor_id = 0, /* sentinel */ },
  96 };
  97
  98 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  99 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 101 #define BNXT_DEVARG_REPRESENTOR "representor"
 102 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
 103 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
 104 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
 105 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
 106 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
 107 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 108
 109 static const char *const bnxt_dev_args[] = {
 110         BNXT_DEVARG_REPRESENTOR,
 111         BNXT_DEVARG_TRUFLOW,
 112         BNXT_DEVARG_FLOW_XSTAT,
 113         BNXT_DEVARG_MAX_NUM_KFLOWS,
 114         BNXT_DEVARG_REP_BASED_PF,
 115         BNXT_DEVARG_REP_IS_PF,
 116         BNXT_DEVARG_REP_Q_R2F,
 117         BNXT_DEVARG_REP_Q_F2R,
 118         BNXT_DEVARG_REP_FC_R2F,
 119         BNXT_DEVARG_REP_FC_F2R,
 120         NULL
 121 };
 122
 123 /*
 124  * truflow == false to disable the feature
 125  * truflow == true to enable the feature
 126  */
 127 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 128
 129 /*
 130  * flow_xstat == false to disable the feature
 131  * flow_xstat == true to enable the feature
 132  */
 133 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 134
 135 /*
 136  * rep_is_pf == false to indicate VF representor
 137  * rep_is_pf == true to indicate PF representor
 138  */
 139 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 140
 141 /*
 142  * rep_based_pf == Physical index of the PF
 143  */
 144 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 145 /*
 146  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 147  */
 148 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 149
 150 /*
 151  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 152  */
 153 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 154
 155 /*
 156  * rep_fc_r2f == Flow control for the representor to endpoint direction
 157  */
 158 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 159
 160 /*
 161  * rep_fc_f2r == Flow control for the endpoint to representor direction
 162  */
 163 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 164
 165 /*
 166  * max_num_kflows must be >= 32
 167  * and must be a power-of-2 supported value
 168  * return: 1 -> invalid
 169  *         0 -> valid
 170  */
 171 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 172 {
 173         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 174                 return 1;
 175         return 0;
 176 }
 177
 178 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 179 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 180 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 181 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 182 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 183 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 184 static void bnxt_dev_recover(void *arg);
 185 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 186 static void bnxt_free_rep_info(struct bnxt *bp);
 187
 188 int is_bnxt_in_error(struct bnxt *bp)
 189 {
 190         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 191                 return -EIO;
 192         if (bp->flags & BNXT_FLAG_FW_RESET)
 193                 return -EBUSY;
 194
 195         return 0;
 196 }
 197
 198 /***********************/
 199
 200 /*
 201  * High level utility functions
 202  */
 203
 204 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 205 {
 206         if (!BNXT_CHIP_THOR(bp))
 207                 return 1;
 208
 209         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 210                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 211                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 212 }
 213
 214 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 215 {
 216         if (!BNXT_CHIP_THOR(bp))
 217                 return HW_HASH_INDEX_SIZE;
 218
 219         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 220 }
 221
 222 static void bnxt_free_parent_info(struct bnxt *bp)
 223 {
 224         rte_free(bp->parent);
 225 }
 226
 227 static void bnxt_free_pf_info(struct bnxt *bp)
 228 {
 229         rte_free(bp->pf);
 230 }
 231
 232 static void bnxt_free_link_info(struct bnxt *bp)
 233 {
 234         rte_free(bp->link_info);
 235 }
 236
 237 static void bnxt_free_leds_info(struct bnxt *bp)
 238 {
 239         if (BNXT_VF(bp))
 240                 return;
 241
 242         rte_free(bp->leds);
 243         bp->leds = NULL;
 244 }
 245
 246 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 247 {
 248         rte_free(bp->flow_stat);
 249         bp->flow_stat = NULL;
 250 }
 251
 252 static void bnxt_free_cos_queues(struct bnxt *bp)
 253 {
 254         rte_free(bp->rx_cos_queue);
 255         rte_free(bp->tx_cos_queue);
 256 }
 257
 258 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 259 {
 260         bnxt_free_filter_mem(bp);
 261         bnxt_free_vnic_attributes(bp);
 262         bnxt_free_vnic_mem(bp);
 263
 264         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 265          * If the number of rings change across fw update,
 266          * we don't have much choice except to warn the user.
 267          */
 268         if (!reconfig) {
 269                 bnxt_free_stats(bp);
 270                 bnxt_free_tx_rings(bp);
 271                 bnxt_free_rx_rings(bp);
 272         }
 273         bnxt_free_async_cp_ring(bp);
 274         bnxt_free_rxtx_nq_ring(bp);
 275
 276         rte_free(bp->grp_info);
 277         bp->grp_info = NULL;
 278 }
 279
 280 static int bnxt_alloc_parent_info(struct bnxt *bp)
 281 {
 282         bp->parent = rte_zmalloc("bnxt_parent_info",
 283                                  sizeof(struct bnxt_parent_info), 0);
 284         if (bp->parent == NULL)
 285                 return -ENOMEM;
 286
 287         return 0;
 288 }
 289
 290 static int bnxt_alloc_pf_info(struct bnxt *bp)
 291 {
 292         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 293         if (bp->pf == NULL)
 294                 return -ENOMEM;
 295
 296         return 0;
 297 }
 298
 299 static int bnxt_alloc_link_info(struct bnxt *bp)
 300 {
 301         bp->link_info =
 302                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 303         if (bp->link_info == NULL)
 304                 return -ENOMEM;
 305
 306         return 0;
 307 }
 308
 309 static int bnxt_alloc_leds_info(struct bnxt *bp)
 310 {
 311         if (BNXT_VF(bp))
 312                 return 0;
 313
 314         bp->leds = rte_zmalloc("bnxt_leds",
 315                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 316                                0);
 317         if (bp->leds == NULL)
 318                 return -ENOMEM;
 319
 320         return 0;
 321 }
 322
 323 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 324 {
 325         bp->rx_cos_queue =
 326                 rte_zmalloc("bnxt_rx_cosq",
 327                             BNXT_COS_QUEUE_COUNT *
 328                             sizeof(struct bnxt_cos_queue_info),
 329                             0);
 330         if (bp->rx_cos_queue == NULL)
 331                 return -ENOMEM;
 332
 333         bp->tx_cos_queue =
 334                 rte_zmalloc("bnxt_tx_cosq",
 335                             BNXT_COS_QUEUE_COUNT *
 336                             sizeof(struct bnxt_cos_queue_info),
 337                             0);
 338         if (bp->tx_cos_queue == NULL)
 339                 return -ENOMEM;
 340
 341         return 0;
 342 }
 343
 344 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 345 {
 346         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 347                                     sizeof(struct bnxt_flow_stat_info), 0);
 348         if (bp->flow_stat == NULL)
 349                 return -ENOMEM;
 350
 351         return 0;
 352 }
 353
 354 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 355 {
 356         int rc;
 357
 358         rc = bnxt_alloc_ring_grps(bp);
 359         if (rc)
 360                 goto alloc_mem_err;
 361
 362         rc = bnxt_alloc_async_ring_struct(bp);
 363         if (rc)
 364                 goto alloc_mem_err;
 365
 366         rc = bnxt_alloc_vnic_mem(bp);
 367         if (rc)
 368                 goto alloc_mem_err;
 369
 370         rc = bnxt_alloc_vnic_attributes(bp);
 371         if (rc)
 372                 goto alloc_mem_err;
 373
 374         rc = bnxt_alloc_filter_mem(bp);
 375         if (rc)
 376                 goto alloc_mem_err;
 377
 378         rc = bnxt_alloc_async_cp_ring(bp);
 379         if (rc)
 380                 goto alloc_mem_err;
 381
 382         rc = bnxt_alloc_rxtx_nq_ring(bp);
 383         if (rc)
 384                 goto alloc_mem_err;
 385
 386         if (BNXT_FLOW_XSTATS_EN(bp)) {
 387                 rc = bnxt_alloc_flow_stats_info(bp);
 388                 if (rc)
 389                         goto alloc_mem_err;
 390         }
 391
 392         return 0;
 393
 394 alloc_mem_err:
 395         bnxt_free_mem(bp, reconfig);
 396         return rc;
 397 }
 398
 399 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 400 {
 401         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 402         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 403         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 404         struct bnxt_rx_queue *rxq;
 405         unsigned int j;
 406         int rc;
 407
 408         rc = bnxt_vnic_grp_alloc(bp, vnic);
 409         if (rc)
 410                 goto err_out;
 411
 412         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 413                     vnic_id, vnic, vnic->fw_grp_ids);
 414
 415         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 416         if (rc)
 417                 goto err_out;
 418
 419         /* Alloc RSS context only if RSS mode is enabled */
 420         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 421                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 422
 423                 rc = 0;
 424                 for (j = 0; j < nr_ctxs; j++) {
 425                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 426                         if (rc)
 427                                 break;
 428                 }
 429                 if (rc) {
 430                         PMD_DRV_LOG(ERR,
 431                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 432                                     vnic_id, j, rc);
 433                         goto err_out;
 434                 }
 435                 vnic->num_lb_ctxts = nr_ctxs;
 436         }
 437
 438         /*
 439          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 440          * setting is not available at this time, it will not be
 441          * configured correctly in the CFA.
 442          */
 443         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 444                 vnic->vlan_strip = true;
 445         else
 446                 vnic->vlan_strip = false;
 447
 448         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 449         if (rc)
 450                 goto err_out;
 451
 452         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 453         if (rc)
 454                 goto err_out;
 455
 456         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 457                 rxq = bp->eth_dev->data->rx_queues[j];
 458
 459                 PMD_DRV_LOG(DEBUG,
 460                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 461                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 462
 463                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 464                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 465                 else
 466                         vnic->rx_queue_cnt++;
 467         }
 468
 469         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 470
 471         rc = bnxt_vnic_rss_configure(bp, vnic);
 472         if (rc)
 473                 goto err_out;
 474
 475         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 476
 477         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 478                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 479         else
 480                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 481
 482         return 0;
 483 err_out:
 484         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 485                     vnic_id, rc);
 486         return rc;
 487 }
 488
 489 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 490 {
 491         int rc = 0;
 492
 493         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 494                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 495         if (rc)
 496                 return rc;
 497
 498         PMD_DRV_LOG(DEBUG,
 499                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 500                     " rx_fc_in_tbl.ctx_id = %d\n",
 501                     bp->flow_stat->rx_fc_in_tbl.va,
 502                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 503                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 504
 505         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 506                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 507         if (rc)
 508                 return rc;
 509
 510         PMD_DRV_LOG(DEBUG,
 511                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 512                     " rx_fc_out_tbl.ctx_id = %d\n",
 513                     bp->flow_stat->rx_fc_out_tbl.va,
 514                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 515                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 516
 517         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 518                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 519         if (rc)
 520                 return rc;
 521
 522         PMD_DRV_LOG(DEBUG,
 523                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 524                     " tx_fc_in_tbl.ctx_id = %d\n",
 525                     bp->flow_stat->tx_fc_in_tbl.va,
 526                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 527                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 528
 529         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 530                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 531         if (rc)
 532                 return rc;
 533
 534         PMD_DRV_LOG(DEBUG,
 535                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 536                     " tx_fc_out_tbl.ctx_id = %d\n",
 537                     bp->flow_stat->tx_fc_out_tbl.va,
 538                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 539                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 540
 541         memset(bp->flow_stat->rx_fc_out_tbl.va,
 542                0,
 543                bp->flow_stat->rx_fc_out_tbl.size);
 544         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 545                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 546                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 547                                        bp->flow_stat->max_fc,
 548                                        true);
 549         if (rc)
 550                 return rc;
 551
 552         memset(bp->flow_stat->tx_fc_out_tbl.va,
 553                0,
 554                bp->flow_stat->tx_fc_out_tbl.size);
 555         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 556                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 557                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 558                                        bp->flow_stat->max_fc,
 559                                        true);
 560
 561         return rc;
 562 }
 563
 564 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 565                                   struct bnxt_ctx_mem_buf_info *ctx)
 566 {
 567         if (!ctx)
 568                 return -EINVAL;
 569
 570         ctx->va = rte_zmalloc(type, size, 0);
 571         if (ctx->va == NULL)
 572                 return -ENOMEM;
 573         rte_mem_lock_page(ctx->va);
 574         ctx->size = size;
 575         ctx->dma = rte_mem_virt2iova(ctx->va);
 576         if (ctx->dma == RTE_BAD_IOVA)
 577                 return -ENOMEM;
 578
 579         return 0;
 580 }
 581
 582 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 583 {
 584         struct rte_pci_device *pdev = bp->pdev;
 585         char type[RTE_MEMZONE_NAMESIZE];
 586         uint16_t max_fc;
 587         int rc = 0;
 588
 589         max_fc = bp->flow_stat->max_fc;
 590
 591         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 592                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 593         /* 4 bytes for each counter-id */
 594         rc = bnxt_alloc_ctx_mem_buf(type,
 595                                     max_fc * 4,
 596                                     &bp->flow_stat->rx_fc_in_tbl);
 597         if (rc)
 598                 return rc;
 599
 600         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 601                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 602         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 603         rc = bnxt_alloc_ctx_mem_buf(type,
 604                                     max_fc * 16,
 605                                     &bp->flow_stat->rx_fc_out_tbl);
 606         if (rc)
 607                 return rc;
 608
 609         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 610                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 611         /* 4 bytes for each counter-id */
 612         rc = bnxt_alloc_ctx_mem_buf(type,
 613                                     max_fc * 4,
 614                                     &bp->flow_stat->tx_fc_in_tbl);
 615         if (rc)
 616                 return rc;
 617
 618         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 619                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 620         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 621         rc = bnxt_alloc_ctx_mem_buf(type,
 622                                     max_fc * 16,
 623                                     &bp->flow_stat->tx_fc_out_tbl);
 624         if (rc)
 625                 return rc;
 626
 627         rc = bnxt_register_fc_ctx_mem(bp);
 628
 629         return rc;
 630 }
 631
 632 static int bnxt_init_ctx_mem(struct bnxt *bp)
 633 {
 634         int rc = 0;
 635
 636         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 637             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 638             !BNXT_FLOW_XSTATS_EN(bp))
 639                 return 0;
 640
 641         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 642         if (rc)
 643                 return rc;
 644
 645         rc = bnxt_init_fc_ctx_mem(bp);
 646
 647         return rc;
 648 }
 649
 650 static int bnxt_update_phy_setting(struct bnxt *bp)
 651 {
 652         struct rte_eth_link new;
 653         int rc;
 654
 655         rc = bnxt_get_hwrm_link_config(bp, &new);
 656         if (rc) {
 657                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 658                 return rc;
 659         }
 660
 661         /*
 662          * On BCM957508-N2100 adapters, FW will not allow any user other
 663          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 664          * always returns link up. Force phy update always in that case.
 665          */
 666         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 667                 rc = bnxt_set_hwrm_link_config(bp, true);
 668                 if (rc) {
 669                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 670                         return rc;
 671                 }
 672         }
 673
 674         return rc;
 675 }
 676
 677 static int bnxt_init_chip(struct bnxt *bp)
 678 {
 679         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 680         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 681         uint32_t intr_vector = 0;
 682         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 683         uint32_t vec = BNXT_MISC_VEC_ID;
 684         unsigned int i, j;
 685         int rc;
 686
 687         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 688                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 689                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 690                 bp->flags |= BNXT_FLAG_JUMBO;
 691         } else {
 692                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 693                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 694                 bp->flags &= ~BNXT_FLAG_JUMBO;
 695         }
 696
 697         /* THOR does not support ring groups.
 698          * But we will use the array to save RSS context IDs.
 699          */
 700         if (BNXT_CHIP_THOR(bp))
 701                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 702
 703         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 704         if (rc) {
 705                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 706                 goto err_out;
 707         }
 708
 709         rc = bnxt_alloc_hwrm_rings(bp);
 710         if (rc) {
 711                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 712                 goto err_out;
 713         }
 714
 715         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 716         if (rc) {
 717                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 718                 goto err_out;
 719         }
 720
 721         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 722                 goto skip_cosq_cfg;
 723
 724         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 725                 if (bp->rx_cos_queue[i].id != 0xff) {
 726                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 727
 728                         if (!vnic) {
 729                                 PMD_DRV_LOG(ERR,
 730                                             "Num pools more than FW profile\n");
 731                                 rc = -EINVAL;
 732                                 goto err_out;
 733                         }
 734                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 735                         bp->rx_cosq_cnt++;
 736                 }
 737         }
 738
 739 skip_cosq_cfg:
 740         rc = bnxt_mq_rx_configure(bp);
 741         if (rc) {
 742                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 743                 goto err_out;
 744         }
 745
 746         /* VNIC configuration */
 747         for (i = 0; i < bp->nr_vnics; i++) {
 748                 rc = bnxt_setup_one_vnic(bp, i);
 749                 if (rc)
 750                         goto err_out;
 751         }
 752
 753         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 754         if (rc) {
 755                 PMD_DRV_LOG(ERR,
 756                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 757                 goto err_out;
 758         }
 759
 760         /* check and configure queue intr-vector mapping */
 761         if ((rte_intr_cap_multiple(intr_handle) ||
 762              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 763             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 764                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 765                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 766                 if (intr_vector > bp->rx_cp_nr_rings) {
 767                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 768                                         bp->rx_cp_nr_rings);
 769                         return -ENOTSUP;
 770                 }
 771                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 772                 if (rc)
 773                         return rc;
 774         }
 775
 776         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 777                 intr_handle->intr_vec =
 778                         rte_zmalloc("intr_vec",
 779                                     bp->eth_dev->data->nb_rx_queues *
 780                                     sizeof(int), 0);
 781                 if (intr_handle->intr_vec == NULL) {
 782                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 783                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 784                         rc = -ENOMEM;
 785                         goto err_disable;
 786                 }
 787                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 788                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 789                          intr_handle->intr_vec, intr_handle->nb_efd,
 790                         intr_handle->max_intr);
 791                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 792                      queue_id++) {
 793                         intr_handle->intr_vec[queue_id] =
 794                                                         vec + BNXT_RX_VEC_START;
 795                         if (vec < base + intr_handle->nb_efd - 1)
 796                                 vec++;
 797                 }
 798         }
 799
 800         /* enable uio/vfio intr/eventfd mapping */
 801         rc = rte_intr_enable(intr_handle);
 802 #ifndef RTE_EXEC_ENV_FREEBSD
 803         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 804         if (rc)
 805                 goto err_free;
 806 #endif
 807
 808         rc = bnxt_update_phy_setting(bp);
 809         if (rc)
 810                 goto err_free;
 811
 812         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 813         if (!bp->mark_table)
 814                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 815
 816         return 0;
 817
 818 err_free:
 819         rte_free(intr_handle->intr_vec);
 820 err_disable:
 821         rte_intr_efd_disable(intr_handle);
 822 err_out:
 823         /* Some of the error status returned by FW may not be from errno.h */
 824         if (rc > 0)
 825                 rc = -EIO;
 826
 827         return rc;
 828 }
 829
 830 static int bnxt_shutdown_nic(struct bnxt *bp)
 831 {
 832         bnxt_free_all_hwrm_resources(bp);
 833         bnxt_free_all_filters(bp);
 834         bnxt_free_all_vnics(bp);
 835         return 0;
 836 }
 837
 838 /*
 839  * Device configuration and status function
 840  */
 841
 842 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 843 {
 844         uint32_t link_speed = bp->link_info->support_speeds;
 845         uint32_t speed_capa = 0;
 846
 847         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 848                 speed_capa |= ETH_LINK_SPEED_100M;
 849         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 850                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 851         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 852                 speed_capa |= ETH_LINK_SPEED_1G;
 853         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 854                 speed_capa |= ETH_LINK_SPEED_2_5G;
 855         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 856                 speed_capa |= ETH_LINK_SPEED_10G;
 857         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 858                 speed_capa |= ETH_LINK_SPEED_20G;
 859         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 860                 speed_capa |= ETH_LINK_SPEED_25G;
 861         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 862                 speed_capa |= ETH_LINK_SPEED_40G;
 863         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 864                 speed_capa |= ETH_LINK_SPEED_50G;
 865         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 866                 speed_capa |= ETH_LINK_SPEED_100G;
 867         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 868                 speed_capa |= ETH_LINK_SPEED_50G;
 869         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 870                 speed_capa |= ETH_LINK_SPEED_100G;
 871         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 872                 speed_capa |= ETH_LINK_SPEED_200G;
 873
 874         if (bp->link_info->auto_mode ==
 875             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 876                 speed_capa |= ETH_LINK_SPEED_FIXED;
 877         else
 878                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 879
 880         return speed_capa;
 881 }
 882
 883 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 884                                 struct rte_eth_dev_info *dev_info)
 885 {
 886         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 887         struct bnxt *bp = eth_dev->data->dev_private;
 888         uint16_t max_vnics, i, j, vpool, vrxq;
 889         unsigned int max_rx_rings;
 890         int rc;
 891
 892         rc = is_bnxt_in_error(bp);
 893         if (rc)
 894                 return rc;
 895
 896         /* MAC Specifics */
 897         dev_info->max_mac_addrs = bp->max_l2_ctx;
 898         dev_info->max_hash_mac_addrs = 0;
 899
 900         /* PF/VF specifics */
 901         if (BNXT_PF(bp))
 902                 dev_info->max_vfs = pdev->max_vfs;
 903
 904         max_rx_rings = BNXT_MAX_RINGS(bp);
 905         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 906         dev_info->max_rx_queues = max_rx_rings;
 907         dev_info->max_tx_queues = max_rx_rings;
 908         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 909         dev_info->hash_key_size = 40;
 910         max_vnics = bp->max_vnics;
 911
 912         /* MTU specifics */
 913         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 914         dev_info->max_mtu = BNXT_MAX_MTU;
 915
 916         /* Fast path specifics */
 917         dev_info->min_rx_bufsize = 1;
 918         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 919
 920         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 921         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 922                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 923         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 924         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 925                                     dev_info->tx_queue_offload_capa;
 926         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 927
 928         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 929
 930         /* *INDENT-OFF* */
 931         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 932                 .rx_thresh = {
 933                         .pthresh = 8,
 934                         .hthresh = 8,
 935                         .wthresh = 0,
 936                 },
 937                 .rx_free_thresh = 32,
 938                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 939         };
 940
 941         dev_info->default_txconf = (struct rte_eth_txconf) {
 942                 .tx_thresh = {
 943                         .pthresh = 32,
 944                         .hthresh = 0,
 945                         .wthresh = 0,
 946                 },
 947                 .tx_free_thresh = 32,
 948                 .tx_rs_thresh = 32,
 949         };
 950         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 951
 952         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 953         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 954         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 955         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 956         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 957
 958         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 959                 dev_info->switch_info.name = eth_dev->device->name;
 960                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 961                 dev_info->switch_info.port_id =
 962                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 963                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 964         }
 965
 966         /* *INDENT-ON* */
 967
 968         /*
 969          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 970          *       need further investigation.
 971          */
 972
 973         /* VMDq resources */
 974         vpool = 64; /* ETH_64_POOLS */
 975         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 976         for (i = 0; i < 4; vpool >>= 1, i++) {
 977                 if (max_vnics > vpool) {
 978                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 979                                 if (dev_info->max_rx_queues > vrxq) {
 980                                         if (vpool > vrxq)
 981                                                 vpool = vrxq;
 982                                         goto found;
 983                                 }
 984                         }
 985                         /* Not enough resources to support VMDq */
 986                         break;
 987                 }
 988         }
 989         /* Not enough resources to support VMDq */
 990         vpool = 0;
 991         vrxq = 0;
 992 found:
 993         dev_info->max_vmdq_pools = vpool;
 994         dev_info->vmdq_queue_num = vrxq;
 995
 996         dev_info->vmdq_pool_base = 0;
 997         dev_info->vmdq_queue_base = 0;
 998
 999         return 0;
1000 }
1001
1002 /* Configure the device based on the configuration provided */
1003 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1004 {
1005         struct bnxt *bp = eth_dev->data->dev_private;
1006         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1007         int rc;
1008
1009         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1010         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1011         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1012         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1013
1014         rc = is_bnxt_in_error(bp);
1015         if (rc)
1016                 return rc;
1017
1018         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1019                 rc = bnxt_hwrm_check_vf_rings(bp);
1020                 if (rc) {
1021                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1022                         return -ENOSPC;
1023                 }
1024
1025                 /* If a resource has already been allocated - in this case
1026                  * it is the async completion ring, free it. Reallocate it after
1027                  * resource reservation. This will ensure the resource counts
1028                  * are calculated correctly.
1029                  */
1030
1031                 pthread_mutex_lock(&bp->def_cp_lock);
1032
1033                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1034                         bnxt_disable_int(bp);
1035                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1036                 }
1037
1038                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1039                 if (rc) {
1040                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1041                         pthread_mutex_unlock(&bp->def_cp_lock);
1042                         return -ENOSPC;
1043                 }
1044
1045                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1046                         rc = bnxt_alloc_async_cp_ring(bp);
1047                         if (rc) {
1048                                 pthread_mutex_unlock(&bp->def_cp_lock);
1049                                 return rc;
1050                         }
1051                         bnxt_enable_int(bp);
1052                 }
1053
1054                 pthread_mutex_unlock(&bp->def_cp_lock);
1055         } else {
1056                 /* legacy driver needs to get updated values */
1057                 rc = bnxt_hwrm_func_qcaps(bp);
1058                 if (rc) {
1059                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1060                         return rc;
1061                 }
1062         }
1063
1064         /* Inherit new configurations */
1065         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1066             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1067             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1068                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1069             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1070             bp->max_stat_ctx)
1071                 goto resource_error;
1072
1073         if (BNXT_HAS_RING_GRPS(bp) &&
1074             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1075                 goto resource_error;
1076
1077         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1078             bp->max_vnics < eth_dev->data->nb_rx_queues)
1079                 goto resource_error;
1080
1081         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1082         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1083
1084         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1085                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1086         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1087
1088         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1089                 eth_dev->data->mtu =
1090                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1091                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1092                         BNXT_NUM_VLANS;
1093                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1094         }
1095         return 0;
1096
1097 resource_error:
1098         PMD_DRV_LOG(ERR,
1099                     "Insufficient resources to support requested config\n");
1100         PMD_DRV_LOG(ERR,
1101                     "Num Queues Requested: Tx %d, Rx %d\n",
1102                     eth_dev->data->nb_tx_queues,
1103                     eth_dev->data->nb_rx_queues);
1104         PMD_DRV_LOG(ERR,
1105                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1106                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1107                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1108         return -ENOSPC;
1109 }
1110
1111 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1112 {
1113         struct rte_eth_link *link = &eth_dev->data->dev_link;
1114
1115         if (link->link_status)
1116                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1117                         eth_dev->data->port_id,
1118                         (uint32_t)link->link_speed,
1119                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1120                         ("full-duplex") : ("half-duplex\n"));
1121         else
1122                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1123                         eth_dev->data->port_id);
1124 }
1125
1126 /*
1127  * Determine whether the current configuration requires support for scattered
1128  * receive; return 1 if scattered receive is required and 0 if not.
1129  */
1130 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1131 {
1132         uint16_t buf_size;
1133         int i;
1134
1135         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1136                 return 1;
1137
1138         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1139                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1140
1141                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1142                                       RTE_PKTMBUF_HEADROOM);
1143                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1144                         return 1;
1145         }
1146         return 0;
1147 }
1148
1149 static eth_rx_burst_t
1150 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1151 {
1152         struct bnxt *bp = eth_dev->data->dev_private;
1153
1154 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1155 #ifndef RTE_LIBRTE_IEEE1588
1156         /*
1157          * Vector mode receive can be enabled only if scatter rx is not
1158          * in use and rx offloads are limited to VLAN stripping and
1159          * CRC stripping.
1160          */
1161         if (!eth_dev->data->scattered_rx &&
1162             !(eth_dev->data->dev_conf.rxmode.offloads &
1163               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1164                 DEV_RX_OFFLOAD_KEEP_CRC |
1165                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1166                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1167                 DEV_RX_OFFLOAD_UDP_CKSUM |
1168                 DEV_RX_OFFLOAD_TCP_CKSUM |
1169                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1170                 DEV_RX_OFFLOAD_RSS_HASH |
1171                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1172             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) {
1173                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1174                             eth_dev->data->port_id);
1175                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1176                 return bnxt_recv_pkts_vec;
1177         }
1178         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1179                     eth_dev->data->port_id);
1180         PMD_DRV_LOG(INFO,
1181                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1182                     eth_dev->data->port_id,
1183                     eth_dev->data->scattered_rx,
1184                     eth_dev->data->dev_conf.rxmode.offloads);
1185 #endif
1186 #endif
1187         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1188         return bnxt_recv_pkts;
1189 }
1190
1191 static eth_tx_burst_t
1192 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1193 {
1194 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1195 #ifndef RTE_LIBRTE_IEEE1588
1196         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1197         struct bnxt *bp = eth_dev->data->dev_private;
1198
1199         /*
1200          * Vector mode transmit can be enabled only if not using scatter rx
1201          * or tx offloads.
1202          */
1203         if (!eth_dev->data->scattered_rx &&
1204             !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1205             !BNXT_TRUFLOW_EN(bp)) {
1206                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1207                             eth_dev->data->port_id);
1208                 return bnxt_xmit_pkts_vec;
1209         }
1210         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1211                     eth_dev->data->port_id);
1212         PMD_DRV_LOG(INFO,
1213                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1214                     eth_dev->data->port_id,
1215                     eth_dev->data->scattered_rx,
1216                     offloads);
1217 #endif
1218 #endif
1219         return bnxt_xmit_pkts;
1220 }
1221
1222 static int bnxt_handle_if_change_status(struct bnxt *bp)
1223 {
1224         int rc;
1225
1226         /* Since fw has undergone a reset and lost all contexts,
1227          * set fatal flag to not issue hwrm during cleanup
1228          */
1229         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1230         bnxt_uninit_resources(bp, true);
1231
1232         /* clear fatal flag so that re-init happens */
1233         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1234         rc = bnxt_init_resources(bp, true);
1235
1236         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1237
1238         return rc;
1239 }
1240
1241 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1242 {
1243         struct bnxt *bp = eth_dev->data->dev_private;
1244         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1245         int vlan_mask = 0;
1246         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1247
1248         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1249                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1250                 return -EINVAL;
1251         }
1252
1253         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1254                 PMD_DRV_LOG(ERR,
1255                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1256                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1257         }
1258
1259         do {
1260                 rc = bnxt_hwrm_if_change(bp, true);
1261                 if (rc == 0 || rc != -EAGAIN)
1262                         break;
1263
1264                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1265         } while (retry_cnt--);
1266
1267         if (rc)
1268                 return rc;
1269
1270         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1271                 rc = bnxt_handle_if_change_status(bp);
1272                 if (rc)
1273                         return rc;
1274         }
1275
1276         bnxt_enable_int(bp);
1277
1278         rc = bnxt_init_chip(bp);
1279         if (rc)
1280                 goto error;
1281
1282         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1283         eth_dev->data->dev_started = 1;
1284
1285         bnxt_link_update_op(eth_dev, 1);
1286
1287         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1288                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1289         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1290                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1291         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1292         if (rc)
1293                 goto error;
1294
1295         /* Initialize bnxt ULP port details */
1296         rc = bnxt_ulp_port_init(bp);
1297         if (rc)
1298                 goto error;
1299
1300         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1301         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1302
1303         bnxt_schedule_fw_health_check(bp);
1304
1305         return 0;
1306
1307 error:
1308         bnxt_shutdown_nic(bp);
1309         bnxt_free_tx_mbufs(bp);
1310         bnxt_free_rx_mbufs(bp);
1311         bnxt_hwrm_if_change(bp, false);
1312         eth_dev->data->dev_started = 0;
1313         return rc;
1314 }
1315
1316 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1317 {
1318         struct bnxt *bp = eth_dev->data->dev_private;
1319         int rc = 0;
1320
1321         if (!bp->link_info->link_up)
1322                 rc = bnxt_set_hwrm_link_config(bp, true);
1323         if (!rc)
1324                 eth_dev->data->dev_link.link_status = 1;
1325
1326         bnxt_print_link_info(eth_dev);
1327         return rc;
1328 }
1329
1330 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1331 {
1332         struct bnxt *bp = eth_dev->data->dev_private;
1333
1334         eth_dev->data->dev_link.link_status = 0;
1335         bnxt_set_hwrm_link_config(bp, false);
1336         bp->link_info->link_up = 0;
1337
1338         return 0;
1339 }
1340
1341 static void bnxt_free_switch_domain(struct bnxt *bp)
1342 {
1343         if (bp->switch_domain_id)
1344                 rte_eth_switch_domain_free(bp->switch_domain_id);
1345 }
1346
1347 /* Unload the driver, release resources */
1348 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1349 {
1350         struct bnxt *bp = eth_dev->data->dev_private;
1351         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1352         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1353         struct rte_eth_link link;
1354         int ret;
1355
1356         eth_dev->data->dev_started = 0;
1357         eth_dev->data->scattered_rx = 0;
1358
1359         /* Prevent crashes when queues are still in use */
1360         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1361         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1362
1363         bnxt_disable_int(bp);
1364
1365         /* disable uio/vfio intr/eventfd mapping */
1366         rte_intr_disable(intr_handle);
1367
1368         /* Stop the child representors for this device */
1369         ret = bnxt_rep_stop_all(bp);
1370         if (ret != 0)
1371                 return ret;
1372
1373         /* delete the bnxt ULP port details */
1374         bnxt_ulp_port_deinit(bp);
1375
1376         bnxt_cancel_fw_health_check(bp);
1377
1378         /* Do not bring link down during reset recovery */
1379         if (!is_bnxt_in_error(bp)) {
1380                 bnxt_dev_set_link_down_op(eth_dev);
1381                 /* Wait for link to be reset */
1382                 if (BNXT_SINGLE_PF(bp))
1383                         rte_delay_ms(500);
1384                 /* clear the recorded link status */
1385                 memset(&link, 0, sizeof(link));
1386                 rte_eth_linkstatus_set(eth_dev, &link);
1387         }
1388
1389         /* Clean queue intr-vector mapping */
1390         rte_intr_efd_disable(intr_handle);
1391         if (intr_handle->intr_vec != NULL) {
1392                 rte_free(intr_handle->intr_vec);
1393                 intr_handle->intr_vec = NULL;
1394         }
1395
1396         bnxt_hwrm_port_clr_stats(bp);
1397         bnxt_free_tx_mbufs(bp);
1398         bnxt_free_rx_mbufs(bp);
1399         /* Process any remaining notifications in default completion queue */
1400         bnxt_int_handler(eth_dev);
1401         bnxt_shutdown_nic(bp);
1402         bnxt_hwrm_if_change(bp, false);
1403
1404         rte_free(bp->mark_table);
1405         bp->mark_table = NULL;
1406
1407         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1408         bp->rx_cosq_cnt = 0;
1409         /* All filters are deleted on a port stop. */
1410         if (BNXT_FLOW_XSTATS_EN(bp))
1411                 bp->flow_stat->flow_count = 0;
1412
1413         return 0;
1414 }
1415
1416 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1417 {
1418         struct bnxt *bp = eth_dev->data->dev_private;
1419         int ret = 0;
1420
1421         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1422                 return 0;
1423
1424         /* cancel the recovery handler before remove dev */
1425         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1426         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1427         bnxt_cancel_fc_thread(bp);
1428
1429         if (eth_dev->data->dev_started)
1430                 ret = bnxt_dev_stop_op(eth_dev);
1431
1432         bnxt_free_switch_domain(bp);
1433
1434         bnxt_uninit_resources(bp, false);
1435
1436         bnxt_free_leds_info(bp);
1437         bnxt_free_cos_queues(bp);
1438         bnxt_free_link_info(bp);
1439         bnxt_free_pf_info(bp);
1440         bnxt_free_parent_info(bp);
1441
1442         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1443         bp->tx_mem_zone = NULL;
1444         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1445         bp->rx_mem_zone = NULL;
1446
1447         bnxt_hwrm_free_vf_info(bp);
1448
1449         rte_free(bp->grp_info);
1450         bp->grp_info = NULL;
1451
1452         return ret;
1453 }
1454
1455 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1456                                     uint32_t index)
1457 {
1458         struct bnxt *bp = eth_dev->data->dev_private;
1459         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1460         struct bnxt_vnic_info *vnic;
1461         struct bnxt_filter_info *filter, *temp_filter;
1462         uint32_t i;
1463
1464         if (is_bnxt_in_error(bp))
1465                 return;
1466
1467         /*
1468          * Loop through all VNICs from the specified filter flow pools to
1469          * remove the corresponding MAC addr filter
1470          */
1471         for (i = 0; i < bp->nr_vnics; i++) {
1472                 if (!(pool_mask & (1ULL << i)))
1473                         continue;
1474
1475                 vnic = &bp->vnic_info[i];
1476                 filter = STAILQ_FIRST(&vnic->filter);
1477                 while (filter) {
1478                         temp_filter = STAILQ_NEXT(filter, next);
1479                         if (filter->mac_index == index) {
1480                                 STAILQ_REMOVE(&vnic->filter, filter,
1481                                                 bnxt_filter_info, next);
1482                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1483                                 bnxt_free_filter(bp, filter);
1484                         }
1485                         filter = temp_filter;
1486                 }
1487         }
1488 }
1489
1490 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1491                                struct rte_ether_addr *mac_addr, uint32_t index,
1492                                uint32_t pool)
1493 {
1494         struct bnxt_filter_info *filter;
1495         int rc = 0;
1496
1497         /* Attach requested MAC address to the new l2_filter */
1498         STAILQ_FOREACH(filter, &vnic->filter, next) {
1499                 if (filter->mac_index == index) {
1500                         PMD_DRV_LOG(DEBUG,
1501                                     "MAC addr already existed for pool %d\n",
1502                                     pool);
1503                         return 0;
1504                 }
1505         }
1506
1507         filter = bnxt_alloc_filter(bp);
1508         if (!filter) {
1509                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1510                 return -ENODEV;
1511         }
1512
1513         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1514          * if the MAC that's been programmed now is a different one, then,
1515          * copy that addr to filter->l2_addr
1516          */
1517         if (mac_addr)
1518                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1519         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1520
1521         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1522         if (!rc) {
1523                 filter->mac_index = index;
1524                 if (filter->mac_index == 0)
1525                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1526                 else
1527                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1528         } else {
1529                 bnxt_free_filter(bp, filter);
1530         }
1531
1532         return rc;
1533 }
1534
1535 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1536                                 struct rte_ether_addr *mac_addr,
1537                                 uint32_t index, uint32_t pool)
1538 {
1539         struct bnxt *bp = eth_dev->data->dev_private;
1540         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1541         int rc = 0;
1542
1543         rc = is_bnxt_in_error(bp);
1544         if (rc)
1545                 return rc;
1546
1547         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1548                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1549                 return -ENOTSUP;
1550         }
1551
1552         if (!vnic) {
1553                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1554                 return -EINVAL;
1555         }
1556
1557         /* Filter settings will get applied when port is started */
1558         if (!eth_dev->data->dev_started)
1559                 return 0;
1560
1561         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1562
1563         return rc;
1564 }
1565
1566 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1567 {
1568         int rc = 0;
1569         struct bnxt *bp = eth_dev->data->dev_private;
1570         struct rte_eth_link new;
1571         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1572                         BNXT_MIN_LINK_WAIT_CNT;
1573
1574         rc = is_bnxt_in_error(bp);
1575         if (rc)
1576                 return rc;
1577
1578         memset(&new, 0, sizeof(new));
1579         do {
1580                 /* Retrieve link info from hardware */
1581                 rc = bnxt_get_hwrm_link_config(bp, &new);
1582                 if (rc) {
1583                         new.link_speed = ETH_LINK_SPEED_100M;
1584                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1585                         PMD_DRV_LOG(ERR,
1586                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1587                         goto out;
1588                 }
1589
1590                 if (!wait_to_complete || new.link_status)
1591                         break;
1592
1593                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1594         } while (cnt--);
1595
1596         /* Only single function PF can bring phy down.
1597          * When port is stopped, report link down for VF/MH/NPAR functions.
1598          */
1599         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1600                 memset(&new, 0, sizeof(new));
1601
1602 out:
1603         /* Timed out or success */
1604         if (new.link_status != eth_dev->data->dev_link.link_status ||
1605         new.link_speed != eth_dev->data->dev_link.link_speed) {
1606                 rte_eth_linkstatus_set(eth_dev, &new);
1607
1608                 rte_eth_dev_callback_process(eth_dev,
1609                                              RTE_ETH_EVENT_INTR_LSC,
1610                                              NULL);
1611
1612                 bnxt_print_link_info(eth_dev);
1613         }
1614
1615         return rc;
1616 }
1617
1618 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1619 {
1620         struct bnxt *bp = eth_dev->data->dev_private;
1621         struct bnxt_vnic_info *vnic;
1622         uint32_t old_flags;
1623         int rc;
1624
1625         rc = is_bnxt_in_error(bp);
1626         if (rc)
1627                 return rc;
1628
1629         /* Filter settings will get applied when port is started */
1630         if (!eth_dev->data->dev_started)
1631                 return 0;
1632
1633         if (bp->vnic_info == NULL)
1634                 return 0;
1635
1636         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1637
1638         old_flags = vnic->flags;
1639         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1640         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1641         if (rc != 0)
1642                 vnic->flags = old_flags;
1643
1644         return rc;
1645 }
1646
1647 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1648 {
1649         struct bnxt *bp = eth_dev->data->dev_private;
1650         struct bnxt_vnic_info *vnic;
1651         uint32_t old_flags;
1652         int rc;
1653
1654         rc = is_bnxt_in_error(bp);
1655         if (rc)
1656                 return rc;
1657
1658         /* Filter settings will get applied when port is started */
1659         if (!eth_dev->data->dev_started)
1660                 return 0;
1661
1662         if (bp->vnic_info == NULL)
1663                 return 0;
1664
1665         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1666
1667         old_flags = vnic->flags;
1668         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1669         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1670         if (rc != 0)
1671                 vnic->flags = old_flags;
1672
1673         return rc;
1674 }
1675
1676 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1677 {
1678         struct bnxt *bp = eth_dev->data->dev_private;
1679         struct bnxt_vnic_info *vnic;
1680         uint32_t old_flags;
1681         int rc;
1682
1683         rc = is_bnxt_in_error(bp);
1684         if (rc)
1685                 return rc;
1686
1687         /* Filter settings will get applied when port is started */
1688         if (!eth_dev->data->dev_started)
1689                 return 0;
1690
1691         if (bp->vnic_info == NULL)
1692                 return 0;
1693
1694         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1695
1696         old_flags = vnic->flags;
1697         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1698         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1699         if (rc != 0)
1700                 vnic->flags = old_flags;
1701
1702         return rc;
1703 }
1704
1705 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1706 {
1707         struct bnxt *bp = eth_dev->data->dev_private;
1708         struct bnxt_vnic_info *vnic;
1709         uint32_t old_flags;
1710         int rc;
1711
1712         rc = is_bnxt_in_error(bp);
1713         if (rc)
1714                 return rc;
1715
1716         /* Filter settings will get applied when port is started */
1717         if (!eth_dev->data->dev_started)
1718                 return 0;
1719
1720         if (bp->vnic_info == NULL)
1721                 return 0;
1722
1723         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1724
1725         old_flags = vnic->flags;
1726         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1727         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1728         if (rc != 0)
1729                 vnic->flags = old_flags;
1730
1731         return rc;
1732 }
1733
1734 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1735 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1736 {
1737         if (qid >= bp->rx_nr_rings)
1738                 return NULL;
1739
1740         return bp->eth_dev->data->rx_queues[qid];
1741 }
1742
1743 /* Return rxq corresponding to a given rss table ring/group ID. */
1744 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1745 {
1746         struct bnxt_rx_queue *rxq;
1747         unsigned int i;
1748
1749         if (!BNXT_HAS_RING_GRPS(bp)) {
1750                 for (i = 0; i < bp->rx_nr_rings; i++) {
1751                         rxq = bp->eth_dev->data->rx_queues[i];
1752                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1753                                 return rxq->index;
1754                 }
1755         } else {
1756                 for (i = 0; i < bp->rx_nr_rings; i++) {
1757                         if (bp->grp_info[i].fw_grp_id == fwr)
1758                                 return i;
1759                 }
1760         }
1761
1762         return INVALID_HW_RING_ID;
1763 }
1764
1765 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1766                             struct rte_eth_rss_reta_entry64 *reta_conf,
1767                             uint16_t reta_size)
1768 {
1769         struct bnxt *bp = eth_dev->data->dev_private;
1770         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1771         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1772         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1773         uint16_t idx, sft;
1774         int i, rc;
1775
1776         rc = is_bnxt_in_error(bp);
1777         if (rc)
1778                 return rc;
1779
1780         if (!vnic->rss_table)
1781                 return -EINVAL;
1782
1783         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1784                 return -EINVAL;
1785
1786         if (reta_size != tbl_size) {
1787                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1788                         "(%d) must equal the size supported by the hardware "
1789                         "(%d)\n", reta_size, tbl_size);
1790                 return -EINVAL;
1791         }
1792
1793         for (i = 0; i < reta_size; i++) {
1794                 struct bnxt_rx_queue *rxq;
1795
1796                 idx = i / RTE_RETA_GROUP_SIZE;
1797                 sft = i % RTE_RETA_GROUP_SIZE;
1798
1799                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1800                         continue;
1801
1802                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1803                 if (!rxq) {
1804                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1805                         return -EINVAL;
1806                 }
1807
1808                 if (BNXT_CHIP_THOR(bp)) {
1809                         vnic->rss_table[i * 2] =
1810                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1811                         vnic->rss_table[i * 2 + 1] =
1812                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1813                 } else {
1814                         vnic->rss_table[i] =
1815                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1816                 }
1817         }
1818
1819         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1820         return 0;
1821 }
1822
1823 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1824                               struct rte_eth_rss_reta_entry64 *reta_conf,
1825                               uint16_t reta_size)
1826 {
1827         struct bnxt *bp = eth_dev->data->dev_private;
1828         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1829         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1830         uint16_t idx, sft, i;
1831         int rc;
1832
1833         rc = is_bnxt_in_error(bp);
1834         if (rc)
1835                 return rc;
1836
1837         /* Retrieve from the default VNIC */
1838         if (!vnic)
1839                 return -EINVAL;
1840         if (!vnic->rss_table)
1841                 return -EINVAL;
1842
1843         if (reta_size != tbl_size) {
1844                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1845                         "(%d) must equal the size supported by the hardware "
1846                         "(%d)\n", reta_size, tbl_size);
1847                 return -EINVAL;
1848         }
1849
1850         for (idx = 0, i = 0; i < reta_size; i++) {
1851                 idx = i / RTE_RETA_GROUP_SIZE;
1852                 sft = i % RTE_RETA_GROUP_SIZE;
1853
1854                 if (reta_conf[idx].mask & (1ULL << sft)) {
1855                         uint16_t qid;
1856
1857                         if (BNXT_CHIP_THOR(bp))
1858                                 qid = bnxt_rss_to_qid(bp,
1859                                                       vnic->rss_table[i * 2]);
1860                         else
1861                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1862
1863                         if (qid == INVALID_HW_RING_ID) {
1864                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1865                                 return -EINVAL;
1866                         }
1867                         reta_conf[idx].reta[sft] = qid;
1868                 }
1869         }
1870
1871         return 0;
1872 }
1873
1874 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1875                                    struct rte_eth_rss_conf *rss_conf)
1876 {
1877         struct bnxt *bp = eth_dev->data->dev_private;
1878         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1879         struct bnxt_vnic_info *vnic;
1880         int rc;
1881
1882         rc = is_bnxt_in_error(bp);
1883         if (rc)
1884                 return rc;
1885
1886         /*
1887          * If RSS enablement were different than dev_configure,
1888          * then return -EINVAL
1889          */
1890         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1891                 if (!rss_conf->rss_hf)
1892                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1893         } else {
1894                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1895                         return -EINVAL;
1896         }
1897
1898         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1899         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1900                rss_conf,
1901                sizeof(*rss_conf));
1902
1903         /* Update the default RSS VNIC(s) */
1904         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1905         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1906         vnic->hash_mode =
1907                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1908                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
1909
1910         /*
1911          * If hashkey is not specified, use the previously configured
1912          * hashkey
1913          */
1914         if (!rss_conf->rss_key)
1915                 goto rss_config;
1916
1917         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1918                 PMD_DRV_LOG(ERR,
1919                             "Invalid hashkey length, should be 16 bytes\n");
1920                 return -EINVAL;
1921         }
1922         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1923
1924 rss_config:
1925         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1926         return 0;
1927 }
1928
1929 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1930                                      struct rte_eth_rss_conf *rss_conf)
1931 {
1932         struct bnxt *bp = eth_dev->data->dev_private;
1933         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1934         int len, rc;
1935         uint32_t hash_types;
1936
1937         rc = is_bnxt_in_error(bp);
1938         if (rc)
1939                 return rc;
1940
1941         /* RSS configuration is the same for all VNICs */
1942         if (vnic && vnic->rss_hash_key) {
1943                 if (rss_conf->rss_key) {
1944                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1945                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1946                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1947                 }
1948
1949                 hash_types = vnic->hash_type;
1950                 rss_conf->rss_hf = 0;
1951                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1952                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1953                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1954                 }
1955                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1956                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1957                         hash_types &=
1958                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1959                 }
1960                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1961                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1962                         hash_types &=
1963                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1964                 }
1965                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1966                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1967                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1968                 }
1969                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1970                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1971                         hash_types &=
1972                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1973                 }
1974                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1975                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1976                         hash_types &=
1977                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1978                 }
1979
1980                 rss_conf->rss_hf |=
1981                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
1982
1983                 if (hash_types) {
1984                         PMD_DRV_LOG(ERR,
1985                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1986                                 vnic->hash_type);
1987                         return -ENOTSUP;
1988                 }
1989         } else {
1990                 rss_conf->rss_hf = 0;
1991         }
1992         return 0;
1993 }
1994
1995 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1996                                struct rte_eth_fc_conf *fc_conf)
1997 {
1998         struct bnxt *bp = dev->data->dev_private;
1999         struct rte_eth_link link_info;
2000         int rc;
2001
2002         rc = is_bnxt_in_error(bp);
2003         if (rc)
2004                 return rc;
2005
2006         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2007         if (rc)
2008                 return rc;
2009
2010         memset(fc_conf, 0, sizeof(*fc_conf));
2011         if (bp->link_info->auto_pause)
2012                 fc_conf->autoneg = 1;
2013         switch (bp->link_info->pause) {
2014         case 0:
2015                 fc_conf->mode = RTE_FC_NONE;
2016                 break;
2017         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2018                 fc_conf->mode = RTE_FC_TX_PAUSE;
2019                 break;
2020         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2021                 fc_conf->mode = RTE_FC_RX_PAUSE;
2022                 break;
2023         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2024                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2025                 fc_conf->mode = RTE_FC_FULL;
2026                 break;
2027         }
2028         return 0;
2029 }
2030
2031 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2032                                struct rte_eth_fc_conf *fc_conf)
2033 {
2034         struct bnxt *bp = dev->data->dev_private;
2035         int rc;
2036
2037         rc = is_bnxt_in_error(bp);
2038         if (rc)
2039                 return rc;
2040
2041         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2042                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2043                 return -ENOTSUP;
2044         }
2045
2046         switch (fc_conf->mode) {
2047         case RTE_FC_NONE:
2048                 bp->link_info->auto_pause = 0;
2049                 bp->link_info->force_pause = 0;
2050                 break;
2051         case RTE_FC_RX_PAUSE:
2052                 if (fc_conf->autoneg) {
2053                         bp->link_info->auto_pause =
2054                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2055                         bp->link_info->force_pause = 0;
2056                 } else {
2057                         bp->link_info->auto_pause = 0;
2058                         bp->link_info->force_pause =
2059                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2060                 }
2061                 break;
2062         case RTE_FC_TX_PAUSE:
2063                 if (fc_conf->autoneg) {
2064                         bp->link_info->auto_pause =
2065                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2066                         bp->link_info->force_pause = 0;
2067                 } else {
2068                         bp->link_info->auto_pause = 0;
2069                         bp->link_info->force_pause =
2070                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2071                 }
2072                 break;
2073         case RTE_FC_FULL:
2074                 if (fc_conf->autoneg) {
2075                         bp->link_info->auto_pause =
2076                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2077                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2078                         bp->link_info->force_pause = 0;
2079                 } else {
2080                         bp->link_info->auto_pause = 0;
2081                         bp->link_info->force_pause =
2082                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2083                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2084                 }
2085                 break;
2086         }
2087         return bnxt_set_hwrm_link_config(bp, true);
2088 }
2089
2090 /* Add UDP tunneling port */
2091 static int
2092 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2093                          struct rte_eth_udp_tunnel *udp_tunnel)
2094 {
2095         struct bnxt *bp = eth_dev->data->dev_private;
2096         uint16_t tunnel_type = 0;
2097         int rc = 0;
2098
2099         rc = is_bnxt_in_error(bp);
2100         if (rc)
2101                 return rc;
2102
2103         switch (udp_tunnel->prot_type) {
2104         case RTE_TUNNEL_TYPE_VXLAN:
2105                 if (bp->vxlan_port_cnt) {
2106                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2107                                 udp_tunnel->udp_port);
2108                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2109                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2110                                 return -ENOSPC;
2111                         }
2112                         bp->vxlan_port_cnt++;
2113                         return 0;
2114                 }
2115                 tunnel_type =
2116                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2117                 bp->vxlan_port_cnt++;
2118                 break;
2119         case RTE_TUNNEL_TYPE_GENEVE:
2120                 if (bp->geneve_port_cnt) {
2121                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2122                                 udp_tunnel->udp_port);
2123                         if (bp->geneve_port != udp_tunnel->udp_port) {
2124                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2125                                 return -ENOSPC;
2126                         }
2127                         bp->geneve_port_cnt++;
2128                         return 0;
2129                 }
2130                 tunnel_type =
2131                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2132                 bp->geneve_port_cnt++;
2133                 break;
2134         default:
2135                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2136                 return -ENOTSUP;
2137         }
2138         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2139                                              tunnel_type);
2140         return rc;
2141 }
2142
2143 static int
2144 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2145                          struct rte_eth_udp_tunnel *udp_tunnel)
2146 {
2147         struct bnxt *bp = eth_dev->data->dev_private;
2148         uint16_t tunnel_type = 0;
2149         uint16_t port = 0;
2150         int rc = 0;
2151
2152         rc = is_bnxt_in_error(bp);
2153         if (rc)
2154                 return rc;
2155
2156         switch (udp_tunnel->prot_type) {
2157         case RTE_TUNNEL_TYPE_VXLAN:
2158                 if (!bp->vxlan_port_cnt) {
2159                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2160                         return -EINVAL;
2161                 }
2162                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2163                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2164                                 udp_tunnel->udp_port, bp->vxlan_port);
2165                         return -EINVAL;
2166                 }
2167                 if (--bp->vxlan_port_cnt)
2168                         return 0;
2169
2170                 tunnel_type =
2171                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2172                 port = bp->vxlan_fw_dst_port_id;
2173                 break;
2174         case RTE_TUNNEL_TYPE_GENEVE:
2175                 if (!bp->geneve_port_cnt) {
2176                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2177                         return -EINVAL;
2178                 }
2179                 if (bp->geneve_port != udp_tunnel->udp_port) {
2180                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2181                                 udp_tunnel->udp_port, bp->geneve_port);
2182                         return -EINVAL;
2183                 }
2184                 if (--bp->geneve_port_cnt)
2185                         return 0;
2186
2187                 tunnel_type =
2188                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2189                 port = bp->geneve_fw_dst_port_id;
2190                 break;
2191         default:
2192                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2193                 return -ENOTSUP;
2194         }
2195
2196         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2197         return rc;
2198 }
2199
2200 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2201 {
2202         struct bnxt_filter_info *filter;
2203         struct bnxt_vnic_info *vnic;
2204         int rc = 0;
2205         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2206
2207         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2208         filter = STAILQ_FIRST(&vnic->filter);
2209         while (filter) {
2210                 /* Search for this matching MAC+VLAN filter */
2211                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2212                         /* Delete the filter */
2213                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2214                         if (rc)
2215                                 return rc;
2216                         STAILQ_REMOVE(&vnic->filter, filter,
2217                                       bnxt_filter_info, next);
2218                         bnxt_free_filter(bp, filter);
2219                         PMD_DRV_LOG(INFO,
2220                                     "Deleted vlan filter for %d\n",
2221                                     vlan_id);
2222                         return 0;
2223                 }
2224                 filter = STAILQ_NEXT(filter, next);
2225         }
2226         return -ENOENT;
2227 }
2228
2229 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2230 {
2231         struct bnxt_filter_info *filter;
2232         struct bnxt_vnic_info *vnic;
2233         int rc = 0;
2234         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2235                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2236         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2237
2238         /* Implementation notes on the use of VNIC in this command:
2239          *
2240          * By default, these filters belong to default vnic for the function.
2241          * Once these filters are set up, only destination VNIC can be modified.
2242          * If the destination VNIC is not specified in this command,
2243          * then the HWRM shall only create an l2 context id.
2244          */
2245
2246         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2247         filter = STAILQ_FIRST(&vnic->filter);
2248         /* Check if the VLAN has already been added */
2249         while (filter) {
2250                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2251                         return -EEXIST;
2252
2253                 filter = STAILQ_NEXT(filter, next);
2254         }
2255
2256         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2257          * command to create MAC+VLAN filter with the right flags, enables set.
2258          */
2259         filter = bnxt_alloc_filter(bp);
2260         if (!filter) {
2261                 PMD_DRV_LOG(ERR,
2262                             "MAC/VLAN filter alloc failed\n");
2263                 return -ENOMEM;
2264         }
2265         /* MAC + VLAN ID filter */
2266         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2267          * untagged packets are received
2268          *
2269          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2270          * packets and only the programmed vlan's packets are received
2271          */
2272         filter->l2_ivlan = vlan_id;
2273         filter->l2_ivlan_mask = 0x0FFF;
2274         filter->enables |= en;
2275         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2276
2277         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2278         if (rc) {
2279                 /* Free the newly allocated filter as we were
2280                  * not able to create the filter in hardware.
2281                  */
2282                 bnxt_free_filter(bp, filter);
2283                 return rc;
2284         }
2285
2286         filter->mac_index = 0;
2287         /* Add this new filter to the list */
2288         if (vlan_id == 0)
2289                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2290         else
2291                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2292
2293         PMD_DRV_LOG(INFO,
2294                     "Added Vlan filter for %d\n", vlan_id);
2295         return rc;
2296 }
2297
2298 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2299                 uint16_t vlan_id, int on)
2300 {
2301         struct bnxt *bp = eth_dev->data->dev_private;
2302         int rc;
2303
2304         rc = is_bnxt_in_error(bp);
2305         if (rc)
2306                 return rc;
2307
2308         if (!eth_dev->data->dev_started) {
2309                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2310                 return -EINVAL;
2311         }
2312
2313         /* These operations apply to ALL existing MAC/VLAN filters */
2314         if (on)
2315                 return bnxt_add_vlan_filter(bp, vlan_id);
2316         else
2317                 return bnxt_del_vlan_filter(bp, vlan_id);
2318 }
2319
2320 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2321                                     struct bnxt_vnic_info *vnic)
2322 {
2323         struct bnxt_filter_info *filter;
2324         int rc;
2325
2326         filter = STAILQ_FIRST(&vnic->filter);
2327         while (filter) {
2328                 if (filter->mac_index == 0 &&
2329                     !memcmp(filter->l2_addr, bp->mac_addr,
2330                             RTE_ETHER_ADDR_LEN)) {
2331                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2332                         if (!rc) {
2333                                 STAILQ_REMOVE(&vnic->filter, filter,
2334                                               bnxt_filter_info, next);
2335                                 bnxt_free_filter(bp, filter);
2336                         }
2337                         return rc;
2338                 }
2339                 filter = STAILQ_NEXT(filter, next);
2340         }
2341         return 0;
2342 }
2343
2344 static int
2345 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2346 {
2347         struct bnxt_vnic_info *vnic;
2348         unsigned int i;
2349         int rc;
2350
2351         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2352         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2353                 /* Remove any VLAN filters programmed */
2354                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2355                         bnxt_del_vlan_filter(bp, i);
2356
2357                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2358                 if (rc)
2359                         return rc;
2360         } else {
2361                 /* Default filter will allow packets that match the
2362                  * dest mac. So, it has to be deleted, otherwise, we
2363                  * will endup receiving vlan packets for which the
2364                  * filter is not programmed, when hw-vlan-filter
2365                  * configuration is ON
2366                  */
2367                 bnxt_del_dflt_mac_filter(bp, vnic);
2368                 /* This filter will allow only untagged packets */
2369                 bnxt_add_vlan_filter(bp, 0);
2370         }
2371         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2372                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2373
2374         return 0;
2375 }
2376
2377 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2378 {
2379         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2380         unsigned int i;
2381         int rc;
2382
2383         /* Destroy vnic filters and vnic */
2384         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2385             DEV_RX_OFFLOAD_VLAN_FILTER) {
2386                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2387                         bnxt_del_vlan_filter(bp, i);
2388         }
2389         bnxt_del_dflt_mac_filter(bp, vnic);
2390
2391         rc = bnxt_hwrm_vnic_free(bp, vnic);
2392         if (rc)
2393                 return rc;
2394
2395         rte_free(vnic->fw_grp_ids);
2396         vnic->fw_grp_ids = NULL;
2397
2398         vnic->rx_queue_cnt = 0;
2399
2400         return 0;
2401 }
2402
2403 static int
2404 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2405 {
2406         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2407         int rc;
2408
2409         /* Destroy, recreate and reconfigure the default vnic */
2410         rc = bnxt_free_one_vnic(bp, 0);
2411         if (rc)
2412                 return rc;
2413
2414         /* default vnic 0 */
2415         rc = bnxt_setup_one_vnic(bp, 0);
2416         if (rc)
2417                 return rc;
2418
2419         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2420             DEV_RX_OFFLOAD_VLAN_FILTER) {
2421                 rc = bnxt_add_vlan_filter(bp, 0);
2422                 if (rc)
2423                         return rc;
2424                 rc = bnxt_restore_vlan_filters(bp);
2425                 if (rc)
2426                         return rc;
2427         } else {
2428                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2429                 if (rc)
2430                         return rc;
2431         }
2432
2433         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2434         if (rc)
2435                 return rc;
2436
2437         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2438                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2439
2440         return rc;
2441 }
2442
2443 static int
2444 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2445 {
2446         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2447         struct bnxt *bp = dev->data->dev_private;
2448         int rc;
2449
2450         rc = is_bnxt_in_error(bp);
2451         if (rc)
2452                 return rc;
2453
2454         /* Filter settings will get applied when port is started */
2455         if (!dev->data->dev_started)
2456                 return 0;
2457
2458         if (mask & ETH_VLAN_FILTER_MASK) {
2459                 /* Enable or disable VLAN filtering */
2460                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2461                 if (rc)
2462                         return rc;
2463         }
2464
2465         if (mask & ETH_VLAN_STRIP_MASK) {
2466                 /* Enable or disable VLAN stripping */
2467                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2468                 if (rc)
2469                         return rc;
2470         }
2471
2472         if (mask & ETH_VLAN_EXTEND_MASK) {
2473                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2474                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2475                 else
2476                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2477         }
2478
2479         return 0;
2480 }
2481
2482 static int
2483 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2484                       uint16_t tpid)
2485 {
2486         struct bnxt *bp = dev->data->dev_private;
2487         int qinq = dev->data->dev_conf.rxmode.offloads &
2488                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2489
2490         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2491             vlan_type != ETH_VLAN_TYPE_OUTER) {
2492                 PMD_DRV_LOG(ERR,
2493                             "Unsupported vlan type.");
2494                 return -EINVAL;
2495         }
2496         if (!qinq) {
2497                 PMD_DRV_LOG(ERR,
2498                             "QinQ not enabled. Needs to be ON as we can "
2499                             "accelerate only outer vlan\n");
2500                 return -EINVAL;
2501         }
2502
2503         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2504                 switch (tpid) {
2505                 case RTE_ETHER_TYPE_QINQ:
2506                         bp->outer_tpid_bd =
2507                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2508                                 break;
2509                 case RTE_ETHER_TYPE_VLAN:
2510                         bp->outer_tpid_bd =
2511                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2512                                 break;
2513                 case RTE_ETHER_TYPE_QINQ1:
2514                         bp->outer_tpid_bd =
2515                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2516                                 break;
2517                 case RTE_ETHER_TYPE_QINQ2:
2518                         bp->outer_tpid_bd =
2519                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2520                                 break;
2521                 case RTE_ETHER_TYPE_QINQ3:
2522                         bp->outer_tpid_bd =
2523                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2524                                 break;
2525                 default:
2526                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2527                         return -EINVAL;
2528                 }
2529                 bp->outer_tpid_bd |= tpid;
2530                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2531         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2532                 PMD_DRV_LOG(ERR,
2533                             "Can accelerate only outer vlan in QinQ\n");
2534                 return -EINVAL;
2535         }
2536
2537         return 0;
2538 }
2539
2540 static int
2541 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2542                              struct rte_ether_addr *addr)
2543 {
2544         struct bnxt *bp = dev->data->dev_private;
2545         /* Default Filter is tied to VNIC 0 */
2546         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2547         int rc;
2548
2549         rc = is_bnxt_in_error(bp);
2550         if (rc)
2551                 return rc;
2552
2553         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2554                 return -EPERM;
2555
2556         if (rte_is_zero_ether_addr(addr))
2557                 return -EINVAL;
2558
2559         /* Filter settings will get applied when port is started */
2560         if (!dev->data->dev_started)
2561                 return 0;
2562
2563         /* Check if the requested MAC is already added */
2564         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2565                 return 0;
2566
2567         /* Destroy filter and re-create it */
2568         bnxt_del_dflt_mac_filter(bp, vnic);
2569
2570         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2571         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2572                 /* This filter will allow only untagged packets */
2573                 rc = bnxt_add_vlan_filter(bp, 0);
2574         } else {
2575                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2576         }
2577
2578         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2579         return rc;
2580 }
2581
2582 static int
2583 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2584                           struct rte_ether_addr *mc_addr_set,
2585                           uint32_t nb_mc_addr)
2586 {
2587         struct bnxt *bp = eth_dev->data->dev_private;
2588         char *mc_addr_list = (char *)mc_addr_set;
2589         struct bnxt_vnic_info *vnic;
2590         uint32_t off = 0, i = 0;
2591         int rc;
2592
2593         rc = is_bnxt_in_error(bp);
2594         if (rc)
2595                 return rc;
2596
2597         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2598
2599         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2600                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2601                 goto allmulti;
2602         }
2603
2604         /* TODO Check for Duplicate mcast addresses */
2605         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2606         for (i = 0; i < nb_mc_addr; i++) {
2607                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2608                         RTE_ETHER_ADDR_LEN);
2609                 off += RTE_ETHER_ADDR_LEN;
2610         }
2611
2612         vnic->mc_addr_cnt = i;
2613         if (vnic->mc_addr_cnt)
2614                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2615         else
2616                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2617
2618 allmulti:
2619         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2620 }
2621
2622 static int
2623 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2624 {
2625         struct bnxt *bp = dev->data->dev_private;
2626         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2627         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2628         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2629         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2630         int ret;
2631
2632         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2633                         fw_major, fw_minor, fw_updt, fw_rsvd);
2634
2635         ret += 1; /* add the size of '\0' */
2636         if (fw_size < (uint32_t)ret)
2637                 return ret;
2638         else
2639                 return 0;
2640 }
2641
2642 static void
2643 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2644         struct rte_eth_rxq_info *qinfo)
2645 {
2646         struct bnxt *bp = dev->data->dev_private;
2647         struct bnxt_rx_queue *rxq;
2648
2649         if (is_bnxt_in_error(bp))
2650                 return;
2651
2652         rxq = dev->data->rx_queues[queue_id];
2653
2654         qinfo->mp = rxq->mb_pool;
2655         qinfo->scattered_rx = dev->data->scattered_rx;
2656         qinfo->nb_desc = rxq->nb_rx_desc;
2657
2658         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2659         qinfo->conf.rx_drop_en = rxq->drop_en;
2660         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2661         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2662 }
2663
2664 static void
2665 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2666         struct rte_eth_txq_info *qinfo)
2667 {
2668         struct bnxt *bp = dev->data->dev_private;
2669         struct bnxt_tx_queue *txq;
2670
2671         if (is_bnxt_in_error(bp))
2672                 return;
2673
2674         txq = dev->data->tx_queues[queue_id];
2675
2676         qinfo->nb_desc = txq->nb_tx_desc;
2677
2678         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2679         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2680         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2681
2682         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2683         qinfo->conf.tx_rs_thresh = 0;
2684         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2685         qinfo->conf.offloads = txq->offloads;
2686 }
2687
2688 static const struct {
2689         eth_rx_burst_t pkt_burst;
2690         const char *info;
2691 } bnxt_rx_burst_info[] = {
2692         {bnxt_recv_pkts,        "Scalar"},
2693 #if defined(RTE_ARCH_X86)
2694         {bnxt_recv_pkts_vec,    "Vector SSE"},
2695 #elif defined(RTE_ARCH_ARM64)
2696         {bnxt_recv_pkts_vec,    "Vector Neon"},
2697 #endif
2698 };
2699
2700 static int
2701 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2702                        struct rte_eth_burst_mode *mode)
2703 {
2704         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2705         size_t i;
2706
2707         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2708                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2709                         snprintf(mode->info, sizeof(mode->info), "%s",
2710                                  bnxt_rx_burst_info[i].info);
2711                         return 0;
2712                 }
2713         }
2714
2715         return -EINVAL;
2716 }
2717
2718 static const struct {
2719         eth_tx_burst_t pkt_burst;
2720         const char *info;
2721 } bnxt_tx_burst_info[] = {
2722         {bnxt_xmit_pkts,        "Scalar"},
2723 #if defined(RTE_ARCH_X86)
2724         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2725 #elif defined(RTE_ARCH_ARM64)
2726         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2727 #endif
2728 };
2729
2730 static int
2731 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2732                        struct rte_eth_burst_mode *mode)
2733 {
2734         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2735         size_t i;
2736
2737         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2738                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2739                         snprintf(mode->info, sizeof(mode->info), "%s",
2740                                  bnxt_tx_burst_info[i].info);
2741                         return 0;
2742                 }
2743         }
2744
2745         return -EINVAL;
2746 }
2747
2748 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2749 {
2750         struct bnxt *bp = eth_dev->data->dev_private;
2751         uint32_t new_pkt_size;
2752         uint32_t rc = 0;
2753         uint32_t i;
2754
2755         rc = is_bnxt_in_error(bp);
2756         if (rc)
2757                 return rc;
2758
2759         /* Exit if receive queues are not configured yet */
2760         if (!eth_dev->data->nb_rx_queues)
2761                 return rc;
2762
2763         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2764                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2765
2766         /*
2767          * Disallow any MTU change that would require scattered receive support
2768          * if it is not already enabled.
2769          */
2770         if (eth_dev->data->dev_started &&
2771             !eth_dev->data->scattered_rx &&
2772             (new_pkt_size >
2773              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2774                 PMD_DRV_LOG(ERR,
2775                             "MTU change would require scattered rx support. ");
2776                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2777                 return -EINVAL;
2778         }
2779
2780         if (new_mtu > RTE_ETHER_MTU) {
2781                 bp->flags |= BNXT_FLAG_JUMBO;
2782                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2783                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2784         } else {
2785                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2786                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2787                 bp->flags &= ~BNXT_FLAG_JUMBO;
2788         }
2789
2790         /* Is there a change in mtu setting? */
2791         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2792                 return rc;
2793
2794         for (i = 0; i < bp->nr_vnics; i++) {
2795                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2796                 uint16_t size = 0;
2797
2798                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2799                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2800                 if (rc)
2801                         break;
2802
2803                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2804                 size -= RTE_PKTMBUF_HEADROOM;
2805
2806                 if (size < new_mtu) {
2807                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2808                         if (rc)
2809                                 return rc;
2810                 }
2811         }
2812
2813         if (!rc)
2814                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2815
2816         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2817
2818         return rc;
2819 }
2820
2821 static int
2822 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2823 {
2824         struct bnxt *bp = dev->data->dev_private;
2825         uint16_t vlan = bp->vlan;
2826         int rc;
2827
2828         rc = is_bnxt_in_error(bp);
2829         if (rc)
2830                 return rc;
2831
2832         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2833                 PMD_DRV_LOG(ERR,
2834                         "PVID cannot be modified for this function\n");
2835                 return -ENOTSUP;
2836         }
2837         bp->vlan = on ? pvid : 0;
2838
2839         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2840         if (rc)
2841                 bp->vlan = vlan;
2842         return rc;
2843 }
2844
2845 static int
2846 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2847 {
2848         struct bnxt *bp = dev->data->dev_private;
2849         int rc;
2850
2851         rc = is_bnxt_in_error(bp);
2852         if (rc)
2853                 return rc;
2854
2855         return bnxt_hwrm_port_led_cfg(bp, true);
2856 }
2857
2858 static int
2859 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2860 {
2861         struct bnxt *bp = dev->data->dev_private;
2862         int rc;
2863
2864         rc = is_bnxt_in_error(bp);
2865         if (rc)
2866                 return rc;
2867
2868         return bnxt_hwrm_port_led_cfg(bp, false);
2869 }
2870
2871 static uint32_t
2872 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2873 {
2874         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2875         uint32_t desc = 0, raw_cons = 0, cons;
2876         struct bnxt_cp_ring_info *cpr;
2877         struct bnxt_rx_queue *rxq;
2878         struct rx_pkt_cmpl *rxcmp;
2879         int rc;
2880
2881         rc = is_bnxt_in_error(bp);
2882         if (rc)
2883                 return rc;
2884
2885         rxq = dev->data->rx_queues[rx_queue_id];
2886         cpr = rxq->cp_ring;
2887         raw_cons = cpr->cp_raw_cons;
2888
2889         while (1) {
2890                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2891                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2892                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2893
2894                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2895                         break;
2896                 } else {
2897                         raw_cons++;
2898                         desc++;
2899                 }
2900         }
2901
2902         return desc;
2903 }
2904
2905 static int
2906 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2907 {
2908         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2909         struct bnxt_rx_ring_info *rxr;
2910         struct bnxt_cp_ring_info *cpr;
2911         struct rte_mbuf *rx_buf;
2912         struct rx_pkt_cmpl *rxcmp;
2913         uint32_t cons, cp_cons;
2914         int rc;
2915
2916         if (!rxq)
2917                 return -EINVAL;
2918
2919         rc = is_bnxt_in_error(rxq->bp);
2920         if (rc)
2921                 return rc;
2922
2923         cpr = rxq->cp_ring;
2924         rxr = rxq->rx_ring;
2925
2926         if (offset >= rxq->nb_rx_desc)
2927                 return -EINVAL;
2928
2929         cons = RING_CMP(cpr->cp_ring_struct, offset);
2930         cp_cons = cpr->cp_raw_cons;
2931         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2932
2933         if (cons > cp_cons) {
2934                 if (CMPL_VALID(rxcmp, cpr->valid))
2935                         return RTE_ETH_RX_DESC_DONE;
2936         } else {
2937                 if (CMPL_VALID(rxcmp, !cpr->valid))
2938                         return RTE_ETH_RX_DESC_DONE;
2939         }
2940         rx_buf = rxr->rx_buf_ring[cons];
2941         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2942                 return RTE_ETH_RX_DESC_UNAVAIL;
2943
2944
2945         return RTE_ETH_RX_DESC_AVAIL;
2946 }
2947
2948 static int
2949 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2950 {
2951         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2952         struct bnxt_tx_ring_info *txr;
2953         struct bnxt_cp_ring_info *cpr;
2954         struct bnxt_sw_tx_bd *tx_buf;
2955         struct tx_pkt_cmpl *txcmp;
2956         uint32_t cons, cp_cons;
2957         int rc;
2958
2959         if (!txq)
2960                 return -EINVAL;
2961
2962         rc = is_bnxt_in_error(txq->bp);
2963         if (rc)
2964                 return rc;
2965
2966         cpr = txq->cp_ring;
2967         txr = txq->tx_ring;
2968
2969         if (offset >= txq->nb_tx_desc)
2970                 return -EINVAL;
2971
2972         cons = RING_CMP(cpr->cp_ring_struct, offset);
2973         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2974         cp_cons = cpr->cp_raw_cons;
2975
2976         if (cons > cp_cons) {
2977                 if (CMPL_VALID(txcmp, cpr->valid))
2978                         return RTE_ETH_TX_DESC_UNAVAIL;
2979         } else {
2980                 if (CMPL_VALID(txcmp, !cpr->valid))
2981                         return RTE_ETH_TX_DESC_UNAVAIL;
2982         }
2983         tx_buf = &txr->tx_buf_ring[cons];
2984         if (tx_buf->mbuf == NULL)
2985                 return RTE_ETH_TX_DESC_DONE;
2986
2987         return RTE_ETH_TX_DESC_FULL;
2988 }
2989
2990 static struct bnxt_filter_info *
2991 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2992                                 struct rte_eth_ethertype_filter *efilter,
2993                                 struct bnxt_vnic_info *vnic0,
2994                                 struct bnxt_vnic_info *vnic,
2995                                 int *ret)
2996 {
2997         struct bnxt_filter_info *mfilter = NULL;
2998         int match = 0;
2999         *ret = 0;
3000
3001         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
3002                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
3003                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
3004                         " ethertype filter.", efilter->ether_type);
3005                 *ret = -EINVAL;
3006                 goto exit;
3007         }
3008         if (efilter->queue >= bp->rx_nr_rings) {
3009                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3010                 *ret = -EINVAL;
3011                 goto exit;
3012         }
3013
3014         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3015         vnic = &bp->vnic_info[efilter->queue];
3016         if (vnic == NULL) {
3017                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3018                 *ret = -EINVAL;
3019                 goto exit;
3020         }
3021
3022         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3023                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
3024                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3025                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3026                              mfilter->flags ==
3027                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
3028                              mfilter->ethertype == efilter->ether_type)) {
3029                                 match = 1;
3030                                 break;
3031                         }
3032                 }
3033         } else {
3034                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
3035                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3036                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3037                              mfilter->ethertype == efilter->ether_type &&
3038                              mfilter->flags ==
3039                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
3040                                 match = 1;
3041                                 break;
3042                         }
3043         }
3044
3045         if (match)
3046                 *ret = -EEXIST;
3047
3048 exit:
3049         return mfilter;
3050 }
3051
3052 static int
3053 bnxt_ethertype_filter(struct rte_eth_dev *dev,
3054                         enum rte_filter_op filter_op,
3055                         void *arg)
3056 {
3057         struct bnxt *bp = dev->data->dev_private;
3058         struct rte_eth_ethertype_filter *efilter =
3059                         (struct rte_eth_ethertype_filter *)arg;
3060         struct bnxt_filter_info *bfilter, *filter1;
3061         struct bnxt_vnic_info *vnic, *vnic0;
3062         int ret;
3063
3064         if (filter_op == RTE_ETH_FILTER_NOP)
3065                 return 0;
3066
3067         if (arg == NULL) {
3068                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3069                             filter_op);
3070                 return -EINVAL;
3071         }
3072
3073         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3074         vnic = &bp->vnic_info[efilter->queue];
3075
3076         switch (filter_op) {
3077         case RTE_ETH_FILTER_ADD:
3078                 bnxt_match_and_validate_ether_filter(bp, efilter,
3079                                                         vnic0, vnic, &ret);
3080                 if (ret < 0)
3081                         return ret;
3082
3083                 bfilter = bnxt_get_unused_filter(bp);
3084                 if (bfilter == NULL) {
3085                         PMD_DRV_LOG(ERR,
3086                                 "Not enough resources for a new filter.\n");
3087                         return -ENOMEM;
3088                 }
3089                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3090                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3091                        RTE_ETHER_ADDR_LEN);
3092                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3093                        RTE_ETHER_ADDR_LEN);
3094                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3095                 bfilter->ethertype = efilter->ether_type;
3096                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3097
3098                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3099                 if (filter1 == NULL) {
3100                         ret = -EINVAL;
3101                         goto cleanup;
3102                 }
3103                 bfilter->enables |=
3104                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3105                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3106
3107                 bfilter->dst_id = vnic->fw_vnic_id;
3108
3109                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3110                         bfilter->flags =
3111                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3112                 }
3113
3114                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3115                 if (ret)
3116                         goto cleanup;
3117                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3118                 break;
3119         case RTE_ETH_FILTER_DELETE:
3120                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3121                                                         vnic0, vnic, &ret);
3122                 if (ret == -EEXIST) {
3123                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3124
3125                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3126                                       next);
3127                         bnxt_free_filter(bp, filter1);
3128                 } else if (ret == 0) {
3129                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3130                 }
3131                 break;
3132         default:
3133                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3134                 ret = -EINVAL;
3135                 goto error;
3136         }
3137         return ret;
3138 cleanup:
3139         bnxt_free_filter(bp, bfilter);
3140 error:
3141         return ret;
3142 }
3143
3144 static inline int
3145 parse_ntuple_filter(struct bnxt *bp,
3146                     struct rte_eth_ntuple_filter *nfilter,
3147                     struct bnxt_filter_info *bfilter)
3148 {
3149         uint32_t en = 0;
3150
3151         if (nfilter->queue >= bp->rx_nr_rings) {
3152                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3153                 return -EINVAL;
3154         }
3155
3156         switch (nfilter->dst_port_mask) {
3157         case UINT16_MAX:
3158                 bfilter->dst_port_mask = -1;
3159                 bfilter->dst_port = nfilter->dst_port;
3160                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3161                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3162                 break;
3163         default:
3164                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3165                 return -EINVAL;
3166         }
3167
3168         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3169         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3170
3171         switch (nfilter->proto_mask) {
3172         case UINT8_MAX:
3173                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3174                         bfilter->ip_protocol = 17;
3175                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3176                         bfilter->ip_protocol = 6;
3177                 else
3178                         return -EINVAL;
3179                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3180                 break;
3181         default:
3182                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3183                 return -EINVAL;
3184         }
3185
3186         switch (nfilter->dst_ip_mask) {
3187         case UINT32_MAX:
3188                 bfilter->dst_ipaddr_mask[0] = -1;
3189                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3190                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3191                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3192                 break;
3193         default:
3194                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3195                 return -EINVAL;
3196         }
3197
3198         switch (nfilter->src_ip_mask) {
3199         case UINT32_MAX:
3200                 bfilter->src_ipaddr_mask[0] = -1;
3201                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3202                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3203                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3204                 break;
3205         default:
3206                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3207                 return -EINVAL;
3208         }
3209
3210         switch (nfilter->src_port_mask) {
3211         case UINT16_MAX:
3212                 bfilter->src_port_mask = -1;
3213                 bfilter->src_port = nfilter->src_port;
3214                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3215                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3216                 break;
3217         default:
3218                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3219                 return -EINVAL;
3220         }
3221
3222         bfilter->enables = en;
3223         return 0;
3224 }
3225
3226 static struct bnxt_filter_info*
3227 bnxt_match_ntuple_filter(struct bnxt *bp,
3228                          struct bnxt_filter_info *bfilter,
3229                          struct bnxt_vnic_info **mvnic)
3230 {
3231         struct bnxt_filter_info *mfilter = NULL;
3232         int i;
3233
3234         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3235                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3236                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3237                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3238                             bfilter->src_ipaddr_mask[0] ==
3239                             mfilter->src_ipaddr_mask[0] &&
3240                             bfilter->src_port == mfilter->src_port &&
3241                             bfilter->src_port_mask == mfilter->src_port_mask &&
3242                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3243                             bfilter->dst_ipaddr_mask[0] ==
3244                             mfilter->dst_ipaddr_mask[0] &&
3245                             bfilter->dst_port == mfilter->dst_port &&
3246                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3247                             bfilter->flags == mfilter->flags &&
3248                             bfilter->enables == mfilter->enables) {
3249                                 if (mvnic)
3250                                         *mvnic = vnic;
3251                                 return mfilter;
3252                         }
3253                 }
3254         }
3255         return NULL;
3256 }
3257
3258 static int
3259 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3260                        struct rte_eth_ntuple_filter *nfilter,
3261                        enum rte_filter_op filter_op)
3262 {
3263         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3264         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3265         int ret;
3266
3267         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3268                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3269                 return -EINVAL;
3270         }
3271
3272         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3273                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3274                 return -EINVAL;
3275         }
3276
3277         bfilter = bnxt_get_unused_filter(bp);
3278         if (bfilter == NULL) {
3279                 PMD_DRV_LOG(ERR,
3280                         "Not enough resources for a new filter.\n");
3281                 return -ENOMEM;
3282         }
3283         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3284         if (ret < 0)
3285                 goto free_filter;
3286
3287         vnic = &bp->vnic_info[nfilter->queue];
3288         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3289         filter1 = STAILQ_FIRST(&vnic0->filter);
3290         if (filter1 == NULL) {
3291                 ret = -EINVAL;
3292                 goto free_filter;
3293         }
3294
3295         bfilter->dst_id = vnic->fw_vnic_id;
3296         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3297         bfilter->enables |=
3298                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3299         bfilter->ethertype = 0x800;
3300         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3301
3302         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3303
3304         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3305             bfilter->dst_id == mfilter->dst_id) {
3306                 PMD_DRV_LOG(ERR, "filter exists.\n");
3307                 ret = -EEXIST;
3308                 goto free_filter;
3309         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3310                    bfilter->dst_id != mfilter->dst_id) {
3311                 mfilter->dst_id = vnic->fw_vnic_id;
3312                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3313                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3314                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3315                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3316                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3317                 goto free_filter;
3318         }
3319         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3320                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3321                 ret = -ENOENT;
3322                 goto free_filter;
3323         }
3324
3325         if (filter_op == RTE_ETH_FILTER_ADD) {
3326                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3327                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3328                 if (ret)
3329                         goto free_filter;
3330                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3331         } else {
3332                 if (mfilter == NULL) {
3333                         /* This should not happen. But for Coverity! */
3334                         ret = -ENOENT;
3335                         goto free_filter;
3336                 }
3337                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3338
3339                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3340                 bnxt_free_filter(bp, mfilter);
3341                 bnxt_free_filter(bp, bfilter);
3342         }
3343
3344         return 0;
3345 free_filter:
3346         bnxt_free_filter(bp, bfilter);
3347         return ret;
3348 }
3349
3350 static int
3351 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3352                         enum rte_filter_op filter_op,
3353                         void *arg)
3354 {
3355         struct bnxt *bp = dev->data->dev_private;
3356         int ret;
3357
3358         if (filter_op == RTE_ETH_FILTER_NOP)
3359                 return 0;
3360
3361         if (arg == NULL) {
3362                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3363                             filter_op);
3364                 return -EINVAL;
3365         }
3366
3367         switch (filter_op) {
3368         case RTE_ETH_FILTER_ADD:
3369                 ret = bnxt_cfg_ntuple_filter(bp,
3370                         (struct rte_eth_ntuple_filter *)arg,
3371                         filter_op);
3372                 break;
3373         case RTE_ETH_FILTER_DELETE:
3374                 ret = bnxt_cfg_ntuple_filter(bp,
3375                         (struct rte_eth_ntuple_filter *)arg,
3376                         filter_op);
3377                 break;
3378         default:
3379                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3380                 ret = -EINVAL;
3381                 break;
3382         }
3383         return ret;
3384 }
3385
3386 static int
3387 bnxt_parse_fdir_filter(struct bnxt *bp,
3388                        struct rte_eth_fdir_filter *fdir,
3389                        struct bnxt_filter_info *filter)
3390 {
3391         enum rte_fdir_mode fdir_mode =
3392                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3393         struct bnxt_vnic_info *vnic0, *vnic;
3394         struct bnxt_filter_info *filter1;
3395         uint32_t en = 0;
3396         int i;
3397
3398         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3399                 return -EINVAL;
3400
3401         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3402         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3403
3404         switch (fdir->input.flow_type) {
3405         case RTE_ETH_FLOW_IPV4:
3406         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3407                 /* FALLTHROUGH */
3408                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3409                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3410                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3411                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3412                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3413                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3414                 filter->ip_addr_type =
3415                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3416                 filter->src_ipaddr_mask[0] = 0xffffffff;
3417                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3418                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3419                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3420                 filter->ethertype = 0x800;
3421                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3422                 break;
3423         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3424                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3425                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3426                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3427                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3428                 filter->dst_port_mask = 0xffff;
3429                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3430                 filter->src_port_mask = 0xffff;
3431                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3432                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3433                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3434                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3435                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3436                 filter->ip_protocol = 6;
3437                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3438                 filter->ip_addr_type =
3439                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3440                 filter->src_ipaddr_mask[0] = 0xffffffff;
3441                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3442                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3443                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3444                 filter->ethertype = 0x800;
3445                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3446                 break;
3447         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3448                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3449                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3450                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3451                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3452                 filter->dst_port_mask = 0xffff;
3453                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3454                 filter->src_port_mask = 0xffff;
3455                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3456                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3457                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3458                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3459                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3460                 filter->ip_protocol = 17;
3461                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3462                 filter->ip_addr_type =
3463                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3464                 filter->src_ipaddr_mask[0] = 0xffffffff;
3465                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3466                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3467                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3468                 filter->ethertype = 0x800;
3469                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3470                 break;
3471         case RTE_ETH_FLOW_IPV6:
3472         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3473                 /* FALLTHROUGH */
3474                 filter->ip_addr_type =
3475                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3476                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3477                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3478                 rte_memcpy(filter->src_ipaddr,
3479                            fdir->input.flow.ipv6_flow.src_ip, 16);
3480                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3481                 rte_memcpy(filter->dst_ipaddr,
3482                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3483                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3484                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3485                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3486                 memset(filter->src_ipaddr_mask, 0xff, 16);
3487                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3488                 filter->ethertype = 0x86dd;
3489                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3490                 break;
3491         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3492                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3493                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3494                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3495                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3496                 filter->dst_port_mask = 0xffff;
3497                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3498                 filter->src_port_mask = 0xffff;
3499                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3500                 filter->ip_addr_type =
3501                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3502                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3503                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3504                 rte_memcpy(filter->src_ipaddr,
3505                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3506                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3507                 rte_memcpy(filter->dst_ipaddr,
3508                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3509                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3510                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3511                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3512                 memset(filter->src_ipaddr_mask, 0xff, 16);
3513                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3514                 filter->ethertype = 0x86dd;
3515                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3516                 break;
3517         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3518                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3519                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3520                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3521                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3522                 filter->dst_port_mask = 0xffff;
3523                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3524                 filter->src_port_mask = 0xffff;
3525                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3526                 filter->ip_addr_type =
3527                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3528                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3529                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3530                 rte_memcpy(filter->src_ipaddr,
3531                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3532                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3533                 rte_memcpy(filter->dst_ipaddr,
3534                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3535                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3536                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3537                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3538                 memset(filter->src_ipaddr_mask, 0xff, 16);
3539                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3540                 filter->ethertype = 0x86dd;
3541                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3542                 break;
3543         case RTE_ETH_FLOW_L2_PAYLOAD:
3544                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3545                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3546                 break;
3547         case RTE_ETH_FLOW_VXLAN:
3548                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3549                         return -EINVAL;
3550                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3551                 filter->tunnel_type =
3552                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3553                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3554                 break;
3555         case RTE_ETH_FLOW_NVGRE:
3556                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3557                         return -EINVAL;
3558                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3559                 filter->tunnel_type =
3560                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3561                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3562                 break;
3563         case RTE_ETH_FLOW_UNKNOWN:
3564         case RTE_ETH_FLOW_RAW:
3565         case RTE_ETH_FLOW_FRAG_IPV4:
3566         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3567         case RTE_ETH_FLOW_FRAG_IPV6:
3568         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3569         case RTE_ETH_FLOW_IPV6_EX:
3570         case RTE_ETH_FLOW_IPV6_TCP_EX:
3571         case RTE_ETH_FLOW_IPV6_UDP_EX:
3572         case RTE_ETH_FLOW_GENEVE:
3573                 /* FALLTHROUGH */
3574         default:
3575                 return -EINVAL;
3576         }
3577
3578         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3579         vnic = &bp->vnic_info[fdir->action.rx_queue];
3580         if (vnic == NULL) {
3581                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3582                 return -EINVAL;
3583         }
3584
3585         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3586                 rte_memcpy(filter->dst_macaddr,
3587                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3588                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3589         }
3590
3591         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3592                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3593                 filter1 = STAILQ_FIRST(&vnic0->filter);
3594                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3595         } else {
3596                 filter->dst_id = vnic->fw_vnic_id;
3597                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3598                         if (filter->dst_macaddr[i] == 0x00)
3599                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3600                         else
3601                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3602         }
3603
3604         if (filter1 == NULL)
3605                 return -EINVAL;
3606
3607         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3608         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3609
3610         filter->enables = en;
3611
3612         return 0;
3613 }
3614
3615 static struct bnxt_filter_info *
3616 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3617                 struct bnxt_vnic_info **mvnic)
3618 {
3619         struct bnxt_filter_info *mf = NULL;
3620         int i;
3621
3622         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3623                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3624
3625                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3626                         if (mf->filter_type == nf->filter_type &&
3627                             mf->flags == nf->flags &&
3628                             mf->src_port == nf->src_port &&
3629                             mf->src_port_mask == nf->src_port_mask &&
3630                             mf->dst_port == nf->dst_port &&
3631                             mf->dst_port_mask == nf->dst_port_mask &&
3632                             mf->ip_protocol == nf->ip_protocol &&
3633                             mf->ip_addr_type == nf->ip_addr_type &&
3634                             mf->ethertype == nf->ethertype &&
3635                             mf->vni == nf->vni &&
3636                             mf->tunnel_type == nf->tunnel_type &&
3637                             mf->l2_ovlan == nf->l2_ovlan &&
3638                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3639                             mf->l2_ivlan == nf->l2_ivlan &&
3640                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3641                             !memcmp(mf->l2_addr, nf->l2_addr,
3642                                     RTE_ETHER_ADDR_LEN) &&
3643                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3644                                     RTE_ETHER_ADDR_LEN) &&
3645                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3646                                     RTE_ETHER_ADDR_LEN) &&
3647                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3648                                     RTE_ETHER_ADDR_LEN) &&
3649                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3650                                     sizeof(nf->src_ipaddr)) &&
3651                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3652                                     sizeof(nf->src_ipaddr_mask)) &&
3653                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3654                                     sizeof(nf->dst_ipaddr)) &&
3655                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3656                                     sizeof(nf->dst_ipaddr_mask))) {
3657                                 if (mvnic)
3658                                         *mvnic = vnic;
3659                                 return mf;
3660                         }
3661                 }
3662         }
3663         return NULL;
3664 }
3665
3666 static int
3667 bnxt_fdir_filter(struct rte_eth_dev *dev,
3668                  enum rte_filter_op filter_op,
3669                  void *arg)
3670 {
3671         struct bnxt *bp = dev->data->dev_private;
3672         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3673         struct bnxt_filter_info *filter, *match;
3674         struct bnxt_vnic_info *vnic, *mvnic;
3675         int ret = 0, i;
3676
3677         if (filter_op == RTE_ETH_FILTER_NOP)
3678                 return 0;
3679
3680         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3681                 return -EINVAL;
3682
3683         switch (filter_op) {
3684         case RTE_ETH_FILTER_ADD:
3685         case RTE_ETH_FILTER_DELETE:
3686                 /* FALLTHROUGH */
3687                 filter = bnxt_get_unused_filter(bp);
3688                 if (filter == NULL) {
3689                         PMD_DRV_LOG(ERR,
3690                                 "Not enough resources for a new flow.\n");
3691                         return -ENOMEM;
3692                 }
3693
3694                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3695                 if (ret != 0)
3696                         goto free_filter;
3697                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3698
3699                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3700                         vnic = &bp->vnic_info[0];
3701                 else
3702                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3703
3704                 match = bnxt_match_fdir(bp, filter, &mvnic);
3705                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3706                         if (match->dst_id == vnic->fw_vnic_id) {
3707                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3708                                 ret = -EEXIST;
3709                                 goto free_filter;
3710                         } else {
3711                                 match->dst_id = vnic->fw_vnic_id;
3712                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3713                                                                   match->dst_id,
3714                                                                   match);
3715                                 STAILQ_REMOVE(&mvnic->filter, match,
3716                                               bnxt_filter_info, next);
3717                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3718                                 PMD_DRV_LOG(ERR,
3719                                         "Filter with matching pattern exist\n");
3720                                 PMD_DRV_LOG(ERR,
3721                                         "Updated it to new destination q\n");
3722                                 goto free_filter;
3723                         }
3724                 }
3725                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3726                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3727                         ret = -ENOENT;
3728                         goto free_filter;
3729                 }
3730
3731                 if (filter_op == RTE_ETH_FILTER_ADD) {
3732                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3733                                                           filter->dst_id,
3734                                                           filter);
3735                         if (ret)
3736                                 goto free_filter;
3737                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3738                 } else {
3739                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3740                         STAILQ_REMOVE(&vnic->filter, match,
3741                                       bnxt_filter_info, next);
3742                         bnxt_free_filter(bp, match);
3743                         bnxt_free_filter(bp, filter);
3744                 }
3745                 break;
3746         case RTE_ETH_FILTER_FLUSH:
3747                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3748                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3749
3750                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3751                                 if (filter->filter_type ==
3752                                     HWRM_CFA_NTUPLE_FILTER) {
3753                                         ret =
3754                                         bnxt_hwrm_clear_ntuple_filter(bp,
3755                                                                       filter);
3756                                         STAILQ_REMOVE(&vnic->filter, filter,
3757                                                       bnxt_filter_info, next);
3758                                 }
3759                         }
3760                 }
3761                 return ret;
3762         case RTE_ETH_FILTER_UPDATE:
3763         case RTE_ETH_FILTER_STATS:
3764         case RTE_ETH_FILTER_INFO:
3765                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3766                 break;
3767         default:
3768                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3769                 ret = -EINVAL;
3770                 break;
3771         }
3772         return ret;
3773
3774 free_filter:
3775         bnxt_free_filter(bp, filter);
3776         return ret;
3777 }
3778
3779 int
3780 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3781                     enum rte_filter_type filter_type,
3782                     enum rte_filter_op filter_op, void *arg)
3783 {
3784         struct bnxt *bp = dev->data->dev_private;
3785         int ret = 0;
3786
3787         if (!bp)
3788                 return -EIO;
3789
3790         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3791                 struct bnxt_representor *vfr = dev->data->dev_private;
3792                 bp = vfr->parent_dev->data->dev_private;
3793                 /* parent is deleted while children are still valid */
3794                 if (!bp) {
3795                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3796                                     dev->data->port_id,
3797                                     filter_type,
3798                                     filter_op);
3799                         return -EIO;
3800                 }
3801         }
3802
3803         ret = is_bnxt_in_error(bp);
3804         if (ret)
3805                 return ret;
3806
3807         switch (filter_type) {
3808         case RTE_ETH_FILTER_TUNNEL:
3809                 PMD_DRV_LOG(ERR,
3810                         "filter type: %d: To be implemented\n", filter_type);
3811                 break;
3812         case RTE_ETH_FILTER_FDIR:
3813                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3814                 break;
3815         case RTE_ETH_FILTER_NTUPLE:
3816                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3817                 break;
3818         case RTE_ETH_FILTER_ETHERTYPE:
3819                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3820                 break;
3821         case RTE_ETH_FILTER_GENERIC:
3822                 if (filter_op != RTE_ETH_FILTER_GET)
3823                         return -EINVAL;
3824                 if (BNXT_TRUFLOW_EN(bp))
3825                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3826                 else
3827                         *(const void **)arg = &bnxt_flow_ops;
3828                 break;
3829         default:
3830                 PMD_DRV_LOG(ERR,
3831                         "Filter type (%d) not supported", filter_type);
3832                 ret = -EINVAL;
3833                 break;
3834         }
3835         return ret;
3836 }
3837
3838 static const uint32_t *
3839 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3840 {
3841         static const uint32_t ptypes[] = {
3842                 RTE_PTYPE_L2_ETHER_VLAN,
3843                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3844                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3845                 RTE_PTYPE_L4_ICMP,
3846                 RTE_PTYPE_L4_TCP,
3847                 RTE_PTYPE_L4_UDP,
3848                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3849                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3850                 RTE_PTYPE_INNER_L4_ICMP,
3851                 RTE_PTYPE_INNER_L4_TCP,
3852                 RTE_PTYPE_INNER_L4_UDP,
3853                 RTE_PTYPE_UNKNOWN
3854         };
3855
3856         if (!dev->rx_pkt_burst)
3857                 return NULL;
3858
3859         return ptypes;
3860 }
3861
3862 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3863                          int reg_win)
3864 {
3865         uint32_t reg_base = *reg_arr & 0xfffff000;
3866         uint32_t win_off;
3867         int i;
3868
3869         for (i = 0; i < count; i++) {
3870                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3871                         return -ERANGE;
3872         }
3873         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3874         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3875         return 0;
3876 }
3877
3878 static int bnxt_map_ptp_regs(struct bnxt *bp)
3879 {
3880         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3881         uint32_t *reg_arr;
3882         int rc, i;
3883
3884         reg_arr = ptp->rx_regs;
3885         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3886         if (rc)
3887                 return rc;
3888
3889         reg_arr = ptp->tx_regs;
3890         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3891         if (rc)
3892                 return rc;
3893
3894         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3895                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3896
3897         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3898                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3899
3900         return 0;
3901 }
3902
3903 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3904 {
3905         rte_write32(0, (uint8_t *)bp->bar0 +
3906                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3907         rte_write32(0, (uint8_t *)bp->bar0 +
3908                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3909 }
3910
3911 static uint64_t bnxt_cc_read(struct bnxt *bp)
3912 {
3913         uint64_t ns;
3914
3915         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3916                               BNXT_GRCPF_REG_SYNC_TIME));
3917         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3918                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3919         return ns;
3920 }
3921
3922 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3923 {
3924         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3925         uint32_t fifo;
3926
3927         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3928                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3929         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3930                 return -EAGAIN;
3931
3932         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3933                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3934         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3935                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3936         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3937                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3938
3939         return 0;
3940 }
3941
3942 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3943 {
3944         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3945         struct bnxt_pf_info *pf = bp->pf;
3946         uint16_t port_id;
3947         uint32_t fifo;
3948
3949         if (!ptp)
3950                 return -ENODEV;
3951
3952         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3953                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3954         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3955                 return -EAGAIN;
3956
3957         port_id = pf->port_id;
3958         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3959                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3960
3961         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3962                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3963         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3964 /*              bnxt_clr_rx_ts(bp);       TBD  */
3965                 return -EBUSY;
3966         }
3967
3968         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3969                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3970         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3971                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3972
3973         return 0;
3974 }
3975
3976 static int
3977 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3978 {
3979         uint64_t ns;
3980         struct bnxt *bp = dev->data->dev_private;
3981         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3982
3983         if (!ptp)
3984                 return 0;
3985
3986         ns = rte_timespec_to_ns(ts);
3987         /* Set the timecounters to a new value. */
3988         ptp->tc.nsec = ns;
3989
3990         return 0;
3991 }
3992
3993 static int
3994 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3995 {
3996         struct bnxt *bp = dev->data->dev_private;
3997         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3998         uint64_t ns, systime_cycles = 0;
3999         int rc = 0;
4000
4001         if (!ptp)
4002                 return 0;
4003
4004         if (BNXT_CHIP_THOR(bp))
4005                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
4006                                              &systime_cycles);
4007         else
4008                 systime_cycles = bnxt_cc_read(bp);
4009
4010         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
4011         *ts = rte_ns_to_timespec(ns);
4012
4013         return rc;
4014 }
4015 static int
4016 bnxt_timesync_enable(struct rte_eth_dev *dev)
4017 {
4018         struct bnxt *bp = dev->data->dev_private;
4019         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4020         uint32_t shift = 0;
4021         int rc;
4022
4023         if (!ptp)
4024                 return 0;
4025
4026         ptp->rx_filter = 1;
4027         ptp->tx_tstamp_en = 1;
4028         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
4029
4030         rc = bnxt_hwrm_ptp_cfg(bp);
4031         if (rc)
4032                 return rc;
4033
4034         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
4035         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4036         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4037
4038         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4039         ptp->tc.cc_shift = shift;
4040         ptp->tc.nsec_mask = (1ULL << shift) - 1;
4041
4042         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4043         ptp->rx_tstamp_tc.cc_shift = shift;
4044         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4045
4046         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4047         ptp->tx_tstamp_tc.cc_shift = shift;
4048         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4049
4050         if (!BNXT_CHIP_THOR(bp))
4051                 bnxt_map_ptp_regs(bp);
4052
4053         return 0;
4054 }
4055
4056 static int
4057 bnxt_timesync_disable(struct rte_eth_dev *dev)
4058 {
4059         struct bnxt *bp = dev->data->dev_private;
4060         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4061
4062         if (!ptp)
4063                 return 0;
4064
4065         ptp->rx_filter = 0;
4066         ptp->tx_tstamp_en = 0;
4067         ptp->rxctl = 0;
4068
4069         bnxt_hwrm_ptp_cfg(bp);
4070
4071         if (!BNXT_CHIP_THOR(bp))
4072                 bnxt_unmap_ptp_regs(bp);
4073
4074         return 0;
4075 }
4076
4077 static int
4078 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4079                                  struct timespec *timestamp,
4080                                  uint32_t flags __rte_unused)
4081 {
4082         struct bnxt *bp = dev->data->dev_private;
4083         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4084         uint64_t rx_tstamp_cycles = 0;
4085         uint64_t ns;
4086
4087         if (!ptp)
4088                 return 0;
4089
4090         if (BNXT_CHIP_THOR(bp))
4091                 rx_tstamp_cycles = ptp->rx_timestamp;
4092         else
4093                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4094
4095         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4096         *timestamp = rte_ns_to_timespec(ns);
4097         return  0;
4098 }
4099
4100 static int
4101 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4102                                  struct timespec *timestamp)
4103 {
4104         struct bnxt *bp = dev->data->dev_private;
4105         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4106         uint64_t tx_tstamp_cycles = 0;
4107         uint64_t ns;
4108         int rc = 0;
4109
4110         if (!ptp)
4111                 return 0;
4112
4113         if (BNXT_CHIP_THOR(bp))
4114                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4115                                              &tx_tstamp_cycles);
4116         else
4117                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4118
4119         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4120         *timestamp = rte_ns_to_timespec(ns);
4121
4122         return rc;
4123 }
4124
4125 static int
4126 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4127 {
4128         struct bnxt *bp = dev->data->dev_private;
4129         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4130
4131         if (!ptp)
4132                 return 0;
4133
4134         ptp->tc.nsec += delta;
4135
4136         return 0;
4137 }
4138
4139 static int
4140 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4141 {
4142         struct bnxt *bp = dev->data->dev_private;
4143         int rc;
4144         uint32_t dir_entries;
4145         uint32_t entry_length;
4146
4147         rc = is_bnxt_in_error(bp);
4148         if (rc)
4149                 return rc;
4150
4151         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4152                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4153                     bp->pdev->addr.devid, bp->pdev->addr.function);
4154
4155         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4156         if (rc != 0)
4157                 return rc;
4158
4159         return dir_entries * entry_length;
4160 }
4161
4162 static int
4163 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4164                 struct rte_dev_eeprom_info *in_eeprom)
4165 {
4166         struct bnxt *bp = dev->data->dev_private;
4167         uint32_t index;
4168         uint32_t offset;
4169         int rc;
4170
4171         rc = is_bnxt_in_error(bp);
4172         if (rc)
4173                 return rc;
4174
4175         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4176                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4177                     bp->pdev->addr.devid, bp->pdev->addr.function,
4178                     in_eeprom->offset, in_eeprom->length);
4179
4180         if (in_eeprom->offset == 0) /* special offset value to get directory */
4181                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4182                                                 in_eeprom->data);
4183
4184         index = in_eeprom->offset >> 24;
4185         offset = in_eeprom->offset & 0xffffff;
4186
4187         if (index != 0)
4188                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4189                                            in_eeprom->length, in_eeprom->data);
4190
4191         return 0;
4192 }
4193
4194 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4195 {
4196         switch (dir_type) {
4197         case BNX_DIR_TYPE_CHIMP_PATCH:
4198         case BNX_DIR_TYPE_BOOTCODE:
4199         case BNX_DIR_TYPE_BOOTCODE_2:
4200         case BNX_DIR_TYPE_APE_FW:
4201         case BNX_DIR_TYPE_APE_PATCH:
4202         case BNX_DIR_TYPE_KONG_FW:
4203         case BNX_DIR_TYPE_KONG_PATCH:
4204         case BNX_DIR_TYPE_BONO_FW:
4205         case BNX_DIR_TYPE_BONO_PATCH:
4206                 /* FALLTHROUGH */
4207                 return true;
4208         }
4209
4210         return false;
4211 }
4212
4213 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4214 {
4215         switch (dir_type) {
4216         case BNX_DIR_TYPE_AVS:
4217         case BNX_DIR_TYPE_EXP_ROM_MBA:
4218         case BNX_DIR_TYPE_PCIE:
4219         case BNX_DIR_TYPE_TSCF_UCODE:
4220         case BNX_DIR_TYPE_EXT_PHY:
4221         case BNX_DIR_TYPE_CCM:
4222         case BNX_DIR_TYPE_ISCSI_BOOT:
4223         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4224         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4225                 /* FALLTHROUGH */
4226                 return true;
4227         }
4228
4229         return false;
4230 }
4231
4232 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4233 {
4234         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4235                 bnxt_dir_type_is_other_exec_format(dir_type);
4236 }
4237
4238 static int
4239 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4240                 struct rte_dev_eeprom_info *in_eeprom)
4241 {
4242         struct bnxt *bp = dev->data->dev_private;
4243         uint8_t index, dir_op;
4244         uint16_t type, ext, ordinal, attr;
4245         int rc;
4246
4247         rc = is_bnxt_in_error(bp);
4248         if (rc)
4249                 return rc;
4250
4251         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4252                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4253                     bp->pdev->addr.devid, bp->pdev->addr.function,
4254                     in_eeprom->offset, in_eeprom->length);
4255
4256         if (!BNXT_PF(bp)) {
4257                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4258                 return -EINVAL;
4259         }
4260
4261         type = in_eeprom->magic >> 16;
4262
4263         if (type == 0xffff) { /* special value for directory operations */
4264                 index = in_eeprom->magic & 0xff;
4265                 dir_op = in_eeprom->magic >> 8;
4266                 if (index == 0)
4267                         return -EINVAL;
4268                 switch (dir_op) {
4269                 case 0x0e: /* erase */
4270                         if (in_eeprom->offset != ~in_eeprom->magic)
4271                                 return -EINVAL;
4272                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4273                 default:
4274                         return -EINVAL;
4275                 }
4276         }
4277
4278         /* Create or re-write an NVM item: */
4279         if (bnxt_dir_type_is_executable(type) == true)
4280                 return -EOPNOTSUPP;
4281         ext = in_eeprom->magic & 0xffff;
4282         ordinal = in_eeprom->offset >> 16;
4283         attr = in_eeprom->offset & 0xffff;
4284
4285         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4286                                      in_eeprom->data, in_eeprom->length);
4287 }
4288
4289 /*
4290  * Initialization
4291  */
4292
4293 static const struct eth_dev_ops bnxt_dev_ops = {
4294         .dev_infos_get = bnxt_dev_info_get_op,
4295         .dev_close = bnxt_dev_close_op,
4296         .dev_configure = bnxt_dev_configure_op,
4297         .dev_start = bnxt_dev_start_op,
4298         .dev_stop = bnxt_dev_stop_op,
4299         .dev_set_link_up = bnxt_dev_set_link_up_op,
4300         .dev_set_link_down = bnxt_dev_set_link_down_op,
4301         .stats_get = bnxt_stats_get_op,
4302         .stats_reset = bnxt_stats_reset_op,
4303         .rx_queue_setup = bnxt_rx_queue_setup_op,
4304         .rx_queue_release = bnxt_rx_queue_release_op,
4305         .tx_queue_setup = bnxt_tx_queue_setup_op,
4306         .tx_queue_release = bnxt_tx_queue_release_op,
4307         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4308         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4309         .reta_update = bnxt_reta_update_op,
4310         .reta_query = bnxt_reta_query_op,
4311         .rss_hash_update = bnxt_rss_hash_update_op,
4312         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4313         .link_update = bnxt_link_update_op,
4314         .promiscuous_enable = bnxt_promiscuous_enable_op,
4315         .promiscuous_disable = bnxt_promiscuous_disable_op,
4316         .allmulticast_enable = bnxt_allmulticast_enable_op,
4317         .allmulticast_disable = bnxt_allmulticast_disable_op,
4318         .mac_addr_add = bnxt_mac_addr_add_op,
4319         .mac_addr_remove = bnxt_mac_addr_remove_op,
4320         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4321         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4322         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4323         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4324         .vlan_filter_set = bnxt_vlan_filter_set_op,
4325         .vlan_offload_set = bnxt_vlan_offload_set_op,
4326         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4327         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4328         .mtu_set = bnxt_mtu_set_op,
4329         .mac_addr_set = bnxt_set_default_mac_addr_op,
4330         .xstats_get = bnxt_dev_xstats_get_op,
4331         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4332         .xstats_reset = bnxt_dev_xstats_reset_op,
4333         .fw_version_get = bnxt_fw_version_get,
4334         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4335         .rxq_info_get = bnxt_rxq_info_get_op,
4336         .txq_info_get = bnxt_txq_info_get_op,
4337         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4338         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4339         .dev_led_on = bnxt_dev_led_on_op,
4340         .dev_led_off = bnxt_dev_led_off_op,
4341         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4342         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4343         .rx_queue_start = bnxt_rx_queue_start,
4344         .rx_queue_stop = bnxt_rx_queue_stop,
4345         .tx_queue_start = bnxt_tx_queue_start,
4346         .tx_queue_stop = bnxt_tx_queue_stop,
4347         .filter_ctrl = bnxt_filter_ctrl_op,
4348         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4349         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4350         .get_eeprom           = bnxt_get_eeprom_op,
4351         .set_eeprom           = bnxt_set_eeprom_op,
4352         .timesync_enable      = bnxt_timesync_enable,
4353         .timesync_disable     = bnxt_timesync_disable,
4354         .timesync_read_time   = bnxt_timesync_read_time,
4355         .timesync_write_time   = bnxt_timesync_write_time,
4356         .timesync_adjust_time = bnxt_timesync_adjust_time,
4357         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4358         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4359 };
4360
4361 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4362 {
4363         uint32_t offset;
4364
4365         /* Only pre-map the reset GRC registers using window 3 */
4366         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4367                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4368
4369         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4370
4371         return offset;
4372 }
4373
4374 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4375 {
4376         struct bnxt_error_recovery_info *info = bp->recovery_info;
4377         uint32_t reg_base = 0xffffffff;
4378         int i;
4379
4380         /* Only pre-map the monitoring GRC registers using window 2 */
4381         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4382                 uint32_t reg = info->status_regs[i];
4383
4384                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4385                         continue;
4386
4387                 if (reg_base == 0xffffffff)
4388                         reg_base = reg & 0xfffff000;
4389                 if ((reg & 0xfffff000) != reg_base)
4390                         return -ERANGE;
4391
4392                 /* Use mask 0xffc as the Lower 2 bits indicates
4393                  * address space location
4394                  */
4395                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4396                                                 (reg & 0xffc);
4397         }
4398
4399         if (reg_base == 0xffffffff)
4400                 return 0;
4401
4402         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4403                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4404
4405         return 0;
4406 }
4407
4408 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4409 {
4410         struct bnxt_error_recovery_info *info = bp->recovery_info;
4411         uint32_t delay = info->delay_after_reset[index];
4412         uint32_t val = info->reset_reg_val[index];
4413         uint32_t reg = info->reset_reg[index];
4414         uint32_t type, offset;
4415
4416         type = BNXT_FW_STATUS_REG_TYPE(reg);
4417         offset = BNXT_FW_STATUS_REG_OFF(reg);
4418
4419         switch (type) {
4420         case BNXT_FW_STATUS_REG_TYPE_CFG:
4421                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4422                 break;
4423         case BNXT_FW_STATUS_REG_TYPE_GRC:
4424                 offset = bnxt_map_reset_regs(bp, offset);
4425                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4426                 break;
4427         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4428                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4429                 break;
4430         }
4431         /* wait on a specific interval of time until core reset is complete */
4432         if (delay)
4433                 rte_delay_ms(delay);
4434 }
4435
4436 static void bnxt_dev_cleanup(struct bnxt *bp)
4437 {
4438         bp->eth_dev->data->dev_link.link_status = 0;
4439         bp->link_info->link_up = 0;
4440         if (bp->eth_dev->data->dev_started)
4441                 bnxt_dev_stop_op(bp->eth_dev);
4442
4443         bnxt_uninit_resources(bp, true);
4444 }
4445
4446 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4447 {
4448         struct rte_eth_dev *dev = bp->eth_dev;
4449         struct rte_vlan_filter_conf *vfc;
4450         int vidx, vbit, rc;
4451         uint16_t vlan_id;
4452
4453         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4454                 vfc = &dev->data->vlan_filter_conf;
4455                 vidx = vlan_id / 64;
4456                 vbit = vlan_id % 64;
4457
4458                 /* Each bit corresponds to a VLAN id */
4459                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4460                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4461                         if (rc)
4462                                 return rc;
4463                 }
4464         }
4465
4466         return 0;
4467 }
4468
4469 static int bnxt_restore_mac_filters(struct bnxt *bp)
4470 {
4471         struct rte_eth_dev *dev = bp->eth_dev;
4472         struct rte_eth_dev_info dev_info;
4473         struct rte_ether_addr *addr;
4474         uint64_t pool_mask;
4475         uint32_t pool = 0;
4476         uint16_t i;
4477         int rc;
4478
4479         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4480                 return 0;
4481
4482         rc = bnxt_dev_info_get_op(dev, &dev_info);
4483         if (rc)
4484                 return rc;
4485
4486         /* replay MAC address configuration */
4487         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4488                 addr = &dev->data->mac_addrs[i];
4489
4490                 /* skip zero address */
4491                 if (rte_is_zero_ether_addr(addr))
4492                         continue;
4493
4494                 pool = 0;
4495                 pool_mask = dev->data->mac_pool_sel[i];
4496
4497                 do {
4498                         if (pool_mask & 1ULL) {
4499                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4500                                 if (rc)
4501                                         return rc;
4502                         }
4503                         pool_mask >>= 1;
4504                         pool++;
4505                 } while (pool_mask);
4506         }
4507
4508         return 0;
4509 }
4510
4511 static int bnxt_restore_filters(struct bnxt *bp)
4512 {
4513         struct rte_eth_dev *dev = bp->eth_dev;
4514         int ret = 0;
4515
4516         if (dev->data->all_multicast) {
4517                 ret = bnxt_allmulticast_enable_op(dev);
4518                 if (ret)
4519                         return ret;
4520         }
4521         if (dev->data->promiscuous) {
4522                 ret = bnxt_promiscuous_enable_op(dev);
4523                 if (ret)
4524                         return ret;
4525         }
4526
4527         ret = bnxt_restore_mac_filters(bp);
4528         if (ret)
4529                 return ret;
4530
4531         ret = bnxt_restore_vlan_filters(bp);
4532         /* TODO restore other filters as well */
4533         return ret;
4534 }
4535
4536 static void bnxt_dev_recover(void *arg)
4537 {
4538         struct bnxt *bp = arg;
4539         int timeout = bp->fw_reset_max_msecs;
4540         int rc = 0;
4541
4542         /* Clear Error flag so that device re-init should happen */
4543         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4544
4545         do {
4546                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4547                 if (rc == 0)
4548                         break;
4549                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4550                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4551         } while (rc && timeout);
4552
4553         if (rc) {
4554                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4555                 goto err;
4556         }
4557
4558         rc = bnxt_init_resources(bp, true);
4559         if (rc) {
4560                 PMD_DRV_LOG(ERR,
4561                             "Failed to initialize resources after reset\n");
4562                 goto err;
4563         }
4564         /* clear reset flag as the device is initialized now */
4565         bp->flags &= ~BNXT_FLAG_FW_RESET;
4566
4567         rc = bnxt_dev_start_op(bp->eth_dev);
4568         if (rc) {
4569                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4570                 goto err_start;
4571         }
4572
4573         rc = bnxt_restore_filters(bp);
4574         if (rc)
4575                 goto err_start;
4576
4577         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4578         return;
4579 err_start:
4580         bnxt_dev_stop_op(bp->eth_dev);
4581 err:
4582         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4583         bnxt_uninit_resources(bp, false);
4584         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4585 }
4586
4587 void bnxt_dev_reset_and_resume(void *arg)
4588 {
4589         struct bnxt *bp = arg;
4590         int rc;
4591
4592         bnxt_dev_cleanup(bp);
4593
4594         bnxt_wait_for_device_shutdown(bp);
4595
4596         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4597                                bnxt_dev_recover, (void *)bp);
4598         if (rc)
4599                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4600 }
4601
4602 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4603 {
4604         struct bnxt_error_recovery_info *info = bp->recovery_info;
4605         uint32_t reg = info->status_regs[index];
4606         uint32_t type, offset, val = 0;
4607
4608         type = BNXT_FW_STATUS_REG_TYPE(reg);
4609         offset = BNXT_FW_STATUS_REG_OFF(reg);
4610
4611         switch (type) {
4612         case BNXT_FW_STATUS_REG_TYPE_CFG:
4613                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4614                 break;
4615         case BNXT_FW_STATUS_REG_TYPE_GRC:
4616                 offset = info->mapped_status_regs[index];
4617                 /* FALLTHROUGH */
4618         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4619                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4620                                        offset));
4621                 break;
4622         }
4623
4624         return val;
4625 }
4626
4627 static int bnxt_fw_reset_all(struct bnxt *bp)
4628 {
4629         struct bnxt_error_recovery_info *info = bp->recovery_info;
4630         uint32_t i;
4631         int rc = 0;
4632
4633         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4634                 /* Reset through master function driver */
4635                 for (i = 0; i < info->reg_array_cnt; i++)
4636                         bnxt_write_fw_reset_reg(bp, i);
4637                 /* Wait for time specified by FW after triggering reset */
4638                 rte_delay_ms(info->master_func_wait_period_after_reset);
4639         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4640                 /* Reset with the help of Kong processor */
4641                 rc = bnxt_hwrm_fw_reset(bp);
4642                 if (rc)
4643                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4644         }
4645
4646         return rc;
4647 }
4648
4649 static void bnxt_fw_reset_cb(void *arg)
4650 {
4651         struct bnxt *bp = arg;
4652         struct bnxt_error_recovery_info *info = bp->recovery_info;
4653         int rc = 0;
4654
4655         /* Only Master function can do FW reset */
4656         if (bnxt_is_master_func(bp) &&
4657             bnxt_is_recovery_enabled(bp)) {
4658                 rc = bnxt_fw_reset_all(bp);
4659                 if (rc) {
4660                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4661                         return;
4662                 }
4663         }
4664
4665         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4666          * EXCEPTION_FATAL_ASYNC event to all the functions
4667          * (including MASTER FUNC). After receiving this Async, all the active
4668          * drivers should treat this case as FW initiated recovery
4669          */
4670         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4671                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4672                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4673
4674                 /* To recover from error */
4675                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4676                                   (void *)bp);
4677         }
4678 }
4679
4680 /* Driver should poll FW heartbeat, reset_counter with the frequency
4681  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4682  * When the driver detects heartbeat stop or change in reset_counter,
4683  * it has to trigger a reset to recover from the error condition.
4684  * A “master PF” is the function who will have the privilege to
4685  * initiate the chimp reset. The master PF will be elected by the
4686  * firmware and will be notified through async message.
4687  */
4688 static void bnxt_check_fw_health(void *arg)
4689 {
4690         struct bnxt *bp = arg;
4691         struct bnxt_error_recovery_info *info = bp->recovery_info;
4692         uint32_t val = 0, wait_msec;
4693
4694         if (!info || !bnxt_is_recovery_enabled(bp) ||
4695             is_bnxt_in_error(bp))
4696                 return;
4697
4698         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4699         if (val == info->last_heart_beat)
4700                 goto reset;
4701
4702         info->last_heart_beat = val;
4703
4704         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4705         if (val != info->last_reset_counter)
4706                 goto reset;
4707
4708         info->last_reset_counter = val;
4709
4710         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4711                           bnxt_check_fw_health, (void *)bp);
4712
4713         return;
4714 reset:
4715         /* Stop DMA to/from device */
4716         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4717         bp->flags |= BNXT_FLAG_FW_RESET;
4718
4719         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4720
4721         if (bnxt_is_master_func(bp))
4722                 wait_msec = info->master_func_wait_period;
4723         else
4724                 wait_msec = info->normal_func_wait_period;
4725
4726         rte_eal_alarm_set(US_PER_MS * wait_msec,
4727                           bnxt_fw_reset_cb, (void *)bp);
4728 }
4729
4730 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4731 {
4732         uint32_t polling_freq;
4733
4734         pthread_mutex_lock(&bp->health_check_lock);
4735
4736         if (!bnxt_is_recovery_enabled(bp))
4737                 goto done;
4738
4739         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4740                 goto done;
4741
4742         polling_freq = bp->recovery_info->driver_polling_freq;
4743
4744         rte_eal_alarm_set(US_PER_MS * polling_freq,
4745                           bnxt_check_fw_health, (void *)bp);
4746         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4747
4748 done:
4749         pthread_mutex_unlock(&bp->health_check_lock);
4750 }
4751
4752 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4753 {
4754         if (!bnxt_is_recovery_enabled(bp))
4755                 return;
4756
4757         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4758         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4759 }
4760
4761 static bool bnxt_vf_pciid(uint16_t device_id)
4762 {
4763         switch (device_id) {
4764         case BROADCOM_DEV_ID_57304_VF:
4765         case BROADCOM_DEV_ID_57406_VF:
4766         case BROADCOM_DEV_ID_5731X_VF:
4767         case BROADCOM_DEV_ID_5741X_VF:
4768         case BROADCOM_DEV_ID_57414_VF:
4769         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4770         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4771         case BROADCOM_DEV_ID_58802_VF:
4772         case BROADCOM_DEV_ID_57500_VF1:
4773         case BROADCOM_DEV_ID_57500_VF2:
4774                 /* FALLTHROUGH */
4775                 return true;
4776         default:
4777                 return false;
4778         }
4779 }
4780
4781 static bool bnxt_thor_device(uint16_t device_id)
4782 {
4783         switch (device_id) {
4784         case BROADCOM_DEV_ID_57508:
4785         case BROADCOM_DEV_ID_57504:
4786         case BROADCOM_DEV_ID_57502:
4787         case BROADCOM_DEV_ID_57508_MF1:
4788         case BROADCOM_DEV_ID_57504_MF1:
4789         case BROADCOM_DEV_ID_57502_MF1:
4790         case BROADCOM_DEV_ID_57508_MF2:
4791         case BROADCOM_DEV_ID_57504_MF2:
4792         case BROADCOM_DEV_ID_57502_MF2:
4793         case BROADCOM_DEV_ID_57500_VF1:
4794         case BROADCOM_DEV_ID_57500_VF2:
4795                 /* FALLTHROUGH */
4796                 return true;
4797         default:
4798                 return false;
4799         }
4800 }
4801
4802 bool bnxt_stratus_device(struct bnxt *bp)
4803 {
4804         uint16_t device_id = bp->pdev->id.device_id;
4805
4806         switch (device_id) {
4807         case BROADCOM_DEV_ID_STRATUS_NIC:
4808         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4809         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4810                 /* FALLTHROUGH */
4811                 return true;
4812         default:
4813                 return false;
4814         }
4815 }
4816
4817 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4818 {
4819         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4820         struct bnxt *bp = eth_dev->data->dev_private;
4821
4822         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4823         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4824         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4825         if (!bp->bar0 || !bp->doorbell_base) {
4826                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4827                 return -ENODEV;
4828         }
4829
4830         bp->eth_dev = eth_dev;
4831         bp->pdev = pci_dev;
4832
4833         return 0;
4834 }
4835
4836 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4837                                   struct bnxt_ctx_pg_info *ctx_pg,
4838                                   uint32_t mem_size,
4839                                   const char *suffix,
4840                                   uint16_t idx)
4841 {
4842         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4843         const struct rte_memzone *mz = NULL;
4844         char mz_name[RTE_MEMZONE_NAMESIZE];
4845         rte_iova_t mz_phys_addr;
4846         uint64_t valid_bits = 0;
4847         uint32_t sz;
4848         int i;
4849
4850         if (!mem_size)
4851                 return 0;
4852
4853         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4854                          BNXT_PAGE_SIZE;
4855         rmem->page_size = BNXT_PAGE_SIZE;
4856         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4857         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4858         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4859
4860         valid_bits = PTU_PTE_VALID;
4861
4862         if (rmem->nr_pages > 1) {
4863                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4864                          "bnxt_ctx_pg_tbl%s_%x_%d",
4865                          suffix, idx, bp->eth_dev->data->port_id);
4866                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4867                 mz = rte_memzone_lookup(mz_name);
4868                 if (!mz) {
4869                         mz = rte_memzone_reserve_aligned(mz_name,
4870                                                 rmem->nr_pages * 8,
4871                                                 SOCKET_ID_ANY,
4872                                                 RTE_MEMZONE_2MB |
4873                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4874                                                 RTE_MEMZONE_IOVA_CONTIG,
4875                                                 BNXT_PAGE_SIZE);
4876                         if (mz == NULL)
4877                                 return -ENOMEM;
4878                 }
4879
4880                 memset(mz->addr, 0, mz->len);
4881                 mz_phys_addr = mz->iova;
4882
4883                 rmem->pg_tbl = mz->addr;
4884                 rmem->pg_tbl_map = mz_phys_addr;
4885                 rmem->pg_tbl_mz = mz;
4886         }
4887
4888         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4889                  suffix, idx, bp->eth_dev->data->port_id);
4890         mz = rte_memzone_lookup(mz_name);
4891         if (!mz) {
4892                 mz = rte_memzone_reserve_aligned(mz_name,
4893                                                  mem_size,
4894                                                  SOCKET_ID_ANY,
4895                                                  RTE_MEMZONE_1GB |
4896                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4897                                                  RTE_MEMZONE_IOVA_CONTIG,
4898                                                  BNXT_PAGE_SIZE);
4899                 if (mz == NULL)
4900                         return -ENOMEM;
4901         }
4902
4903         memset(mz->addr, 0, mz->len);
4904         mz_phys_addr = mz->iova;
4905
4906         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4907                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4908                 rmem->dma_arr[i] = mz_phys_addr + sz;
4909
4910                 if (rmem->nr_pages > 1) {
4911                         if (i == rmem->nr_pages - 2 &&
4912                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4913                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4914                         else if (i == rmem->nr_pages - 1 &&
4915                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4916                                 valid_bits |= PTU_PTE_LAST;
4917
4918                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4919                                                            valid_bits);
4920                 }
4921         }
4922
4923         rmem->mz = mz;
4924         if (rmem->vmem_size)
4925                 rmem->vmem = (void **)mz->addr;
4926         rmem->dma_arr[0] = mz_phys_addr;
4927         return 0;
4928 }
4929
4930 static void bnxt_free_ctx_mem(struct bnxt *bp)
4931 {
4932         int i;
4933
4934         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4935                 return;
4936
4937         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4938         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4939         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4940         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4941         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4942         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4943         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4944         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4945         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4946         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4947         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4948
4949         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4950                 if (bp->ctx->tqm_mem[i])
4951                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4952         }
4953
4954         rte_free(bp->ctx);
4955         bp->ctx = NULL;
4956 }
4957
4958 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4959
4960 #define min_t(type, x, y) ({                    \
4961         type __min1 = (x);                      \
4962         type __min2 = (y);                      \
4963         __min1 < __min2 ? __min1 : __min2; })
4964
4965 #define max_t(type, x, y) ({                    \
4966         type __max1 = (x);                      \
4967         type __max2 = (y);                      \
4968         __max1 > __max2 ? __max1 : __max2; })
4969
4970 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4971
4972 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4973 {
4974         struct bnxt_ctx_pg_info *ctx_pg;
4975         struct bnxt_ctx_mem_info *ctx;
4976         uint32_t mem_size, ena, entries;
4977         uint32_t entries_sp, min;
4978         int i, rc;
4979
4980         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4981         if (rc) {
4982                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4983                 return rc;
4984         }
4985         ctx = bp->ctx;
4986         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4987                 return 0;
4988
4989         ctx_pg = &ctx->qp_mem;
4990         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4991         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4992         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4993         if (rc)
4994                 return rc;
4995
4996         ctx_pg = &ctx->srq_mem;
4997         ctx_pg->entries = ctx->srq_max_l2_entries;
4998         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4999         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
5000         if (rc)
5001                 return rc;
5002
5003         ctx_pg = &ctx->cq_mem;
5004         ctx_pg->entries = ctx->cq_max_l2_entries;
5005         mem_size = ctx->cq_entry_size * ctx_pg->entries;
5006         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
5007         if (rc)
5008                 return rc;
5009
5010         ctx_pg = &ctx->vnic_mem;
5011         ctx_pg->entries = ctx->vnic_max_vnic_entries +
5012                 ctx->vnic_max_ring_table_entries;
5013         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
5014         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
5015         if (rc)
5016                 return rc;
5017
5018         ctx_pg = &ctx->stat_mem;
5019         ctx_pg->entries = ctx->stat_max_entries;
5020         mem_size = ctx->stat_entry_size * ctx_pg->entries;
5021         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
5022         if (rc)
5023                 return rc;
5024
5025         min = ctx->tqm_min_entries_per_ring;
5026
5027         entries_sp = ctx->qp_max_l2_entries +
5028                      ctx->vnic_max_vnic_entries +
5029                      2 * ctx->qp_min_qp1_entries + min;
5030         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
5031
5032         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
5033         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
5034         entries = clamp_t(uint32_t, entries, min,
5035                           ctx->tqm_max_entries_per_ring);
5036         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
5037                 ctx_pg = ctx->tqm_mem[i];
5038                 ctx_pg->entries = i ? entries : entries_sp;
5039                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
5040                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
5041                 if (rc)
5042                         return rc;
5043                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
5044         }
5045
5046         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
5047         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
5048         if (rc)
5049                 PMD_DRV_LOG(ERR,
5050                             "Failed to configure context mem: rc = %d\n", rc);
5051         else
5052                 ctx->flags |= BNXT_CTX_FLAG_INITED;
5053
5054         return rc;
5055 }
5056
5057 static int bnxt_alloc_stats_mem(struct bnxt *bp)
5058 {
5059         struct rte_pci_device *pci_dev = bp->pdev;
5060         char mz_name[RTE_MEMZONE_NAMESIZE];
5061         const struct rte_memzone *mz = NULL;
5062         uint32_t total_alloc_len;
5063         rte_iova_t mz_phys_addr;
5064
5065         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
5066                 return 0;
5067
5068         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5069                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5070                  pci_dev->addr.bus, pci_dev->addr.devid,
5071                  pci_dev->addr.function, "rx_port_stats");
5072         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5073         mz = rte_memzone_lookup(mz_name);
5074         total_alloc_len =
5075                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
5076                                        sizeof(struct rx_port_stats_ext) + 512);
5077         if (!mz) {
5078                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5079                                          SOCKET_ID_ANY,
5080                                          RTE_MEMZONE_2MB |
5081                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5082                                          RTE_MEMZONE_IOVA_CONTIG);
5083                 if (mz == NULL)
5084                         return -ENOMEM;
5085         }
5086         memset(mz->addr, 0, mz->len);
5087         mz_phys_addr = mz->iova;
5088
5089         bp->rx_mem_zone = (const void *)mz;
5090         bp->hw_rx_port_stats = mz->addr;
5091         bp->hw_rx_port_stats_map = mz_phys_addr;
5092
5093         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5094                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5095                  pci_dev->addr.bus, pci_dev->addr.devid,
5096                  pci_dev->addr.function, "tx_port_stats");
5097         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5098         mz = rte_memzone_lookup(mz_name);
5099         total_alloc_len =
5100                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5101                                        sizeof(struct tx_port_stats_ext) + 512);
5102         if (!mz) {
5103                 mz = rte_memzone_reserve(mz_name,
5104                                          total_alloc_len,
5105                                          SOCKET_ID_ANY,
5106                                          RTE_MEMZONE_2MB |
5107                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5108                                          RTE_MEMZONE_IOVA_CONTIG);
5109                 if (mz == NULL)
5110                         return -ENOMEM;
5111         }
5112         memset(mz->addr, 0, mz->len);
5113         mz_phys_addr = mz->iova;
5114
5115         bp->tx_mem_zone = (const void *)mz;
5116         bp->hw_tx_port_stats = mz->addr;
5117         bp->hw_tx_port_stats_map = mz_phys_addr;
5118         bp->flags |= BNXT_FLAG_PORT_STATS;
5119
5120         /* Display extended statistics if FW supports it */
5121         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5122             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5123             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5124                 return 0;
5125
5126         bp->hw_rx_port_stats_ext = (void *)
5127                 ((uint8_t *)bp->hw_rx_port_stats +
5128                  sizeof(struct rx_port_stats));
5129         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5130                 sizeof(struct rx_port_stats);
5131         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5132
5133         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5134             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5135                 bp->hw_tx_port_stats_ext = (void *)
5136                         ((uint8_t *)bp->hw_tx_port_stats +
5137                          sizeof(struct tx_port_stats));
5138                 bp->hw_tx_port_stats_ext_map =
5139                         bp->hw_tx_port_stats_map +
5140                         sizeof(struct tx_port_stats);
5141                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5142         }
5143
5144         return 0;
5145 }
5146
5147 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5148 {
5149         struct bnxt *bp = eth_dev->data->dev_private;
5150         int rc = 0;
5151
5152         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5153                                                RTE_ETHER_ADDR_LEN *
5154                                                bp->max_l2_ctx,
5155                                                0);
5156         if (eth_dev->data->mac_addrs == NULL) {
5157                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5158                 return -ENOMEM;
5159         }
5160
5161         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5162                 if (BNXT_PF(bp))
5163                         return -EINVAL;
5164
5165                 /* Generate a random MAC address, if none was assigned by PF */
5166                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5167                 bnxt_eth_hw_addr_random(bp->mac_addr);
5168                 PMD_DRV_LOG(INFO,
5169                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5170                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5171                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5172
5173                 rc = bnxt_hwrm_set_mac(bp);
5174                 if (rc)
5175                         return rc;
5176         }
5177
5178         /* Copy the permanent MAC from the FUNC_QCAPS response */
5179         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5180
5181         return rc;
5182 }
5183
5184 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5185 {
5186         int rc = 0;
5187
5188         /* MAC is already configured in FW */
5189         if (BNXT_HAS_DFLT_MAC_SET(bp))
5190                 return 0;
5191
5192         /* Restore the old MAC configured */
5193         rc = bnxt_hwrm_set_mac(bp);
5194         if (rc)
5195                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5196
5197         return rc;
5198 }
5199
5200 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5201 {
5202         if (!BNXT_PF(bp))
5203                 return;
5204
5205         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5206
5207         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
5208                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
5209         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
5210         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
5211         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
5212         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
5213 }
5214
5215 uint16_t
5216 bnxt_get_svif(uint16_t port_id, bool func_svif,
5217               enum bnxt_ulp_intf_type type)
5218 {
5219         struct rte_eth_dev *eth_dev;
5220         struct bnxt *bp;
5221
5222         eth_dev = &rte_eth_devices[port_id];
5223         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5224                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5225                 if (!vfr)
5226                         return 0;
5227
5228                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5229                         return vfr->svif;
5230
5231                 eth_dev = vfr->parent_dev;
5232         }
5233
5234         bp = eth_dev->data->dev_private;
5235
5236         return func_svif ? bp->func_svif : bp->port_svif;
5237 }
5238
5239 uint16_t
5240 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5241 {
5242         struct rte_eth_dev *eth_dev;
5243         struct bnxt_vnic_info *vnic;
5244         struct bnxt *bp;
5245
5246         eth_dev = &rte_eth_devices[port];
5247         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5248                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5249                 if (!vfr)
5250                         return 0;
5251
5252                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5253                         return vfr->dflt_vnic_id;
5254
5255                 eth_dev = vfr->parent_dev;
5256         }
5257
5258         bp = eth_dev->data->dev_private;
5259
5260         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5261
5262         return vnic->fw_vnic_id;
5263 }
5264
5265 uint16_t
5266 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5267 {
5268         struct rte_eth_dev *eth_dev;
5269         struct bnxt *bp;
5270
5271         eth_dev = &rte_eth_devices[port];
5272         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5273                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5274                 if (!vfr)
5275                         return 0;
5276
5277                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5278                         return vfr->fw_fid;
5279
5280                 eth_dev = vfr->parent_dev;
5281         }
5282
5283         bp = eth_dev->data->dev_private;
5284
5285         return bp->fw_fid;
5286 }
5287
5288 enum bnxt_ulp_intf_type
5289 bnxt_get_interface_type(uint16_t port)
5290 {
5291         struct rte_eth_dev *eth_dev;
5292         struct bnxt *bp;
5293
5294         eth_dev = &rte_eth_devices[port];
5295         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5296                 return BNXT_ULP_INTF_TYPE_VF_REP;
5297
5298         bp = eth_dev->data->dev_private;
5299         if (BNXT_PF(bp))
5300                 return BNXT_ULP_INTF_TYPE_PF;
5301         else if (BNXT_VF_IS_TRUSTED(bp))
5302                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5303         else if (BNXT_VF(bp))
5304                 return BNXT_ULP_INTF_TYPE_VF;
5305
5306         return BNXT_ULP_INTF_TYPE_INVALID;
5307 }
5308
5309 uint16_t
5310 bnxt_get_phy_port_id(uint16_t port_id)
5311 {
5312         struct bnxt_representor *vfr;
5313         struct rte_eth_dev *eth_dev;
5314         struct bnxt *bp;
5315
5316         eth_dev = &rte_eth_devices[port_id];
5317         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5318                 vfr = eth_dev->data->dev_private;
5319                 if (!vfr)
5320                         return 0;
5321
5322                 eth_dev = vfr->parent_dev;
5323         }
5324
5325         bp = eth_dev->data->dev_private;
5326
5327         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5328 }
5329
5330 uint16_t
5331 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5332 {
5333         struct rte_eth_dev *eth_dev;
5334         struct bnxt *bp;
5335
5336         eth_dev = &rte_eth_devices[port_id];
5337         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5338                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5339                 if (!vfr)
5340                         return 0;
5341
5342                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5343                         return vfr->fw_fid - 1;
5344
5345                 eth_dev = vfr->parent_dev;
5346         }
5347
5348         bp = eth_dev->data->dev_private;
5349
5350         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5351 }
5352
5353 uint16_t
5354 bnxt_get_vport(uint16_t port_id)
5355 {
5356         return (1 << bnxt_get_phy_port_id(port_id));
5357 }
5358
5359 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5360 {
5361         struct bnxt_error_recovery_info *info = bp->recovery_info;
5362
5363         if (info) {
5364                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5365                         memset(info, 0, sizeof(*info));
5366                 return;
5367         }
5368
5369         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5370                 return;
5371
5372         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5373                            sizeof(*info), 0);
5374         if (!info)
5375                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5376
5377         bp->recovery_info = info;
5378 }
5379
5380 static void bnxt_check_fw_status(struct bnxt *bp)
5381 {
5382         uint32_t fw_status;
5383
5384         if (!(bp->recovery_info &&
5385               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5386                 return;
5387
5388         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5389         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5390                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5391                             fw_status);
5392 }
5393
5394 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5395 {
5396         struct bnxt_error_recovery_info *info = bp->recovery_info;
5397         uint32_t status_loc;
5398         uint32_t sig_ver;
5399
5400         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5401                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5402         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5403                                    BNXT_GRCP_WINDOW_2_BASE +
5404                                    offsetof(struct hcomm_status,
5405                                             sig_ver)));
5406         /* If the signature is absent, then FW does not support this feature */
5407         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5408             HCOMM_STATUS_SIGNATURE_VAL)
5409                 return 0;
5410
5411         if (!info) {
5412                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5413                                    sizeof(*info), 0);
5414                 if (!info)
5415                         return -ENOMEM;
5416                 bp->recovery_info = info;
5417         } else {
5418                 memset(info, 0, sizeof(*info));
5419         }
5420
5421         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5422                                       BNXT_GRCP_WINDOW_2_BASE +
5423                                       offsetof(struct hcomm_status,
5424                                                fw_status_loc)));
5425
5426         /* Only pre-map the FW health status GRC register */
5427         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5428                 return 0;
5429
5430         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5431         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5432                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5433
5434         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5435                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5436
5437         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5438
5439         return 0;
5440 }
5441
5442 static int bnxt_init_fw(struct bnxt *bp)
5443 {
5444         uint16_t mtu;
5445         int rc = 0;
5446
5447         bp->fw_cap = 0;
5448
5449         rc = bnxt_map_hcomm_fw_status_reg(bp);
5450         if (rc)
5451                 return rc;
5452
5453         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5454         if (rc) {
5455                 bnxt_check_fw_status(bp);
5456                 return rc;
5457         }
5458
5459         rc = bnxt_hwrm_func_reset(bp);
5460         if (rc)
5461                 return -EIO;
5462
5463         rc = bnxt_hwrm_vnic_qcaps(bp);
5464         if (rc)
5465                 return rc;
5466
5467         rc = bnxt_hwrm_queue_qportcfg(bp);
5468         if (rc)
5469                 return rc;
5470
5471         /* Get the MAX capabilities for this function.
5472          * This function also allocates context memory for TQM rings and
5473          * informs the firmware about this allocated backing store memory.
5474          */
5475         rc = bnxt_hwrm_func_qcaps(bp);
5476         if (rc)
5477                 return rc;
5478
5479         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5480         if (rc)
5481                 return rc;
5482
5483         bnxt_hwrm_port_mac_qcfg(bp);
5484
5485         bnxt_hwrm_parent_pf_qcfg(bp);
5486
5487         bnxt_hwrm_port_phy_qcaps(bp);
5488
5489         bnxt_alloc_error_recovery_info(bp);
5490         /* Get the adapter error recovery support info */
5491         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5492         if (rc)
5493                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5494
5495         bnxt_hwrm_port_led_qcaps(bp);
5496
5497         return 0;
5498 }
5499
5500 static int
5501 bnxt_init_locks(struct bnxt *bp)
5502 {
5503         int err;
5504
5505         err = pthread_mutex_init(&bp->flow_lock, NULL);
5506         if (err) {
5507                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5508                 return err;
5509         }
5510
5511         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5512         if (err)
5513                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5514
5515         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5516         if (err)
5517                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5518         return err;
5519 }
5520
5521 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5522 {
5523         int rc = 0;
5524
5525         rc = bnxt_init_fw(bp);
5526         if (rc)
5527                 return rc;
5528
5529         if (!reconfig_dev) {
5530                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5531                 if (rc)
5532                         return rc;
5533         } else {
5534                 rc = bnxt_restore_dflt_mac(bp);
5535                 if (rc)
5536                         return rc;
5537         }
5538
5539         bnxt_config_vf_req_fwd(bp);
5540
5541         rc = bnxt_hwrm_func_driver_register(bp);
5542         if (rc) {
5543                 PMD_DRV_LOG(ERR, "Failed to register driver");
5544                 return -EBUSY;
5545         }
5546
5547         if (BNXT_PF(bp)) {
5548                 if (bp->pdev->max_vfs) {
5549                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5550                         if (rc) {
5551                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5552                                 return rc;
5553                         }
5554                 } else {
5555                         rc = bnxt_hwrm_allocate_pf_only(bp);
5556                         if (rc) {
5557                                 PMD_DRV_LOG(ERR,
5558                                             "Failed to allocate PF resources");
5559                                 return rc;
5560                         }
5561                 }
5562         }
5563
5564         rc = bnxt_alloc_mem(bp, reconfig_dev);
5565         if (rc)
5566                 return rc;
5567
5568         rc = bnxt_setup_int(bp);
5569         if (rc)
5570                 return rc;
5571
5572         rc = bnxt_request_int(bp);
5573         if (rc)
5574                 return rc;
5575
5576         rc = bnxt_init_ctx_mem(bp);
5577         if (rc) {
5578                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5579                 return rc;
5580         }
5581
5582         rc = bnxt_init_locks(bp);
5583         if (rc)
5584                 return rc;
5585
5586         return 0;
5587 }
5588
5589 static int
5590 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5591                           const char *value, void *opaque_arg)
5592 {
5593         struct bnxt *bp = opaque_arg;
5594         unsigned long truflow;
5595         char *end = NULL;
5596
5597         if (!value || !opaque_arg) {
5598                 PMD_DRV_LOG(ERR,
5599                             "Invalid parameter passed to truflow devargs.\n");
5600                 return -EINVAL;
5601         }
5602
5603         truflow = strtoul(value, &end, 10);
5604         if (end == NULL || *end != '\0' ||
5605             (truflow == ULONG_MAX && errno == ERANGE)) {
5606                 PMD_DRV_LOG(ERR,
5607                             "Invalid parameter passed to truflow devargs.\n");
5608                 return -EINVAL;
5609         }
5610
5611         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5612                 PMD_DRV_LOG(ERR,
5613                             "Invalid value passed to truflow devargs.\n");
5614                 return -EINVAL;
5615         }
5616
5617         if (truflow) {
5618                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5619                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5620         } else {
5621                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5622                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5623         }
5624
5625         return 0;
5626 }
5627
5628 static int
5629 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5630                              const char *value, void *opaque_arg)
5631 {
5632         struct bnxt *bp = opaque_arg;
5633         unsigned long flow_xstat;
5634         char *end = NULL;
5635
5636         if (!value || !opaque_arg) {
5637                 PMD_DRV_LOG(ERR,
5638                             "Invalid parameter passed to flow_xstat devarg.\n");
5639                 return -EINVAL;
5640         }
5641
5642         flow_xstat = strtoul(value, &end, 10);
5643         if (end == NULL || *end != '\0' ||
5644             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5645                 PMD_DRV_LOG(ERR,
5646                             "Invalid parameter passed to flow_xstat devarg.\n");
5647                 return -EINVAL;
5648         }
5649
5650         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5651                 PMD_DRV_LOG(ERR,
5652                             "Invalid value passed to flow_xstat devarg.\n");
5653                 return -EINVAL;
5654         }
5655
5656         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5657         if (BNXT_FLOW_XSTATS_EN(bp))
5658                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5659
5660         return 0;
5661 }
5662
5663 static int
5664 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5665                                         const char *value, void *opaque_arg)
5666 {
5667         struct bnxt *bp = opaque_arg;
5668         unsigned long max_num_kflows;
5669         char *end = NULL;
5670
5671         if (!value || !opaque_arg) {
5672                 PMD_DRV_LOG(ERR,
5673                         "Invalid parameter passed to max_num_kflows devarg.\n");
5674                 return -EINVAL;
5675         }
5676
5677         max_num_kflows = strtoul(value, &end, 10);
5678         if (end == NULL || *end != '\0' ||
5679                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5680                 PMD_DRV_LOG(ERR,
5681                         "Invalid parameter passed to max_num_kflows devarg.\n");
5682                 return -EINVAL;
5683         }
5684
5685         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5686                 PMD_DRV_LOG(ERR,
5687                         "Invalid value passed to max_num_kflows devarg.\n");
5688                 return -EINVAL;
5689         }
5690
5691         bp->max_num_kflows = max_num_kflows;
5692         if (bp->max_num_kflows)
5693                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5694                                 max_num_kflows);
5695
5696         return 0;
5697 }
5698
5699 static int
5700 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5701                             const char *value, void *opaque_arg)
5702 {
5703         struct bnxt_representor *vfr_bp = opaque_arg;
5704         unsigned long rep_is_pf;
5705         char *end = NULL;
5706
5707         if (!value || !opaque_arg) {
5708                 PMD_DRV_LOG(ERR,
5709                             "Invalid parameter passed to rep_is_pf devargs.\n");
5710                 return -EINVAL;
5711         }
5712
5713         rep_is_pf = strtoul(value, &end, 10);
5714         if (end == NULL || *end != '\0' ||
5715             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5716                 PMD_DRV_LOG(ERR,
5717                             "Invalid parameter passed to rep_is_pf devargs.\n");
5718                 return -EINVAL;
5719         }
5720
5721         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5722                 PMD_DRV_LOG(ERR,
5723                             "Invalid value passed to rep_is_pf devargs.\n");
5724                 return -EINVAL;
5725         }
5726
5727         vfr_bp->flags |= rep_is_pf;
5728         if (BNXT_REP_PF(vfr_bp))
5729                 PMD_DRV_LOG(INFO, "PF representor\n");
5730         else
5731                 PMD_DRV_LOG(INFO, "VF representor\n");
5732
5733         return 0;
5734 }
5735
5736 static int
5737 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5738                                const char *value, void *opaque_arg)
5739 {
5740         struct bnxt_representor *vfr_bp = opaque_arg;
5741         unsigned long rep_based_pf;
5742         char *end = NULL;
5743
5744         if (!value || !opaque_arg) {
5745                 PMD_DRV_LOG(ERR,
5746                             "Invalid parameter passed to rep_based_pf "
5747                             "devargs.\n");
5748                 return -EINVAL;
5749         }
5750
5751         rep_based_pf = strtoul(value, &end, 10);
5752         if (end == NULL || *end != '\0' ||
5753             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5754                 PMD_DRV_LOG(ERR,
5755                             "Invalid parameter passed to rep_based_pf "
5756                             "devargs.\n");
5757                 return -EINVAL;
5758         }
5759
5760         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5761                 PMD_DRV_LOG(ERR,
5762                             "Invalid value passed to rep_based_pf devargs.\n");
5763                 return -EINVAL;
5764         }
5765
5766         vfr_bp->rep_based_pf = rep_based_pf;
5767         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5768
5769         return 0;
5770 }
5771
5772 static int
5773 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5774                             const char *value, void *opaque_arg)
5775 {
5776         struct bnxt_representor *vfr_bp = opaque_arg;
5777         unsigned long rep_q_r2f;
5778         char *end = NULL;
5779
5780         if (!value || !opaque_arg) {
5781                 PMD_DRV_LOG(ERR,
5782                             "Invalid parameter passed to rep_q_r2f "
5783                             "devargs.\n");
5784                 return -EINVAL;
5785         }
5786
5787         rep_q_r2f = strtoul(value, &end, 10);
5788         if (end == NULL || *end != '\0' ||
5789             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5790                 PMD_DRV_LOG(ERR,
5791                             "Invalid parameter passed to rep_q_r2f "
5792                             "devargs.\n");
5793                 return -EINVAL;
5794         }
5795
5796         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5797                 PMD_DRV_LOG(ERR,
5798                             "Invalid value passed to rep_q_r2f devargs.\n");
5799                 return -EINVAL;
5800         }
5801
5802         vfr_bp->rep_q_r2f = rep_q_r2f;
5803         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5804         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5805
5806         return 0;
5807 }
5808
5809 static int
5810 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5811                             const char *value, void *opaque_arg)
5812 {
5813         struct bnxt_representor *vfr_bp = opaque_arg;
5814         unsigned long rep_q_f2r;
5815         char *end = NULL;
5816
5817         if (!value || !opaque_arg) {
5818                 PMD_DRV_LOG(ERR,
5819                             "Invalid parameter passed to rep_q_f2r "
5820                             "devargs.\n");
5821                 return -EINVAL;
5822         }
5823
5824         rep_q_f2r = strtoul(value, &end, 10);
5825         if (end == NULL || *end != '\0' ||
5826             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5827                 PMD_DRV_LOG(ERR,
5828                             "Invalid parameter passed to rep_q_f2r "
5829                             "devargs.\n");
5830                 return -EINVAL;
5831         }
5832
5833         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5834                 PMD_DRV_LOG(ERR,
5835                             "Invalid value passed to rep_q_f2r devargs.\n");
5836                 return -EINVAL;
5837         }
5838
5839         vfr_bp->rep_q_f2r = rep_q_f2r;
5840         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5841         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5842
5843         return 0;
5844 }
5845
5846 static int
5847 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5848                              const char *value, void *opaque_arg)
5849 {
5850         struct bnxt_representor *vfr_bp = opaque_arg;
5851         unsigned long rep_fc_r2f;
5852         char *end = NULL;
5853
5854         if (!value || !opaque_arg) {
5855                 PMD_DRV_LOG(ERR,
5856                             "Invalid parameter passed to rep_fc_r2f "
5857                             "devargs.\n");
5858                 return -EINVAL;
5859         }
5860
5861         rep_fc_r2f = strtoul(value, &end, 10);
5862         if (end == NULL || *end != '\0' ||
5863             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5864                 PMD_DRV_LOG(ERR,
5865                             "Invalid parameter passed to rep_fc_r2f "
5866                             "devargs.\n");
5867                 return -EINVAL;
5868         }
5869
5870         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5871                 PMD_DRV_LOG(ERR,
5872                             "Invalid value passed to rep_fc_r2f devargs.\n");
5873                 return -EINVAL;
5874         }
5875
5876         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5877         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5878         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5879
5880         return 0;
5881 }
5882
5883 static int
5884 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5885                              const char *value, void *opaque_arg)
5886 {
5887         struct bnxt_representor *vfr_bp = opaque_arg;
5888         unsigned long rep_fc_f2r;
5889         char *end = NULL;
5890
5891         if (!value || !opaque_arg) {
5892                 PMD_DRV_LOG(ERR,
5893                             "Invalid parameter passed to rep_fc_f2r "
5894                             "devargs.\n");
5895                 return -EINVAL;
5896         }
5897
5898         rep_fc_f2r = strtoul(value, &end, 10);
5899         if (end == NULL || *end != '\0' ||
5900             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5901                 PMD_DRV_LOG(ERR,
5902                             "Invalid parameter passed to rep_fc_f2r "
5903                             "devargs.\n");
5904                 return -EINVAL;
5905         }
5906
5907         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5908                 PMD_DRV_LOG(ERR,
5909                             "Invalid value passed to rep_fc_f2r devargs.\n");
5910                 return -EINVAL;
5911         }
5912
5913         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5914         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5915         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5916
5917         return 0;
5918 }
5919
5920 static void
5921 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5922 {
5923         struct rte_kvargs *kvlist;
5924
5925         if (devargs == NULL)
5926                 return;
5927
5928         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5929         if (kvlist == NULL)
5930                 return;
5931
5932         /*
5933          * Handler for "truflow" devarg.
5934          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5935          */
5936         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5937                            bnxt_parse_devarg_truflow, bp);
5938
5939         /*
5940          * Handler for "flow_xstat" devarg.
5941          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5942          */
5943         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5944                            bnxt_parse_devarg_flow_xstat, bp);
5945
5946         /*
5947          * Handler for "max_num_kflows" devarg.
5948          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5949          */
5950         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5951                            bnxt_parse_devarg_max_num_kflows, bp);
5952
5953         rte_kvargs_free(kvlist);
5954 }
5955
5956 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5957 {
5958         int rc = 0;
5959
5960         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5961                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5962                 if (rc)
5963                         PMD_DRV_LOG(ERR,
5964                                     "Failed to alloc switch domain: %d\n", rc);
5965                 else
5966                         PMD_DRV_LOG(INFO,
5967                                     "Switch domain allocated %d\n",
5968                                     bp->switch_domain_id);
5969         }
5970
5971         return rc;
5972 }
5973
5974 static int
5975 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5976 {
5977         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5978         static int version_printed;
5979         struct bnxt *bp;
5980         int rc;
5981
5982         if (version_printed++ == 0)
5983                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5984
5985         eth_dev->dev_ops = &bnxt_dev_ops;
5986         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5987         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5988         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5989         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5990         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5991
5992         /*
5993          * For secondary processes, we don't initialise any further
5994          * as primary has already done this work.
5995          */
5996         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5997                 return 0;
5998
5999         rte_eth_copy_pci_info(eth_dev, pci_dev);
6000
6001         bp = eth_dev->data->dev_private;
6002
6003         /* Parse dev arguments passed on when starting the DPDK application. */
6004         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6005
6006         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
6007
6008         if (bnxt_vf_pciid(pci_dev->id.device_id))
6009                 bp->flags |= BNXT_FLAG_VF;
6010
6011         if (bnxt_thor_device(pci_dev->id.device_id))
6012                 bp->flags |= BNXT_FLAG_THOR_CHIP;
6013
6014         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
6015             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
6016             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
6017             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
6018                 bp->flags |= BNXT_FLAG_STINGRAY;
6019
6020         rc = bnxt_init_board(eth_dev);
6021         if (rc) {
6022                 PMD_DRV_LOG(ERR,
6023                             "Failed to initialize board rc: %x\n", rc);
6024                 return rc;
6025         }
6026
6027         rc = bnxt_alloc_pf_info(bp);
6028         if (rc)
6029                 goto error_free;
6030
6031         rc = bnxt_alloc_link_info(bp);
6032         if (rc)
6033                 goto error_free;
6034
6035         rc = bnxt_alloc_parent_info(bp);
6036         if (rc)
6037                 goto error_free;
6038
6039         rc = bnxt_alloc_hwrm_resources(bp);
6040         if (rc) {
6041                 PMD_DRV_LOG(ERR,
6042                             "Failed to allocate hwrm resource rc: %x\n", rc);
6043                 goto error_free;
6044         }
6045         rc = bnxt_alloc_leds_info(bp);
6046         if (rc)
6047                 goto error_free;
6048
6049         rc = bnxt_alloc_cos_queues(bp);
6050         if (rc)
6051                 goto error_free;
6052
6053         rc = bnxt_init_resources(bp, false);
6054         if (rc)
6055                 goto error_free;
6056
6057         rc = bnxt_alloc_stats_mem(bp);
6058         if (rc)
6059                 goto error_free;
6060
6061         bnxt_alloc_switch_domain(bp);
6062
6063         PMD_DRV_LOG(INFO,
6064                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
6065                     pci_dev->mem_resource[0].phys_addr,
6066                     pci_dev->mem_resource[0].addr);
6067
6068         return 0;
6069
6070 error_free:
6071         bnxt_dev_uninit(eth_dev);
6072         return rc;
6073 }
6074
6075
6076 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6077 {
6078         if (!ctx)
6079                 return;
6080
6081         if (ctx->va)
6082                 rte_free(ctx->va);
6083
6084         ctx->va = NULL;
6085         ctx->dma = RTE_BAD_IOVA;
6086         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6087 }
6088
6089 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6090 {
6091         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6092                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6093                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
6094                                   bp->flow_stat->max_fc,
6095                                   false);
6096
6097         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6098                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6099                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
6100                                   bp->flow_stat->max_fc,
6101                                   false);
6102
6103         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6104                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6105         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6106
6107         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6108                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6109         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6110
6111         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6112                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6113         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6114
6115         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6116                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6117         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6118 }
6119
6120 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6121 {
6122         bnxt_unregister_fc_ctx_mem(bp);
6123
6124         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6125         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6126         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6127         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6128 }
6129
6130 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6131 {
6132         if (BNXT_FLOW_XSTATS_EN(bp))
6133                 bnxt_uninit_fc_ctx_mem(bp);
6134 }
6135
6136 static void
6137 bnxt_free_error_recovery_info(struct bnxt *bp)
6138 {
6139         rte_free(bp->recovery_info);
6140         bp->recovery_info = NULL;
6141         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6142 }
6143
6144 static void
6145 bnxt_uninit_locks(struct bnxt *bp)
6146 {
6147         pthread_mutex_destroy(&bp->flow_lock);
6148         pthread_mutex_destroy(&bp->def_cp_lock);
6149         pthread_mutex_destroy(&bp->health_check_lock);
6150         if (bp->rep_info) {
6151                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
6152                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
6153         }
6154 }
6155
6156 static int
6157 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6158 {
6159         int rc;
6160
6161         bnxt_free_int(bp);
6162         bnxt_free_mem(bp, reconfig_dev);
6163
6164         bnxt_hwrm_func_buf_unrgtr(bp);
6165         rte_free(bp->pf->vf_req_buf);
6166
6167         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
6168         bp->flags &= ~BNXT_FLAG_REGISTERED;
6169         bnxt_free_ctx_mem(bp);
6170         if (!reconfig_dev) {
6171                 bnxt_free_hwrm_resources(bp);
6172                 bnxt_free_error_recovery_info(bp);
6173         }
6174
6175         bnxt_uninit_ctx_mem(bp);
6176
6177         bnxt_uninit_locks(bp);
6178         bnxt_free_flow_stats_info(bp);
6179         bnxt_free_rep_info(bp);
6180         rte_free(bp->ptp_cfg);
6181         bp->ptp_cfg = NULL;
6182         return rc;
6183 }
6184
6185 static int
6186 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6187 {
6188         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6189                 return -EPERM;
6190
6191         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6192
6193         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6194                 bnxt_dev_close_op(eth_dev);
6195
6196         return 0;
6197 }
6198
6199 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6200 {
6201         struct bnxt *bp = eth_dev->data->dev_private;
6202         struct rte_eth_dev *vf_rep_eth_dev;
6203         int ret = 0, i;
6204
6205         if (!bp)
6206                 return -EINVAL;
6207
6208         for (i = 0; i < bp->num_reps; i++) {
6209                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6210                 if (!vf_rep_eth_dev)
6211                         continue;
6212                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6213                             vf_rep_eth_dev->data->port_id);
6214                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6215         }
6216         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6217                     eth_dev->data->port_id);
6218         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6219
6220         return ret;
6221 }
6222
6223 static void bnxt_free_rep_info(struct bnxt *bp)
6224 {
6225         rte_free(bp->rep_info);
6226         bp->rep_info = NULL;
6227         rte_free(bp->cfa_code_map);
6228         bp->cfa_code_map = NULL;
6229 }
6230
6231 static int bnxt_init_rep_info(struct bnxt *bp)
6232 {
6233         int i = 0, rc;
6234
6235         if (bp->rep_info)
6236                 return 0;
6237
6238         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6239                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6240                                    0);
6241         if (!bp->rep_info) {
6242                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6243                 return -ENOMEM;
6244         }
6245         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6246                                        sizeof(*bp->cfa_code_map) *
6247                                        BNXT_MAX_CFA_CODE, 0);
6248         if (!bp->cfa_code_map) {
6249                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6250                 bnxt_free_rep_info(bp);
6251                 return -ENOMEM;
6252         }
6253
6254         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6255                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6256
6257         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6258         if (rc) {
6259                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6260                 bnxt_free_rep_info(bp);
6261                 return rc;
6262         }
6263
6264         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6265         if (rc) {
6266                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6267                 bnxt_free_rep_info(bp);
6268                 return rc;
6269         }
6270
6271         return rc;
6272 }
6273
6274 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6275                                struct rte_eth_devargs eth_da,
6276                                struct rte_eth_dev *backing_eth_dev,
6277                                const char *dev_args)
6278 {
6279         struct rte_eth_dev *vf_rep_eth_dev;
6280         char name[RTE_ETH_NAME_MAX_LEN];
6281         struct bnxt *backing_bp;
6282         uint16_t num_rep;
6283         int i, ret = 0;
6284         struct rte_kvargs *kvlist;
6285
6286         num_rep = eth_da.nb_representor_ports;
6287         if (num_rep > BNXT_MAX_VF_REPS) {
6288                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6289                             num_rep, BNXT_MAX_VF_REPS);
6290                 return -EINVAL;
6291         }
6292
6293         if (num_rep >= RTE_MAX_ETHPORTS) {
6294                 PMD_DRV_LOG(ERR,
6295                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6296                             num_rep, RTE_MAX_ETHPORTS);
6297                 return -EINVAL;
6298         }
6299
6300         backing_bp = backing_eth_dev->data->dev_private;
6301
6302         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6303                 PMD_DRV_LOG(ERR,
6304                             "Not a PF or trusted VF. No Representor support\n");
6305                 /* Returning an error is not an option.
6306                  * Applications are not handling this correctly
6307                  */
6308                 return 0;
6309         }
6310
6311         if (bnxt_init_rep_info(backing_bp))
6312                 return 0;
6313
6314         for (i = 0; i < num_rep; i++) {
6315                 struct bnxt_representor representor = {
6316                         .vf_id = eth_da.representor_ports[i],
6317                         .switch_domain_id = backing_bp->switch_domain_id,
6318                         .parent_dev = backing_eth_dev
6319                 };
6320
6321                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6322                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6323                                     representor.vf_id, BNXT_MAX_VF_REPS);
6324                         continue;
6325                 }
6326
6327                 /* representor port net_bdf_port */
6328                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6329                          pci_dev->device.name, eth_da.representor_ports[i]);
6330
6331                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6332                 if (kvlist) {
6333                         /*
6334                          * Handler for "rep_is_pf" devarg.
6335                          * Invoked as for ex: "-w 000:00:0d.0,
6336                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6337                          */
6338                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6339                                            bnxt_parse_devarg_rep_is_pf,
6340                                            (void *)&representor);
6341                         /*
6342                          * Handler for "rep_based_pf" devarg.
6343                          * Invoked as for ex: "-w 000:00:0d.0,
6344                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6345                          */
6346                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_BASED_PF,
6347                                            bnxt_parse_devarg_rep_based_pf,
6348                                            (void *)&representor);
6349                         /*
6350                          * Handler for "rep_based_pf" devarg.
6351                          * Invoked as for ex: "-w 000:00:0d.0,
6352                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6353                          */
6354                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6355                                            bnxt_parse_devarg_rep_q_r2f,
6356                                            (void *)&representor);
6357                         /*
6358                          * Handler for "rep_based_pf" devarg.
6359                          * Invoked as for ex: "-w 000:00:0d.0,
6360                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6361                          */
6362                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6363                                            bnxt_parse_devarg_rep_q_f2r,
6364                                            (void *)&representor);
6365                         /*
6366                          * Handler for "rep_based_pf" devarg.
6367                          * Invoked as for ex: "-w 000:00:0d.0,
6368                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6369                          */
6370                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6371                                            bnxt_parse_devarg_rep_fc_r2f,
6372                                            (void *)&representor);
6373                         /*
6374                          * Handler for "rep_based_pf" devarg.
6375                          * Invoked as for ex: "-w 000:00:0d.0,
6376                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6377                          */
6378                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6379                                            bnxt_parse_devarg_rep_fc_f2r,
6380                                            (void *)&representor);
6381                 }
6382
6383                 ret = rte_eth_dev_create(&pci_dev->device, name,
6384                                          sizeof(struct bnxt_representor),
6385                                          NULL, NULL,
6386                                          bnxt_representor_init,
6387                                          &representor);
6388                 if (ret) {
6389                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6390                                     "representor %s.", name);
6391                         goto err;
6392                 }
6393
6394                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6395                 if (!vf_rep_eth_dev) {
6396                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6397                                     " for VF-Rep: %s.", name);
6398                         ret = -ENODEV;
6399                         goto err;
6400                 }
6401
6402                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6403                             backing_eth_dev->data->port_id);
6404                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6405                                                          vf_rep_eth_dev;
6406                 backing_bp->num_reps++;
6407
6408         }
6409
6410         return 0;
6411
6412 err:
6413         /* If num_rep > 1, then rollback already created
6414          * ports, since we'll be failing the probe anyway
6415          */
6416         if (num_rep > 1)
6417                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6418
6419         return ret;
6420 }
6421
6422 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6423                           struct rte_pci_device *pci_dev)
6424 {
6425         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6426         struct rte_eth_dev *backing_eth_dev;
6427         uint16_t num_rep;
6428         int ret = 0;
6429
6430         if (pci_dev->device.devargs) {
6431                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6432                                             &eth_da);
6433                 if (ret)
6434                         return ret;
6435         }
6436
6437         num_rep = eth_da.nb_representor_ports;
6438         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6439                     num_rep);
6440
6441         /* We could come here after first level of probe is already invoked
6442          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6443          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6444          */
6445         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6446         if (backing_eth_dev == NULL) {
6447                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6448                                          sizeof(struct bnxt),
6449                                          eth_dev_pci_specific_init, pci_dev,
6450                                          bnxt_dev_init, NULL);
6451
6452                 if (ret || !num_rep)
6453                         return ret;
6454
6455                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6456         }
6457         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6458                     backing_eth_dev->data->port_id);
6459
6460         if (!num_rep)
6461                 return ret;
6462
6463         /* probe representor ports now */
6464         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev,
6465                                   pci_dev->device.devargs->args);
6466
6467         return ret;
6468 }
6469
6470 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6471 {
6472         struct rte_eth_dev *eth_dev;
6473
6474         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6475         if (!eth_dev)
6476                 return 0; /* Invoked typically only by OVS-DPDK, by the
6477                            * time it comes here the eth_dev is already
6478                            * deleted by rte_eth_dev_close(), so returning
6479                            * +ve value will at least help in proper cleanup
6480                            */
6481
6482         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6483         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6484                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6485                         return rte_eth_dev_destroy(eth_dev,
6486                                                    bnxt_representor_uninit);
6487                 else
6488                         return rte_eth_dev_destroy(eth_dev,
6489                                                    bnxt_dev_uninit);
6490         } else {
6491                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6492         }
6493 }
6494
6495 static struct rte_pci_driver bnxt_rte_pmd = {
6496         .id_table = bnxt_pci_id_map,
6497         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6498                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6499                                                   * and OVS-DPDK
6500                                                   */
6501         .probe = bnxt_pci_probe,
6502         .remove = bnxt_pci_remove,
6503 };
6504
6505 static bool
6506 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6507 {
6508         if (strcmp(dev->device->driver->name, drv->driver.name))
6509                 return false;
6510
6511         return true;
6512 }
6513
6514 bool is_bnxt_supported(struct rte_eth_dev *dev)
6515 {
6516         return is_device_supported(dev, &bnxt_rte_pmd);
6517 }
6518
6519 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6520 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6521 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6522 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");