drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29 #include "bnxt_util.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  37
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  42 #define BROADCOM_DEV_ID_57301 0x16c8
  43 #define BROADCOM_DEV_ID_57302 0x16c9
  44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  47 #define BROADCOM_DEV_ID_NS2 0x16cd
  48 #define BROADCOM_DEV_ID_57311 0x16ce
  49 #define BROADCOM_DEV_ID_57312 0x16cf
  50 #define BROADCOM_DEV_ID_57402 0x16d0
  51 #define BROADCOM_DEV_ID_57404 0x16d1
  52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  56 #define BROADCOM_DEV_ID_57412 0x16d6
  57 #define BROADCOM_DEV_ID_57414 0x16d7
  58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  61 #define BROADCOM_DEV_ID_57412_MF 0x16de
  62 #define BROADCOM_DEV_ID_57314 0x16df
  63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  74 #define BROADCOM_DEV_ID_57508 0x1750
  75 #define BROADCOM_DEV_ID_57504 0x1751
  76 #define BROADCOM_DEV_ID_57502 0x1752
  77 #define BROADCOM_DEV_ID_57500_VF 0x1807
  78 #define BROADCOM_DEV_ID_58802 0xd802
  79 #define BROADCOM_DEV_ID_58804 0xd804
  80 #define BROADCOM_DEV_ID_58808 0x16f0
  81 #define BROADCOM_DEV_ID_58802_VF 0xd800
  82
  83 static const struct rte_pci_id bnxt_pci_id_map[] = {
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  85                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  87                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF) },
 130         { .vendor_id = 0, /* sentinel */ },
 131 };
 132
 133 #define BNXT_ETH_RSS_SUPPORT (  \
 134         ETH_RSS_IPV4 |          \
 135         ETH_RSS_NONFRAG_IPV4_TCP |      \
 136         ETH_RSS_NONFRAG_IPV4_UDP |      \
 137         ETH_RSS_IPV6 |          \
 138         ETH_RSS_NONFRAG_IPV6_TCP |      \
 139         ETH_RSS_NONFRAG_IPV6_UDP)
 140
 141 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 142                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 143                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 144                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 145                                      DEV_TX_OFFLOAD_TCP_TSO | \
 146                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 147                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 148                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 149                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 150                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 152
 153 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 154                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 155                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 156                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 157                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 158                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 159                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 160                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 161                                      DEV_RX_OFFLOAD_TCP_LRO)
 162
 163 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 164 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 165 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 166 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 167
 168 /***********************/
 169
 170 /*
 171  * High level utility functions
 172  */
 173
 174 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 175 {
 176         if (!BNXT_CHIP_THOR(bp))
 177                 return 1;
 178
 179         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 180                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 181                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 182 }
 183
 184 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 185 {
 186         if (!BNXT_CHIP_THOR(bp))
 187                 return HW_HASH_INDEX_SIZE;
 188
 189         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 190 }
 191
 192 static void bnxt_free_mem(struct bnxt *bp)
 193 {
 194         bnxt_free_filter_mem(bp);
 195         bnxt_free_vnic_attributes(bp);
 196         bnxt_free_vnic_mem(bp);
 197
 198         bnxt_free_stats(bp);
 199         bnxt_free_tx_rings(bp);
 200         bnxt_free_rx_rings(bp);
 201 }
 202
 203 static int bnxt_alloc_mem(struct bnxt *bp)
 204 {
 205         int rc;
 206
 207         rc = bnxt_alloc_vnic_mem(bp);
 208         if (rc)
 209                 goto alloc_mem_err;
 210
 211         rc = bnxt_alloc_vnic_attributes(bp);
 212         if (rc)
 213                 goto alloc_mem_err;
 214
 215         rc = bnxt_alloc_filter_mem(bp);
 216         if (rc)
 217                 goto alloc_mem_err;
 218
 219         return 0;
 220
 221 alloc_mem_err:
 222         bnxt_free_mem(bp);
 223         return rc;
 224 }
 225
 226 static int bnxt_init_chip(struct bnxt *bp)
 227 {
 228         struct bnxt_rx_queue *rxq;
 229         struct rte_eth_link new;
 230         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 231         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 232         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 233         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 234         uint32_t intr_vector = 0;
 235         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 236         uint32_t vec = BNXT_MISC_VEC_ID;
 237         unsigned int i, j;
 238         int rc;
 239
 240         /* disable uio/vfio intr/eventfd mapping */
 241         rte_intr_disable(intr_handle);
 242
 243         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 244                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 245                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 246                 bp->flags |= BNXT_FLAG_JUMBO;
 247         } else {
 248                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 249                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 250                 bp->flags &= ~BNXT_FLAG_JUMBO;
 251         }
 252
 253         /* THOR does not support ring groups.
 254          * But we will use the array to save RSS context IDs.
 255          */
 256         if (BNXT_CHIP_THOR(bp))
 257                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 258
 259         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 260         if (rc) {
 261                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 262                 goto err_out;
 263         }
 264
 265         rc = bnxt_alloc_hwrm_rings(bp);
 266         if (rc) {
 267                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 268                 goto err_out;
 269         }
 270
 271         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 272         if (rc) {
 273                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 274                 goto err_out;
 275         }
 276
 277         rc = bnxt_mq_rx_configure(bp);
 278         if (rc) {
 279                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 280                 goto err_out;
 281         }
 282
 283         /* VNIC configuration */
 284         for (i = 0; i < bp->nr_vnics; i++) {
 285                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 286                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 287                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 288
 289                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 290                 if (!vnic->fw_grp_ids) {
 291                         PMD_DRV_LOG(ERR,
 292                                     "Failed to alloc %d bytes for group ids\n",
 293                                     size);
 294                         rc = -ENOMEM;
 295                         goto err_out;
 296                 }
 297                 memset(vnic->fw_grp_ids, -1, size);
 298
 299                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 300                             i, vnic, vnic->fw_grp_ids);
 301
 302                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 303                 if (rc) {
 304                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 305                                 i, rc);
 306                         goto err_out;
 307                 }
 308
 309                 /* Alloc RSS context only if RSS mode is enabled */
 310                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 311                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 312
 313                         rc = 0;
 314                         for (j = 0; j < nr_ctxs; j++) {
 315                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 316                                 if (rc)
 317                                         break;
 318                         }
 319                         if (rc) {
 320                                 PMD_DRV_LOG(ERR,
 321                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 322                                   i, j, rc);
 323                                 goto err_out;
 324                         }
 325                         vnic->num_lb_ctxts = nr_ctxs;
 326                 }
 327
 328                 /*
 329                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 330                  * setting is not available at this time, it will not be
 331                  * configured correctly in the CFA.
 332                  */
 333                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 334                         vnic->vlan_strip = true;
 335                 else
 336                         vnic->vlan_strip = false;
 337
 338                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 339                 if (rc) {
 340                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 341                                 i, rc);
 342                         goto err_out;
 343                 }
 344
 345                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 346                 if (rc) {
 347                         PMD_DRV_LOG(ERR,
 348                                 "HWRM vnic %d filter failure rc: %x\n",
 349                                 i, rc);
 350                         goto err_out;
 351                 }
 352
 353                 for (j = 0; j < bp->rx_nr_rings; j++) {
 354                         rxq = bp->eth_dev->data->rx_queues[j];
 355
 356                         PMD_DRV_LOG(DEBUG,
 357                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 358                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 359
 360                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 361                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 362                 }
 363
 364                 rc = bnxt_vnic_rss_configure(bp, vnic);
 365                 if (rc) {
 366                         PMD_DRV_LOG(ERR,
 367                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 368                         goto err_out;
 369                 }
 370
 371                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 372
 373                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 374                     DEV_RX_OFFLOAD_TCP_LRO)
 375                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 376                 else
 377                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 378         }
 379         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 380         if (rc) {
 381                 PMD_DRV_LOG(ERR,
 382                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 383                 goto err_out;
 384         }
 385
 386         /* check and configure queue intr-vector mapping */
 387         if ((rte_intr_cap_multiple(intr_handle) ||
 388              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 389             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 390                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 391                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 392                 if (intr_vector > bp->rx_cp_nr_rings) {
 393                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 394                                         bp->rx_cp_nr_rings);
 395                         return -ENOTSUP;
 396                 }
 397                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 398                 if (rc)
 399                         return rc;
 400         }
 401
 402         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 403                 intr_handle->intr_vec =
 404                         rte_zmalloc("intr_vec",
 405                                     bp->eth_dev->data->nb_rx_queues *
 406                                     sizeof(int), 0);
 407                 if (intr_handle->intr_vec == NULL) {
 408                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 409                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 410                         rc = -ENOMEM;
 411                         goto err_disable;
 412                 }
 413                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 414                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 415                          intr_handle->intr_vec, intr_handle->nb_efd,
 416                         intr_handle->max_intr);
 417                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 418                      queue_id++) {
 419                         intr_handle->intr_vec[queue_id] = vec;
 420                         if (vec < base + intr_handle->nb_efd - 1)
 421                                 vec++;
 422                 }
 423         }
 424
 425         /* enable uio/vfio intr/eventfd mapping */
 426         rc = rte_intr_enable(intr_handle);
 427         if (rc)
 428                 goto err_free;
 429
 430         rc = bnxt_get_hwrm_link_config(bp, &new);
 431         if (rc) {
 432                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 433                 goto err_free;
 434         }
 435
 436         if (!bp->link_info.link_up) {
 437                 rc = bnxt_set_hwrm_link_config(bp, true);
 438                 if (rc) {
 439                         PMD_DRV_LOG(ERR,
 440                                 "HWRM link config failure rc: %x\n", rc);
 441                         goto err_free;
 442                 }
 443         }
 444         bnxt_print_link_info(bp->eth_dev);
 445
 446         return 0;
 447
 448 err_free:
 449         rte_free(intr_handle->intr_vec);
 450 err_disable:
 451         rte_intr_efd_disable(intr_handle);
 452 err_out:
 453         /* Some of the error status returned by FW may not be from errno.h */
 454         if (rc > 0)
 455                 rc = -EIO;
 456
 457         return rc;
 458 }
 459
 460 static int bnxt_shutdown_nic(struct bnxt *bp)
 461 {
 462         bnxt_free_all_hwrm_resources(bp);
 463         bnxt_free_all_filters(bp);
 464         bnxt_free_all_vnics(bp);
 465         return 0;
 466 }
 467
 468 static int bnxt_init_nic(struct bnxt *bp)
 469 {
 470         int rc;
 471
 472         if (BNXT_HAS_RING_GRPS(bp)) {
 473                 rc = bnxt_init_ring_grps(bp);
 474                 if (rc)
 475                         return rc;
 476         }
 477
 478         bnxt_init_vnics(bp);
 479         bnxt_init_filters(bp);
 480
 481         return 0;
 482 }
 483
 484 /*
 485  * Device configuration and status function
 486  */
 487
 488 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 489                                   struct rte_eth_dev_info *dev_info)
 490 {
 491         struct bnxt *bp = eth_dev->data->dev_private;
 492         uint16_t max_vnics, i, j, vpool, vrxq;
 493         unsigned int max_rx_rings;
 494
 495         /* MAC Specifics */
 496         dev_info->max_mac_addrs = bp->max_l2_ctx;
 497         dev_info->max_hash_mac_addrs = 0;
 498
 499         /* PF/VF specifics */
 500         if (BNXT_PF(bp))
 501                 dev_info->max_vfs = bp->pdev->max_vfs;
 502         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 503         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 504         dev_info->max_rx_queues = max_rx_rings;
 505         dev_info->max_tx_queues = max_rx_rings;
 506         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 507         dev_info->hash_key_size = 40;
 508         max_vnics = bp->max_vnics;
 509
 510         /* Fast path specifics */
 511         dev_info->min_rx_bufsize = 1;
 512         dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
 513                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
 514
 515         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 516         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 517                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 518         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 519         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 520
 521         /* *INDENT-OFF* */
 522         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 523                 .rx_thresh = {
 524                         .pthresh = 8,
 525                         .hthresh = 8,
 526                         .wthresh = 0,
 527                 },
 528                 .rx_free_thresh = 32,
 529                 /* If no descriptors available, pkts are dropped by default */
 530                 .rx_drop_en = 1,
 531         };
 532
 533         dev_info->default_txconf = (struct rte_eth_txconf) {
 534                 .tx_thresh = {
 535                         .pthresh = 32,
 536                         .hthresh = 0,
 537                         .wthresh = 0,
 538                 },
 539                 .tx_free_thresh = 32,
 540                 .tx_rs_thresh = 32,
 541         };
 542         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 543
 544         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 545         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 546         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 547         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 548         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 549
 550         /* *INDENT-ON* */
 551
 552         /*
 553          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 554          *       need further investigation.
 555          */
 556
 557         /* VMDq resources */
 558         vpool = 64; /* ETH_64_POOLS */
 559         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 560         for (i = 0; i < 4; vpool >>= 1, i++) {
 561                 if (max_vnics > vpool) {
 562                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 563                                 if (dev_info->max_rx_queues > vrxq) {
 564                                         if (vpool > vrxq)
 565                                                 vpool = vrxq;
 566                                         goto found;
 567                                 }
 568                         }
 569                         /* Not enough resources to support VMDq */
 570                         break;
 571                 }
 572         }
 573         /* Not enough resources to support VMDq */
 574         vpool = 0;
 575         vrxq = 0;
 576 found:
 577         dev_info->max_vmdq_pools = vpool;
 578         dev_info->vmdq_queue_num = vrxq;
 579
 580         dev_info->vmdq_pool_base = 0;
 581         dev_info->vmdq_queue_base = 0;
 582 }
 583
 584 /* Configure the device based on the configuration provided */
 585 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 586 {
 587         struct bnxt *bp = eth_dev->data->dev_private;
 588         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 589         int rc;
 590
 591         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 592         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 593         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 594         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 595
 596         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 597                 rc = bnxt_hwrm_check_vf_rings(bp);
 598                 if (rc) {
 599                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 600                         return -ENOSPC;
 601                 }
 602
 603                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 604                 if (rc) {
 605                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 606                         return -ENOSPC;
 607                 }
 608         } else {
 609                 /* legacy driver needs to get updated values */
 610                 rc = bnxt_hwrm_func_qcaps(bp);
 611                 if (rc) {
 612                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 613                         return rc;
 614                 }
 615         }
 616
 617         /* Inherit new configurations */
 618         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 619             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 620             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 621             bp->max_cp_rings ||
 622             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 623             bp->max_stat_ctx)
 624                 goto resource_error;
 625
 626         if (BNXT_HAS_RING_GRPS(bp) &&
 627             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 628                 goto resource_error;
 629
 630         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 631             bp->max_vnics < eth_dev->data->nb_rx_queues)
 632                 goto resource_error;
 633
 634         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 635         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 636
 637         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 638                 eth_dev->data->mtu =
 639                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 640                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 641                         BNXT_NUM_VLANS;
 642                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 643         }
 644         return 0;
 645
 646 resource_error:
 647         PMD_DRV_LOG(ERR,
 648                     "Insufficient resources to support requested config\n");
 649         PMD_DRV_LOG(ERR,
 650                     "Num Queues Requested: Tx %d, Rx %d\n",
 651                     eth_dev->data->nb_tx_queues,
 652                     eth_dev->data->nb_rx_queues);
 653         PMD_DRV_LOG(ERR,
 654                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 655                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 656                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 657         return -ENOSPC;
 658 }
 659
 660 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 661 {
 662         struct rte_eth_link *link = &eth_dev->data->dev_link;
 663
 664         if (link->link_status)
 665                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 666                         eth_dev->data->port_id,
 667                         (uint32_t)link->link_speed,
 668                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 669                         ("full-duplex") : ("half-duplex\n"));
 670         else
 671                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 672                         eth_dev->data->port_id);
 673 }
 674
 675 /*
 676  * Determine whether the current configuration requires support for scattered
 677  * receive; return 1 if scattered receive is required and 0 if not.
 678  */
 679 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 680 {
 681         uint16_t buf_size;
 682         int i;
 683
 684         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 685                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 686
 687                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 688                                       RTE_PKTMBUF_HEADROOM);
 689                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 690                         return 1;
 691         }
 692         return 0;
 693 }
 694
 695 static eth_rx_burst_t
 696 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 697 {
 698 #ifdef RTE_ARCH_X86
 699         /*
 700          * Vector mode receive can be enabled only if scatter rx is not
 701          * in use and rx offloads are limited to VLAN stripping and
 702          * CRC stripping.
 703          */
 704         if (!eth_dev->data->scattered_rx &&
 705             !(eth_dev->data->dev_conf.rxmode.offloads &
 706               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 707                 DEV_RX_OFFLOAD_KEEP_CRC |
 708                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 709                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 710                 DEV_RX_OFFLOAD_UDP_CKSUM |
 711                 DEV_RX_OFFLOAD_TCP_CKSUM |
 712                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 713                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 714                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 715                             eth_dev->data->port_id);
 716                 return bnxt_recv_pkts_vec;
 717         }
 718         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 719                     eth_dev->data->port_id);
 720         PMD_DRV_LOG(INFO,
 721                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 722                     eth_dev->data->port_id,
 723                     eth_dev->data->scattered_rx,
 724                     eth_dev->data->dev_conf.rxmode.offloads);
 725 #endif
 726         return bnxt_recv_pkts;
 727 }
 728
 729 static eth_tx_burst_t
 730 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 731 {
 732 #ifdef RTE_ARCH_X86
 733         /*
 734          * Vector mode receive can be enabled only if scatter tx is not
 735          * in use and tx offloads other than VLAN insertion are not
 736          * in use.
 737          */
 738         if (!eth_dev->data->scattered_rx &&
 739             !(eth_dev->data->dev_conf.txmode.offloads &
 740               ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
 741                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 742                             eth_dev->data->port_id);
 743                 return bnxt_xmit_pkts_vec;
 744         }
 745         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 746                     eth_dev->data->port_id);
 747         PMD_DRV_LOG(INFO,
 748                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 749                     eth_dev->data->port_id,
 750                     eth_dev->data->scattered_rx,
 751                     eth_dev->data->dev_conf.txmode.offloads);
 752 #endif
 753         return bnxt_xmit_pkts;
 754 }
 755
 756 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 757 {
 758         struct bnxt *bp = eth_dev->data->dev_private;
 759         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 760         int vlan_mask = 0;
 761         int rc;
 762
 763         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 764                 PMD_DRV_LOG(ERR,
 765                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 766                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 767         }
 768
 769         rc = bnxt_init_chip(bp);
 770         if (rc)
 771                 goto error;
 772
 773         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 774
 775         bnxt_link_update_op(eth_dev, 1);
 776
 777         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 778                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 779         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 780                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 781         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 782         if (rc)
 783                 goto error;
 784
 785         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 786         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 787         bnxt_enable_int(bp);
 788         bp->flags |= BNXT_FLAG_INIT_DONE;
 789         bp->dev_stopped = 0;
 790         return 0;
 791
 792 error:
 793         bnxt_shutdown_nic(bp);
 794         bnxt_free_tx_mbufs(bp);
 795         bnxt_free_rx_mbufs(bp);
 796         return rc;
 797 }
 798
 799 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 800 {
 801         struct bnxt *bp = eth_dev->data->dev_private;
 802         int rc = 0;
 803
 804         if (!bp->link_info.link_up)
 805                 rc = bnxt_set_hwrm_link_config(bp, true);
 806         if (!rc)
 807                 eth_dev->data->dev_link.link_status = 1;
 808
 809         bnxt_print_link_info(eth_dev);
 810         return 0;
 811 }
 812
 813 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 814 {
 815         struct bnxt *bp = eth_dev->data->dev_private;
 816
 817         eth_dev->data->dev_link.link_status = 0;
 818         bnxt_set_hwrm_link_config(bp, false);
 819         bp->link_info.link_up = 0;
 820
 821         return 0;
 822 }
 823
 824 /* Unload the driver, release resources */
 825 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 826 {
 827         struct bnxt *bp = eth_dev->data->dev_private;
 828         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 829         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 830
 831         bnxt_disable_int(bp);
 832
 833         /* disable uio/vfio intr/eventfd mapping */
 834         rte_intr_disable(intr_handle);
 835
 836         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 837         if (bp->eth_dev->data->dev_started) {
 838                 /* TBD: STOP HW queues DMA */
 839                 eth_dev->data->dev_link.link_status = 0;
 840         }
 841         bnxt_set_hwrm_link_config(bp, false);
 842
 843         /* Clean queue intr-vector mapping */
 844         rte_intr_efd_disable(intr_handle);
 845         if (intr_handle->intr_vec != NULL) {
 846                 rte_free(intr_handle->intr_vec);
 847                 intr_handle->intr_vec = NULL;
 848         }
 849
 850         bnxt_hwrm_port_clr_stats(bp);
 851         bnxt_free_tx_mbufs(bp);
 852         bnxt_free_rx_mbufs(bp);
 853         bnxt_shutdown_nic(bp);
 854         bp->dev_stopped = 1;
 855 }
 856
 857 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 858 {
 859         struct bnxt *bp = eth_dev->data->dev_private;
 860
 861         if (bp->dev_stopped == 0)
 862                 bnxt_dev_stop_op(eth_dev);
 863
 864         if (eth_dev->data->mac_addrs != NULL) {
 865                 rte_free(eth_dev->data->mac_addrs);
 866                 eth_dev->data->mac_addrs = NULL;
 867         }
 868         if (bp->grp_info != NULL) {
 869                 rte_free(bp->grp_info);
 870                 bp->grp_info = NULL;
 871         }
 872
 873         bnxt_dev_uninit(eth_dev);
 874 }
 875
 876 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 877                                     uint32_t index)
 878 {
 879         struct bnxt *bp = eth_dev->data->dev_private;
 880         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 881         struct bnxt_vnic_info *vnic;
 882         struct bnxt_filter_info *filter, *temp_filter;
 883         uint32_t i;
 884
 885         /*
 886          * Loop through all VNICs from the specified filter flow pools to
 887          * remove the corresponding MAC addr filter
 888          */
 889         for (i = 0; i < bp->nr_vnics; i++) {
 890                 if (!(pool_mask & (1ULL << i)))
 891                         continue;
 892
 893                 vnic = &bp->vnic_info[i];
 894                 filter = STAILQ_FIRST(&vnic->filter);
 895                 while (filter) {
 896                         temp_filter = STAILQ_NEXT(filter, next);
 897                         if (filter->mac_index == index) {
 898                                 STAILQ_REMOVE(&vnic->filter, filter,
 899                                                 bnxt_filter_info, next);
 900                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 901                                 filter->mac_index = INVALID_MAC_INDEX;
 902                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 903                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 904                                                    filter, next);
 905                         }
 906                         filter = temp_filter;
 907                 }
 908         }
 909 }
 910
 911 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 912                                 struct rte_ether_addr *mac_addr,
 913                                 uint32_t index, uint32_t pool)
 914 {
 915         struct bnxt *bp = eth_dev->data->dev_private;
 916         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
 917         struct bnxt_filter_info *filter;
 918         int rc = 0;
 919
 920         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
 921                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 922                 return -ENOTSUP;
 923         }
 924
 925         if (!vnic) {
 926                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 927                 return -EINVAL;
 928         }
 929         /* Attach requested MAC address to the new l2_filter */
 930         STAILQ_FOREACH(filter, &vnic->filter, next) {
 931                 if (filter->mac_index == index) {
 932                         PMD_DRV_LOG(ERR,
 933                                 "MAC addr already existed for pool %d\n", pool);
 934                         return 0;
 935                 }
 936         }
 937         filter = bnxt_alloc_filter(bp);
 938         if (!filter) {
 939                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 940                 return -ENODEV;
 941         }
 942
 943         filter->mac_index = index;
 944         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
 945
 946         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 947         if (!rc) {
 948                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 949         } else {
 950                 filter->mac_index = INVALID_MAC_INDEX;
 951                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 952                 bnxt_free_filter(bp, filter);
 953         }
 954
 955         return rc;
 956 }
 957
 958 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 959 {
 960         int rc = 0;
 961         struct bnxt *bp = eth_dev->data->dev_private;
 962         struct rte_eth_link new;
 963         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 964
 965         memset(&new, 0, sizeof(new));
 966         do {
 967                 /* Retrieve link info from hardware */
 968                 rc = bnxt_get_hwrm_link_config(bp, &new);
 969                 if (rc) {
 970                         new.link_speed = ETH_LINK_SPEED_100M;
 971                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 972                         PMD_DRV_LOG(ERR,
 973                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 974                         goto out;
 975                 }
 976
 977                 if (!wait_to_complete || new.link_status)
 978                         break;
 979
 980                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 981         } while (cnt--);
 982
 983 out:
 984         /* Timed out or success */
 985         if (new.link_status != eth_dev->data->dev_link.link_status ||
 986         new.link_speed != eth_dev->data->dev_link.link_speed) {
 987                 memcpy(&eth_dev->data->dev_link, &new,
 988                         sizeof(struct rte_eth_link));
 989
 990                 _rte_eth_dev_callback_process(eth_dev,
 991                                               RTE_ETH_EVENT_INTR_LSC,
 992                                               NULL);
 993
 994                 bnxt_print_link_info(eth_dev);
 995         }
 996
 997         return rc;
 998 }
 999
1000 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1001 {
1002         struct bnxt *bp = eth_dev->data->dev_private;
1003         struct bnxt_vnic_info *vnic;
1004
1005         if (bp->vnic_info == NULL)
1006                 return;
1007
1008         vnic = &bp->vnic_info[0];
1009
1010         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1011         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1012 }
1013
1014 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1015 {
1016         struct bnxt *bp = eth_dev->data->dev_private;
1017         struct bnxt_vnic_info *vnic;
1018
1019         if (bp->vnic_info == NULL)
1020                 return;
1021
1022         vnic = &bp->vnic_info[0];
1023
1024         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1025         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1026 }
1027
1028 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1029 {
1030         struct bnxt *bp = eth_dev->data->dev_private;
1031         struct bnxt_vnic_info *vnic;
1032
1033         if (bp->vnic_info == NULL)
1034                 return;
1035
1036         vnic = &bp->vnic_info[0];
1037
1038         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1039         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1040 }
1041
1042 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1043 {
1044         struct bnxt *bp = eth_dev->data->dev_private;
1045         struct bnxt_vnic_info *vnic;
1046
1047         if (bp->vnic_info == NULL)
1048                 return;
1049
1050         vnic = &bp->vnic_info[0];
1051
1052         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1053         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1054 }
1055
1056 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1057 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1058 {
1059         if (qid >= bp->rx_nr_rings)
1060                 return NULL;
1061
1062         return bp->eth_dev->data->rx_queues[qid];
1063 }
1064
1065 /* Return rxq corresponding to a given rss table ring/group ID. */
1066 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1067 {
1068         struct bnxt_rx_queue *rxq;
1069         unsigned int i;
1070
1071         if (!BNXT_HAS_RING_GRPS(bp)) {
1072                 for (i = 0; i < bp->rx_nr_rings; i++) {
1073                         rxq = bp->eth_dev->data->rx_queues[i];
1074                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1075                                 return rxq->index;
1076                 }
1077         } else {
1078                 for (i = 0; i < bp->rx_nr_rings; i++) {
1079                         if (bp->grp_info[i].fw_grp_id == fwr)
1080                                 return i;
1081                 }
1082         }
1083
1084         return INVALID_HW_RING_ID;
1085 }
1086
1087 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1088                             struct rte_eth_rss_reta_entry64 *reta_conf,
1089                             uint16_t reta_size)
1090 {
1091         struct bnxt *bp = eth_dev->data->dev_private;
1092         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1093         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1094         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1095         uint16_t idx, sft;
1096         int i;
1097
1098         if (!vnic->rss_table)
1099                 return -EINVAL;
1100
1101         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1102                 return -EINVAL;
1103
1104         if (reta_size != tbl_size) {
1105                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1106                         "(%d) must equal the size supported by the hardware "
1107                         "(%d)\n", reta_size, tbl_size);
1108                 return -EINVAL;
1109         }
1110
1111         for (i = 0; i < reta_size; i++) {
1112                 struct bnxt_rx_queue *rxq;
1113
1114                 idx = i / RTE_RETA_GROUP_SIZE;
1115                 sft = i % RTE_RETA_GROUP_SIZE;
1116
1117                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1118                         continue;
1119
1120                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1121                 if (!rxq) {
1122                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1123                         return -EINVAL;
1124                 }
1125
1126                 if (BNXT_CHIP_THOR(bp)) {
1127                         vnic->rss_table[i * 2] =
1128                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1129                         vnic->rss_table[i * 2 + 1] =
1130                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1131                 } else {
1132                         vnic->rss_table[i] =
1133                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1134                 }
1135
1136                 vnic->rss_table[i] =
1137                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1138         }
1139
1140         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1141         return 0;
1142 }
1143
1144 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1145                               struct rte_eth_rss_reta_entry64 *reta_conf,
1146                               uint16_t reta_size)
1147 {
1148         struct bnxt *bp = eth_dev->data->dev_private;
1149         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1150         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1151         uint16_t idx, sft, i;
1152
1153         /* Retrieve from the default VNIC */
1154         if (!vnic)
1155                 return -EINVAL;
1156         if (!vnic->rss_table)
1157                 return -EINVAL;
1158
1159         if (reta_size != tbl_size) {
1160                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1161                         "(%d) must equal the size supported by the hardware "
1162                         "(%d)\n", reta_size, tbl_size);
1163                 return -EINVAL;
1164         }
1165
1166         for (idx = 0, i = 0; i < reta_size; i++) {
1167                 idx = i / RTE_RETA_GROUP_SIZE;
1168                 sft = i % RTE_RETA_GROUP_SIZE;
1169
1170                 if (reta_conf[idx].mask & (1ULL << sft)) {
1171                         uint16_t qid;
1172
1173                         if (BNXT_CHIP_THOR(bp))
1174                                 qid = bnxt_rss_to_qid(bp,
1175                                                       vnic->rss_table[i * 2]);
1176                         else
1177                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1178
1179                         if (qid == INVALID_HW_RING_ID) {
1180                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1181                                 return -EINVAL;
1182                         }
1183                         reta_conf[idx].reta[sft] = qid;
1184                 }
1185         }
1186
1187         return 0;
1188 }
1189
1190 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1191                                    struct rte_eth_rss_conf *rss_conf)
1192 {
1193         struct bnxt *bp = eth_dev->data->dev_private;
1194         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1195         struct bnxt_vnic_info *vnic;
1196         uint16_t hash_type = 0;
1197         unsigned int i;
1198
1199         /*
1200          * If RSS enablement were different than dev_configure,
1201          * then return -EINVAL
1202          */
1203         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1204                 if (!rss_conf->rss_hf)
1205                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1206         } else {
1207                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1208                         return -EINVAL;
1209         }
1210
1211         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1212         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1213
1214         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1215                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1216         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1217                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1218         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1219                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1220         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1221                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1222         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1223                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1224         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1225                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1226
1227         /* Update the RSS VNIC(s) */
1228         for (i = 0; i < bp->nr_vnics; i++) {
1229                 vnic = &bp->vnic_info[i];
1230                 vnic->hash_type = hash_type;
1231
1232                 /*
1233                  * Use the supplied key if the key length is
1234                  * acceptable and the rss_key is not NULL
1235                  */
1236                 if (rss_conf->rss_key &&
1237                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1238                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1239                                rss_conf->rss_key_len);
1240
1241                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1242         }
1243         return 0;
1244 }
1245
1246 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1247                                      struct rte_eth_rss_conf *rss_conf)
1248 {
1249         struct bnxt *bp = eth_dev->data->dev_private;
1250         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1251         int len;
1252         uint32_t hash_types;
1253
1254         /* RSS configuration is the same for all VNICs */
1255         if (vnic && vnic->rss_hash_key) {
1256                 if (rss_conf->rss_key) {
1257                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1258                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1259                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1260                 }
1261
1262                 hash_types = vnic->hash_type;
1263                 rss_conf->rss_hf = 0;
1264                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1265                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1266                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1267                 }
1268                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1269                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1270                         hash_types &=
1271                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1272                 }
1273                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1274                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1275                         hash_types &=
1276                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1277                 }
1278                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1279                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1280                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1281                 }
1282                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1283                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1284                         hash_types &=
1285                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1286                 }
1287                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1288                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1289                         hash_types &=
1290                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1291                 }
1292                 if (hash_types) {
1293                         PMD_DRV_LOG(ERR,
1294                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1295                                 vnic->hash_type);
1296                         return -ENOTSUP;
1297                 }
1298         } else {
1299                 rss_conf->rss_hf = 0;
1300         }
1301         return 0;
1302 }
1303
1304 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1305                                struct rte_eth_fc_conf *fc_conf)
1306 {
1307         struct bnxt *bp = dev->data->dev_private;
1308         struct rte_eth_link link_info;
1309         int rc;
1310
1311         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1312         if (rc)
1313                 return rc;
1314
1315         memset(fc_conf, 0, sizeof(*fc_conf));
1316         if (bp->link_info.auto_pause)
1317                 fc_conf->autoneg = 1;
1318         switch (bp->link_info.pause) {
1319         case 0:
1320                 fc_conf->mode = RTE_FC_NONE;
1321                 break;
1322         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1323                 fc_conf->mode = RTE_FC_TX_PAUSE;
1324                 break;
1325         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1326                 fc_conf->mode = RTE_FC_RX_PAUSE;
1327                 break;
1328         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1329                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1330                 fc_conf->mode = RTE_FC_FULL;
1331                 break;
1332         }
1333         return 0;
1334 }
1335
1336 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1337                                struct rte_eth_fc_conf *fc_conf)
1338 {
1339         struct bnxt *bp = dev->data->dev_private;
1340
1341         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1342                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1343                 return -ENOTSUP;
1344         }
1345
1346         switch (fc_conf->mode) {
1347         case RTE_FC_NONE:
1348                 bp->link_info.auto_pause = 0;
1349                 bp->link_info.force_pause = 0;
1350                 break;
1351         case RTE_FC_RX_PAUSE:
1352                 if (fc_conf->autoneg) {
1353                         bp->link_info.auto_pause =
1354                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1355                         bp->link_info.force_pause = 0;
1356                 } else {
1357                         bp->link_info.auto_pause = 0;
1358                         bp->link_info.force_pause =
1359                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1360                 }
1361                 break;
1362         case RTE_FC_TX_PAUSE:
1363                 if (fc_conf->autoneg) {
1364                         bp->link_info.auto_pause =
1365                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1366                         bp->link_info.force_pause = 0;
1367                 } else {
1368                         bp->link_info.auto_pause = 0;
1369                         bp->link_info.force_pause =
1370                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1371                 }
1372                 break;
1373         case RTE_FC_FULL:
1374                 if (fc_conf->autoneg) {
1375                         bp->link_info.auto_pause =
1376                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1377                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1378                         bp->link_info.force_pause = 0;
1379                 } else {
1380                         bp->link_info.auto_pause = 0;
1381                         bp->link_info.force_pause =
1382                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1383                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1384                 }
1385                 break;
1386         }
1387         return bnxt_set_hwrm_link_config(bp, true);
1388 }
1389
1390 /* Add UDP tunneling port */
1391 static int
1392 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1393                          struct rte_eth_udp_tunnel *udp_tunnel)
1394 {
1395         struct bnxt *bp = eth_dev->data->dev_private;
1396         uint16_t tunnel_type = 0;
1397         int rc = 0;
1398
1399         switch (udp_tunnel->prot_type) {
1400         case RTE_TUNNEL_TYPE_VXLAN:
1401                 if (bp->vxlan_port_cnt) {
1402                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1403                                 udp_tunnel->udp_port);
1404                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1405                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1406                                 return -ENOSPC;
1407                         }
1408                         bp->vxlan_port_cnt++;
1409                         return 0;
1410                 }
1411                 tunnel_type =
1412                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1413                 bp->vxlan_port_cnt++;
1414                 break;
1415         case RTE_TUNNEL_TYPE_GENEVE:
1416                 if (bp->geneve_port_cnt) {
1417                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1418                                 udp_tunnel->udp_port);
1419                         if (bp->geneve_port != udp_tunnel->udp_port) {
1420                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1421                                 return -ENOSPC;
1422                         }
1423                         bp->geneve_port_cnt++;
1424                         return 0;
1425                 }
1426                 tunnel_type =
1427                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1428                 bp->geneve_port_cnt++;
1429                 break;
1430         default:
1431                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1432                 return -ENOTSUP;
1433         }
1434         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1435                                              tunnel_type);
1436         return rc;
1437 }
1438
1439 static int
1440 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1441                          struct rte_eth_udp_tunnel *udp_tunnel)
1442 {
1443         struct bnxt *bp = eth_dev->data->dev_private;
1444         uint16_t tunnel_type = 0;
1445         uint16_t port = 0;
1446         int rc = 0;
1447
1448         switch (udp_tunnel->prot_type) {
1449         case RTE_TUNNEL_TYPE_VXLAN:
1450                 if (!bp->vxlan_port_cnt) {
1451                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1452                         return -EINVAL;
1453                 }
1454                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1455                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1456                                 udp_tunnel->udp_port, bp->vxlan_port);
1457                         return -EINVAL;
1458                 }
1459                 if (--bp->vxlan_port_cnt)
1460                         return 0;
1461
1462                 tunnel_type =
1463                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1464                 port = bp->vxlan_fw_dst_port_id;
1465                 break;
1466         case RTE_TUNNEL_TYPE_GENEVE:
1467                 if (!bp->geneve_port_cnt) {
1468                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1469                         return -EINVAL;
1470                 }
1471                 if (bp->geneve_port != udp_tunnel->udp_port) {
1472                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1473                                 udp_tunnel->udp_port, bp->geneve_port);
1474                         return -EINVAL;
1475                 }
1476                 if (--bp->geneve_port_cnt)
1477                         return 0;
1478
1479                 tunnel_type =
1480                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1481                 port = bp->geneve_fw_dst_port_id;
1482                 break;
1483         default:
1484                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1485                 return -ENOTSUP;
1486         }
1487
1488         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1489         if (!rc) {
1490                 if (tunnel_type ==
1491                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1492                         bp->vxlan_port = 0;
1493                 if (tunnel_type ==
1494                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1495                         bp->geneve_port = 0;
1496         }
1497         return rc;
1498 }
1499
1500 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1501 {
1502         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1503         struct bnxt_vnic_info *vnic;
1504         unsigned int i;
1505         int rc = 0;
1506         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1507
1508         /* Cycle through all VNICs */
1509         for (i = 0; i < bp->nr_vnics; i++) {
1510                 /*
1511                  * For each VNIC and each associated filter(s)
1512                  * if VLAN exists && VLAN matches vlan_id
1513                  *      remove the MAC+VLAN filter
1514                  *      add a new MAC only filter
1515                  * else
1516                  *      VLAN filter doesn't exist, just skip and continue
1517                  */
1518                 vnic = &bp->vnic_info[i];
1519                 filter = STAILQ_FIRST(&vnic->filter);
1520                 while (filter) {
1521                         temp_filter = STAILQ_NEXT(filter, next);
1522
1523                         if (filter->enables & chk &&
1524                             filter->l2_ovlan == vlan_id) {
1525                                 /* Must delete the filter */
1526                                 STAILQ_REMOVE(&vnic->filter, filter,
1527                                               bnxt_filter_info, next);
1528                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1529                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1530                                                    filter, next);
1531
1532                                 /*
1533                                  * Need to examine to see if the MAC
1534                                  * filter already existed or not before
1535                                  * allocating a new one
1536                                  */
1537
1538                                 new_filter = bnxt_alloc_filter(bp);
1539                                 if (!new_filter) {
1540                                         PMD_DRV_LOG(ERR,
1541                                                         "MAC/VLAN filter alloc failed\n");
1542                                         rc = -ENOMEM;
1543                                         goto exit;
1544                                 }
1545                                 STAILQ_INSERT_TAIL(&vnic->filter,
1546                                                 new_filter, next);
1547                                 /* Inherit MAC from previous filter */
1548                                 new_filter->mac_index =
1549                                         filter->mac_index;
1550                                 memcpy(new_filter->l2_addr, filter->l2_addr,
1551                                        RTE_ETHER_ADDR_LEN);
1552                                 /* MAC only filter */
1553                                 rc = bnxt_hwrm_set_l2_filter(bp,
1554                                                              vnic->fw_vnic_id,
1555                                                              new_filter);
1556                                 if (rc)
1557                                         goto exit;
1558                                 PMD_DRV_LOG(INFO,
1559                                             "Del Vlan filter for %d\n",
1560                                             vlan_id);
1561                         }
1562                         filter = temp_filter;
1563                 }
1564         }
1565 exit:
1566         return rc;
1567 }
1568
1569 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1570 {
1571         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1572         struct bnxt_vnic_info *vnic;
1573         unsigned int i;
1574         int rc = 0;
1575         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1576                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1577         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1578
1579         /* Cycle through all VNICs */
1580         for (i = 0; i < bp->nr_vnics; i++) {
1581                 /*
1582                  * For each VNIC and each associated filter(s)
1583                  * if VLAN exists:
1584                  *   if VLAN matches vlan_id
1585                  *      VLAN filter already exists, just skip and continue
1586                  *   else
1587                  *      add a new MAC+VLAN filter
1588                  * else
1589                  *   Remove the old MAC only filter
1590                  *    Add a new MAC+VLAN filter
1591                  */
1592                 vnic = &bp->vnic_info[i];
1593                 filter = STAILQ_FIRST(&vnic->filter);
1594                 while (filter) {
1595                         temp_filter = STAILQ_NEXT(filter, next);
1596
1597                         if (filter->enables & chk) {
1598                                 if (filter->l2_ivlan == vlan_id)
1599                                         goto cont;
1600                         } else {
1601                                 /* Must delete the MAC filter */
1602                                 STAILQ_REMOVE(&vnic->filter, filter,
1603                                                 bnxt_filter_info, next);
1604                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1605                                 filter->l2_ovlan = 0;
1606                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1607                                                    filter, next);
1608                         }
1609                         new_filter = bnxt_alloc_filter(bp);
1610                         if (!new_filter) {
1611                                 PMD_DRV_LOG(ERR,
1612                                                 "MAC/VLAN filter alloc failed\n");
1613                                 rc = -ENOMEM;
1614                                 goto exit;
1615                         }
1616                         STAILQ_INSERT_TAIL(&vnic->filter, new_filter, next);
1617                         /* Inherit MAC from the previous filter */
1618                         new_filter->mac_index = filter->mac_index;
1619                         memcpy(new_filter->l2_addr, filter->l2_addr,
1620                                RTE_ETHER_ADDR_LEN);
1621                         /* MAC + VLAN ID filter */
1622                         new_filter->l2_ivlan = vlan_id;
1623                         new_filter->l2_ivlan_mask = 0xF000;
1624                         new_filter->enables |= en;
1625                         rc = bnxt_hwrm_set_l2_filter(bp,
1626                                         vnic->fw_vnic_id,
1627                                         new_filter);
1628                         if (rc)
1629                                 goto exit;
1630                         PMD_DRV_LOG(INFO,
1631                                     "Added Vlan filter for %d\n", vlan_id);
1632 cont:
1633                         filter = temp_filter;
1634                 }
1635         }
1636 exit:
1637         return rc;
1638 }
1639
1640 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1641                 uint16_t vlan_id, int on)
1642 {
1643         struct bnxt *bp = eth_dev->data->dev_private;
1644
1645         /* These operations apply to ALL existing MAC/VLAN filters */
1646         if (on)
1647                 return bnxt_add_vlan_filter(bp, vlan_id);
1648         else
1649                 return bnxt_del_vlan_filter(bp, vlan_id);
1650 }
1651
1652 static int
1653 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1654 {
1655         struct bnxt *bp = dev->data->dev_private;
1656         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1657         unsigned int i;
1658
1659         if (mask & ETH_VLAN_FILTER_MASK) {
1660                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1661                         /* Remove any VLAN filters programmed */
1662                         for (i = 0; i < 4095; i++)
1663                                 bnxt_del_vlan_filter(bp, i);
1664                 }
1665                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1666                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1667         }
1668
1669         if (mask & ETH_VLAN_STRIP_MASK) {
1670                 /* Enable or disable VLAN stripping */
1671                 for (i = 0; i < bp->nr_vnics; i++) {
1672                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1673                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1674                                 vnic->vlan_strip = true;
1675                         else
1676                                 vnic->vlan_strip = false;
1677                         bnxt_hwrm_vnic_cfg(bp, vnic);
1678                 }
1679                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1680                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1681         }
1682
1683         if (mask & ETH_VLAN_EXTEND_MASK)
1684                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1685
1686         return 0;
1687 }
1688
1689 static int
1690 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1691                         struct rte_ether_addr *addr)
1692 {
1693         struct bnxt *bp = dev->data->dev_private;
1694         /* Default Filter is tied to VNIC 0 */
1695         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1696         struct bnxt_filter_info *filter;
1697         int rc;
1698
1699         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1700                 return -EPERM;
1701
1702         if (rte_is_zero_ether_addr(addr))
1703                 return -EINVAL;
1704
1705         STAILQ_FOREACH(filter, &vnic->filter, next) {
1706                 /* Default Filter is at Index 0 */
1707                 if (filter->mac_index != 0)
1708                         continue;
1709
1710                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1711                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1712                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1713                 filter->enables |=
1714                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1715                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1716
1717                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1718                 if (rc)
1719                         return rc;
1720
1721                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1722                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1723                 return 0;
1724         }
1725
1726         return 0;
1727 }
1728
1729 static int
1730 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1731                           struct rte_ether_addr *mc_addr_set,
1732                           uint32_t nb_mc_addr)
1733 {
1734         struct bnxt *bp = eth_dev->data->dev_private;
1735         char *mc_addr_list = (char *)mc_addr_set;
1736         struct bnxt_vnic_info *vnic;
1737         uint32_t off = 0, i = 0;
1738
1739         vnic = &bp->vnic_info[0];
1740
1741         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1742                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1743                 goto allmulti;
1744         }
1745
1746         /* TODO Check for Duplicate mcast addresses */
1747         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1748         for (i = 0; i < nb_mc_addr; i++) {
1749                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1750                         RTE_ETHER_ADDR_LEN);
1751                 off += RTE_ETHER_ADDR_LEN;
1752         }
1753
1754         vnic->mc_addr_cnt = i;
1755
1756 allmulti:
1757         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1758 }
1759
1760 static int
1761 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1762 {
1763         struct bnxt *bp = dev->data->dev_private;
1764         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1765         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1766         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1767         int ret;
1768
1769         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1770                         fw_major, fw_minor, fw_updt);
1771
1772         ret += 1; /* add the size of '\0' */
1773         if (fw_size < (uint32_t)ret)
1774                 return ret;
1775         else
1776                 return 0;
1777 }
1778
1779 static void
1780 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1781         struct rte_eth_rxq_info *qinfo)
1782 {
1783         struct bnxt_rx_queue *rxq;
1784
1785         rxq = dev->data->rx_queues[queue_id];
1786
1787         qinfo->mp = rxq->mb_pool;
1788         qinfo->scattered_rx = dev->data->scattered_rx;
1789         qinfo->nb_desc = rxq->nb_rx_desc;
1790
1791         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1792         qinfo->conf.rx_drop_en = 0;
1793         qinfo->conf.rx_deferred_start = 0;
1794 }
1795
1796 static void
1797 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1798         struct rte_eth_txq_info *qinfo)
1799 {
1800         struct bnxt_tx_queue *txq;
1801
1802         txq = dev->data->tx_queues[queue_id];
1803
1804         qinfo->nb_desc = txq->nb_tx_desc;
1805
1806         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1807         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1808         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1809
1810         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1811         qinfo->conf.tx_rs_thresh = 0;
1812         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1813 }
1814
1815 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1816 {
1817         struct bnxt *bp = eth_dev->data->dev_private;
1818         struct rte_eth_dev_info dev_info;
1819         uint32_t new_pkt_size;
1820         uint32_t rc = 0;
1821         uint32_t i;
1822
1823         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1824                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1825
1826         bnxt_dev_info_get_op(eth_dev, &dev_info);
1827
1828         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1829                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1830                         RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1831                 return -EINVAL;
1832         }
1833
1834 #ifdef RTE_ARCH_X86
1835         /*
1836          * If vector-mode tx/rx is active, disallow any MTU change that would
1837          * require scattered receive support.
1838          */
1839         if (eth_dev->data->dev_started &&
1840             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1841              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1842             (new_pkt_size >
1843              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1844                 PMD_DRV_LOG(ERR,
1845                             "MTU change would require scattered rx support. ");
1846                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1847                 return -EINVAL;
1848         }
1849 #endif
1850
1851         if (new_mtu > RTE_ETHER_MTU) {
1852                 bp->flags |= BNXT_FLAG_JUMBO;
1853                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1854                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1855         } else {
1856                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1857                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1858                 bp->flags &= ~BNXT_FLAG_JUMBO;
1859         }
1860
1861         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1862
1863         eth_dev->data->mtu = new_mtu;
1864         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1865
1866         for (i = 0; i < bp->nr_vnics; i++) {
1867                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1868                 uint16_t size = 0;
1869
1870                 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1871                                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1872                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1873                 if (rc)
1874                         break;
1875
1876                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1877                 size -= RTE_PKTMBUF_HEADROOM;
1878
1879                 if (size < new_mtu) {
1880                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1881                         if (rc)
1882                                 return rc;
1883                 }
1884         }
1885
1886         return rc;
1887 }
1888
1889 static int
1890 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1891 {
1892         struct bnxt *bp = dev->data->dev_private;
1893         uint16_t vlan = bp->vlan;
1894         int rc;
1895
1896         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1897                 PMD_DRV_LOG(ERR,
1898                         "PVID cannot be modified for this function\n");
1899                 return -ENOTSUP;
1900         }
1901         bp->vlan = on ? pvid : 0;
1902
1903         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1904         if (rc)
1905                 bp->vlan = vlan;
1906         return rc;
1907 }
1908
1909 static int
1910 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1911 {
1912         struct bnxt *bp = dev->data->dev_private;
1913
1914         return bnxt_hwrm_port_led_cfg(bp, true);
1915 }
1916
1917 static int
1918 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1919 {
1920         struct bnxt *bp = dev->data->dev_private;
1921
1922         return bnxt_hwrm_port_led_cfg(bp, false);
1923 }
1924
1925 static uint32_t
1926 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1927 {
1928         uint32_t desc = 0, raw_cons = 0, cons;
1929         struct bnxt_cp_ring_info *cpr;
1930         struct bnxt_rx_queue *rxq;
1931         struct rx_pkt_cmpl *rxcmp;
1932         uint16_t cmp_type;
1933         uint8_t cmp = 1;
1934         bool valid;
1935
1936         rxq = dev->data->rx_queues[rx_queue_id];
1937         cpr = rxq->cp_ring;
1938         valid = cpr->valid;
1939
1940         while (raw_cons < rxq->nb_rx_desc) {
1941                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1942                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1943
1944                 if (!CMPL_VALID(rxcmp, valid))
1945                         goto nothing_to_do;
1946                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1947                 cmp_type = CMP_TYPE(rxcmp);
1948                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1949                         cmp = (rte_le_to_cpu_32(
1950                                         ((struct rx_tpa_end_cmpl *)
1951                                          (rxcmp))->agg_bufs_v1) &
1952                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1953                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1954                         desc++;
1955                 } else if (cmp_type == 0x11) {
1956                         desc++;
1957                         cmp = (rxcmp->agg_bufs_v1 &
1958                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1959                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1960                 } else {
1961                         cmp = 1;
1962                 }
1963 nothing_to_do:
1964                 raw_cons += cmp ? cmp : 2;
1965         }
1966
1967         return desc;
1968 }
1969
1970 static int
1971 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1972 {
1973         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1974         struct bnxt_rx_ring_info *rxr;
1975         struct bnxt_cp_ring_info *cpr;
1976         struct bnxt_sw_rx_bd *rx_buf;
1977         struct rx_pkt_cmpl *rxcmp;
1978         uint32_t cons, cp_cons;
1979
1980         if (!rxq)
1981                 return -EINVAL;
1982
1983         cpr = rxq->cp_ring;
1984         rxr = rxq->rx_ring;
1985
1986         if (offset >= rxq->nb_rx_desc)
1987                 return -EINVAL;
1988
1989         cons = RING_CMP(cpr->cp_ring_struct, offset);
1990         cp_cons = cpr->cp_raw_cons;
1991         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1992
1993         if (cons > cp_cons) {
1994                 if (CMPL_VALID(rxcmp, cpr->valid))
1995                         return RTE_ETH_RX_DESC_DONE;
1996         } else {
1997                 if (CMPL_VALID(rxcmp, !cpr->valid))
1998                         return RTE_ETH_RX_DESC_DONE;
1999         }
2000         rx_buf = &rxr->rx_buf_ring[cons];
2001         if (rx_buf->mbuf == NULL)
2002                 return RTE_ETH_RX_DESC_UNAVAIL;
2003
2004
2005         return RTE_ETH_RX_DESC_AVAIL;
2006 }
2007
2008 static int
2009 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2010 {
2011         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2012         struct bnxt_tx_ring_info *txr;
2013         struct bnxt_cp_ring_info *cpr;
2014         struct bnxt_sw_tx_bd *tx_buf;
2015         struct tx_pkt_cmpl *txcmp;
2016         uint32_t cons, cp_cons;
2017
2018         if (!txq)
2019                 return -EINVAL;
2020
2021         cpr = txq->cp_ring;
2022         txr = txq->tx_ring;
2023
2024         if (offset >= txq->nb_tx_desc)
2025                 return -EINVAL;
2026
2027         cons = RING_CMP(cpr->cp_ring_struct, offset);
2028         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2029         cp_cons = cpr->cp_raw_cons;
2030
2031         if (cons > cp_cons) {
2032                 if (CMPL_VALID(txcmp, cpr->valid))
2033                         return RTE_ETH_TX_DESC_UNAVAIL;
2034         } else {
2035                 if (CMPL_VALID(txcmp, !cpr->valid))
2036                         return RTE_ETH_TX_DESC_UNAVAIL;
2037         }
2038         tx_buf = &txr->tx_buf_ring[cons];
2039         if (tx_buf->mbuf == NULL)
2040                 return RTE_ETH_TX_DESC_DONE;
2041
2042         return RTE_ETH_TX_DESC_FULL;
2043 }
2044
2045 static struct bnxt_filter_info *
2046 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2047                                 struct rte_eth_ethertype_filter *efilter,
2048                                 struct bnxt_vnic_info *vnic0,
2049                                 struct bnxt_vnic_info *vnic,
2050                                 int *ret)
2051 {
2052         struct bnxt_filter_info *mfilter = NULL;
2053         int match = 0;
2054         *ret = 0;
2055
2056         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2057                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2058                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2059                         " ethertype filter.", efilter->ether_type);
2060                 *ret = -EINVAL;
2061                 goto exit;
2062         }
2063         if (efilter->queue >= bp->rx_nr_rings) {
2064                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2065                 *ret = -EINVAL;
2066                 goto exit;
2067         }
2068
2069         vnic0 = &bp->vnic_info[0];
2070         vnic = &bp->vnic_info[efilter->queue];
2071         if (vnic == NULL) {
2072                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2073                 *ret = -EINVAL;
2074                 goto exit;
2075         }
2076
2077         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2078                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2079                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2080                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2081                              mfilter->flags ==
2082                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2083                              mfilter->ethertype == efilter->ether_type)) {
2084                                 match = 1;
2085                                 break;
2086                         }
2087                 }
2088         } else {
2089                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2090                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2091                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2092                              mfilter->ethertype == efilter->ether_type &&
2093                              mfilter->flags ==
2094                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2095                                 match = 1;
2096                                 break;
2097                         }
2098         }
2099
2100         if (match)
2101                 *ret = -EEXIST;
2102
2103 exit:
2104         return mfilter;
2105 }
2106
2107 static int
2108 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2109                         enum rte_filter_op filter_op,
2110                         void *arg)
2111 {
2112         struct bnxt *bp = dev->data->dev_private;
2113         struct rte_eth_ethertype_filter *efilter =
2114                         (struct rte_eth_ethertype_filter *)arg;
2115         struct bnxt_filter_info *bfilter, *filter1;
2116         struct bnxt_vnic_info *vnic, *vnic0;
2117         int ret;
2118
2119         if (filter_op == RTE_ETH_FILTER_NOP)
2120                 return 0;
2121
2122         if (arg == NULL) {
2123                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2124                             filter_op);
2125                 return -EINVAL;
2126         }
2127
2128         vnic0 = &bp->vnic_info[0];
2129         vnic = &bp->vnic_info[efilter->queue];
2130
2131         switch (filter_op) {
2132         case RTE_ETH_FILTER_ADD:
2133                 bnxt_match_and_validate_ether_filter(bp, efilter,
2134                                                         vnic0, vnic, &ret);
2135                 if (ret < 0)
2136                         return ret;
2137
2138                 bfilter = bnxt_get_unused_filter(bp);
2139                 if (bfilter == NULL) {
2140                         PMD_DRV_LOG(ERR,
2141                                 "Not enough resources for a new filter.\n");
2142                         return -ENOMEM;
2143                 }
2144                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2145                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2146                        RTE_ETHER_ADDR_LEN);
2147                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2148                        RTE_ETHER_ADDR_LEN);
2149                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2150                 bfilter->ethertype = efilter->ether_type;
2151                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2152
2153                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2154                 if (filter1 == NULL) {
2155                         ret = -1;
2156                         goto cleanup;
2157                 }
2158                 bfilter->enables |=
2159                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2160                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2161
2162                 bfilter->dst_id = vnic->fw_vnic_id;
2163
2164                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2165                         bfilter->flags =
2166                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2167                 }
2168
2169                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2170                 if (ret)
2171                         goto cleanup;
2172                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2173                 break;
2174         case RTE_ETH_FILTER_DELETE:
2175                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2176                                                         vnic0, vnic, &ret);
2177                 if (ret == -EEXIST) {
2178                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2179
2180                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2181                                       next);
2182                         bnxt_free_filter(bp, filter1);
2183                 } else if (ret == 0) {
2184                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2185                 }
2186                 break;
2187         default:
2188                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2189                 ret = -EINVAL;
2190                 goto error;
2191         }
2192         return ret;
2193 cleanup:
2194         bnxt_free_filter(bp, bfilter);
2195 error:
2196         return ret;
2197 }
2198
2199 static inline int
2200 parse_ntuple_filter(struct bnxt *bp,
2201                     struct rte_eth_ntuple_filter *nfilter,
2202                     struct bnxt_filter_info *bfilter)
2203 {
2204         uint32_t en = 0;
2205
2206         if (nfilter->queue >= bp->rx_nr_rings) {
2207                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2208                 return -EINVAL;
2209         }
2210
2211         switch (nfilter->dst_port_mask) {
2212         case UINT16_MAX:
2213                 bfilter->dst_port_mask = -1;
2214                 bfilter->dst_port = nfilter->dst_port;
2215                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2216                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2217                 break;
2218         default:
2219                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2220                 return -EINVAL;
2221         }
2222
2223         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2224         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2225
2226         switch (nfilter->proto_mask) {
2227         case UINT8_MAX:
2228                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2229                         bfilter->ip_protocol = 17;
2230                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2231                         bfilter->ip_protocol = 6;
2232                 else
2233                         return -EINVAL;
2234                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2235                 break;
2236         default:
2237                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2238                 return -EINVAL;
2239         }
2240
2241         switch (nfilter->dst_ip_mask) {
2242         case UINT32_MAX:
2243                 bfilter->dst_ipaddr_mask[0] = -1;
2244                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2245                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2246                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2247                 break;
2248         default:
2249                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2250                 return -EINVAL;
2251         }
2252
2253         switch (nfilter->src_ip_mask) {
2254         case UINT32_MAX:
2255                 bfilter->src_ipaddr_mask[0] = -1;
2256                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2257                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2258                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2259                 break;
2260         default:
2261                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2262                 return -EINVAL;
2263         }
2264
2265         switch (nfilter->src_port_mask) {
2266         case UINT16_MAX:
2267                 bfilter->src_port_mask = -1;
2268                 bfilter->src_port = nfilter->src_port;
2269                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2270                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2271                 break;
2272         default:
2273                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2274                 return -EINVAL;
2275         }
2276
2277         //TODO Priority
2278         //nfilter->priority = (uint8_t)filter->priority;
2279
2280         bfilter->enables = en;
2281         return 0;
2282 }
2283
2284 static struct bnxt_filter_info*
2285 bnxt_match_ntuple_filter(struct bnxt *bp,
2286                          struct bnxt_filter_info *bfilter,
2287                          struct bnxt_vnic_info **mvnic)
2288 {
2289         struct bnxt_filter_info *mfilter = NULL;
2290         int i;
2291
2292         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2293                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2294                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2295                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2296                             bfilter->src_ipaddr_mask[0] ==
2297                             mfilter->src_ipaddr_mask[0] &&
2298                             bfilter->src_port == mfilter->src_port &&
2299                             bfilter->src_port_mask == mfilter->src_port_mask &&
2300                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2301                             bfilter->dst_ipaddr_mask[0] ==
2302                             mfilter->dst_ipaddr_mask[0] &&
2303                             bfilter->dst_port == mfilter->dst_port &&
2304                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2305                             bfilter->flags == mfilter->flags &&
2306                             bfilter->enables == mfilter->enables) {
2307                                 if (mvnic)
2308                                         *mvnic = vnic;
2309                                 return mfilter;
2310                         }
2311                 }
2312         }
2313         return NULL;
2314 }
2315
2316 static int
2317 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2318                        struct rte_eth_ntuple_filter *nfilter,
2319                        enum rte_filter_op filter_op)
2320 {
2321         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2322         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2323         int ret;
2324
2325         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2326                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2327                 return -EINVAL;
2328         }
2329
2330         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2331                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2332                 return -EINVAL;
2333         }
2334
2335         bfilter = bnxt_get_unused_filter(bp);
2336         if (bfilter == NULL) {
2337                 PMD_DRV_LOG(ERR,
2338                         "Not enough resources for a new filter.\n");
2339                 return -ENOMEM;
2340         }
2341         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2342         if (ret < 0)
2343                 goto free_filter;
2344
2345         vnic = &bp->vnic_info[nfilter->queue];
2346         vnic0 = &bp->vnic_info[0];
2347         filter1 = STAILQ_FIRST(&vnic0->filter);
2348         if (filter1 == NULL) {
2349                 ret = -1;
2350                 goto free_filter;
2351         }
2352
2353         bfilter->dst_id = vnic->fw_vnic_id;
2354         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2355         bfilter->enables |=
2356                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2357         bfilter->ethertype = 0x800;
2358         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2359
2360         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2361
2362         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2363             bfilter->dst_id == mfilter->dst_id) {
2364                 PMD_DRV_LOG(ERR, "filter exists.\n");
2365                 ret = -EEXIST;
2366                 goto free_filter;
2367         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2368                    bfilter->dst_id != mfilter->dst_id) {
2369                 mfilter->dst_id = vnic->fw_vnic_id;
2370                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2371                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2372                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2373                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2374                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2375                 goto free_filter;
2376         }
2377         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2378                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2379                 ret = -ENOENT;
2380                 goto free_filter;
2381         }
2382
2383         if (filter_op == RTE_ETH_FILTER_ADD) {
2384                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2385                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2386                 if (ret)
2387                         goto free_filter;
2388                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2389         } else {
2390                 if (mfilter == NULL) {
2391                         /* This should not happen. But for Coverity! */
2392                         ret = -ENOENT;
2393                         goto free_filter;
2394                 }
2395                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2396
2397                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2398                 bnxt_free_filter(bp, mfilter);
2399                 mfilter->fw_l2_filter_id = -1;
2400                 bnxt_free_filter(bp, bfilter);
2401                 bfilter->fw_l2_filter_id = -1;
2402         }
2403
2404         return 0;
2405 free_filter:
2406         bfilter->fw_l2_filter_id = -1;
2407         bnxt_free_filter(bp, bfilter);
2408         return ret;
2409 }
2410
2411 static int
2412 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2413                         enum rte_filter_op filter_op,
2414                         void *arg)
2415 {
2416         struct bnxt *bp = dev->data->dev_private;
2417         int ret;
2418
2419         if (filter_op == RTE_ETH_FILTER_NOP)
2420                 return 0;
2421
2422         if (arg == NULL) {
2423                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2424                             filter_op);
2425                 return -EINVAL;
2426         }
2427
2428         switch (filter_op) {
2429         case RTE_ETH_FILTER_ADD:
2430                 ret = bnxt_cfg_ntuple_filter(bp,
2431                         (struct rte_eth_ntuple_filter *)arg,
2432                         filter_op);
2433                 break;
2434         case RTE_ETH_FILTER_DELETE:
2435                 ret = bnxt_cfg_ntuple_filter(bp,
2436                         (struct rte_eth_ntuple_filter *)arg,
2437                         filter_op);
2438                 break;
2439         default:
2440                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2441                 ret = -EINVAL;
2442                 break;
2443         }
2444         return ret;
2445 }
2446
2447 static int
2448 bnxt_parse_fdir_filter(struct bnxt *bp,
2449                        struct rte_eth_fdir_filter *fdir,
2450                        struct bnxt_filter_info *filter)
2451 {
2452         enum rte_fdir_mode fdir_mode =
2453                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2454         struct bnxt_vnic_info *vnic0, *vnic;
2455         struct bnxt_filter_info *filter1;
2456         uint32_t en = 0;
2457         int i;
2458
2459         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2460                 return -EINVAL;
2461
2462         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2463         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2464
2465         switch (fdir->input.flow_type) {
2466         case RTE_ETH_FLOW_IPV4:
2467         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2468                 /* FALLTHROUGH */
2469                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2470                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2471                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2472                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2473                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2474                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2475                 filter->ip_addr_type =
2476                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2477                 filter->src_ipaddr_mask[0] = 0xffffffff;
2478                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2479                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2480                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2481                 filter->ethertype = 0x800;
2482                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2483                 break;
2484         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2485                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2486                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2487                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2488                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2489                 filter->dst_port_mask = 0xffff;
2490                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2491                 filter->src_port_mask = 0xffff;
2492                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2493                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2494                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2495                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2496                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2497                 filter->ip_protocol = 6;
2498                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2499                 filter->ip_addr_type =
2500                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2501                 filter->src_ipaddr_mask[0] = 0xffffffff;
2502                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2503                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2504                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2505                 filter->ethertype = 0x800;
2506                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2507                 break;
2508         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2509                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2510                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2511                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2512                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2513                 filter->dst_port_mask = 0xffff;
2514                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2515                 filter->src_port_mask = 0xffff;
2516                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2517                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2518                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2519                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2520                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2521                 filter->ip_protocol = 17;
2522                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2523                 filter->ip_addr_type =
2524                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2525                 filter->src_ipaddr_mask[0] = 0xffffffff;
2526                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2527                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2528                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2529                 filter->ethertype = 0x800;
2530                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2531                 break;
2532         case RTE_ETH_FLOW_IPV6:
2533         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2534                 /* FALLTHROUGH */
2535                 filter->ip_addr_type =
2536                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2537                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2538                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2539                 rte_memcpy(filter->src_ipaddr,
2540                            fdir->input.flow.ipv6_flow.src_ip, 16);
2541                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2542                 rte_memcpy(filter->dst_ipaddr,
2543                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2544                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2545                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2546                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2547                 memset(filter->src_ipaddr_mask, 0xff, 16);
2548                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2549                 filter->ethertype = 0x86dd;
2550                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2551                 break;
2552         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2553                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2554                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2555                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2556                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2557                 filter->dst_port_mask = 0xffff;
2558                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2559                 filter->src_port_mask = 0xffff;
2560                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2561                 filter->ip_addr_type =
2562                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2563                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2564                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2565                 rte_memcpy(filter->src_ipaddr,
2566                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2567                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2568                 rte_memcpy(filter->dst_ipaddr,
2569                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2570                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2571                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2572                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2573                 memset(filter->src_ipaddr_mask, 0xff, 16);
2574                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2575                 filter->ethertype = 0x86dd;
2576                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2577                 break;
2578         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2579                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2580                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2581                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2582                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2583                 filter->dst_port_mask = 0xffff;
2584                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2585                 filter->src_port_mask = 0xffff;
2586                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2587                 filter->ip_addr_type =
2588                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2589                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2590                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2591                 rte_memcpy(filter->src_ipaddr,
2592                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2593                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2594                 rte_memcpy(filter->dst_ipaddr,
2595                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2596                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2597                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2598                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2599                 memset(filter->src_ipaddr_mask, 0xff, 16);
2600                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2601                 filter->ethertype = 0x86dd;
2602                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2603                 break;
2604         case RTE_ETH_FLOW_L2_PAYLOAD:
2605                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2606                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2607                 break;
2608         case RTE_ETH_FLOW_VXLAN:
2609                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2610                         return -EINVAL;
2611                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2612                 filter->tunnel_type =
2613                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2614                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2615                 break;
2616         case RTE_ETH_FLOW_NVGRE:
2617                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2618                         return -EINVAL;
2619                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2620                 filter->tunnel_type =
2621                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2622                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2623                 break;
2624         case RTE_ETH_FLOW_UNKNOWN:
2625         case RTE_ETH_FLOW_RAW:
2626         case RTE_ETH_FLOW_FRAG_IPV4:
2627         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2628         case RTE_ETH_FLOW_FRAG_IPV6:
2629         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2630         case RTE_ETH_FLOW_IPV6_EX:
2631         case RTE_ETH_FLOW_IPV6_TCP_EX:
2632         case RTE_ETH_FLOW_IPV6_UDP_EX:
2633         case RTE_ETH_FLOW_GENEVE:
2634                 /* FALLTHROUGH */
2635         default:
2636                 return -EINVAL;
2637         }
2638
2639         vnic0 = &bp->vnic_info[0];
2640         vnic = &bp->vnic_info[fdir->action.rx_queue];
2641         if (vnic == NULL) {
2642                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2643                 return -EINVAL;
2644         }
2645
2646
2647         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2648                 rte_memcpy(filter->dst_macaddr,
2649                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2650                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2651         }
2652
2653         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2654                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2655                 filter1 = STAILQ_FIRST(&vnic0->filter);
2656                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2657         } else {
2658                 filter->dst_id = vnic->fw_vnic_id;
2659                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2660                         if (filter->dst_macaddr[i] == 0x00)
2661                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2662                         else
2663                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2664         }
2665
2666         if (filter1 == NULL)
2667                 return -EINVAL;
2668
2669         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2670         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2671
2672         filter->enables = en;
2673
2674         return 0;
2675 }
2676
2677 static struct bnxt_filter_info *
2678 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2679                 struct bnxt_vnic_info **mvnic)
2680 {
2681         struct bnxt_filter_info *mf = NULL;
2682         int i;
2683
2684         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2685                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2686
2687                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2688                         if (mf->filter_type == nf->filter_type &&
2689                             mf->flags == nf->flags &&
2690                             mf->src_port == nf->src_port &&
2691                             mf->src_port_mask == nf->src_port_mask &&
2692                             mf->dst_port == nf->dst_port &&
2693                             mf->dst_port_mask == nf->dst_port_mask &&
2694                             mf->ip_protocol == nf->ip_protocol &&
2695                             mf->ip_addr_type == nf->ip_addr_type &&
2696                             mf->ethertype == nf->ethertype &&
2697                             mf->vni == nf->vni &&
2698                             mf->tunnel_type == nf->tunnel_type &&
2699                             mf->l2_ovlan == nf->l2_ovlan &&
2700                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2701                             mf->l2_ivlan == nf->l2_ivlan &&
2702                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2703                             !memcmp(mf->l2_addr, nf->l2_addr,
2704                                     RTE_ETHER_ADDR_LEN) &&
2705                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2706                                     RTE_ETHER_ADDR_LEN) &&
2707                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2708                                     RTE_ETHER_ADDR_LEN) &&
2709                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2710                                     RTE_ETHER_ADDR_LEN) &&
2711                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2712                                     sizeof(nf->src_ipaddr)) &&
2713                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2714                                     sizeof(nf->src_ipaddr_mask)) &&
2715                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2716                                     sizeof(nf->dst_ipaddr)) &&
2717                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2718                                     sizeof(nf->dst_ipaddr_mask))) {
2719                                 if (mvnic)
2720                                         *mvnic = vnic;
2721                                 return mf;
2722                         }
2723                 }
2724         }
2725         return NULL;
2726 }
2727
2728 static int
2729 bnxt_fdir_filter(struct rte_eth_dev *dev,
2730                  enum rte_filter_op filter_op,
2731                  void *arg)
2732 {
2733         struct bnxt *bp = dev->data->dev_private;
2734         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2735         struct bnxt_filter_info *filter, *match;
2736         struct bnxt_vnic_info *vnic, *mvnic;
2737         int ret = 0, i;
2738
2739         if (filter_op == RTE_ETH_FILTER_NOP)
2740                 return 0;
2741
2742         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2743                 return -EINVAL;
2744
2745         switch (filter_op) {
2746         case RTE_ETH_FILTER_ADD:
2747         case RTE_ETH_FILTER_DELETE:
2748                 /* FALLTHROUGH */
2749                 filter = bnxt_get_unused_filter(bp);
2750                 if (filter == NULL) {
2751                         PMD_DRV_LOG(ERR,
2752                                 "Not enough resources for a new flow.\n");
2753                         return -ENOMEM;
2754                 }
2755
2756                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2757                 if (ret != 0)
2758                         goto free_filter;
2759                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2760
2761                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2762                         vnic = &bp->vnic_info[0];
2763                 else
2764                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2765
2766                 match = bnxt_match_fdir(bp, filter, &mvnic);
2767                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2768                         if (match->dst_id == vnic->fw_vnic_id) {
2769                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2770                                 ret = -EEXIST;
2771                                 goto free_filter;
2772                         } else {
2773                                 match->dst_id = vnic->fw_vnic_id;
2774                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2775                                                                   match->dst_id,
2776                                                                   match);
2777                                 STAILQ_REMOVE(&mvnic->filter, match,
2778                                               bnxt_filter_info, next);
2779                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2780                                 PMD_DRV_LOG(ERR,
2781                                         "Filter with matching pattern exist\n");
2782                                 PMD_DRV_LOG(ERR,
2783                                         "Updated it to new destination q\n");
2784                                 goto free_filter;
2785                         }
2786                 }
2787                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2788                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2789                         ret = -ENOENT;
2790                         goto free_filter;
2791                 }
2792
2793                 if (filter_op == RTE_ETH_FILTER_ADD) {
2794                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2795                                                           filter->dst_id,
2796                                                           filter);
2797                         if (ret)
2798                                 goto free_filter;
2799                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2800                 } else {
2801                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2802                         STAILQ_REMOVE(&vnic->filter, match,
2803                                       bnxt_filter_info, next);
2804                         bnxt_free_filter(bp, match);
2805                         filter->fw_l2_filter_id = -1;
2806                         bnxt_free_filter(bp, filter);
2807                 }
2808                 break;
2809         case RTE_ETH_FILTER_FLUSH:
2810                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2811                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2812
2813                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2814                                 if (filter->filter_type ==
2815                                     HWRM_CFA_NTUPLE_FILTER) {
2816                                         ret =
2817                                         bnxt_hwrm_clear_ntuple_filter(bp,
2818                                                                       filter);
2819                                         STAILQ_REMOVE(&vnic->filter, filter,
2820                                                       bnxt_filter_info, next);
2821                                 }
2822                         }
2823                 }
2824                 return ret;
2825         case RTE_ETH_FILTER_UPDATE:
2826         case RTE_ETH_FILTER_STATS:
2827         case RTE_ETH_FILTER_INFO:
2828                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2829                 break;
2830         default:
2831                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2832                 ret = -EINVAL;
2833                 break;
2834         }
2835         return ret;
2836
2837 free_filter:
2838         filter->fw_l2_filter_id = -1;
2839         bnxt_free_filter(bp, filter);
2840         return ret;
2841 }
2842
2843 static int
2844 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2845                     enum rte_filter_type filter_type,
2846                     enum rte_filter_op filter_op, void *arg)
2847 {
2848         int ret = 0;
2849
2850         switch (filter_type) {
2851         case RTE_ETH_FILTER_TUNNEL:
2852                 PMD_DRV_LOG(ERR,
2853                         "filter type: %d: To be implemented\n", filter_type);
2854                 break;
2855         case RTE_ETH_FILTER_FDIR:
2856                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2857                 break;
2858         case RTE_ETH_FILTER_NTUPLE:
2859                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2860                 break;
2861         case RTE_ETH_FILTER_ETHERTYPE:
2862                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2863                 break;
2864         case RTE_ETH_FILTER_GENERIC:
2865                 if (filter_op != RTE_ETH_FILTER_GET)
2866                         return -EINVAL;
2867                 *(const void **)arg = &bnxt_flow_ops;
2868                 break;
2869         default:
2870                 PMD_DRV_LOG(ERR,
2871                         "Filter type (%d) not supported", filter_type);
2872                 ret = -EINVAL;
2873                 break;
2874         }
2875         return ret;
2876 }
2877
2878 static const uint32_t *
2879 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2880 {
2881         static const uint32_t ptypes[] = {
2882                 RTE_PTYPE_L2_ETHER_VLAN,
2883                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2884                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2885                 RTE_PTYPE_L4_ICMP,
2886                 RTE_PTYPE_L4_TCP,
2887                 RTE_PTYPE_L4_UDP,
2888                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2889                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2890                 RTE_PTYPE_INNER_L4_ICMP,
2891                 RTE_PTYPE_INNER_L4_TCP,
2892                 RTE_PTYPE_INNER_L4_UDP,
2893                 RTE_PTYPE_UNKNOWN
2894         };
2895
2896         if (!dev->rx_pkt_burst)
2897                 return NULL;
2898
2899         return ptypes;
2900 }
2901
2902 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2903                          int reg_win)
2904 {
2905         uint32_t reg_base = *reg_arr & 0xfffff000;
2906         uint32_t win_off;
2907         int i;
2908
2909         for (i = 0; i < count; i++) {
2910                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2911                         return -ERANGE;
2912         }
2913         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2914         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2915         return 0;
2916 }
2917
2918 static int bnxt_map_ptp_regs(struct bnxt *bp)
2919 {
2920         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2921         uint32_t *reg_arr;
2922         int rc, i;
2923
2924         reg_arr = ptp->rx_regs;
2925         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2926         if (rc)
2927                 return rc;
2928
2929         reg_arr = ptp->tx_regs;
2930         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2931         if (rc)
2932                 return rc;
2933
2934         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2935                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2936
2937         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2938                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2939
2940         return 0;
2941 }
2942
2943 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2944 {
2945         rte_write32(0, (uint8_t *)bp->bar0 +
2946                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2947         rte_write32(0, (uint8_t *)bp->bar0 +
2948                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2949 }
2950
2951 static uint64_t bnxt_cc_read(struct bnxt *bp)
2952 {
2953         uint64_t ns;
2954
2955         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2956                               BNXT_GRCPF_REG_SYNC_TIME));
2957         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2958                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2959         return ns;
2960 }
2961
2962 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2963 {
2964         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2965         uint32_t fifo;
2966
2967         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2968                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2969         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2970                 return -EAGAIN;
2971
2972         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2973                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2974         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2975                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2976         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2977                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2978
2979         return 0;
2980 }
2981
2982 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2983 {
2984         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2985         struct bnxt_pf_info *pf = &bp->pf;
2986         uint16_t port_id;
2987         uint32_t fifo;
2988
2989         if (!ptp)
2990                 return -ENODEV;
2991
2992         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2993                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2994         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2995                 return -EAGAIN;
2996
2997         port_id = pf->port_id;
2998         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2999                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3000
3001         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3002                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3003         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3004 /*              bnxt_clr_rx_ts(bp);       TBD  */
3005                 return -EBUSY;
3006         }
3007
3008         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3009                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3010         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3011                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3012
3013         return 0;
3014 }
3015
3016 static int
3017 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3018 {
3019         uint64_t ns;
3020         struct bnxt *bp = dev->data->dev_private;
3021         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3022
3023         if (!ptp)
3024                 return 0;
3025
3026         ns = rte_timespec_to_ns(ts);
3027         /* Set the timecounters to a new value. */
3028         ptp->tc.nsec = ns;
3029
3030         return 0;
3031 }
3032
3033 static int
3034 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3035 {
3036         uint64_t ns, systime_cycles;
3037         struct bnxt *bp = dev->data->dev_private;
3038         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3039
3040         if (!ptp)
3041                 return 0;
3042
3043         systime_cycles = bnxt_cc_read(bp);
3044         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3045         *ts = rte_ns_to_timespec(ns);
3046
3047         return 0;
3048 }
3049 static int
3050 bnxt_timesync_enable(struct rte_eth_dev *dev)
3051 {
3052         struct bnxt *bp = dev->data->dev_private;
3053         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3054         uint32_t shift = 0;
3055
3056         if (!ptp)
3057                 return 0;
3058
3059         ptp->rx_filter = 1;
3060         ptp->tx_tstamp_en = 1;
3061         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3062
3063         if (!bnxt_hwrm_ptp_cfg(bp))
3064                 bnxt_map_ptp_regs(bp);
3065
3066         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3067         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3068         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3069
3070         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3071         ptp->tc.cc_shift = shift;
3072         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3073
3074         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3075         ptp->rx_tstamp_tc.cc_shift = shift;
3076         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3077
3078         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3079         ptp->tx_tstamp_tc.cc_shift = shift;
3080         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3081
3082         return 0;
3083 }
3084
3085 static int
3086 bnxt_timesync_disable(struct rte_eth_dev *dev)
3087 {
3088         struct bnxt *bp = dev->data->dev_private;
3089         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3090
3091         if (!ptp)
3092                 return 0;
3093
3094         ptp->rx_filter = 0;
3095         ptp->tx_tstamp_en = 0;
3096         ptp->rxctl = 0;
3097
3098         bnxt_hwrm_ptp_cfg(bp);
3099
3100         bnxt_unmap_ptp_regs(bp);
3101
3102         return 0;
3103 }
3104
3105 static int
3106 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3107                                  struct timespec *timestamp,
3108                                  uint32_t flags __rte_unused)
3109 {
3110         struct bnxt *bp = dev->data->dev_private;
3111         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3112         uint64_t rx_tstamp_cycles = 0;
3113         uint64_t ns;
3114
3115         if (!ptp)
3116                 return 0;
3117
3118         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3119         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3120         *timestamp = rte_ns_to_timespec(ns);
3121         return  0;
3122 }
3123
3124 static int
3125 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3126                                  struct timespec *timestamp)
3127 {
3128         struct bnxt *bp = dev->data->dev_private;
3129         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3130         uint64_t tx_tstamp_cycles = 0;
3131         uint64_t ns;
3132
3133         if (!ptp)
3134                 return 0;
3135
3136         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3137         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3138         *timestamp = rte_ns_to_timespec(ns);
3139
3140         return 0;
3141 }
3142
3143 static int
3144 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3145 {
3146         struct bnxt *bp = dev->data->dev_private;
3147         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3148
3149         if (!ptp)
3150                 return 0;
3151
3152         ptp->tc.nsec += delta;
3153
3154         return 0;
3155 }
3156
3157 static int
3158 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3159 {
3160         struct bnxt *bp = dev->data->dev_private;
3161         int rc;
3162         uint32_t dir_entries;
3163         uint32_t entry_length;
3164
3165         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3166                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3167                 bp->pdev->addr.devid, bp->pdev->addr.function);
3168
3169         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3170         if (rc != 0)
3171                 return rc;
3172
3173         return dir_entries * entry_length;
3174 }
3175
3176 static int
3177 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3178                 struct rte_dev_eeprom_info *in_eeprom)
3179 {
3180         struct bnxt *bp = dev->data->dev_private;
3181         uint32_t index;
3182         uint32_t offset;
3183
3184         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3185                 "len = %d\n", bp->pdev->addr.domain,
3186                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3187                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3188
3189         if (in_eeprom->offset == 0) /* special offset value to get directory */
3190                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3191                                                 in_eeprom->data);
3192
3193         index = in_eeprom->offset >> 24;
3194         offset = in_eeprom->offset & 0xffffff;
3195
3196         if (index != 0)
3197                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3198                                            in_eeprom->length, in_eeprom->data);
3199
3200         return 0;
3201 }
3202
3203 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3204 {
3205         switch (dir_type) {
3206         case BNX_DIR_TYPE_CHIMP_PATCH:
3207         case BNX_DIR_TYPE_BOOTCODE:
3208         case BNX_DIR_TYPE_BOOTCODE_2:
3209         case BNX_DIR_TYPE_APE_FW:
3210         case BNX_DIR_TYPE_APE_PATCH:
3211         case BNX_DIR_TYPE_KONG_FW:
3212         case BNX_DIR_TYPE_KONG_PATCH:
3213         case BNX_DIR_TYPE_BONO_FW:
3214         case BNX_DIR_TYPE_BONO_PATCH:
3215                 /* FALLTHROUGH */
3216                 return true;
3217         }
3218
3219         return false;
3220 }
3221
3222 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3223 {
3224         switch (dir_type) {
3225         case BNX_DIR_TYPE_AVS:
3226         case BNX_DIR_TYPE_EXP_ROM_MBA:
3227         case BNX_DIR_TYPE_PCIE:
3228         case BNX_DIR_TYPE_TSCF_UCODE:
3229         case BNX_DIR_TYPE_EXT_PHY:
3230         case BNX_DIR_TYPE_CCM:
3231         case BNX_DIR_TYPE_ISCSI_BOOT:
3232         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3233         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3234                 /* FALLTHROUGH */
3235                 return true;
3236         }
3237
3238         return false;
3239 }
3240
3241 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3242 {
3243         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3244                 bnxt_dir_type_is_other_exec_format(dir_type);
3245 }
3246
3247 static int
3248 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3249                 struct rte_dev_eeprom_info *in_eeprom)
3250 {
3251         struct bnxt *bp = dev->data->dev_private;
3252         uint8_t index, dir_op;
3253         uint16_t type, ext, ordinal, attr;
3254
3255         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3256                 "len = %d\n", bp->pdev->addr.domain,
3257                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3258                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3259
3260         if (!BNXT_PF(bp)) {
3261                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3262                 return -EINVAL;
3263         }
3264
3265         type = in_eeprom->magic >> 16;
3266
3267         if (type == 0xffff) { /* special value for directory operations */
3268                 index = in_eeprom->magic & 0xff;
3269                 dir_op = in_eeprom->magic >> 8;
3270                 if (index == 0)
3271                         return -EINVAL;
3272                 switch (dir_op) {
3273                 case 0x0e: /* erase */
3274                         if (in_eeprom->offset != ~in_eeprom->magic)
3275                                 return -EINVAL;
3276                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3277                 default:
3278                         return -EINVAL;
3279                 }
3280         }
3281
3282         /* Create or re-write an NVM item: */
3283         if (bnxt_dir_type_is_executable(type) == true)
3284                 return -EOPNOTSUPP;
3285         ext = in_eeprom->magic & 0xffff;
3286         ordinal = in_eeprom->offset >> 16;
3287         attr = in_eeprom->offset & 0xffff;
3288
3289         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3290                                      in_eeprom->data, in_eeprom->length);
3291         return 0;
3292 }
3293
3294 /*
3295  * Initialization
3296  */
3297
3298 static const struct eth_dev_ops bnxt_dev_ops = {
3299         .dev_infos_get = bnxt_dev_info_get_op,
3300         .dev_close = bnxt_dev_close_op,
3301         .dev_configure = bnxt_dev_configure_op,
3302         .dev_start = bnxt_dev_start_op,
3303         .dev_stop = bnxt_dev_stop_op,
3304         .dev_set_link_up = bnxt_dev_set_link_up_op,
3305         .dev_set_link_down = bnxt_dev_set_link_down_op,
3306         .stats_get = bnxt_stats_get_op,
3307         .stats_reset = bnxt_stats_reset_op,
3308         .rx_queue_setup = bnxt_rx_queue_setup_op,
3309         .rx_queue_release = bnxt_rx_queue_release_op,
3310         .tx_queue_setup = bnxt_tx_queue_setup_op,
3311         .tx_queue_release = bnxt_tx_queue_release_op,
3312         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3313         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3314         .reta_update = bnxt_reta_update_op,
3315         .reta_query = bnxt_reta_query_op,
3316         .rss_hash_update = bnxt_rss_hash_update_op,
3317         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3318         .link_update = bnxt_link_update_op,
3319         .promiscuous_enable = bnxt_promiscuous_enable_op,
3320         .promiscuous_disable = bnxt_promiscuous_disable_op,
3321         .allmulticast_enable = bnxt_allmulticast_enable_op,
3322         .allmulticast_disable = bnxt_allmulticast_disable_op,
3323         .mac_addr_add = bnxt_mac_addr_add_op,
3324         .mac_addr_remove = bnxt_mac_addr_remove_op,
3325         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3326         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3327         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3328         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3329         .vlan_filter_set = bnxt_vlan_filter_set_op,
3330         .vlan_offload_set = bnxt_vlan_offload_set_op,
3331         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3332         .mtu_set = bnxt_mtu_set_op,
3333         .mac_addr_set = bnxt_set_default_mac_addr_op,
3334         .xstats_get = bnxt_dev_xstats_get_op,
3335         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3336         .xstats_reset = bnxt_dev_xstats_reset_op,
3337         .fw_version_get = bnxt_fw_version_get,
3338         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3339         .rxq_info_get = bnxt_rxq_info_get_op,
3340         .txq_info_get = bnxt_txq_info_get_op,
3341         .dev_led_on = bnxt_dev_led_on_op,
3342         .dev_led_off = bnxt_dev_led_off_op,
3343         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3344         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3345         .rx_queue_count = bnxt_rx_queue_count_op,
3346         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3347         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3348         .rx_queue_start = bnxt_rx_queue_start,
3349         .rx_queue_stop = bnxt_rx_queue_stop,
3350         .tx_queue_start = bnxt_tx_queue_start,
3351         .tx_queue_stop = bnxt_tx_queue_stop,
3352         .filter_ctrl = bnxt_filter_ctrl_op,
3353         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3354         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3355         .get_eeprom           = bnxt_get_eeprom_op,
3356         .set_eeprom           = bnxt_set_eeprom_op,
3357         .timesync_enable      = bnxt_timesync_enable,
3358         .timesync_disable     = bnxt_timesync_disable,
3359         .timesync_read_time   = bnxt_timesync_read_time,
3360         .timesync_write_time   = bnxt_timesync_write_time,
3361         .timesync_adjust_time = bnxt_timesync_adjust_time,
3362         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3363         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3364 };
3365
3366 static bool bnxt_vf_pciid(uint16_t id)
3367 {
3368         if (id == BROADCOM_DEV_ID_57304_VF ||
3369             id == BROADCOM_DEV_ID_57406_VF ||
3370             id == BROADCOM_DEV_ID_5731X_VF ||
3371             id == BROADCOM_DEV_ID_5741X_VF ||
3372             id == BROADCOM_DEV_ID_57414_VF ||
3373             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3374             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3375             id == BROADCOM_DEV_ID_58802_VF ||
3376             id == BROADCOM_DEV_ID_57500_VF)
3377                 return true;
3378         return false;
3379 }
3380
3381 bool bnxt_stratus_device(struct bnxt *bp)
3382 {
3383         uint16_t id = bp->pdev->id.device_id;
3384
3385         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3386             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3387             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3388                 return true;
3389         return false;
3390 }
3391
3392 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3393 {
3394         struct bnxt *bp = eth_dev->data->dev_private;
3395         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3396         int rc;
3397
3398         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3399         if (!pci_dev->mem_resource[0].addr) {
3400                 PMD_DRV_LOG(ERR,
3401                         "Cannot find PCI device base address, aborting\n");
3402                 rc = -ENODEV;
3403                 goto init_err_disable;
3404         }
3405
3406         bp->eth_dev = eth_dev;
3407         bp->pdev = pci_dev;
3408
3409         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3410         if (!bp->bar0) {
3411                 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3412                 rc = -ENOMEM;
3413                 goto init_err_release;
3414         }
3415
3416         if (!pci_dev->mem_resource[2].addr) {
3417                 PMD_DRV_LOG(ERR,
3418                             "Cannot find PCI device BAR 2 address, aborting\n");
3419                 rc = -ENODEV;
3420                 goto init_err_release;
3421         } else {
3422                 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3423         }
3424
3425         return 0;
3426
3427 init_err_release:
3428         if (bp->bar0)
3429                 bp->bar0 = NULL;
3430         if (bp->doorbell_base)
3431                 bp->doorbell_base = NULL;
3432
3433 init_err_disable:
3434
3435         return rc;
3436 }
3437
3438 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3439                                   struct bnxt_ctx_pg_info *ctx_pg,
3440                                   uint32_t mem_size,
3441                                   const char *suffix,
3442                                   uint16_t idx)
3443 {
3444         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3445         const struct rte_memzone *mz = NULL;
3446         char mz_name[RTE_MEMZONE_NAMESIZE];
3447         rte_iova_t mz_phys_addr;
3448         uint64_t valid_bits = 0;
3449         uint32_t sz;
3450         int i;
3451
3452         if (!mem_size)
3453                 return 0;
3454
3455         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3456                          BNXT_PAGE_SIZE;
3457         rmem->page_size = BNXT_PAGE_SIZE;
3458         rmem->pg_arr = ctx_pg->ctx_pg_arr;
3459         rmem->dma_arr = ctx_pg->ctx_dma_arr;
3460         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3461
3462         valid_bits = PTU_PTE_VALID;
3463
3464         if (rmem->nr_pages > 1) {
3465                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_pg_tbl%s_%x",
3466                          suffix, idx);
3467                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3468                 mz = rte_memzone_lookup(mz_name);
3469                 if (!mz) {
3470                         mz = rte_memzone_reserve_aligned(mz_name,
3471                                                 rmem->nr_pages * 8,
3472                                                 SOCKET_ID_ANY,
3473                                                 RTE_MEMZONE_2MB |
3474                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
3475                                                 RTE_MEMZONE_IOVA_CONTIG,
3476                                                 BNXT_PAGE_SIZE);
3477                         if (mz == NULL)
3478                                 return -ENOMEM;
3479                 }
3480
3481                 memset(mz->addr, 0, mz->len);
3482                 mz_phys_addr = mz->iova;
3483                 if ((unsigned long)mz->addr == mz_phys_addr) {
3484                         PMD_DRV_LOG(WARNING,
3485                                 "Memzone physical address same as virtual.\n");
3486                         PMD_DRV_LOG(WARNING,
3487                                     "Using rte_mem_virt2iova()\n");
3488                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3489                         if (mz_phys_addr == RTE_BAD_IOVA) {
3490                                 PMD_DRV_LOG(ERR,
3491                                         "unable to map addr to phys memory\n");
3492                                 return -ENOMEM;
3493                         }
3494                 }
3495                 rte_mem_lock_page(((char *)mz->addr));
3496
3497                 rmem->pg_tbl = mz->addr;
3498                 rmem->pg_tbl_map = mz_phys_addr;
3499                 rmem->pg_tbl_mz = mz;
3500         }
3501
3502         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x", suffix, idx);
3503         mz = rte_memzone_lookup(mz_name);
3504         if (!mz) {
3505                 mz = rte_memzone_reserve_aligned(mz_name,
3506                                                  mem_size,
3507                                                  SOCKET_ID_ANY,
3508                                                  RTE_MEMZONE_1GB |
3509                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
3510                                                  RTE_MEMZONE_IOVA_CONTIG,
3511                                                  BNXT_PAGE_SIZE);
3512                 if (mz == NULL)
3513                         return -ENOMEM;
3514         }
3515
3516         memset(mz->addr, 0, mz->len);
3517         mz_phys_addr = mz->iova;
3518         if ((unsigned long)mz->addr == mz_phys_addr) {
3519                 PMD_DRV_LOG(WARNING,
3520                             "Memzone physical address same as virtual.\n");
3521                 PMD_DRV_LOG(WARNING,
3522                             "Using rte_mem_virt2iova()\n");
3523                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3524                         rte_mem_lock_page(((char *)mz->addr) + sz);
3525                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3526                 if (mz_phys_addr == RTE_BAD_IOVA) {
3527                         PMD_DRV_LOG(ERR,
3528                                     "unable to map addr to phys memory\n");
3529                         return -ENOMEM;
3530                 }
3531         }
3532
3533         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3534                 rte_mem_lock_page(((char *)mz->addr) + sz);
3535                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3536                 rmem->dma_arr[i] = mz_phys_addr + sz;
3537
3538                 if (rmem->nr_pages > 1) {
3539                         if (i == rmem->nr_pages - 2 &&
3540                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3541                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3542                         else if (i == rmem->nr_pages - 1 &&
3543                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3544                                 valid_bits |= PTU_PTE_LAST;
3545
3546                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3547                                                            valid_bits);
3548                 }
3549         }
3550
3551         rmem->mz = mz;
3552         if (rmem->vmem_size)
3553                 rmem->vmem = (void **)mz->addr;
3554         rmem->dma_arr[0] = mz_phys_addr;
3555         return 0;
3556 }
3557
3558 static void bnxt_free_ctx_mem(struct bnxt *bp)
3559 {
3560         int i;
3561
3562         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3563                 return;
3564
3565         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3566         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3567         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3568         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3569         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3570         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3571         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3572         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3573         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3574         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3575         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3576
3577         for (i = 0; i < BNXT_MAX_Q; i++) {
3578                 if (bp->ctx->tqm_mem[i])
3579                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3580         }
3581
3582         rte_free(bp->ctx);
3583         bp->ctx = NULL;
3584 }
3585
3586 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
3587
3588 #define min_t(type, x, y) ({                    \
3589         type __min1 = (x);                      \
3590         type __min2 = (y);                      \
3591         __min1 < __min2 ? __min1 : __min2; })
3592
3593 #define max_t(type, x, y) ({                    \
3594         type __max1 = (x);                      \
3595         type __max2 = (y);                      \
3596         __max1 > __max2 ? __max1 : __max2; })
3597
3598 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
3599
3600 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3601 {
3602         struct bnxt_ctx_pg_info *ctx_pg;
3603         struct bnxt_ctx_mem_info *ctx;
3604         uint32_t mem_size, ena, entries;
3605         int i, rc;
3606
3607         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3608         if (rc) {
3609                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3610                 return rc;
3611         }
3612         ctx = bp->ctx;
3613         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3614                 return 0;
3615
3616         ctx_pg = &ctx->qp_mem;
3617         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3618         mem_size = ctx->qp_entry_size * ctx_pg->entries;
3619         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3620         if (rc)
3621                 return rc;
3622
3623         ctx_pg = &ctx->srq_mem;
3624         ctx_pg->entries = ctx->srq_max_l2_entries;
3625         mem_size = ctx->srq_entry_size * ctx_pg->entries;
3626         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3627         if (rc)
3628                 return rc;
3629
3630         ctx_pg = &ctx->cq_mem;
3631         ctx_pg->entries = ctx->cq_max_l2_entries;
3632         mem_size = ctx->cq_entry_size * ctx_pg->entries;
3633         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3634         if (rc)
3635                 return rc;
3636
3637         ctx_pg = &ctx->vnic_mem;
3638         ctx_pg->entries = ctx->vnic_max_vnic_entries +
3639                 ctx->vnic_max_ring_table_entries;
3640         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3641         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3642         if (rc)
3643                 return rc;
3644
3645         ctx_pg = &ctx->stat_mem;
3646         ctx_pg->entries = ctx->stat_max_entries;
3647         mem_size = ctx->stat_entry_size * ctx_pg->entries;
3648         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3649         if (rc)
3650                 return rc;
3651
3652         entries = ctx->qp_max_l2_entries;
3653         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
3654         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3655                           ctx->tqm_max_entries_per_ring);
3656         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3657                 ctx_pg = ctx->tqm_mem[i];
3658                 /* use min tqm entries for now. */
3659                 ctx_pg->entries = entries;
3660                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3661                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3662                 if (rc)
3663                         return rc;
3664                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3665         }
3666
3667         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3668         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3669         if (rc)
3670                 PMD_DRV_LOG(ERR,
3671                             "Failed to configure context mem: rc = %d\n", rc);
3672         else
3673                 ctx->flags |= BNXT_CTX_FLAG_INITED;
3674
3675         return 0;
3676 }
3677
3678 static int bnxt_alloc_stats_mem(struct bnxt *bp)
3679 {
3680         struct rte_pci_device *pci_dev = bp->pdev;
3681         char mz_name[RTE_MEMZONE_NAMESIZE];
3682         const struct rte_memzone *mz = NULL;
3683         uint32_t total_alloc_len;
3684         rte_iova_t mz_phys_addr;
3685
3686         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
3687                 return 0;
3688
3689         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3690                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3691                  pci_dev->addr.bus, pci_dev->addr.devid,
3692                  pci_dev->addr.function, "rx_port_stats");
3693         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3694         mz = rte_memzone_lookup(mz_name);
3695         total_alloc_len =
3696                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
3697                                        sizeof(struct rx_port_stats_ext) + 512);
3698         if (!mz) {
3699                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3700                                          SOCKET_ID_ANY,
3701                                          RTE_MEMZONE_2MB |
3702                                          RTE_MEMZONE_SIZE_HINT_ONLY |
3703                                          RTE_MEMZONE_IOVA_CONTIG);
3704                 if (mz == NULL)
3705                         return -ENOMEM;
3706         }
3707         memset(mz->addr, 0, mz->len);
3708         mz_phys_addr = mz->iova;
3709         if ((unsigned long)mz->addr == mz_phys_addr) {
3710                 PMD_DRV_LOG(WARNING,
3711                             "Memzone physical address same as virtual.\n");
3712                 PMD_DRV_LOG(WARNING,
3713                             "Using rte_mem_virt2iova()\n");
3714                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3715                 if (mz_phys_addr == RTE_BAD_IOVA) {
3716                         PMD_DRV_LOG(ERR,
3717                                     "Can't map address to physical memory\n");
3718                         return -ENOMEM;
3719                 }
3720         }
3721
3722         bp->rx_mem_zone = (const void *)mz;
3723         bp->hw_rx_port_stats = mz->addr;
3724         bp->hw_rx_port_stats_map = mz_phys_addr;
3725
3726         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3727                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3728                  pci_dev->addr.bus, pci_dev->addr.devid,
3729                  pci_dev->addr.function, "tx_port_stats");
3730         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3731         mz = rte_memzone_lookup(mz_name);
3732         total_alloc_len =
3733                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
3734                                        sizeof(struct tx_port_stats_ext) + 512);
3735         if (!mz) {
3736                 mz = rte_memzone_reserve(mz_name,
3737                                          total_alloc_len,
3738                                          SOCKET_ID_ANY,
3739                                          RTE_MEMZONE_2MB |
3740                                          RTE_MEMZONE_SIZE_HINT_ONLY |
3741                                          RTE_MEMZONE_IOVA_CONTIG);
3742                 if (mz == NULL)
3743                         return -ENOMEM;
3744         }
3745         memset(mz->addr, 0, mz->len);
3746         mz_phys_addr = mz->iova;
3747         if ((unsigned long)mz->addr == mz_phys_addr) {
3748                 PMD_DRV_LOG(WARNING,
3749                             "Memzone physical address same as virtual\n");
3750                 PMD_DRV_LOG(WARNING,
3751                             "Using rte_mem_virt2iova()\n");
3752                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3753                 if (mz_phys_addr == RTE_BAD_IOVA) {
3754                         PMD_DRV_LOG(ERR,
3755                                     "Can't map address to physical memory\n");
3756                         return -ENOMEM;
3757                 }
3758         }
3759
3760         bp->tx_mem_zone = (const void *)mz;
3761         bp->hw_tx_port_stats = mz->addr;
3762         bp->hw_tx_port_stats_map = mz_phys_addr;
3763         bp->flags |= BNXT_FLAG_PORT_STATS;
3764
3765         /* Display extended statistics if FW supports it */
3766         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3767             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
3768             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
3769                 return 0;
3770
3771         bp->hw_rx_port_stats_ext = (void *)
3772                 ((uint8_t *)bp->hw_rx_port_stats +
3773                  sizeof(struct rx_port_stats));
3774         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3775                 sizeof(struct rx_port_stats);
3776         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3777
3778         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
3779             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
3780                 bp->hw_tx_port_stats_ext = (void *)
3781                         ((uint8_t *)bp->hw_tx_port_stats +
3782                          sizeof(struct tx_port_stats));
3783                 bp->hw_tx_port_stats_ext_map =
3784                         bp->hw_tx_port_stats_map +
3785                         sizeof(struct tx_port_stats);
3786                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3787         }
3788
3789         return 0;
3790 }
3791
3792 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
3793 {
3794         struct bnxt *bp = eth_dev->data->dev_private;
3795         int rc = 0;
3796
3797         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3798                                                RTE_ETHER_ADDR_LEN *
3799                                                bp->max_l2_ctx,
3800                                                0);
3801         if (eth_dev->data->mac_addrs == NULL) {
3802                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
3803                 return -ENOMEM;
3804         }
3805
3806         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3807                 if (BNXT_PF(bp))
3808                         return -EINVAL;
3809
3810                 /* Generate a random MAC address, if none was assigned by PF */
3811                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
3812                 bnxt_eth_hw_addr_random(bp->mac_addr);
3813                 PMD_DRV_LOG(INFO,
3814                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
3815                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
3816                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
3817
3818                 rc = bnxt_hwrm_set_mac(bp);
3819                 if (!rc)
3820                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
3821                                RTE_ETHER_ADDR_LEN);
3822                 return rc;
3823         }
3824
3825         /* Copy the permanent MAC from the FUNC_QCAPS response */
3826         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
3827         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3828
3829         return rc;
3830 }
3831
3832 #define ALLOW_FUNC(x)   \
3833         { \
3834                 uint32_t arg = (x); \
3835                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3836                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3837         }
3838 static int
3839 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3840 {
3841         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3842         static int version_printed;
3843         struct bnxt *bp;
3844         uint16_t mtu;
3845         int rc;
3846
3847         if (version_printed++ == 0)
3848                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3849
3850         rte_eth_copy_pci_info(eth_dev, pci_dev);
3851
3852         bp = eth_dev->data->dev_private;
3853
3854         bp->dev_stopped = 1;
3855
3856         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3857                 goto skip_init;
3858
3859         if (bnxt_vf_pciid(pci_dev->id.device_id))
3860                 bp->flags |= BNXT_FLAG_VF;
3861
3862         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
3863             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
3864             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
3865             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF)
3866                 bp->flags |= BNXT_FLAG_THOR_CHIP;
3867
3868         rc = bnxt_init_board(eth_dev);
3869         if (rc) {
3870                 PMD_DRV_LOG(ERR,
3871                         "Board initialization failed rc: %x\n", rc);
3872                 goto error;
3873         }
3874 skip_init:
3875         eth_dev->dev_ops = &bnxt_dev_ops;
3876         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3877         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3878         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3879                 return 0;
3880
3881         rc = bnxt_alloc_hwrm_resources(bp);
3882         if (rc) {
3883                 PMD_DRV_LOG(ERR,
3884                         "hwrm resource allocation failure rc: %x\n", rc);
3885                 goto error_free;
3886         }
3887         rc = bnxt_hwrm_ver_get(bp);
3888         if (rc)
3889                 goto error_free;
3890
3891         rc = bnxt_hwrm_func_reset(bp);
3892         if (rc) {
3893                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3894                 rc = -EIO;
3895                 goto error_free;
3896         }
3897
3898         rc = bnxt_hwrm_queue_qportcfg(bp);
3899         if (rc) {
3900                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3901                 goto error_free;
3902         }
3903         /* Get the MAX capabilities for this function */
3904         rc = bnxt_hwrm_func_qcaps(bp);
3905         if (rc) {
3906                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3907                 goto error_free;
3908         }
3909
3910         rc = bnxt_alloc_stats_mem(bp);
3911         if (rc)
3912                 goto error_free;
3913
3914         if (bp->max_tx_rings == 0) {
3915                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3916                 rc = -EBUSY;
3917                 goto error_free;
3918         }
3919
3920         rc = bnxt_setup_mac_addr(eth_dev);
3921         if (rc)
3922                 goto error_free;
3923
3924         /* THOR does not support ring groups.
3925          * But we will use the array to save RSS context IDs.
3926          */
3927         if (BNXT_CHIP_THOR(bp)) {
3928                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
3929         } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3930                 /* 1 ring is for default completion ring */
3931                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3932                 rc = -ENOSPC;
3933                 goto error_free;
3934         }
3935
3936         if (BNXT_HAS_RING_GRPS(bp)) {
3937                 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3938                                         sizeof(*bp->grp_info) *
3939                                                 bp->max_ring_grps, 0);
3940                 if (!bp->grp_info) {
3941                         PMD_DRV_LOG(ERR,
3942                                 "Failed to alloc %zu bytes for grp info tbl.\n",
3943                                 sizeof(*bp->grp_info) * bp->max_ring_grps);
3944                         rc = -ENOMEM;
3945                         goto error_free;
3946                 }
3947         }
3948
3949         /* Forward all requests if firmware is new enough */
3950         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3951             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3952             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3953                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3954         } else {
3955                 PMD_DRV_LOG(WARNING,
3956                         "Firmware too old for VF mailbox functionality\n");
3957                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3958         }
3959
3960         /*
3961          * The following are used for driver cleanup.  If we disallow these,
3962          * VF drivers can't clean up cleanly.
3963          */
3964         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3965         ALLOW_FUNC(HWRM_VNIC_FREE);
3966         ALLOW_FUNC(HWRM_RING_FREE);
3967         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3968         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3969         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3970         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3971         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3972         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3973         rc = bnxt_hwrm_func_driver_register(bp);
3974         if (rc) {
3975                 PMD_DRV_LOG(ERR,
3976                         "Failed to register driver");
3977                 rc = -EBUSY;
3978                 goto error_free;
3979         }
3980
3981         PMD_DRV_LOG(INFO,
3982                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3983                 pci_dev->mem_resource[0].phys_addr,
3984                 pci_dev->mem_resource[0].addr);
3985
3986         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
3987         if (rc) {
3988                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3989                 goto error_free;
3990         }
3991
3992         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
3993             mtu != eth_dev->data->mtu)
3994                 eth_dev->data->mtu = mtu;
3995
3996         if (BNXT_PF(bp)) {
3997                 //if (bp->pf.active_vfs) {
3998                         // TODO: Deallocate VF resources?
3999                 //}
4000                 if (bp->pdev->max_vfs) {
4001                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4002                         if (rc) {
4003                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4004                                 goto error_free;
4005                         }
4006                 } else {
4007                         rc = bnxt_hwrm_allocate_pf_only(bp);
4008                         if (rc) {
4009                                 PMD_DRV_LOG(ERR,
4010                                         "Failed to allocate PF resources\n");
4011                                 goto error_free;
4012                         }
4013                 }
4014         }
4015
4016         bnxt_hwrm_port_led_qcaps(bp);
4017
4018         rc = bnxt_setup_int(bp);
4019         if (rc)
4020                 goto error_free;
4021
4022         rc = bnxt_alloc_mem(bp);
4023         if (rc)
4024                 goto error_free_int;
4025
4026         rc = bnxt_request_int(bp);
4027         if (rc)
4028                 goto error_free_int;
4029
4030         bnxt_init_nic(bp);
4031
4032         return 0;
4033
4034 error_free_int:
4035         bnxt_disable_int(bp);
4036         bnxt_hwrm_func_buf_unrgtr(bp);
4037         bnxt_free_int(bp);
4038         bnxt_free_mem(bp);
4039 error_free:
4040         bnxt_dev_uninit(eth_dev);
4041 error:
4042         return rc;
4043 }
4044
4045 static int
4046 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4047 {
4048         struct bnxt *bp = eth_dev->data->dev_private;
4049         int rc;
4050
4051         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4052                 return -EPERM;
4053
4054         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4055         bnxt_disable_int(bp);
4056         bnxt_free_int(bp);
4057         bnxt_free_mem(bp);
4058         if (bp->grp_info != NULL) {
4059                 rte_free(bp->grp_info);
4060                 bp->grp_info = NULL;
4061         }
4062         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4063         bnxt_free_hwrm_resources(bp);
4064
4065         if (bp->tx_mem_zone) {
4066                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4067                 bp->tx_mem_zone = NULL;
4068         }
4069
4070         if (bp->rx_mem_zone) {
4071                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4072                 bp->rx_mem_zone = NULL;
4073         }
4074
4075         if (bp->dev_stopped == 0)
4076                 bnxt_dev_close_op(eth_dev);
4077         if (bp->pf.vf_info)
4078                 rte_free(bp->pf.vf_info);
4079         bnxt_free_ctx_mem(bp);
4080         eth_dev->dev_ops = NULL;
4081         eth_dev->rx_pkt_burst = NULL;
4082         eth_dev->tx_pkt_burst = NULL;
4083
4084         return rc;
4085 }
4086
4087 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4088         struct rte_pci_device *pci_dev)
4089 {
4090         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4091                 bnxt_dev_init);
4092 }
4093
4094 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4095 {
4096         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4097                 return rte_eth_dev_pci_generic_remove(pci_dev,
4098                                 bnxt_dev_uninit);
4099         else
4100                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4101 }
4102
4103 static struct rte_pci_driver bnxt_rte_pmd = {
4104         .id_table = bnxt_pci_id_map,
4105         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4106         .probe = bnxt_pci_probe,
4107         .remove = bnxt_pci_remove,
4108 };
4109
4110 static bool
4111 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4112 {
4113         if (strcmp(dev->device->driver->name, drv->driver.name))
4114                 return false;
4115
4116         return true;
4117 }
4118
4119 bool is_bnxt_supported(struct rte_eth_dev *dev)
4120 {
4121         return is_device_supported(dev, &bnxt_rte_pmd);
4122 }
4123
4124 RTE_INIT(bnxt_init_log)
4125 {
4126         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4127         if (bnxt_logtype_driver >= 0)
4128                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4129 }
4130
4131 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4132 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4133 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");