drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31 #include "bnxt_tf_common.h"
  32 #include "ulp_flow_db.h"
  33
  34 #define DRV_MODULE_NAME         "bnxt"
  35 static const char bnxt_version[] =
  36         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  37
  38 /*
  39  * The set of PCI devices this driver supports
  40  */
  41 static const struct rte_pci_id bnxt_pci_id_map[] = {
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  95         { .vendor_id = 0, /* sentinel */ },
  96 };
  97
  98 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  99 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 101 #define BNXT_DEVARG_REPRESENTOR "representor"
 102
 103 static const char *const bnxt_dev_args[] = {
 104         BNXT_DEVARG_REPRESENTOR,
 105         BNXT_DEVARG_TRUFLOW,
 106         BNXT_DEVARG_FLOW_XSTAT,
 107         BNXT_DEVARG_MAX_NUM_KFLOWS,
 108         NULL
 109 };
 110
 111 /*
 112  * truflow == false to disable the feature
 113  * truflow == true to enable the feature
 114  */
 115 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 116
 117 /*
 118  * flow_xstat == false to disable the feature
 119  * flow_xstat == true to enable the feature
 120  */
 121 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 122
 123 /*
 124  * max_num_kflows must be >= 32
 125  * and must be a power-of-2 supported value
 126  * return: 1 -> invalid
 127  *         0 -> valid
 128  */
 129 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 130 {
 131         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 132                 return 1;
 133         return 0;
 134 }
 135
 136 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 137 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 138 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 139 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 140 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 141 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 142 static void bnxt_dev_recover(void *arg);
 143 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 144 static void bnxt_free_rep_info(struct bnxt *bp);
 145
 146 int is_bnxt_in_error(struct bnxt *bp)
 147 {
 148         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 149                 return -EIO;
 150         if (bp->flags & BNXT_FLAG_FW_RESET)
 151                 return -EBUSY;
 152
 153         return 0;
 154 }
 155
 156 /***********************/
 157
 158 /*
 159  * High level utility functions
 160  */
 161
 162 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 163 {
 164         if (!BNXT_CHIP_THOR(bp))
 165                 return 1;
 166
 167         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 168                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 169                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 170 }
 171
 172 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 173 {
 174         if (!BNXT_CHIP_THOR(bp))
 175                 return HW_HASH_INDEX_SIZE;
 176
 177         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 178 }
 179
 180 static void bnxt_free_parent_info(struct bnxt *bp)
 181 {
 182         rte_free(bp->parent);
 183 }
 184
 185 static void bnxt_free_pf_info(struct bnxt *bp)
 186 {
 187         rte_free(bp->pf);
 188 }
 189
 190 static void bnxt_free_link_info(struct bnxt *bp)
 191 {
 192         rte_free(bp->link_info);
 193 }
 194
 195 static void bnxt_free_leds_info(struct bnxt *bp)
 196 {
 197         if (BNXT_VF(bp))
 198                 return;
 199
 200         rte_free(bp->leds);
 201         bp->leds = NULL;
 202 }
 203
 204 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 205 {
 206         rte_free(bp->flow_stat);
 207         bp->flow_stat = NULL;
 208 }
 209
 210 static void bnxt_free_cos_queues(struct bnxt *bp)
 211 {
 212         rte_free(bp->rx_cos_queue);
 213         rte_free(bp->tx_cos_queue);
 214 }
 215
 216 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 217 {
 218         bnxt_free_filter_mem(bp);
 219         bnxt_free_vnic_attributes(bp);
 220         bnxt_free_vnic_mem(bp);
 221
 222         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 223          * If the number of rings change across fw update,
 224          * we don't have much choice except to warn the user.
 225          */
 226         if (!reconfig) {
 227                 bnxt_free_stats(bp);
 228                 bnxt_free_tx_rings(bp);
 229                 bnxt_free_rx_rings(bp);
 230         }
 231         bnxt_free_async_cp_ring(bp);
 232         bnxt_free_rxtx_nq_ring(bp);
 233
 234         rte_free(bp->grp_info);
 235         bp->grp_info = NULL;
 236 }
 237
 238 static int bnxt_alloc_parent_info(struct bnxt *bp)
 239 {
 240         bp->parent = rte_zmalloc("bnxt_parent_info",
 241                                  sizeof(struct bnxt_parent_info), 0);
 242         if (bp->parent == NULL)
 243                 return -ENOMEM;
 244
 245         return 0;
 246 }
 247
 248 static int bnxt_alloc_pf_info(struct bnxt *bp)
 249 {
 250         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 251         if (bp->pf == NULL)
 252                 return -ENOMEM;
 253
 254         return 0;
 255 }
 256
 257 static int bnxt_alloc_link_info(struct bnxt *bp)
 258 {
 259         bp->link_info =
 260                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 261         if (bp->link_info == NULL)
 262                 return -ENOMEM;
 263
 264         return 0;
 265 }
 266
 267 static int bnxt_alloc_leds_info(struct bnxt *bp)
 268 {
 269         if (BNXT_VF(bp))
 270                 return 0;
 271
 272         bp->leds = rte_zmalloc("bnxt_leds",
 273                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 274                                0);
 275         if (bp->leds == NULL)
 276                 return -ENOMEM;
 277
 278         return 0;
 279 }
 280
 281 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 282 {
 283         bp->rx_cos_queue =
 284                 rte_zmalloc("bnxt_rx_cosq",
 285                             BNXT_COS_QUEUE_COUNT *
 286                             sizeof(struct bnxt_cos_queue_info),
 287                             0);
 288         if (bp->rx_cos_queue == NULL)
 289                 return -ENOMEM;
 290
 291         bp->tx_cos_queue =
 292                 rte_zmalloc("bnxt_tx_cosq",
 293                             BNXT_COS_QUEUE_COUNT *
 294                             sizeof(struct bnxt_cos_queue_info),
 295                             0);
 296         if (bp->tx_cos_queue == NULL)
 297                 return -ENOMEM;
 298
 299         return 0;
 300 }
 301
 302 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 303 {
 304         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 305                                     sizeof(struct bnxt_flow_stat_info), 0);
 306         if (bp->flow_stat == NULL)
 307                 return -ENOMEM;
 308
 309         return 0;
 310 }
 311
 312 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 313 {
 314         int rc;
 315
 316         rc = bnxt_alloc_ring_grps(bp);
 317         if (rc)
 318                 goto alloc_mem_err;
 319
 320         rc = bnxt_alloc_async_ring_struct(bp);
 321         if (rc)
 322                 goto alloc_mem_err;
 323
 324         rc = bnxt_alloc_vnic_mem(bp);
 325         if (rc)
 326                 goto alloc_mem_err;
 327
 328         rc = bnxt_alloc_vnic_attributes(bp);
 329         if (rc)
 330                 goto alloc_mem_err;
 331
 332         rc = bnxt_alloc_filter_mem(bp);
 333         if (rc)
 334                 goto alloc_mem_err;
 335
 336         rc = bnxt_alloc_async_cp_ring(bp);
 337         if (rc)
 338                 goto alloc_mem_err;
 339
 340         rc = bnxt_alloc_rxtx_nq_ring(bp);
 341         if (rc)
 342                 goto alloc_mem_err;
 343
 344         if (BNXT_FLOW_XSTATS_EN(bp)) {
 345                 rc = bnxt_alloc_flow_stats_info(bp);
 346                 if (rc)
 347                         goto alloc_mem_err;
 348         }
 349
 350         return 0;
 351
 352 alloc_mem_err:
 353         bnxt_free_mem(bp, reconfig);
 354         return rc;
 355 }
 356
 357 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 358 {
 359         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 360         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 361         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 362         struct bnxt_rx_queue *rxq;
 363         unsigned int j;
 364         int rc;
 365
 366         rc = bnxt_vnic_grp_alloc(bp, vnic);
 367         if (rc)
 368                 goto err_out;
 369
 370         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 371                     vnic_id, vnic, vnic->fw_grp_ids);
 372
 373         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 374         if (rc)
 375                 goto err_out;
 376
 377         /* Alloc RSS context only if RSS mode is enabled */
 378         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 379                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 380
 381                 rc = 0;
 382                 for (j = 0; j < nr_ctxs; j++) {
 383                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 384                         if (rc)
 385                                 break;
 386                 }
 387                 if (rc) {
 388                         PMD_DRV_LOG(ERR,
 389                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 390                                     vnic_id, j, rc);
 391                         goto err_out;
 392                 }
 393                 vnic->num_lb_ctxts = nr_ctxs;
 394         }
 395
 396         /*
 397          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 398          * setting is not available at this time, it will not be
 399          * configured correctly in the CFA.
 400          */
 401         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 402                 vnic->vlan_strip = true;
 403         else
 404                 vnic->vlan_strip = false;
 405
 406         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 407         if (rc)
 408                 goto err_out;
 409
 410         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 411         if (rc)
 412                 goto err_out;
 413
 414         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 415                 rxq = bp->eth_dev->data->rx_queues[j];
 416
 417                 PMD_DRV_LOG(DEBUG,
 418                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 419                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 420
 421                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 422                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 423                 else
 424                         vnic->rx_queue_cnt++;
 425         }
 426
 427         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 428
 429         rc = bnxt_vnic_rss_configure(bp, vnic);
 430         if (rc)
 431                 goto err_out;
 432
 433         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 434
 435         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 436                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 437         else
 438                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 439
 440         return 0;
 441 err_out:
 442         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 443                     vnic_id, rc);
 444         return rc;
 445 }
 446
 447 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 448 {
 449         int rc = 0;
 450
 451         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 452                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 453         if (rc)
 454                 return rc;
 455
 456         PMD_DRV_LOG(DEBUG,
 457                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 458                     " rx_fc_in_tbl.ctx_id = %d\n",
 459                     bp->flow_stat->rx_fc_in_tbl.va,
 460                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 461                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 462
 463         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 464                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 465         if (rc)
 466                 return rc;
 467
 468         PMD_DRV_LOG(DEBUG,
 469                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 470                     " rx_fc_out_tbl.ctx_id = %d\n",
 471                     bp->flow_stat->rx_fc_out_tbl.va,
 472                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 473                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 474
 475         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 476                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 477         if (rc)
 478                 return rc;
 479
 480         PMD_DRV_LOG(DEBUG,
 481                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 482                     " tx_fc_in_tbl.ctx_id = %d\n",
 483                     bp->flow_stat->tx_fc_in_tbl.va,
 484                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 485                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 486
 487         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 488                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 489         if (rc)
 490                 return rc;
 491
 492         PMD_DRV_LOG(DEBUG,
 493                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 494                     " tx_fc_out_tbl.ctx_id = %d\n",
 495                     bp->flow_stat->tx_fc_out_tbl.va,
 496                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 497                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 498
 499         memset(bp->flow_stat->rx_fc_out_tbl.va,
 500                0,
 501                bp->flow_stat->rx_fc_out_tbl.size);
 502         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 503                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 504                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 505                                        bp->flow_stat->max_fc,
 506                                        true);
 507         if (rc)
 508                 return rc;
 509
 510         memset(bp->flow_stat->tx_fc_out_tbl.va,
 511                0,
 512                bp->flow_stat->tx_fc_out_tbl.size);
 513         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 514                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 515                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 516                                        bp->flow_stat->max_fc,
 517                                        true);
 518
 519         return rc;
 520 }
 521
 522 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 523                                   struct bnxt_ctx_mem_buf_info *ctx)
 524 {
 525         if (!ctx)
 526                 return -EINVAL;
 527
 528         ctx->va = rte_zmalloc(type, size, 0);
 529         if (ctx->va == NULL)
 530                 return -ENOMEM;
 531         rte_mem_lock_page(ctx->va);
 532         ctx->size = size;
 533         ctx->dma = rte_mem_virt2iova(ctx->va);
 534         if (ctx->dma == RTE_BAD_IOVA)
 535                 return -ENOMEM;
 536
 537         return 0;
 538 }
 539
 540 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 541 {
 542         struct rte_pci_device *pdev = bp->pdev;
 543         char type[RTE_MEMZONE_NAMESIZE];
 544         uint16_t max_fc;
 545         int rc = 0;
 546
 547         max_fc = bp->flow_stat->max_fc;
 548
 549         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 550                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 551         /* 4 bytes for each counter-id */
 552         rc = bnxt_alloc_ctx_mem_buf(type,
 553                                     max_fc * 4,
 554                                     &bp->flow_stat->rx_fc_in_tbl);
 555         if (rc)
 556                 return rc;
 557
 558         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 559                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 560         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 561         rc = bnxt_alloc_ctx_mem_buf(type,
 562                                     max_fc * 16,
 563                                     &bp->flow_stat->rx_fc_out_tbl);
 564         if (rc)
 565                 return rc;
 566
 567         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 568                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 569         /* 4 bytes for each counter-id */
 570         rc = bnxt_alloc_ctx_mem_buf(type,
 571                                     max_fc * 4,
 572                                     &bp->flow_stat->tx_fc_in_tbl);
 573         if (rc)
 574                 return rc;
 575
 576         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 577                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 578         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 579         rc = bnxt_alloc_ctx_mem_buf(type,
 580                                     max_fc * 16,
 581                                     &bp->flow_stat->tx_fc_out_tbl);
 582         if (rc)
 583                 return rc;
 584
 585         rc = bnxt_register_fc_ctx_mem(bp);
 586
 587         return rc;
 588 }
 589
 590 static int bnxt_init_ctx_mem(struct bnxt *bp)
 591 {
 592         int rc = 0;
 593
 594         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 595             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 596             !BNXT_FLOW_XSTATS_EN(bp))
 597                 return 0;
 598
 599         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 600         if (rc)
 601                 return rc;
 602
 603         rc = bnxt_init_fc_ctx_mem(bp);
 604
 605         return rc;
 606 }
 607
 608 static int bnxt_update_phy_setting(struct bnxt *bp)
 609 {
 610         struct rte_eth_link new;
 611         int rc;
 612
 613         rc = bnxt_get_hwrm_link_config(bp, &new);
 614         if (rc) {
 615                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 616                 return rc;
 617         }
 618
 619         /*
 620          * On BCM957508-N2100 adapters, FW will not allow any user other
 621          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 622          * always returns link up. Force phy update always in that case.
 623          */
 624         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 625                 rc = bnxt_set_hwrm_link_config(bp, true);
 626                 if (rc) {
 627                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 628                         return rc;
 629                 }
 630         }
 631
 632         return rc;
 633 }
 634
 635 static int bnxt_init_chip(struct bnxt *bp)
 636 {
 637         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 638         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 639         uint32_t intr_vector = 0;
 640         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 641         uint32_t vec = BNXT_MISC_VEC_ID;
 642         unsigned int i, j;
 643         int rc;
 644
 645         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 646                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 647                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 648                 bp->flags |= BNXT_FLAG_JUMBO;
 649         } else {
 650                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 651                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 652                 bp->flags &= ~BNXT_FLAG_JUMBO;
 653         }
 654
 655         /* THOR does not support ring groups.
 656          * But we will use the array to save RSS context IDs.
 657          */
 658         if (BNXT_CHIP_THOR(bp))
 659                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 660
 661         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 662         if (rc) {
 663                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 664                 goto err_out;
 665         }
 666
 667         rc = bnxt_alloc_hwrm_rings(bp);
 668         if (rc) {
 669                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 670                 goto err_out;
 671         }
 672
 673         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 674         if (rc) {
 675                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 676                 goto err_out;
 677         }
 678
 679         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 680                 goto skip_cosq_cfg;
 681
 682         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 683                 if (bp->rx_cos_queue[i].id != 0xff) {
 684                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 685
 686                         if (!vnic) {
 687                                 PMD_DRV_LOG(ERR,
 688                                             "Num pools more than FW profile\n");
 689                                 rc = -EINVAL;
 690                                 goto err_out;
 691                         }
 692                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 693                         bp->rx_cosq_cnt++;
 694                 }
 695         }
 696
 697 skip_cosq_cfg:
 698         rc = bnxt_mq_rx_configure(bp);
 699         if (rc) {
 700                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 701                 goto err_out;
 702         }
 703
 704         /* VNIC configuration */
 705         for (i = 0; i < bp->nr_vnics; i++) {
 706                 rc = bnxt_setup_one_vnic(bp, i);
 707                 if (rc)
 708                         goto err_out;
 709         }
 710
 711         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 712         if (rc) {
 713                 PMD_DRV_LOG(ERR,
 714                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 715                 goto err_out;
 716         }
 717
 718         /* check and configure queue intr-vector mapping */
 719         if ((rte_intr_cap_multiple(intr_handle) ||
 720              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 721             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 722                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 723                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 724                 if (intr_vector > bp->rx_cp_nr_rings) {
 725                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 726                                         bp->rx_cp_nr_rings);
 727                         return -ENOTSUP;
 728                 }
 729                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 730                 if (rc)
 731                         return rc;
 732         }
 733
 734         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 735                 intr_handle->intr_vec =
 736                         rte_zmalloc("intr_vec",
 737                                     bp->eth_dev->data->nb_rx_queues *
 738                                     sizeof(int), 0);
 739                 if (intr_handle->intr_vec == NULL) {
 740                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 741                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 742                         rc = -ENOMEM;
 743                         goto err_disable;
 744                 }
 745                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 746                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 747                          intr_handle->intr_vec, intr_handle->nb_efd,
 748                         intr_handle->max_intr);
 749                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 750                      queue_id++) {
 751                         intr_handle->intr_vec[queue_id] =
 752                                                         vec + BNXT_RX_VEC_START;
 753                         if (vec < base + intr_handle->nb_efd - 1)
 754                                 vec++;
 755                 }
 756         }
 757
 758         /* enable uio/vfio intr/eventfd mapping */
 759         rc = rte_intr_enable(intr_handle);
 760 #ifndef RTE_EXEC_ENV_FREEBSD
 761         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 762         if (rc)
 763                 goto err_free;
 764 #endif
 765
 766         rc = bnxt_update_phy_setting(bp);
 767         if (rc)
 768                 goto err_free;
 769
 770         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 771         if (!bp->mark_table)
 772                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 773
 774         return 0;
 775
 776 err_free:
 777         rte_free(intr_handle->intr_vec);
 778 err_disable:
 779         rte_intr_efd_disable(intr_handle);
 780 err_out:
 781         /* Some of the error status returned by FW may not be from errno.h */
 782         if (rc > 0)
 783                 rc = -EIO;
 784
 785         return rc;
 786 }
 787
 788 static int bnxt_shutdown_nic(struct bnxt *bp)
 789 {
 790         bnxt_free_all_hwrm_resources(bp);
 791         bnxt_free_all_filters(bp);
 792         bnxt_free_all_vnics(bp);
 793         return 0;
 794 }
 795
 796 /*
 797  * Device configuration and status function
 798  */
 799
 800 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 801 {
 802         uint32_t link_speed = bp->link_info->support_speeds;
 803         uint32_t speed_capa = 0;
 804
 805         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 806                 speed_capa |= ETH_LINK_SPEED_100M;
 807         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 808                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 809         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 810                 speed_capa |= ETH_LINK_SPEED_1G;
 811         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 812                 speed_capa |= ETH_LINK_SPEED_2_5G;
 813         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 814                 speed_capa |= ETH_LINK_SPEED_10G;
 815         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 816                 speed_capa |= ETH_LINK_SPEED_20G;
 817         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 818                 speed_capa |= ETH_LINK_SPEED_25G;
 819         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 820                 speed_capa |= ETH_LINK_SPEED_40G;
 821         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 822                 speed_capa |= ETH_LINK_SPEED_50G;
 823         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 824                 speed_capa |= ETH_LINK_SPEED_100G;
 825         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
 826                 speed_capa |= ETH_LINK_SPEED_200G;
 827
 828         if (bp->link_info->auto_mode ==
 829             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 830                 speed_capa |= ETH_LINK_SPEED_FIXED;
 831         else
 832                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 833
 834         return speed_capa;
 835 }
 836
 837 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 838                                 struct rte_eth_dev_info *dev_info)
 839 {
 840         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 841         struct bnxt *bp = eth_dev->data->dev_private;
 842         uint16_t max_vnics, i, j, vpool, vrxq;
 843         unsigned int max_rx_rings;
 844         int rc;
 845
 846         rc = is_bnxt_in_error(bp);
 847         if (rc)
 848                 return rc;
 849
 850         /* MAC Specifics */
 851         dev_info->max_mac_addrs = bp->max_l2_ctx;
 852         dev_info->max_hash_mac_addrs = 0;
 853
 854         /* PF/VF specifics */
 855         if (BNXT_PF(bp))
 856                 dev_info->max_vfs = pdev->max_vfs;
 857
 858         max_rx_rings = BNXT_MAX_RINGS(bp);
 859         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 860         dev_info->max_rx_queues = max_rx_rings;
 861         dev_info->max_tx_queues = max_rx_rings;
 862         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 863         dev_info->hash_key_size = 40;
 864         max_vnics = bp->max_vnics;
 865
 866         /* MTU specifics */
 867         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 868         dev_info->max_mtu = BNXT_MAX_MTU;
 869
 870         /* Fast path specifics */
 871         dev_info->min_rx_bufsize = 1;
 872         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 873
 874         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 875         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 876                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 877         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 878         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 879
 880         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 881
 882         /* *INDENT-OFF* */
 883         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 884                 .rx_thresh = {
 885                         .pthresh = 8,
 886                         .hthresh = 8,
 887                         .wthresh = 0,
 888                 },
 889                 .rx_free_thresh = 32,
 890                 /* If no descriptors available, pkts are dropped by default */
 891                 .rx_drop_en = 1,
 892         };
 893
 894         dev_info->default_txconf = (struct rte_eth_txconf) {
 895                 .tx_thresh = {
 896                         .pthresh = 32,
 897                         .hthresh = 0,
 898                         .wthresh = 0,
 899                 },
 900                 .tx_free_thresh = 32,
 901                 .tx_rs_thresh = 32,
 902         };
 903         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 904
 905         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 906         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 907         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 908         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 909         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 910
 911         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 912                 dev_info->switch_info.name = eth_dev->device->name;
 913                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 914                 dev_info->switch_info.port_id =
 915                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 916                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 917         }
 918
 919         /* *INDENT-ON* */
 920
 921         /*
 922          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 923          *       need further investigation.
 924          */
 925
 926         /* VMDq resources */
 927         vpool = 64; /* ETH_64_POOLS */
 928         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 929         for (i = 0; i < 4; vpool >>= 1, i++) {
 930                 if (max_vnics > vpool) {
 931                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 932                                 if (dev_info->max_rx_queues > vrxq) {
 933                                         if (vpool > vrxq)
 934                                                 vpool = vrxq;
 935                                         goto found;
 936                                 }
 937                         }
 938                         /* Not enough resources to support VMDq */
 939                         break;
 940                 }
 941         }
 942         /* Not enough resources to support VMDq */
 943         vpool = 0;
 944         vrxq = 0;
 945 found:
 946         dev_info->max_vmdq_pools = vpool;
 947         dev_info->vmdq_queue_num = vrxq;
 948
 949         dev_info->vmdq_pool_base = 0;
 950         dev_info->vmdq_queue_base = 0;
 951
 952         return 0;
 953 }
 954
 955 /* Configure the device based on the configuration provided */
 956 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 957 {
 958         struct bnxt *bp = eth_dev->data->dev_private;
 959         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 960         int rc;
 961
 962         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 963         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 964         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 965         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 966
 967         rc = is_bnxt_in_error(bp);
 968         if (rc)
 969                 return rc;
 970
 971         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 972                 rc = bnxt_hwrm_check_vf_rings(bp);
 973                 if (rc) {
 974                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 975                         return -ENOSPC;
 976                 }
 977
 978                 /* If a resource has already been allocated - in this case
 979                  * it is the async completion ring, free it. Reallocate it after
 980                  * resource reservation. This will ensure the resource counts
 981                  * are calculated correctly.
 982                  */
 983
 984                 pthread_mutex_lock(&bp->def_cp_lock);
 985
 986                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 987                         bnxt_disable_int(bp);
 988                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 989                 }
 990
 991                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 992                 if (rc) {
 993                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 994                         pthread_mutex_unlock(&bp->def_cp_lock);
 995                         return -ENOSPC;
 996                 }
 997
 998                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 999                         rc = bnxt_alloc_async_cp_ring(bp);
1000                         if (rc) {
1001                                 pthread_mutex_unlock(&bp->def_cp_lock);
1002                                 return rc;
1003                         }
1004                         bnxt_enable_int(bp);
1005                 }
1006
1007                 pthread_mutex_unlock(&bp->def_cp_lock);
1008         } else {
1009                 /* legacy driver needs to get updated values */
1010                 rc = bnxt_hwrm_func_qcaps(bp);
1011                 if (rc) {
1012                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1013                         return rc;
1014                 }
1015         }
1016
1017         /* Inherit new configurations */
1018         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1019             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1020             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1021                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1022             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1023             bp->max_stat_ctx)
1024                 goto resource_error;
1025
1026         if (BNXT_HAS_RING_GRPS(bp) &&
1027             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1028                 goto resource_error;
1029
1030         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1031             bp->max_vnics < eth_dev->data->nb_rx_queues)
1032                 goto resource_error;
1033
1034         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1035         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1036
1037         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1038                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1039         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1040
1041         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1042                 eth_dev->data->mtu =
1043                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1044                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1045                         BNXT_NUM_VLANS;
1046                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1047         }
1048         return 0;
1049
1050 resource_error:
1051         PMD_DRV_LOG(ERR,
1052                     "Insufficient resources to support requested config\n");
1053         PMD_DRV_LOG(ERR,
1054                     "Num Queues Requested: Tx %d, Rx %d\n",
1055                     eth_dev->data->nb_tx_queues,
1056                     eth_dev->data->nb_rx_queues);
1057         PMD_DRV_LOG(ERR,
1058                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1059                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1060                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1061         return -ENOSPC;
1062 }
1063
1064 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1065 {
1066         struct rte_eth_link *link = &eth_dev->data->dev_link;
1067
1068         if (link->link_status)
1069                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1070                         eth_dev->data->port_id,
1071                         (uint32_t)link->link_speed,
1072                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1073                         ("full-duplex") : ("half-duplex\n"));
1074         else
1075                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1076                         eth_dev->data->port_id);
1077 }
1078
1079 /*
1080  * Determine whether the current configuration requires support for scattered
1081  * receive; return 1 if scattered receive is required and 0 if not.
1082  */
1083 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1084 {
1085         uint16_t buf_size;
1086         int i;
1087
1088         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1089                 return 1;
1090
1091         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1092                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1093
1094                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1095                                       RTE_PKTMBUF_HEADROOM);
1096                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1097                         return 1;
1098         }
1099         return 0;
1100 }
1101
1102 static eth_rx_burst_t
1103 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1104 {
1105         struct bnxt *bp = eth_dev->data->dev_private;
1106
1107 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1108 #ifndef RTE_LIBRTE_IEEE1588
1109         /*
1110          * Vector mode receive can be enabled only if scatter rx is not
1111          * in use and rx offloads are limited to VLAN stripping and
1112          * CRC stripping.
1113          */
1114         if (!eth_dev->data->scattered_rx &&
1115             !(eth_dev->data->dev_conf.rxmode.offloads &
1116               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1117                 DEV_RX_OFFLOAD_KEEP_CRC |
1118                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1119                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1120                 DEV_RX_OFFLOAD_UDP_CKSUM |
1121                 DEV_RX_OFFLOAD_TCP_CKSUM |
1122                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1123                 DEV_RX_OFFLOAD_RSS_HASH |
1124                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1125             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) {
1126                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1127                             eth_dev->data->port_id);
1128                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1129                 return bnxt_recv_pkts_vec;
1130         }
1131         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1132                     eth_dev->data->port_id);
1133         PMD_DRV_LOG(INFO,
1134                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1135                     eth_dev->data->port_id,
1136                     eth_dev->data->scattered_rx,
1137                     eth_dev->data->dev_conf.rxmode.offloads);
1138 #endif
1139 #endif
1140         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1141         return bnxt_recv_pkts;
1142 }
1143
1144 static eth_tx_burst_t
1145 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1146 {
1147 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1148 #ifndef RTE_LIBRTE_IEEE1588
1149         struct bnxt *bp = eth_dev->data->dev_private;
1150
1151         /*
1152          * Vector mode transmit can be enabled only if not using scatter rx
1153          * or tx offloads.
1154          */
1155         if (!eth_dev->data->scattered_rx &&
1156             !eth_dev->data->dev_conf.txmode.offloads &&
1157             !BNXT_TRUFLOW_EN(bp)) {
1158                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1159                             eth_dev->data->port_id);
1160                 return bnxt_xmit_pkts_vec;
1161         }
1162         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1163                     eth_dev->data->port_id);
1164         PMD_DRV_LOG(INFO,
1165                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1166                     eth_dev->data->port_id,
1167                     eth_dev->data->scattered_rx,
1168                     eth_dev->data->dev_conf.txmode.offloads);
1169 #endif
1170 #endif
1171         return bnxt_xmit_pkts;
1172 }
1173
1174 static int bnxt_handle_if_change_status(struct bnxt *bp)
1175 {
1176         int rc;
1177
1178         /* Since fw has undergone a reset and lost all contexts,
1179          * set fatal flag to not issue hwrm during cleanup
1180          */
1181         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1182         bnxt_uninit_resources(bp, true);
1183
1184         /* clear fatal flag so that re-init happens */
1185         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1186         rc = bnxt_init_resources(bp, true);
1187
1188         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1189
1190         return rc;
1191 }
1192
1193 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1194 {
1195         struct bnxt *bp = eth_dev->data->dev_private;
1196         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1197         int vlan_mask = 0;
1198         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1199
1200         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1201                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1202                 return -EINVAL;
1203         }
1204
1205         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1206                 PMD_DRV_LOG(ERR,
1207                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1208                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1209         }
1210
1211         do {
1212                 rc = bnxt_hwrm_if_change(bp, true);
1213                 if (rc == 0 || rc != -EAGAIN)
1214                         break;
1215
1216                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1217         } while (retry_cnt--);
1218
1219         if (rc)
1220                 return rc;
1221
1222         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1223                 rc = bnxt_handle_if_change_status(bp);
1224                 if (rc)
1225                         return rc;
1226         }
1227
1228         bnxt_enable_int(bp);
1229
1230         rc = bnxt_init_chip(bp);
1231         if (rc)
1232                 goto error;
1233
1234         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1235         eth_dev->data->dev_started = 1;
1236
1237         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1238
1239         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1240                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1241         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1242                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1243         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1244         if (rc)
1245                 goto error;
1246
1247         /* Initialize bnxt ULP port details */
1248         rc = bnxt_ulp_port_init(bp);
1249         if (rc)
1250                 goto error;
1251
1252         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1253         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1254
1255         bnxt_schedule_fw_health_check(bp);
1256
1257         return 0;
1258
1259 error:
1260         bnxt_shutdown_nic(bp);
1261         bnxt_free_tx_mbufs(bp);
1262         bnxt_free_rx_mbufs(bp);
1263         bnxt_hwrm_if_change(bp, false);
1264         eth_dev->data->dev_started = 0;
1265         return rc;
1266 }
1267
1268 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1269 {
1270         struct bnxt *bp = eth_dev->data->dev_private;
1271         int rc = 0;
1272
1273         if (!bp->link_info->link_up)
1274                 rc = bnxt_set_hwrm_link_config(bp, true);
1275         if (!rc)
1276                 eth_dev->data->dev_link.link_status = 1;
1277
1278         bnxt_print_link_info(eth_dev);
1279         return rc;
1280 }
1281
1282 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1283 {
1284         struct bnxt *bp = eth_dev->data->dev_private;
1285
1286         eth_dev->data->dev_link.link_status = 0;
1287         bnxt_set_hwrm_link_config(bp, false);
1288         bp->link_info->link_up = 0;
1289
1290         return 0;
1291 }
1292
1293 static void bnxt_free_switch_domain(struct bnxt *bp)
1294 {
1295         if (bp->switch_domain_id)
1296                 rte_eth_switch_domain_free(bp->switch_domain_id);
1297 }
1298
1299 /* Unload the driver, release resources */
1300 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1301 {
1302         struct bnxt *bp = eth_dev->data->dev_private;
1303         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1304         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1305
1306         eth_dev->data->dev_started = 0;
1307         eth_dev->data->scattered_rx = 0;
1308
1309         /* Prevent crashes when queues are still in use */
1310         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1311         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1312
1313         bnxt_disable_int(bp);
1314
1315         /* disable uio/vfio intr/eventfd mapping */
1316         rte_intr_disable(intr_handle);
1317
1318         /* Stop the child representors for this device */
1319         bnxt_vf_rep_stop_all(bp);
1320
1321         /* delete the bnxt ULP port details */
1322         bnxt_ulp_port_deinit(bp);
1323
1324         bnxt_cancel_fw_health_check(bp);
1325
1326         /* Do not bring link down during reset recovery */
1327         if (!is_bnxt_in_error(bp))
1328                 bnxt_dev_set_link_down_op(eth_dev);
1329
1330         /* Wait for link to be reset and the async notification to process.
1331          * During reset recovery, there is no need to wait and
1332          * VF/NPAR functions do not have privilege to change PHY config.
1333          */
1334         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1335                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1336
1337         /* Clean queue intr-vector mapping */
1338         rte_intr_efd_disable(intr_handle);
1339         if (intr_handle->intr_vec != NULL) {
1340                 rte_free(intr_handle->intr_vec);
1341                 intr_handle->intr_vec = NULL;
1342         }
1343
1344         bnxt_hwrm_port_clr_stats(bp);
1345         bnxt_free_tx_mbufs(bp);
1346         bnxt_free_rx_mbufs(bp);
1347         /* Process any remaining notifications in default completion queue */
1348         bnxt_int_handler(eth_dev);
1349         bnxt_shutdown_nic(bp);
1350         bnxt_hwrm_if_change(bp, false);
1351
1352         rte_free(bp->mark_table);
1353         bp->mark_table = NULL;
1354
1355         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1356         bp->rx_cosq_cnt = 0;
1357         /* All filters are deleted on a port stop. */
1358         if (BNXT_FLOW_XSTATS_EN(bp))
1359                 bp->flow_stat->flow_count = 0;
1360 }
1361
1362 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1363 {
1364         struct bnxt *bp = eth_dev->data->dev_private;
1365
1366         /* cancel the recovery handler before remove dev */
1367         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1368         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1369         bnxt_cancel_fc_thread(bp);
1370
1371         if (eth_dev->data->dev_started)
1372                 bnxt_dev_stop_op(eth_dev);
1373
1374         bnxt_free_switch_domain(bp);
1375
1376         bnxt_uninit_resources(bp, false);
1377
1378         bnxt_free_leds_info(bp);
1379         bnxt_free_cos_queues(bp);
1380         bnxt_free_link_info(bp);
1381         bnxt_free_pf_info(bp);
1382         bnxt_free_parent_info(bp);
1383
1384         eth_dev->dev_ops = NULL;
1385         eth_dev->rx_pkt_burst = NULL;
1386         eth_dev->tx_pkt_burst = NULL;
1387
1388         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1389         bp->tx_mem_zone = NULL;
1390         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1391         bp->rx_mem_zone = NULL;
1392
1393         bnxt_hwrm_free_vf_info(bp);
1394
1395         rte_free(bp->grp_info);
1396         bp->grp_info = NULL;
1397 }
1398
1399 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1400                                     uint32_t index)
1401 {
1402         struct bnxt *bp = eth_dev->data->dev_private;
1403         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1404         struct bnxt_vnic_info *vnic;
1405         struct bnxt_filter_info *filter, *temp_filter;
1406         uint32_t i;
1407
1408         if (is_bnxt_in_error(bp))
1409                 return;
1410
1411         /*
1412          * Loop through all VNICs from the specified filter flow pools to
1413          * remove the corresponding MAC addr filter
1414          */
1415         for (i = 0; i < bp->nr_vnics; i++) {
1416                 if (!(pool_mask & (1ULL << i)))
1417                         continue;
1418
1419                 vnic = &bp->vnic_info[i];
1420                 filter = STAILQ_FIRST(&vnic->filter);
1421                 while (filter) {
1422                         temp_filter = STAILQ_NEXT(filter, next);
1423                         if (filter->mac_index == index) {
1424                                 STAILQ_REMOVE(&vnic->filter, filter,
1425                                                 bnxt_filter_info, next);
1426                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1427                                 bnxt_free_filter(bp, filter);
1428                         }
1429                         filter = temp_filter;
1430                 }
1431         }
1432 }
1433
1434 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1435                                struct rte_ether_addr *mac_addr, uint32_t index,
1436                                uint32_t pool)
1437 {
1438         struct bnxt_filter_info *filter;
1439         int rc = 0;
1440
1441         /* Attach requested MAC address to the new l2_filter */
1442         STAILQ_FOREACH(filter, &vnic->filter, next) {
1443                 if (filter->mac_index == index) {
1444                         PMD_DRV_LOG(DEBUG,
1445                                     "MAC addr already existed for pool %d\n",
1446                                     pool);
1447                         return 0;
1448                 }
1449         }
1450
1451         filter = bnxt_alloc_filter(bp);
1452         if (!filter) {
1453                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1454                 return -ENODEV;
1455         }
1456
1457         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1458          * if the MAC that's been programmed now is a different one, then,
1459          * copy that addr to filter->l2_addr
1460          */
1461         if (mac_addr)
1462                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1463         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1464
1465         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1466         if (!rc) {
1467                 filter->mac_index = index;
1468                 if (filter->mac_index == 0)
1469                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1470                 else
1471                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1472         } else {
1473                 bnxt_free_filter(bp, filter);
1474         }
1475
1476         return rc;
1477 }
1478
1479 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1480                                 struct rte_ether_addr *mac_addr,
1481                                 uint32_t index, uint32_t pool)
1482 {
1483         struct bnxt *bp = eth_dev->data->dev_private;
1484         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1485         int rc = 0;
1486
1487         rc = is_bnxt_in_error(bp);
1488         if (rc)
1489                 return rc;
1490
1491         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1492                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1493                 return -ENOTSUP;
1494         }
1495
1496         if (!vnic) {
1497                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1498                 return -EINVAL;
1499         }
1500
1501         /* Filter settings will get applied when port is started */
1502         if (!eth_dev->data->dev_started)
1503                 return 0;
1504
1505         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1506
1507         return rc;
1508 }
1509
1510 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1511                      bool exp_link_status)
1512 {
1513         int rc = 0;
1514         struct bnxt *bp = eth_dev->data->dev_private;
1515         struct rte_eth_link new;
1516         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1517                   BNXT_LINK_DOWN_WAIT_CNT;
1518
1519         rc = is_bnxt_in_error(bp);
1520         if (rc)
1521                 return rc;
1522
1523         memset(&new, 0, sizeof(new));
1524         do {
1525                 /* Retrieve link info from hardware */
1526                 rc = bnxt_get_hwrm_link_config(bp, &new);
1527                 if (rc) {
1528                         new.link_speed = ETH_LINK_SPEED_100M;
1529                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1530                         PMD_DRV_LOG(ERR,
1531                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1532                         goto out;
1533                 }
1534
1535                 if (!wait_to_complete || new.link_status == exp_link_status)
1536                         break;
1537
1538                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1539         } while (cnt--);
1540
1541 out:
1542         /* Timed out or success */
1543         if (new.link_status != eth_dev->data->dev_link.link_status ||
1544         new.link_speed != eth_dev->data->dev_link.link_speed) {
1545                 rte_eth_linkstatus_set(eth_dev, &new);
1546
1547                 rte_eth_dev_callback_process(eth_dev,
1548                                              RTE_ETH_EVENT_INTR_LSC,
1549                                              NULL);
1550
1551                 bnxt_print_link_info(eth_dev);
1552         }
1553
1554         return rc;
1555 }
1556
1557 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1558                         int wait_to_complete)
1559 {
1560         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1561 }
1562
1563 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1564 {
1565         struct bnxt *bp = eth_dev->data->dev_private;
1566         struct bnxt_vnic_info *vnic;
1567         uint32_t old_flags;
1568         int rc;
1569
1570         rc = is_bnxt_in_error(bp);
1571         if (rc)
1572                 return rc;
1573
1574         /* Filter settings will get applied when port is started */
1575         if (!eth_dev->data->dev_started)
1576                 return 0;
1577
1578         if (bp->vnic_info == NULL)
1579                 return 0;
1580
1581         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1582
1583         old_flags = vnic->flags;
1584         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1585         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1586         if (rc != 0)
1587                 vnic->flags = old_flags;
1588
1589         return rc;
1590 }
1591
1592 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1593 {
1594         struct bnxt *bp = eth_dev->data->dev_private;
1595         struct bnxt_vnic_info *vnic;
1596         uint32_t old_flags;
1597         int rc;
1598
1599         rc = is_bnxt_in_error(bp);
1600         if (rc)
1601                 return rc;
1602
1603         /* Filter settings will get applied when port is started */
1604         if (!eth_dev->data->dev_started)
1605                 return 0;
1606
1607         if (bp->vnic_info == NULL)
1608                 return 0;
1609
1610         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1611
1612         old_flags = vnic->flags;
1613         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1614         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1615         if (rc != 0)
1616                 vnic->flags = old_flags;
1617
1618         return rc;
1619 }
1620
1621 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1622 {
1623         struct bnxt *bp = eth_dev->data->dev_private;
1624         struct bnxt_vnic_info *vnic;
1625         uint32_t old_flags;
1626         int rc;
1627
1628         rc = is_bnxt_in_error(bp);
1629         if (rc)
1630                 return rc;
1631
1632         /* Filter settings will get applied when port is started */
1633         if (!eth_dev->data->dev_started)
1634                 return 0;
1635
1636         if (bp->vnic_info == NULL)
1637                 return 0;
1638
1639         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1640
1641         old_flags = vnic->flags;
1642         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1643         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1644         if (rc != 0)
1645                 vnic->flags = old_flags;
1646
1647         return rc;
1648 }
1649
1650 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1651 {
1652         struct bnxt *bp = eth_dev->data->dev_private;
1653         struct bnxt_vnic_info *vnic;
1654         uint32_t old_flags;
1655         int rc;
1656
1657         rc = is_bnxt_in_error(bp);
1658         if (rc)
1659                 return rc;
1660
1661         /* Filter settings will get applied when port is started */
1662         if (!eth_dev->data->dev_started)
1663                 return 0;
1664
1665         if (bp->vnic_info == NULL)
1666                 return 0;
1667
1668         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1669
1670         old_flags = vnic->flags;
1671         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1672         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1673         if (rc != 0)
1674                 vnic->flags = old_flags;
1675
1676         return rc;
1677 }
1678
1679 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1680 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1681 {
1682         if (qid >= bp->rx_nr_rings)
1683                 return NULL;
1684
1685         return bp->eth_dev->data->rx_queues[qid];
1686 }
1687
1688 /* Return rxq corresponding to a given rss table ring/group ID. */
1689 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1690 {
1691         struct bnxt_rx_queue *rxq;
1692         unsigned int i;
1693
1694         if (!BNXT_HAS_RING_GRPS(bp)) {
1695                 for (i = 0; i < bp->rx_nr_rings; i++) {
1696                         rxq = bp->eth_dev->data->rx_queues[i];
1697                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1698                                 return rxq->index;
1699                 }
1700         } else {
1701                 for (i = 0; i < bp->rx_nr_rings; i++) {
1702                         if (bp->grp_info[i].fw_grp_id == fwr)
1703                                 return i;
1704                 }
1705         }
1706
1707         return INVALID_HW_RING_ID;
1708 }
1709
1710 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1711                             struct rte_eth_rss_reta_entry64 *reta_conf,
1712                             uint16_t reta_size)
1713 {
1714         struct bnxt *bp = eth_dev->data->dev_private;
1715         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1716         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1717         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1718         uint16_t idx, sft;
1719         int i, rc;
1720
1721         rc = is_bnxt_in_error(bp);
1722         if (rc)
1723                 return rc;
1724
1725         if (!vnic->rss_table)
1726                 return -EINVAL;
1727
1728         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1729                 return -EINVAL;
1730
1731         if (reta_size != tbl_size) {
1732                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1733                         "(%d) must equal the size supported by the hardware "
1734                         "(%d)\n", reta_size, tbl_size);
1735                 return -EINVAL;
1736         }
1737
1738         for (i = 0; i < reta_size; i++) {
1739                 struct bnxt_rx_queue *rxq;
1740
1741                 idx = i / RTE_RETA_GROUP_SIZE;
1742                 sft = i % RTE_RETA_GROUP_SIZE;
1743
1744                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1745                         continue;
1746
1747                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1748                 if (!rxq) {
1749                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1750                         return -EINVAL;
1751                 }
1752
1753                 if (BNXT_CHIP_THOR(bp)) {
1754                         vnic->rss_table[i * 2] =
1755                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1756                         vnic->rss_table[i * 2 + 1] =
1757                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1758                 } else {
1759                         vnic->rss_table[i] =
1760                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1761                 }
1762         }
1763
1764         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1765         return 0;
1766 }
1767
1768 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1769                               struct rte_eth_rss_reta_entry64 *reta_conf,
1770                               uint16_t reta_size)
1771 {
1772         struct bnxt *bp = eth_dev->data->dev_private;
1773         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1774         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1775         uint16_t idx, sft, i;
1776         int rc;
1777
1778         rc = is_bnxt_in_error(bp);
1779         if (rc)
1780                 return rc;
1781
1782         /* Retrieve from the default VNIC */
1783         if (!vnic)
1784                 return -EINVAL;
1785         if (!vnic->rss_table)
1786                 return -EINVAL;
1787
1788         if (reta_size != tbl_size) {
1789                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1790                         "(%d) must equal the size supported by the hardware "
1791                         "(%d)\n", reta_size, tbl_size);
1792                 return -EINVAL;
1793         }
1794
1795         for (idx = 0, i = 0; i < reta_size; i++) {
1796                 idx = i / RTE_RETA_GROUP_SIZE;
1797                 sft = i % RTE_RETA_GROUP_SIZE;
1798
1799                 if (reta_conf[idx].mask & (1ULL << sft)) {
1800                         uint16_t qid;
1801
1802                         if (BNXT_CHIP_THOR(bp))
1803                                 qid = bnxt_rss_to_qid(bp,
1804                                                       vnic->rss_table[i * 2]);
1805                         else
1806                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1807
1808                         if (qid == INVALID_HW_RING_ID) {
1809                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1810                                 return -EINVAL;
1811                         }
1812                         reta_conf[idx].reta[sft] = qid;
1813                 }
1814         }
1815
1816         return 0;
1817 }
1818
1819 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1820                                    struct rte_eth_rss_conf *rss_conf)
1821 {
1822         struct bnxt *bp = eth_dev->data->dev_private;
1823         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1824         struct bnxt_vnic_info *vnic;
1825         int rc;
1826
1827         rc = is_bnxt_in_error(bp);
1828         if (rc)
1829                 return rc;
1830
1831         /*
1832          * If RSS enablement were different than dev_configure,
1833          * then return -EINVAL
1834          */
1835         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1836                 if (!rss_conf->rss_hf)
1837                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1838         } else {
1839                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1840                         return -EINVAL;
1841         }
1842
1843         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1844         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1845                rss_conf,
1846                sizeof(*rss_conf));
1847
1848         /* Update the default RSS VNIC(s) */
1849         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1850         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1851
1852         /*
1853          * If hashkey is not specified, use the previously configured
1854          * hashkey
1855          */
1856         if (!rss_conf->rss_key)
1857                 goto rss_config;
1858
1859         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1860                 PMD_DRV_LOG(ERR,
1861                             "Invalid hashkey length, should be 16 bytes\n");
1862                 return -EINVAL;
1863         }
1864         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1865
1866 rss_config:
1867         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1868         return 0;
1869 }
1870
1871 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1872                                      struct rte_eth_rss_conf *rss_conf)
1873 {
1874         struct bnxt *bp = eth_dev->data->dev_private;
1875         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1876         int len, rc;
1877         uint32_t hash_types;
1878
1879         rc = is_bnxt_in_error(bp);
1880         if (rc)
1881                 return rc;
1882
1883         /* RSS configuration is the same for all VNICs */
1884         if (vnic && vnic->rss_hash_key) {
1885                 if (rss_conf->rss_key) {
1886                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1887                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1888                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1889                 }
1890
1891                 hash_types = vnic->hash_type;
1892                 rss_conf->rss_hf = 0;
1893                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1894                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1895                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1896                 }
1897                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1898                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1899                         hash_types &=
1900                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1901                 }
1902                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1903                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1904                         hash_types &=
1905                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1906                 }
1907                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1908                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1909                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1910                 }
1911                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1912                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1913                         hash_types &=
1914                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1915                 }
1916                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1917                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1918                         hash_types &=
1919                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1920                 }
1921                 if (hash_types) {
1922                         PMD_DRV_LOG(ERR,
1923                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1924                                 vnic->hash_type);
1925                         return -ENOTSUP;
1926                 }
1927         } else {
1928                 rss_conf->rss_hf = 0;
1929         }
1930         return 0;
1931 }
1932
1933 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1934                                struct rte_eth_fc_conf *fc_conf)
1935 {
1936         struct bnxt *bp = dev->data->dev_private;
1937         struct rte_eth_link link_info;
1938         int rc;
1939
1940         rc = is_bnxt_in_error(bp);
1941         if (rc)
1942                 return rc;
1943
1944         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1945         if (rc)
1946                 return rc;
1947
1948         memset(fc_conf, 0, sizeof(*fc_conf));
1949         if (bp->link_info->auto_pause)
1950                 fc_conf->autoneg = 1;
1951         switch (bp->link_info->pause) {
1952         case 0:
1953                 fc_conf->mode = RTE_FC_NONE;
1954                 break;
1955         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1956                 fc_conf->mode = RTE_FC_TX_PAUSE;
1957                 break;
1958         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1959                 fc_conf->mode = RTE_FC_RX_PAUSE;
1960                 break;
1961         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1962                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1963                 fc_conf->mode = RTE_FC_FULL;
1964                 break;
1965         }
1966         return 0;
1967 }
1968
1969 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1970                                struct rte_eth_fc_conf *fc_conf)
1971 {
1972         struct bnxt *bp = dev->data->dev_private;
1973         int rc;
1974
1975         rc = is_bnxt_in_error(bp);
1976         if (rc)
1977                 return rc;
1978
1979         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1980                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1981                 return -ENOTSUP;
1982         }
1983
1984         switch (fc_conf->mode) {
1985         case RTE_FC_NONE:
1986                 bp->link_info->auto_pause = 0;
1987                 bp->link_info->force_pause = 0;
1988                 break;
1989         case RTE_FC_RX_PAUSE:
1990                 if (fc_conf->autoneg) {
1991                         bp->link_info->auto_pause =
1992                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1993                         bp->link_info->force_pause = 0;
1994                 } else {
1995                         bp->link_info->auto_pause = 0;
1996                         bp->link_info->force_pause =
1997                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1998                 }
1999                 break;
2000         case RTE_FC_TX_PAUSE:
2001                 if (fc_conf->autoneg) {
2002                         bp->link_info->auto_pause =
2003                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2004                         bp->link_info->force_pause = 0;
2005                 } else {
2006                         bp->link_info->auto_pause = 0;
2007                         bp->link_info->force_pause =
2008                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2009                 }
2010                 break;
2011         case RTE_FC_FULL:
2012                 if (fc_conf->autoneg) {
2013                         bp->link_info->auto_pause =
2014                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2015                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2016                         bp->link_info->force_pause = 0;
2017                 } else {
2018                         bp->link_info->auto_pause = 0;
2019                         bp->link_info->force_pause =
2020                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2021                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2022                 }
2023                 break;
2024         }
2025         return bnxt_set_hwrm_link_config(bp, true);
2026 }
2027
2028 /* Add UDP tunneling port */
2029 static int
2030 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2031                          struct rte_eth_udp_tunnel *udp_tunnel)
2032 {
2033         struct bnxt *bp = eth_dev->data->dev_private;
2034         uint16_t tunnel_type = 0;
2035         int rc = 0;
2036
2037         rc = is_bnxt_in_error(bp);
2038         if (rc)
2039                 return rc;
2040
2041         switch (udp_tunnel->prot_type) {
2042         case RTE_TUNNEL_TYPE_VXLAN:
2043                 if (bp->vxlan_port_cnt) {
2044                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2045                                 udp_tunnel->udp_port);
2046                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2047                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2048                                 return -ENOSPC;
2049                         }
2050                         bp->vxlan_port_cnt++;
2051                         return 0;
2052                 }
2053                 tunnel_type =
2054                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2055                 bp->vxlan_port_cnt++;
2056                 break;
2057         case RTE_TUNNEL_TYPE_GENEVE:
2058                 if (bp->geneve_port_cnt) {
2059                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2060                                 udp_tunnel->udp_port);
2061                         if (bp->geneve_port != udp_tunnel->udp_port) {
2062                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2063                                 return -ENOSPC;
2064                         }
2065                         bp->geneve_port_cnt++;
2066                         return 0;
2067                 }
2068                 tunnel_type =
2069                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2070                 bp->geneve_port_cnt++;
2071                 break;
2072         default:
2073                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2074                 return -ENOTSUP;
2075         }
2076         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2077                                              tunnel_type);
2078         return rc;
2079 }
2080
2081 static int
2082 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2083                          struct rte_eth_udp_tunnel *udp_tunnel)
2084 {
2085         struct bnxt *bp = eth_dev->data->dev_private;
2086         uint16_t tunnel_type = 0;
2087         uint16_t port = 0;
2088         int rc = 0;
2089
2090         rc = is_bnxt_in_error(bp);
2091         if (rc)
2092                 return rc;
2093
2094         switch (udp_tunnel->prot_type) {
2095         case RTE_TUNNEL_TYPE_VXLAN:
2096                 if (!bp->vxlan_port_cnt) {
2097                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2098                         return -EINVAL;
2099                 }
2100                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2101                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2102                                 udp_tunnel->udp_port, bp->vxlan_port);
2103                         return -EINVAL;
2104                 }
2105                 if (--bp->vxlan_port_cnt)
2106                         return 0;
2107
2108                 tunnel_type =
2109                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2110                 port = bp->vxlan_fw_dst_port_id;
2111                 break;
2112         case RTE_TUNNEL_TYPE_GENEVE:
2113                 if (!bp->geneve_port_cnt) {
2114                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2115                         return -EINVAL;
2116                 }
2117                 if (bp->geneve_port != udp_tunnel->udp_port) {
2118                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2119                                 udp_tunnel->udp_port, bp->geneve_port);
2120                         return -EINVAL;
2121                 }
2122                 if (--bp->geneve_port_cnt)
2123                         return 0;
2124
2125                 tunnel_type =
2126                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2127                 port = bp->geneve_fw_dst_port_id;
2128                 break;
2129         default:
2130                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2131                 return -ENOTSUP;
2132         }
2133
2134         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2135         if (!rc) {
2136                 if (tunnel_type ==
2137                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2138                         bp->vxlan_port = 0;
2139                 if (tunnel_type ==
2140                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2141                         bp->geneve_port = 0;
2142         }
2143         return rc;
2144 }
2145
2146 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2147 {
2148         struct bnxt_filter_info *filter;
2149         struct bnxt_vnic_info *vnic;
2150         int rc = 0;
2151         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2152
2153         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2154         filter = STAILQ_FIRST(&vnic->filter);
2155         while (filter) {
2156                 /* Search for this matching MAC+VLAN filter */
2157                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2158                         /* Delete the filter */
2159                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2160                         if (rc)
2161                                 return rc;
2162                         STAILQ_REMOVE(&vnic->filter, filter,
2163                                       bnxt_filter_info, next);
2164                         bnxt_free_filter(bp, filter);
2165                         PMD_DRV_LOG(INFO,
2166                                     "Deleted vlan filter for %d\n",
2167                                     vlan_id);
2168                         return 0;
2169                 }
2170                 filter = STAILQ_NEXT(filter, next);
2171         }
2172         return -ENOENT;
2173 }
2174
2175 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2176 {
2177         struct bnxt_filter_info *filter;
2178         struct bnxt_vnic_info *vnic;
2179         int rc = 0;
2180         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2181                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2182         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2183
2184         /* Implementation notes on the use of VNIC in this command:
2185          *
2186          * By default, these filters belong to default vnic for the function.
2187          * Once these filters are set up, only destination VNIC can be modified.
2188          * If the destination VNIC is not specified in this command,
2189          * then the HWRM shall only create an l2 context id.
2190          */
2191
2192         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2193         filter = STAILQ_FIRST(&vnic->filter);
2194         /* Check if the VLAN has already been added */
2195         while (filter) {
2196                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2197                         return -EEXIST;
2198
2199                 filter = STAILQ_NEXT(filter, next);
2200         }
2201
2202         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2203          * command to create MAC+VLAN filter with the right flags, enables set.
2204          */
2205         filter = bnxt_alloc_filter(bp);
2206         if (!filter) {
2207                 PMD_DRV_LOG(ERR,
2208                             "MAC/VLAN filter alloc failed\n");
2209                 return -ENOMEM;
2210         }
2211         /* MAC + VLAN ID filter */
2212         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2213          * untagged packets are received
2214          *
2215          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2216          * packets and only the programmed vlan's packets are received
2217          */
2218         filter->l2_ivlan = vlan_id;
2219         filter->l2_ivlan_mask = 0x0FFF;
2220         filter->enables |= en;
2221         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2222
2223         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2224         if (rc) {
2225                 /* Free the newly allocated filter as we were
2226                  * not able to create the filter in hardware.
2227                  */
2228                 bnxt_free_filter(bp, filter);
2229                 return rc;
2230         }
2231
2232         filter->mac_index = 0;
2233         /* Add this new filter to the list */
2234         if (vlan_id == 0)
2235                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2236         else
2237                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2238
2239         PMD_DRV_LOG(INFO,
2240                     "Added Vlan filter for %d\n", vlan_id);
2241         return rc;
2242 }
2243
2244 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2245                 uint16_t vlan_id, int on)
2246 {
2247         struct bnxt *bp = eth_dev->data->dev_private;
2248         int rc;
2249
2250         rc = is_bnxt_in_error(bp);
2251         if (rc)
2252                 return rc;
2253
2254         if (!eth_dev->data->dev_started) {
2255                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2256                 return -EINVAL;
2257         }
2258
2259         /* These operations apply to ALL existing MAC/VLAN filters */
2260         if (on)
2261                 return bnxt_add_vlan_filter(bp, vlan_id);
2262         else
2263                 return bnxt_del_vlan_filter(bp, vlan_id);
2264 }
2265
2266 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2267                                     struct bnxt_vnic_info *vnic)
2268 {
2269         struct bnxt_filter_info *filter;
2270         int rc;
2271
2272         filter = STAILQ_FIRST(&vnic->filter);
2273         while (filter) {
2274                 if (filter->mac_index == 0 &&
2275                     !memcmp(filter->l2_addr, bp->mac_addr,
2276                             RTE_ETHER_ADDR_LEN)) {
2277                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2278                         if (!rc) {
2279                                 STAILQ_REMOVE(&vnic->filter, filter,
2280                                               bnxt_filter_info, next);
2281                                 bnxt_free_filter(bp, filter);
2282                         }
2283                         return rc;
2284                 }
2285                 filter = STAILQ_NEXT(filter, next);
2286         }
2287         return 0;
2288 }
2289
2290 static int
2291 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2292 {
2293         struct bnxt_vnic_info *vnic;
2294         unsigned int i;
2295         int rc;
2296
2297         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2298         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2299                 /* Remove any VLAN filters programmed */
2300                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2301                         bnxt_del_vlan_filter(bp, i);
2302
2303                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2304                 if (rc)
2305                         return rc;
2306         } else {
2307                 /* Default filter will allow packets that match the
2308                  * dest mac. So, it has to be deleted, otherwise, we
2309                  * will endup receiving vlan packets for which the
2310                  * filter is not programmed, when hw-vlan-filter
2311                  * configuration is ON
2312                  */
2313                 bnxt_del_dflt_mac_filter(bp, vnic);
2314                 /* This filter will allow only untagged packets */
2315                 bnxt_add_vlan_filter(bp, 0);
2316         }
2317         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2318                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2319
2320         return 0;
2321 }
2322
2323 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2324 {
2325         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2326         unsigned int i;
2327         int rc;
2328
2329         /* Destroy vnic filters and vnic */
2330         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2331             DEV_RX_OFFLOAD_VLAN_FILTER) {
2332                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2333                         bnxt_del_vlan_filter(bp, i);
2334         }
2335         bnxt_del_dflt_mac_filter(bp, vnic);
2336
2337         rc = bnxt_hwrm_vnic_free(bp, vnic);
2338         if (rc)
2339                 return rc;
2340
2341         rte_free(vnic->fw_grp_ids);
2342         vnic->fw_grp_ids = NULL;
2343
2344         vnic->rx_queue_cnt = 0;
2345
2346         return 0;
2347 }
2348
2349 static int
2350 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2351 {
2352         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2353         int rc;
2354
2355         /* Destroy, recreate and reconfigure the default vnic */
2356         rc = bnxt_free_one_vnic(bp, 0);
2357         if (rc)
2358                 return rc;
2359
2360         /* default vnic 0 */
2361         rc = bnxt_setup_one_vnic(bp, 0);
2362         if (rc)
2363                 return rc;
2364
2365         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2366             DEV_RX_OFFLOAD_VLAN_FILTER) {
2367                 rc = bnxt_add_vlan_filter(bp, 0);
2368                 if (rc)
2369                         return rc;
2370                 rc = bnxt_restore_vlan_filters(bp);
2371                 if (rc)
2372                         return rc;
2373         } else {
2374                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2375                 if (rc)
2376                         return rc;
2377         }
2378
2379         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2380         if (rc)
2381                 return rc;
2382
2383         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2384                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2385
2386         return rc;
2387 }
2388
2389 static int
2390 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2391 {
2392         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2393         struct bnxt *bp = dev->data->dev_private;
2394         int rc;
2395
2396         rc = is_bnxt_in_error(bp);
2397         if (rc)
2398                 return rc;
2399
2400         /* Filter settings will get applied when port is started */
2401         if (!dev->data->dev_started)
2402                 return 0;
2403
2404         if (mask & ETH_VLAN_FILTER_MASK) {
2405                 /* Enable or disable VLAN filtering */
2406                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2407                 if (rc)
2408                         return rc;
2409         }
2410
2411         if (mask & ETH_VLAN_STRIP_MASK) {
2412                 /* Enable or disable VLAN stripping */
2413                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2414                 if (rc)
2415                         return rc;
2416         }
2417
2418         if (mask & ETH_VLAN_EXTEND_MASK) {
2419                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2420                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2421                 else
2422                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2423         }
2424
2425         return 0;
2426 }
2427
2428 static int
2429 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2430                       uint16_t tpid)
2431 {
2432         struct bnxt *bp = dev->data->dev_private;
2433         int qinq = dev->data->dev_conf.rxmode.offloads &
2434                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2435
2436         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2437             vlan_type != ETH_VLAN_TYPE_OUTER) {
2438                 PMD_DRV_LOG(ERR,
2439                             "Unsupported vlan type.");
2440                 return -EINVAL;
2441         }
2442         if (!qinq) {
2443                 PMD_DRV_LOG(ERR,
2444                             "QinQ not enabled. Needs to be ON as we can "
2445                             "accelerate only outer vlan\n");
2446                 return -EINVAL;
2447         }
2448
2449         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2450                 switch (tpid) {
2451                 case RTE_ETHER_TYPE_QINQ:
2452                         bp->outer_tpid_bd =
2453                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2454                                 break;
2455                 case RTE_ETHER_TYPE_VLAN:
2456                         bp->outer_tpid_bd =
2457                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2458                                 break;
2459                 case RTE_ETHER_TYPE_QINQ1:
2460                         bp->outer_tpid_bd =
2461                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2462                                 break;
2463                 case RTE_ETHER_TYPE_QINQ2:
2464                         bp->outer_tpid_bd =
2465                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2466                                 break;
2467                 case RTE_ETHER_TYPE_QINQ3:
2468                         bp->outer_tpid_bd =
2469                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2470                                 break;
2471                 default:
2472                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2473                         return -EINVAL;
2474                 }
2475                 bp->outer_tpid_bd |= tpid;
2476                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2477         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2478                 PMD_DRV_LOG(ERR,
2479                             "Can accelerate only outer vlan in QinQ\n");
2480                 return -EINVAL;
2481         }
2482
2483         return 0;
2484 }
2485
2486 static int
2487 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2488                              struct rte_ether_addr *addr)
2489 {
2490         struct bnxt *bp = dev->data->dev_private;
2491         /* Default Filter is tied to VNIC 0 */
2492         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2493         int rc;
2494
2495         rc = is_bnxt_in_error(bp);
2496         if (rc)
2497                 return rc;
2498
2499         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2500                 return -EPERM;
2501
2502         if (rte_is_zero_ether_addr(addr))
2503                 return -EINVAL;
2504
2505         /* Filter settings will get applied when port is started */
2506         if (!dev->data->dev_started)
2507                 return 0;
2508
2509         /* Check if the requested MAC is already added */
2510         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2511                 return 0;
2512
2513         /* Destroy filter and re-create it */
2514         bnxt_del_dflt_mac_filter(bp, vnic);
2515
2516         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2517         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2518                 /* This filter will allow only untagged packets */
2519                 rc = bnxt_add_vlan_filter(bp, 0);
2520         } else {
2521                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2522         }
2523
2524         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2525         return rc;
2526 }
2527
2528 static int
2529 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2530                           struct rte_ether_addr *mc_addr_set,
2531                           uint32_t nb_mc_addr)
2532 {
2533         struct bnxt *bp = eth_dev->data->dev_private;
2534         char *mc_addr_list = (char *)mc_addr_set;
2535         struct bnxt_vnic_info *vnic;
2536         uint32_t off = 0, i = 0;
2537         int rc;
2538
2539         rc = is_bnxt_in_error(bp);
2540         if (rc)
2541                 return rc;
2542
2543         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2544
2545         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2546                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2547                 goto allmulti;
2548         }
2549
2550         /* TODO Check for Duplicate mcast addresses */
2551         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2552         for (i = 0; i < nb_mc_addr; i++) {
2553                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2554                         RTE_ETHER_ADDR_LEN);
2555                 off += RTE_ETHER_ADDR_LEN;
2556         }
2557
2558         vnic->mc_addr_cnt = i;
2559         if (vnic->mc_addr_cnt)
2560                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2561         else
2562                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2563
2564 allmulti:
2565         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2566 }
2567
2568 static int
2569 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2570 {
2571         struct bnxt *bp = dev->data->dev_private;
2572         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2573         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2574         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2575         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2576         int ret;
2577
2578         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2579                         fw_major, fw_minor, fw_updt, fw_rsvd);
2580
2581         ret += 1; /* add the size of '\0' */
2582         if (fw_size < (uint32_t)ret)
2583                 return ret;
2584         else
2585                 return 0;
2586 }
2587
2588 static void
2589 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2590         struct rte_eth_rxq_info *qinfo)
2591 {
2592         struct bnxt *bp = dev->data->dev_private;
2593         struct bnxt_rx_queue *rxq;
2594
2595         if (is_bnxt_in_error(bp))
2596                 return;
2597
2598         rxq = dev->data->rx_queues[queue_id];
2599
2600         qinfo->mp = rxq->mb_pool;
2601         qinfo->scattered_rx = dev->data->scattered_rx;
2602         qinfo->nb_desc = rxq->nb_rx_desc;
2603
2604         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2605         qinfo->conf.rx_drop_en = 0;
2606         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2607 }
2608
2609 static void
2610 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2611         struct rte_eth_txq_info *qinfo)
2612 {
2613         struct bnxt *bp = dev->data->dev_private;
2614         struct bnxt_tx_queue *txq;
2615
2616         if (is_bnxt_in_error(bp))
2617                 return;
2618
2619         txq = dev->data->tx_queues[queue_id];
2620
2621         qinfo->nb_desc = txq->nb_tx_desc;
2622
2623         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2624         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2625         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2626
2627         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2628         qinfo->conf.tx_rs_thresh = 0;
2629         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2630 }
2631
2632 static const struct {
2633         eth_rx_burst_t pkt_burst;
2634         const char *info;
2635 } bnxt_rx_burst_info[] = {
2636         {bnxt_recv_pkts,        "Scalar"},
2637 #if defined(RTE_ARCH_X86)
2638         {bnxt_recv_pkts_vec,    "Vector SSE"},
2639 #elif defined(RTE_ARCH_ARM64)
2640         {bnxt_recv_pkts_vec,    "Vector Neon"},
2641 #endif
2642 };
2643
2644 static int
2645 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2646                        struct rte_eth_burst_mode *mode)
2647 {
2648         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2649         size_t i;
2650
2651         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2652                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2653                         snprintf(mode->info, sizeof(mode->info), "%s",
2654                                  bnxt_rx_burst_info[i].info);
2655                         return 0;
2656                 }
2657         }
2658
2659         return -EINVAL;
2660 }
2661
2662 static const struct {
2663         eth_tx_burst_t pkt_burst;
2664         const char *info;
2665 } bnxt_tx_burst_info[] = {
2666         {bnxt_xmit_pkts,        "Scalar"},
2667 #if defined(RTE_ARCH_X86)
2668         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2669 #elif defined(RTE_ARCH_ARM64)
2670         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2671 #endif
2672 };
2673
2674 static int
2675 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2676                        struct rte_eth_burst_mode *mode)
2677 {
2678         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2679         size_t i;
2680
2681         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2682                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2683                         snprintf(mode->info, sizeof(mode->info), "%s",
2684                                  bnxt_tx_burst_info[i].info);
2685                         return 0;
2686                 }
2687         }
2688
2689         return -EINVAL;
2690 }
2691
2692 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2693 {
2694         struct bnxt *bp = eth_dev->data->dev_private;
2695         uint32_t new_pkt_size;
2696         uint32_t rc = 0;
2697         uint32_t i;
2698
2699         rc = is_bnxt_in_error(bp);
2700         if (rc)
2701                 return rc;
2702
2703         /* Exit if receive queues are not configured yet */
2704         if (!eth_dev->data->nb_rx_queues)
2705                 return rc;
2706
2707         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2708                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2709
2710         /*
2711          * Disallow any MTU change that would require scattered receive support
2712          * if it is not already enabled.
2713          */
2714         if (eth_dev->data->dev_started &&
2715             !eth_dev->data->scattered_rx &&
2716             (new_pkt_size >
2717              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2718                 PMD_DRV_LOG(ERR,
2719                             "MTU change would require scattered rx support. ");
2720                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2721                 return -EINVAL;
2722         }
2723
2724         if (new_mtu > RTE_ETHER_MTU) {
2725                 bp->flags |= BNXT_FLAG_JUMBO;
2726                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2727                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2728         } else {
2729                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2730                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2731                 bp->flags &= ~BNXT_FLAG_JUMBO;
2732         }
2733
2734         /* Is there a change in mtu setting? */
2735         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2736                 return rc;
2737
2738         for (i = 0; i < bp->nr_vnics; i++) {
2739                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2740                 uint16_t size = 0;
2741
2742                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2743                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2744                 if (rc)
2745                         break;
2746
2747                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2748                 size -= RTE_PKTMBUF_HEADROOM;
2749
2750                 if (size < new_mtu) {
2751                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2752                         if (rc)
2753                                 return rc;
2754                 }
2755         }
2756
2757         if (!rc)
2758                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2759
2760         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2761
2762         return rc;
2763 }
2764
2765 static int
2766 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2767 {
2768         struct bnxt *bp = dev->data->dev_private;
2769         uint16_t vlan = bp->vlan;
2770         int rc;
2771
2772         rc = is_bnxt_in_error(bp);
2773         if (rc)
2774                 return rc;
2775
2776         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2777                 PMD_DRV_LOG(ERR,
2778                         "PVID cannot be modified for this function\n");
2779                 return -ENOTSUP;
2780         }
2781         bp->vlan = on ? pvid : 0;
2782
2783         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2784         if (rc)
2785                 bp->vlan = vlan;
2786         return rc;
2787 }
2788
2789 static int
2790 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2791 {
2792         struct bnxt *bp = dev->data->dev_private;
2793         int rc;
2794
2795         rc = is_bnxt_in_error(bp);
2796         if (rc)
2797                 return rc;
2798
2799         return bnxt_hwrm_port_led_cfg(bp, true);
2800 }
2801
2802 static int
2803 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2804 {
2805         struct bnxt *bp = dev->data->dev_private;
2806         int rc;
2807
2808         rc = is_bnxt_in_error(bp);
2809         if (rc)
2810                 return rc;
2811
2812         return bnxt_hwrm_port_led_cfg(bp, false);
2813 }
2814
2815 static uint32_t
2816 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2817 {
2818         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2819         uint32_t desc = 0, raw_cons = 0, cons;
2820         struct bnxt_cp_ring_info *cpr;
2821         struct bnxt_rx_queue *rxq;
2822         struct rx_pkt_cmpl *rxcmp;
2823         int rc;
2824
2825         rc = is_bnxt_in_error(bp);
2826         if (rc)
2827                 return rc;
2828
2829         rxq = dev->data->rx_queues[rx_queue_id];
2830         cpr = rxq->cp_ring;
2831         raw_cons = cpr->cp_raw_cons;
2832
2833         while (1) {
2834                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2835                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2836                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2837
2838                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2839                         break;
2840                 } else {
2841                         raw_cons++;
2842                         desc++;
2843                 }
2844         }
2845
2846         return desc;
2847 }
2848
2849 static int
2850 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2851 {
2852         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2853         struct bnxt_rx_ring_info *rxr;
2854         struct bnxt_cp_ring_info *cpr;
2855         struct rte_mbuf *rx_buf;
2856         struct rx_pkt_cmpl *rxcmp;
2857         uint32_t cons, cp_cons;
2858         int rc;
2859
2860         if (!rxq)
2861                 return -EINVAL;
2862
2863         rc = is_bnxt_in_error(rxq->bp);
2864         if (rc)
2865                 return rc;
2866
2867         cpr = rxq->cp_ring;
2868         rxr = rxq->rx_ring;
2869
2870         if (offset >= rxq->nb_rx_desc)
2871                 return -EINVAL;
2872
2873         cons = RING_CMP(cpr->cp_ring_struct, offset);
2874         cp_cons = cpr->cp_raw_cons;
2875         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2876
2877         if (cons > cp_cons) {
2878                 if (CMPL_VALID(rxcmp, cpr->valid))
2879                         return RTE_ETH_RX_DESC_DONE;
2880         } else {
2881                 if (CMPL_VALID(rxcmp, !cpr->valid))
2882                         return RTE_ETH_RX_DESC_DONE;
2883         }
2884         rx_buf = rxr->rx_buf_ring[cons];
2885         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2886                 return RTE_ETH_RX_DESC_UNAVAIL;
2887
2888
2889         return RTE_ETH_RX_DESC_AVAIL;
2890 }
2891
2892 static int
2893 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2894 {
2895         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2896         struct bnxt_tx_ring_info *txr;
2897         struct bnxt_cp_ring_info *cpr;
2898         struct bnxt_sw_tx_bd *tx_buf;
2899         struct tx_pkt_cmpl *txcmp;
2900         uint32_t cons, cp_cons;
2901         int rc;
2902
2903         if (!txq)
2904                 return -EINVAL;
2905
2906         rc = is_bnxt_in_error(txq->bp);
2907         if (rc)
2908                 return rc;
2909
2910         cpr = txq->cp_ring;
2911         txr = txq->tx_ring;
2912
2913         if (offset >= txq->nb_tx_desc)
2914                 return -EINVAL;
2915
2916         cons = RING_CMP(cpr->cp_ring_struct, offset);
2917         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2918         cp_cons = cpr->cp_raw_cons;
2919
2920         if (cons > cp_cons) {
2921                 if (CMPL_VALID(txcmp, cpr->valid))
2922                         return RTE_ETH_TX_DESC_UNAVAIL;
2923         } else {
2924                 if (CMPL_VALID(txcmp, !cpr->valid))
2925                         return RTE_ETH_TX_DESC_UNAVAIL;
2926         }
2927         tx_buf = &txr->tx_buf_ring[cons];
2928         if (tx_buf->mbuf == NULL)
2929                 return RTE_ETH_TX_DESC_DONE;
2930
2931         return RTE_ETH_TX_DESC_FULL;
2932 }
2933
2934 static struct bnxt_filter_info *
2935 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2936                                 struct rte_eth_ethertype_filter *efilter,
2937                                 struct bnxt_vnic_info *vnic0,
2938                                 struct bnxt_vnic_info *vnic,
2939                                 int *ret)
2940 {
2941         struct bnxt_filter_info *mfilter = NULL;
2942         int match = 0;
2943         *ret = 0;
2944
2945         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2946                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2947                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2948                         " ethertype filter.", efilter->ether_type);
2949                 *ret = -EINVAL;
2950                 goto exit;
2951         }
2952         if (efilter->queue >= bp->rx_nr_rings) {
2953                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2954                 *ret = -EINVAL;
2955                 goto exit;
2956         }
2957
2958         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2959         vnic = &bp->vnic_info[efilter->queue];
2960         if (vnic == NULL) {
2961                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2962                 *ret = -EINVAL;
2963                 goto exit;
2964         }
2965
2966         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2967                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2968                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2969                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2970                              mfilter->flags ==
2971                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2972                              mfilter->ethertype == efilter->ether_type)) {
2973                                 match = 1;
2974                                 break;
2975                         }
2976                 }
2977         } else {
2978                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2979                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2980                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2981                              mfilter->ethertype == efilter->ether_type &&
2982                              mfilter->flags ==
2983                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2984                                 match = 1;
2985                                 break;
2986                         }
2987         }
2988
2989         if (match)
2990                 *ret = -EEXIST;
2991
2992 exit:
2993         return mfilter;
2994 }
2995
2996 static int
2997 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2998                         enum rte_filter_op filter_op,
2999                         void *arg)
3000 {
3001         struct bnxt *bp = dev->data->dev_private;
3002         struct rte_eth_ethertype_filter *efilter =
3003                         (struct rte_eth_ethertype_filter *)arg;
3004         struct bnxt_filter_info *bfilter, *filter1;
3005         struct bnxt_vnic_info *vnic, *vnic0;
3006         int ret;
3007
3008         if (filter_op == RTE_ETH_FILTER_NOP)
3009                 return 0;
3010
3011         if (arg == NULL) {
3012                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3013                             filter_op);
3014                 return -EINVAL;
3015         }
3016
3017         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3018         vnic = &bp->vnic_info[efilter->queue];
3019
3020         switch (filter_op) {
3021         case RTE_ETH_FILTER_ADD:
3022                 bnxt_match_and_validate_ether_filter(bp, efilter,
3023                                                         vnic0, vnic, &ret);
3024                 if (ret < 0)
3025                         return ret;
3026
3027                 bfilter = bnxt_get_unused_filter(bp);
3028                 if (bfilter == NULL) {
3029                         PMD_DRV_LOG(ERR,
3030                                 "Not enough resources for a new filter.\n");
3031                         return -ENOMEM;
3032                 }
3033                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3034                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3035                        RTE_ETHER_ADDR_LEN);
3036                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3037                        RTE_ETHER_ADDR_LEN);
3038                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3039                 bfilter->ethertype = efilter->ether_type;
3040                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3041
3042                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3043                 if (filter1 == NULL) {
3044                         ret = -EINVAL;
3045                         goto cleanup;
3046                 }
3047                 bfilter->enables |=
3048                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3049                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3050
3051                 bfilter->dst_id = vnic->fw_vnic_id;
3052
3053                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3054                         bfilter->flags =
3055                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3056                 }
3057
3058                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3059                 if (ret)
3060                         goto cleanup;
3061                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3062                 break;
3063         case RTE_ETH_FILTER_DELETE:
3064                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3065                                                         vnic0, vnic, &ret);
3066                 if (ret == -EEXIST) {
3067                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3068
3069                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3070                                       next);
3071                         bnxt_free_filter(bp, filter1);
3072                 } else if (ret == 0) {
3073                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3074                 }
3075                 break;
3076         default:
3077                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3078                 ret = -EINVAL;
3079                 goto error;
3080         }
3081         return ret;
3082 cleanup:
3083         bnxt_free_filter(bp, bfilter);
3084 error:
3085         return ret;
3086 }
3087
3088 static inline int
3089 parse_ntuple_filter(struct bnxt *bp,
3090                     struct rte_eth_ntuple_filter *nfilter,
3091                     struct bnxt_filter_info *bfilter)
3092 {
3093         uint32_t en = 0;
3094
3095         if (nfilter->queue >= bp->rx_nr_rings) {
3096                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3097                 return -EINVAL;
3098         }
3099
3100         switch (nfilter->dst_port_mask) {
3101         case UINT16_MAX:
3102                 bfilter->dst_port_mask = -1;
3103                 bfilter->dst_port = nfilter->dst_port;
3104                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3105                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3106                 break;
3107         default:
3108                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3109                 return -EINVAL;
3110         }
3111
3112         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3113         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3114
3115         switch (nfilter->proto_mask) {
3116         case UINT8_MAX:
3117                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3118                         bfilter->ip_protocol = 17;
3119                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3120                         bfilter->ip_protocol = 6;
3121                 else
3122                         return -EINVAL;
3123                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3124                 break;
3125         default:
3126                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3127                 return -EINVAL;
3128         }
3129
3130         switch (nfilter->dst_ip_mask) {
3131         case UINT32_MAX:
3132                 bfilter->dst_ipaddr_mask[0] = -1;
3133                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3134                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3135                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3136                 break;
3137         default:
3138                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3139                 return -EINVAL;
3140         }
3141
3142         switch (nfilter->src_ip_mask) {
3143         case UINT32_MAX:
3144                 bfilter->src_ipaddr_mask[0] = -1;
3145                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3146                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3147                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3148                 break;
3149         default:
3150                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3151                 return -EINVAL;
3152         }
3153
3154         switch (nfilter->src_port_mask) {
3155         case UINT16_MAX:
3156                 bfilter->src_port_mask = -1;
3157                 bfilter->src_port = nfilter->src_port;
3158                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3159                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3160                 break;
3161         default:
3162                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3163                 return -EINVAL;
3164         }
3165
3166         bfilter->enables = en;
3167         return 0;
3168 }
3169
3170 static struct bnxt_filter_info*
3171 bnxt_match_ntuple_filter(struct bnxt *bp,
3172                          struct bnxt_filter_info *bfilter,
3173                          struct bnxt_vnic_info **mvnic)
3174 {
3175         struct bnxt_filter_info *mfilter = NULL;
3176         int i;
3177
3178         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3179                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3180                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3181                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3182                             bfilter->src_ipaddr_mask[0] ==
3183                             mfilter->src_ipaddr_mask[0] &&
3184                             bfilter->src_port == mfilter->src_port &&
3185                             bfilter->src_port_mask == mfilter->src_port_mask &&
3186                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3187                             bfilter->dst_ipaddr_mask[0] ==
3188                             mfilter->dst_ipaddr_mask[0] &&
3189                             bfilter->dst_port == mfilter->dst_port &&
3190                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3191                             bfilter->flags == mfilter->flags &&
3192                             bfilter->enables == mfilter->enables) {
3193                                 if (mvnic)
3194                                         *mvnic = vnic;
3195                                 return mfilter;
3196                         }
3197                 }
3198         }
3199         return NULL;
3200 }
3201
3202 static int
3203 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3204                        struct rte_eth_ntuple_filter *nfilter,
3205                        enum rte_filter_op filter_op)
3206 {
3207         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3208         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3209         int ret;
3210
3211         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3212                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3213                 return -EINVAL;
3214         }
3215
3216         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3217                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3218                 return -EINVAL;
3219         }
3220
3221         bfilter = bnxt_get_unused_filter(bp);
3222         if (bfilter == NULL) {
3223                 PMD_DRV_LOG(ERR,
3224                         "Not enough resources for a new filter.\n");
3225                 return -ENOMEM;
3226         }
3227         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3228         if (ret < 0)
3229                 goto free_filter;
3230
3231         vnic = &bp->vnic_info[nfilter->queue];
3232         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3233         filter1 = STAILQ_FIRST(&vnic0->filter);
3234         if (filter1 == NULL) {
3235                 ret = -EINVAL;
3236                 goto free_filter;
3237         }
3238
3239         bfilter->dst_id = vnic->fw_vnic_id;
3240         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3241         bfilter->enables |=
3242                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3243         bfilter->ethertype = 0x800;
3244         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3245
3246         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3247
3248         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3249             bfilter->dst_id == mfilter->dst_id) {
3250                 PMD_DRV_LOG(ERR, "filter exists.\n");
3251                 ret = -EEXIST;
3252                 goto free_filter;
3253         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3254                    bfilter->dst_id != mfilter->dst_id) {
3255                 mfilter->dst_id = vnic->fw_vnic_id;
3256                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3257                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3258                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3259                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3260                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3261                 goto free_filter;
3262         }
3263         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3264                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3265                 ret = -ENOENT;
3266                 goto free_filter;
3267         }
3268
3269         if (filter_op == RTE_ETH_FILTER_ADD) {
3270                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3271                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3272                 if (ret)
3273                         goto free_filter;
3274                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3275         } else {
3276                 if (mfilter == NULL) {
3277                         /* This should not happen. But for Coverity! */
3278                         ret = -ENOENT;
3279                         goto free_filter;
3280                 }
3281                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3282
3283                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3284                 bnxt_free_filter(bp, mfilter);
3285                 bnxt_free_filter(bp, bfilter);
3286         }
3287
3288         return 0;
3289 free_filter:
3290         bnxt_free_filter(bp, bfilter);
3291         return ret;
3292 }
3293
3294 static int
3295 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3296                         enum rte_filter_op filter_op,
3297                         void *arg)
3298 {
3299         struct bnxt *bp = dev->data->dev_private;
3300         int ret;
3301
3302         if (filter_op == RTE_ETH_FILTER_NOP)
3303                 return 0;
3304
3305         if (arg == NULL) {
3306                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3307                             filter_op);
3308                 return -EINVAL;
3309         }
3310
3311         switch (filter_op) {
3312         case RTE_ETH_FILTER_ADD:
3313                 ret = bnxt_cfg_ntuple_filter(bp,
3314                         (struct rte_eth_ntuple_filter *)arg,
3315                         filter_op);
3316                 break;
3317         case RTE_ETH_FILTER_DELETE:
3318                 ret = bnxt_cfg_ntuple_filter(bp,
3319                         (struct rte_eth_ntuple_filter *)arg,
3320                         filter_op);
3321                 break;
3322         default:
3323                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3324                 ret = -EINVAL;
3325                 break;
3326         }
3327         return ret;
3328 }
3329
3330 static int
3331 bnxt_parse_fdir_filter(struct bnxt *bp,
3332                        struct rte_eth_fdir_filter *fdir,
3333                        struct bnxt_filter_info *filter)
3334 {
3335         enum rte_fdir_mode fdir_mode =
3336                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3337         struct bnxt_vnic_info *vnic0, *vnic;
3338         struct bnxt_filter_info *filter1;
3339         uint32_t en = 0;
3340         int i;
3341
3342         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3343                 return -EINVAL;
3344
3345         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3346         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3347
3348         switch (fdir->input.flow_type) {
3349         case RTE_ETH_FLOW_IPV4:
3350         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3351                 /* FALLTHROUGH */
3352                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3353                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3354                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3355                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3356                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3357                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3358                 filter->ip_addr_type =
3359                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3360                 filter->src_ipaddr_mask[0] = 0xffffffff;
3361                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3362                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3363                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3364                 filter->ethertype = 0x800;
3365                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3366                 break;
3367         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3368                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3369                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3370                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3371                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3372                 filter->dst_port_mask = 0xffff;
3373                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3374                 filter->src_port_mask = 0xffff;
3375                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3376                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3377                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3378                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3379                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3380                 filter->ip_protocol = 6;
3381                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3382                 filter->ip_addr_type =
3383                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3384                 filter->src_ipaddr_mask[0] = 0xffffffff;
3385                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3386                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3387                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3388                 filter->ethertype = 0x800;
3389                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3390                 break;
3391         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3392                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3393                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3394                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3395                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3396                 filter->dst_port_mask = 0xffff;
3397                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3398                 filter->src_port_mask = 0xffff;
3399                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3400                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3401                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3402                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3403                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3404                 filter->ip_protocol = 17;
3405                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3406                 filter->ip_addr_type =
3407                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3408                 filter->src_ipaddr_mask[0] = 0xffffffff;
3409                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3410                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3411                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3412                 filter->ethertype = 0x800;
3413                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3414                 break;
3415         case RTE_ETH_FLOW_IPV6:
3416         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3417                 /* FALLTHROUGH */
3418                 filter->ip_addr_type =
3419                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3420                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3421                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3422                 rte_memcpy(filter->src_ipaddr,
3423                            fdir->input.flow.ipv6_flow.src_ip, 16);
3424                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3425                 rte_memcpy(filter->dst_ipaddr,
3426                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3427                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3428                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3429                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3430                 memset(filter->src_ipaddr_mask, 0xff, 16);
3431                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3432                 filter->ethertype = 0x86dd;
3433                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3434                 break;
3435         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3436                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3437                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3438                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3439                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3440                 filter->dst_port_mask = 0xffff;
3441                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3442                 filter->src_port_mask = 0xffff;
3443                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3444                 filter->ip_addr_type =
3445                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3446                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3447                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3448                 rte_memcpy(filter->src_ipaddr,
3449                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3450                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3451                 rte_memcpy(filter->dst_ipaddr,
3452                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3453                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3454                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3455                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3456                 memset(filter->src_ipaddr_mask, 0xff, 16);
3457                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3458                 filter->ethertype = 0x86dd;
3459                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3460                 break;
3461         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3462                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3463                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3464                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3465                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3466                 filter->dst_port_mask = 0xffff;
3467                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3468                 filter->src_port_mask = 0xffff;
3469                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3470                 filter->ip_addr_type =
3471                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3472                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3473                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3474                 rte_memcpy(filter->src_ipaddr,
3475                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3476                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3477                 rte_memcpy(filter->dst_ipaddr,
3478                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3479                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3480                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3481                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3482                 memset(filter->src_ipaddr_mask, 0xff, 16);
3483                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3484                 filter->ethertype = 0x86dd;
3485                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3486                 break;
3487         case RTE_ETH_FLOW_L2_PAYLOAD:
3488                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3489                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3490                 break;
3491         case RTE_ETH_FLOW_VXLAN:
3492                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3493                         return -EINVAL;
3494                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3495                 filter->tunnel_type =
3496                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3497                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3498                 break;
3499         case RTE_ETH_FLOW_NVGRE:
3500                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3501                         return -EINVAL;
3502                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3503                 filter->tunnel_type =
3504                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3505                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3506                 break;
3507         case RTE_ETH_FLOW_UNKNOWN:
3508         case RTE_ETH_FLOW_RAW:
3509         case RTE_ETH_FLOW_FRAG_IPV4:
3510         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3511         case RTE_ETH_FLOW_FRAG_IPV6:
3512         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3513         case RTE_ETH_FLOW_IPV6_EX:
3514         case RTE_ETH_FLOW_IPV6_TCP_EX:
3515         case RTE_ETH_FLOW_IPV6_UDP_EX:
3516         case RTE_ETH_FLOW_GENEVE:
3517                 /* FALLTHROUGH */
3518         default:
3519                 return -EINVAL;
3520         }
3521
3522         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3523         vnic = &bp->vnic_info[fdir->action.rx_queue];
3524         if (vnic == NULL) {
3525                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3526                 return -EINVAL;
3527         }
3528
3529         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3530                 rte_memcpy(filter->dst_macaddr,
3531                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3532                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3533         }
3534
3535         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3536                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3537                 filter1 = STAILQ_FIRST(&vnic0->filter);
3538                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3539         } else {
3540                 filter->dst_id = vnic->fw_vnic_id;
3541                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3542                         if (filter->dst_macaddr[i] == 0x00)
3543                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3544                         else
3545                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3546         }
3547
3548         if (filter1 == NULL)
3549                 return -EINVAL;
3550
3551         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3552         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3553
3554         filter->enables = en;
3555
3556         return 0;
3557 }
3558
3559 static struct bnxt_filter_info *
3560 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3561                 struct bnxt_vnic_info **mvnic)
3562 {
3563         struct bnxt_filter_info *mf = NULL;
3564         int i;
3565
3566         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3567                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3568
3569                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3570                         if (mf->filter_type == nf->filter_type &&
3571                             mf->flags == nf->flags &&
3572                             mf->src_port == nf->src_port &&
3573                             mf->src_port_mask == nf->src_port_mask &&
3574                             mf->dst_port == nf->dst_port &&
3575                             mf->dst_port_mask == nf->dst_port_mask &&
3576                             mf->ip_protocol == nf->ip_protocol &&
3577                             mf->ip_addr_type == nf->ip_addr_type &&
3578                             mf->ethertype == nf->ethertype &&
3579                             mf->vni == nf->vni &&
3580                             mf->tunnel_type == nf->tunnel_type &&
3581                             mf->l2_ovlan == nf->l2_ovlan &&
3582                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3583                             mf->l2_ivlan == nf->l2_ivlan &&
3584                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3585                             !memcmp(mf->l2_addr, nf->l2_addr,
3586                                     RTE_ETHER_ADDR_LEN) &&
3587                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3588                                     RTE_ETHER_ADDR_LEN) &&
3589                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3590                                     RTE_ETHER_ADDR_LEN) &&
3591                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3592                                     RTE_ETHER_ADDR_LEN) &&
3593                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3594                                     sizeof(nf->src_ipaddr)) &&
3595                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3596                                     sizeof(nf->src_ipaddr_mask)) &&
3597                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3598                                     sizeof(nf->dst_ipaddr)) &&
3599                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3600                                     sizeof(nf->dst_ipaddr_mask))) {
3601                                 if (mvnic)
3602                                         *mvnic = vnic;
3603                                 return mf;
3604                         }
3605                 }
3606         }
3607         return NULL;
3608 }
3609
3610 static int
3611 bnxt_fdir_filter(struct rte_eth_dev *dev,
3612                  enum rte_filter_op filter_op,
3613                  void *arg)
3614 {
3615         struct bnxt *bp = dev->data->dev_private;
3616         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3617         struct bnxt_filter_info *filter, *match;
3618         struct bnxt_vnic_info *vnic, *mvnic;
3619         int ret = 0, i;
3620
3621         if (filter_op == RTE_ETH_FILTER_NOP)
3622                 return 0;
3623
3624         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3625                 return -EINVAL;
3626
3627         switch (filter_op) {
3628         case RTE_ETH_FILTER_ADD:
3629         case RTE_ETH_FILTER_DELETE:
3630                 /* FALLTHROUGH */
3631                 filter = bnxt_get_unused_filter(bp);
3632                 if (filter == NULL) {
3633                         PMD_DRV_LOG(ERR,
3634                                 "Not enough resources for a new flow.\n");
3635                         return -ENOMEM;
3636                 }
3637
3638                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3639                 if (ret != 0)
3640                         goto free_filter;
3641                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3642
3643                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3644                         vnic = &bp->vnic_info[0];
3645                 else
3646                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3647
3648                 match = bnxt_match_fdir(bp, filter, &mvnic);
3649                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3650                         if (match->dst_id == vnic->fw_vnic_id) {
3651                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3652                                 ret = -EEXIST;
3653                                 goto free_filter;
3654                         } else {
3655                                 match->dst_id = vnic->fw_vnic_id;
3656                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3657                                                                   match->dst_id,
3658                                                                   match);
3659                                 STAILQ_REMOVE(&mvnic->filter, match,
3660                                               bnxt_filter_info, next);
3661                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3662                                 PMD_DRV_LOG(ERR,
3663                                         "Filter with matching pattern exist\n");
3664                                 PMD_DRV_LOG(ERR,
3665                                         "Updated it to new destination q\n");
3666                                 goto free_filter;
3667                         }
3668                 }
3669                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3670                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3671                         ret = -ENOENT;
3672                         goto free_filter;
3673                 }
3674
3675                 if (filter_op == RTE_ETH_FILTER_ADD) {
3676                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3677                                                           filter->dst_id,
3678                                                           filter);
3679                         if (ret)
3680                                 goto free_filter;
3681                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3682                 } else {
3683                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3684                         STAILQ_REMOVE(&vnic->filter, match,
3685                                       bnxt_filter_info, next);
3686                         bnxt_free_filter(bp, match);
3687                         bnxt_free_filter(bp, filter);
3688                 }
3689                 break;
3690         case RTE_ETH_FILTER_FLUSH:
3691                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3692                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3693
3694                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3695                                 if (filter->filter_type ==
3696                                     HWRM_CFA_NTUPLE_FILTER) {
3697                                         ret =
3698                                         bnxt_hwrm_clear_ntuple_filter(bp,
3699                                                                       filter);
3700                                         STAILQ_REMOVE(&vnic->filter, filter,
3701                                                       bnxt_filter_info, next);
3702                                 }
3703                         }
3704                 }
3705                 return ret;
3706         case RTE_ETH_FILTER_UPDATE:
3707         case RTE_ETH_FILTER_STATS:
3708         case RTE_ETH_FILTER_INFO:
3709                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3710                 break;
3711         default:
3712                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3713                 ret = -EINVAL;
3714                 break;
3715         }
3716         return ret;
3717
3718 free_filter:
3719         bnxt_free_filter(bp, filter);
3720         return ret;
3721 }
3722
3723 int
3724 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3725                     enum rte_filter_type filter_type,
3726                     enum rte_filter_op filter_op, void *arg)
3727 {
3728         struct bnxt *bp = dev->data->dev_private;
3729         int ret = 0;
3730
3731         if (!bp)
3732                 return -EIO;
3733
3734         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3735                 struct bnxt_vf_representor *vfr = dev->data->dev_private;
3736                 bp = vfr->parent_dev->data->dev_private;
3737                 /* parent is deleted while children are still valid */
3738                 if (!bp) {
3739                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3740                                     dev->data->port_id,
3741                                     filter_type,
3742                                     filter_op);
3743                         return -EIO;
3744                 }
3745         }
3746
3747         ret = is_bnxt_in_error(bp);
3748         if (ret)
3749                 return ret;
3750
3751         switch (filter_type) {
3752         case RTE_ETH_FILTER_TUNNEL:
3753                 PMD_DRV_LOG(ERR,
3754                         "filter type: %d: To be implemented\n", filter_type);
3755                 break;
3756         case RTE_ETH_FILTER_FDIR:
3757                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3758                 break;
3759         case RTE_ETH_FILTER_NTUPLE:
3760                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3761                 break;
3762         case RTE_ETH_FILTER_ETHERTYPE:
3763                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3764                 break;
3765         case RTE_ETH_FILTER_GENERIC:
3766                 if (filter_op != RTE_ETH_FILTER_GET)
3767                         return -EINVAL;
3768                 if (BNXT_TRUFLOW_EN(bp))
3769                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3770                 else
3771                         *(const void **)arg = &bnxt_flow_ops;
3772                 break;
3773         default:
3774                 PMD_DRV_LOG(ERR,
3775                         "Filter type (%d) not supported", filter_type);
3776                 ret = -EINVAL;
3777                 break;
3778         }
3779         return ret;
3780 }
3781
3782 static const uint32_t *
3783 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3784 {
3785         static const uint32_t ptypes[] = {
3786                 RTE_PTYPE_L2_ETHER_VLAN,
3787                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3788                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3789                 RTE_PTYPE_L4_ICMP,
3790                 RTE_PTYPE_L4_TCP,
3791                 RTE_PTYPE_L4_UDP,
3792                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3793                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3794                 RTE_PTYPE_INNER_L4_ICMP,
3795                 RTE_PTYPE_INNER_L4_TCP,
3796                 RTE_PTYPE_INNER_L4_UDP,
3797                 RTE_PTYPE_UNKNOWN
3798         };
3799
3800         if (!dev->rx_pkt_burst)
3801                 return NULL;
3802
3803         return ptypes;
3804 }
3805
3806 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3807                          int reg_win)
3808 {
3809         uint32_t reg_base = *reg_arr & 0xfffff000;
3810         uint32_t win_off;
3811         int i;
3812
3813         for (i = 0; i < count; i++) {
3814                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3815                         return -ERANGE;
3816         }
3817         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3818         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3819         return 0;
3820 }
3821
3822 static int bnxt_map_ptp_regs(struct bnxt *bp)
3823 {
3824         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3825         uint32_t *reg_arr;
3826         int rc, i;
3827
3828         reg_arr = ptp->rx_regs;
3829         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3830         if (rc)
3831                 return rc;
3832
3833         reg_arr = ptp->tx_regs;
3834         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3835         if (rc)
3836                 return rc;
3837
3838         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3839                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3840
3841         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3842                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3843
3844         return 0;
3845 }
3846
3847 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3848 {
3849         rte_write32(0, (uint8_t *)bp->bar0 +
3850                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3851         rte_write32(0, (uint8_t *)bp->bar0 +
3852                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3853 }
3854
3855 static uint64_t bnxt_cc_read(struct bnxt *bp)
3856 {
3857         uint64_t ns;
3858
3859         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3860                               BNXT_GRCPF_REG_SYNC_TIME));
3861         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3862                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3863         return ns;
3864 }
3865
3866 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3867 {
3868         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3869         uint32_t fifo;
3870
3871         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3872                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3873         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3874                 return -EAGAIN;
3875
3876         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3877                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3878         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3879                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3880         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3881                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3882
3883         return 0;
3884 }
3885
3886 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3887 {
3888         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3889         struct bnxt_pf_info *pf = bp->pf;
3890         uint16_t port_id;
3891         uint32_t fifo;
3892
3893         if (!ptp)
3894                 return -ENODEV;
3895
3896         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3897                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3898         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3899                 return -EAGAIN;
3900
3901         port_id = pf->port_id;
3902         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3903                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3904
3905         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3906                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3907         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3908 /*              bnxt_clr_rx_ts(bp);       TBD  */
3909                 return -EBUSY;
3910         }
3911
3912         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3913                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3914         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3915                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3916
3917         return 0;
3918 }
3919
3920 static int
3921 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3922 {
3923         uint64_t ns;
3924         struct bnxt *bp = dev->data->dev_private;
3925         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3926
3927         if (!ptp)
3928                 return 0;
3929
3930         ns = rte_timespec_to_ns(ts);
3931         /* Set the timecounters to a new value. */
3932         ptp->tc.nsec = ns;
3933
3934         return 0;
3935 }
3936
3937 static int
3938 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3939 {
3940         struct bnxt *bp = dev->data->dev_private;
3941         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3942         uint64_t ns, systime_cycles = 0;
3943         int rc = 0;
3944
3945         if (!ptp)
3946                 return 0;
3947
3948         if (BNXT_CHIP_THOR(bp))
3949                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3950                                              &systime_cycles);
3951         else
3952                 systime_cycles = bnxt_cc_read(bp);
3953
3954         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3955         *ts = rte_ns_to_timespec(ns);
3956
3957         return rc;
3958 }
3959 static int
3960 bnxt_timesync_enable(struct rte_eth_dev *dev)
3961 {
3962         struct bnxt *bp = dev->data->dev_private;
3963         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3964         uint32_t shift = 0;
3965         int rc;
3966
3967         if (!ptp)
3968                 return 0;
3969
3970         ptp->rx_filter = 1;
3971         ptp->tx_tstamp_en = 1;
3972         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3973
3974         rc = bnxt_hwrm_ptp_cfg(bp);
3975         if (rc)
3976                 return rc;
3977
3978         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3979         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3980         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3981
3982         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3983         ptp->tc.cc_shift = shift;
3984         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3985
3986         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3987         ptp->rx_tstamp_tc.cc_shift = shift;
3988         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3989
3990         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3991         ptp->tx_tstamp_tc.cc_shift = shift;
3992         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3993
3994         if (!BNXT_CHIP_THOR(bp))
3995                 bnxt_map_ptp_regs(bp);
3996
3997         return 0;
3998 }
3999
4000 static int
4001 bnxt_timesync_disable(struct rte_eth_dev *dev)
4002 {
4003         struct bnxt *bp = dev->data->dev_private;
4004         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4005
4006         if (!ptp)
4007                 return 0;
4008
4009         ptp->rx_filter = 0;
4010         ptp->tx_tstamp_en = 0;
4011         ptp->rxctl = 0;
4012
4013         bnxt_hwrm_ptp_cfg(bp);
4014
4015         if (!BNXT_CHIP_THOR(bp))
4016                 bnxt_unmap_ptp_regs(bp);
4017
4018         return 0;
4019 }
4020
4021 static int
4022 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4023                                  struct timespec *timestamp,
4024                                  uint32_t flags __rte_unused)
4025 {
4026         struct bnxt *bp = dev->data->dev_private;
4027         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4028         uint64_t rx_tstamp_cycles = 0;
4029         uint64_t ns;
4030
4031         if (!ptp)
4032                 return 0;
4033
4034         if (BNXT_CHIP_THOR(bp))
4035                 rx_tstamp_cycles = ptp->rx_timestamp;
4036         else
4037                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4038
4039         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4040         *timestamp = rte_ns_to_timespec(ns);
4041         return  0;
4042 }
4043
4044 static int
4045 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4046                                  struct timespec *timestamp)
4047 {
4048         struct bnxt *bp = dev->data->dev_private;
4049         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4050         uint64_t tx_tstamp_cycles = 0;
4051         uint64_t ns;
4052         int rc = 0;
4053
4054         if (!ptp)
4055                 return 0;
4056
4057         if (BNXT_CHIP_THOR(bp))
4058                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4059                                              &tx_tstamp_cycles);
4060         else
4061                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4062
4063         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4064         *timestamp = rte_ns_to_timespec(ns);
4065
4066         return rc;
4067 }
4068
4069 static int
4070 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4071 {
4072         struct bnxt *bp = dev->data->dev_private;
4073         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4074
4075         if (!ptp)
4076                 return 0;
4077
4078         ptp->tc.nsec += delta;
4079
4080         return 0;
4081 }
4082
4083 static int
4084 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4085 {
4086         struct bnxt *bp = dev->data->dev_private;
4087         int rc;
4088         uint32_t dir_entries;
4089         uint32_t entry_length;
4090
4091         rc = is_bnxt_in_error(bp);
4092         if (rc)
4093                 return rc;
4094
4095         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4096                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4097                     bp->pdev->addr.devid, bp->pdev->addr.function);
4098
4099         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4100         if (rc != 0)
4101                 return rc;
4102
4103         return dir_entries * entry_length;
4104 }
4105
4106 static int
4107 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4108                 struct rte_dev_eeprom_info *in_eeprom)
4109 {
4110         struct bnxt *bp = dev->data->dev_private;
4111         uint32_t index;
4112         uint32_t offset;
4113         int rc;
4114
4115         rc = is_bnxt_in_error(bp);
4116         if (rc)
4117                 return rc;
4118
4119         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4120                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4121                     bp->pdev->addr.devid, bp->pdev->addr.function,
4122                     in_eeprom->offset, in_eeprom->length);
4123
4124         if (in_eeprom->offset == 0) /* special offset value to get directory */
4125                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4126                                                 in_eeprom->data);
4127
4128         index = in_eeprom->offset >> 24;
4129         offset = in_eeprom->offset & 0xffffff;
4130
4131         if (index != 0)
4132                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4133                                            in_eeprom->length, in_eeprom->data);
4134
4135         return 0;
4136 }
4137
4138 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4139 {
4140         switch (dir_type) {
4141         case BNX_DIR_TYPE_CHIMP_PATCH:
4142         case BNX_DIR_TYPE_BOOTCODE:
4143         case BNX_DIR_TYPE_BOOTCODE_2:
4144         case BNX_DIR_TYPE_APE_FW:
4145         case BNX_DIR_TYPE_APE_PATCH:
4146         case BNX_DIR_TYPE_KONG_FW:
4147         case BNX_DIR_TYPE_KONG_PATCH:
4148         case BNX_DIR_TYPE_BONO_FW:
4149         case BNX_DIR_TYPE_BONO_PATCH:
4150                 /* FALLTHROUGH */
4151                 return true;
4152         }
4153
4154         return false;
4155 }
4156
4157 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4158 {
4159         switch (dir_type) {
4160         case BNX_DIR_TYPE_AVS:
4161         case BNX_DIR_TYPE_EXP_ROM_MBA:
4162         case BNX_DIR_TYPE_PCIE:
4163         case BNX_DIR_TYPE_TSCF_UCODE:
4164         case BNX_DIR_TYPE_EXT_PHY:
4165         case BNX_DIR_TYPE_CCM:
4166         case BNX_DIR_TYPE_ISCSI_BOOT:
4167         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4168         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4169                 /* FALLTHROUGH */
4170                 return true;
4171         }
4172
4173         return false;
4174 }
4175
4176 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4177 {
4178         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4179                 bnxt_dir_type_is_other_exec_format(dir_type);
4180 }
4181
4182 static int
4183 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4184                 struct rte_dev_eeprom_info *in_eeprom)
4185 {
4186         struct bnxt *bp = dev->data->dev_private;
4187         uint8_t index, dir_op;
4188         uint16_t type, ext, ordinal, attr;
4189         int rc;
4190
4191         rc = is_bnxt_in_error(bp);
4192         if (rc)
4193                 return rc;
4194
4195         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4196                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4197                     bp->pdev->addr.devid, bp->pdev->addr.function,
4198                     in_eeprom->offset, in_eeprom->length);
4199
4200         if (!BNXT_PF(bp)) {
4201                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4202                 return -EINVAL;
4203         }
4204
4205         type = in_eeprom->magic >> 16;
4206
4207         if (type == 0xffff) { /* special value for directory operations */
4208                 index = in_eeprom->magic & 0xff;
4209                 dir_op = in_eeprom->magic >> 8;
4210                 if (index == 0)
4211                         return -EINVAL;
4212                 switch (dir_op) {
4213                 case 0x0e: /* erase */
4214                         if (in_eeprom->offset != ~in_eeprom->magic)
4215                                 return -EINVAL;
4216                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4217                 default:
4218                         return -EINVAL;
4219                 }
4220         }
4221
4222         /* Create or re-write an NVM item: */
4223         if (bnxt_dir_type_is_executable(type) == true)
4224                 return -EOPNOTSUPP;
4225         ext = in_eeprom->magic & 0xffff;
4226         ordinal = in_eeprom->offset >> 16;
4227         attr = in_eeprom->offset & 0xffff;
4228
4229         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4230                                      in_eeprom->data, in_eeprom->length);
4231 }
4232
4233 /*
4234  * Initialization
4235  */
4236
4237 static const struct eth_dev_ops bnxt_dev_ops = {
4238         .dev_infos_get = bnxt_dev_info_get_op,
4239         .dev_close = bnxt_dev_close_op,
4240         .dev_configure = bnxt_dev_configure_op,
4241         .dev_start = bnxt_dev_start_op,
4242         .dev_stop = bnxt_dev_stop_op,
4243         .dev_set_link_up = bnxt_dev_set_link_up_op,
4244         .dev_set_link_down = bnxt_dev_set_link_down_op,
4245         .stats_get = bnxt_stats_get_op,
4246         .stats_reset = bnxt_stats_reset_op,
4247         .rx_queue_setup = bnxt_rx_queue_setup_op,
4248         .rx_queue_release = bnxt_rx_queue_release_op,
4249         .tx_queue_setup = bnxt_tx_queue_setup_op,
4250         .tx_queue_release = bnxt_tx_queue_release_op,
4251         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4252         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4253         .reta_update = bnxt_reta_update_op,
4254         .reta_query = bnxt_reta_query_op,
4255         .rss_hash_update = bnxt_rss_hash_update_op,
4256         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4257         .link_update = bnxt_link_update_op,
4258         .promiscuous_enable = bnxt_promiscuous_enable_op,
4259         .promiscuous_disable = bnxt_promiscuous_disable_op,
4260         .allmulticast_enable = bnxt_allmulticast_enable_op,
4261         .allmulticast_disable = bnxt_allmulticast_disable_op,
4262         .mac_addr_add = bnxt_mac_addr_add_op,
4263         .mac_addr_remove = bnxt_mac_addr_remove_op,
4264         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4265         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4266         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4267         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4268         .vlan_filter_set = bnxt_vlan_filter_set_op,
4269         .vlan_offload_set = bnxt_vlan_offload_set_op,
4270         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4271         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4272         .mtu_set = bnxt_mtu_set_op,
4273         .mac_addr_set = bnxt_set_default_mac_addr_op,
4274         .xstats_get = bnxt_dev_xstats_get_op,
4275         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4276         .xstats_reset = bnxt_dev_xstats_reset_op,
4277         .fw_version_get = bnxt_fw_version_get,
4278         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4279         .rxq_info_get = bnxt_rxq_info_get_op,
4280         .txq_info_get = bnxt_txq_info_get_op,
4281         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4282         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4283         .dev_led_on = bnxt_dev_led_on_op,
4284         .dev_led_off = bnxt_dev_led_off_op,
4285         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4286         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4287         .rx_queue_start = bnxt_rx_queue_start,
4288         .rx_queue_stop = bnxt_rx_queue_stop,
4289         .tx_queue_start = bnxt_tx_queue_start,
4290         .tx_queue_stop = bnxt_tx_queue_stop,
4291         .filter_ctrl = bnxt_filter_ctrl_op,
4292         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4293         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4294         .get_eeprom           = bnxt_get_eeprom_op,
4295         .set_eeprom           = bnxt_set_eeprom_op,
4296         .timesync_enable      = bnxt_timesync_enable,
4297         .timesync_disable     = bnxt_timesync_disable,
4298         .timesync_read_time   = bnxt_timesync_read_time,
4299         .timesync_write_time   = bnxt_timesync_write_time,
4300         .timesync_adjust_time = bnxt_timesync_adjust_time,
4301         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4302         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4303 };
4304
4305 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4306 {
4307         uint32_t offset;
4308
4309         /* Only pre-map the reset GRC registers using window 3 */
4310         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4311                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4312
4313         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4314
4315         return offset;
4316 }
4317
4318 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4319 {
4320         struct bnxt_error_recovery_info *info = bp->recovery_info;
4321         uint32_t reg_base = 0xffffffff;
4322         int i;
4323
4324         /* Only pre-map the monitoring GRC registers using window 2 */
4325         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4326                 uint32_t reg = info->status_regs[i];
4327
4328                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4329                         continue;
4330
4331                 if (reg_base == 0xffffffff)
4332                         reg_base = reg & 0xfffff000;
4333                 if ((reg & 0xfffff000) != reg_base)
4334                         return -ERANGE;
4335
4336                 /* Use mask 0xffc as the Lower 2 bits indicates
4337                  * address space location
4338                  */
4339                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4340                                                 (reg & 0xffc);
4341         }
4342
4343         if (reg_base == 0xffffffff)
4344                 return 0;
4345
4346         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4347                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4348
4349         return 0;
4350 }
4351
4352 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4353 {
4354         struct bnxt_error_recovery_info *info = bp->recovery_info;
4355         uint32_t delay = info->delay_after_reset[index];
4356         uint32_t val = info->reset_reg_val[index];
4357         uint32_t reg = info->reset_reg[index];
4358         uint32_t type, offset;
4359
4360         type = BNXT_FW_STATUS_REG_TYPE(reg);
4361         offset = BNXT_FW_STATUS_REG_OFF(reg);
4362
4363         switch (type) {
4364         case BNXT_FW_STATUS_REG_TYPE_CFG:
4365                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4366                 break;
4367         case BNXT_FW_STATUS_REG_TYPE_GRC:
4368                 offset = bnxt_map_reset_regs(bp, offset);
4369                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4370                 break;
4371         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4372                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4373                 break;
4374         }
4375         /* wait on a specific interval of time until core reset is complete */
4376         if (delay)
4377                 rte_delay_ms(delay);
4378 }
4379
4380 static void bnxt_dev_cleanup(struct bnxt *bp)
4381 {
4382         bp->eth_dev->data->dev_link.link_status = 0;
4383         bp->link_info->link_up = 0;
4384         if (bp->eth_dev->data->dev_started)
4385                 bnxt_dev_stop_op(bp->eth_dev);
4386
4387         bnxt_uninit_resources(bp, true);
4388 }
4389
4390 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4391 {
4392         struct rte_eth_dev *dev = bp->eth_dev;
4393         struct rte_vlan_filter_conf *vfc;
4394         int vidx, vbit, rc;
4395         uint16_t vlan_id;
4396
4397         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4398                 vfc = &dev->data->vlan_filter_conf;
4399                 vidx = vlan_id / 64;
4400                 vbit = vlan_id % 64;
4401
4402                 /* Each bit corresponds to a VLAN id */
4403                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4404                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4405                         if (rc)
4406                                 return rc;
4407                 }
4408         }
4409
4410         return 0;
4411 }
4412
4413 static int bnxt_restore_mac_filters(struct bnxt *bp)
4414 {
4415         struct rte_eth_dev *dev = bp->eth_dev;
4416         struct rte_eth_dev_info dev_info;
4417         struct rte_ether_addr *addr;
4418         uint64_t pool_mask;
4419         uint32_t pool = 0;
4420         uint16_t i;
4421         int rc;
4422
4423         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4424                 return 0;
4425
4426         rc = bnxt_dev_info_get_op(dev, &dev_info);
4427         if (rc)
4428                 return rc;
4429
4430         /* replay MAC address configuration */
4431         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4432                 addr = &dev->data->mac_addrs[i];
4433
4434                 /* skip zero address */
4435                 if (rte_is_zero_ether_addr(addr))
4436                         continue;
4437
4438                 pool = 0;
4439                 pool_mask = dev->data->mac_pool_sel[i];
4440
4441                 do {
4442                         if (pool_mask & 1ULL) {
4443                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4444                                 if (rc)
4445                                         return rc;
4446                         }
4447                         pool_mask >>= 1;
4448                         pool++;
4449                 } while (pool_mask);
4450         }
4451
4452         return 0;
4453 }
4454
4455 static int bnxt_restore_filters(struct bnxt *bp)
4456 {
4457         struct rte_eth_dev *dev = bp->eth_dev;
4458         int ret = 0;
4459
4460         if (dev->data->all_multicast) {
4461                 ret = bnxt_allmulticast_enable_op(dev);
4462                 if (ret)
4463                         return ret;
4464         }
4465         if (dev->data->promiscuous) {
4466                 ret = bnxt_promiscuous_enable_op(dev);
4467                 if (ret)
4468                         return ret;
4469         }
4470
4471         ret = bnxt_restore_mac_filters(bp);
4472         if (ret)
4473                 return ret;
4474
4475         ret = bnxt_restore_vlan_filters(bp);
4476         /* TODO restore other filters as well */
4477         return ret;
4478 }
4479
4480 static void bnxt_dev_recover(void *arg)
4481 {
4482         struct bnxt *bp = arg;
4483         int timeout = bp->fw_reset_max_msecs;
4484         int rc = 0;
4485
4486         /* Clear Error flag so that device re-init should happen */
4487         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4488
4489         do {
4490                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4491                 if (rc == 0)
4492                         break;
4493                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4494                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4495         } while (rc && timeout);
4496
4497         if (rc) {
4498                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4499                 goto err;
4500         }
4501
4502         rc = bnxt_init_resources(bp, true);
4503         if (rc) {
4504                 PMD_DRV_LOG(ERR,
4505                             "Failed to initialize resources after reset\n");
4506                 goto err;
4507         }
4508         /* clear reset flag as the device is initialized now */
4509         bp->flags &= ~BNXT_FLAG_FW_RESET;
4510
4511         rc = bnxt_dev_start_op(bp->eth_dev);
4512         if (rc) {
4513                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4514                 goto err_start;
4515         }
4516
4517         rc = bnxt_restore_filters(bp);
4518         if (rc)
4519                 goto err_start;
4520
4521         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4522         return;
4523 err_start:
4524         bnxt_dev_stop_op(bp->eth_dev);
4525 err:
4526         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4527         bnxt_uninit_resources(bp, false);
4528         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4529 }
4530
4531 void bnxt_dev_reset_and_resume(void *arg)
4532 {
4533         struct bnxt *bp = arg;
4534         int rc;
4535
4536         bnxt_dev_cleanup(bp);
4537
4538         bnxt_wait_for_device_shutdown(bp);
4539
4540         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4541                                bnxt_dev_recover, (void *)bp);
4542         if (rc)
4543                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4544 }
4545
4546 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4547 {
4548         struct bnxt_error_recovery_info *info = bp->recovery_info;
4549         uint32_t reg = info->status_regs[index];
4550         uint32_t type, offset, val = 0;
4551
4552         type = BNXT_FW_STATUS_REG_TYPE(reg);
4553         offset = BNXT_FW_STATUS_REG_OFF(reg);
4554
4555         switch (type) {
4556         case BNXT_FW_STATUS_REG_TYPE_CFG:
4557                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4558                 break;
4559         case BNXT_FW_STATUS_REG_TYPE_GRC:
4560                 offset = info->mapped_status_regs[index];
4561                 /* FALLTHROUGH */
4562         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4563                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4564                                        offset));
4565                 break;
4566         }
4567
4568         return val;
4569 }
4570
4571 static int bnxt_fw_reset_all(struct bnxt *bp)
4572 {
4573         struct bnxt_error_recovery_info *info = bp->recovery_info;
4574         uint32_t i;
4575         int rc = 0;
4576
4577         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4578                 /* Reset through master function driver */
4579                 for (i = 0; i < info->reg_array_cnt; i++)
4580                         bnxt_write_fw_reset_reg(bp, i);
4581                 /* Wait for time specified by FW after triggering reset */
4582                 rte_delay_ms(info->master_func_wait_period_after_reset);
4583         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4584                 /* Reset with the help of Kong processor */
4585                 rc = bnxt_hwrm_fw_reset(bp);
4586                 if (rc)
4587                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4588         }
4589
4590         return rc;
4591 }
4592
4593 static void bnxt_fw_reset_cb(void *arg)
4594 {
4595         struct bnxt *bp = arg;
4596         struct bnxt_error_recovery_info *info = bp->recovery_info;
4597         int rc = 0;
4598
4599         /* Only Master function can do FW reset */
4600         if (bnxt_is_master_func(bp) &&
4601             bnxt_is_recovery_enabled(bp)) {
4602                 rc = bnxt_fw_reset_all(bp);
4603                 if (rc) {
4604                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4605                         return;
4606                 }
4607         }
4608
4609         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4610          * EXCEPTION_FATAL_ASYNC event to all the functions
4611          * (including MASTER FUNC). After receiving this Async, all the active
4612          * drivers should treat this case as FW initiated recovery
4613          */
4614         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4615                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4616                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4617
4618                 /* To recover from error */
4619                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4620                                   (void *)bp);
4621         }
4622 }
4623
4624 /* Driver should poll FW heartbeat, reset_counter with the frequency
4625  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4626  * When the driver detects heartbeat stop or change in reset_counter,
4627  * it has to trigger a reset to recover from the error condition.
4628  * A “master PF” is the function who will have the privilege to
4629  * initiate the chimp reset. The master PF will be elected by the
4630  * firmware and will be notified through async message.
4631  */
4632 static void bnxt_check_fw_health(void *arg)
4633 {
4634         struct bnxt *bp = arg;
4635         struct bnxt_error_recovery_info *info = bp->recovery_info;
4636         uint32_t val = 0, wait_msec;
4637
4638         if (!info || !bnxt_is_recovery_enabled(bp) ||
4639             is_bnxt_in_error(bp))
4640                 return;
4641
4642         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4643         if (val == info->last_heart_beat)
4644                 goto reset;
4645
4646         info->last_heart_beat = val;
4647
4648         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4649         if (val != info->last_reset_counter)
4650                 goto reset;
4651
4652         info->last_reset_counter = val;
4653
4654         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4655                           bnxt_check_fw_health, (void *)bp);
4656
4657         return;
4658 reset:
4659         /* Stop DMA to/from device */
4660         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4661         bp->flags |= BNXT_FLAG_FW_RESET;
4662
4663         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4664
4665         if (bnxt_is_master_func(bp))
4666                 wait_msec = info->master_func_wait_period;
4667         else
4668                 wait_msec = info->normal_func_wait_period;
4669
4670         rte_eal_alarm_set(US_PER_MS * wait_msec,
4671                           bnxt_fw_reset_cb, (void *)bp);
4672 }
4673
4674 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4675 {
4676         uint32_t polling_freq;
4677
4678         pthread_mutex_lock(&bp->health_check_lock);
4679
4680         if (!bnxt_is_recovery_enabled(bp))
4681                 goto done;
4682
4683         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4684                 goto done;
4685
4686         polling_freq = bp->recovery_info->driver_polling_freq;
4687
4688         rte_eal_alarm_set(US_PER_MS * polling_freq,
4689                           bnxt_check_fw_health, (void *)bp);
4690         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4691
4692 done:
4693         pthread_mutex_unlock(&bp->health_check_lock);
4694 }
4695
4696 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4697 {
4698         if (!bnxt_is_recovery_enabled(bp))
4699                 return;
4700
4701         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4702         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4703 }
4704
4705 static bool bnxt_vf_pciid(uint16_t device_id)
4706 {
4707         switch (device_id) {
4708         case BROADCOM_DEV_ID_57304_VF:
4709         case BROADCOM_DEV_ID_57406_VF:
4710         case BROADCOM_DEV_ID_5731X_VF:
4711         case BROADCOM_DEV_ID_5741X_VF:
4712         case BROADCOM_DEV_ID_57414_VF:
4713         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4714         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4715         case BROADCOM_DEV_ID_58802_VF:
4716         case BROADCOM_DEV_ID_57500_VF1:
4717         case BROADCOM_DEV_ID_57500_VF2:
4718                 /* FALLTHROUGH */
4719                 return true;
4720         default:
4721                 return false;
4722         }
4723 }
4724
4725 static bool bnxt_thor_device(uint16_t device_id)
4726 {
4727         switch (device_id) {
4728         case BROADCOM_DEV_ID_57508:
4729         case BROADCOM_DEV_ID_57504:
4730         case BROADCOM_DEV_ID_57502:
4731         case BROADCOM_DEV_ID_57508_MF1:
4732         case BROADCOM_DEV_ID_57504_MF1:
4733         case BROADCOM_DEV_ID_57502_MF1:
4734         case BROADCOM_DEV_ID_57508_MF2:
4735         case BROADCOM_DEV_ID_57504_MF2:
4736         case BROADCOM_DEV_ID_57502_MF2:
4737         case BROADCOM_DEV_ID_57500_VF1:
4738         case BROADCOM_DEV_ID_57500_VF2:
4739                 /* FALLTHROUGH */
4740                 return true;
4741         default:
4742                 return false;
4743         }
4744 }
4745
4746 bool bnxt_stratus_device(struct bnxt *bp)
4747 {
4748         uint16_t device_id = bp->pdev->id.device_id;
4749
4750         switch (device_id) {
4751         case BROADCOM_DEV_ID_STRATUS_NIC:
4752         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4753         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4754                 /* FALLTHROUGH */
4755                 return true;
4756         default:
4757                 return false;
4758         }
4759 }
4760
4761 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4762 {
4763         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4764         struct bnxt *bp = eth_dev->data->dev_private;
4765
4766         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4767         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4768         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4769         if (!bp->bar0 || !bp->doorbell_base) {
4770                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4771                 return -ENODEV;
4772         }
4773
4774         bp->eth_dev = eth_dev;
4775         bp->pdev = pci_dev;
4776
4777         return 0;
4778 }
4779
4780 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4781                                   struct bnxt_ctx_pg_info *ctx_pg,
4782                                   uint32_t mem_size,
4783                                   const char *suffix,
4784                                   uint16_t idx)
4785 {
4786         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4787         const struct rte_memzone *mz = NULL;
4788         char mz_name[RTE_MEMZONE_NAMESIZE];
4789         rte_iova_t mz_phys_addr;
4790         uint64_t valid_bits = 0;
4791         uint32_t sz;
4792         int i;
4793
4794         if (!mem_size)
4795                 return 0;
4796
4797         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4798                          BNXT_PAGE_SIZE;
4799         rmem->page_size = BNXT_PAGE_SIZE;
4800         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4801         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4802         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4803
4804         valid_bits = PTU_PTE_VALID;
4805
4806         if (rmem->nr_pages > 1) {
4807                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4808                          "bnxt_ctx_pg_tbl%s_%x_%d",
4809                          suffix, idx, bp->eth_dev->data->port_id);
4810                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4811                 mz = rte_memzone_lookup(mz_name);
4812                 if (!mz) {
4813                         mz = rte_memzone_reserve_aligned(mz_name,
4814                                                 rmem->nr_pages * 8,
4815                                                 SOCKET_ID_ANY,
4816                                                 RTE_MEMZONE_2MB |
4817                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4818                                                 RTE_MEMZONE_IOVA_CONTIG,
4819                                                 BNXT_PAGE_SIZE);
4820                         if (mz == NULL)
4821                                 return -ENOMEM;
4822                 }
4823
4824                 memset(mz->addr, 0, mz->len);
4825                 mz_phys_addr = mz->iova;
4826
4827                 rmem->pg_tbl = mz->addr;
4828                 rmem->pg_tbl_map = mz_phys_addr;
4829                 rmem->pg_tbl_mz = mz;
4830         }
4831
4832         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4833                  suffix, idx, bp->eth_dev->data->port_id);
4834         mz = rte_memzone_lookup(mz_name);
4835         if (!mz) {
4836                 mz = rte_memzone_reserve_aligned(mz_name,
4837                                                  mem_size,
4838                                                  SOCKET_ID_ANY,
4839                                                  RTE_MEMZONE_1GB |
4840                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4841                                                  RTE_MEMZONE_IOVA_CONTIG,
4842                                                  BNXT_PAGE_SIZE);
4843                 if (mz == NULL)
4844                         return -ENOMEM;
4845         }
4846
4847         memset(mz->addr, 0, mz->len);
4848         mz_phys_addr = mz->iova;
4849
4850         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4851                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4852                 rmem->dma_arr[i] = mz_phys_addr + sz;
4853
4854                 if (rmem->nr_pages > 1) {
4855                         if (i == rmem->nr_pages - 2 &&
4856                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4857                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4858                         else if (i == rmem->nr_pages - 1 &&
4859                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4860                                 valid_bits |= PTU_PTE_LAST;
4861
4862                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4863                                                            valid_bits);
4864                 }
4865         }
4866
4867         rmem->mz = mz;
4868         if (rmem->vmem_size)
4869                 rmem->vmem = (void **)mz->addr;
4870         rmem->dma_arr[0] = mz_phys_addr;
4871         return 0;
4872 }
4873
4874 static void bnxt_free_ctx_mem(struct bnxt *bp)
4875 {
4876         int i;
4877
4878         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4879                 return;
4880
4881         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4882         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4883         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4884         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4885         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4886         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4887         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4888         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4889         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4890         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4891         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4892
4893         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4894                 if (bp->ctx->tqm_mem[i])
4895                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4896         }
4897
4898         rte_free(bp->ctx);
4899         bp->ctx = NULL;
4900 }
4901
4902 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4903
4904 #define min_t(type, x, y) ({                    \
4905         type __min1 = (x);                      \
4906         type __min2 = (y);                      \
4907         __min1 < __min2 ? __min1 : __min2; })
4908
4909 #define max_t(type, x, y) ({                    \
4910         type __max1 = (x);                      \
4911         type __max2 = (y);                      \
4912         __max1 > __max2 ? __max1 : __max2; })
4913
4914 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4915
4916 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4917 {
4918         struct bnxt_ctx_pg_info *ctx_pg;
4919         struct bnxt_ctx_mem_info *ctx;
4920         uint32_t mem_size, ena, entries;
4921         uint32_t entries_sp, min;
4922         int i, rc;
4923
4924         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4925         if (rc) {
4926                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4927                 return rc;
4928         }
4929         ctx = bp->ctx;
4930         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4931                 return 0;
4932
4933         ctx_pg = &ctx->qp_mem;
4934         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4935         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4936         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4937         if (rc)
4938                 return rc;
4939
4940         ctx_pg = &ctx->srq_mem;
4941         ctx_pg->entries = ctx->srq_max_l2_entries;
4942         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4943         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4944         if (rc)
4945                 return rc;
4946
4947         ctx_pg = &ctx->cq_mem;
4948         ctx_pg->entries = ctx->cq_max_l2_entries;
4949         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4950         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4951         if (rc)
4952                 return rc;
4953
4954         ctx_pg = &ctx->vnic_mem;
4955         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4956                 ctx->vnic_max_ring_table_entries;
4957         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4958         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4959         if (rc)
4960                 return rc;
4961
4962         ctx_pg = &ctx->stat_mem;
4963         ctx_pg->entries = ctx->stat_max_entries;
4964         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4965         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4966         if (rc)
4967                 return rc;
4968
4969         min = ctx->tqm_min_entries_per_ring;
4970
4971         entries_sp = ctx->qp_max_l2_entries +
4972                      ctx->vnic_max_vnic_entries +
4973                      2 * ctx->qp_min_qp1_entries + min;
4974         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4975
4976         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4977         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4978         entries = clamp_t(uint32_t, entries, min,
4979                           ctx->tqm_max_entries_per_ring);
4980         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4981                 ctx_pg = ctx->tqm_mem[i];
4982                 ctx_pg->entries = i ? entries : entries_sp;
4983                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4984                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4985                 if (rc)
4986                         return rc;
4987                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4988         }
4989
4990         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4991         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4992         if (rc)
4993                 PMD_DRV_LOG(ERR,
4994                             "Failed to configure context mem: rc = %d\n", rc);
4995         else
4996                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4997
4998         return rc;
4999 }
5000
5001 static int bnxt_alloc_stats_mem(struct bnxt *bp)
5002 {
5003         struct rte_pci_device *pci_dev = bp->pdev;
5004         char mz_name[RTE_MEMZONE_NAMESIZE];
5005         const struct rte_memzone *mz = NULL;
5006         uint32_t total_alloc_len;
5007         rte_iova_t mz_phys_addr;
5008
5009         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
5010                 return 0;
5011
5012         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5013                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5014                  pci_dev->addr.bus, pci_dev->addr.devid,
5015                  pci_dev->addr.function, "rx_port_stats");
5016         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5017         mz = rte_memzone_lookup(mz_name);
5018         total_alloc_len =
5019                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
5020                                        sizeof(struct rx_port_stats_ext) + 512);
5021         if (!mz) {
5022                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5023                                          SOCKET_ID_ANY,
5024                                          RTE_MEMZONE_2MB |
5025                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5026                                          RTE_MEMZONE_IOVA_CONTIG);
5027                 if (mz == NULL)
5028                         return -ENOMEM;
5029         }
5030         memset(mz->addr, 0, mz->len);
5031         mz_phys_addr = mz->iova;
5032
5033         bp->rx_mem_zone = (const void *)mz;
5034         bp->hw_rx_port_stats = mz->addr;
5035         bp->hw_rx_port_stats_map = mz_phys_addr;
5036
5037         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5038                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5039                  pci_dev->addr.bus, pci_dev->addr.devid,
5040                  pci_dev->addr.function, "tx_port_stats");
5041         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5042         mz = rte_memzone_lookup(mz_name);
5043         total_alloc_len =
5044                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5045                                        sizeof(struct tx_port_stats_ext) + 512);
5046         if (!mz) {
5047                 mz = rte_memzone_reserve(mz_name,
5048                                          total_alloc_len,
5049                                          SOCKET_ID_ANY,
5050                                          RTE_MEMZONE_2MB |
5051                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5052                                          RTE_MEMZONE_IOVA_CONTIG);
5053                 if (mz == NULL)
5054                         return -ENOMEM;
5055         }
5056         memset(mz->addr, 0, mz->len);
5057         mz_phys_addr = mz->iova;
5058
5059         bp->tx_mem_zone = (const void *)mz;
5060         bp->hw_tx_port_stats = mz->addr;
5061         bp->hw_tx_port_stats_map = mz_phys_addr;
5062         bp->flags |= BNXT_FLAG_PORT_STATS;
5063
5064         /* Display extended statistics if FW supports it */
5065         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5066             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5067             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5068                 return 0;
5069
5070         bp->hw_rx_port_stats_ext = (void *)
5071                 ((uint8_t *)bp->hw_rx_port_stats +
5072                  sizeof(struct rx_port_stats));
5073         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5074                 sizeof(struct rx_port_stats);
5075         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5076
5077         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5078             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5079                 bp->hw_tx_port_stats_ext = (void *)
5080                         ((uint8_t *)bp->hw_tx_port_stats +
5081                          sizeof(struct tx_port_stats));
5082                 bp->hw_tx_port_stats_ext_map =
5083                         bp->hw_tx_port_stats_map +
5084                         sizeof(struct tx_port_stats);
5085                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5086         }
5087
5088         return 0;
5089 }
5090
5091 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5092 {
5093         struct bnxt *bp = eth_dev->data->dev_private;
5094         int rc = 0;
5095
5096         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5097                                                RTE_ETHER_ADDR_LEN *
5098                                                bp->max_l2_ctx,
5099                                                0);
5100         if (eth_dev->data->mac_addrs == NULL) {
5101                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5102                 return -ENOMEM;
5103         }
5104
5105         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5106                 if (BNXT_PF(bp))
5107                         return -EINVAL;
5108
5109                 /* Generate a random MAC address, if none was assigned by PF */
5110                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5111                 bnxt_eth_hw_addr_random(bp->mac_addr);
5112                 PMD_DRV_LOG(INFO,
5113                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5114                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5115                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5116
5117                 rc = bnxt_hwrm_set_mac(bp);
5118                 if (rc)
5119                         return rc;
5120         }
5121
5122         /* Copy the permanent MAC from the FUNC_QCAPS response */
5123         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5124
5125         return rc;
5126 }
5127
5128 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5129 {
5130         int rc = 0;
5131
5132         /* MAC is already configured in FW */
5133         if (BNXT_HAS_DFLT_MAC_SET(bp))
5134                 return 0;
5135
5136         /* Restore the old MAC configured */
5137         rc = bnxt_hwrm_set_mac(bp);
5138         if (rc)
5139                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5140
5141         return rc;
5142 }
5143
5144 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5145 {
5146         if (!BNXT_PF(bp))
5147                 return;
5148
5149 #define ALLOW_FUNC(x)   \
5150         { \
5151                 uint32_t arg = (x); \
5152                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5153                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5154         }
5155
5156         /* Forward all requests if firmware is new enough */
5157         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5158              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5159             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5160                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5161         } else {
5162                 PMD_DRV_LOG(WARNING,
5163                             "Firmware too old for VF mailbox functionality\n");
5164                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5165         }
5166
5167         /*
5168          * The following are used for driver cleanup. If we disallow these,
5169          * VF drivers can't clean up cleanly.
5170          */
5171         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5172         ALLOW_FUNC(HWRM_VNIC_FREE);
5173         ALLOW_FUNC(HWRM_RING_FREE);
5174         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5175         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5176         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5177         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5178         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5179         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5180 }
5181
5182 uint16_t
5183 bnxt_get_svif(uint16_t port_id, bool func_svif,
5184               enum bnxt_ulp_intf_type type)
5185 {
5186         struct rte_eth_dev *eth_dev;
5187         struct bnxt *bp;
5188
5189         eth_dev = &rte_eth_devices[port_id];
5190         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5191                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5192                 if (!vfr)
5193                         return 0;
5194
5195                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5196                         return vfr->svif;
5197
5198                 eth_dev = vfr->parent_dev;
5199         }
5200
5201         bp = eth_dev->data->dev_private;
5202
5203         return func_svif ? bp->func_svif : bp->port_svif;
5204 }
5205
5206 uint16_t
5207 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5208 {
5209         struct rte_eth_dev *eth_dev;
5210         struct bnxt_vnic_info *vnic;
5211         struct bnxt *bp;
5212
5213         eth_dev = &rte_eth_devices[port];
5214         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5215                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5216                 if (!vfr)
5217                         return 0;
5218
5219                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5220                         return vfr->dflt_vnic_id;
5221
5222                 eth_dev = vfr->parent_dev;
5223         }
5224
5225         bp = eth_dev->data->dev_private;
5226
5227         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5228
5229         return vnic->fw_vnic_id;
5230 }
5231
5232 uint16_t
5233 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5234 {
5235         struct rte_eth_dev *eth_dev;
5236         struct bnxt *bp;
5237
5238         eth_dev = &rte_eth_devices[port];
5239         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5240                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5241                 if (!vfr)
5242                         return 0;
5243
5244                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5245                         return vfr->fw_fid;
5246
5247                 eth_dev = vfr->parent_dev;
5248         }
5249
5250         bp = eth_dev->data->dev_private;
5251
5252         return bp->fw_fid;
5253 }
5254
5255 enum bnxt_ulp_intf_type
5256 bnxt_get_interface_type(uint16_t port)
5257 {
5258         struct rte_eth_dev *eth_dev;
5259         struct bnxt *bp;
5260
5261         eth_dev = &rte_eth_devices[port];
5262         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5263                 return BNXT_ULP_INTF_TYPE_VF_REP;
5264
5265         bp = eth_dev->data->dev_private;
5266         if (BNXT_PF(bp))
5267                 return BNXT_ULP_INTF_TYPE_PF;
5268         else if (BNXT_VF_IS_TRUSTED(bp))
5269                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5270         else if (BNXT_VF(bp))
5271                 return BNXT_ULP_INTF_TYPE_VF;
5272
5273         return BNXT_ULP_INTF_TYPE_INVALID;
5274 }
5275
5276 uint16_t
5277 bnxt_get_phy_port_id(uint16_t port_id)
5278 {
5279         struct bnxt_vf_representor *vfr;
5280         struct rte_eth_dev *eth_dev;
5281         struct bnxt *bp;
5282
5283         eth_dev = &rte_eth_devices[port_id];
5284         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5285                 vfr = eth_dev->data->dev_private;
5286                 if (!vfr)
5287                         return 0;
5288
5289                 eth_dev = vfr->parent_dev;
5290         }
5291
5292         bp = eth_dev->data->dev_private;
5293
5294         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5295 }
5296
5297 uint16_t
5298 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5299 {
5300         struct rte_eth_dev *eth_dev;
5301         struct bnxt *bp;
5302
5303         eth_dev = &rte_eth_devices[port_id];
5304         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5305                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5306                 if (!vfr)
5307                         return 0;
5308
5309                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5310                         return vfr->fw_fid - 1;
5311
5312                 eth_dev = vfr->parent_dev;
5313         }
5314
5315         bp = eth_dev->data->dev_private;
5316
5317         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5318 }
5319
5320 uint16_t
5321 bnxt_get_vport(uint16_t port_id)
5322 {
5323         return (1 << bnxt_get_phy_port_id(port_id));
5324 }
5325
5326 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5327 {
5328         struct bnxt_error_recovery_info *info = bp->recovery_info;
5329
5330         if (info) {
5331                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5332                         memset(info, 0, sizeof(*info));
5333                 return;
5334         }
5335
5336         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5337                 return;
5338
5339         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5340                            sizeof(*info), 0);
5341         if (!info)
5342                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5343
5344         bp->recovery_info = info;
5345 }
5346
5347 static void bnxt_check_fw_status(struct bnxt *bp)
5348 {
5349         uint32_t fw_status;
5350
5351         if (!(bp->recovery_info &&
5352               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5353                 return;
5354
5355         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5356         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5357                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5358                             fw_status);
5359 }
5360
5361 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5362 {
5363         struct bnxt_error_recovery_info *info = bp->recovery_info;
5364         uint32_t status_loc;
5365         uint32_t sig_ver;
5366
5367         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5368                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5369         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5370                                    BNXT_GRCP_WINDOW_2_BASE +
5371                                    offsetof(struct hcomm_status,
5372                                             sig_ver)));
5373         /* If the signature is absent, then FW does not support this feature */
5374         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5375             HCOMM_STATUS_SIGNATURE_VAL)
5376                 return 0;
5377
5378         if (!info) {
5379                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5380                                    sizeof(*info), 0);
5381                 if (!info)
5382                         return -ENOMEM;
5383                 bp->recovery_info = info;
5384         } else {
5385                 memset(info, 0, sizeof(*info));
5386         }
5387
5388         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5389                                       BNXT_GRCP_WINDOW_2_BASE +
5390                                       offsetof(struct hcomm_status,
5391                                                fw_status_loc)));
5392
5393         /* Only pre-map the FW health status GRC register */
5394         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5395                 return 0;
5396
5397         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5398         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5399                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5400
5401         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5402                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5403
5404         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5405
5406         return 0;
5407 }
5408
5409 static int bnxt_init_fw(struct bnxt *bp)
5410 {
5411         uint16_t mtu;
5412         int rc = 0;
5413
5414         bp->fw_cap = 0;
5415
5416         rc = bnxt_map_hcomm_fw_status_reg(bp);
5417         if (rc)
5418                 return rc;
5419
5420         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5421         if (rc) {
5422                 bnxt_check_fw_status(bp);
5423                 return rc;
5424         }
5425
5426         rc = bnxt_hwrm_func_reset(bp);
5427         if (rc)
5428                 return -EIO;
5429
5430         rc = bnxt_hwrm_vnic_qcaps(bp);
5431         if (rc)
5432                 return rc;
5433
5434         rc = bnxt_hwrm_queue_qportcfg(bp);
5435         if (rc)
5436                 return rc;
5437
5438         /* Get the MAX capabilities for this function.
5439          * This function also allocates context memory for TQM rings and
5440          * informs the firmware about this allocated backing store memory.
5441          */
5442         rc = bnxt_hwrm_func_qcaps(bp);
5443         if (rc)
5444                 return rc;
5445
5446         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5447         if (rc)
5448                 return rc;
5449
5450         bnxt_hwrm_port_mac_qcfg(bp);
5451
5452         bnxt_hwrm_parent_pf_qcfg(bp);
5453
5454         bnxt_hwrm_port_phy_qcaps(bp);
5455
5456         bnxt_alloc_error_recovery_info(bp);
5457         /* Get the adapter error recovery support info */
5458         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5459         if (rc)
5460                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5461
5462         bnxt_hwrm_port_led_qcaps(bp);
5463
5464         return 0;
5465 }
5466
5467 static int
5468 bnxt_init_locks(struct bnxt *bp)
5469 {
5470         int err;
5471
5472         err = pthread_mutex_init(&bp->flow_lock, NULL);
5473         if (err) {
5474                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5475                 return err;
5476         }
5477
5478         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5479         if (err)
5480                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5481
5482         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5483         if (err)
5484                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5485         return err;
5486 }
5487
5488 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5489 {
5490         int rc = 0;
5491
5492         rc = bnxt_init_fw(bp);
5493         if (rc)
5494                 return rc;
5495
5496         if (!reconfig_dev) {
5497                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5498                 if (rc)
5499                         return rc;
5500         } else {
5501                 rc = bnxt_restore_dflt_mac(bp);
5502                 if (rc)
5503                         return rc;
5504         }
5505
5506         bnxt_config_vf_req_fwd(bp);
5507
5508         rc = bnxt_hwrm_func_driver_register(bp);
5509         if (rc) {
5510                 PMD_DRV_LOG(ERR, "Failed to register driver");
5511                 return -EBUSY;
5512         }
5513
5514         if (BNXT_PF(bp)) {
5515                 if (bp->pdev->max_vfs) {
5516                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5517                         if (rc) {
5518                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5519                                 return rc;
5520                         }
5521                 } else {
5522                         rc = bnxt_hwrm_allocate_pf_only(bp);
5523                         if (rc) {
5524                                 PMD_DRV_LOG(ERR,
5525                                             "Failed to allocate PF resources");
5526                                 return rc;
5527                         }
5528                 }
5529         }
5530
5531         rc = bnxt_alloc_mem(bp, reconfig_dev);
5532         if (rc)
5533                 return rc;
5534
5535         rc = bnxt_setup_int(bp);
5536         if (rc)
5537                 return rc;
5538
5539         rc = bnxt_request_int(bp);
5540         if (rc)
5541                 return rc;
5542
5543         rc = bnxt_init_ctx_mem(bp);
5544         if (rc) {
5545                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5546                 return rc;
5547         }
5548
5549         rc = bnxt_init_locks(bp);
5550         if (rc)
5551                 return rc;
5552
5553         return 0;
5554 }
5555
5556 static int
5557 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5558                           const char *value, void *opaque_arg)
5559 {
5560         struct bnxt *bp = opaque_arg;
5561         unsigned long truflow;
5562         char *end = NULL;
5563
5564         if (!value || !opaque_arg) {
5565                 PMD_DRV_LOG(ERR,
5566                             "Invalid parameter passed to truflow devargs.\n");
5567                 return -EINVAL;
5568         }
5569
5570         truflow = strtoul(value, &end, 10);
5571         if (end == NULL || *end != '\0' ||
5572             (truflow == ULONG_MAX && errno == ERANGE)) {
5573                 PMD_DRV_LOG(ERR,
5574                             "Invalid parameter passed to truflow devargs.\n");
5575                 return -EINVAL;
5576         }
5577
5578         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5579                 PMD_DRV_LOG(ERR,
5580                             "Invalid value passed to truflow devargs.\n");
5581                 return -EINVAL;
5582         }
5583
5584         bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5585         if (BNXT_TRUFLOW_EN(bp))
5586                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5587
5588         return 0;
5589 }
5590
5591 static int
5592 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5593                              const char *value, void *opaque_arg)
5594 {
5595         struct bnxt *bp = opaque_arg;
5596         unsigned long flow_xstat;
5597         char *end = NULL;
5598
5599         if (!value || !opaque_arg) {
5600                 PMD_DRV_LOG(ERR,
5601                             "Invalid parameter passed to flow_xstat devarg.\n");
5602                 return -EINVAL;
5603         }
5604
5605         flow_xstat = strtoul(value, &end, 10);
5606         if (end == NULL || *end != '\0' ||
5607             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5608                 PMD_DRV_LOG(ERR,
5609                             "Invalid parameter passed to flow_xstat devarg.\n");
5610                 return -EINVAL;
5611         }
5612
5613         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5614                 PMD_DRV_LOG(ERR,
5615                             "Invalid value passed to flow_xstat devarg.\n");
5616                 return -EINVAL;
5617         }
5618
5619         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5620         if (BNXT_FLOW_XSTATS_EN(bp))
5621                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5622
5623         return 0;
5624 }
5625
5626 static int
5627 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5628                                         const char *value, void *opaque_arg)
5629 {
5630         struct bnxt *bp = opaque_arg;
5631         unsigned long max_num_kflows;
5632         char *end = NULL;
5633
5634         if (!value || !opaque_arg) {
5635                 PMD_DRV_LOG(ERR,
5636                         "Invalid parameter passed to max_num_kflows devarg.\n");
5637                 return -EINVAL;
5638         }
5639
5640         max_num_kflows = strtoul(value, &end, 10);
5641         if (end == NULL || *end != '\0' ||
5642                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5643                 PMD_DRV_LOG(ERR,
5644                         "Invalid parameter passed to max_num_kflows devarg.\n");
5645                 return -EINVAL;
5646         }
5647
5648         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5649                 PMD_DRV_LOG(ERR,
5650                         "Invalid value passed to max_num_kflows devarg.\n");
5651                 return -EINVAL;
5652         }
5653
5654         bp->max_num_kflows = max_num_kflows;
5655         if (bp->max_num_kflows)
5656                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5657                                 max_num_kflows);
5658
5659         return 0;
5660 }
5661
5662 static void
5663 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5664 {
5665         struct rte_kvargs *kvlist;
5666
5667         if (devargs == NULL)
5668                 return;
5669
5670         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5671         if (kvlist == NULL)
5672                 return;
5673
5674         /*
5675          * Handler for "truflow" devarg.
5676          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5677          */
5678         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5679                            bnxt_parse_devarg_truflow, bp);
5680
5681         /*
5682          * Handler for "flow_xstat" devarg.
5683          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5684          */
5685         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5686                            bnxt_parse_devarg_flow_xstat, bp);
5687
5688         /*
5689          * Handler for "max_num_kflows" devarg.
5690          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5691          */
5692         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5693                            bnxt_parse_devarg_max_num_kflows, bp);
5694
5695         rte_kvargs_free(kvlist);
5696 }
5697
5698 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5699 {
5700         int rc = 0;
5701
5702         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5703                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5704                 if (rc)
5705                         PMD_DRV_LOG(ERR,
5706                                     "Failed to alloc switch domain: %d\n", rc);
5707                 else
5708                         PMD_DRV_LOG(INFO,
5709                                     "Switch domain allocated %d\n",
5710                                     bp->switch_domain_id);
5711         }
5712
5713         return rc;
5714 }
5715
5716 static int
5717 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5718 {
5719         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5720         static int version_printed;
5721         struct bnxt *bp;
5722         int rc;
5723
5724         if (version_printed++ == 0)
5725                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5726
5727         eth_dev->dev_ops = &bnxt_dev_ops;
5728         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5729         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5730         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5731         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5732         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5733
5734         /*
5735          * For secondary processes, we don't initialise any further
5736          * as primary has already done this work.
5737          */
5738         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5739                 return 0;
5740
5741         rte_eth_copy_pci_info(eth_dev, pci_dev);
5742
5743         bp = eth_dev->data->dev_private;
5744
5745         /* Parse dev arguments passed on when starting the DPDK application. */
5746         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5747
5748         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5749
5750         if (bnxt_vf_pciid(pci_dev->id.device_id))
5751                 bp->flags |= BNXT_FLAG_VF;
5752
5753         if (bnxt_thor_device(pci_dev->id.device_id))
5754                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5755
5756         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5757             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5758             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5759             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5760                 bp->flags |= BNXT_FLAG_STINGRAY;
5761
5762         rc = bnxt_init_board(eth_dev);
5763         if (rc) {
5764                 PMD_DRV_LOG(ERR,
5765                             "Failed to initialize board rc: %x\n", rc);
5766                 return rc;
5767         }
5768
5769         rc = bnxt_alloc_pf_info(bp);
5770         if (rc)
5771                 goto error_free;
5772
5773         rc = bnxt_alloc_link_info(bp);
5774         if (rc)
5775                 goto error_free;
5776
5777         rc = bnxt_alloc_parent_info(bp);
5778         if (rc)
5779                 goto error_free;
5780
5781         rc = bnxt_alloc_hwrm_resources(bp);
5782         if (rc) {
5783                 PMD_DRV_LOG(ERR,
5784                             "Failed to allocate hwrm resource rc: %x\n", rc);
5785                 goto error_free;
5786         }
5787         rc = bnxt_alloc_leds_info(bp);
5788         if (rc)
5789                 goto error_free;
5790
5791         rc = bnxt_alloc_cos_queues(bp);
5792         if (rc)
5793                 goto error_free;
5794
5795         rc = bnxt_init_resources(bp, false);
5796         if (rc)
5797                 goto error_free;
5798
5799         rc = bnxt_alloc_stats_mem(bp);
5800         if (rc)
5801                 goto error_free;
5802
5803         bnxt_alloc_switch_domain(bp);
5804
5805         /* Pass the information to the rte_eth_dev_close() that it should also
5806          * release the private port resources.
5807          */
5808         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5809
5810         PMD_DRV_LOG(INFO,
5811                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5812                     pci_dev->mem_resource[0].phys_addr,
5813                     pci_dev->mem_resource[0].addr);
5814
5815         return 0;
5816
5817 error_free:
5818         bnxt_dev_uninit(eth_dev);
5819         return rc;
5820 }
5821
5822
5823 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5824 {
5825         if (!ctx)
5826                 return;
5827
5828         if (ctx->va)
5829                 rte_free(ctx->va);
5830
5831         ctx->va = NULL;
5832         ctx->dma = RTE_BAD_IOVA;
5833         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5834 }
5835
5836 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5837 {
5838         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5839                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5840                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5841                                   bp->flow_stat->max_fc,
5842                                   false);
5843
5844         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5845                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5846                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5847                                   bp->flow_stat->max_fc,
5848                                   false);
5849
5850         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5851                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5852         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5853
5854         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5855                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5856         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5857
5858         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5859                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5860         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5861
5862         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5863                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5864         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5865 }
5866
5867 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5868 {
5869         bnxt_unregister_fc_ctx_mem(bp);
5870
5871         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5872         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5873         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5874         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5875 }
5876
5877 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5878 {
5879         if (BNXT_FLOW_XSTATS_EN(bp))
5880                 bnxt_uninit_fc_ctx_mem(bp);
5881 }
5882
5883 static void
5884 bnxt_free_error_recovery_info(struct bnxt *bp)
5885 {
5886         rte_free(bp->recovery_info);
5887         bp->recovery_info = NULL;
5888         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5889 }
5890
5891 static void
5892 bnxt_uninit_locks(struct bnxt *bp)
5893 {
5894         pthread_mutex_destroy(&bp->flow_lock);
5895         pthread_mutex_destroy(&bp->def_cp_lock);
5896         pthread_mutex_destroy(&bp->health_check_lock);
5897         if (bp->rep_info) {
5898                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5899                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
5900         }
5901 }
5902
5903 static int
5904 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5905 {
5906         int rc;
5907
5908         bnxt_free_int(bp);
5909         bnxt_free_mem(bp, reconfig_dev);
5910         bnxt_hwrm_func_buf_unrgtr(bp);
5911         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5912         bp->flags &= ~BNXT_FLAG_REGISTERED;
5913         bnxt_free_ctx_mem(bp);
5914         if (!reconfig_dev) {
5915                 bnxt_free_hwrm_resources(bp);
5916                 bnxt_free_error_recovery_info(bp);
5917         }
5918
5919         bnxt_uninit_ctx_mem(bp);
5920
5921         bnxt_uninit_locks(bp);
5922         bnxt_free_flow_stats_info(bp);
5923         bnxt_free_rep_info(bp);
5924         rte_free(bp->ptp_cfg);
5925         bp->ptp_cfg = NULL;
5926         return rc;
5927 }
5928
5929 static int
5930 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5931 {
5932         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5933                 return -EPERM;
5934
5935         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5936
5937         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5938                 bnxt_dev_close_op(eth_dev);
5939
5940         return 0;
5941 }
5942
5943 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5944 {
5945         struct bnxt *bp = eth_dev->data->dev_private;
5946         struct rte_eth_dev *vf_rep_eth_dev;
5947         int ret = 0, i;
5948
5949         if (!bp)
5950                 return -EINVAL;
5951
5952         for (i = 0; i < bp->num_reps; i++) {
5953                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5954                 if (!vf_rep_eth_dev)
5955                         continue;
5956                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5957                             vf_rep_eth_dev->data->port_id);
5958                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
5959         }
5960         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5961                     eth_dev->data->port_id);
5962         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5963
5964         return ret;
5965 }
5966
5967 static void bnxt_free_rep_info(struct bnxt *bp)
5968 {
5969         rte_free(bp->rep_info);
5970         bp->rep_info = NULL;
5971         rte_free(bp->cfa_code_map);
5972         bp->cfa_code_map = NULL;
5973 }
5974
5975 static int bnxt_init_rep_info(struct bnxt *bp)
5976 {
5977         int i = 0, rc;
5978
5979         if (bp->rep_info)
5980                 return 0;
5981
5982         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5983                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5984                                    0);
5985         if (!bp->rep_info) {
5986                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5987                 return -ENOMEM;
5988         }
5989         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5990                                        sizeof(*bp->cfa_code_map) *
5991                                        BNXT_MAX_CFA_CODE, 0);
5992         if (!bp->cfa_code_map) {
5993                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5994                 bnxt_free_rep_info(bp);
5995                 return -ENOMEM;
5996         }
5997
5998         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5999                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6000
6001         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6002         if (rc) {
6003                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6004                 bnxt_free_rep_info(bp);
6005                 return rc;
6006         }
6007
6008         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6009         if (rc) {
6010                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6011                 bnxt_free_rep_info(bp);
6012                 return rc;
6013         }
6014
6015         return rc;
6016 }
6017
6018 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6019                                struct rte_eth_devargs eth_da,
6020                                struct rte_eth_dev *backing_eth_dev)
6021 {
6022         struct rte_eth_dev *vf_rep_eth_dev;
6023         char name[RTE_ETH_NAME_MAX_LEN];
6024         struct bnxt *backing_bp;
6025         uint16_t num_rep;
6026         int i, ret = 0;
6027
6028         num_rep = eth_da.nb_representor_ports;
6029         if (num_rep > BNXT_MAX_VF_REPS) {
6030                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6031                             num_rep, BNXT_MAX_VF_REPS);
6032                 return -EINVAL;
6033         }
6034
6035         if (num_rep >= RTE_MAX_ETHPORTS) {
6036                 PMD_DRV_LOG(ERR,
6037                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6038                             num_rep, RTE_MAX_ETHPORTS);
6039                 return -EINVAL;
6040         }
6041
6042         backing_bp = backing_eth_dev->data->dev_private;
6043
6044         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6045                 PMD_DRV_LOG(ERR,
6046                             "Not a PF or trusted VF. No Representor support\n");
6047                 /* Returning an error is not an option.
6048                  * Applications are not handling this correctly
6049                  */
6050                 return 0;
6051         }
6052
6053         if (bnxt_init_rep_info(backing_bp))
6054                 return 0;
6055
6056         for (i = 0; i < num_rep; i++) {
6057                 struct bnxt_vf_representor representor = {
6058                         .vf_id = eth_da.representor_ports[i],
6059                         .switch_domain_id = backing_bp->switch_domain_id,
6060                         .parent_dev = backing_eth_dev
6061                 };
6062
6063                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6064                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6065                                     representor.vf_id, BNXT_MAX_VF_REPS);
6066                         continue;
6067                 }
6068
6069                 /* representor port net_bdf_port */
6070                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6071                          pci_dev->device.name, eth_da.representor_ports[i]);
6072
6073                 ret = rte_eth_dev_create(&pci_dev->device, name,
6074                                          sizeof(struct bnxt_vf_representor),
6075                                          NULL, NULL,
6076                                          bnxt_vf_representor_init,
6077                                          &representor);
6078                 if (ret) {
6079                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6080                                     "representor %s.", name);
6081                         goto err;
6082                 }
6083
6084                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6085                 if (!vf_rep_eth_dev) {
6086                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6087                                     " for VF-Rep: %s.", name);
6088                         ret = -ENODEV;
6089                         goto err;
6090                 }
6091
6092                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6093                                 backing_eth_dev->data->port_id);
6094                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6095                                                          vf_rep_eth_dev;
6096                 backing_bp->num_reps++;
6097         }
6098
6099         return 0;
6100
6101 err:
6102         /* If num_rep > 1, then rollback already created
6103          * ports, since we'll be failing the probe anyway
6104          */
6105         if (num_rep > 1)
6106                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6107
6108         return ret;
6109 }
6110
6111 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6112                           struct rte_pci_device *pci_dev)
6113 {
6114         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6115         struct rte_eth_dev *backing_eth_dev;
6116         uint16_t num_rep;
6117         int ret = 0;
6118
6119         if (pci_dev->device.devargs) {
6120                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6121                                             &eth_da);
6122                 if (ret)
6123                         return ret;
6124         }
6125
6126         num_rep = eth_da.nb_representor_ports;
6127         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6128                     num_rep);
6129
6130         /* We could come here after first level of probe is already invoked
6131          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6132          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6133          */
6134         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6135         if (backing_eth_dev == NULL) {
6136                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6137                                          sizeof(struct bnxt),
6138                                          eth_dev_pci_specific_init, pci_dev,
6139                                          bnxt_dev_init, NULL);
6140
6141                 if (ret || !num_rep)
6142                         return ret;
6143
6144                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6145         }
6146         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6147                     backing_eth_dev->data->port_id);
6148         /* probe representor ports now */
6149         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
6150
6151         return ret;
6152 }
6153
6154 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6155 {
6156         struct rte_eth_dev *eth_dev;
6157
6158         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6159         if (!eth_dev)
6160                 return 0; /* Invoked typically only by OVS-DPDK, by the
6161                            * time it comes here the eth_dev is already
6162                            * deleted by rte_eth_dev_close(), so returning
6163                            * +ve value will at least help in proper cleanup
6164                            */
6165
6166         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6167         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6168                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6169                         return rte_eth_dev_destroy(eth_dev,
6170                                                    bnxt_vf_representor_uninit);
6171                 else
6172                         return rte_eth_dev_destroy(eth_dev,
6173                                                    bnxt_dev_uninit);
6174         } else {
6175                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6176         }
6177 }
6178
6179 static struct rte_pci_driver bnxt_rte_pmd = {
6180         .id_table = bnxt_pci_id_map,
6181         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6182                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6183                                                   * and OVS-DPDK
6184                                                   */
6185         .probe = bnxt_pci_probe,
6186         .remove = bnxt_pci_remove,
6187 };
6188
6189 static bool
6190 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6191 {
6192         if (strcmp(dev->device->driver->name, drv->driver.name))
6193                 return false;
6194
6195         return true;
6196 }
6197
6198 bool is_bnxt_supported(struct rte_eth_dev *dev)
6199 {
6200         return is_device_supported(dev, &bnxt_rte_pmd);
6201 }
6202
6203 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6204 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6205 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6206 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");