drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_cpr.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30 #include "bnxt_util.h"
  31
  32 #define DRV_MODULE_NAME         "bnxt"
  33 static const char bnxt_version[] =
  34         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  35 int bnxt_logtype_driver;
  36
  37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  38
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  43 #define BROADCOM_DEV_ID_57301 0x16c8
  44 #define BROADCOM_DEV_ID_57302 0x16c9
  45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  48 #define BROADCOM_DEV_ID_NS2 0x16cd
  49 #define BROADCOM_DEV_ID_57311 0x16ce
  50 #define BROADCOM_DEV_ID_57312 0x16cf
  51 #define BROADCOM_DEV_ID_57402 0x16d0
  52 #define BROADCOM_DEV_ID_57404 0x16d1
  53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  57 #define BROADCOM_DEV_ID_57412 0x16d6
  58 #define BROADCOM_DEV_ID_57414 0x16d7
  59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  62 #define BROADCOM_DEV_ID_57412_MF 0x16de
  63 #define BROADCOM_DEV_ID_57314 0x16df
  64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  75 #define BROADCOM_DEV_ID_57508 0x1750
  76 #define BROADCOM_DEV_ID_57504 0x1751
  77 #define BROADCOM_DEV_ID_57502 0x1752
  78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
  79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
  80 #define BROADCOM_DEV_ID_58802 0xd802
  81 #define BROADCOM_DEV_ID_58804 0xd804
  82 #define BROADCOM_DEV_ID_58808 0x16f0
  83 #define BROADCOM_DEV_ID_58802_VF 0xd800
  84
  85 static const struct rte_pci_id bnxt_pci_id_map[] = {
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  87                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  89                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 131         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
 132         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
 133         { .vendor_id = 0, /* sentinel */ },
 134 };
 135
 136 #define BNXT_ETH_RSS_SUPPORT (  \
 137         ETH_RSS_IPV4 |          \
 138         ETH_RSS_NONFRAG_IPV4_TCP |      \
 139         ETH_RSS_NONFRAG_IPV4_UDP |      \
 140         ETH_RSS_IPV6 |          \
 141         ETH_RSS_NONFRAG_IPV6_TCP |      \
 142         ETH_RSS_NONFRAG_IPV6_UDP)
 143
 144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 145                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 146                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 147                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 148                                      DEV_TX_OFFLOAD_TCP_TSO | \
 149                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 150                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 152                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 153                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 154                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 155                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 156
 157 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 158                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 159                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 160                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 161                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 162                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 163                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 164                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 165                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 166                                      DEV_RX_OFFLOAD_TCP_LRO)
 167
 168 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 169 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 170 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 171 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 172 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 173 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 174 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 175
 176 int is_bnxt_in_error(struct bnxt *bp)
 177 {
 178         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 179                 return -EIO;
 180         if (bp->flags & BNXT_FLAG_FW_RESET)
 181                 return -EBUSY;
 182
 183         return 0;
 184 }
 185
 186 /***********************/
 187
 188 /*
 189  * High level utility functions
 190  */
 191
 192 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 193 {
 194         if (!BNXT_CHIP_THOR(bp))
 195                 return 1;
 196
 197         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 198                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 199                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 200 }
 201
 202 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 203 {
 204         if (!BNXT_CHIP_THOR(bp))
 205                 return HW_HASH_INDEX_SIZE;
 206
 207         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 208 }
 209
 210 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 211 {
 212         bnxt_free_filter_mem(bp);
 213         bnxt_free_vnic_attributes(bp);
 214         bnxt_free_vnic_mem(bp);
 215
 216         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 217          * If the number of rings change across fw update,
 218          * we don't have much choice except to warn the user.
 219          */
 220         if (!reconfig) {
 221                 bnxt_free_stats(bp);
 222                 bnxt_free_tx_rings(bp);
 223                 bnxt_free_rx_rings(bp);
 224         }
 225         bnxt_free_async_cp_ring(bp);
 226 }
 227
 228 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 229 {
 230         int rc;
 231
 232         rc = bnxt_alloc_ring_grps(bp);
 233         if (rc)
 234                 goto alloc_mem_err;
 235
 236         rc = bnxt_alloc_async_ring_struct(bp);
 237         if (rc)
 238                 goto alloc_mem_err;
 239
 240         rc = bnxt_alloc_vnic_mem(bp);
 241         if (rc)
 242                 goto alloc_mem_err;
 243
 244         rc = bnxt_alloc_vnic_attributes(bp);
 245         if (rc)
 246                 goto alloc_mem_err;
 247
 248         rc = bnxt_alloc_filter_mem(bp);
 249         if (rc)
 250                 goto alloc_mem_err;
 251
 252         rc = bnxt_alloc_async_cp_ring(bp);
 253         if (rc)
 254                 goto alloc_mem_err;
 255
 256         return 0;
 257
 258 alloc_mem_err:
 259         bnxt_free_mem(bp, reconfig);
 260         return rc;
 261 }
 262
 263 static int bnxt_init_chip(struct bnxt *bp)
 264 {
 265         struct bnxt_rx_queue *rxq;
 266         struct rte_eth_link new;
 267         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 268         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 269         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 270         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 271         uint32_t intr_vector = 0;
 272         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 273         uint32_t vec = BNXT_MISC_VEC_ID;
 274         unsigned int i, j;
 275         int rc;
 276
 277         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 278                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 279                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 280                 bp->flags |= BNXT_FLAG_JUMBO;
 281         } else {
 282                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 283                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 284                 bp->flags &= ~BNXT_FLAG_JUMBO;
 285         }
 286
 287         /* THOR does not support ring groups.
 288          * But we will use the array to save RSS context IDs.
 289          */
 290         if (BNXT_CHIP_THOR(bp))
 291                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 292
 293         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 294         if (rc) {
 295                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 296                 goto err_out;
 297         }
 298
 299         rc = bnxt_alloc_hwrm_rings(bp);
 300         if (rc) {
 301                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 302                 goto err_out;
 303         }
 304
 305         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 306         if (rc) {
 307                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 308                 goto err_out;
 309         }
 310
 311         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 312                 goto skip_cosq_cfg;
 313
 314         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 315                 if (bp->rx_cos_queue[i].id != 0xff) {
 316                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 317
 318                         if (!vnic) {
 319                                 PMD_DRV_LOG(ERR,
 320                                             "Num pools more than FW profile\n");
 321                                 rc = -EINVAL;
 322                                 goto err_out;
 323                         }
 324                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 325                         bp->rx_cosq_cnt++;
 326                 }
 327         }
 328
 329 skip_cosq_cfg:
 330         rc = bnxt_mq_rx_configure(bp);
 331         if (rc) {
 332                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 333                 goto err_out;
 334         }
 335
 336         /* VNIC configuration */
 337         for (i = 0; i < bp->nr_vnics; i++) {
 338                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 339                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 340
 341                 rc = bnxt_vnic_grp_alloc(bp, vnic);
 342                 if (rc)
 343                         goto err_out;
 344
 345                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 346                             i, vnic, vnic->fw_grp_ids);
 347
 348                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 349                 if (rc) {
 350                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 351                                 i, rc);
 352                         goto err_out;
 353                 }
 354
 355                 /* Alloc RSS context only if RSS mode is enabled */
 356                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 357                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 358
 359                         rc = 0;
 360                         for (j = 0; j < nr_ctxs; j++) {
 361                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 362                                 if (rc)
 363                                         break;
 364                         }
 365                         if (rc) {
 366                                 PMD_DRV_LOG(ERR,
 367                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 368                                   i, j, rc);
 369                                 goto err_out;
 370                         }
 371                         vnic->num_lb_ctxts = nr_ctxs;
 372                 }
 373
 374                 /*
 375                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 376                  * setting is not available at this time, it will not be
 377                  * configured correctly in the CFA.
 378                  */
 379                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 380                         vnic->vlan_strip = true;
 381                 else
 382                         vnic->vlan_strip = false;
 383
 384                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 385                 if (rc) {
 386                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 387                                 i, rc);
 388                         goto err_out;
 389                 }
 390
 391                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 392                 if (rc) {
 393                         PMD_DRV_LOG(ERR,
 394                                 "HWRM vnic %d filter failure rc: %x\n",
 395                                 i, rc);
 396                         goto err_out;
 397                 }
 398
 399                 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 400                         rxq = bp->eth_dev->data->rx_queues[j];
 401
 402                         PMD_DRV_LOG(DEBUG,
 403                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 404                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 405
 406                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 407                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 408                 }
 409
 410                 rc = bnxt_vnic_rss_configure(bp, vnic);
 411                 if (rc) {
 412                         PMD_DRV_LOG(ERR,
 413                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 414                         goto err_out;
 415                 }
 416
 417                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 418
 419                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 420                     DEV_RX_OFFLOAD_TCP_LRO)
 421                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 422                 else
 423                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 424         }
 425         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 426         if (rc) {
 427                 PMD_DRV_LOG(ERR,
 428                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 429                 goto err_out;
 430         }
 431
 432         /* check and configure queue intr-vector mapping */
 433         if ((rte_intr_cap_multiple(intr_handle) ||
 434              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 435             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 436                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 437                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 438                 if (intr_vector > bp->rx_cp_nr_rings) {
 439                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 440                                         bp->rx_cp_nr_rings);
 441                         return -ENOTSUP;
 442                 }
 443                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 444                 if (rc)
 445                         return rc;
 446         }
 447
 448         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 449                 intr_handle->intr_vec =
 450                         rte_zmalloc("intr_vec",
 451                                     bp->eth_dev->data->nb_rx_queues *
 452                                     sizeof(int), 0);
 453                 if (intr_handle->intr_vec == NULL) {
 454                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 455                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 456                         rc = -ENOMEM;
 457                         goto err_disable;
 458                 }
 459                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 460                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 461                          intr_handle->intr_vec, intr_handle->nb_efd,
 462                         intr_handle->max_intr);
 463                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 464                      queue_id++) {
 465                         intr_handle->intr_vec[queue_id] =
 466                                                         vec + BNXT_RX_VEC_START;
 467                         if (vec < base + intr_handle->nb_efd - 1)
 468                                 vec++;
 469                 }
 470         }
 471
 472         /* enable uio/vfio intr/eventfd mapping */
 473         rc = rte_intr_enable(intr_handle);
 474         if (rc)
 475                 goto err_free;
 476
 477         rc = bnxt_get_hwrm_link_config(bp, &new);
 478         if (rc) {
 479                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 480                 goto err_free;
 481         }
 482
 483         if (!bp->link_info.link_up) {
 484                 rc = bnxt_set_hwrm_link_config(bp, true);
 485                 if (rc) {
 486                         PMD_DRV_LOG(ERR,
 487                                 "HWRM link config failure rc: %x\n", rc);
 488                         goto err_free;
 489                 }
 490         }
 491         bnxt_print_link_info(bp->eth_dev);
 492
 493         return 0;
 494
 495 err_free:
 496         rte_free(intr_handle->intr_vec);
 497 err_disable:
 498         rte_intr_efd_disable(intr_handle);
 499 err_out:
 500         /* Some of the error status returned by FW may not be from errno.h */
 501         if (rc > 0)
 502                 rc = -EIO;
 503
 504         return rc;
 505 }
 506
 507 static int bnxt_shutdown_nic(struct bnxt *bp)
 508 {
 509         bnxt_free_all_hwrm_resources(bp);
 510         bnxt_free_all_filters(bp);
 511         bnxt_free_all_vnics(bp);
 512         return 0;
 513 }
 514
 515 static int bnxt_init_nic(struct bnxt *bp)
 516 {
 517         int rc;
 518
 519         if (BNXT_HAS_RING_GRPS(bp)) {
 520                 rc = bnxt_init_ring_grps(bp);
 521                 if (rc)
 522                         return rc;
 523         }
 524
 525         bnxt_init_vnics(bp);
 526         bnxt_init_filters(bp);
 527
 528         return 0;
 529 }
 530
 531 /*
 532  * Device configuration and status function
 533  */
 534
 535 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 536                                 struct rte_eth_dev_info *dev_info)
 537 {
 538         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 539         struct bnxt *bp = eth_dev->data->dev_private;
 540         uint16_t max_vnics, i, j, vpool, vrxq;
 541         unsigned int max_rx_rings;
 542         int rc;
 543
 544         rc = is_bnxt_in_error(bp);
 545         if (rc)
 546                 return rc;
 547
 548         /* MAC Specifics */
 549         dev_info->max_mac_addrs = bp->max_l2_ctx;
 550         dev_info->max_hash_mac_addrs = 0;
 551
 552         /* PF/VF specifics */
 553         if (BNXT_PF(bp))
 554                 dev_info->max_vfs = pdev->max_vfs;
 555
 556         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 557         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 558         dev_info->max_rx_queues = max_rx_rings;
 559         dev_info->max_tx_queues = max_rx_rings;
 560         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 561         dev_info->hash_key_size = 40;
 562         max_vnics = bp->max_vnics;
 563
 564         /* MTU specifics */
 565         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 566         dev_info->max_mtu = BNXT_MAX_MTU;
 567
 568         /* Fast path specifics */
 569         dev_info->min_rx_bufsize = 1;
 570         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 571
 572         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 573         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 574                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 575         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 576         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 577
 578         /* *INDENT-OFF* */
 579         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 580                 .rx_thresh = {
 581                         .pthresh = 8,
 582                         .hthresh = 8,
 583                         .wthresh = 0,
 584                 },
 585                 .rx_free_thresh = 32,
 586                 /* If no descriptors available, pkts are dropped by default */
 587                 .rx_drop_en = 1,
 588         };
 589
 590         dev_info->default_txconf = (struct rte_eth_txconf) {
 591                 .tx_thresh = {
 592                         .pthresh = 32,
 593                         .hthresh = 0,
 594                         .wthresh = 0,
 595                 },
 596                 .tx_free_thresh = 32,
 597                 .tx_rs_thresh = 32,
 598         };
 599         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 600
 601         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 602         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 603         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 604         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 605         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 606
 607         /* *INDENT-ON* */
 608
 609         /*
 610          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 611          *       need further investigation.
 612          */
 613
 614         /* VMDq resources */
 615         vpool = 64; /* ETH_64_POOLS */
 616         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 617         for (i = 0; i < 4; vpool >>= 1, i++) {
 618                 if (max_vnics > vpool) {
 619                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 620                                 if (dev_info->max_rx_queues > vrxq) {
 621                                         if (vpool > vrxq)
 622                                                 vpool = vrxq;
 623                                         goto found;
 624                                 }
 625                         }
 626                         /* Not enough resources to support VMDq */
 627                         break;
 628                 }
 629         }
 630         /* Not enough resources to support VMDq */
 631         vpool = 0;
 632         vrxq = 0;
 633 found:
 634         dev_info->max_vmdq_pools = vpool;
 635         dev_info->vmdq_queue_num = vrxq;
 636
 637         dev_info->vmdq_pool_base = 0;
 638         dev_info->vmdq_queue_base = 0;
 639
 640         return 0;
 641 }
 642
 643 /* Configure the device based on the configuration provided */
 644 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 645 {
 646         struct bnxt *bp = eth_dev->data->dev_private;
 647         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 648         int rc;
 649
 650         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 651         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 652         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 653         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 654
 655         rc = is_bnxt_in_error(bp);
 656         if (rc)
 657                 return rc;
 658
 659         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 660                 rc = bnxt_hwrm_check_vf_rings(bp);
 661                 if (rc) {
 662                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 663                         return -ENOSPC;
 664                 }
 665
 666                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 667                 if (rc) {
 668                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 669                         return -ENOSPC;
 670                 }
 671         } else {
 672                 /* legacy driver needs to get updated values */
 673                 rc = bnxt_hwrm_func_qcaps(bp);
 674                 if (rc) {
 675                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 676                         return rc;
 677                 }
 678         }
 679
 680         /* Inherit new configurations */
 681         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 682             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 683             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 684                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 685             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 686             bp->max_stat_ctx)
 687                 goto resource_error;
 688
 689         if (BNXT_HAS_RING_GRPS(bp) &&
 690             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 691                 goto resource_error;
 692
 693         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 694             bp->max_vnics < eth_dev->data->nb_rx_queues)
 695                 goto resource_error;
 696
 697         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 698         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 699
 700         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 701                 eth_dev->data->mtu =
 702                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 703                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 704                         BNXT_NUM_VLANS;
 705                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 706         }
 707         return 0;
 708
 709 resource_error:
 710         PMD_DRV_LOG(ERR,
 711                     "Insufficient resources to support requested config\n");
 712         PMD_DRV_LOG(ERR,
 713                     "Num Queues Requested: Tx %d, Rx %d\n",
 714                     eth_dev->data->nb_tx_queues,
 715                     eth_dev->data->nb_rx_queues);
 716         PMD_DRV_LOG(ERR,
 717                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 718                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 719                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 720         return -ENOSPC;
 721 }
 722
 723 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 724 {
 725         struct rte_eth_link *link = &eth_dev->data->dev_link;
 726
 727         if (link->link_status)
 728                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 729                         eth_dev->data->port_id,
 730                         (uint32_t)link->link_speed,
 731                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 732                         ("full-duplex") : ("half-duplex\n"));
 733         else
 734                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 735                         eth_dev->data->port_id);
 736 }
 737
 738 /*
 739  * Determine whether the current configuration requires support for scattered
 740  * receive; return 1 if scattered receive is required and 0 if not.
 741  */
 742 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 743 {
 744         uint16_t buf_size;
 745         int i;
 746
 747         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 748                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 749
 750                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 751                                       RTE_PKTMBUF_HEADROOM);
 752                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 753                         return 1;
 754         }
 755         return 0;
 756 }
 757
 758 static eth_rx_burst_t
 759 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 760 {
 761 #ifdef RTE_ARCH_X86
 762 #ifndef RTE_LIBRTE_IEEE1588
 763         /*
 764          * Vector mode receive can be enabled only if scatter rx is not
 765          * in use and rx offloads are limited to VLAN stripping and
 766          * CRC stripping.
 767          */
 768         if (!eth_dev->data->scattered_rx &&
 769             !(eth_dev->data->dev_conf.rxmode.offloads &
 770               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 771                 DEV_RX_OFFLOAD_KEEP_CRC |
 772                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 773                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 774                 DEV_RX_OFFLOAD_UDP_CKSUM |
 775                 DEV_RX_OFFLOAD_TCP_CKSUM |
 776                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 777                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 778                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 779                             eth_dev->data->port_id);
 780                 return bnxt_recv_pkts_vec;
 781         }
 782         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 783                     eth_dev->data->port_id);
 784         PMD_DRV_LOG(INFO,
 785                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 786                     eth_dev->data->port_id,
 787                     eth_dev->data->scattered_rx,
 788                     eth_dev->data->dev_conf.rxmode.offloads);
 789 #endif
 790 #endif
 791         return bnxt_recv_pkts;
 792 }
 793
 794 static eth_tx_burst_t
 795 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 796 {
 797 #ifdef RTE_ARCH_X86
 798 #ifndef RTE_LIBRTE_IEEE1588
 799         /*
 800          * Vector mode transmit can be enabled only if not using scatter rx
 801          * or tx offloads.
 802          */
 803         if (!eth_dev->data->scattered_rx &&
 804             !eth_dev->data->dev_conf.txmode.offloads) {
 805                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 806                             eth_dev->data->port_id);
 807                 return bnxt_xmit_pkts_vec;
 808         }
 809         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 810                     eth_dev->data->port_id);
 811         PMD_DRV_LOG(INFO,
 812                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 813                     eth_dev->data->port_id,
 814                     eth_dev->data->scattered_rx,
 815                     eth_dev->data->dev_conf.txmode.offloads);
 816 #endif
 817 #endif
 818         return bnxt_xmit_pkts;
 819 }
 820
 821 static int bnxt_handle_if_change_status(struct bnxt *bp)
 822 {
 823         int rc;
 824
 825         /* Since fw has undergone a reset and lost all contexts,
 826          * set fatal flag to not issue hwrm during cleanup
 827          */
 828         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 829         bnxt_uninit_resources(bp, true);
 830
 831         /* clear fatal flag so that re-init happens */
 832         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 833         rc = bnxt_init_resources(bp, true);
 834
 835         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 836
 837         return rc;
 838 }
 839
 840 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 841 {
 842         struct bnxt *bp = eth_dev->data->dev_private;
 843         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 844         int vlan_mask = 0;
 845         int rc;
 846
 847         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 848                 PMD_DRV_LOG(ERR,
 849                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 850                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 851         }
 852
 853         bnxt_enable_int(bp);
 854         rc = bnxt_hwrm_if_change(bp, 1);
 855         if (!rc) {
 856                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 857                         rc = bnxt_handle_if_change_status(bp);
 858                         if (rc)
 859                                 return rc;
 860                 }
 861         }
 862
 863         rc = bnxt_init_chip(bp);
 864         if (rc)
 865                 goto error;
 866
 867         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 868
 869         bnxt_link_update_op(eth_dev, 1);
 870
 871         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 872                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 873         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 874                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 875         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 876         if (rc)
 877                 goto error;
 878
 879         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 880         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 881
 882         bp->flags |= BNXT_FLAG_INIT_DONE;
 883         eth_dev->data->dev_started = 1;
 884         bp->dev_stopped = 0;
 885         bnxt_schedule_fw_health_check(bp);
 886         return 0;
 887
 888 error:
 889         bnxt_hwrm_if_change(bp, 0);
 890         bnxt_shutdown_nic(bp);
 891         bnxt_free_tx_mbufs(bp);
 892         bnxt_free_rx_mbufs(bp);
 893         return rc;
 894 }
 895
 896 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 897 {
 898         struct bnxt *bp = eth_dev->data->dev_private;
 899         int rc = 0;
 900
 901         if (!bp->link_info.link_up)
 902                 rc = bnxt_set_hwrm_link_config(bp, true);
 903         if (!rc)
 904                 eth_dev->data->dev_link.link_status = 1;
 905
 906         bnxt_print_link_info(eth_dev);
 907         return 0;
 908 }
 909
 910 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 911 {
 912         struct bnxt *bp = eth_dev->data->dev_private;
 913
 914         eth_dev->data->dev_link.link_status = 0;
 915         bnxt_set_hwrm_link_config(bp, false);
 916         bp->link_info.link_up = 0;
 917
 918         return 0;
 919 }
 920
 921 /* Unload the driver, release resources */
 922 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 923 {
 924         struct bnxt *bp = eth_dev->data->dev_private;
 925         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 926         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 927
 928         eth_dev->data->dev_started = 0;
 929         /* Prevent crashes when queues are still in use */
 930         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 931         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 932
 933         bnxt_disable_int(bp);
 934
 935         /* disable uio/vfio intr/eventfd mapping */
 936         rte_intr_disable(intr_handle);
 937
 938         bnxt_cancel_fw_health_check(bp);
 939
 940         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 941         if (bp->eth_dev->data->dev_started) {
 942                 /* TBD: STOP HW queues DMA */
 943                 eth_dev->data->dev_link.link_status = 0;
 944         }
 945         bnxt_dev_set_link_down_op(eth_dev);
 946         /* Wait for link to be reset and the async notification to process. */
 947         rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
 948
 949         /* Clean queue intr-vector mapping */
 950         rte_intr_efd_disable(intr_handle);
 951         if (intr_handle->intr_vec != NULL) {
 952                 rte_free(intr_handle->intr_vec);
 953                 intr_handle->intr_vec = NULL;
 954         }
 955
 956         bnxt_hwrm_port_clr_stats(bp);
 957         bnxt_free_tx_mbufs(bp);
 958         bnxt_free_rx_mbufs(bp);
 959         /* Process any remaining notifications in default completion queue */
 960         bnxt_int_handler(eth_dev);
 961         bnxt_shutdown_nic(bp);
 962         bnxt_hwrm_if_change(bp, 0);
 963         bp->dev_stopped = 1;
 964 }
 965
 966 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 967 {
 968         struct bnxt *bp = eth_dev->data->dev_private;
 969
 970         if (bp->dev_stopped == 0)
 971                 bnxt_dev_stop_op(eth_dev);
 972
 973         if (eth_dev->data->mac_addrs != NULL) {
 974                 rte_free(eth_dev->data->mac_addrs);
 975                 eth_dev->data->mac_addrs = NULL;
 976         }
 977         if (bp->grp_info != NULL) {
 978                 rte_free(bp->grp_info);
 979                 bp->grp_info = NULL;
 980         }
 981
 982         bnxt_dev_uninit(eth_dev);
 983 }
 984
 985 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 986                                     uint32_t index)
 987 {
 988         struct bnxt *bp = eth_dev->data->dev_private;
 989         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 990         struct bnxt_vnic_info *vnic;
 991         struct bnxt_filter_info *filter, *temp_filter;
 992         uint32_t i;
 993
 994         if (is_bnxt_in_error(bp))
 995                 return;
 996
 997         /*
 998          * Loop through all VNICs from the specified filter flow pools to
 999          * remove the corresponding MAC addr filter
1000          */
1001         for (i = 0; i < bp->nr_vnics; i++) {
1002                 if (!(pool_mask & (1ULL << i)))
1003                         continue;
1004
1005                 vnic = &bp->vnic_info[i];
1006                 filter = STAILQ_FIRST(&vnic->filter);
1007                 while (filter) {
1008                         temp_filter = STAILQ_NEXT(filter, next);
1009                         if (filter->mac_index == index) {
1010                                 STAILQ_REMOVE(&vnic->filter, filter,
1011                                                 bnxt_filter_info, next);
1012                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1013                                 filter->mac_index = INVALID_MAC_INDEX;
1014                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1015                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1016                                                    filter, next);
1017                         }
1018                         filter = temp_filter;
1019                 }
1020         }
1021 }
1022
1023 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1024                                struct rte_ether_addr *mac_addr, uint32_t index)
1025 {
1026         struct bnxt_filter_info *filter;
1027         int rc = 0;
1028
1029         filter = STAILQ_FIRST(&vnic->filter);
1030         /* During bnxt_mac_addr_add_op, default MAC is
1031          * already programmed, so skip it. But, when
1032          * hw-vlan-filter is turned OFF from ON, default
1033          * MAC filter should be restored
1034          */
1035         if (filter->dflt)
1036                 return 0;
1037
1038         filter = bnxt_alloc_filter(bp);
1039         if (!filter) {
1040                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1041                 return -ENODEV;
1042         }
1043
1044         filter->mac_index = index;
1045         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1046          * if the MAC that's been programmed now is a different one, then,
1047          * copy that addr to filter->l2_addr
1048          */
1049         if (mac_addr)
1050                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1051         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1052
1053         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1054         if (!rc) {
1055                 if (filter->mac_index == 0) {
1056                         filter->dflt = true;
1057                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1058                 } else {
1059                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1060                 }
1061         } else {
1062                 filter->mac_index = INVALID_MAC_INDEX;
1063                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1064                 bnxt_free_filter(bp, filter);
1065         }
1066
1067         return rc;
1068 }
1069
1070 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1071                                 struct rte_ether_addr *mac_addr,
1072                                 uint32_t index, uint32_t pool)
1073 {
1074         struct bnxt *bp = eth_dev->data->dev_private;
1075         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1076         struct bnxt_filter_info *filter;
1077         int rc = 0;
1078
1079         rc = is_bnxt_in_error(bp);
1080         if (rc)
1081                 return rc;
1082
1083         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1084                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1085                 return -ENOTSUP;
1086         }
1087
1088         if (!vnic) {
1089                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1090                 return -EINVAL;
1091         }
1092         /* Attach requested MAC address to the new l2_filter */
1093         STAILQ_FOREACH(filter, &vnic->filter, next) {
1094                 if (filter->mac_index == index) {
1095                         PMD_DRV_LOG(ERR,
1096                                 "MAC addr already existed for pool %d\n", pool);
1097                         return 0;
1098                 }
1099         }
1100
1101         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index);
1102
1103         return rc;
1104 }
1105
1106 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1107 {
1108         int rc = 0;
1109         struct bnxt *bp = eth_dev->data->dev_private;
1110         struct rte_eth_link new;
1111         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1112
1113         rc = is_bnxt_in_error(bp);
1114         if (rc)
1115                 return rc;
1116
1117         memset(&new, 0, sizeof(new));
1118         do {
1119                 /* Retrieve link info from hardware */
1120                 rc = bnxt_get_hwrm_link_config(bp, &new);
1121                 if (rc) {
1122                         new.link_speed = ETH_LINK_SPEED_100M;
1123                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1124                         PMD_DRV_LOG(ERR,
1125                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1126                         goto out;
1127                 }
1128
1129                 if (!wait_to_complete || new.link_status)
1130                         break;
1131
1132                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1133         } while (cnt--);
1134
1135 out:
1136         /* Timed out or success */
1137         if (new.link_status != eth_dev->data->dev_link.link_status ||
1138         new.link_speed != eth_dev->data->dev_link.link_speed) {
1139                 rte_eth_linkstatus_set(eth_dev, &new);
1140
1141                 _rte_eth_dev_callback_process(eth_dev,
1142                                               RTE_ETH_EVENT_INTR_LSC,
1143                                               NULL);
1144
1145                 bnxt_print_link_info(eth_dev);
1146         }
1147
1148         return rc;
1149 }
1150
1151 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1152 {
1153         struct bnxt *bp = eth_dev->data->dev_private;
1154         struct bnxt_vnic_info *vnic;
1155         uint32_t old_flags;
1156         int rc;
1157
1158         rc = is_bnxt_in_error(bp);
1159         if (rc)
1160                 return rc;
1161
1162         if (bp->vnic_info == NULL)
1163                 return 0;
1164
1165         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1166
1167         old_flags = vnic->flags;
1168         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1169         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1170         if (rc != 0)
1171                 vnic->flags = old_flags;
1172
1173         return rc;
1174 }
1175
1176 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1177 {
1178         struct bnxt *bp = eth_dev->data->dev_private;
1179         struct bnxt_vnic_info *vnic;
1180         uint32_t old_flags;
1181         int rc;
1182
1183         rc = is_bnxt_in_error(bp);
1184         if (rc)
1185                 return rc;
1186
1187         if (bp->vnic_info == NULL)
1188                 return 0;
1189
1190         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1191
1192         old_flags = vnic->flags;
1193         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1194         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1195         if (rc != 0)
1196                 vnic->flags = old_flags;
1197
1198         return rc;
1199 }
1200
1201 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1202 {
1203         struct bnxt *bp = eth_dev->data->dev_private;
1204         struct bnxt_vnic_info *vnic;
1205         uint32_t old_flags;
1206         int rc;
1207
1208         rc = is_bnxt_in_error(bp);
1209         if (rc)
1210                 return rc;
1211
1212         if (bp->vnic_info == NULL)
1213                 return 0;
1214
1215         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1216
1217         old_flags = vnic->flags;
1218         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1219         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1220         if (rc != 0)
1221                 vnic->flags = old_flags;
1222
1223         return rc;
1224 }
1225
1226 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1227 {
1228         struct bnxt *bp = eth_dev->data->dev_private;
1229         struct bnxt_vnic_info *vnic;
1230         uint32_t old_flags;
1231         int rc;
1232
1233         rc = is_bnxt_in_error(bp);
1234         if (rc)
1235                 return rc;
1236
1237         if (bp->vnic_info == NULL)
1238                 return 0;
1239
1240         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1241
1242         old_flags = vnic->flags;
1243         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1244         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1245         if (rc != 0)
1246                 vnic->flags = old_flags;
1247
1248         return rc;
1249 }
1250
1251 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1252 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1253 {
1254         if (qid >= bp->rx_nr_rings)
1255                 return NULL;
1256
1257         return bp->eth_dev->data->rx_queues[qid];
1258 }
1259
1260 /* Return rxq corresponding to a given rss table ring/group ID. */
1261 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1262 {
1263         struct bnxt_rx_queue *rxq;
1264         unsigned int i;
1265
1266         if (!BNXT_HAS_RING_GRPS(bp)) {
1267                 for (i = 0; i < bp->rx_nr_rings; i++) {
1268                         rxq = bp->eth_dev->data->rx_queues[i];
1269                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1270                                 return rxq->index;
1271                 }
1272         } else {
1273                 for (i = 0; i < bp->rx_nr_rings; i++) {
1274                         if (bp->grp_info[i].fw_grp_id == fwr)
1275                                 return i;
1276                 }
1277         }
1278
1279         return INVALID_HW_RING_ID;
1280 }
1281
1282 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1283                             struct rte_eth_rss_reta_entry64 *reta_conf,
1284                             uint16_t reta_size)
1285 {
1286         struct bnxt *bp = eth_dev->data->dev_private;
1287         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1288         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1289         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1290         uint16_t idx, sft;
1291         int i, rc;
1292
1293         rc = is_bnxt_in_error(bp);
1294         if (rc)
1295                 return rc;
1296
1297         if (!vnic->rss_table)
1298                 return -EINVAL;
1299
1300         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1301                 return -EINVAL;
1302
1303         if (reta_size != tbl_size) {
1304                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1305                         "(%d) must equal the size supported by the hardware "
1306                         "(%d)\n", reta_size, tbl_size);
1307                 return -EINVAL;
1308         }
1309
1310         for (i = 0; i < reta_size; i++) {
1311                 struct bnxt_rx_queue *rxq;
1312
1313                 idx = i / RTE_RETA_GROUP_SIZE;
1314                 sft = i % RTE_RETA_GROUP_SIZE;
1315
1316                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1317                         continue;
1318
1319                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1320                 if (!rxq) {
1321                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1322                         return -EINVAL;
1323                 }
1324
1325                 if (BNXT_CHIP_THOR(bp)) {
1326                         vnic->rss_table[i * 2] =
1327                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1328                         vnic->rss_table[i * 2 + 1] =
1329                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1330                 } else {
1331                         vnic->rss_table[i] =
1332                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1333                 }
1334
1335                 vnic->rss_table[i] =
1336                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1337         }
1338
1339         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1340         return 0;
1341 }
1342
1343 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1344                               struct rte_eth_rss_reta_entry64 *reta_conf,
1345                               uint16_t reta_size)
1346 {
1347         struct bnxt *bp = eth_dev->data->dev_private;
1348         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1349         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1350         uint16_t idx, sft, i;
1351         int rc;
1352
1353         rc = is_bnxt_in_error(bp);
1354         if (rc)
1355                 return rc;
1356
1357         /* Retrieve from the default VNIC */
1358         if (!vnic)
1359                 return -EINVAL;
1360         if (!vnic->rss_table)
1361                 return -EINVAL;
1362
1363         if (reta_size != tbl_size) {
1364                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1365                         "(%d) must equal the size supported by the hardware "
1366                         "(%d)\n", reta_size, tbl_size);
1367                 return -EINVAL;
1368         }
1369
1370         for (idx = 0, i = 0; i < reta_size; i++) {
1371                 idx = i / RTE_RETA_GROUP_SIZE;
1372                 sft = i % RTE_RETA_GROUP_SIZE;
1373
1374                 if (reta_conf[idx].mask & (1ULL << sft)) {
1375                         uint16_t qid;
1376
1377                         if (BNXT_CHIP_THOR(bp))
1378                                 qid = bnxt_rss_to_qid(bp,
1379                                                       vnic->rss_table[i * 2]);
1380                         else
1381                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1382
1383                         if (qid == INVALID_HW_RING_ID) {
1384                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1385                                 return -EINVAL;
1386                         }
1387                         reta_conf[idx].reta[sft] = qid;
1388                 }
1389         }
1390
1391         return 0;
1392 }
1393
1394 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1395                                    struct rte_eth_rss_conf *rss_conf)
1396 {
1397         struct bnxt *bp = eth_dev->data->dev_private;
1398         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1399         struct bnxt_vnic_info *vnic;
1400         int rc;
1401
1402         rc = is_bnxt_in_error(bp);
1403         if (rc)
1404                 return rc;
1405
1406         /*
1407          * If RSS enablement were different than dev_configure,
1408          * then return -EINVAL
1409          */
1410         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1411                 if (!rss_conf->rss_hf)
1412                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1413         } else {
1414                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1415                         return -EINVAL;
1416         }
1417
1418         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1419         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1420
1421         /* Update the default RSS VNIC(s) */
1422         vnic = &bp->vnic_info[0];
1423         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1424
1425         /*
1426          * If hashkey is not specified, use the previously configured
1427          * hashkey
1428          */
1429         if (!rss_conf->rss_key)
1430                 goto rss_config;
1431
1432         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1433                 PMD_DRV_LOG(ERR,
1434                             "Invalid hashkey length, should be 16 bytes\n");
1435                 return -EINVAL;
1436         }
1437         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1438
1439 rss_config:
1440         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1441         return 0;
1442 }
1443
1444 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1445                                      struct rte_eth_rss_conf *rss_conf)
1446 {
1447         struct bnxt *bp = eth_dev->data->dev_private;
1448         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1449         int len, rc;
1450         uint32_t hash_types;
1451
1452         rc = is_bnxt_in_error(bp);
1453         if (rc)
1454                 return rc;
1455
1456         /* RSS configuration is the same for all VNICs */
1457         if (vnic && vnic->rss_hash_key) {
1458                 if (rss_conf->rss_key) {
1459                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1460                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1461                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1462                 }
1463
1464                 hash_types = vnic->hash_type;
1465                 rss_conf->rss_hf = 0;
1466                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1467                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1468                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1469                 }
1470                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1471                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1472                         hash_types &=
1473                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1474                 }
1475                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1476                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1477                         hash_types &=
1478                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1479                 }
1480                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1481                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1482                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1483                 }
1484                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1485                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1486                         hash_types &=
1487                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1488                 }
1489                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1490                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1491                         hash_types &=
1492                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1493                 }
1494                 if (hash_types) {
1495                         PMD_DRV_LOG(ERR,
1496                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1497                                 vnic->hash_type);
1498                         return -ENOTSUP;
1499                 }
1500         } else {
1501                 rss_conf->rss_hf = 0;
1502         }
1503         return 0;
1504 }
1505
1506 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1507                                struct rte_eth_fc_conf *fc_conf)
1508 {
1509         struct bnxt *bp = dev->data->dev_private;
1510         struct rte_eth_link link_info;
1511         int rc;
1512
1513         rc = is_bnxt_in_error(bp);
1514         if (rc)
1515                 return rc;
1516
1517         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1518         if (rc)
1519                 return rc;
1520
1521         memset(fc_conf, 0, sizeof(*fc_conf));
1522         if (bp->link_info.auto_pause)
1523                 fc_conf->autoneg = 1;
1524         switch (bp->link_info.pause) {
1525         case 0:
1526                 fc_conf->mode = RTE_FC_NONE;
1527                 break;
1528         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1529                 fc_conf->mode = RTE_FC_TX_PAUSE;
1530                 break;
1531         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1532                 fc_conf->mode = RTE_FC_RX_PAUSE;
1533                 break;
1534         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1535                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1536                 fc_conf->mode = RTE_FC_FULL;
1537                 break;
1538         }
1539         return 0;
1540 }
1541
1542 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1543                                struct rte_eth_fc_conf *fc_conf)
1544 {
1545         struct bnxt *bp = dev->data->dev_private;
1546         int rc;
1547
1548         rc = is_bnxt_in_error(bp);
1549         if (rc)
1550                 return rc;
1551
1552         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1553                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1554                 return -ENOTSUP;
1555         }
1556
1557         switch (fc_conf->mode) {
1558         case RTE_FC_NONE:
1559                 bp->link_info.auto_pause = 0;
1560                 bp->link_info.force_pause = 0;
1561                 break;
1562         case RTE_FC_RX_PAUSE:
1563                 if (fc_conf->autoneg) {
1564                         bp->link_info.auto_pause =
1565                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1566                         bp->link_info.force_pause = 0;
1567                 } else {
1568                         bp->link_info.auto_pause = 0;
1569                         bp->link_info.force_pause =
1570                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1571                 }
1572                 break;
1573         case RTE_FC_TX_PAUSE:
1574                 if (fc_conf->autoneg) {
1575                         bp->link_info.auto_pause =
1576                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1577                         bp->link_info.force_pause = 0;
1578                 } else {
1579                         bp->link_info.auto_pause = 0;
1580                         bp->link_info.force_pause =
1581                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1582                 }
1583                 break;
1584         case RTE_FC_FULL:
1585                 if (fc_conf->autoneg) {
1586                         bp->link_info.auto_pause =
1587                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1588                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1589                         bp->link_info.force_pause = 0;
1590                 } else {
1591                         bp->link_info.auto_pause = 0;
1592                         bp->link_info.force_pause =
1593                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1594                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1595                 }
1596                 break;
1597         }
1598         return bnxt_set_hwrm_link_config(bp, true);
1599 }
1600
1601 /* Add UDP tunneling port */
1602 static int
1603 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1604                          struct rte_eth_udp_tunnel *udp_tunnel)
1605 {
1606         struct bnxt *bp = eth_dev->data->dev_private;
1607         uint16_t tunnel_type = 0;
1608         int rc = 0;
1609
1610         rc = is_bnxt_in_error(bp);
1611         if (rc)
1612                 return rc;
1613
1614         switch (udp_tunnel->prot_type) {
1615         case RTE_TUNNEL_TYPE_VXLAN:
1616                 if (bp->vxlan_port_cnt) {
1617                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1618                                 udp_tunnel->udp_port);
1619                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1620                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1621                                 return -ENOSPC;
1622                         }
1623                         bp->vxlan_port_cnt++;
1624                         return 0;
1625                 }
1626                 tunnel_type =
1627                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1628                 bp->vxlan_port_cnt++;
1629                 break;
1630         case RTE_TUNNEL_TYPE_GENEVE:
1631                 if (bp->geneve_port_cnt) {
1632                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1633                                 udp_tunnel->udp_port);
1634                         if (bp->geneve_port != udp_tunnel->udp_port) {
1635                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1636                                 return -ENOSPC;
1637                         }
1638                         bp->geneve_port_cnt++;
1639                         return 0;
1640                 }
1641                 tunnel_type =
1642                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1643                 bp->geneve_port_cnt++;
1644                 break;
1645         default:
1646                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1647                 return -ENOTSUP;
1648         }
1649         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1650                                              tunnel_type);
1651         return rc;
1652 }
1653
1654 static int
1655 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1656                          struct rte_eth_udp_tunnel *udp_tunnel)
1657 {
1658         struct bnxt *bp = eth_dev->data->dev_private;
1659         uint16_t tunnel_type = 0;
1660         uint16_t port = 0;
1661         int rc = 0;
1662
1663         rc = is_bnxt_in_error(bp);
1664         if (rc)
1665                 return rc;
1666
1667         switch (udp_tunnel->prot_type) {
1668         case RTE_TUNNEL_TYPE_VXLAN:
1669                 if (!bp->vxlan_port_cnt) {
1670                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1671                         return -EINVAL;
1672                 }
1673                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1674                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1675                                 udp_tunnel->udp_port, bp->vxlan_port);
1676                         return -EINVAL;
1677                 }
1678                 if (--bp->vxlan_port_cnt)
1679                         return 0;
1680
1681                 tunnel_type =
1682                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1683                 port = bp->vxlan_fw_dst_port_id;
1684                 break;
1685         case RTE_TUNNEL_TYPE_GENEVE:
1686                 if (!bp->geneve_port_cnt) {
1687                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1688                         return -EINVAL;
1689                 }
1690                 if (bp->geneve_port != udp_tunnel->udp_port) {
1691                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1692                                 udp_tunnel->udp_port, bp->geneve_port);
1693                         return -EINVAL;
1694                 }
1695                 if (--bp->geneve_port_cnt)
1696                         return 0;
1697
1698                 tunnel_type =
1699                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1700                 port = bp->geneve_fw_dst_port_id;
1701                 break;
1702         default:
1703                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1704                 return -ENOTSUP;
1705         }
1706
1707         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1708         if (!rc) {
1709                 if (tunnel_type ==
1710                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1711                         bp->vxlan_port = 0;
1712                 if (tunnel_type ==
1713                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1714                         bp->geneve_port = 0;
1715         }
1716         return rc;
1717 }
1718
1719 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1720 {
1721         struct bnxt_filter_info *filter;
1722         struct bnxt_vnic_info *vnic;
1723         int rc = 0;
1724         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1725
1726         /* if VLAN exists && VLAN matches vlan_id
1727          *      remove the MAC+VLAN filter
1728          *      add a new MAC only filter
1729          * else
1730          *      VLAN filter doesn't exist, just skip and continue
1731          */
1732         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1733         filter = STAILQ_FIRST(&vnic->filter);
1734         while (filter) {
1735                 /* Search for this matching MAC+VLAN filter */
1736                 if ((filter->enables & chk) &&
1737                     (filter->l2_ivlan == vlan_id &&
1738                      filter->l2_ivlan_mask != 0) &&
1739                     !memcmp(filter->l2_addr, bp->mac_addr,
1740                             RTE_ETHER_ADDR_LEN)) {
1741                         /* Delete the filter */
1742                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1743                         if (rc)
1744                                 return rc;
1745                         STAILQ_REMOVE(&vnic->filter, filter,
1746                                       bnxt_filter_info, next);
1747                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1748
1749                         PMD_DRV_LOG(INFO,
1750                                     "Del Vlan filter for %d\n",
1751                                     vlan_id);
1752                         return rc;
1753                 }
1754                 filter = STAILQ_NEXT(filter, next);
1755         }
1756         return -ENOENT;
1757 }
1758
1759 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1760 {
1761         struct bnxt_filter_info *filter;
1762         struct bnxt_vnic_info *vnic;
1763         int rc = 0;
1764         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1765                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1766         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1767
1768         /* Implementation notes on the use of VNIC in this command:
1769          *
1770          * By default, these filters belong to default vnic for the function.
1771          * Once these filters are set up, only destination VNIC can be modified.
1772          * If the destination VNIC is not specified in this command,
1773          * then the HWRM shall only create an l2 context id.
1774          */
1775
1776         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1777         filter = STAILQ_FIRST(&vnic->filter);
1778         /* Check if the VLAN has already been added */
1779         while (filter) {
1780                 if ((filter->enables & chk) &&
1781                     (filter->l2_ivlan == vlan_id &&
1782                      filter->l2_ivlan_mask == 0x0FFF) &&
1783                      !memcmp(filter->l2_addr, bp->mac_addr,
1784                              RTE_ETHER_ADDR_LEN))
1785                         return -EEXIST;
1786
1787                 filter = STAILQ_NEXT(filter, next);
1788         }
1789
1790         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1791          * command to create MAC+VLAN filter with the right flags, enables set.
1792          */
1793         filter = bnxt_alloc_filter(bp);
1794         if (!filter) {
1795                 PMD_DRV_LOG(ERR,
1796                             "MAC/VLAN filter alloc failed\n");
1797                 return -ENOMEM;
1798         }
1799         /* MAC + VLAN ID filter */
1800         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1801          * untagged packets are received
1802          *
1803          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1804          * packets and only the programmed vlan's packets are received
1805          */
1806         filter->l2_ivlan = vlan_id;
1807         filter->l2_ivlan_mask = 0x0FFF;
1808         filter->enables |= en;
1809         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1810
1811         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1812         if (rc) {
1813                 /* Free the newly allocated filter as we were
1814                  * not able to create the filter in hardware.
1815                  */
1816                 filter->fw_l2_filter_id = UINT64_MAX;
1817                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1818                 return rc;
1819         } else {
1820                 /* Add this new filter to the list */
1821                 if (vlan_id == 0) {
1822                         filter->dflt = true;
1823                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1824                 } else {
1825                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1826                 }
1827         }
1828
1829         PMD_DRV_LOG(INFO,
1830                     "Added Vlan filter for %d\n", vlan_id);
1831         return rc;
1832 }
1833
1834 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1835                 uint16_t vlan_id, int on)
1836 {
1837         struct bnxt *bp = eth_dev->data->dev_private;
1838         int rc;
1839
1840         rc = is_bnxt_in_error(bp);
1841         if (rc)
1842                 return rc;
1843
1844         /* These operations apply to ALL existing MAC/VLAN filters */
1845         if (on)
1846                 return bnxt_add_vlan_filter(bp, vlan_id);
1847         else
1848                 return bnxt_del_vlan_filter(bp, vlan_id);
1849 }
1850
1851 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1852                                     struct bnxt_vnic_info *vnic)
1853 {
1854         struct bnxt_filter_info *filter;
1855         int rc;
1856
1857         filter = STAILQ_FIRST(&vnic->filter);
1858         while (filter) {
1859                 if (filter->dflt &&
1860                     !memcmp(filter->l2_addr, bp->mac_addr,
1861                             RTE_ETHER_ADDR_LEN)) {
1862                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1863                         if (rc)
1864                                 return rc;
1865                         filter->dflt = false;
1866                         STAILQ_REMOVE(&vnic->filter, filter,
1867                                       bnxt_filter_info, next);
1868                         STAILQ_INSERT_TAIL(&bp->free_filter_list,
1869                                            filter, next);
1870                         filter->fw_l2_filter_id = -1;
1871                         break;
1872                 }
1873                 filter = STAILQ_NEXT(filter, next);
1874         }
1875         return 0;
1876 }
1877
1878 static int
1879 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1880 {
1881         struct bnxt *bp = dev->data->dev_private;
1882         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1883         struct bnxt_vnic_info *vnic;
1884         unsigned int i;
1885         int rc;
1886
1887         rc = is_bnxt_in_error(bp);
1888         if (rc)
1889                 return rc;
1890
1891         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1892         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1893                 /* Remove any VLAN filters programmed */
1894                 for (i = 0; i < 4095; i++)
1895                         bnxt_del_vlan_filter(bp, i);
1896
1897                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0);
1898                 if (rc)
1899                         return rc;
1900         } else {
1901                 /* Default filter will allow packets that match the
1902                  * dest mac. So, it has to be deleted, otherwise, we
1903                  * will endup receiving vlan packets for which the
1904                  * filter is not programmed, when hw-vlan-filter
1905                  * configuration is ON
1906                  */
1907                 bnxt_del_dflt_mac_filter(bp, vnic);
1908                 /* This filter will allow only untagged packets */
1909                 bnxt_add_vlan_filter(bp, 0);
1910         }
1911         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1912                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1913
1914         if (mask & ETH_VLAN_STRIP_MASK) {
1915                 /* Enable or disable VLAN stripping */
1916                 for (i = 0; i < bp->nr_vnics; i++) {
1917                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1918                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1919                                 vnic->vlan_strip = true;
1920                         else
1921                                 vnic->vlan_strip = false;
1922                         bnxt_hwrm_vnic_cfg(bp, vnic);
1923                 }
1924                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1925                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1926         }
1927
1928         if (mask & ETH_VLAN_EXTEND_MASK) {
1929                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1930                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1931                 else
1932                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1933         }
1934
1935         return 0;
1936 }
1937
1938 static int
1939 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1940                       uint16_t tpid)
1941 {
1942         struct bnxt *bp = dev->data->dev_private;
1943         int qinq = dev->data->dev_conf.rxmode.offloads &
1944                    DEV_RX_OFFLOAD_VLAN_EXTEND;
1945
1946         if (vlan_type != ETH_VLAN_TYPE_INNER &&
1947             vlan_type != ETH_VLAN_TYPE_OUTER) {
1948                 PMD_DRV_LOG(ERR,
1949                             "Unsupported vlan type.");
1950                 return -EINVAL;
1951         }
1952         if (!qinq) {
1953                 PMD_DRV_LOG(ERR,
1954                             "QinQ not enabled. Needs to be ON as we can "
1955                             "accelerate only outer vlan\n");
1956                 return -EINVAL;
1957         }
1958
1959         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1960                 switch (tpid) {
1961                 case RTE_ETHER_TYPE_QINQ:
1962                         bp->outer_tpid_bd =
1963                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1964                                 break;
1965                 case RTE_ETHER_TYPE_VLAN:
1966                         bp->outer_tpid_bd =
1967                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1968                                 break;
1969                 case 0x9100:
1970                         bp->outer_tpid_bd =
1971                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1972                                 break;
1973                 case 0x9200:
1974                         bp->outer_tpid_bd =
1975                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1976                                 break;
1977                 case 0x9300:
1978                         bp->outer_tpid_bd =
1979                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1980                                 break;
1981                 default:
1982                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1983                         return -EINVAL;
1984                 }
1985                 bp->outer_tpid_bd |= tpid;
1986                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1987         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1988                 PMD_DRV_LOG(ERR,
1989                             "Can accelerate only outer vlan in QinQ\n");
1990                 return -EINVAL;
1991         }
1992
1993         return 0;
1994 }
1995
1996 static int
1997 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1998                              struct rte_ether_addr *addr)
1999 {
2000         struct bnxt *bp = dev->data->dev_private;
2001         /* Default Filter is tied to VNIC 0 */
2002         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
2003         struct bnxt_filter_info *filter;
2004         int rc;
2005
2006         rc = is_bnxt_in_error(bp);
2007         if (rc)
2008                 return rc;
2009
2010         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2011                 return -EPERM;
2012
2013         if (rte_is_zero_ether_addr(addr))
2014                 return -EINVAL;
2015
2016         STAILQ_FOREACH(filter, &vnic->filter, next) {
2017                 /* Default Filter is at Index 0 */
2018                 if (filter->mac_index != 0)
2019                         continue;
2020
2021                 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
2022                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
2023                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
2024                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2025                 filter->enables |=
2026                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
2027                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
2028
2029                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2030                 if (rc) {
2031                         memcpy(filter->l2_addr, bp->mac_addr,
2032                                RTE_ETHER_ADDR_LEN);
2033                         return rc;
2034                 }
2035
2036                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2037                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2038                 return 0;
2039         }
2040
2041         return 0;
2042 }
2043
2044 static int
2045 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2046                           struct rte_ether_addr *mc_addr_set,
2047                           uint32_t nb_mc_addr)
2048 {
2049         struct bnxt *bp = eth_dev->data->dev_private;
2050         char *mc_addr_list = (char *)mc_addr_set;
2051         struct bnxt_vnic_info *vnic;
2052         uint32_t off = 0, i = 0;
2053         int rc;
2054
2055         rc = is_bnxt_in_error(bp);
2056         if (rc)
2057                 return rc;
2058
2059         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2060
2061         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2062                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2063                 goto allmulti;
2064         }
2065
2066         /* TODO Check for Duplicate mcast addresses */
2067         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2068         for (i = 0; i < nb_mc_addr; i++) {
2069                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2070                         RTE_ETHER_ADDR_LEN);
2071                 off += RTE_ETHER_ADDR_LEN;
2072         }
2073
2074         vnic->mc_addr_cnt = i;
2075         if (vnic->mc_addr_cnt)
2076                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2077         else
2078                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2079
2080 allmulti:
2081         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2082 }
2083
2084 static int
2085 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2086 {
2087         struct bnxt *bp = dev->data->dev_private;
2088         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2089         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2090         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2091         int ret;
2092
2093         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2094                         fw_major, fw_minor, fw_updt);
2095
2096         ret += 1; /* add the size of '\0' */
2097         if (fw_size < (uint32_t)ret)
2098                 return ret;
2099         else
2100                 return 0;
2101 }
2102
2103 static void
2104 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2105         struct rte_eth_rxq_info *qinfo)
2106 {
2107         struct bnxt_rx_queue *rxq;
2108
2109         rxq = dev->data->rx_queues[queue_id];
2110
2111         qinfo->mp = rxq->mb_pool;
2112         qinfo->scattered_rx = dev->data->scattered_rx;
2113         qinfo->nb_desc = rxq->nb_rx_desc;
2114
2115         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2116         qinfo->conf.rx_drop_en = 0;
2117         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2118 }
2119
2120 static void
2121 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2122         struct rte_eth_txq_info *qinfo)
2123 {
2124         struct bnxt_tx_queue *txq;
2125
2126         txq = dev->data->tx_queues[queue_id];
2127
2128         qinfo->nb_desc = txq->nb_tx_desc;
2129
2130         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2131         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2132         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2133
2134         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2135         qinfo->conf.tx_rs_thresh = 0;
2136         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2137 }
2138
2139 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2140 {
2141         struct bnxt *bp = eth_dev->data->dev_private;
2142         uint32_t new_pkt_size;
2143         uint32_t rc = 0;
2144         uint32_t i;
2145
2146         rc = is_bnxt_in_error(bp);
2147         if (rc)
2148                 return rc;
2149
2150         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2151                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2152
2153 #ifdef RTE_ARCH_X86
2154         /*
2155          * If vector-mode tx/rx is active, disallow any MTU change that would
2156          * require scattered receive support.
2157          */
2158         if (eth_dev->data->dev_started &&
2159             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2160              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2161             (new_pkt_size >
2162              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2163                 PMD_DRV_LOG(ERR,
2164                             "MTU change would require scattered rx support. ");
2165                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2166                 return -EINVAL;
2167         }
2168 #endif
2169
2170         if (new_mtu > RTE_ETHER_MTU) {
2171                 bp->flags |= BNXT_FLAG_JUMBO;
2172                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2173                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2174         } else {
2175                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2176                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2177                 bp->flags &= ~BNXT_FLAG_JUMBO;
2178         }
2179
2180         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2181
2182         for (i = 0; i < bp->nr_vnics; i++) {
2183                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2184                 uint16_t size = 0;
2185
2186                 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN +
2187                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2188                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2189                 if (rc)
2190                         break;
2191
2192                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2193                 size -= RTE_PKTMBUF_HEADROOM;
2194
2195                 if (size < new_mtu) {
2196                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2197                         if (rc)
2198                                 return rc;
2199                 }
2200         }
2201
2202         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2203
2204         return rc;
2205 }
2206
2207 static int
2208 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2209 {
2210         struct bnxt *bp = dev->data->dev_private;
2211         uint16_t vlan = bp->vlan;
2212         int rc;
2213
2214         rc = is_bnxt_in_error(bp);
2215         if (rc)
2216                 return rc;
2217
2218         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2219                 PMD_DRV_LOG(ERR,
2220                         "PVID cannot be modified for this function\n");
2221                 return -ENOTSUP;
2222         }
2223         bp->vlan = on ? pvid : 0;
2224
2225         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2226         if (rc)
2227                 bp->vlan = vlan;
2228         return rc;
2229 }
2230
2231 static int
2232 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2233 {
2234         struct bnxt *bp = dev->data->dev_private;
2235         int rc;
2236
2237         rc = is_bnxt_in_error(bp);
2238         if (rc)
2239                 return rc;
2240
2241         return bnxt_hwrm_port_led_cfg(bp, true);
2242 }
2243
2244 static int
2245 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2246 {
2247         struct bnxt *bp = dev->data->dev_private;
2248         int rc;
2249
2250         rc = is_bnxt_in_error(bp);
2251         if (rc)
2252                 return rc;
2253
2254         return bnxt_hwrm_port_led_cfg(bp, false);
2255 }
2256
2257 static uint32_t
2258 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2259 {
2260         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2261         uint32_t desc = 0, raw_cons = 0, cons;
2262         struct bnxt_cp_ring_info *cpr;
2263         struct bnxt_rx_queue *rxq;
2264         struct rx_pkt_cmpl *rxcmp;
2265         int rc;
2266
2267         rc = is_bnxt_in_error(bp);
2268         if (rc)
2269                 return rc;
2270
2271         rxq = dev->data->rx_queues[rx_queue_id];
2272         cpr = rxq->cp_ring;
2273         raw_cons = cpr->cp_raw_cons;
2274
2275         while (1) {
2276                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2277                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2278                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2279
2280                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2281                         break;
2282                 } else {
2283                         raw_cons++;
2284                         desc++;
2285                 }
2286         }
2287
2288         return desc;
2289 }
2290
2291 static int
2292 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2293 {
2294         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2295         struct bnxt_rx_ring_info *rxr;
2296         struct bnxt_cp_ring_info *cpr;
2297         struct bnxt_sw_rx_bd *rx_buf;
2298         struct rx_pkt_cmpl *rxcmp;
2299         uint32_t cons, cp_cons;
2300         int rc;
2301
2302         if (!rxq)
2303                 return -EINVAL;
2304
2305         rc = is_bnxt_in_error(rxq->bp);
2306         if (rc)
2307                 return rc;
2308
2309         cpr = rxq->cp_ring;
2310         rxr = rxq->rx_ring;
2311
2312         if (offset >= rxq->nb_rx_desc)
2313                 return -EINVAL;
2314
2315         cons = RING_CMP(cpr->cp_ring_struct, offset);
2316         cp_cons = cpr->cp_raw_cons;
2317         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2318
2319         if (cons > cp_cons) {
2320                 if (CMPL_VALID(rxcmp, cpr->valid))
2321                         return RTE_ETH_RX_DESC_DONE;
2322         } else {
2323                 if (CMPL_VALID(rxcmp, !cpr->valid))
2324                         return RTE_ETH_RX_DESC_DONE;
2325         }
2326         rx_buf = &rxr->rx_buf_ring[cons];
2327         if (rx_buf->mbuf == NULL)
2328                 return RTE_ETH_RX_DESC_UNAVAIL;
2329
2330
2331         return RTE_ETH_RX_DESC_AVAIL;
2332 }
2333
2334 static int
2335 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2336 {
2337         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2338         struct bnxt_tx_ring_info *txr;
2339         struct bnxt_cp_ring_info *cpr;
2340         struct bnxt_sw_tx_bd *tx_buf;
2341         struct tx_pkt_cmpl *txcmp;
2342         uint32_t cons, cp_cons;
2343         int rc;
2344
2345         if (!txq)
2346                 return -EINVAL;
2347
2348         rc = is_bnxt_in_error(txq->bp);
2349         if (rc)
2350                 return rc;
2351
2352         cpr = txq->cp_ring;
2353         txr = txq->tx_ring;
2354
2355         if (offset >= txq->nb_tx_desc)
2356                 return -EINVAL;
2357
2358         cons = RING_CMP(cpr->cp_ring_struct, offset);
2359         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2360         cp_cons = cpr->cp_raw_cons;
2361
2362         if (cons > cp_cons) {
2363                 if (CMPL_VALID(txcmp, cpr->valid))
2364                         return RTE_ETH_TX_DESC_UNAVAIL;
2365         } else {
2366                 if (CMPL_VALID(txcmp, !cpr->valid))
2367                         return RTE_ETH_TX_DESC_UNAVAIL;
2368         }
2369         tx_buf = &txr->tx_buf_ring[cons];
2370         if (tx_buf->mbuf == NULL)
2371                 return RTE_ETH_TX_DESC_DONE;
2372
2373         return RTE_ETH_TX_DESC_FULL;
2374 }
2375
2376 static struct bnxt_filter_info *
2377 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2378                                 struct rte_eth_ethertype_filter *efilter,
2379                                 struct bnxt_vnic_info *vnic0,
2380                                 struct bnxt_vnic_info *vnic,
2381                                 int *ret)
2382 {
2383         struct bnxt_filter_info *mfilter = NULL;
2384         int match = 0;
2385         *ret = 0;
2386
2387         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2388                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2389                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2390                         " ethertype filter.", efilter->ether_type);
2391                 *ret = -EINVAL;
2392                 goto exit;
2393         }
2394         if (efilter->queue >= bp->rx_nr_rings) {
2395                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2396                 *ret = -EINVAL;
2397                 goto exit;
2398         }
2399
2400         vnic0 = &bp->vnic_info[0];
2401         vnic = &bp->vnic_info[efilter->queue];
2402         if (vnic == NULL) {
2403                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2404                 *ret = -EINVAL;
2405                 goto exit;
2406         }
2407
2408         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2409                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2410                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2411                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2412                              mfilter->flags ==
2413                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2414                              mfilter->ethertype == efilter->ether_type)) {
2415                                 match = 1;
2416                                 break;
2417                         }
2418                 }
2419         } else {
2420                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2421                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2422                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2423                              mfilter->ethertype == efilter->ether_type &&
2424                              mfilter->flags ==
2425                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2426                                 match = 1;
2427                                 break;
2428                         }
2429         }
2430
2431         if (match)
2432                 *ret = -EEXIST;
2433
2434 exit:
2435         return mfilter;
2436 }
2437
2438 static int
2439 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2440                         enum rte_filter_op filter_op,
2441                         void *arg)
2442 {
2443         struct bnxt *bp = dev->data->dev_private;
2444         struct rte_eth_ethertype_filter *efilter =
2445                         (struct rte_eth_ethertype_filter *)arg;
2446         struct bnxt_filter_info *bfilter, *filter1;
2447         struct bnxt_vnic_info *vnic, *vnic0;
2448         int ret;
2449
2450         if (filter_op == RTE_ETH_FILTER_NOP)
2451                 return 0;
2452
2453         if (arg == NULL) {
2454                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2455                             filter_op);
2456                 return -EINVAL;
2457         }
2458
2459         vnic0 = &bp->vnic_info[0];
2460         vnic = &bp->vnic_info[efilter->queue];
2461
2462         switch (filter_op) {
2463         case RTE_ETH_FILTER_ADD:
2464                 bnxt_match_and_validate_ether_filter(bp, efilter,
2465                                                         vnic0, vnic, &ret);
2466                 if (ret < 0)
2467                         return ret;
2468
2469                 bfilter = bnxt_get_unused_filter(bp);
2470                 if (bfilter == NULL) {
2471                         PMD_DRV_LOG(ERR,
2472                                 "Not enough resources for a new filter.\n");
2473                         return -ENOMEM;
2474                 }
2475                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2476                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2477                        RTE_ETHER_ADDR_LEN);
2478                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2479                        RTE_ETHER_ADDR_LEN);
2480                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2481                 bfilter->ethertype = efilter->ether_type;
2482                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2483
2484                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2485                 if (filter1 == NULL) {
2486                         ret = -EINVAL;
2487                         goto cleanup;
2488                 }
2489                 bfilter->enables |=
2490                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2491                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2492
2493                 bfilter->dst_id = vnic->fw_vnic_id;
2494
2495                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2496                         bfilter->flags =
2497                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2498                 }
2499
2500                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2501                 if (ret)
2502                         goto cleanup;
2503                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2504                 break;
2505         case RTE_ETH_FILTER_DELETE:
2506                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2507                                                         vnic0, vnic, &ret);
2508                 if (ret == -EEXIST) {
2509                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2510
2511                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2512                                       next);
2513                         bnxt_free_filter(bp, filter1);
2514                 } else if (ret == 0) {
2515                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2516                 }
2517                 break;
2518         default:
2519                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2520                 ret = -EINVAL;
2521                 goto error;
2522         }
2523         return ret;
2524 cleanup:
2525         bnxt_free_filter(bp, bfilter);
2526 error:
2527         return ret;
2528 }
2529
2530 static inline int
2531 parse_ntuple_filter(struct bnxt *bp,
2532                     struct rte_eth_ntuple_filter *nfilter,
2533                     struct bnxt_filter_info *bfilter)
2534 {
2535         uint32_t en = 0;
2536
2537         if (nfilter->queue >= bp->rx_nr_rings) {
2538                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2539                 return -EINVAL;
2540         }
2541
2542         switch (nfilter->dst_port_mask) {
2543         case UINT16_MAX:
2544                 bfilter->dst_port_mask = -1;
2545                 bfilter->dst_port = nfilter->dst_port;
2546                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2547                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2548                 break;
2549         default:
2550                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2551                 return -EINVAL;
2552         }
2553
2554         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2555         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2556
2557         switch (nfilter->proto_mask) {
2558         case UINT8_MAX:
2559                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2560                         bfilter->ip_protocol = 17;
2561                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2562                         bfilter->ip_protocol = 6;
2563                 else
2564                         return -EINVAL;
2565                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2566                 break;
2567         default:
2568                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2569                 return -EINVAL;
2570         }
2571
2572         switch (nfilter->dst_ip_mask) {
2573         case UINT32_MAX:
2574                 bfilter->dst_ipaddr_mask[0] = -1;
2575                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2576                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2577                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2578                 break;
2579         default:
2580                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2581                 return -EINVAL;
2582         }
2583
2584         switch (nfilter->src_ip_mask) {
2585         case UINT32_MAX:
2586                 bfilter->src_ipaddr_mask[0] = -1;
2587                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2588                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2589                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2590                 break;
2591         default:
2592                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2593                 return -EINVAL;
2594         }
2595
2596         switch (nfilter->src_port_mask) {
2597         case UINT16_MAX:
2598                 bfilter->src_port_mask = -1;
2599                 bfilter->src_port = nfilter->src_port;
2600                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2601                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2602                 break;
2603         default:
2604                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2605                 return -EINVAL;
2606         }
2607
2608         //TODO Priority
2609         //nfilter->priority = (uint8_t)filter->priority;
2610
2611         bfilter->enables = en;
2612         return 0;
2613 }
2614
2615 static struct bnxt_filter_info*
2616 bnxt_match_ntuple_filter(struct bnxt *bp,
2617                          struct bnxt_filter_info *bfilter,
2618                          struct bnxt_vnic_info **mvnic)
2619 {
2620         struct bnxt_filter_info *mfilter = NULL;
2621         int i;
2622
2623         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2624                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2625                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2626                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2627                             bfilter->src_ipaddr_mask[0] ==
2628                             mfilter->src_ipaddr_mask[0] &&
2629                             bfilter->src_port == mfilter->src_port &&
2630                             bfilter->src_port_mask == mfilter->src_port_mask &&
2631                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2632                             bfilter->dst_ipaddr_mask[0] ==
2633                             mfilter->dst_ipaddr_mask[0] &&
2634                             bfilter->dst_port == mfilter->dst_port &&
2635                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2636                             bfilter->flags == mfilter->flags &&
2637                             bfilter->enables == mfilter->enables) {
2638                                 if (mvnic)
2639                                         *mvnic = vnic;
2640                                 return mfilter;
2641                         }
2642                 }
2643         }
2644         return NULL;
2645 }
2646
2647 static int
2648 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2649                        struct rte_eth_ntuple_filter *nfilter,
2650                        enum rte_filter_op filter_op)
2651 {
2652         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2653         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2654         int ret;
2655
2656         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2657                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2658                 return -EINVAL;
2659         }
2660
2661         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2662                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2663                 return -EINVAL;
2664         }
2665
2666         bfilter = bnxt_get_unused_filter(bp);
2667         if (bfilter == NULL) {
2668                 PMD_DRV_LOG(ERR,
2669                         "Not enough resources for a new filter.\n");
2670                 return -ENOMEM;
2671         }
2672         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2673         if (ret < 0)
2674                 goto free_filter;
2675
2676         vnic = &bp->vnic_info[nfilter->queue];
2677         vnic0 = &bp->vnic_info[0];
2678         filter1 = STAILQ_FIRST(&vnic0->filter);
2679         if (filter1 == NULL) {
2680                 ret = -EINVAL;
2681                 goto free_filter;
2682         }
2683
2684         bfilter->dst_id = vnic->fw_vnic_id;
2685         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2686         bfilter->enables |=
2687                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2688         bfilter->ethertype = 0x800;
2689         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2690
2691         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2692
2693         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2694             bfilter->dst_id == mfilter->dst_id) {
2695                 PMD_DRV_LOG(ERR, "filter exists.\n");
2696                 ret = -EEXIST;
2697                 goto free_filter;
2698         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2699                    bfilter->dst_id != mfilter->dst_id) {
2700                 mfilter->dst_id = vnic->fw_vnic_id;
2701                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2702                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2703                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2704                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2705                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2706                 goto free_filter;
2707         }
2708         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2709                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2710                 ret = -ENOENT;
2711                 goto free_filter;
2712         }
2713
2714         if (filter_op == RTE_ETH_FILTER_ADD) {
2715                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2716                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2717                 if (ret)
2718                         goto free_filter;
2719                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2720         } else {
2721                 if (mfilter == NULL) {
2722                         /* This should not happen. But for Coverity! */
2723                         ret = -ENOENT;
2724                         goto free_filter;
2725                 }
2726                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2727
2728                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2729                 bnxt_free_filter(bp, mfilter);
2730                 mfilter->fw_l2_filter_id = -1;
2731                 bnxt_free_filter(bp, bfilter);
2732                 bfilter->fw_l2_filter_id = -1;
2733         }
2734
2735         return 0;
2736 free_filter:
2737         bfilter->fw_l2_filter_id = -1;
2738         bnxt_free_filter(bp, bfilter);
2739         return ret;
2740 }
2741
2742 static int
2743 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2744                         enum rte_filter_op filter_op,
2745                         void *arg)
2746 {
2747         struct bnxt *bp = dev->data->dev_private;
2748         int ret;
2749
2750         if (filter_op == RTE_ETH_FILTER_NOP)
2751                 return 0;
2752
2753         if (arg == NULL) {
2754                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2755                             filter_op);
2756                 return -EINVAL;
2757         }
2758
2759         switch (filter_op) {
2760         case RTE_ETH_FILTER_ADD:
2761                 ret = bnxt_cfg_ntuple_filter(bp,
2762                         (struct rte_eth_ntuple_filter *)arg,
2763                         filter_op);
2764                 break;
2765         case RTE_ETH_FILTER_DELETE:
2766                 ret = bnxt_cfg_ntuple_filter(bp,
2767                         (struct rte_eth_ntuple_filter *)arg,
2768                         filter_op);
2769                 break;
2770         default:
2771                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2772                 ret = -EINVAL;
2773                 break;
2774         }
2775         return ret;
2776 }
2777
2778 static int
2779 bnxt_parse_fdir_filter(struct bnxt *bp,
2780                        struct rte_eth_fdir_filter *fdir,
2781                        struct bnxt_filter_info *filter)
2782 {
2783         enum rte_fdir_mode fdir_mode =
2784                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2785         struct bnxt_vnic_info *vnic0, *vnic;
2786         struct bnxt_filter_info *filter1;
2787         uint32_t en = 0;
2788         int i;
2789
2790         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2791                 return -EINVAL;
2792
2793         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2794         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2795
2796         switch (fdir->input.flow_type) {
2797         case RTE_ETH_FLOW_IPV4:
2798         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2799                 /* FALLTHROUGH */
2800                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2801                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2802                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2803                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2804                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2805                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2806                 filter->ip_addr_type =
2807                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2808                 filter->src_ipaddr_mask[0] = 0xffffffff;
2809                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2810                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2811                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2812                 filter->ethertype = 0x800;
2813                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2814                 break;
2815         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2816                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2817                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2818                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2819                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2820                 filter->dst_port_mask = 0xffff;
2821                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2822                 filter->src_port_mask = 0xffff;
2823                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2824                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2825                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2826                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2827                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2828                 filter->ip_protocol = 6;
2829                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2830                 filter->ip_addr_type =
2831                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2832                 filter->src_ipaddr_mask[0] = 0xffffffff;
2833                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2834                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2835                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2836                 filter->ethertype = 0x800;
2837                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2838                 break;
2839         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2840                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2841                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2842                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2843                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2844                 filter->dst_port_mask = 0xffff;
2845                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2846                 filter->src_port_mask = 0xffff;
2847                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2848                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2849                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2850                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2851                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2852                 filter->ip_protocol = 17;
2853                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2854                 filter->ip_addr_type =
2855                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2856                 filter->src_ipaddr_mask[0] = 0xffffffff;
2857                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2858                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2859                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2860                 filter->ethertype = 0x800;
2861                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2862                 break;
2863         case RTE_ETH_FLOW_IPV6:
2864         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2865                 /* FALLTHROUGH */
2866                 filter->ip_addr_type =
2867                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2868                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2869                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2870                 rte_memcpy(filter->src_ipaddr,
2871                            fdir->input.flow.ipv6_flow.src_ip, 16);
2872                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2873                 rte_memcpy(filter->dst_ipaddr,
2874                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2875                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2876                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2877                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2878                 memset(filter->src_ipaddr_mask, 0xff, 16);
2879                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2880                 filter->ethertype = 0x86dd;
2881                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2882                 break;
2883         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2884                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2885                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2886                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2887                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2888                 filter->dst_port_mask = 0xffff;
2889                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2890                 filter->src_port_mask = 0xffff;
2891                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2892                 filter->ip_addr_type =
2893                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2894                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2895                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2896                 rte_memcpy(filter->src_ipaddr,
2897                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2898                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2899                 rte_memcpy(filter->dst_ipaddr,
2900                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2901                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2902                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2903                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2904                 memset(filter->src_ipaddr_mask, 0xff, 16);
2905                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2906                 filter->ethertype = 0x86dd;
2907                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2908                 break;
2909         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2910                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2911                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2912                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2913                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2914                 filter->dst_port_mask = 0xffff;
2915                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2916                 filter->src_port_mask = 0xffff;
2917                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2918                 filter->ip_addr_type =
2919                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2920                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2921                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2922                 rte_memcpy(filter->src_ipaddr,
2923                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2924                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2925                 rte_memcpy(filter->dst_ipaddr,
2926                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2927                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2928                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2929                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2930                 memset(filter->src_ipaddr_mask, 0xff, 16);
2931                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2932                 filter->ethertype = 0x86dd;
2933                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2934                 break;
2935         case RTE_ETH_FLOW_L2_PAYLOAD:
2936                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2937                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2938                 break;
2939         case RTE_ETH_FLOW_VXLAN:
2940                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2941                         return -EINVAL;
2942                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2943                 filter->tunnel_type =
2944                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2945                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2946                 break;
2947         case RTE_ETH_FLOW_NVGRE:
2948                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2949                         return -EINVAL;
2950                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2951                 filter->tunnel_type =
2952                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2953                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2954                 break;
2955         case RTE_ETH_FLOW_UNKNOWN:
2956         case RTE_ETH_FLOW_RAW:
2957         case RTE_ETH_FLOW_FRAG_IPV4:
2958         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2959         case RTE_ETH_FLOW_FRAG_IPV6:
2960         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2961         case RTE_ETH_FLOW_IPV6_EX:
2962         case RTE_ETH_FLOW_IPV6_TCP_EX:
2963         case RTE_ETH_FLOW_IPV6_UDP_EX:
2964         case RTE_ETH_FLOW_GENEVE:
2965                 /* FALLTHROUGH */
2966         default:
2967                 return -EINVAL;
2968         }
2969
2970         vnic0 = &bp->vnic_info[0];
2971         vnic = &bp->vnic_info[fdir->action.rx_queue];
2972         if (vnic == NULL) {
2973                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2974                 return -EINVAL;
2975         }
2976
2977
2978         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2979                 rte_memcpy(filter->dst_macaddr,
2980                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2981                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2982         }
2983
2984         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2985                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2986                 filter1 = STAILQ_FIRST(&vnic0->filter);
2987                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2988         } else {
2989                 filter->dst_id = vnic->fw_vnic_id;
2990                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2991                         if (filter->dst_macaddr[i] == 0x00)
2992                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2993                         else
2994                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2995         }
2996
2997         if (filter1 == NULL)
2998                 return -EINVAL;
2999
3000         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3001         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3002
3003         filter->enables = en;
3004
3005         return 0;
3006 }
3007
3008 static struct bnxt_filter_info *
3009 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3010                 struct bnxt_vnic_info **mvnic)
3011 {
3012         struct bnxt_filter_info *mf = NULL;
3013         int i;
3014
3015         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3016                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3017
3018                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3019                         if (mf->filter_type == nf->filter_type &&
3020                             mf->flags == nf->flags &&
3021                             mf->src_port == nf->src_port &&
3022                             mf->src_port_mask == nf->src_port_mask &&
3023                             mf->dst_port == nf->dst_port &&
3024                             mf->dst_port_mask == nf->dst_port_mask &&
3025                             mf->ip_protocol == nf->ip_protocol &&
3026                             mf->ip_addr_type == nf->ip_addr_type &&
3027                             mf->ethertype == nf->ethertype &&
3028                             mf->vni == nf->vni &&
3029                             mf->tunnel_type == nf->tunnel_type &&
3030                             mf->l2_ovlan == nf->l2_ovlan &&
3031                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3032                             mf->l2_ivlan == nf->l2_ivlan &&
3033                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3034                             !memcmp(mf->l2_addr, nf->l2_addr,
3035                                     RTE_ETHER_ADDR_LEN) &&
3036                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3037                                     RTE_ETHER_ADDR_LEN) &&
3038                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3039                                     RTE_ETHER_ADDR_LEN) &&
3040                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3041                                     RTE_ETHER_ADDR_LEN) &&
3042                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3043                                     sizeof(nf->src_ipaddr)) &&
3044                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3045                                     sizeof(nf->src_ipaddr_mask)) &&
3046                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3047                                     sizeof(nf->dst_ipaddr)) &&
3048                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3049                                     sizeof(nf->dst_ipaddr_mask))) {
3050                                 if (mvnic)
3051                                         *mvnic = vnic;
3052                                 return mf;
3053                         }
3054                 }
3055         }
3056         return NULL;
3057 }
3058
3059 static int
3060 bnxt_fdir_filter(struct rte_eth_dev *dev,
3061                  enum rte_filter_op filter_op,
3062                  void *arg)
3063 {
3064         struct bnxt *bp = dev->data->dev_private;
3065         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3066         struct bnxt_filter_info *filter, *match;
3067         struct bnxt_vnic_info *vnic, *mvnic;
3068         int ret = 0, i;
3069
3070         if (filter_op == RTE_ETH_FILTER_NOP)
3071                 return 0;
3072
3073         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3074                 return -EINVAL;
3075
3076         switch (filter_op) {
3077         case RTE_ETH_FILTER_ADD:
3078         case RTE_ETH_FILTER_DELETE:
3079                 /* FALLTHROUGH */
3080                 filter = bnxt_get_unused_filter(bp);
3081                 if (filter == NULL) {
3082                         PMD_DRV_LOG(ERR,
3083                                 "Not enough resources for a new flow.\n");
3084                         return -ENOMEM;
3085                 }
3086
3087                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3088                 if (ret != 0)
3089                         goto free_filter;
3090                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3091
3092                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3093                         vnic = &bp->vnic_info[0];
3094                 else
3095                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3096
3097                 match = bnxt_match_fdir(bp, filter, &mvnic);
3098                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3099                         if (match->dst_id == vnic->fw_vnic_id) {
3100                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3101                                 ret = -EEXIST;
3102                                 goto free_filter;
3103                         } else {
3104                                 match->dst_id = vnic->fw_vnic_id;
3105                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3106                                                                   match->dst_id,
3107                                                                   match);
3108                                 STAILQ_REMOVE(&mvnic->filter, match,
3109                                               bnxt_filter_info, next);
3110                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3111                                 PMD_DRV_LOG(ERR,
3112                                         "Filter with matching pattern exist\n");
3113                                 PMD_DRV_LOG(ERR,
3114                                         "Updated it to new destination q\n");
3115                                 goto free_filter;
3116                         }
3117                 }
3118                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3119                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3120                         ret = -ENOENT;
3121                         goto free_filter;
3122                 }
3123
3124                 if (filter_op == RTE_ETH_FILTER_ADD) {
3125                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3126                                                           filter->dst_id,
3127                                                           filter);
3128                         if (ret)
3129                                 goto free_filter;
3130                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3131                 } else {
3132                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3133                         STAILQ_REMOVE(&vnic->filter, match,
3134                                       bnxt_filter_info, next);
3135                         bnxt_free_filter(bp, match);
3136                         filter->fw_l2_filter_id = -1;
3137                         bnxt_free_filter(bp, filter);
3138                 }
3139                 break;
3140         case RTE_ETH_FILTER_FLUSH:
3141                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3142                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3143
3144                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3145                                 if (filter->filter_type ==
3146                                     HWRM_CFA_NTUPLE_FILTER) {
3147                                         ret =
3148                                         bnxt_hwrm_clear_ntuple_filter(bp,
3149                                                                       filter);
3150                                         STAILQ_REMOVE(&vnic->filter, filter,
3151                                                       bnxt_filter_info, next);
3152                                 }
3153                         }
3154                 }
3155                 return ret;
3156         case RTE_ETH_FILTER_UPDATE:
3157         case RTE_ETH_FILTER_STATS:
3158         case RTE_ETH_FILTER_INFO:
3159                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3160                 break;
3161         default:
3162                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3163                 ret = -EINVAL;
3164                 break;
3165         }
3166         return ret;
3167
3168 free_filter:
3169         filter->fw_l2_filter_id = -1;
3170         bnxt_free_filter(bp, filter);
3171         return ret;
3172 }
3173
3174 static int
3175 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3176                     enum rte_filter_type filter_type,
3177                     enum rte_filter_op filter_op, void *arg)
3178 {
3179         int ret = 0;
3180
3181         ret = is_bnxt_in_error(dev->data->dev_private);
3182         if (ret)
3183                 return ret;
3184
3185         switch (filter_type) {
3186         case RTE_ETH_FILTER_TUNNEL:
3187                 PMD_DRV_LOG(ERR,
3188                         "filter type: %d: To be implemented\n", filter_type);
3189                 break;
3190         case RTE_ETH_FILTER_FDIR:
3191                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3192                 break;
3193         case RTE_ETH_FILTER_NTUPLE:
3194                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3195                 break;
3196         case RTE_ETH_FILTER_ETHERTYPE:
3197                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3198                 break;
3199         case RTE_ETH_FILTER_GENERIC:
3200                 if (filter_op != RTE_ETH_FILTER_GET)
3201                         return -EINVAL;
3202                 *(const void **)arg = &bnxt_flow_ops;
3203                 break;
3204         default:
3205                 PMD_DRV_LOG(ERR,
3206                         "Filter type (%d) not supported", filter_type);
3207                 ret = -EINVAL;
3208                 break;
3209         }
3210         return ret;
3211 }
3212
3213 static const uint32_t *
3214 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3215 {
3216         static const uint32_t ptypes[] = {
3217                 RTE_PTYPE_L2_ETHER_VLAN,
3218                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3219                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3220                 RTE_PTYPE_L4_ICMP,
3221                 RTE_PTYPE_L4_TCP,
3222                 RTE_PTYPE_L4_UDP,
3223                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3224                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3225                 RTE_PTYPE_INNER_L4_ICMP,
3226                 RTE_PTYPE_INNER_L4_TCP,
3227                 RTE_PTYPE_INNER_L4_UDP,
3228                 RTE_PTYPE_UNKNOWN
3229         };
3230
3231         if (!dev->rx_pkt_burst)
3232                 return NULL;
3233
3234         return ptypes;
3235 }
3236
3237 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3238                          int reg_win)
3239 {
3240         uint32_t reg_base = *reg_arr & 0xfffff000;
3241         uint32_t win_off;
3242         int i;
3243
3244         for (i = 0; i < count; i++) {
3245                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3246                         return -ERANGE;
3247         }
3248         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3249         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3250         return 0;
3251 }
3252
3253 static int bnxt_map_ptp_regs(struct bnxt *bp)
3254 {
3255         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3256         uint32_t *reg_arr;
3257         int rc, i;
3258
3259         reg_arr = ptp->rx_regs;
3260         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3261         if (rc)
3262                 return rc;
3263
3264         reg_arr = ptp->tx_regs;
3265         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3266         if (rc)
3267                 return rc;
3268
3269         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3270                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3271
3272         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3273                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3274
3275         return 0;
3276 }
3277
3278 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3279 {
3280         rte_write32(0, (uint8_t *)bp->bar0 +
3281                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3282         rte_write32(0, (uint8_t *)bp->bar0 +
3283                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3284 }
3285
3286 static uint64_t bnxt_cc_read(struct bnxt *bp)
3287 {
3288         uint64_t ns;
3289
3290         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3291                               BNXT_GRCPF_REG_SYNC_TIME));
3292         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3293                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3294         return ns;
3295 }
3296
3297 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3298 {
3299         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3300         uint32_t fifo;
3301
3302         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3303                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3304         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3305                 return -EAGAIN;
3306
3307         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3308                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3309         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3310                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3311         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3312                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3313
3314         return 0;
3315 }
3316
3317 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3318 {
3319         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3320         struct bnxt_pf_info *pf = &bp->pf;
3321         uint16_t port_id;
3322         uint32_t fifo;
3323
3324         if (!ptp)
3325                 return -ENODEV;
3326
3327         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3328                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3329         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3330                 return -EAGAIN;
3331
3332         port_id = pf->port_id;
3333         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3334                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3335
3336         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3337                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3338         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3339 /*              bnxt_clr_rx_ts(bp);       TBD  */
3340                 return -EBUSY;
3341         }
3342
3343         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3344                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3345         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3346                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3347
3348         return 0;
3349 }
3350
3351 static int
3352 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3353 {
3354         uint64_t ns;
3355         struct bnxt *bp = dev->data->dev_private;
3356         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3357
3358         if (!ptp)
3359                 return 0;
3360
3361         ns = rte_timespec_to_ns(ts);
3362         /* Set the timecounters to a new value. */
3363         ptp->tc.nsec = ns;
3364
3365         return 0;
3366 }
3367
3368 static int
3369 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3370 {
3371         struct bnxt *bp = dev->data->dev_private;
3372         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3373         uint64_t ns, systime_cycles = 0;
3374         int rc = 0;
3375
3376         if (!ptp)
3377                 return 0;
3378
3379         if (BNXT_CHIP_THOR(bp))
3380                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3381                                              &systime_cycles);
3382         else
3383                 systime_cycles = bnxt_cc_read(bp);
3384
3385         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3386         *ts = rte_ns_to_timespec(ns);
3387
3388         return rc;
3389 }
3390 static int
3391 bnxt_timesync_enable(struct rte_eth_dev *dev)
3392 {
3393         struct bnxt *bp = dev->data->dev_private;
3394         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3395         uint32_t shift = 0;
3396         int rc;
3397
3398         if (!ptp)
3399                 return 0;
3400
3401         ptp->rx_filter = 1;
3402         ptp->tx_tstamp_en = 1;
3403         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3404
3405         rc = bnxt_hwrm_ptp_cfg(bp);
3406         if (rc)
3407                 return rc;
3408
3409         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3410         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3411         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3412
3413         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3414         ptp->tc.cc_shift = shift;
3415         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3416
3417         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3418         ptp->rx_tstamp_tc.cc_shift = shift;
3419         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3420
3421         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3422         ptp->tx_tstamp_tc.cc_shift = shift;
3423         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3424
3425         if (!BNXT_CHIP_THOR(bp))
3426                 bnxt_map_ptp_regs(bp);
3427
3428         return 0;
3429 }
3430
3431 static int
3432 bnxt_timesync_disable(struct rte_eth_dev *dev)
3433 {
3434         struct bnxt *bp = dev->data->dev_private;
3435         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3436
3437         if (!ptp)
3438                 return 0;
3439
3440         ptp->rx_filter = 0;
3441         ptp->tx_tstamp_en = 0;
3442         ptp->rxctl = 0;
3443
3444         bnxt_hwrm_ptp_cfg(bp);
3445
3446         if (!BNXT_CHIP_THOR(bp))
3447                 bnxt_unmap_ptp_regs(bp);
3448
3449         return 0;
3450 }
3451
3452 static int
3453 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3454                                  struct timespec *timestamp,
3455                                  uint32_t flags __rte_unused)
3456 {
3457         struct bnxt *bp = dev->data->dev_private;
3458         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3459         uint64_t rx_tstamp_cycles = 0;
3460         uint64_t ns;
3461
3462         if (!ptp)
3463                 return 0;
3464
3465         if (BNXT_CHIP_THOR(bp))
3466                 rx_tstamp_cycles = ptp->rx_timestamp;
3467         else
3468                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3469
3470         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3471         *timestamp = rte_ns_to_timespec(ns);
3472         return  0;
3473 }
3474
3475 static int
3476 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3477                                  struct timespec *timestamp)
3478 {
3479         struct bnxt *bp = dev->data->dev_private;
3480         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3481         uint64_t tx_tstamp_cycles = 0;
3482         uint64_t ns;
3483         int rc = 0;
3484
3485         if (!ptp)
3486                 return 0;
3487
3488         if (BNXT_CHIP_THOR(bp))
3489                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3490                                              &tx_tstamp_cycles);
3491         else
3492                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3493
3494         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3495         *timestamp = rte_ns_to_timespec(ns);
3496
3497         return rc;
3498 }
3499
3500 static int
3501 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3502 {
3503         struct bnxt *bp = dev->data->dev_private;
3504         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3505
3506         if (!ptp)
3507                 return 0;
3508
3509         ptp->tc.nsec += delta;
3510
3511         return 0;
3512 }
3513
3514 static int
3515 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3516 {
3517         struct bnxt *bp = dev->data->dev_private;
3518         int rc;
3519         uint32_t dir_entries;
3520         uint32_t entry_length;
3521
3522         rc = is_bnxt_in_error(bp);
3523         if (rc)
3524                 return rc;
3525
3526         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3527                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3528                 bp->pdev->addr.devid, bp->pdev->addr.function);
3529
3530         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3531         if (rc != 0)
3532                 return rc;
3533
3534         return dir_entries * entry_length;
3535 }
3536
3537 static int
3538 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3539                 struct rte_dev_eeprom_info *in_eeprom)
3540 {
3541         struct bnxt *bp = dev->data->dev_private;
3542         uint32_t index;
3543         uint32_t offset;
3544         int rc;
3545
3546         rc = is_bnxt_in_error(bp);
3547         if (rc)
3548                 return rc;
3549
3550         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3551                 "len = %d\n", bp->pdev->addr.domain,
3552                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3553                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3554
3555         if (in_eeprom->offset == 0) /* special offset value to get directory */
3556                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3557                                                 in_eeprom->data);
3558
3559         index = in_eeprom->offset >> 24;
3560         offset = in_eeprom->offset & 0xffffff;
3561
3562         if (index != 0)
3563                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3564                                            in_eeprom->length, in_eeprom->data);
3565
3566         return 0;
3567 }
3568
3569 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3570 {
3571         switch (dir_type) {
3572         case BNX_DIR_TYPE_CHIMP_PATCH:
3573         case BNX_DIR_TYPE_BOOTCODE:
3574         case BNX_DIR_TYPE_BOOTCODE_2:
3575         case BNX_DIR_TYPE_APE_FW:
3576         case BNX_DIR_TYPE_APE_PATCH:
3577         case BNX_DIR_TYPE_KONG_FW:
3578         case BNX_DIR_TYPE_KONG_PATCH:
3579         case BNX_DIR_TYPE_BONO_FW:
3580         case BNX_DIR_TYPE_BONO_PATCH:
3581                 /* FALLTHROUGH */
3582                 return true;
3583         }
3584
3585         return false;
3586 }
3587
3588 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3589 {
3590         switch (dir_type) {
3591         case BNX_DIR_TYPE_AVS:
3592         case BNX_DIR_TYPE_EXP_ROM_MBA:
3593         case BNX_DIR_TYPE_PCIE:
3594         case BNX_DIR_TYPE_TSCF_UCODE:
3595         case BNX_DIR_TYPE_EXT_PHY:
3596         case BNX_DIR_TYPE_CCM:
3597         case BNX_DIR_TYPE_ISCSI_BOOT:
3598         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3599         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3600                 /* FALLTHROUGH */
3601                 return true;
3602         }
3603
3604         return false;
3605 }
3606
3607 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3608 {
3609         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3610                 bnxt_dir_type_is_other_exec_format(dir_type);
3611 }
3612
3613 static int
3614 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3615                 struct rte_dev_eeprom_info *in_eeprom)
3616 {
3617         struct bnxt *bp = dev->data->dev_private;
3618         uint8_t index, dir_op;
3619         uint16_t type, ext, ordinal, attr;
3620         int rc;
3621
3622         rc = is_bnxt_in_error(bp);
3623         if (rc)
3624                 return rc;
3625
3626         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3627                 "len = %d\n", bp->pdev->addr.domain,
3628                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3629                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3630
3631         if (!BNXT_PF(bp)) {
3632                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3633                 return -EINVAL;
3634         }
3635
3636         type = in_eeprom->magic >> 16;
3637
3638         if (type == 0xffff) { /* special value for directory operations */
3639                 index = in_eeprom->magic & 0xff;
3640                 dir_op = in_eeprom->magic >> 8;
3641                 if (index == 0)
3642                         return -EINVAL;
3643                 switch (dir_op) {
3644                 case 0x0e: /* erase */
3645                         if (in_eeprom->offset != ~in_eeprom->magic)
3646                                 return -EINVAL;
3647                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3648                 default:
3649                         return -EINVAL;
3650                 }
3651         }
3652
3653         /* Create or re-write an NVM item: */
3654         if (bnxt_dir_type_is_executable(type) == true)
3655                 return -EOPNOTSUPP;
3656         ext = in_eeprom->magic & 0xffff;
3657         ordinal = in_eeprom->offset >> 16;
3658         attr = in_eeprom->offset & 0xffff;
3659
3660         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3661                                      in_eeprom->data, in_eeprom->length);
3662 }
3663
3664 /*
3665  * Initialization
3666  */
3667
3668 static const struct eth_dev_ops bnxt_dev_ops = {
3669         .dev_infos_get = bnxt_dev_info_get_op,
3670         .dev_close = bnxt_dev_close_op,
3671         .dev_configure = bnxt_dev_configure_op,
3672         .dev_start = bnxt_dev_start_op,
3673         .dev_stop = bnxt_dev_stop_op,
3674         .dev_set_link_up = bnxt_dev_set_link_up_op,
3675         .dev_set_link_down = bnxt_dev_set_link_down_op,
3676         .stats_get = bnxt_stats_get_op,
3677         .stats_reset = bnxt_stats_reset_op,
3678         .rx_queue_setup = bnxt_rx_queue_setup_op,
3679         .rx_queue_release = bnxt_rx_queue_release_op,
3680         .tx_queue_setup = bnxt_tx_queue_setup_op,
3681         .tx_queue_release = bnxt_tx_queue_release_op,
3682         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3683         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3684         .reta_update = bnxt_reta_update_op,
3685         .reta_query = bnxt_reta_query_op,
3686         .rss_hash_update = bnxt_rss_hash_update_op,
3687         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3688         .link_update = bnxt_link_update_op,
3689         .promiscuous_enable = bnxt_promiscuous_enable_op,
3690         .promiscuous_disable = bnxt_promiscuous_disable_op,
3691         .allmulticast_enable = bnxt_allmulticast_enable_op,
3692         .allmulticast_disable = bnxt_allmulticast_disable_op,
3693         .mac_addr_add = bnxt_mac_addr_add_op,
3694         .mac_addr_remove = bnxt_mac_addr_remove_op,
3695         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3696         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3697         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3698         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3699         .vlan_filter_set = bnxt_vlan_filter_set_op,
3700         .vlan_offload_set = bnxt_vlan_offload_set_op,
3701         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3702         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3703         .mtu_set = bnxt_mtu_set_op,
3704         .mac_addr_set = bnxt_set_default_mac_addr_op,
3705         .xstats_get = bnxt_dev_xstats_get_op,
3706         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3707         .xstats_reset = bnxt_dev_xstats_reset_op,
3708         .fw_version_get = bnxt_fw_version_get,
3709         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3710         .rxq_info_get = bnxt_rxq_info_get_op,
3711         .txq_info_get = bnxt_txq_info_get_op,
3712         .dev_led_on = bnxt_dev_led_on_op,
3713         .dev_led_off = bnxt_dev_led_off_op,
3714         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3715         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3716         .rx_queue_count = bnxt_rx_queue_count_op,
3717         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3718         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3719         .rx_queue_start = bnxt_rx_queue_start,
3720         .rx_queue_stop = bnxt_rx_queue_stop,
3721         .tx_queue_start = bnxt_tx_queue_start,
3722         .tx_queue_stop = bnxt_tx_queue_stop,
3723         .filter_ctrl = bnxt_filter_ctrl_op,
3724         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3725         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3726         .get_eeprom           = bnxt_get_eeprom_op,
3727         .set_eeprom           = bnxt_set_eeprom_op,
3728         .timesync_enable      = bnxt_timesync_enable,
3729         .timesync_disable     = bnxt_timesync_disable,
3730         .timesync_read_time   = bnxt_timesync_read_time,
3731         .timesync_write_time   = bnxt_timesync_write_time,
3732         .timesync_adjust_time = bnxt_timesync_adjust_time,
3733         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3734         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3735 };
3736
3737 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3738 {
3739         uint32_t offset;
3740
3741         /* Only pre-map the reset GRC registers using window 3 */
3742         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3743                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3744
3745         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3746
3747         return offset;
3748 }
3749
3750 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3751 {
3752         struct bnxt_error_recovery_info *info = bp->recovery_info;
3753         uint32_t reg_base = 0xffffffff;
3754         int i;
3755
3756         /* Only pre-map the monitoring GRC registers using window 2 */
3757         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3758                 uint32_t reg = info->status_regs[i];
3759
3760                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3761                         continue;
3762
3763                 if (reg_base == 0xffffffff)
3764                         reg_base = reg & 0xfffff000;
3765                 if ((reg & 0xfffff000) != reg_base)
3766                         return -ERANGE;
3767
3768                 /* Use mask 0xffc as the Lower 2 bits indicates
3769                  * address space location
3770                  */
3771                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3772                                                 (reg & 0xffc);
3773         }
3774
3775         if (reg_base == 0xffffffff)
3776                 return 0;
3777
3778         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3779                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3780
3781         return 0;
3782 }
3783
3784 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3785 {
3786         struct bnxt_error_recovery_info *info = bp->recovery_info;
3787         uint32_t delay = info->delay_after_reset[index];
3788         uint32_t val = info->reset_reg_val[index];
3789         uint32_t reg = info->reset_reg[index];
3790         uint32_t type, offset;
3791
3792         type = BNXT_FW_STATUS_REG_TYPE(reg);
3793         offset = BNXT_FW_STATUS_REG_OFF(reg);
3794
3795         switch (type) {
3796         case BNXT_FW_STATUS_REG_TYPE_CFG:
3797                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3798                 break;
3799         case BNXT_FW_STATUS_REG_TYPE_GRC:
3800                 offset = bnxt_map_reset_regs(bp, offset);
3801                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3802                 break;
3803         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3804                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3805                 break;
3806         }
3807         /* wait on a specific interval of time until core reset is complete */
3808         if (delay)
3809                 rte_delay_ms(delay);
3810 }
3811
3812 static void bnxt_dev_cleanup(struct bnxt *bp)
3813 {
3814         bnxt_set_hwrm_link_config(bp, false);
3815         bp->link_info.link_up = 0;
3816         if (bp->dev_stopped == 0)
3817                 bnxt_dev_stop_op(bp->eth_dev);
3818
3819         bnxt_uninit_resources(bp, true);
3820 }
3821
3822 static int bnxt_restore_filters(struct bnxt *bp)
3823 {
3824         struct rte_eth_dev *dev = bp->eth_dev;
3825         int ret = 0;
3826
3827         if (dev->data->all_multicast)
3828                 ret = bnxt_allmulticast_enable_op(dev);
3829         if (dev->data->promiscuous)
3830                 ret = bnxt_promiscuous_enable_op(dev);
3831
3832         /* TODO restore other filters as well */
3833         return ret;
3834 }
3835
3836 static void bnxt_dev_recover(void *arg)
3837 {
3838         struct bnxt *bp = arg;
3839         int timeout = bp->fw_reset_max_msecs;
3840         int rc = 0;
3841
3842         /* Clear Error flag so that device re-init should happen */
3843         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3844
3845         do {
3846                 rc = bnxt_hwrm_ver_get(bp);
3847                 if (rc == 0)
3848                         break;
3849                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3850                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3851         } while (rc && timeout);
3852
3853         if (rc) {
3854                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3855                 goto err;
3856         }
3857
3858         rc = bnxt_init_resources(bp, true);
3859         if (rc) {
3860                 PMD_DRV_LOG(ERR,
3861                             "Failed to initialize resources after reset\n");
3862                 goto err;
3863         }
3864         /* clear reset flag as the device is initialized now */
3865         bp->flags &= ~BNXT_FLAG_FW_RESET;
3866
3867         rc = bnxt_dev_start_op(bp->eth_dev);
3868         if (rc) {
3869                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3870                 goto err;
3871         }
3872
3873         rc = bnxt_restore_filters(bp);
3874         if (rc)
3875                 goto err;
3876
3877         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3878         return;
3879 err:
3880         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3881         bnxt_uninit_resources(bp, false);
3882         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3883 }
3884
3885 void bnxt_dev_reset_and_resume(void *arg)
3886 {
3887         struct bnxt *bp = arg;
3888         int rc;
3889
3890         bnxt_dev_cleanup(bp);
3891
3892         bnxt_wait_for_device_shutdown(bp);
3893
3894         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3895                                bnxt_dev_recover, (void *)bp);
3896         if (rc)
3897                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3898 }
3899
3900 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3901 {
3902         struct bnxt_error_recovery_info *info = bp->recovery_info;
3903         uint32_t reg = info->status_regs[index];
3904         uint32_t type, offset, val = 0;
3905
3906         type = BNXT_FW_STATUS_REG_TYPE(reg);
3907         offset = BNXT_FW_STATUS_REG_OFF(reg);
3908
3909         switch (type) {
3910         case BNXT_FW_STATUS_REG_TYPE_CFG:
3911                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3912                 break;
3913         case BNXT_FW_STATUS_REG_TYPE_GRC:
3914                 offset = info->mapped_status_regs[index];
3915                 /* FALLTHROUGH */
3916         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3917                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3918                                        offset));
3919                 break;
3920         }
3921
3922         return val;
3923 }
3924
3925 static int bnxt_fw_reset_all(struct bnxt *bp)
3926 {
3927         struct bnxt_error_recovery_info *info = bp->recovery_info;
3928         uint32_t i;
3929         int rc = 0;
3930
3931         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3932                 /* Reset through master function driver */
3933                 for (i = 0; i < info->reg_array_cnt; i++)
3934                         bnxt_write_fw_reset_reg(bp, i);
3935                 /* Wait for time specified by FW after triggering reset */
3936                 rte_delay_ms(info->master_func_wait_period_after_reset);
3937         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3938                 /* Reset with the help of Kong processor */
3939                 rc = bnxt_hwrm_fw_reset(bp);
3940                 if (rc)
3941                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3942         }
3943
3944         return rc;
3945 }
3946
3947 static void bnxt_fw_reset_cb(void *arg)
3948 {
3949         struct bnxt *bp = arg;
3950         struct bnxt_error_recovery_info *info = bp->recovery_info;
3951         int rc = 0;
3952
3953         /* Only Master function can do FW reset */
3954         if (bnxt_is_master_func(bp) &&
3955             bnxt_is_recovery_enabled(bp)) {
3956                 rc = bnxt_fw_reset_all(bp);
3957                 if (rc) {
3958                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3959                         return;
3960                 }
3961         }
3962
3963         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3964          * EXCEPTION_FATAL_ASYNC event to all the functions
3965          * (including MASTER FUNC). After receiving this Async, all the active
3966          * drivers should treat this case as FW initiated recovery
3967          */
3968         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3969                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3970                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3971
3972                 /* To recover from error */
3973                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3974                                   (void *)bp);
3975         }
3976 }
3977
3978 /* Driver should poll FW heartbeat, reset_counter with the frequency
3979  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3980  * When the driver detects heartbeat stop or change in reset_counter,
3981  * it has to trigger a reset to recover from the error condition.
3982  * A “master PF” is the function who will have the privilege to
3983  * initiate the chimp reset. The master PF will be elected by the
3984  * firmware and will be notified through async message.
3985  */
3986 static void bnxt_check_fw_health(void *arg)
3987 {
3988         struct bnxt *bp = arg;
3989         struct bnxt_error_recovery_info *info = bp->recovery_info;
3990         uint32_t val = 0, wait_msec;
3991
3992         if (!info || !bnxt_is_recovery_enabled(bp) ||
3993             is_bnxt_in_error(bp))
3994                 return;
3995
3996         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3997         if (val == info->last_heart_beat)
3998                 goto reset;
3999
4000         info->last_heart_beat = val;
4001
4002         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4003         if (val != info->last_reset_counter)
4004                 goto reset;
4005
4006         info->last_reset_counter = val;
4007
4008         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4009                           bnxt_check_fw_health, (void *)bp);
4010
4011         return;
4012 reset:
4013         /* Stop DMA to/from device */
4014         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4015         bp->flags |= BNXT_FLAG_FW_RESET;
4016
4017         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4018
4019         if (bnxt_is_master_func(bp))
4020                 wait_msec = info->master_func_wait_period;
4021         else
4022                 wait_msec = info->normal_func_wait_period;
4023
4024         rte_eal_alarm_set(US_PER_MS * wait_msec,
4025                           bnxt_fw_reset_cb, (void *)bp);
4026 }
4027
4028 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4029 {
4030         uint32_t polling_freq;
4031
4032         if (!bnxt_is_recovery_enabled(bp))
4033                 return;
4034
4035         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4036                 return;
4037
4038         polling_freq = bp->recovery_info->driver_polling_freq;
4039
4040         rte_eal_alarm_set(US_PER_MS * polling_freq,
4041                           bnxt_check_fw_health, (void *)bp);
4042         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4043 }
4044
4045 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4046 {
4047         if (!bnxt_is_recovery_enabled(bp))
4048                 return;
4049
4050         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4051         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4052 }
4053
4054 static bool bnxt_vf_pciid(uint16_t id)
4055 {
4056         if (id == BROADCOM_DEV_ID_57304_VF ||
4057             id == BROADCOM_DEV_ID_57406_VF ||
4058             id == BROADCOM_DEV_ID_5731X_VF ||
4059             id == BROADCOM_DEV_ID_5741X_VF ||
4060             id == BROADCOM_DEV_ID_57414_VF ||
4061             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4062             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
4063             id == BROADCOM_DEV_ID_58802_VF ||
4064             id == BROADCOM_DEV_ID_57500_VF1 ||
4065             id == BROADCOM_DEV_ID_57500_VF2)
4066                 return true;
4067         return false;
4068 }
4069
4070 bool bnxt_stratus_device(struct bnxt *bp)
4071 {
4072         uint16_t id = bp->pdev->id.device_id;
4073
4074         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
4075             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4076             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
4077                 return true;
4078         return false;
4079 }
4080
4081 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4082 {
4083         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4084         struct bnxt *bp = eth_dev->data->dev_private;
4085
4086         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4087         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4088         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4089         if (!bp->bar0 || !bp->doorbell_base) {
4090                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4091                 return -ENODEV;
4092         }
4093
4094         bp->eth_dev = eth_dev;
4095         bp->pdev = pci_dev;
4096
4097         return 0;
4098 }
4099
4100 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4101                                   struct bnxt_ctx_pg_info *ctx_pg,
4102                                   uint32_t mem_size,
4103                                   const char *suffix,
4104                                   uint16_t idx)
4105 {
4106         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4107         const struct rte_memzone *mz = NULL;
4108         char mz_name[RTE_MEMZONE_NAMESIZE];
4109         rte_iova_t mz_phys_addr;
4110         uint64_t valid_bits = 0;
4111         uint32_t sz;
4112         int i;
4113
4114         if (!mem_size)
4115                 return 0;
4116
4117         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4118                          BNXT_PAGE_SIZE;
4119         rmem->page_size = BNXT_PAGE_SIZE;
4120         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4121         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4122         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4123
4124         valid_bits = PTU_PTE_VALID;
4125
4126         if (rmem->nr_pages > 1) {
4127                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4128                          "bnxt_ctx_pg_tbl%s_%x_%d",
4129                          suffix, idx, bp->eth_dev->data->port_id);
4130                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4131                 mz = rte_memzone_lookup(mz_name);
4132                 if (!mz) {
4133                         mz = rte_memzone_reserve_aligned(mz_name,
4134                                                 rmem->nr_pages * 8,
4135                                                 SOCKET_ID_ANY,
4136                                                 RTE_MEMZONE_2MB |
4137                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4138                                                 RTE_MEMZONE_IOVA_CONTIG,
4139                                                 BNXT_PAGE_SIZE);
4140                         if (mz == NULL)
4141                                 return -ENOMEM;
4142                 }
4143
4144                 memset(mz->addr, 0, mz->len);
4145                 mz_phys_addr = mz->iova;
4146                 if ((unsigned long)mz->addr == mz_phys_addr) {
4147                         PMD_DRV_LOG(DEBUG,
4148                                     "physical address same as virtual\n");
4149                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4150                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
4151                         if (mz_phys_addr == RTE_BAD_IOVA) {
4152                                 PMD_DRV_LOG(ERR,
4153                                         "unable to map addr to phys memory\n");
4154                                 return -ENOMEM;
4155                         }
4156                 }
4157                 rte_mem_lock_page(((char *)mz->addr));
4158
4159                 rmem->pg_tbl = mz->addr;
4160                 rmem->pg_tbl_map = mz_phys_addr;
4161                 rmem->pg_tbl_mz = mz;
4162         }
4163
4164         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4165                  suffix, idx, bp->eth_dev->data->port_id);
4166         mz = rte_memzone_lookup(mz_name);
4167         if (!mz) {
4168                 mz = rte_memzone_reserve_aligned(mz_name,
4169                                                  mem_size,
4170                                                  SOCKET_ID_ANY,
4171                                                  RTE_MEMZONE_1GB |
4172                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4173                                                  RTE_MEMZONE_IOVA_CONTIG,
4174                                                  BNXT_PAGE_SIZE);
4175                 if (mz == NULL)
4176                         return -ENOMEM;
4177         }
4178
4179         memset(mz->addr, 0, mz->len);
4180         mz_phys_addr = mz->iova;
4181         if ((unsigned long)mz->addr == mz_phys_addr) {
4182                 PMD_DRV_LOG(DEBUG,
4183                             "Memzone physical address same as virtual.\n");
4184                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4185                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4186                         rte_mem_lock_page(((char *)mz->addr) + sz);
4187                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4188                 if (mz_phys_addr == RTE_BAD_IOVA) {
4189                         PMD_DRV_LOG(ERR,
4190                                     "unable to map addr to phys memory\n");
4191                         return -ENOMEM;
4192                 }
4193         }
4194
4195         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4196                 rte_mem_lock_page(((char *)mz->addr) + sz);
4197                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4198                 rmem->dma_arr[i] = mz_phys_addr + sz;
4199
4200                 if (rmem->nr_pages > 1) {
4201                         if (i == rmem->nr_pages - 2 &&
4202                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4203                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4204                         else if (i == rmem->nr_pages - 1 &&
4205                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4206                                 valid_bits |= PTU_PTE_LAST;
4207
4208                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4209                                                            valid_bits);
4210                 }
4211         }
4212
4213         rmem->mz = mz;
4214         if (rmem->vmem_size)
4215                 rmem->vmem = (void **)mz->addr;
4216         rmem->dma_arr[0] = mz_phys_addr;
4217         return 0;
4218 }
4219
4220 static void bnxt_free_ctx_mem(struct bnxt *bp)
4221 {
4222         int i;
4223
4224         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4225                 return;
4226
4227         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4228         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4229         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4230         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4231         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4232         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4233         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4234         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4235         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4236         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4237         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4238
4239         for (i = 0; i < BNXT_MAX_Q; i++) {
4240                 if (bp->ctx->tqm_mem[i])
4241                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4242         }
4243
4244         rte_free(bp->ctx);
4245         bp->ctx = NULL;
4246 }
4247
4248 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4249
4250 #define min_t(type, x, y) ({                    \
4251         type __min1 = (x);                      \
4252         type __min2 = (y);                      \
4253         __min1 < __min2 ? __min1 : __min2; })
4254
4255 #define max_t(type, x, y) ({                    \
4256         type __max1 = (x);                      \
4257         type __max2 = (y);                      \
4258         __max1 > __max2 ? __max1 : __max2; })
4259
4260 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4261
4262 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4263 {
4264         struct bnxt_ctx_pg_info *ctx_pg;
4265         struct bnxt_ctx_mem_info *ctx;
4266         uint32_t mem_size, ena, entries;
4267         int i, rc;
4268
4269         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4270         if (rc) {
4271                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4272                 return rc;
4273         }
4274         ctx = bp->ctx;
4275         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4276                 return 0;
4277
4278         ctx_pg = &ctx->qp_mem;
4279         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4280         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4281         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4282         if (rc)
4283                 return rc;
4284
4285         ctx_pg = &ctx->srq_mem;
4286         ctx_pg->entries = ctx->srq_max_l2_entries;
4287         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4288         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4289         if (rc)
4290                 return rc;
4291
4292         ctx_pg = &ctx->cq_mem;
4293         ctx_pg->entries = ctx->cq_max_l2_entries;
4294         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4295         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4296         if (rc)
4297                 return rc;
4298
4299         ctx_pg = &ctx->vnic_mem;
4300         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4301                 ctx->vnic_max_ring_table_entries;
4302         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4303         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4304         if (rc)
4305                 return rc;
4306
4307         ctx_pg = &ctx->stat_mem;
4308         ctx_pg->entries = ctx->stat_max_entries;
4309         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4310         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4311         if (rc)
4312                 return rc;
4313
4314         entries = ctx->qp_max_l2_entries +
4315                   ctx->vnic_max_vnic_entries +
4316                   ctx->tqm_min_entries_per_ring;
4317         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4318         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4319                           ctx->tqm_max_entries_per_ring);
4320         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4321                 ctx_pg = ctx->tqm_mem[i];
4322                 /* use min tqm entries for now. */
4323                 ctx_pg->entries = entries;
4324                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4325                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4326                 if (rc)
4327                         return rc;
4328                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4329         }
4330
4331         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4332         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4333         if (rc)
4334                 PMD_DRV_LOG(ERR,
4335                             "Failed to configure context mem: rc = %d\n", rc);
4336         else
4337                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4338
4339         return rc;
4340 }
4341
4342 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4343 {
4344         struct rte_pci_device *pci_dev = bp->pdev;
4345         char mz_name[RTE_MEMZONE_NAMESIZE];
4346         const struct rte_memzone *mz = NULL;
4347         uint32_t total_alloc_len;
4348         rte_iova_t mz_phys_addr;
4349
4350         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4351                 return 0;
4352
4353         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4354                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4355                  pci_dev->addr.bus, pci_dev->addr.devid,
4356                  pci_dev->addr.function, "rx_port_stats");
4357         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4358         mz = rte_memzone_lookup(mz_name);
4359         total_alloc_len =
4360                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4361                                        sizeof(struct rx_port_stats_ext) + 512);
4362         if (!mz) {
4363                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4364                                          SOCKET_ID_ANY,
4365                                          RTE_MEMZONE_2MB |
4366                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4367                                          RTE_MEMZONE_IOVA_CONTIG);
4368                 if (mz == NULL)
4369                         return -ENOMEM;
4370         }
4371         memset(mz->addr, 0, mz->len);
4372         mz_phys_addr = mz->iova;
4373         if ((unsigned long)mz->addr == mz_phys_addr) {
4374                 PMD_DRV_LOG(DEBUG,
4375                             "Memzone physical address same as virtual.\n");
4376                 PMD_DRV_LOG(DEBUG,
4377                             "Using rte_mem_virt2iova()\n");
4378                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4379                 if (mz_phys_addr == RTE_BAD_IOVA) {
4380                         PMD_DRV_LOG(ERR,
4381                                     "Can't map address to physical memory\n");
4382                         return -ENOMEM;
4383                 }
4384         }
4385
4386         bp->rx_mem_zone = (const void *)mz;
4387         bp->hw_rx_port_stats = mz->addr;
4388         bp->hw_rx_port_stats_map = mz_phys_addr;
4389
4390         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4391                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4392                  pci_dev->addr.bus, pci_dev->addr.devid,
4393                  pci_dev->addr.function, "tx_port_stats");
4394         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4395         mz = rte_memzone_lookup(mz_name);
4396         total_alloc_len =
4397                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4398                                        sizeof(struct tx_port_stats_ext) + 512);
4399         if (!mz) {
4400                 mz = rte_memzone_reserve(mz_name,
4401                                          total_alloc_len,
4402                                          SOCKET_ID_ANY,
4403                                          RTE_MEMZONE_2MB |
4404                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4405                                          RTE_MEMZONE_IOVA_CONTIG);
4406                 if (mz == NULL)
4407                         return -ENOMEM;
4408         }
4409         memset(mz->addr, 0, mz->len);
4410         mz_phys_addr = mz->iova;
4411         if ((unsigned long)mz->addr == mz_phys_addr) {
4412                 PMD_DRV_LOG(DEBUG,
4413                             "Memzone physical address same as virtual\n");
4414                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4415                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4416                 if (mz_phys_addr == RTE_BAD_IOVA) {
4417                         PMD_DRV_LOG(ERR,
4418                                     "Can't map address to physical memory\n");
4419                         return -ENOMEM;
4420                 }
4421         }
4422
4423         bp->tx_mem_zone = (const void *)mz;
4424         bp->hw_tx_port_stats = mz->addr;
4425         bp->hw_tx_port_stats_map = mz_phys_addr;
4426         bp->flags |= BNXT_FLAG_PORT_STATS;
4427
4428         /* Display extended statistics if FW supports it */
4429         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4430             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4431             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4432                 return 0;
4433
4434         bp->hw_rx_port_stats_ext = (void *)
4435                 ((uint8_t *)bp->hw_rx_port_stats +
4436                  sizeof(struct rx_port_stats));
4437         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4438                 sizeof(struct rx_port_stats);
4439         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4440
4441         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4442             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4443                 bp->hw_tx_port_stats_ext = (void *)
4444                         ((uint8_t *)bp->hw_tx_port_stats +
4445                          sizeof(struct tx_port_stats));
4446                 bp->hw_tx_port_stats_ext_map =
4447                         bp->hw_tx_port_stats_map +
4448                         sizeof(struct tx_port_stats);
4449                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4450         }
4451
4452         return 0;
4453 }
4454
4455 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4456 {
4457         struct bnxt *bp = eth_dev->data->dev_private;
4458         int rc = 0;
4459
4460         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4461                                                RTE_ETHER_ADDR_LEN *
4462                                                bp->max_l2_ctx,
4463                                                0);
4464         if (eth_dev->data->mac_addrs == NULL) {
4465                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4466                 return -ENOMEM;
4467         }
4468
4469         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4470                 if (BNXT_PF(bp))
4471                         return -EINVAL;
4472
4473                 /* Generate a random MAC address, if none was assigned by PF */
4474                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4475                 bnxt_eth_hw_addr_random(bp->mac_addr);
4476                 PMD_DRV_LOG(INFO,
4477                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4478                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4479                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4480
4481                 rc = bnxt_hwrm_set_mac(bp);
4482                 if (!rc)
4483                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4484                                RTE_ETHER_ADDR_LEN);
4485                 return rc;
4486         }
4487
4488         /* Copy the permanent MAC from the FUNC_QCAPS response */
4489         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4490         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4491
4492         return rc;
4493 }
4494
4495 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4496 {
4497         int rc = 0;
4498
4499         /* MAC is already configured in FW */
4500         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4501                 return 0;
4502
4503         /* Restore the old MAC configured */
4504         rc = bnxt_hwrm_set_mac(bp);
4505         if (rc)
4506                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4507
4508         return rc;
4509 }
4510
4511 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4512 {
4513         if (!BNXT_PF(bp))
4514                 return;
4515
4516 #define ALLOW_FUNC(x)   \
4517         { \
4518                 uint32_t arg = (x); \
4519                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4520                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4521         }
4522
4523         /* Forward all requests if firmware is new enough */
4524         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4525              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4526             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4527                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4528         } else {
4529                 PMD_DRV_LOG(WARNING,
4530                             "Firmware too old for VF mailbox functionality\n");
4531                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4532         }
4533
4534         /*
4535          * The following are used for driver cleanup. If we disallow these,
4536          * VF drivers can't clean up cleanly.
4537          */
4538         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4539         ALLOW_FUNC(HWRM_VNIC_FREE);
4540         ALLOW_FUNC(HWRM_RING_FREE);
4541         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4542         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4543         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4544         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4545         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4546         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4547 }
4548
4549 static int bnxt_init_fw(struct bnxt *bp)
4550 {
4551         uint16_t mtu;
4552         int rc = 0;
4553
4554         rc = bnxt_hwrm_ver_get(bp);
4555         if (rc)
4556                 return rc;
4557
4558         rc = bnxt_hwrm_func_reset(bp);
4559         if (rc)
4560                 return -EIO;
4561
4562         rc = bnxt_hwrm_vnic_qcaps(bp);
4563         if (rc)
4564                 return rc;
4565
4566         rc = bnxt_hwrm_queue_qportcfg(bp);
4567         if (rc)
4568                 return rc;
4569
4570         /* Get the MAX capabilities for this function.
4571          * This function also allocates context memory for TQM rings and
4572          * informs the firmware about this allocated backing store memory.
4573          */
4574         rc = bnxt_hwrm_func_qcaps(bp);
4575         if (rc)
4576                 return rc;
4577
4578         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4579         if (rc)
4580                 return rc;
4581
4582         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4583         if (rc)
4584                 return rc;
4585
4586         /* Get the adapter error recovery support info */
4587         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4588         if (rc)
4589                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4590
4591         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4592             mtu != bp->eth_dev->data->mtu)
4593                 bp->eth_dev->data->mtu = mtu;
4594
4595         bnxt_hwrm_port_led_qcaps(bp);
4596
4597         return 0;
4598 }
4599
4600 static int
4601 bnxt_init_locks(struct bnxt *bp)
4602 {
4603         int err;
4604
4605         err = pthread_mutex_init(&bp->flow_lock, NULL);
4606         if (err)
4607                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4608         return err;
4609 }
4610
4611 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4612 {
4613         int rc;
4614
4615         rc = bnxt_init_fw(bp);
4616         if (rc)
4617                 return rc;
4618
4619         if (!reconfig_dev) {
4620                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4621                 if (rc)
4622                         return rc;
4623         } else {
4624                 rc = bnxt_restore_dflt_mac(bp);
4625                 if (rc)
4626                         return rc;
4627         }
4628
4629         bnxt_config_vf_req_fwd(bp);
4630
4631         rc = bnxt_hwrm_func_driver_register(bp);
4632         if (rc) {
4633                 PMD_DRV_LOG(ERR, "Failed to register driver");
4634                 return -EBUSY;
4635         }
4636
4637         if (BNXT_PF(bp)) {
4638                 if (bp->pdev->max_vfs) {
4639                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4640                         if (rc) {
4641                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4642                                 return rc;
4643                         }
4644                 } else {
4645                         rc = bnxt_hwrm_allocate_pf_only(bp);
4646                         if (rc) {
4647                                 PMD_DRV_LOG(ERR,
4648                                             "Failed to allocate PF resources");
4649                                 return rc;
4650                         }
4651                 }
4652         }
4653
4654         rc = bnxt_alloc_mem(bp, reconfig_dev);
4655         if (rc)
4656                 return rc;
4657
4658         rc = bnxt_setup_int(bp);
4659         if (rc)
4660                 return rc;
4661
4662         bnxt_init_nic(bp);
4663
4664         rc = bnxt_request_int(bp);
4665         if (rc)
4666                 return rc;
4667
4668         rc = bnxt_init_locks(bp);
4669         if (rc)
4670                 return rc;
4671
4672         return 0;
4673 }
4674
4675 static int
4676 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4677 {
4678         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4679         static int version_printed;
4680         struct bnxt *bp;
4681         int rc;
4682
4683         if (version_printed++ == 0)
4684                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4685
4686         eth_dev->dev_ops = &bnxt_dev_ops;
4687         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4688         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4689
4690         /*
4691          * For secondary processes, we don't initialise any further
4692          * as primary has already done this work.
4693          */
4694         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4695                 return 0;
4696
4697         rte_eth_copy_pci_info(eth_dev, pci_dev);
4698
4699         bp = eth_dev->data->dev_private;
4700
4701         bp->dev_stopped = 1;
4702
4703         if (bnxt_vf_pciid(pci_dev->id.device_id))
4704                 bp->flags |= BNXT_FLAG_VF;
4705
4706         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4707             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4708             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4709             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4710             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4711                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4712
4713         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4714             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4715             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4716             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4717                 bp->flags |= BNXT_FLAG_STINGRAY;
4718
4719         rc = bnxt_init_board(eth_dev);
4720         if (rc) {
4721                 PMD_DRV_LOG(ERR,
4722                             "Failed to initialize board rc: %x\n", rc);
4723                 return rc;
4724         }
4725
4726         rc = bnxt_alloc_hwrm_resources(bp);
4727         if (rc) {
4728                 PMD_DRV_LOG(ERR,
4729                             "Failed to allocate hwrm resource rc: %x\n", rc);
4730                 goto error_free;
4731         }
4732         rc = bnxt_init_resources(bp, false);
4733         if (rc)
4734                 goto error_free;
4735
4736         rc = bnxt_alloc_stats_mem(bp);
4737         if (rc)
4738                 goto error_free;
4739
4740         PMD_DRV_LOG(INFO,
4741                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4742                     pci_dev->mem_resource[0].phys_addr,
4743                     pci_dev->mem_resource[0].addr);
4744
4745         return 0;
4746
4747 error_free:
4748         bnxt_dev_uninit(eth_dev);
4749         return rc;
4750 }
4751
4752 static void
4753 bnxt_uninit_locks(struct bnxt *bp)
4754 {
4755         pthread_mutex_destroy(&bp->flow_lock);
4756 }
4757
4758 static int
4759 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4760 {
4761         int rc;
4762
4763         bnxt_free_int(bp);
4764         bnxt_free_mem(bp, reconfig_dev);
4765         bnxt_hwrm_func_buf_unrgtr(bp);
4766         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4767         bp->flags &= ~BNXT_FLAG_REGISTERED;
4768         bnxt_free_ctx_mem(bp);
4769         if (!reconfig_dev) {
4770                 bnxt_free_hwrm_resources(bp);
4771
4772                 if (bp->recovery_info != NULL) {
4773                         rte_free(bp->recovery_info);
4774                         bp->recovery_info = NULL;
4775                 }
4776         }
4777
4778         rte_free(bp->ptp_cfg);
4779         bp->ptp_cfg = NULL;
4780         return rc;
4781 }
4782
4783 static int
4784 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4785 {
4786         struct bnxt *bp = eth_dev->data->dev_private;
4787         int rc;
4788
4789         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4790                 return -EPERM;
4791
4792         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4793
4794         rc = bnxt_uninit_resources(bp, false);
4795
4796         if (bp->grp_info != NULL) {
4797                 rte_free(bp->grp_info);
4798                 bp->grp_info = NULL;
4799         }
4800
4801         if (bp->tx_mem_zone) {
4802                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4803                 bp->tx_mem_zone = NULL;
4804         }
4805
4806         if (bp->rx_mem_zone) {
4807                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4808                 bp->rx_mem_zone = NULL;
4809         }
4810
4811         if (bp->dev_stopped == 0)
4812                 bnxt_dev_close_op(eth_dev);
4813         if (bp->pf.vf_info)
4814                 rte_free(bp->pf.vf_info);
4815         eth_dev->dev_ops = NULL;
4816         eth_dev->rx_pkt_burst = NULL;
4817         eth_dev->tx_pkt_burst = NULL;
4818
4819         bnxt_uninit_locks(bp);
4820
4821         return rc;
4822 }
4823
4824 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4825         struct rte_pci_device *pci_dev)
4826 {
4827         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4828                 bnxt_dev_init);
4829 }
4830
4831 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4832 {
4833         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4834                 return rte_eth_dev_pci_generic_remove(pci_dev,
4835                                 bnxt_dev_uninit);
4836         else
4837                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4838 }
4839
4840 static struct rte_pci_driver bnxt_rte_pmd = {
4841         .id_table = bnxt_pci_id_map,
4842         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4843         .probe = bnxt_pci_probe,
4844         .remove = bnxt_pci_remove,
4845 };
4846
4847 static bool
4848 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4849 {
4850         if (strcmp(dev->device->driver->name, drv->driver.name))
4851                 return false;
4852
4853         return true;
4854 }
4855
4856 bool is_bnxt_supported(struct rte_eth_dev *dev)
4857 {
4858         return is_device_supported(dev, &bnxt_rte_pmd);
4859 }
4860
4861 RTE_INIT(bnxt_init_log)
4862 {
4863         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4864         if (bnxt_logtype_driver >= 0)
4865                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4866 }
4867
4868 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4869 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4870 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");