drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100
 101 static const char *const bnxt_dev_args[] = {
 102         BNXT_DEVARG_REPRESENTOR,
 103         BNXT_DEVARG_TRUFLOW,
 104         BNXT_DEVARG_FLOW_XSTAT,
 105         BNXT_DEVARG_MAX_NUM_KFLOWS,
 106         BNXT_DEVARG_REP_BASED_PF,
 107         BNXT_DEVARG_REP_IS_PF,
 108         BNXT_DEVARG_REP_Q_R2F,
 109         BNXT_DEVARG_REP_Q_F2R,
 110         BNXT_DEVARG_REP_FC_R2F,
 111         BNXT_DEVARG_REP_FC_F2R,
 112         NULL
 113 };
 114
 115 /*
 116  * truflow == false to disable the feature
 117  * truflow == true to enable the feature
 118  */
 119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 120
 121 /*
 122  * flow_xstat == false to disable the feature
 123  * flow_xstat == true to enable the feature
 124  */
 125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 126
 127 /*
 128  * rep_is_pf == false to indicate VF representor
 129  * rep_is_pf == true to indicate PF representor
 130  */
 131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 132
 133 /*
 134  * rep_based_pf == Physical index of the PF
 135  */
 136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 137 /*
 138  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 139  */
 140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 141
 142 /*
 143  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 144  */
 145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 146
 147 /*
 148  * rep_fc_r2f == Flow control for the representor to endpoint direction
 149  */
 150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 151
 152 /*
 153  * rep_fc_f2r == Flow control for the endpoint to representor direction
 154  */
 155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 156
 157 int bnxt_cfa_code_dynfield_offset = -1;
 158
 159 /*
 160  * max_num_kflows must be >= 32
 161  * and must be a power-of-2 supported value
 162  * return: 1 -> invalid
 163  *         0 -> valid
 164  */
 165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 166 {
 167         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 168                 return 1;
 169         return 0;
 170 }
 171
 172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 178 static void bnxt_dev_recover(void *arg);
 179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 180 static void bnxt_free_rep_info(struct bnxt *bp);
 181
 182 int is_bnxt_in_error(struct bnxt *bp)
 183 {
 184         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 185                 return -EIO;
 186         if (bp->flags & BNXT_FLAG_FW_RESET)
 187                 return -EBUSY;
 188
 189         return 0;
 190 }
 191
 192 /***********************/
 193
 194 /*
 195  * High level utility functions
 196  */
 197
 198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 199 {
 200         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 201                                              BNXT_RSS_TBL_SIZE_P5);
 202
 203         if (!BNXT_CHIP_P5(bp))
 204                 return 1;
 205
 206         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 207                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 208                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 209 }
 210
 211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 212 {
 213         if (!BNXT_CHIP_P5(bp))
 214                 return HW_HASH_INDEX_SIZE;
 215
 216         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 217 }
 218
 219 static void bnxt_free_parent_info(struct bnxt *bp)
 220 {
 221         rte_free(bp->parent);
 222 }
 223
 224 static void bnxt_free_pf_info(struct bnxt *bp)
 225 {
 226         rte_free(bp->pf);
 227 }
 228
 229 static void bnxt_free_link_info(struct bnxt *bp)
 230 {
 231         rte_free(bp->link_info);
 232 }
 233
 234 static void bnxt_free_leds_info(struct bnxt *bp)
 235 {
 236         if (BNXT_VF(bp))
 237                 return;
 238
 239         rte_free(bp->leds);
 240         bp->leds = NULL;
 241 }
 242
 243 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 244 {
 245         rte_free(bp->flow_stat);
 246         bp->flow_stat = NULL;
 247 }
 248
 249 static void bnxt_free_cos_queues(struct bnxt *bp)
 250 {
 251         rte_free(bp->rx_cos_queue);
 252         rte_free(bp->tx_cos_queue);
 253 }
 254
 255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 256 {
 257         bnxt_free_filter_mem(bp);
 258         bnxt_free_vnic_attributes(bp);
 259         bnxt_free_vnic_mem(bp);
 260
 261         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 262          * If the number of rings change across fw update,
 263          * we don't have much choice except to warn the user.
 264          */
 265         if (!reconfig) {
 266                 bnxt_free_stats(bp);
 267                 bnxt_free_tx_rings(bp);
 268                 bnxt_free_rx_rings(bp);
 269         }
 270         bnxt_free_async_cp_ring(bp);
 271         bnxt_free_rxtx_nq_ring(bp);
 272
 273         rte_free(bp->grp_info);
 274         bp->grp_info = NULL;
 275 }
 276
 277 static int bnxt_alloc_parent_info(struct bnxt *bp)
 278 {
 279         bp->parent = rte_zmalloc("bnxt_parent_info",
 280                                  sizeof(struct bnxt_parent_info), 0);
 281         if (bp->parent == NULL)
 282                 return -ENOMEM;
 283
 284         return 0;
 285 }
 286
 287 static int bnxt_alloc_pf_info(struct bnxt *bp)
 288 {
 289         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 290         if (bp->pf == NULL)
 291                 return -ENOMEM;
 292
 293         return 0;
 294 }
 295
 296 static int bnxt_alloc_link_info(struct bnxt *bp)
 297 {
 298         bp->link_info =
 299                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 300         if (bp->link_info == NULL)
 301                 return -ENOMEM;
 302
 303         return 0;
 304 }
 305
 306 static int bnxt_alloc_leds_info(struct bnxt *bp)
 307 {
 308         if (BNXT_VF(bp))
 309                 return 0;
 310
 311         bp->leds = rte_zmalloc("bnxt_leds",
 312                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 313                                0);
 314         if (bp->leds == NULL)
 315                 return -ENOMEM;
 316
 317         return 0;
 318 }
 319
 320 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 321 {
 322         bp->rx_cos_queue =
 323                 rte_zmalloc("bnxt_rx_cosq",
 324                             BNXT_COS_QUEUE_COUNT *
 325                             sizeof(struct bnxt_cos_queue_info),
 326                             0);
 327         if (bp->rx_cos_queue == NULL)
 328                 return -ENOMEM;
 329
 330         bp->tx_cos_queue =
 331                 rte_zmalloc("bnxt_tx_cosq",
 332                             BNXT_COS_QUEUE_COUNT *
 333                             sizeof(struct bnxt_cos_queue_info),
 334                             0);
 335         if (bp->tx_cos_queue == NULL)
 336                 return -ENOMEM;
 337
 338         return 0;
 339 }
 340
 341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 342 {
 343         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 344                                     sizeof(struct bnxt_flow_stat_info), 0);
 345         if (bp->flow_stat == NULL)
 346                 return -ENOMEM;
 347
 348         return 0;
 349 }
 350
 351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 352 {
 353         int rc;
 354
 355         rc = bnxt_alloc_ring_grps(bp);
 356         if (rc)
 357                 goto alloc_mem_err;
 358
 359         rc = bnxt_alloc_async_ring_struct(bp);
 360         if (rc)
 361                 goto alloc_mem_err;
 362
 363         rc = bnxt_alloc_vnic_mem(bp);
 364         if (rc)
 365                 goto alloc_mem_err;
 366
 367         rc = bnxt_alloc_vnic_attributes(bp);
 368         if (rc)
 369                 goto alloc_mem_err;
 370
 371         rc = bnxt_alloc_filter_mem(bp);
 372         if (rc)
 373                 goto alloc_mem_err;
 374
 375         rc = bnxt_alloc_async_cp_ring(bp);
 376         if (rc)
 377                 goto alloc_mem_err;
 378
 379         rc = bnxt_alloc_rxtx_nq_ring(bp);
 380         if (rc)
 381                 goto alloc_mem_err;
 382
 383         if (BNXT_FLOW_XSTATS_EN(bp)) {
 384                 rc = bnxt_alloc_flow_stats_info(bp);
 385                 if (rc)
 386                         goto alloc_mem_err;
 387         }
 388
 389         return 0;
 390
 391 alloc_mem_err:
 392         bnxt_free_mem(bp, reconfig);
 393         return rc;
 394 }
 395
 396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 397 {
 398         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 399         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 400         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 401         struct bnxt_rx_queue *rxq;
 402         unsigned int j;
 403         int rc;
 404
 405         rc = bnxt_vnic_grp_alloc(bp, vnic);
 406         if (rc)
 407                 goto err_out;
 408
 409         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 410                     vnic_id, vnic, vnic->fw_grp_ids);
 411
 412         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 413         if (rc)
 414                 goto err_out;
 415
 416         /* Alloc RSS context only if RSS mode is enabled */
 417         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 418                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 419
 420                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 421                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 422                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 423                         PMD_DRV_LOG(ERR,
 424                                     "Only queues 0-%d will be in RSS table\n",
 425                                     BNXT_RSS_TBL_SIZE_P5 - 1);
 426                 }
 427
 428                 rc = 0;
 429                 for (j = 0; j < nr_ctxs; j++) {
 430                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 431                         if (rc)
 432                                 break;
 433                 }
 434                 if (rc) {
 435                         PMD_DRV_LOG(ERR,
 436                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 437                                     vnic_id, j, rc);
 438                         goto err_out;
 439                 }
 440                 vnic->num_lb_ctxts = nr_ctxs;
 441         }
 442
 443         /*
 444          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 445          * setting is not available at this time, it will not be
 446          * configured correctly in the CFA.
 447          */
 448         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 449                 vnic->vlan_strip = true;
 450         else
 451                 vnic->vlan_strip = false;
 452
 453         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 454         if (rc)
 455                 goto err_out;
 456
 457         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 458         if (rc)
 459                 goto err_out;
 460
 461         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 462                 rxq = bp->eth_dev->data->rx_queues[j];
 463
 464                 PMD_DRV_LOG(DEBUG,
 465                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 466                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 467
 468                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 469                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 470                 else
 471                         vnic->rx_queue_cnt++;
 472         }
 473
 474         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 475
 476         rc = bnxt_vnic_rss_configure(bp, vnic);
 477         if (rc)
 478                 goto err_out;
 479
 480         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 481
 482         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 483                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 484         else
 485                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 486
 487         return 0;
 488 err_out:
 489         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 490                     vnic_id, rc);
 491         return rc;
 492 }
 493
 494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 495 {
 496         int rc = 0;
 497
 498         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 499                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 500         if (rc)
 501                 return rc;
 502
 503         PMD_DRV_LOG(DEBUG,
 504                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 505                     " rx_fc_in_tbl.ctx_id = %d\n",
 506                     bp->flow_stat->rx_fc_in_tbl.va,
 507                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 508                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 509
 510         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 511                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 512         if (rc)
 513                 return rc;
 514
 515         PMD_DRV_LOG(DEBUG,
 516                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 517                     " rx_fc_out_tbl.ctx_id = %d\n",
 518                     bp->flow_stat->rx_fc_out_tbl.va,
 519                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 520                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 521
 522         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 523                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 524         if (rc)
 525                 return rc;
 526
 527         PMD_DRV_LOG(DEBUG,
 528                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 529                     " tx_fc_in_tbl.ctx_id = %d\n",
 530                     bp->flow_stat->tx_fc_in_tbl.va,
 531                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 532                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 533
 534         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 535                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 536         if (rc)
 537                 return rc;
 538
 539         PMD_DRV_LOG(DEBUG,
 540                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 541                     " tx_fc_out_tbl.ctx_id = %d\n",
 542                     bp->flow_stat->tx_fc_out_tbl.va,
 543                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 544                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 545
 546         memset(bp->flow_stat->rx_fc_out_tbl.va,
 547                0,
 548                bp->flow_stat->rx_fc_out_tbl.size);
 549         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 550                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 551                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 552                                        bp->flow_stat->max_fc,
 553                                        true);
 554         if (rc)
 555                 return rc;
 556
 557         memset(bp->flow_stat->tx_fc_out_tbl.va,
 558                0,
 559                bp->flow_stat->tx_fc_out_tbl.size);
 560         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 561                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 562                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 563                                        bp->flow_stat->max_fc,
 564                                        true);
 565
 566         return rc;
 567 }
 568
 569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 570                                   struct bnxt_ctx_mem_buf_info *ctx)
 571 {
 572         if (!ctx)
 573                 return -EINVAL;
 574
 575         ctx->va = rte_zmalloc(type, size, 0);
 576         if (ctx->va == NULL)
 577                 return -ENOMEM;
 578         rte_mem_lock_page(ctx->va);
 579         ctx->size = size;
 580         ctx->dma = rte_mem_virt2iova(ctx->va);
 581         if (ctx->dma == RTE_BAD_IOVA)
 582                 return -ENOMEM;
 583
 584         return 0;
 585 }
 586
 587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 588 {
 589         struct rte_pci_device *pdev = bp->pdev;
 590         char type[RTE_MEMZONE_NAMESIZE];
 591         uint16_t max_fc;
 592         int rc = 0;
 593
 594         max_fc = bp->flow_stat->max_fc;
 595
 596         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 597                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 598         /* 4 bytes for each counter-id */
 599         rc = bnxt_alloc_ctx_mem_buf(type,
 600                                     max_fc * 4,
 601                                     &bp->flow_stat->rx_fc_in_tbl);
 602         if (rc)
 603                 return rc;
 604
 605         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 606                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 607         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 608         rc = bnxt_alloc_ctx_mem_buf(type,
 609                                     max_fc * 16,
 610                                     &bp->flow_stat->rx_fc_out_tbl);
 611         if (rc)
 612                 return rc;
 613
 614         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 615                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 616         /* 4 bytes for each counter-id */
 617         rc = bnxt_alloc_ctx_mem_buf(type,
 618                                     max_fc * 4,
 619                                     &bp->flow_stat->tx_fc_in_tbl);
 620         if (rc)
 621                 return rc;
 622
 623         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 624                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 625         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 626         rc = bnxt_alloc_ctx_mem_buf(type,
 627                                     max_fc * 16,
 628                                     &bp->flow_stat->tx_fc_out_tbl);
 629         if (rc)
 630                 return rc;
 631
 632         rc = bnxt_register_fc_ctx_mem(bp);
 633
 634         return rc;
 635 }
 636
 637 static int bnxt_init_ctx_mem(struct bnxt *bp)
 638 {
 639         int rc = 0;
 640
 641         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 642             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 643             !BNXT_FLOW_XSTATS_EN(bp))
 644                 return 0;
 645
 646         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 647         if (rc)
 648                 return rc;
 649
 650         rc = bnxt_init_fc_ctx_mem(bp);
 651
 652         return rc;
 653 }
 654
 655 static int bnxt_update_phy_setting(struct bnxt *bp)
 656 {
 657         struct rte_eth_link new;
 658         int rc;
 659
 660         rc = bnxt_get_hwrm_link_config(bp, &new);
 661         if (rc) {
 662                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 663                 return rc;
 664         }
 665
 666         /*
 667          * On BCM957508-N2100 adapters, FW will not allow any user other
 668          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 669          * always returns link up. Force phy update always in that case.
 670          */
 671         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 672                 rc = bnxt_set_hwrm_link_config(bp, true);
 673                 if (rc) {
 674                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 675                         return rc;
 676                 }
 677         }
 678
 679         return rc;
 680 }
 681
 682 static int bnxt_start_nic(struct bnxt *bp)
 683 {
 684         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 685         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 686         uint32_t intr_vector = 0;
 687         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 688         uint32_t vec = BNXT_MISC_VEC_ID;
 689         unsigned int i, j;
 690         int rc;
 691
 692         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 693                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 694                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 695                 bp->flags |= BNXT_FLAG_JUMBO;
 696         } else {
 697                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 698                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 699                 bp->flags &= ~BNXT_FLAG_JUMBO;
 700         }
 701
 702         /* THOR does not support ring groups.
 703          * But we will use the array to save RSS context IDs.
 704          */
 705         if (BNXT_CHIP_P5(bp))
 706                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 707
 708         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 709         if (rc) {
 710                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 711                 goto err_out;
 712         }
 713
 714         rc = bnxt_alloc_hwrm_rings(bp);
 715         if (rc) {
 716                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 717                 goto err_out;
 718         }
 719
 720         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 721         if (rc) {
 722                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 723                 goto err_out;
 724         }
 725
 726         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 727                 goto skip_cosq_cfg;
 728
 729         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 730                 if (bp->rx_cos_queue[i].id != 0xff) {
 731                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 732
 733                         if (!vnic) {
 734                                 PMD_DRV_LOG(ERR,
 735                                             "Num pools more than FW profile\n");
 736                                 rc = -EINVAL;
 737                                 goto err_out;
 738                         }
 739                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 740                         bp->rx_cosq_cnt++;
 741                 }
 742         }
 743
 744 skip_cosq_cfg:
 745         rc = bnxt_mq_rx_configure(bp);
 746         if (rc) {
 747                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 748                 goto err_out;
 749         }
 750
 751         /* default vnic 0 */
 752         rc = bnxt_setup_one_vnic(bp, 0);
 753         if (rc)
 754                 goto err_out;
 755         /* VNIC configuration */
 756         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 757                 for (i = 1; i < bp->nr_vnics; i++) {
 758                         rc = bnxt_setup_one_vnic(bp, i);
 759                         if (rc)
 760                                 goto err_out;
 761                 }
 762         }
 763
 764         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 765         if (rc) {
 766                 PMD_DRV_LOG(ERR,
 767                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 768                 goto err_out;
 769         }
 770
 771         /* check and configure queue intr-vector mapping */
 772         if ((rte_intr_cap_multiple(intr_handle) ||
 773              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 774             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 775                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 776                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 777                 if (intr_vector > bp->rx_cp_nr_rings) {
 778                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 779                                         bp->rx_cp_nr_rings);
 780                         return -ENOTSUP;
 781                 }
 782                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 783                 if (rc)
 784                         return rc;
 785         }
 786
 787         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 788                 intr_handle->intr_vec =
 789                         rte_zmalloc("intr_vec",
 790                                     bp->eth_dev->data->nb_rx_queues *
 791                                     sizeof(int), 0);
 792                 if (intr_handle->intr_vec == NULL) {
 793                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 794                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 795                         rc = -ENOMEM;
 796                         goto err_disable;
 797                 }
 798                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 799                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 800                          intr_handle->intr_vec, intr_handle->nb_efd,
 801                         intr_handle->max_intr);
 802                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 803                      queue_id++) {
 804                         intr_handle->intr_vec[queue_id] =
 805                                                         vec + BNXT_RX_VEC_START;
 806                         if (vec < base + intr_handle->nb_efd - 1)
 807                                 vec++;
 808                 }
 809         }
 810
 811         /* enable uio/vfio intr/eventfd mapping */
 812         rc = rte_intr_enable(intr_handle);
 813 #ifndef RTE_EXEC_ENV_FREEBSD
 814         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 815         if (rc)
 816                 goto err_free;
 817 #endif
 818
 819         rc = bnxt_update_phy_setting(bp);
 820         if (rc)
 821                 goto err_free;
 822
 823         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 824         if (!bp->mark_table)
 825                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 826
 827         return 0;
 828
 829 err_free:
 830         rte_free(intr_handle->intr_vec);
 831 err_disable:
 832         rte_intr_efd_disable(intr_handle);
 833 err_out:
 834         /* Some of the error status returned by FW may not be from errno.h */
 835         if (rc > 0)
 836                 rc = -EIO;
 837
 838         return rc;
 839 }
 840
 841 static int bnxt_shutdown_nic(struct bnxt *bp)
 842 {
 843         bnxt_free_all_hwrm_resources(bp);
 844         bnxt_free_all_filters(bp);
 845         bnxt_free_all_vnics(bp);
 846         return 0;
 847 }
 848
 849 /*
 850  * Device configuration and status function
 851  */
 852
 853 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 854 {
 855         uint32_t link_speed = bp->link_info->support_speeds;
 856         uint32_t speed_capa = 0;
 857
 858         /* If PAM4 is configured, use PAM4 supported speed */
 859         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 860                 link_speed = bp->link_info->support_pam4_speeds;
 861
 862         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 863                 speed_capa |= ETH_LINK_SPEED_100M;
 864         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 865                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 866         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 867                 speed_capa |= ETH_LINK_SPEED_1G;
 868         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 869                 speed_capa |= ETH_LINK_SPEED_2_5G;
 870         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 871                 speed_capa |= ETH_LINK_SPEED_10G;
 872         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 873                 speed_capa |= ETH_LINK_SPEED_20G;
 874         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 875                 speed_capa |= ETH_LINK_SPEED_25G;
 876         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 877                 speed_capa |= ETH_LINK_SPEED_40G;
 878         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 879                 speed_capa |= ETH_LINK_SPEED_50G;
 880         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 881                 speed_capa |= ETH_LINK_SPEED_100G;
 882         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 883                 speed_capa |= ETH_LINK_SPEED_50G;
 884         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 885                 speed_capa |= ETH_LINK_SPEED_100G;
 886         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 887                 speed_capa |= ETH_LINK_SPEED_200G;
 888
 889         if (bp->link_info->auto_mode ==
 890             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 891                 speed_capa |= ETH_LINK_SPEED_FIXED;
 892         else
 893                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 894
 895         return speed_capa;
 896 }
 897
 898 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 899                                 struct rte_eth_dev_info *dev_info)
 900 {
 901         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 902         struct bnxt *bp = eth_dev->data->dev_private;
 903         uint16_t max_vnics, i, j, vpool, vrxq;
 904         unsigned int max_rx_rings;
 905         int rc;
 906
 907         rc = is_bnxt_in_error(bp);
 908         if (rc)
 909                 return rc;
 910
 911         /* MAC Specifics */
 912         dev_info->max_mac_addrs = bp->max_l2_ctx;
 913         dev_info->max_hash_mac_addrs = 0;
 914
 915         /* PF/VF specifics */
 916         if (BNXT_PF(bp))
 917                 dev_info->max_vfs = pdev->max_vfs;
 918
 919         max_rx_rings = bnxt_max_rings(bp);
 920         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 921         dev_info->max_rx_queues = max_rx_rings;
 922         dev_info->max_tx_queues = max_rx_rings;
 923         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 924         dev_info->hash_key_size = 40;
 925         max_vnics = bp->max_vnics;
 926
 927         /* MTU specifics */
 928         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 929         dev_info->max_mtu = BNXT_MAX_MTU;
 930
 931         /* Fast path specifics */
 932         dev_info->min_rx_bufsize = 1;
 933         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 934
 935         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 936         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 937                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 938         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 939         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 940                                     dev_info->tx_queue_offload_capa;
 941         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 942
 943         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 944
 945         /* *INDENT-OFF* */
 946         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 947                 .rx_thresh = {
 948                         .pthresh = 8,
 949                         .hthresh = 8,
 950                         .wthresh = 0,
 951                 },
 952                 .rx_free_thresh = 32,
 953                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 954         };
 955
 956         dev_info->default_txconf = (struct rte_eth_txconf) {
 957                 .tx_thresh = {
 958                         .pthresh = 32,
 959                         .hthresh = 0,
 960                         .wthresh = 0,
 961                 },
 962                 .tx_free_thresh = 32,
 963                 .tx_rs_thresh = 32,
 964         };
 965         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 966
 967         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 968         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 969         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 970         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 971         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 972
 973         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 974                 dev_info->switch_info.name = eth_dev->device->name;
 975                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 976                 dev_info->switch_info.port_id =
 977                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 978                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 979         }
 980
 981         /* *INDENT-ON* */
 982
 983         /*
 984          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 985          *       need further investigation.
 986          */
 987
 988         /* VMDq resources */
 989         vpool = 64; /* ETH_64_POOLS */
 990         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 991         for (i = 0; i < 4; vpool >>= 1, i++) {
 992                 if (max_vnics > vpool) {
 993                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 994                                 if (dev_info->max_rx_queues > vrxq) {
 995                                         if (vpool > vrxq)
 996                                                 vpool = vrxq;
 997                                         goto found;
 998                                 }
 999                         }
1000                         /* Not enough resources to support VMDq */
1001                         break;
1002                 }
1003         }
1004         /* Not enough resources to support VMDq */
1005         vpool = 0;
1006         vrxq = 0;
1007 found:
1008         dev_info->max_vmdq_pools = vpool;
1009         dev_info->vmdq_queue_num = vrxq;
1010
1011         dev_info->vmdq_pool_base = 0;
1012         dev_info->vmdq_queue_base = 0;
1013
1014         return 0;
1015 }
1016
1017 /* Configure the device based on the configuration provided */
1018 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1019 {
1020         struct bnxt *bp = eth_dev->data->dev_private;
1021         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1022         int rc;
1023
1024         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1025         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1026         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1027         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1028
1029         rc = is_bnxt_in_error(bp);
1030         if (rc)
1031                 return rc;
1032
1033         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1034                 rc = bnxt_hwrm_check_vf_rings(bp);
1035                 if (rc) {
1036                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1037                         return -ENOSPC;
1038                 }
1039
1040                 /* If a resource has already been allocated - in this case
1041                  * it is the async completion ring, free it. Reallocate it after
1042                  * resource reservation. This will ensure the resource counts
1043                  * are calculated correctly.
1044                  */
1045
1046                 pthread_mutex_lock(&bp->def_cp_lock);
1047
1048                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1049                         bnxt_disable_int(bp);
1050                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1051                 }
1052
1053                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1054                 if (rc) {
1055                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1056                         pthread_mutex_unlock(&bp->def_cp_lock);
1057                         return -ENOSPC;
1058                 }
1059
1060                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1061                         rc = bnxt_alloc_async_cp_ring(bp);
1062                         if (rc) {
1063                                 pthread_mutex_unlock(&bp->def_cp_lock);
1064                                 return rc;
1065                         }
1066                         bnxt_enable_int(bp);
1067                 }
1068
1069                 pthread_mutex_unlock(&bp->def_cp_lock);
1070         }
1071
1072         /* Inherit new configurations */
1073         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1074             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1075             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1076                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1077             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1078             bp->max_stat_ctx)
1079                 goto resource_error;
1080
1081         if (BNXT_HAS_RING_GRPS(bp) &&
1082             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1083                 goto resource_error;
1084
1085         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1086             bp->max_vnics < eth_dev->data->nb_rx_queues)
1087                 goto resource_error;
1088
1089         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1090         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1091
1092         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1093                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1094         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1095
1096         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1097                 eth_dev->data->mtu =
1098                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1099                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1100                         BNXT_NUM_VLANS;
1101                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1102         }
1103         return 0;
1104
1105 resource_error:
1106         PMD_DRV_LOG(ERR,
1107                     "Insufficient resources to support requested config\n");
1108         PMD_DRV_LOG(ERR,
1109                     "Num Queues Requested: Tx %d, Rx %d\n",
1110                     eth_dev->data->nb_tx_queues,
1111                     eth_dev->data->nb_rx_queues);
1112         PMD_DRV_LOG(ERR,
1113                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1114                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1115                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1116         return -ENOSPC;
1117 }
1118
1119 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1120 {
1121         struct rte_eth_link *link = &eth_dev->data->dev_link;
1122
1123         if (link->link_status)
1124                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1125                         eth_dev->data->port_id,
1126                         (uint32_t)link->link_speed,
1127                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1128                         ("full-duplex") : ("half-duplex\n"));
1129         else
1130                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1131                         eth_dev->data->port_id);
1132 }
1133
1134 /*
1135  * Determine whether the current configuration requires support for scattered
1136  * receive; return 1 if scattered receive is required and 0 if not.
1137  */
1138 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1139 {
1140         uint16_t buf_size;
1141         int i;
1142
1143         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1144                 return 1;
1145
1146         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1147                 return 1;
1148
1149         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1150                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1151
1152                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1153                                       RTE_PKTMBUF_HEADROOM);
1154                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1155                         return 1;
1156         }
1157         return 0;
1158 }
1159
1160 static eth_rx_burst_t
1161 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1162 {
1163         struct bnxt *bp = eth_dev->data->dev_private;
1164
1165         /* Disable vector mode RX for Stingray2 for now */
1166         if (BNXT_CHIP_SR2(bp)) {
1167                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1168                 return bnxt_recv_pkts;
1169         }
1170
1171 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1172 #ifndef RTE_LIBRTE_IEEE1588
1173         /*
1174          * Vector mode receive can be enabled only if scatter rx is not
1175          * in use and rx offloads are limited to VLAN stripping and
1176          * CRC stripping.
1177          */
1178         if (!eth_dev->data->scattered_rx &&
1179             !(eth_dev->data->dev_conf.rxmode.offloads &
1180               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1181                 DEV_RX_OFFLOAD_KEEP_CRC |
1182                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1183                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1184                 DEV_RX_OFFLOAD_UDP_CKSUM |
1185                 DEV_RX_OFFLOAD_TCP_CKSUM |
1186                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1187                 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1188                 DEV_RX_OFFLOAD_RSS_HASH |
1189                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1190             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1191             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1192                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1193                             eth_dev->data->port_id);
1194                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1195                 return bnxt_recv_pkts_vec;
1196         }
1197         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1198                     eth_dev->data->port_id);
1199         PMD_DRV_LOG(INFO,
1200                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1201                     eth_dev->data->port_id,
1202                     eth_dev->data->scattered_rx,
1203                     eth_dev->data->dev_conf.rxmode.offloads);
1204 #endif
1205 #endif
1206         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1207         return bnxt_recv_pkts;
1208 }
1209
1210 static eth_tx_burst_t
1211 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1212 {
1213         struct bnxt *bp = eth_dev->data->dev_private;
1214
1215         /* Disable vector mode TX for Stingray2 for now */
1216         if (BNXT_CHIP_SR2(bp))
1217                 return bnxt_xmit_pkts;
1218
1219 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1220 #ifndef RTE_LIBRTE_IEEE1588
1221         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1222
1223         /*
1224          * Vector mode transmit can be enabled only if not using scatter rx
1225          * or tx offloads.
1226          */
1227         if (!eth_dev->data->scattered_rx &&
1228             !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1229             !BNXT_TRUFLOW_EN(bp) &&
1230             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1231                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1232                             eth_dev->data->port_id);
1233                 return bnxt_xmit_pkts_vec;
1234         }
1235         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1236                     eth_dev->data->port_id);
1237         PMD_DRV_LOG(INFO,
1238                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1239                     eth_dev->data->port_id,
1240                     eth_dev->data->scattered_rx,
1241                     offloads);
1242 #endif
1243 #endif
1244         return bnxt_xmit_pkts;
1245 }
1246
1247 static int bnxt_handle_if_change_status(struct bnxt *bp)
1248 {
1249         int rc;
1250
1251         /* Since fw has undergone a reset and lost all contexts,
1252          * set fatal flag to not issue hwrm during cleanup
1253          */
1254         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1255         bnxt_uninit_resources(bp, true);
1256
1257         /* clear fatal flag so that re-init happens */
1258         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1259         rc = bnxt_init_resources(bp, true);
1260
1261         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1262
1263         return rc;
1264 }
1265
1266 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1267 {
1268         struct bnxt *bp = eth_dev->data->dev_private;
1269         int rc = 0;
1270
1271         if (!bp->link_info->link_up)
1272                 rc = bnxt_set_hwrm_link_config(bp, true);
1273         if (!rc)
1274                 eth_dev->data->dev_link.link_status = 1;
1275
1276         bnxt_print_link_info(eth_dev);
1277         return rc;
1278 }
1279
1280 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1281 {
1282         struct bnxt *bp = eth_dev->data->dev_private;
1283
1284         eth_dev->data->dev_link.link_status = 0;
1285         bnxt_set_hwrm_link_config(bp, false);
1286         bp->link_info->link_up = 0;
1287
1288         return 0;
1289 }
1290
1291 static void bnxt_free_switch_domain(struct bnxt *bp)
1292 {
1293         int rc = 0;
1294
1295         if (bp->switch_domain_id) {
1296                 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1297                 if (rc)
1298                         PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1299                                     bp->switch_domain_id, rc);
1300         }
1301 }
1302
1303 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1304 {
1305         struct bnxt *bp = eth_dev->data->dev_private;
1306         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1307         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1308         struct rte_eth_link link;
1309         int ret;
1310
1311         eth_dev->data->dev_started = 0;
1312         eth_dev->data->scattered_rx = 0;
1313
1314         /* Prevent crashes when queues are still in use */
1315         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1316         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1317
1318         bnxt_disable_int(bp);
1319
1320         /* disable uio/vfio intr/eventfd mapping */
1321         rte_intr_disable(intr_handle);
1322
1323         /* Stop the child representors for this device */
1324         ret = bnxt_rep_stop_all(bp);
1325         if (ret != 0)
1326                 return ret;
1327
1328         /* delete the bnxt ULP port details */
1329         bnxt_ulp_port_deinit(bp);
1330
1331         bnxt_cancel_fw_health_check(bp);
1332
1333         /* Do not bring link down during reset recovery */
1334         if (!is_bnxt_in_error(bp)) {
1335                 bnxt_dev_set_link_down_op(eth_dev);
1336                 /* Wait for link to be reset */
1337                 if (BNXT_SINGLE_PF(bp))
1338                         rte_delay_ms(500);
1339                 /* clear the recorded link status */
1340                 memset(&link, 0, sizeof(link));
1341                 rte_eth_linkstatus_set(eth_dev, &link);
1342         }
1343
1344         /* Clean queue intr-vector mapping */
1345         rte_intr_efd_disable(intr_handle);
1346         if (intr_handle->intr_vec != NULL) {
1347                 rte_free(intr_handle->intr_vec);
1348                 intr_handle->intr_vec = NULL;
1349         }
1350
1351         bnxt_hwrm_port_clr_stats(bp);
1352         bnxt_free_tx_mbufs(bp);
1353         bnxt_free_rx_mbufs(bp);
1354         /* Process any remaining notifications in default completion queue */
1355         bnxt_int_handler(eth_dev);
1356         bnxt_shutdown_nic(bp);
1357         bnxt_hwrm_if_change(bp, false);
1358
1359         rte_free(bp->mark_table);
1360         bp->mark_table = NULL;
1361
1362         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1363         bp->rx_cosq_cnt = 0;
1364         /* All filters are deleted on a port stop. */
1365         if (BNXT_FLOW_XSTATS_EN(bp))
1366                 bp->flow_stat->flow_count = 0;
1367
1368         return 0;
1369 }
1370
1371 /* Unload the driver, release resources */
1372 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1373 {
1374         struct bnxt *bp = eth_dev->data->dev_private;
1375
1376         pthread_mutex_lock(&bp->err_recovery_lock);
1377         if (bp->flags & BNXT_FLAG_FW_RESET) {
1378                 PMD_DRV_LOG(ERR,
1379                             "Adapter recovering from error..Please retry\n");
1380                 pthread_mutex_unlock(&bp->err_recovery_lock);
1381                 return -EAGAIN;
1382         }
1383         pthread_mutex_unlock(&bp->err_recovery_lock);
1384
1385         return bnxt_dev_stop(eth_dev);
1386 }
1387
1388 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1389 {
1390         struct bnxt *bp = eth_dev->data->dev_private;
1391         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1392         int vlan_mask = 0;
1393         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1394
1395         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1396                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1397                 return -EINVAL;
1398         }
1399
1400         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1401                 PMD_DRV_LOG(ERR,
1402                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1403                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1404
1405         do {
1406                 rc = bnxt_hwrm_if_change(bp, true);
1407                 if (rc == 0 || rc != -EAGAIN)
1408                         break;
1409
1410                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1411         } while (retry_cnt--);
1412
1413         if (rc)
1414                 return rc;
1415
1416         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1417                 rc = bnxt_handle_if_change_status(bp);
1418                 if (rc)
1419                         return rc;
1420         }
1421
1422         bnxt_enable_int(bp);
1423
1424         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1425
1426         rc = bnxt_start_nic(bp);
1427         if (rc)
1428                 goto error;
1429
1430         eth_dev->data->dev_started = 1;
1431
1432         bnxt_link_update_op(eth_dev, 1);
1433
1434         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1435                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1436         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1437                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1438         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1439         if (rc)
1440                 goto error;
1441
1442         /* Initialize bnxt ULP port details */
1443         rc = bnxt_ulp_port_init(bp);
1444         if (rc)
1445                 goto error;
1446
1447         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1448         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1449
1450         bnxt_schedule_fw_health_check(bp);
1451
1452         return 0;
1453
1454 error:
1455         bnxt_dev_stop(eth_dev);
1456         return rc;
1457 }
1458
1459 static void
1460 bnxt_uninit_locks(struct bnxt *bp)
1461 {
1462         pthread_mutex_destroy(&bp->flow_lock);
1463         pthread_mutex_destroy(&bp->def_cp_lock);
1464         pthread_mutex_destroy(&bp->health_check_lock);
1465         pthread_mutex_destroy(&bp->err_recovery_lock);
1466         if (bp->rep_info) {
1467                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1468                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1469         }
1470 }
1471
1472 static void bnxt_drv_uninit(struct bnxt *bp)
1473 {
1474         bnxt_free_switch_domain(bp);
1475         bnxt_free_leds_info(bp);
1476         bnxt_free_cos_queues(bp);
1477         bnxt_free_link_info(bp);
1478         bnxt_free_pf_info(bp);
1479         bnxt_free_parent_info(bp);
1480         bnxt_uninit_locks(bp);
1481
1482         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1483         bp->tx_mem_zone = NULL;
1484         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1485         bp->rx_mem_zone = NULL;
1486
1487         bnxt_hwrm_free_vf_info(bp);
1488
1489         rte_free(bp->grp_info);
1490         bp->grp_info = NULL;
1491 }
1492
1493 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1494 {
1495         struct bnxt *bp = eth_dev->data->dev_private;
1496         int ret = 0;
1497
1498         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1499                 return 0;
1500
1501         pthread_mutex_lock(&bp->err_recovery_lock);
1502         if (bp->flags & BNXT_FLAG_FW_RESET) {
1503                 PMD_DRV_LOG(ERR,
1504                             "Adapter recovering from error...Please retry\n");
1505                 pthread_mutex_unlock(&bp->err_recovery_lock);
1506                 return -EAGAIN;
1507         }
1508         pthread_mutex_unlock(&bp->err_recovery_lock);
1509
1510         /* cancel the recovery handler before remove dev */
1511         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1512         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1513         bnxt_cancel_fc_thread(bp);
1514
1515         if (eth_dev->data->dev_started)
1516                 ret = bnxt_dev_stop(eth_dev);
1517
1518         bnxt_uninit_resources(bp, false);
1519
1520         bnxt_drv_uninit(bp);
1521
1522         return ret;
1523 }
1524
1525 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1526                                     uint32_t index)
1527 {
1528         struct bnxt *bp = eth_dev->data->dev_private;
1529         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1530         struct bnxt_vnic_info *vnic;
1531         struct bnxt_filter_info *filter, *temp_filter;
1532         uint32_t i;
1533
1534         if (is_bnxt_in_error(bp))
1535                 return;
1536
1537         /*
1538          * Loop through all VNICs from the specified filter flow pools to
1539          * remove the corresponding MAC addr filter
1540          */
1541         for (i = 0; i < bp->nr_vnics; i++) {
1542                 if (!(pool_mask & (1ULL << i)))
1543                         continue;
1544
1545                 vnic = &bp->vnic_info[i];
1546                 filter = STAILQ_FIRST(&vnic->filter);
1547                 while (filter) {
1548                         temp_filter = STAILQ_NEXT(filter, next);
1549                         if (filter->mac_index == index) {
1550                                 STAILQ_REMOVE(&vnic->filter, filter,
1551                                                 bnxt_filter_info, next);
1552                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1553                                 bnxt_free_filter(bp, filter);
1554                         }
1555                         filter = temp_filter;
1556                 }
1557         }
1558 }
1559
1560 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1561                                struct rte_ether_addr *mac_addr, uint32_t index,
1562                                uint32_t pool)
1563 {
1564         struct bnxt_filter_info *filter;
1565         int rc = 0;
1566
1567         /* Attach requested MAC address to the new l2_filter */
1568         STAILQ_FOREACH(filter, &vnic->filter, next) {
1569                 if (filter->mac_index == index) {
1570                         PMD_DRV_LOG(DEBUG,
1571                                     "MAC addr already existed for pool %d\n",
1572                                     pool);
1573                         return 0;
1574                 }
1575         }
1576
1577         filter = bnxt_alloc_filter(bp);
1578         if (!filter) {
1579                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1580                 return -ENODEV;
1581         }
1582
1583         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1584          * if the MAC that's been programmed now is a different one, then,
1585          * copy that addr to filter->l2_addr
1586          */
1587         if (mac_addr)
1588                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1589         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1590
1591         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1592         if (!rc) {
1593                 filter->mac_index = index;
1594                 if (filter->mac_index == 0)
1595                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1596                 else
1597                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1598         } else {
1599                 bnxt_free_filter(bp, filter);
1600         }
1601
1602         return rc;
1603 }
1604
1605 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1606                                 struct rte_ether_addr *mac_addr,
1607                                 uint32_t index, uint32_t pool)
1608 {
1609         struct bnxt *bp = eth_dev->data->dev_private;
1610         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1611         int rc = 0;
1612
1613         rc = is_bnxt_in_error(bp);
1614         if (rc)
1615                 return rc;
1616
1617         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1618                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1619                 return -ENOTSUP;
1620         }
1621
1622         if (!vnic) {
1623                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1624                 return -EINVAL;
1625         }
1626
1627         /* Filter settings will get applied when port is started */
1628         if (!eth_dev->data->dev_started)
1629                 return 0;
1630
1631         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1632
1633         return rc;
1634 }
1635
1636 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1637 {
1638         int rc = 0;
1639         struct bnxt *bp = eth_dev->data->dev_private;
1640         struct rte_eth_link new;
1641         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1642                         BNXT_MIN_LINK_WAIT_CNT;
1643
1644         rc = is_bnxt_in_error(bp);
1645         if (rc)
1646                 return rc;
1647
1648         memset(&new, 0, sizeof(new));
1649         do {
1650                 /* Retrieve link info from hardware */
1651                 rc = bnxt_get_hwrm_link_config(bp, &new);
1652                 if (rc) {
1653                         new.link_speed = ETH_LINK_SPEED_100M;
1654                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1655                         PMD_DRV_LOG(ERR,
1656                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1657                         goto out;
1658                 }
1659
1660                 if (!wait_to_complete || new.link_status)
1661                         break;
1662
1663                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1664         } while (cnt--);
1665
1666         /* Only single function PF can bring phy down.
1667          * When port is stopped, report link down for VF/MH/NPAR functions.
1668          */
1669         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1670                 memset(&new, 0, sizeof(new));
1671
1672 out:
1673         /* Timed out or success */
1674         if (new.link_status != eth_dev->data->dev_link.link_status ||
1675             new.link_speed != eth_dev->data->dev_link.link_speed) {
1676                 rte_eth_linkstatus_set(eth_dev, &new);
1677
1678                 rte_eth_dev_callback_process(eth_dev,
1679                                              RTE_ETH_EVENT_INTR_LSC,
1680                                              NULL);
1681
1682                 bnxt_print_link_info(eth_dev);
1683         }
1684
1685         return rc;
1686 }
1687
1688 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1689 {
1690         struct bnxt *bp = eth_dev->data->dev_private;
1691         struct bnxt_vnic_info *vnic;
1692         uint32_t old_flags;
1693         int rc;
1694
1695         rc = is_bnxt_in_error(bp);
1696         if (rc)
1697                 return rc;
1698
1699         /* Filter settings will get applied when port is started */
1700         if (!eth_dev->data->dev_started)
1701                 return 0;
1702
1703         if (bp->vnic_info == NULL)
1704                 return 0;
1705
1706         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1707
1708         old_flags = vnic->flags;
1709         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1710         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1711         if (rc != 0)
1712                 vnic->flags = old_flags;
1713
1714         return rc;
1715 }
1716
1717 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1718 {
1719         struct bnxt *bp = eth_dev->data->dev_private;
1720         struct bnxt_vnic_info *vnic;
1721         uint32_t old_flags;
1722         int rc;
1723
1724         rc = is_bnxt_in_error(bp);
1725         if (rc)
1726                 return rc;
1727
1728         /* Filter settings will get applied when port is started */
1729         if (!eth_dev->data->dev_started)
1730                 return 0;
1731
1732         if (bp->vnic_info == NULL)
1733                 return 0;
1734
1735         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1736
1737         old_flags = vnic->flags;
1738         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1739         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1740         if (rc != 0)
1741                 vnic->flags = old_flags;
1742
1743         return rc;
1744 }
1745
1746 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1747 {
1748         struct bnxt *bp = eth_dev->data->dev_private;
1749         struct bnxt_vnic_info *vnic;
1750         uint32_t old_flags;
1751         int rc;
1752
1753         rc = is_bnxt_in_error(bp);
1754         if (rc)
1755                 return rc;
1756
1757         /* Filter settings will get applied when port is started */
1758         if (!eth_dev->data->dev_started)
1759                 return 0;
1760
1761         if (bp->vnic_info == NULL)
1762                 return 0;
1763
1764         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1765
1766         old_flags = vnic->flags;
1767         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1768         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1769         if (rc != 0)
1770                 vnic->flags = old_flags;
1771
1772         return rc;
1773 }
1774
1775 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1776 {
1777         struct bnxt *bp = eth_dev->data->dev_private;
1778         struct bnxt_vnic_info *vnic;
1779         uint32_t old_flags;
1780         int rc;
1781
1782         rc = is_bnxt_in_error(bp);
1783         if (rc)
1784                 return rc;
1785
1786         /* Filter settings will get applied when port is started */
1787         if (!eth_dev->data->dev_started)
1788                 return 0;
1789
1790         if (bp->vnic_info == NULL)
1791                 return 0;
1792
1793         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1794
1795         old_flags = vnic->flags;
1796         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1797         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1798         if (rc != 0)
1799                 vnic->flags = old_flags;
1800
1801         return rc;
1802 }
1803
1804 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1805 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1806 {
1807         if (qid >= bp->rx_nr_rings)
1808                 return NULL;
1809
1810         return bp->eth_dev->data->rx_queues[qid];
1811 }
1812
1813 /* Return rxq corresponding to a given rss table ring/group ID. */
1814 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1815 {
1816         struct bnxt_rx_queue *rxq;
1817         unsigned int i;
1818
1819         if (!BNXT_HAS_RING_GRPS(bp)) {
1820                 for (i = 0; i < bp->rx_nr_rings; i++) {
1821                         rxq = bp->eth_dev->data->rx_queues[i];
1822                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1823                                 return rxq->index;
1824                 }
1825         } else {
1826                 for (i = 0; i < bp->rx_nr_rings; i++) {
1827                         if (bp->grp_info[i].fw_grp_id == fwr)
1828                                 return i;
1829                 }
1830         }
1831
1832         return INVALID_HW_RING_ID;
1833 }
1834
1835 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1836                             struct rte_eth_rss_reta_entry64 *reta_conf,
1837                             uint16_t reta_size)
1838 {
1839         struct bnxt *bp = eth_dev->data->dev_private;
1840         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1841         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1842         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1843         uint16_t idx, sft;
1844         int i, rc;
1845
1846         rc = is_bnxt_in_error(bp);
1847         if (rc)
1848                 return rc;
1849
1850         if (!vnic->rss_table)
1851                 return -EINVAL;
1852
1853         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1854                 return -EINVAL;
1855
1856         if (reta_size != tbl_size) {
1857                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1858                         "(%d) must equal the size supported by the hardware "
1859                         "(%d)\n", reta_size, tbl_size);
1860                 return -EINVAL;
1861         }
1862
1863         for (i = 0; i < reta_size; i++) {
1864                 struct bnxt_rx_queue *rxq;
1865
1866                 idx = i / RTE_RETA_GROUP_SIZE;
1867                 sft = i % RTE_RETA_GROUP_SIZE;
1868
1869                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1870                         continue;
1871
1872                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1873                 if (!rxq) {
1874                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1875                         return -EINVAL;
1876                 }
1877
1878                 if (BNXT_CHIP_P5(bp)) {
1879                         vnic->rss_table[i * 2] =
1880                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1881                         vnic->rss_table[i * 2 + 1] =
1882                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1883                 } else {
1884                         vnic->rss_table[i] =
1885                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1886                 }
1887         }
1888
1889         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1890         return rc;
1891 }
1892
1893 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1894                               struct rte_eth_rss_reta_entry64 *reta_conf,
1895                               uint16_t reta_size)
1896 {
1897         struct bnxt *bp = eth_dev->data->dev_private;
1898         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1899         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1900         uint16_t idx, sft, i;
1901         int rc;
1902
1903         rc = is_bnxt_in_error(bp);
1904         if (rc)
1905                 return rc;
1906
1907         /* Retrieve from the default VNIC */
1908         if (!vnic)
1909                 return -EINVAL;
1910         if (!vnic->rss_table)
1911                 return -EINVAL;
1912
1913         if (reta_size != tbl_size) {
1914                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1915                         "(%d) must equal the size supported by the hardware "
1916                         "(%d)\n", reta_size, tbl_size);
1917                 return -EINVAL;
1918         }
1919
1920         for (idx = 0, i = 0; i < reta_size; i++) {
1921                 idx = i / RTE_RETA_GROUP_SIZE;
1922                 sft = i % RTE_RETA_GROUP_SIZE;
1923
1924                 if (reta_conf[idx].mask & (1ULL << sft)) {
1925                         uint16_t qid;
1926
1927                         if (BNXT_CHIP_P5(bp))
1928                                 qid = bnxt_rss_to_qid(bp,
1929                                                       vnic->rss_table[i * 2]);
1930                         else
1931                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1932
1933                         if (qid == INVALID_HW_RING_ID) {
1934                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1935                                 return -EINVAL;
1936                         }
1937                         reta_conf[idx].reta[sft] = qid;
1938                 }
1939         }
1940
1941         return 0;
1942 }
1943
1944 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1945                                    struct rte_eth_rss_conf *rss_conf)
1946 {
1947         struct bnxt *bp = eth_dev->data->dev_private;
1948         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1949         struct bnxt_vnic_info *vnic;
1950         int rc;
1951
1952         rc = is_bnxt_in_error(bp);
1953         if (rc)
1954                 return rc;
1955
1956         /*
1957          * If RSS enablement were different than dev_configure,
1958          * then return -EINVAL
1959          */
1960         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1961                 if (!rss_conf->rss_hf)
1962                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1963         } else {
1964                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1965                         return -EINVAL;
1966         }
1967
1968         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1969         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1970                rss_conf,
1971                sizeof(*rss_conf));
1972
1973         /* Update the default RSS VNIC(s) */
1974         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1975         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1976         vnic->hash_mode =
1977                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1978                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
1979
1980         /*
1981          * If hashkey is not specified, use the previously configured
1982          * hashkey
1983          */
1984         if (!rss_conf->rss_key)
1985                 goto rss_config;
1986
1987         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1988                 PMD_DRV_LOG(ERR,
1989                             "Invalid hashkey length, should be 16 bytes\n");
1990                 return -EINVAL;
1991         }
1992         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1993
1994 rss_config:
1995         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1996         return rc;
1997 }
1998
1999 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2000                                      struct rte_eth_rss_conf *rss_conf)
2001 {
2002         struct bnxt *bp = eth_dev->data->dev_private;
2003         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2004         int len, rc;
2005         uint32_t hash_types;
2006
2007         rc = is_bnxt_in_error(bp);
2008         if (rc)
2009                 return rc;
2010
2011         /* RSS configuration is the same for all VNICs */
2012         if (vnic && vnic->rss_hash_key) {
2013                 if (rss_conf->rss_key) {
2014                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2015                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2016                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2017                 }
2018
2019                 hash_types = vnic->hash_type;
2020                 rss_conf->rss_hf = 0;
2021                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2022                         rss_conf->rss_hf |= ETH_RSS_IPV4;
2023                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2024                 }
2025                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2026                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2027                         hash_types &=
2028                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2029                 }
2030                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2031                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2032                         hash_types &=
2033                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2034                 }
2035                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2036                         rss_conf->rss_hf |= ETH_RSS_IPV6;
2037                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2038                 }
2039                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2040                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2041                         hash_types &=
2042                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2043                 }
2044                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2045                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2046                         hash_types &=
2047                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2048                 }
2049
2050                 rss_conf->rss_hf |=
2051                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2052
2053                 if (hash_types) {
2054                         PMD_DRV_LOG(ERR,
2055                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2056                                 vnic->hash_type);
2057                         return -ENOTSUP;
2058                 }
2059         } else {
2060                 rss_conf->rss_hf = 0;
2061         }
2062         return 0;
2063 }
2064
2065 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2066                                struct rte_eth_fc_conf *fc_conf)
2067 {
2068         struct bnxt *bp = dev->data->dev_private;
2069         struct rte_eth_link link_info;
2070         int rc;
2071
2072         rc = is_bnxt_in_error(bp);
2073         if (rc)
2074                 return rc;
2075
2076         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2077         if (rc)
2078                 return rc;
2079
2080         memset(fc_conf, 0, sizeof(*fc_conf));
2081         if (bp->link_info->auto_pause)
2082                 fc_conf->autoneg = 1;
2083         switch (bp->link_info->pause) {
2084         case 0:
2085                 fc_conf->mode = RTE_FC_NONE;
2086                 break;
2087         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2088                 fc_conf->mode = RTE_FC_TX_PAUSE;
2089                 break;
2090         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2091                 fc_conf->mode = RTE_FC_RX_PAUSE;
2092                 break;
2093         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2094                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2095                 fc_conf->mode = RTE_FC_FULL;
2096                 break;
2097         }
2098         return 0;
2099 }
2100
2101 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2102                                struct rte_eth_fc_conf *fc_conf)
2103 {
2104         struct bnxt *bp = dev->data->dev_private;
2105         int rc;
2106
2107         rc = is_bnxt_in_error(bp);
2108         if (rc)
2109                 return rc;
2110
2111         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2112                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2113                 return -ENOTSUP;
2114         }
2115
2116         switch (fc_conf->mode) {
2117         case RTE_FC_NONE:
2118                 bp->link_info->auto_pause = 0;
2119                 bp->link_info->force_pause = 0;
2120                 break;
2121         case RTE_FC_RX_PAUSE:
2122                 if (fc_conf->autoneg) {
2123                         bp->link_info->auto_pause =
2124                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2125                         bp->link_info->force_pause = 0;
2126                 } else {
2127                         bp->link_info->auto_pause = 0;
2128                         bp->link_info->force_pause =
2129                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2130                 }
2131                 break;
2132         case RTE_FC_TX_PAUSE:
2133                 if (fc_conf->autoneg) {
2134                         bp->link_info->auto_pause =
2135                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2136                         bp->link_info->force_pause = 0;
2137                 } else {
2138                         bp->link_info->auto_pause = 0;
2139                         bp->link_info->force_pause =
2140                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2141                 }
2142                 break;
2143         case RTE_FC_FULL:
2144                 if (fc_conf->autoneg) {
2145                         bp->link_info->auto_pause =
2146                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2147                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2148                         bp->link_info->force_pause = 0;
2149                 } else {
2150                         bp->link_info->auto_pause = 0;
2151                         bp->link_info->force_pause =
2152                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2153                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2154                 }
2155                 break;
2156         }
2157         return bnxt_set_hwrm_link_config(bp, true);
2158 }
2159
2160 /* Add UDP tunneling port */
2161 static int
2162 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2163                          struct rte_eth_udp_tunnel *udp_tunnel)
2164 {
2165         struct bnxt *bp = eth_dev->data->dev_private;
2166         uint16_t tunnel_type = 0;
2167         int rc = 0;
2168
2169         rc = is_bnxt_in_error(bp);
2170         if (rc)
2171                 return rc;
2172
2173         switch (udp_tunnel->prot_type) {
2174         case RTE_TUNNEL_TYPE_VXLAN:
2175                 if (bp->vxlan_port_cnt) {
2176                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2177                                 udp_tunnel->udp_port);
2178                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2179                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2180                                 return -ENOSPC;
2181                         }
2182                         bp->vxlan_port_cnt++;
2183                         return 0;
2184                 }
2185                 tunnel_type =
2186                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2187                 bp->vxlan_port_cnt++;
2188                 break;
2189         case RTE_TUNNEL_TYPE_GENEVE:
2190                 if (bp->geneve_port_cnt) {
2191                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2192                                 udp_tunnel->udp_port);
2193                         if (bp->geneve_port != udp_tunnel->udp_port) {
2194                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2195                                 return -ENOSPC;
2196                         }
2197                         bp->geneve_port_cnt++;
2198                         return 0;
2199                 }
2200                 tunnel_type =
2201                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2202                 bp->geneve_port_cnt++;
2203                 break;
2204         default:
2205                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2206                 return -ENOTSUP;
2207         }
2208         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2209                                              tunnel_type);
2210         return rc;
2211 }
2212
2213 static int
2214 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2215                          struct rte_eth_udp_tunnel *udp_tunnel)
2216 {
2217         struct bnxt *bp = eth_dev->data->dev_private;
2218         uint16_t tunnel_type = 0;
2219         uint16_t port = 0;
2220         int rc = 0;
2221
2222         rc = is_bnxt_in_error(bp);
2223         if (rc)
2224                 return rc;
2225
2226         switch (udp_tunnel->prot_type) {
2227         case RTE_TUNNEL_TYPE_VXLAN:
2228                 if (!bp->vxlan_port_cnt) {
2229                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2230                         return -EINVAL;
2231                 }
2232                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2233                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2234                                 udp_tunnel->udp_port, bp->vxlan_port);
2235                         return -EINVAL;
2236                 }
2237                 if (--bp->vxlan_port_cnt)
2238                         return 0;
2239
2240                 tunnel_type =
2241                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2242                 port = bp->vxlan_fw_dst_port_id;
2243                 break;
2244         case RTE_TUNNEL_TYPE_GENEVE:
2245                 if (!bp->geneve_port_cnt) {
2246                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2247                         return -EINVAL;
2248                 }
2249                 if (bp->geneve_port != udp_tunnel->udp_port) {
2250                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2251                                 udp_tunnel->udp_port, bp->geneve_port);
2252                         return -EINVAL;
2253                 }
2254                 if (--bp->geneve_port_cnt)
2255                         return 0;
2256
2257                 tunnel_type =
2258                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2259                 port = bp->geneve_fw_dst_port_id;
2260                 break;
2261         default:
2262                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2263                 return -ENOTSUP;
2264         }
2265
2266         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2267         return rc;
2268 }
2269
2270 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2271 {
2272         struct bnxt_filter_info *filter;
2273         struct bnxt_vnic_info *vnic;
2274         int rc = 0;
2275         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2276
2277         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2278         filter = STAILQ_FIRST(&vnic->filter);
2279         while (filter) {
2280                 /* Search for this matching MAC+VLAN filter */
2281                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2282                         /* Delete the filter */
2283                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2284                         if (rc)
2285                                 return rc;
2286                         STAILQ_REMOVE(&vnic->filter, filter,
2287                                       bnxt_filter_info, next);
2288                         bnxt_free_filter(bp, filter);
2289                         PMD_DRV_LOG(INFO,
2290                                     "Deleted vlan filter for %d\n",
2291                                     vlan_id);
2292                         return 0;
2293                 }
2294                 filter = STAILQ_NEXT(filter, next);
2295         }
2296         return -ENOENT;
2297 }
2298
2299 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2300 {
2301         struct bnxt_filter_info *filter;
2302         struct bnxt_vnic_info *vnic;
2303         int rc = 0;
2304         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2305                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2306         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2307
2308         /* Implementation notes on the use of VNIC in this command:
2309          *
2310          * By default, these filters belong to default vnic for the function.
2311          * Once these filters are set up, only destination VNIC can be modified.
2312          * If the destination VNIC is not specified in this command,
2313          * then the HWRM shall only create an l2 context id.
2314          */
2315
2316         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2317         filter = STAILQ_FIRST(&vnic->filter);
2318         /* Check if the VLAN has already been added */
2319         while (filter) {
2320                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2321                         return -EEXIST;
2322
2323                 filter = STAILQ_NEXT(filter, next);
2324         }
2325
2326         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2327          * command to create MAC+VLAN filter with the right flags, enables set.
2328          */
2329         filter = bnxt_alloc_filter(bp);
2330         if (!filter) {
2331                 PMD_DRV_LOG(ERR,
2332                             "MAC/VLAN filter alloc failed\n");
2333                 return -ENOMEM;
2334         }
2335         /* MAC + VLAN ID filter */
2336         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2337          * untagged packets are received
2338          *
2339          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2340          * packets and only the programmed vlan's packets are received
2341          */
2342         filter->l2_ivlan = vlan_id;
2343         filter->l2_ivlan_mask = 0x0FFF;
2344         filter->enables |= en;
2345         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2346
2347         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2348         if (rc) {
2349                 /* Free the newly allocated filter as we were
2350                  * not able to create the filter in hardware.
2351                  */
2352                 bnxt_free_filter(bp, filter);
2353                 return rc;
2354         }
2355
2356         filter->mac_index = 0;
2357         /* Add this new filter to the list */
2358         if (vlan_id == 0)
2359                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2360         else
2361                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2362
2363         PMD_DRV_LOG(INFO,
2364                     "Added Vlan filter for %d\n", vlan_id);
2365         return rc;
2366 }
2367
2368 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2369                 uint16_t vlan_id, int on)
2370 {
2371         struct bnxt *bp = eth_dev->data->dev_private;
2372         int rc;
2373
2374         rc = is_bnxt_in_error(bp);
2375         if (rc)
2376                 return rc;
2377
2378         if (!eth_dev->data->dev_started) {
2379                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2380                 return -EINVAL;
2381         }
2382
2383         /* These operations apply to ALL existing MAC/VLAN filters */
2384         if (on)
2385                 return bnxt_add_vlan_filter(bp, vlan_id);
2386         else
2387                 return bnxt_del_vlan_filter(bp, vlan_id);
2388 }
2389
2390 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2391                                     struct bnxt_vnic_info *vnic)
2392 {
2393         struct bnxt_filter_info *filter;
2394         int rc;
2395
2396         filter = STAILQ_FIRST(&vnic->filter);
2397         while (filter) {
2398                 if (filter->mac_index == 0 &&
2399                     !memcmp(filter->l2_addr, bp->mac_addr,
2400                             RTE_ETHER_ADDR_LEN)) {
2401                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2402                         if (!rc) {
2403                                 STAILQ_REMOVE(&vnic->filter, filter,
2404                                               bnxt_filter_info, next);
2405                                 bnxt_free_filter(bp, filter);
2406                         }
2407                         return rc;
2408                 }
2409                 filter = STAILQ_NEXT(filter, next);
2410         }
2411         return 0;
2412 }
2413
2414 static int
2415 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2416 {
2417         struct bnxt_vnic_info *vnic;
2418         unsigned int i;
2419         int rc;
2420
2421         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2422         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2423                 /* Remove any VLAN filters programmed */
2424                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2425                         bnxt_del_vlan_filter(bp, i);
2426
2427                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2428                 if (rc)
2429                         return rc;
2430         } else {
2431                 /* Default filter will allow packets that match the
2432                  * dest mac. So, it has to be deleted, otherwise, we
2433                  * will endup receiving vlan packets for which the
2434                  * filter is not programmed, when hw-vlan-filter
2435                  * configuration is ON
2436                  */
2437                 bnxt_del_dflt_mac_filter(bp, vnic);
2438                 /* This filter will allow only untagged packets */
2439                 bnxt_add_vlan_filter(bp, 0);
2440         }
2441         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2442                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2443
2444         return 0;
2445 }
2446
2447 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2448 {
2449         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2450         unsigned int i;
2451         int rc;
2452
2453         /* Destroy vnic filters and vnic */
2454         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2455             DEV_RX_OFFLOAD_VLAN_FILTER) {
2456                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2457                         bnxt_del_vlan_filter(bp, i);
2458         }
2459         bnxt_del_dflt_mac_filter(bp, vnic);
2460
2461         rc = bnxt_hwrm_vnic_free(bp, vnic);
2462         if (rc)
2463                 return rc;
2464
2465         rte_free(vnic->fw_grp_ids);
2466         vnic->fw_grp_ids = NULL;
2467
2468         vnic->rx_queue_cnt = 0;
2469
2470         return 0;
2471 }
2472
2473 static int
2474 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2475 {
2476         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2477         int rc;
2478
2479         /* Destroy, recreate and reconfigure the default vnic */
2480         rc = bnxt_free_one_vnic(bp, 0);
2481         if (rc)
2482                 return rc;
2483
2484         /* default vnic 0 */
2485         rc = bnxt_setup_one_vnic(bp, 0);
2486         if (rc)
2487                 return rc;
2488
2489         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2490             DEV_RX_OFFLOAD_VLAN_FILTER) {
2491                 rc = bnxt_add_vlan_filter(bp, 0);
2492                 if (rc)
2493                         return rc;
2494                 rc = bnxt_restore_vlan_filters(bp);
2495                 if (rc)
2496                         return rc;
2497         } else {
2498                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2499                 if (rc)
2500                         return rc;
2501         }
2502
2503         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2504         if (rc)
2505                 return rc;
2506
2507         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2508                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2509
2510         return rc;
2511 }
2512
2513 static int
2514 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2515 {
2516         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2517         struct bnxt *bp = dev->data->dev_private;
2518         int rc;
2519
2520         rc = is_bnxt_in_error(bp);
2521         if (rc)
2522                 return rc;
2523
2524         /* Filter settings will get applied when port is started */
2525         if (!dev->data->dev_started)
2526                 return 0;
2527
2528         if (mask & ETH_VLAN_FILTER_MASK) {
2529                 /* Enable or disable VLAN filtering */
2530                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2531                 if (rc)
2532                         return rc;
2533         }
2534
2535         if (mask & ETH_VLAN_STRIP_MASK) {
2536                 /* Enable or disable VLAN stripping */
2537                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2538                 if (rc)
2539                         return rc;
2540         }
2541
2542         if (mask & ETH_VLAN_EXTEND_MASK) {
2543                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2544                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2545                 else
2546                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2547         }
2548
2549         return 0;
2550 }
2551
2552 static int
2553 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2554                       uint16_t tpid)
2555 {
2556         struct bnxt *bp = dev->data->dev_private;
2557         int qinq = dev->data->dev_conf.rxmode.offloads &
2558                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2559
2560         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2561             vlan_type != ETH_VLAN_TYPE_OUTER) {
2562                 PMD_DRV_LOG(ERR,
2563                             "Unsupported vlan type.");
2564                 return -EINVAL;
2565         }
2566         if (!qinq) {
2567                 PMD_DRV_LOG(ERR,
2568                             "QinQ not enabled. Needs to be ON as we can "
2569                             "accelerate only outer vlan\n");
2570                 return -EINVAL;
2571         }
2572
2573         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2574                 switch (tpid) {
2575                 case RTE_ETHER_TYPE_QINQ:
2576                         bp->outer_tpid_bd =
2577                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2578                                 break;
2579                 case RTE_ETHER_TYPE_VLAN:
2580                         bp->outer_tpid_bd =
2581                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2582                                 break;
2583                 case RTE_ETHER_TYPE_QINQ1:
2584                         bp->outer_tpid_bd =
2585                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2586                                 break;
2587                 case RTE_ETHER_TYPE_QINQ2:
2588                         bp->outer_tpid_bd =
2589                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2590                                 break;
2591                 case RTE_ETHER_TYPE_QINQ3:
2592                         bp->outer_tpid_bd =
2593                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2594                                 break;
2595                 default:
2596                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2597                         return -EINVAL;
2598                 }
2599                 bp->outer_tpid_bd |= tpid;
2600                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2601         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2602                 PMD_DRV_LOG(ERR,
2603                             "Can accelerate only outer vlan in QinQ\n");
2604                 return -EINVAL;
2605         }
2606
2607         return 0;
2608 }
2609
2610 static int
2611 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2612                              struct rte_ether_addr *addr)
2613 {
2614         struct bnxt *bp = dev->data->dev_private;
2615         /* Default Filter is tied to VNIC 0 */
2616         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2617         int rc;
2618
2619         rc = is_bnxt_in_error(bp);
2620         if (rc)
2621                 return rc;
2622
2623         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2624                 return -EPERM;
2625
2626         if (rte_is_zero_ether_addr(addr))
2627                 return -EINVAL;
2628
2629         /* Filter settings will get applied when port is started */
2630         if (!dev->data->dev_started)
2631                 return 0;
2632
2633         /* Check if the requested MAC is already added */
2634         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2635                 return 0;
2636
2637         /* Destroy filter and re-create it */
2638         bnxt_del_dflt_mac_filter(bp, vnic);
2639
2640         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2641         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2642                 /* This filter will allow only untagged packets */
2643                 rc = bnxt_add_vlan_filter(bp, 0);
2644         } else {
2645                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2646         }
2647
2648         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2649         return rc;
2650 }
2651
2652 static int
2653 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2654                           struct rte_ether_addr *mc_addr_set,
2655                           uint32_t nb_mc_addr)
2656 {
2657         struct bnxt *bp = eth_dev->data->dev_private;
2658         char *mc_addr_list = (char *)mc_addr_set;
2659         struct bnxt_vnic_info *vnic;
2660         uint32_t off = 0, i = 0;
2661         int rc;
2662
2663         rc = is_bnxt_in_error(bp);
2664         if (rc)
2665                 return rc;
2666
2667         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2668
2669         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2670                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2671                 goto allmulti;
2672         }
2673
2674         /* TODO Check for Duplicate mcast addresses */
2675         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2676         for (i = 0; i < nb_mc_addr; i++) {
2677                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2678                         RTE_ETHER_ADDR_LEN);
2679                 off += RTE_ETHER_ADDR_LEN;
2680         }
2681
2682         vnic->mc_addr_cnt = i;
2683         if (vnic->mc_addr_cnt)
2684                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2685         else
2686                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2687
2688 allmulti:
2689         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2690 }
2691
2692 static int
2693 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2694 {
2695         struct bnxt *bp = dev->data->dev_private;
2696         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2697         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2698         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2699         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2700         int ret;
2701
2702         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2703                         fw_major, fw_minor, fw_updt, fw_rsvd);
2704
2705         ret += 1; /* add the size of '\0' */
2706         if (fw_size < (uint32_t)ret)
2707                 return ret;
2708         else
2709                 return 0;
2710 }
2711
2712 static void
2713 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2714         struct rte_eth_rxq_info *qinfo)
2715 {
2716         struct bnxt *bp = dev->data->dev_private;
2717         struct bnxt_rx_queue *rxq;
2718
2719         if (is_bnxt_in_error(bp))
2720                 return;
2721
2722         rxq = dev->data->rx_queues[queue_id];
2723
2724         qinfo->mp = rxq->mb_pool;
2725         qinfo->scattered_rx = dev->data->scattered_rx;
2726         qinfo->nb_desc = rxq->nb_rx_desc;
2727
2728         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2729         qinfo->conf.rx_drop_en = rxq->drop_en;
2730         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2731         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2732 }
2733
2734 static void
2735 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2736         struct rte_eth_txq_info *qinfo)
2737 {
2738         struct bnxt *bp = dev->data->dev_private;
2739         struct bnxt_tx_queue *txq;
2740
2741         if (is_bnxt_in_error(bp))
2742                 return;
2743
2744         txq = dev->data->tx_queues[queue_id];
2745
2746         qinfo->nb_desc = txq->nb_tx_desc;
2747
2748         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2749         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2750         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2751
2752         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2753         qinfo->conf.tx_rs_thresh = 0;
2754         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2755         qinfo->conf.offloads = txq->offloads;
2756 }
2757
2758 static const struct {
2759         eth_rx_burst_t pkt_burst;
2760         const char *info;
2761 } bnxt_rx_burst_info[] = {
2762         {bnxt_recv_pkts,        "Scalar"},
2763 #if defined(RTE_ARCH_X86)
2764         {bnxt_recv_pkts_vec,    "Vector SSE"},
2765 #elif defined(RTE_ARCH_ARM64)
2766         {bnxt_recv_pkts_vec,    "Vector Neon"},
2767 #endif
2768 };
2769
2770 static int
2771 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2772                        struct rte_eth_burst_mode *mode)
2773 {
2774         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2775         size_t i;
2776
2777         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2778                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2779                         snprintf(mode->info, sizeof(mode->info), "%s",
2780                                  bnxt_rx_burst_info[i].info);
2781                         return 0;
2782                 }
2783         }
2784
2785         return -EINVAL;
2786 }
2787
2788 static const struct {
2789         eth_tx_burst_t pkt_burst;
2790         const char *info;
2791 } bnxt_tx_burst_info[] = {
2792         {bnxt_xmit_pkts,        "Scalar"},
2793 #if defined(RTE_ARCH_X86)
2794         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2795 #elif defined(RTE_ARCH_ARM64)
2796         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2797 #endif
2798 };
2799
2800 static int
2801 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2802                        struct rte_eth_burst_mode *mode)
2803 {
2804         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2805         size_t i;
2806
2807         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2808                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2809                         snprintf(mode->info, sizeof(mode->info), "%s",
2810                                  bnxt_tx_burst_info[i].info);
2811                         return 0;
2812                 }
2813         }
2814
2815         return -EINVAL;
2816 }
2817
2818 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2819 {
2820         struct bnxt *bp = eth_dev->data->dev_private;
2821         uint32_t new_pkt_size;
2822         uint32_t rc = 0;
2823         uint32_t i;
2824
2825         rc = is_bnxt_in_error(bp);
2826         if (rc)
2827                 return rc;
2828
2829         /* Exit if receive queues are not configured yet */
2830         if (!eth_dev->data->nb_rx_queues)
2831                 return rc;
2832
2833         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2834                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2835
2836         /*
2837          * Disallow any MTU change that would require scattered receive support
2838          * if it is not already enabled.
2839          */
2840         if (eth_dev->data->dev_started &&
2841             !eth_dev->data->scattered_rx &&
2842             (new_pkt_size >
2843              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2844                 PMD_DRV_LOG(ERR,
2845                             "MTU change would require scattered rx support. ");
2846                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2847                 return -EINVAL;
2848         }
2849
2850         if (new_mtu > RTE_ETHER_MTU) {
2851                 bp->flags |= BNXT_FLAG_JUMBO;
2852                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2853                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2854         } else {
2855                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2856                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2857                 bp->flags &= ~BNXT_FLAG_JUMBO;
2858         }
2859
2860         /* Is there a change in mtu setting? */
2861         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2862                 return rc;
2863
2864         for (i = 0; i < bp->nr_vnics; i++) {
2865                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2866                 uint16_t size = 0;
2867
2868                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2869                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2870                 if (rc)
2871                         break;
2872
2873                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2874                 size -= RTE_PKTMBUF_HEADROOM;
2875
2876                 if (size < new_mtu) {
2877                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2878                         if (rc)
2879                                 return rc;
2880                 }
2881         }
2882
2883         if (!rc)
2884                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2885
2886         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2887
2888         return rc;
2889 }
2890
2891 static int
2892 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2893 {
2894         struct bnxt *bp = dev->data->dev_private;
2895         uint16_t vlan = bp->vlan;
2896         int rc;
2897
2898         rc = is_bnxt_in_error(bp);
2899         if (rc)
2900                 return rc;
2901
2902         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2903                 PMD_DRV_LOG(ERR,
2904                         "PVID cannot be modified for this function\n");
2905                 return -ENOTSUP;
2906         }
2907         bp->vlan = on ? pvid : 0;
2908
2909         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2910         if (rc)
2911                 bp->vlan = vlan;
2912         return rc;
2913 }
2914
2915 static int
2916 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2917 {
2918         struct bnxt *bp = dev->data->dev_private;
2919         int rc;
2920
2921         rc = is_bnxt_in_error(bp);
2922         if (rc)
2923                 return rc;
2924
2925         return bnxt_hwrm_port_led_cfg(bp, true);
2926 }
2927
2928 static int
2929 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2930 {
2931         struct bnxt *bp = dev->data->dev_private;
2932         int rc;
2933
2934         rc = is_bnxt_in_error(bp);
2935         if (rc)
2936                 return rc;
2937
2938         return bnxt_hwrm_port_led_cfg(bp, false);
2939 }
2940
2941 static uint32_t
2942 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2943 {
2944         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2945         uint32_t desc = 0, raw_cons = 0, cons;
2946         struct bnxt_cp_ring_info *cpr;
2947         struct bnxt_rx_queue *rxq;
2948         struct rx_pkt_cmpl *rxcmp;
2949         int rc;
2950
2951         rc = is_bnxt_in_error(bp);
2952         if (rc)
2953                 return rc;
2954
2955         rxq = dev->data->rx_queues[rx_queue_id];
2956         cpr = rxq->cp_ring;
2957         raw_cons = cpr->cp_raw_cons;
2958
2959         while (1) {
2960                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2961                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2962                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2963
2964                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2965                         break;
2966                 } else {
2967                         raw_cons++;
2968                         desc++;
2969                 }
2970         }
2971
2972         return desc;
2973 }
2974
2975 static int
2976 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2977 {
2978         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2979         struct bnxt_rx_ring_info *rxr;
2980         struct bnxt_cp_ring_info *cpr;
2981         struct rte_mbuf *rx_buf;
2982         struct rx_pkt_cmpl *rxcmp;
2983         uint32_t cons, cp_cons;
2984         int rc;
2985
2986         if (!rxq)
2987                 return -EINVAL;
2988
2989         rc = is_bnxt_in_error(rxq->bp);
2990         if (rc)
2991                 return rc;
2992
2993         cpr = rxq->cp_ring;
2994         rxr = rxq->rx_ring;
2995
2996         if (offset >= rxq->nb_rx_desc)
2997                 return -EINVAL;
2998
2999         cons = RING_CMP(cpr->cp_ring_struct, offset);
3000         cp_cons = cpr->cp_raw_cons;
3001         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3002
3003         if (cons > cp_cons) {
3004                 if (CMPL_VALID(rxcmp, cpr->valid))
3005                         return RTE_ETH_RX_DESC_DONE;
3006         } else {
3007                 if (CMPL_VALID(rxcmp, !cpr->valid))
3008                         return RTE_ETH_RX_DESC_DONE;
3009         }
3010         rx_buf = rxr->rx_buf_ring[cons];
3011         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
3012                 return RTE_ETH_RX_DESC_UNAVAIL;
3013
3014
3015         return RTE_ETH_RX_DESC_AVAIL;
3016 }
3017
3018 static int
3019 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3020 {
3021         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3022         struct bnxt_tx_ring_info *txr;
3023         struct bnxt_cp_ring_info *cpr;
3024         struct bnxt_sw_tx_bd *tx_buf;
3025         struct tx_pkt_cmpl *txcmp;
3026         uint32_t cons, cp_cons;
3027         int rc;
3028
3029         if (!txq)
3030                 return -EINVAL;
3031
3032         rc = is_bnxt_in_error(txq->bp);
3033         if (rc)
3034                 return rc;
3035
3036         cpr = txq->cp_ring;
3037         txr = txq->tx_ring;
3038
3039         if (offset >= txq->nb_tx_desc)
3040                 return -EINVAL;
3041
3042         cons = RING_CMP(cpr->cp_ring_struct, offset);
3043         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3044         cp_cons = cpr->cp_raw_cons;
3045
3046         if (cons > cp_cons) {
3047                 if (CMPL_VALID(txcmp, cpr->valid))
3048                         return RTE_ETH_TX_DESC_UNAVAIL;
3049         } else {
3050                 if (CMPL_VALID(txcmp, !cpr->valid))
3051                         return RTE_ETH_TX_DESC_UNAVAIL;
3052         }
3053         tx_buf = &txr->tx_buf_ring[cons];
3054         if (tx_buf->mbuf == NULL)
3055                 return RTE_ETH_TX_DESC_DONE;
3056
3057         return RTE_ETH_TX_DESC_FULL;
3058 }
3059
3060 int
3061 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3062                     enum rte_filter_type filter_type,
3063                     enum rte_filter_op filter_op, void *arg)
3064 {
3065         struct bnxt *bp = dev->data->dev_private;
3066         int ret = 0;
3067
3068         if (!bp)
3069                 return -EIO;
3070
3071         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3072                 struct bnxt_representor *vfr = dev->data->dev_private;
3073                 bp = vfr->parent_dev->data->dev_private;
3074                 /* parent is deleted while children are still valid */
3075                 if (!bp) {
3076                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3077                                     dev->data->port_id,
3078                                     filter_type,
3079                                     filter_op);
3080                         return -EIO;
3081                 }
3082         }
3083
3084         ret = is_bnxt_in_error(bp);
3085         if (ret)
3086                 return ret;
3087
3088         switch (filter_type) {
3089         case RTE_ETH_FILTER_GENERIC:
3090                 if (filter_op != RTE_ETH_FILTER_GET)
3091                         return -EINVAL;
3092
3093                 /* PMD supports thread-safe flow operations.  rte_flow API
3094                  * functions can avoid mutex for multi-thread safety.
3095                  */
3096                 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3097
3098                 if (BNXT_TRUFLOW_EN(bp))
3099                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3100                 else
3101                         *(const void **)arg = &bnxt_flow_ops;
3102                 break;
3103         default:
3104                 PMD_DRV_LOG(ERR,
3105                         "Filter type (%d) not supported", filter_type);
3106                 ret = -EINVAL;
3107                 break;
3108         }
3109         return ret;
3110 }
3111
3112 static const uint32_t *
3113 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3114 {
3115         static const uint32_t ptypes[] = {
3116                 RTE_PTYPE_L2_ETHER_VLAN,
3117                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3118                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3119                 RTE_PTYPE_L4_ICMP,
3120                 RTE_PTYPE_L4_TCP,
3121                 RTE_PTYPE_L4_UDP,
3122                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3123                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3124                 RTE_PTYPE_INNER_L4_ICMP,
3125                 RTE_PTYPE_INNER_L4_TCP,
3126                 RTE_PTYPE_INNER_L4_UDP,
3127                 RTE_PTYPE_UNKNOWN
3128         };
3129
3130         if (!dev->rx_pkt_burst)
3131                 return NULL;
3132
3133         return ptypes;
3134 }
3135
3136 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3137                          int reg_win)
3138 {
3139         uint32_t reg_base = *reg_arr & 0xfffff000;
3140         uint32_t win_off;
3141         int i;
3142
3143         for (i = 0; i < count; i++) {
3144                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3145                         return -ERANGE;
3146         }
3147         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3148         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3149         return 0;
3150 }
3151
3152 static int bnxt_map_ptp_regs(struct bnxt *bp)
3153 {
3154         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3155         uint32_t *reg_arr;
3156         int rc, i;
3157
3158         reg_arr = ptp->rx_regs;
3159         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3160         if (rc)
3161                 return rc;
3162
3163         reg_arr = ptp->tx_regs;
3164         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3165         if (rc)
3166                 return rc;
3167
3168         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3169                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3170
3171         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3172                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3173
3174         return 0;
3175 }
3176
3177 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3178 {
3179         rte_write32(0, (uint8_t *)bp->bar0 +
3180                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3181         rte_write32(0, (uint8_t *)bp->bar0 +
3182                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3183 }
3184
3185 static uint64_t bnxt_cc_read(struct bnxt *bp)
3186 {
3187         uint64_t ns;
3188
3189         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3190                               BNXT_GRCPF_REG_SYNC_TIME));
3191         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3192                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3193         return ns;
3194 }
3195
3196 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3197 {
3198         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3199         uint32_t fifo;
3200
3201         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3202                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3203         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3204                 return -EAGAIN;
3205
3206         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3207                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3208         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3209                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3210         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3211                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3212
3213         return 0;
3214 }
3215
3216 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3217 {
3218         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3219         struct bnxt_pf_info *pf = bp->pf;
3220         uint16_t port_id;
3221         uint32_t fifo;
3222
3223         if (!ptp)
3224                 return -ENODEV;
3225
3226         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3227                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3228         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3229                 return -EAGAIN;
3230
3231         port_id = pf->port_id;
3232         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3233                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3234
3235         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3236                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3237         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3238 /*              bnxt_clr_rx_ts(bp);       TBD  */
3239                 return -EBUSY;
3240         }
3241
3242         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3243                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3244         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3245                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3246
3247         return 0;
3248 }
3249
3250 static int
3251 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3252 {
3253         uint64_t ns;
3254         struct bnxt *bp = dev->data->dev_private;
3255         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3256
3257         if (!ptp)
3258                 return 0;
3259
3260         ns = rte_timespec_to_ns(ts);
3261         /* Set the timecounters to a new value. */
3262         ptp->tc.nsec = ns;
3263
3264         return 0;
3265 }
3266
3267 static int
3268 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3269 {
3270         struct bnxt *bp = dev->data->dev_private;
3271         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3272         uint64_t ns, systime_cycles = 0;
3273         int rc = 0;
3274
3275         if (!ptp)
3276                 return 0;
3277
3278         if (BNXT_CHIP_P5(bp))
3279                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3280                                              &systime_cycles);
3281         else
3282                 systime_cycles = bnxt_cc_read(bp);
3283
3284         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3285         *ts = rte_ns_to_timespec(ns);
3286
3287         return rc;
3288 }
3289 static int
3290 bnxt_timesync_enable(struct rte_eth_dev *dev)
3291 {
3292         struct bnxt *bp = dev->data->dev_private;
3293         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3294         uint32_t shift = 0;
3295         int rc;
3296
3297         if (!ptp)
3298                 return 0;
3299
3300         ptp->rx_filter = 1;
3301         ptp->tx_tstamp_en = 1;
3302         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3303
3304         rc = bnxt_hwrm_ptp_cfg(bp);
3305         if (rc)
3306                 return rc;
3307
3308         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3309         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3310         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3311
3312         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3313         ptp->tc.cc_shift = shift;
3314         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3315
3316         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3317         ptp->rx_tstamp_tc.cc_shift = shift;
3318         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3319
3320         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3321         ptp->tx_tstamp_tc.cc_shift = shift;
3322         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3323
3324         if (!BNXT_CHIP_P5(bp))
3325                 bnxt_map_ptp_regs(bp);
3326
3327         return 0;
3328 }
3329
3330 static int
3331 bnxt_timesync_disable(struct rte_eth_dev *dev)
3332 {
3333         struct bnxt *bp = dev->data->dev_private;
3334         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3335
3336         if (!ptp)
3337                 return 0;
3338
3339         ptp->rx_filter = 0;
3340         ptp->tx_tstamp_en = 0;
3341         ptp->rxctl = 0;
3342
3343         bnxt_hwrm_ptp_cfg(bp);
3344
3345         if (!BNXT_CHIP_P5(bp))
3346                 bnxt_unmap_ptp_regs(bp);
3347
3348         return 0;
3349 }
3350
3351 static int
3352 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3353                                  struct timespec *timestamp,
3354                                  uint32_t flags __rte_unused)
3355 {
3356         struct bnxt *bp = dev->data->dev_private;
3357         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3358         uint64_t rx_tstamp_cycles = 0;
3359         uint64_t ns;
3360
3361         if (!ptp)
3362                 return 0;
3363
3364         if (BNXT_CHIP_P5(bp))
3365                 rx_tstamp_cycles = ptp->rx_timestamp;
3366         else
3367                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3368
3369         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3370         *timestamp = rte_ns_to_timespec(ns);
3371         return  0;
3372 }
3373
3374 static int
3375 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3376                                  struct timespec *timestamp)
3377 {
3378         struct bnxt *bp = dev->data->dev_private;
3379         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3380         uint64_t tx_tstamp_cycles = 0;
3381         uint64_t ns;
3382         int rc = 0;
3383
3384         if (!ptp)
3385                 return 0;
3386
3387         if (BNXT_CHIP_P5(bp))
3388                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3389                                              &tx_tstamp_cycles);
3390         else
3391                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3392
3393         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3394         *timestamp = rte_ns_to_timespec(ns);
3395
3396         return rc;
3397 }
3398
3399 static int
3400 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3401 {
3402         struct bnxt *bp = dev->data->dev_private;
3403         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3404
3405         if (!ptp)
3406                 return 0;
3407
3408         ptp->tc.nsec += delta;
3409
3410         return 0;
3411 }
3412
3413 static int
3414 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3415 {
3416         struct bnxt *bp = dev->data->dev_private;
3417         int rc;
3418         uint32_t dir_entries;
3419         uint32_t entry_length;
3420
3421         rc = is_bnxt_in_error(bp);
3422         if (rc)
3423                 return rc;
3424
3425         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3426                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3427                     bp->pdev->addr.devid, bp->pdev->addr.function);
3428
3429         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3430         if (rc != 0)
3431                 return rc;
3432
3433         return dir_entries * entry_length;
3434 }
3435
3436 static int
3437 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3438                 struct rte_dev_eeprom_info *in_eeprom)
3439 {
3440         struct bnxt *bp = dev->data->dev_private;
3441         uint32_t index;
3442         uint32_t offset;
3443         int rc;
3444
3445         rc = is_bnxt_in_error(bp);
3446         if (rc)
3447                 return rc;
3448
3449         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3450                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3451                     bp->pdev->addr.devid, bp->pdev->addr.function,
3452                     in_eeprom->offset, in_eeprom->length);
3453
3454         if (in_eeprom->offset == 0) /* special offset value to get directory */
3455                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3456                                                 in_eeprom->data);
3457
3458         index = in_eeprom->offset >> 24;
3459         offset = in_eeprom->offset & 0xffffff;
3460
3461         if (index != 0)
3462                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3463                                            in_eeprom->length, in_eeprom->data);
3464
3465         return 0;
3466 }
3467
3468 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3469 {
3470         switch (dir_type) {
3471         case BNX_DIR_TYPE_CHIMP_PATCH:
3472         case BNX_DIR_TYPE_BOOTCODE:
3473         case BNX_DIR_TYPE_BOOTCODE_2:
3474         case BNX_DIR_TYPE_APE_FW:
3475         case BNX_DIR_TYPE_APE_PATCH:
3476         case BNX_DIR_TYPE_KONG_FW:
3477         case BNX_DIR_TYPE_KONG_PATCH:
3478         case BNX_DIR_TYPE_BONO_FW:
3479         case BNX_DIR_TYPE_BONO_PATCH:
3480                 /* FALLTHROUGH */
3481                 return true;
3482         }
3483
3484         return false;
3485 }
3486
3487 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3488 {
3489         switch (dir_type) {
3490         case BNX_DIR_TYPE_AVS:
3491         case BNX_DIR_TYPE_EXP_ROM_MBA:
3492         case BNX_DIR_TYPE_PCIE:
3493         case BNX_DIR_TYPE_TSCF_UCODE:
3494         case BNX_DIR_TYPE_EXT_PHY:
3495         case BNX_DIR_TYPE_CCM:
3496         case BNX_DIR_TYPE_ISCSI_BOOT:
3497         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3498         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3499                 /* FALLTHROUGH */
3500                 return true;
3501         }
3502
3503         return false;
3504 }
3505
3506 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3507 {
3508         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3509                 bnxt_dir_type_is_other_exec_format(dir_type);
3510 }
3511
3512 static int
3513 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3514                 struct rte_dev_eeprom_info *in_eeprom)
3515 {
3516         struct bnxt *bp = dev->data->dev_private;
3517         uint8_t index, dir_op;
3518         uint16_t type, ext, ordinal, attr;
3519         int rc;
3520
3521         rc = is_bnxt_in_error(bp);
3522         if (rc)
3523                 return rc;
3524
3525         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3526                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3527                     bp->pdev->addr.devid, bp->pdev->addr.function,
3528                     in_eeprom->offset, in_eeprom->length);
3529
3530         if (!BNXT_PF(bp)) {
3531                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3532                 return -EINVAL;
3533         }
3534
3535         type = in_eeprom->magic >> 16;
3536
3537         if (type == 0xffff) { /* special value for directory operations */
3538                 index = in_eeprom->magic & 0xff;
3539                 dir_op = in_eeprom->magic >> 8;
3540                 if (index == 0)
3541                         return -EINVAL;
3542                 switch (dir_op) {
3543                 case 0x0e: /* erase */
3544                         if (in_eeprom->offset != ~in_eeprom->magic)
3545                                 return -EINVAL;
3546                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3547                 default:
3548                         return -EINVAL;
3549                 }
3550         }
3551
3552         /* Create or re-write an NVM item: */
3553         if (bnxt_dir_type_is_executable(type) == true)
3554                 return -EOPNOTSUPP;
3555         ext = in_eeprom->magic & 0xffff;
3556         ordinal = in_eeprom->offset >> 16;
3557         attr = in_eeprom->offset & 0xffff;
3558
3559         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3560                                      in_eeprom->data, in_eeprom->length);
3561 }
3562
3563 /*
3564  * Initialization
3565  */
3566
3567 static const struct eth_dev_ops bnxt_dev_ops = {
3568         .dev_infos_get = bnxt_dev_info_get_op,
3569         .dev_close = bnxt_dev_close_op,
3570         .dev_configure = bnxt_dev_configure_op,
3571         .dev_start = bnxt_dev_start_op,
3572         .dev_stop = bnxt_dev_stop_op,
3573         .dev_set_link_up = bnxt_dev_set_link_up_op,
3574         .dev_set_link_down = bnxt_dev_set_link_down_op,
3575         .stats_get = bnxt_stats_get_op,
3576         .stats_reset = bnxt_stats_reset_op,
3577         .rx_queue_setup = bnxt_rx_queue_setup_op,
3578         .rx_queue_release = bnxt_rx_queue_release_op,
3579         .tx_queue_setup = bnxt_tx_queue_setup_op,
3580         .tx_queue_release = bnxt_tx_queue_release_op,
3581         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3582         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3583         .reta_update = bnxt_reta_update_op,
3584         .reta_query = bnxt_reta_query_op,
3585         .rss_hash_update = bnxt_rss_hash_update_op,
3586         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3587         .link_update = bnxt_link_update_op,
3588         .promiscuous_enable = bnxt_promiscuous_enable_op,
3589         .promiscuous_disable = bnxt_promiscuous_disable_op,
3590         .allmulticast_enable = bnxt_allmulticast_enable_op,
3591         .allmulticast_disable = bnxt_allmulticast_disable_op,
3592         .mac_addr_add = bnxt_mac_addr_add_op,
3593         .mac_addr_remove = bnxt_mac_addr_remove_op,
3594         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3595         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3596         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3597         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3598         .vlan_filter_set = bnxt_vlan_filter_set_op,
3599         .vlan_offload_set = bnxt_vlan_offload_set_op,
3600         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3601         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3602         .mtu_set = bnxt_mtu_set_op,
3603         .mac_addr_set = bnxt_set_default_mac_addr_op,
3604         .xstats_get = bnxt_dev_xstats_get_op,
3605         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3606         .xstats_reset = bnxt_dev_xstats_reset_op,
3607         .fw_version_get = bnxt_fw_version_get,
3608         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3609         .rxq_info_get = bnxt_rxq_info_get_op,
3610         .txq_info_get = bnxt_txq_info_get_op,
3611         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3612         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3613         .dev_led_on = bnxt_dev_led_on_op,
3614         .dev_led_off = bnxt_dev_led_off_op,
3615         .rx_queue_start = bnxt_rx_queue_start,
3616         .rx_queue_stop = bnxt_rx_queue_stop,
3617         .tx_queue_start = bnxt_tx_queue_start,
3618         .tx_queue_stop = bnxt_tx_queue_stop,
3619         .filter_ctrl = bnxt_filter_ctrl_op,
3620         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3621         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3622         .get_eeprom           = bnxt_get_eeprom_op,
3623         .set_eeprom           = bnxt_set_eeprom_op,
3624         .timesync_enable      = bnxt_timesync_enable,
3625         .timesync_disable     = bnxt_timesync_disable,
3626         .timesync_read_time   = bnxt_timesync_read_time,
3627         .timesync_write_time   = bnxt_timesync_write_time,
3628         .timesync_adjust_time = bnxt_timesync_adjust_time,
3629         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3630         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3631 };
3632
3633 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3634 {
3635         uint32_t offset;
3636
3637         /* Only pre-map the reset GRC registers using window 3 */
3638         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3639                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3640
3641         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3642
3643         return offset;
3644 }
3645
3646 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3647 {
3648         struct bnxt_error_recovery_info *info = bp->recovery_info;
3649         uint32_t reg_base = 0xffffffff;
3650         int i;
3651
3652         /* Only pre-map the monitoring GRC registers using window 2 */
3653         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3654                 uint32_t reg = info->status_regs[i];
3655
3656                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3657                         continue;
3658
3659                 if (reg_base == 0xffffffff)
3660                         reg_base = reg & 0xfffff000;
3661                 if ((reg & 0xfffff000) != reg_base)
3662                         return -ERANGE;
3663
3664                 /* Use mask 0xffc as the Lower 2 bits indicates
3665                  * address space location
3666                  */
3667                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3668                                                 (reg & 0xffc);
3669         }
3670
3671         if (reg_base == 0xffffffff)
3672                 return 0;
3673
3674         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3675                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3676
3677         return 0;
3678 }
3679
3680 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3681 {
3682         struct bnxt_error_recovery_info *info = bp->recovery_info;
3683         uint32_t delay = info->delay_after_reset[index];
3684         uint32_t val = info->reset_reg_val[index];
3685         uint32_t reg = info->reset_reg[index];
3686         uint32_t type, offset;
3687
3688         type = BNXT_FW_STATUS_REG_TYPE(reg);
3689         offset = BNXT_FW_STATUS_REG_OFF(reg);
3690
3691         switch (type) {
3692         case BNXT_FW_STATUS_REG_TYPE_CFG:
3693                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3694                 break;
3695         case BNXT_FW_STATUS_REG_TYPE_GRC:
3696                 offset = bnxt_map_reset_regs(bp, offset);
3697                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3698                 break;
3699         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3700                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3701                 break;
3702         }
3703         /* wait on a specific interval of time until core reset is complete */
3704         if (delay)
3705                 rte_delay_ms(delay);
3706 }
3707
3708 static void bnxt_dev_cleanup(struct bnxt *bp)
3709 {
3710         bp->eth_dev->data->dev_link.link_status = 0;
3711         bp->link_info->link_up = 0;
3712         if (bp->eth_dev->data->dev_started)
3713                 bnxt_dev_stop(bp->eth_dev);
3714
3715         bnxt_uninit_resources(bp, true);
3716 }
3717
3718 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3719 {
3720         struct rte_eth_dev *dev = bp->eth_dev;
3721         struct rte_vlan_filter_conf *vfc;
3722         int vidx, vbit, rc;
3723         uint16_t vlan_id;
3724
3725         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3726                 vfc = &dev->data->vlan_filter_conf;
3727                 vidx = vlan_id / 64;
3728                 vbit = vlan_id % 64;
3729
3730                 /* Each bit corresponds to a VLAN id */
3731                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3732                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3733                         if (rc)
3734                                 return rc;
3735                 }
3736         }
3737
3738         return 0;
3739 }
3740
3741 static int bnxt_restore_mac_filters(struct bnxt *bp)
3742 {
3743         struct rte_eth_dev *dev = bp->eth_dev;
3744         struct rte_eth_dev_info dev_info;
3745         struct rte_ether_addr *addr;
3746         uint64_t pool_mask;
3747         uint32_t pool = 0;
3748         uint16_t i;
3749         int rc;
3750
3751         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3752                 return 0;
3753
3754         rc = bnxt_dev_info_get_op(dev, &dev_info);
3755         if (rc)
3756                 return rc;
3757
3758         /* replay MAC address configuration */
3759         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3760                 addr = &dev->data->mac_addrs[i];
3761
3762                 /* skip zero address */
3763                 if (rte_is_zero_ether_addr(addr))
3764                         continue;
3765
3766                 pool = 0;
3767                 pool_mask = dev->data->mac_pool_sel[i];
3768
3769                 do {
3770                         if (pool_mask & 1ULL) {
3771                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3772                                 if (rc)
3773                                         return rc;
3774                         }
3775                         pool_mask >>= 1;
3776                         pool++;
3777                 } while (pool_mask);
3778         }
3779
3780         return 0;
3781 }
3782
3783 static int bnxt_restore_filters(struct bnxt *bp)
3784 {
3785         struct rte_eth_dev *dev = bp->eth_dev;
3786         int ret = 0;
3787
3788         if (dev->data->all_multicast) {
3789                 ret = bnxt_allmulticast_enable_op(dev);
3790                 if (ret)
3791                         return ret;
3792         }
3793         if (dev->data->promiscuous) {
3794                 ret = bnxt_promiscuous_enable_op(dev);
3795                 if (ret)
3796                         return ret;
3797         }
3798
3799         ret = bnxt_restore_mac_filters(bp);
3800         if (ret)
3801                 return ret;
3802
3803         ret = bnxt_restore_vlan_filters(bp);
3804         /* TODO restore other filters as well */
3805         return ret;
3806 }
3807
3808 static void bnxt_dev_recover(void *arg)
3809 {
3810         struct bnxt *bp = arg;
3811         int timeout = bp->fw_reset_max_msecs;
3812         int rc = 0;
3813
3814         pthread_mutex_lock(&bp->err_recovery_lock);
3815         /* Clear Error flag so that device re-init should happen */
3816         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3817
3818         do {
3819                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
3820                 if (rc == 0)
3821                         break;
3822                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3823                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3824         } while (rc && timeout);
3825
3826         if (rc) {
3827                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3828                 goto err;
3829         }
3830
3831         rc = bnxt_init_resources(bp, true);
3832         if (rc) {
3833                 PMD_DRV_LOG(ERR,
3834                             "Failed to initialize resources after reset\n");
3835                 goto err;
3836         }
3837         /* clear reset flag as the device is initialized now */
3838         bp->flags &= ~BNXT_FLAG_FW_RESET;
3839
3840         rc = bnxt_dev_start_op(bp->eth_dev);
3841         if (rc) {
3842                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3843                 goto err_start;
3844         }
3845
3846         rc = bnxt_restore_filters(bp);
3847         if (rc)
3848                 goto err_start;
3849
3850         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3851         pthread_mutex_unlock(&bp->err_recovery_lock);
3852
3853         return;
3854 err_start:
3855         bnxt_dev_stop(bp->eth_dev);
3856 err:
3857         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3858         bnxt_uninit_resources(bp, false);
3859         pthread_mutex_unlock(&bp->err_recovery_lock);
3860         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3861 }
3862
3863 void bnxt_dev_reset_and_resume(void *arg)
3864 {
3865         struct bnxt *bp = arg;
3866         int rc;
3867
3868         bnxt_dev_cleanup(bp);
3869
3870         bnxt_wait_for_device_shutdown(bp);
3871
3872         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3873                                bnxt_dev_recover, (void *)bp);
3874         if (rc)
3875                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3876 }
3877
3878 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3879 {
3880         struct bnxt_error_recovery_info *info = bp->recovery_info;
3881         uint32_t reg = info->status_regs[index];
3882         uint32_t type, offset, val = 0;
3883
3884         type = BNXT_FW_STATUS_REG_TYPE(reg);
3885         offset = BNXT_FW_STATUS_REG_OFF(reg);
3886
3887         switch (type) {
3888         case BNXT_FW_STATUS_REG_TYPE_CFG:
3889                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3890                 break;
3891         case BNXT_FW_STATUS_REG_TYPE_GRC:
3892                 offset = info->mapped_status_regs[index];
3893                 /* FALLTHROUGH */
3894         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3895                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3896                                        offset));
3897                 break;
3898         }
3899
3900         return val;
3901 }
3902
3903 static int bnxt_fw_reset_all(struct bnxt *bp)
3904 {
3905         struct bnxt_error_recovery_info *info = bp->recovery_info;
3906         uint32_t i;
3907         int rc = 0;
3908
3909         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3910                 /* Reset through master function driver */
3911                 for (i = 0; i < info->reg_array_cnt; i++)
3912                         bnxt_write_fw_reset_reg(bp, i);
3913                 /* Wait for time specified by FW after triggering reset */
3914                 rte_delay_ms(info->master_func_wait_period_after_reset);
3915         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3916                 /* Reset with the help of Kong processor */
3917                 rc = bnxt_hwrm_fw_reset(bp);
3918                 if (rc)
3919                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3920         }
3921
3922         return rc;
3923 }
3924
3925 static void bnxt_fw_reset_cb(void *arg)
3926 {
3927         struct bnxt *bp = arg;
3928         struct bnxt_error_recovery_info *info = bp->recovery_info;
3929         int rc = 0;
3930
3931         /* Only Master function can do FW reset */
3932         if (bnxt_is_master_func(bp) &&
3933             bnxt_is_recovery_enabled(bp)) {
3934                 rc = bnxt_fw_reset_all(bp);
3935                 if (rc) {
3936                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3937                         return;
3938                 }
3939         }
3940
3941         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3942          * EXCEPTION_FATAL_ASYNC event to all the functions
3943          * (including MASTER FUNC). After receiving this Async, all the active
3944          * drivers should treat this case as FW initiated recovery
3945          */
3946         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3947                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3948                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3949
3950                 /* To recover from error */
3951                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3952                                   (void *)bp);
3953         }
3954 }
3955
3956 /* Driver should poll FW heartbeat, reset_counter with the frequency
3957  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3958  * When the driver detects heartbeat stop or change in reset_counter,
3959  * it has to trigger a reset to recover from the error condition.
3960  * A “master PF” is the function who will have the privilege to
3961  * initiate the chimp reset. The master PF will be elected by the
3962  * firmware and will be notified through async message.
3963  */
3964 static void bnxt_check_fw_health(void *arg)
3965 {
3966         struct bnxt *bp = arg;
3967         struct bnxt_error_recovery_info *info = bp->recovery_info;
3968         uint32_t val = 0, wait_msec;
3969
3970         if (!info || !bnxt_is_recovery_enabled(bp) ||
3971             is_bnxt_in_error(bp))
3972                 return;
3973
3974         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3975         if (val == info->last_heart_beat)
3976                 goto reset;
3977
3978         info->last_heart_beat = val;
3979
3980         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3981         if (val != info->last_reset_counter)
3982                 goto reset;
3983
3984         info->last_reset_counter = val;
3985
3986         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3987                           bnxt_check_fw_health, (void *)bp);
3988
3989         return;
3990 reset:
3991         /* Stop DMA to/from device */
3992         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3993         bp->flags |= BNXT_FLAG_FW_RESET;
3994
3995         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3996
3997         if (bnxt_is_master_func(bp))
3998                 wait_msec = info->master_func_wait_period;
3999         else
4000                 wait_msec = info->normal_func_wait_period;
4001
4002         rte_eal_alarm_set(US_PER_MS * wait_msec,
4003                           bnxt_fw_reset_cb, (void *)bp);
4004 }
4005
4006 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4007 {
4008         uint32_t polling_freq;
4009
4010         pthread_mutex_lock(&bp->health_check_lock);
4011
4012         if (!bnxt_is_recovery_enabled(bp))
4013                 goto done;
4014
4015         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4016                 goto done;
4017
4018         polling_freq = bp->recovery_info->driver_polling_freq;
4019
4020         rte_eal_alarm_set(US_PER_MS * polling_freq,
4021                           bnxt_check_fw_health, (void *)bp);
4022         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4023
4024 done:
4025         pthread_mutex_unlock(&bp->health_check_lock);
4026 }
4027
4028 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4029 {
4030         if (!bnxt_is_recovery_enabled(bp))
4031                 return;
4032
4033         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4034         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4035 }
4036
4037 static bool bnxt_vf_pciid(uint16_t device_id)
4038 {
4039         switch (device_id) {
4040         case BROADCOM_DEV_ID_57304_VF:
4041         case BROADCOM_DEV_ID_57406_VF:
4042         case BROADCOM_DEV_ID_5731X_VF:
4043         case BROADCOM_DEV_ID_5741X_VF:
4044         case BROADCOM_DEV_ID_57414_VF:
4045         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4046         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4047         case BROADCOM_DEV_ID_58802_VF:
4048         case BROADCOM_DEV_ID_57500_VF1:
4049         case BROADCOM_DEV_ID_57500_VF2:
4050         case BROADCOM_DEV_ID_58818_VF:
4051                 /* FALLTHROUGH */
4052                 return true;
4053         default:
4054                 return false;
4055         }
4056 }
4057
4058 /* Phase 5 device */
4059 static bool bnxt_p5_device(uint16_t device_id)
4060 {
4061         switch (device_id) {
4062         case BROADCOM_DEV_ID_57508:
4063         case BROADCOM_DEV_ID_57504:
4064         case BROADCOM_DEV_ID_57502:
4065         case BROADCOM_DEV_ID_57508_MF1:
4066         case BROADCOM_DEV_ID_57504_MF1:
4067         case BROADCOM_DEV_ID_57502_MF1:
4068         case BROADCOM_DEV_ID_57508_MF2:
4069         case BROADCOM_DEV_ID_57504_MF2:
4070         case BROADCOM_DEV_ID_57502_MF2:
4071         case BROADCOM_DEV_ID_57500_VF1:
4072         case BROADCOM_DEV_ID_57500_VF2:
4073         case BROADCOM_DEV_ID_58812:
4074         case BROADCOM_DEV_ID_58814:
4075         case BROADCOM_DEV_ID_58818:
4076         case BROADCOM_DEV_ID_58818_VF:
4077                 /* FALLTHROUGH */
4078                 return true;
4079         default:
4080                 return false;
4081         }
4082 }
4083
4084 bool bnxt_stratus_device(struct bnxt *bp)
4085 {
4086         uint16_t device_id = bp->pdev->id.device_id;
4087
4088         switch (device_id) {
4089         case BROADCOM_DEV_ID_STRATUS_NIC:
4090         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4091         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4092                 /* FALLTHROUGH */
4093                 return true;
4094         default:
4095                 return false;
4096         }
4097 }
4098
4099 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4100 {
4101         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4102         struct bnxt *bp = eth_dev->data->dev_private;
4103
4104         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4105         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4106         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4107         if (!bp->bar0 || !bp->doorbell_base) {
4108                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4109                 return -ENODEV;
4110         }
4111
4112         bp->eth_dev = eth_dev;
4113         bp->pdev = pci_dev;
4114
4115         return 0;
4116 }
4117
4118 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4119                                   struct bnxt_ctx_pg_info *ctx_pg,
4120                                   uint32_t mem_size,
4121                                   const char *suffix,
4122                                   uint16_t idx)
4123 {
4124         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4125         const struct rte_memzone *mz = NULL;
4126         char mz_name[RTE_MEMZONE_NAMESIZE];
4127         rte_iova_t mz_phys_addr;
4128         uint64_t valid_bits = 0;
4129         uint32_t sz;
4130         int i;
4131
4132         if (!mem_size)
4133                 return 0;
4134
4135         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4136                          BNXT_PAGE_SIZE;
4137         rmem->page_size = BNXT_PAGE_SIZE;
4138         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4139         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4140         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4141
4142         valid_bits = PTU_PTE_VALID;
4143
4144         if (rmem->nr_pages > 1) {
4145                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4146                          "bnxt_ctx_pg_tbl%s_%x_%d",
4147                          suffix, idx, bp->eth_dev->data->port_id);
4148                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4149                 mz = rte_memzone_lookup(mz_name);
4150                 if (!mz) {
4151                         mz = rte_memzone_reserve_aligned(mz_name,
4152                                                 rmem->nr_pages * 8,
4153                                                 SOCKET_ID_ANY,
4154                                                 RTE_MEMZONE_2MB |
4155                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4156                                                 RTE_MEMZONE_IOVA_CONTIG,
4157                                                 BNXT_PAGE_SIZE);
4158                         if (mz == NULL)
4159                                 return -ENOMEM;
4160                 }
4161
4162                 memset(mz->addr, 0, mz->len);
4163                 mz_phys_addr = mz->iova;
4164
4165                 rmem->pg_tbl = mz->addr;
4166                 rmem->pg_tbl_map = mz_phys_addr;
4167                 rmem->pg_tbl_mz = mz;
4168         }
4169
4170         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4171                  suffix, idx, bp->eth_dev->data->port_id);
4172         mz = rte_memzone_lookup(mz_name);
4173         if (!mz) {
4174                 mz = rte_memzone_reserve_aligned(mz_name,
4175                                                  mem_size,
4176                                                  SOCKET_ID_ANY,
4177                                                  RTE_MEMZONE_1GB |
4178                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4179                                                  RTE_MEMZONE_IOVA_CONTIG,
4180                                                  BNXT_PAGE_SIZE);
4181                 if (mz == NULL)
4182                         return -ENOMEM;
4183         }
4184
4185         memset(mz->addr, 0, mz->len);
4186         mz_phys_addr = mz->iova;
4187
4188         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4189                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4190                 rmem->dma_arr[i] = mz_phys_addr + sz;
4191
4192                 if (rmem->nr_pages > 1) {
4193                         if (i == rmem->nr_pages - 2 &&
4194                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4195                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4196                         else if (i == rmem->nr_pages - 1 &&
4197                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4198                                 valid_bits |= PTU_PTE_LAST;
4199
4200                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4201                                                            valid_bits);
4202                 }
4203         }
4204
4205         rmem->mz = mz;
4206         if (rmem->vmem_size)
4207                 rmem->vmem = (void **)mz->addr;
4208         rmem->dma_arr[0] = mz_phys_addr;
4209         return 0;
4210 }
4211
4212 static void bnxt_free_ctx_mem(struct bnxt *bp)
4213 {
4214         int i;
4215
4216         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4217                 return;
4218
4219         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4220         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4221         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4222         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4223         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4224         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4225         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4226         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4227         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4228         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4229         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4230
4231         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4232                 if (bp->ctx->tqm_mem[i])
4233                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4234         }
4235
4236         rte_free(bp->ctx);
4237         bp->ctx = NULL;
4238 }
4239
4240 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4241
4242 #define min_t(type, x, y) ({                    \
4243         type __min1 = (x);                      \
4244         type __min2 = (y);                      \
4245         __min1 < __min2 ? __min1 : __min2; })
4246
4247 #define max_t(type, x, y) ({                    \
4248         type __max1 = (x);                      \
4249         type __max2 = (y);                      \
4250         __max1 > __max2 ? __max1 : __max2; })
4251
4252 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4253
4254 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4255 {
4256         struct bnxt_ctx_pg_info *ctx_pg;
4257         struct bnxt_ctx_mem_info *ctx;
4258         uint32_t mem_size, ena, entries;
4259         uint32_t entries_sp, min;
4260         int i, rc;
4261
4262         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4263         if (rc) {
4264                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4265                 return rc;
4266         }
4267         ctx = bp->ctx;
4268         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4269                 return 0;
4270
4271         ctx_pg = &ctx->qp_mem;
4272         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4273         if (ctx->qp_entry_size) {
4274                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4275                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4276                 if (rc)
4277                         return rc;
4278         }
4279
4280         ctx_pg = &ctx->srq_mem;
4281         ctx_pg->entries = ctx->srq_max_l2_entries;
4282         if (ctx->srq_entry_size) {
4283                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4284                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4285                 if (rc)
4286                         return rc;
4287         }
4288
4289         ctx_pg = &ctx->cq_mem;
4290         ctx_pg->entries = ctx->cq_max_l2_entries;
4291         if (ctx->cq_entry_size) {
4292                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4293                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4294                 if (rc)
4295                         return rc;
4296         }
4297
4298         ctx_pg = &ctx->vnic_mem;
4299         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4300                 ctx->vnic_max_ring_table_entries;
4301         if (ctx->vnic_entry_size) {
4302                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4303                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4304                 if (rc)
4305                         return rc;
4306         }
4307
4308         ctx_pg = &ctx->stat_mem;
4309         ctx_pg->entries = ctx->stat_max_entries;
4310         if (ctx->stat_entry_size) {
4311                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4312                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4313                 if (rc)
4314                         return rc;
4315         }
4316
4317         min = ctx->tqm_min_entries_per_ring;
4318
4319         entries_sp = ctx->qp_max_l2_entries +
4320                      ctx->vnic_max_vnic_entries +
4321                      2 * ctx->qp_min_qp1_entries + min;
4322         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4323
4324         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4325         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4326         entries = clamp_t(uint32_t, entries, min,
4327                           ctx->tqm_max_entries_per_ring);
4328         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4329                 ctx_pg = ctx->tqm_mem[i];
4330                 ctx_pg->entries = i ? entries : entries_sp;
4331                 if (ctx->tqm_entry_size) {
4332                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4333                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4334                         if (rc)
4335                                 return rc;
4336                 }
4337                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4338         }
4339
4340         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4341         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4342         if (rc)
4343                 PMD_DRV_LOG(ERR,
4344                             "Failed to configure context mem: rc = %d\n", rc);
4345         else
4346                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4347
4348         return rc;
4349 }
4350
4351 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4352 {
4353         struct rte_pci_device *pci_dev = bp->pdev;
4354         char mz_name[RTE_MEMZONE_NAMESIZE];
4355         const struct rte_memzone *mz = NULL;
4356         uint32_t total_alloc_len;
4357         rte_iova_t mz_phys_addr;
4358
4359         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4360                 return 0;
4361
4362         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4363                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4364                  pci_dev->addr.bus, pci_dev->addr.devid,
4365                  pci_dev->addr.function, "rx_port_stats");
4366         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4367         mz = rte_memzone_lookup(mz_name);
4368         total_alloc_len =
4369                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4370                                        sizeof(struct rx_port_stats_ext) + 512);
4371         if (!mz) {
4372                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4373                                          SOCKET_ID_ANY,
4374                                          RTE_MEMZONE_2MB |
4375                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4376                                          RTE_MEMZONE_IOVA_CONTIG);
4377                 if (mz == NULL)
4378                         return -ENOMEM;
4379         }
4380         memset(mz->addr, 0, mz->len);
4381         mz_phys_addr = mz->iova;
4382
4383         bp->rx_mem_zone = (const void *)mz;
4384         bp->hw_rx_port_stats = mz->addr;
4385         bp->hw_rx_port_stats_map = mz_phys_addr;
4386
4387         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4388                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4389                  pci_dev->addr.bus, pci_dev->addr.devid,
4390                  pci_dev->addr.function, "tx_port_stats");
4391         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4392         mz = rte_memzone_lookup(mz_name);
4393         total_alloc_len =
4394                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4395                                        sizeof(struct tx_port_stats_ext) + 512);
4396         if (!mz) {
4397                 mz = rte_memzone_reserve(mz_name,
4398                                          total_alloc_len,
4399                                          SOCKET_ID_ANY,
4400                                          RTE_MEMZONE_2MB |
4401                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4402                                          RTE_MEMZONE_IOVA_CONTIG);
4403                 if (mz == NULL)
4404                         return -ENOMEM;
4405         }
4406         memset(mz->addr, 0, mz->len);
4407         mz_phys_addr = mz->iova;
4408
4409         bp->tx_mem_zone = (const void *)mz;
4410         bp->hw_tx_port_stats = mz->addr;
4411         bp->hw_tx_port_stats_map = mz_phys_addr;
4412         bp->flags |= BNXT_FLAG_PORT_STATS;
4413
4414         /* Display extended statistics if FW supports it */
4415         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4416             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4417             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4418                 return 0;
4419
4420         bp->hw_rx_port_stats_ext = (void *)
4421                 ((uint8_t *)bp->hw_rx_port_stats +
4422                  sizeof(struct rx_port_stats));
4423         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4424                 sizeof(struct rx_port_stats);
4425         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4426
4427         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4428             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4429                 bp->hw_tx_port_stats_ext = (void *)
4430                         ((uint8_t *)bp->hw_tx_port_stats +
4431                          sizeof(struct tx_port_stats));
4432                 bp->hw_tx_port_stats_ext_map =
4433                         bp->hw_tx_port_stats_map +
4434                         sizeof(struct tx_port_stats);
4435                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4436         }
4437
4438         return 0;
4439 }
4440
4441 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4442 {
4443         struct bnxt *bp = eth_dev->data->dev_private;
4444         int rc = 0;
4445
4446         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4447                                                RTE_ETHER_ADDR_LEN *
4448                                                bp->max_l2_ctx,
4449                                                0);
4450         if (eth_dev->data->mac_addrs == NULL) {
4451                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4452                 return -ENOMEM;
4453         }
4454
4455         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4456                 if (BNXT_PF(bp))
4457                         return -EINVAL;
4458
4459                 /* Generate a random MAC address, if none was assigned by PF */
4460                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4461                 bnxt_eth_hw_addr_random(bp->mac_addr);
4462                 PMD_DRV_LOG(INFO,
4463                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4464                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4465                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4466
4467                 rc = bnxt_hwrm_set_mac(bp);
4468                 if (rc)
4469                         return rc;
4470         }
4471
4472         /* Copy the permanent MAC from the FUNC_QCAPS response */
4473         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4474
4475         return rc;
4476 }
4477
4478 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4479 {
4480         int rc = 0;
4481
4482         /* MAC is already configured in FW */
4483         if (BNXT_HAS_DFLT_MAC_SET(bp))
4484                 return 0;
4485
4486         /* Restore the old MAC configured */
4487         rc = bnxt_hwrm_set_mac(bp);
4488         if (rc)
4489                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4490
4491         return rc;
4492 }
4493
4494 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4495 {
4496         if (!BNXT_PF(bp))
4497                 return;
4498
4499         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4500
4501         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4502                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4503         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4504         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4505         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4506         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4507 }
4508
4509 uint16_t
4510 bnxt_get_svif(uint16_t port_id, bool func_svif,
4511               enum bnxt_ulp_intf_type type)
4512 {
4513         struct rte_eth_dev *eth_dev;
4514         struct bnxt *bp;
4515
4516         eth_dev = &rte_eth_devices[port_id];
4517         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4518                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4519                 if (!vfr)
4520                         return 0;
4521
4522                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4523                         return vfr->svif;
4524
4525                 eth_dev = vfr->parent_dev;
4526         }
4527
4528         bp = eth_dev->data->dev_private;
4529
4530         return func_svif ? bp->func_svif : bp->port_svif;
4531 }
4532
4533 uint16_t
4534 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4535 {
4536         struct rte_eth_dev *eth_dev;
4537         struct bnxt_vnic_info *vnic;
4538         struct bnxt *bp;
4539
4540         eth_dev = &rte_eth_devices[port];
4541         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4542                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4543                 if (!vfr)
4544                         return 0;
4545
4546                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4547                         return vfr->dflt_vnic_id;
4548
4549                 eth_dev = vfr->parent_dev;
4550         }
4551
4552         bp = eth_dev->data->dev_private;
4553
4554         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4555
4556         return vnic->fw_vnic_id;
4557 }
4558
4559 uint16_t
4560 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4561 {
4562         struct rte_eth_dev *eth_dev;
4563         struct bnxt *bp;
4564
4565         eth_dev = &rte_eth_devices[port];
4566         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4567                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4568                 if (!vfr)
4569                         return 0;
4570
4571                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4572                         return vfr->fw_fid;
4573
4574                 eth_dev = vfr->parent_dev;
4575         }
4576
4577         bp = eth_dev->data->dev_private;
4578
4579         return bp->fw_fid;
4580 }
4581
4582 enum bnxt_ulp_intf_type
4583 bnxt_get_interface_type(uint16_t port)
4584 {
4585         struct rte_eth_dev *eth_dev;
4586         struct bnxt *bp;
4587
4588         eth_dev = &rte_eth_devices[port];
4589         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4590                 return BNXT_ULP_INTF_TYPE_VF_REP;
4591
4592         bp = eth_dev->data->dev_private;
4593         if (BNXT_PF(bp))
4594                 return BNXT_ULP_INTF_TYPE_PF;
4595         else if (BNXT_VF_IS_TRUSTED(bp))
4596                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4597         else if (BNXT_VF(bp))
4598                 return BNXT_ULP_INTF_TYPE_VF;
4599
4600         return BNXT_ULP_INTF_TYPE_INVALID;
4601 }
4602
4603 uint16_t
4604 bnxt_get_phy_port_id(uint16_t port_id)
4605 {
4606         struct bnxt_representor *vfr;
4607         struct rte_eth_dev *eth_dev;
4608         struct bnxt *bp;
4609
4610         eth_dev = &rte_eth_devices[port_id];
4611         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4612                 vfr = eth_dev->data->dev_private;
4613                 if (!vfr)
4614                         return 0;
4615
4616                 eth_dev = vfr->parent_dev;
4617         }
4618
4619         bp = eth_dev->data->dev_private;
4620
4621         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4622 }
4623
4624 uint16_t
4625 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4626 {
4627         struct rte_eth_dev *eth_dev;
4628         struct bnxt *bp;
4629
4630         eth_dev = &rte_eth_devices[port_id];
4631         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4632                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4633                 if (!vfr)
4634                         return 0;
4635
4636                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4637                         return vfr->fw_fid - 1;
4638
4639                 eth_dev = vfr->parent_dev;
4640         }
4641
4642         bp = eth_dev->data->dev_private;
4643
4644         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4645 }
4646
4647 uint16_t
4648 bnxt_get_vport(uint16_t port_id)
4649 {
4650         return (1 << bnxt_get_phy_port_id(port_id));
4651 }
4652
4653 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4654 {
4655         struct bnxt_error_recovery_info *info = bp->recovery_info;
4656
4657         if (info) {
4658                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4659                         memset(info, 0, sizeof(*info));
4660                 return;
4661         }
4662
4663         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4664                 return;
4665
4666         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4667                            sizeof(*info), 0);
4668         if (!info)
4669                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4670
4671         bp->recovery_info = info;
4672 }
4673
4674 static void bnxt_check_fw_status(struct bnxt *bp)
4675 {
4676         uint32_t fw_status;
4677
4678         if (!(bp->recovery_info &&
4679               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4680                 return;
4681
4682         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4683         if (fw_status != BNXT_FW_STATUS_HEALTHY)
4684                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4685                             fw_status);
4686 }
4687
4688 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4689 {
4690         struct bnxt_error_recovery_info *info = bp->recovery_info;
4691         uint32_t status_loc;
4692         uint32_t sig_ver;
4693
4694         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4695                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4696         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4697                                    BNXT_GRCP_WINDOW_2_BASE +
4698                                    offsetof(struct hcomm_status,
4699                                             sig_ver)));
4700         /* If the signature is absent, then FW does not support this feature */
4701         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4702             HCOMM_STATUS_SIGNATURE_VAL)
4703                 return 0;
4704
4705         if (!info) {
4706                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4707                                    sizeof(*info), 0);
4708                 if (!info)
4709                         return -ENOMEM;
4710                 bp->recovery_info = info;
4711         } else {
4712                 memset(info, 0, sizeof(*info));
4713         }
4714
4715         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4716                                       BNXT_GRCP_WINDOW_2_BASE +
4717                                       offsetof(struct hcomm_status,
4718                                                fw_status_loc)));
4719
4720         /* Only pre-map the FW health status GRC register */
4721         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4722                 return 0;
4723
4724         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4725         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4726                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4727
4728         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4729                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4730
4731         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4732
4733         return 0;
4734 }
4735
4736 /* This function gets the FW version along with the
4737  * capabilities(MAX and current) of the function, vnic,
4738  * error recovery, phy and other chip related info
4739  */
4740 static int bnxt_get_config(struct bnxt *bp)
4741 {
4742         uint16_t mtu;
4743         int rc = 0;
4744
4745         bp->fw_cap = 0;
4746
4747         rc = bnxt_map_hcomm_fw_status_reg(bp);
4748         if (rc)
4749                 return rc;
4750
4751         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4752         if (rc) {
4753                 bnxt_check_fw_status(bp);
4754                 return rc;
4755         }
4756
4757         rc = bnxt_hwrm_func_reset(bp);
4758         if (rc)
4759                 return -EIO;
4760
4761         rc = bnxt_hwrm_vnic_qcaps(bp);
4762         if (rc)
4763                 return rc;
4764
4765         rc = bnxt_hwrm_queue_qportcfg(bp);
4766         if (rc)
4767                 return rc;
4768
4769         /* Get the MAX capabilities for this function.
4770          * This function also allocates context memory for TQM rings and
4771          * informs the firmware about this allocated backing store memory.
4772          */
4773         rc = bnxt_hwrm_func_qcaps(bp);
4774         if (rc)
4775                 return rc;
4776
4777         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4778         if (rc)
4779                 return rc;
4780
4781         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4782         if (rc)
4783                 return rc;
4784
4785         bnxt_hwrm_port_mac_qcfg(bp);
4786
4787         bnxt_hwrm_parent_pf_qcfg(bp);
4788
4789         bnxt_hwrm_port_phy_qcaps(bp);
4790
4791         bnxt_alloc_error_recovery_info(bp);
4792         /* Get the adapter error recovery support info */
4793         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4794         if (rc)
4795                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4796
4797         bnxt_hwrm_port_led_qcaps(bp);
4798
4799         return 0;
4800 }
4801
4802 static int
4803 bnxt_init_locks(struct bnxt *bp)
4804 {
4805         int err;
4806
4807         err = pthread_mutex_init(&bp->flow_lock, NULL);
4808         if (err) {
4809                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4810                 return err;
4811         }
4812
4813         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4814         if (err) {
4815                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4816                 return err;
4817         }
4818
4819         err = pthread_mutex_init(&bp->health_check_lock, NULL);
4820         if (err) {
4821                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
4822                 return err;
4823         }
4824
4825         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
4826         if (err)
4827                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
4828
4829         return err;
4830 }
4831
4832 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4833 {
4834         int rc = 0;
4835
4836         rc = bnxt_get_config(bp);
4837         if (rc)
4838                 return rc;
4839
4840         if (!reconfig_dev) {
4841                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4842                 if (rc)
4843                         return rc;
4844         } else {
4845                 rc = bnxt_restore_dflt_mac(bp);
4846                 if (rc)
4847                         return rc;
4848         }
4849
4850         bnxt_config_vf_req_fwd(bp);
4851
4852         rc = bnxt_hwrm_func_driver_register(bp);
4853         if (rc) {
4854                 PMD_DRV_LOG(ERR, "Failed to register driver");
4855                 return -EBUSY;
4856         }
4857
4858         if (BNXT_PF(bp)) {
4859                 if (bp->pdev->max_vfs) {
4860                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4861                         if (rc) {
4862                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4863                                 return rc;
4864                         }
4865                 } else {
4866                         rc = bnxt_hwrm_allocate_pf_only(bp);
4867                         if (rc) {
4868                                 PMD_DRV_LOG(ERR,
4869                                             "Failed to allocate PF resources");
4870                                 return rc;
4871                         }
4872                 }
4873         }
4874
4875         rc = bnxt_alloc_mem(bp, reconfig_dev);
4876         if (rc)
4877                 return rc;
4878
4879         rc = bnxt_setup_int(bp);
4880         if (rc)
4881                 return rc;
4882
4883         rc = bnxt_request_int(bp);
4884         if (rc)
4885                 return rc;
4886
4887         rc = bnxt_init_ctx_mem(bp);
4888         if (rc) {
4889                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
4890                 return rc;
4891         }
4892
4893         return 0;
4894 }
4895
4896 static int
4897 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4898                           const char *value, void *opaque_arg)
4899 {
4900         struct bnxt *bp = opaque_arg;
4901         unsigned long truflow;
4902         char *end = NULL;
4903
4904         if (!value || !opaque_arg) {
4905                 PMD_DRV_LOG(ERR,
4906                             "Invalid parameter passed to truflow devargs.\n");
4907                 return -EINVAL;
4908         }
4909
4910         truflow = strtoul(value, &end, 10);
4911         if (end == NULL || *end != '\0' ||
4912             (truflow == ULONG_MAX && errno == ERANGE)) {
4913                 PMD_DRV_LOG(ERR,
4914                             "Invalid parameter passed to truflow devargs.\n");
4915                 return -EINVAL;
4916         }
4917
4918         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4919                 PMD_DRV_LOG(ERR,
4920                             "Invalid value passed to truflow devargs.\n");
4921                 return -EINVAL;
4922         }
4923
4924         if (truflow) {
4925                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
4926                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4927         } else {
4928                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
4929                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
4930         }
4931
4932         return 0;
4933 }
4934
4935 static int
4936 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
4937                              const char *value, void *opaque_arg)
4938 {
4939         struct bnxt *bp = opaque_arg;
4940         unsigned long flow_xstat;
4941         char *end = NULL;
4942
4943         if (!value || !opaque_arg) {
4944                 PMD_DRV_LOG(ERR,
4945                             "Invalid parameter passed to flow_xstat devarg.\n");
4946                 return -EINVAL;
4947         }
4948
4949         flow_xstat = strtoul(value, &end, 10);
4950         if (end == NULL || *end != '\0' ||
4951             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
4952                 PMD_DRV_LOG(ERR,
4953                             "Invalid parameter passed to flow_xstat devarg.\n");
4954                 return -EINVAL;
4955         }
4956
4957         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
4958                 PMD_DRV_LOG(ERR,
4959                             "Invalid value passed to flow_xstat devarg.\n");
4960                 return -EINVAL;
4961         }
4962
4963         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
4964         if (BNXT_FLOW_XSTATS_EN(bp))
4965                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
4966
4967         return 0;
4968 }
4969
4970 static int
4971 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
4972                                         const char *value, void *opaque_arg)
4973 {
4974         struct bnxt *bp = opaque_arg;
4975         unsigned long max_num_kflows;
4976         char *end = NULL;
4977
4978         if (!value || !opaque_arg) {
4979                 PMD_DRV_LOG(ERR,
4980                         "Invalid parameter passed to max_num_kflows devarg.\n");
4981                 return -EINVAL;
4982         }
4983
4984         max_num_kflows = strtoul(value, &end, 10);
4985         if (end == NULL || *end != '\0' ||
4986                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
4987                 PMD_DRV_LOG(ERR,
4988                         "Invalid parameter passed to max_num_kflows devarg.\n");
4989                 return -EINVAL;
4990         }
4991
4992         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
4993                 PMD_DRV_LOG(ERR,
4994                         "Invalid value passed to max_num_kflows devarg.\n");
4995                 return -EINVAL;
4996         }
4997
4998         bp->max_num_kflows = max_num_kflows;
4999         if (bp->max_num_kflows)
5000                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5001                                 max_num_kflows);
5002
5003         return 0;
5004 }
5005
5006 static int
5007 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5008                             const char *value, void *opaque_arg)
5009 {
5010         struct bnxt_representor *vfr_bp = opaque_arg;
5011         unsigned long rep_is_pf;
5012         char *end = NULL;
5013
5014         if (!value || !opaque_arg) {
5015                 PMD_DRV_LOG(ERR,
5016                             "Invalid parameter passed to rep_is_pf devargs.\n");
5017                 return -EINVAL;
5018         }
5019
5020         rep_is_pf = strtoul(value, &end, 10);
5021         if (end == NULL || *end != '\0' ||
5022             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5023                 PMD_DRV_LOG(ERR,
5024                             "Invalid parameter passed to rep_is_pf devargs.\n");
5025                 return -EINVAL;
5026         }
5027
5028         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5029                 PMD_DRV_LOG(ERR,
5030                             "Invalid value passed to rep_is_pf devargs.\n");
5031                 return -EINVAL;
5032         }
5033
5034         vfr_bp->flags |= rep_is_pf;
5035         if (BNXT_REP_PF(vfr_bp))
5036                 PMD_DRV_LOG(INFO, "PF representor\n");
5037         else
5038                 PMD_DRV_LOG(INFO, "VF representor\n");
5039
5040         return 0;
5041 }
5042
5043 static int
5044 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5045                                const char *value, void *opaque_arg)
5046 {
5047         struct bnxt_representor *vfr_bp = opaque_arg;
5048         unsigned long rep_based_pf;
5049         char *end = NULL;
5050
5051         if (!value || !opaque_arg) {
5052                 PMD_DRV_LOG(ERR,
5053                             "Invalid parameter passed to rep_based_pf "
5054                             "devargs.\n");
5055                 return -EINVAL;
5056         }
5057
5058         rep_based_pf = strtoul(value, &end, 10);
5059         if (end == NULL || *end != '\0' ||
5060             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5061                 PMD_DRV_LOG(ERR,
5062                             "Invalid parameter passed to rep_based_pf "
5063                             "devargs.\n");
5064                 return -EINVAL;
5065         }
5066
5067         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5068                 PMD_DRV_LOG(ERR,
5069                             "Invalid value passed to rep_based_pf devargs.\n");
5070                 return -EINVAL;
5071         }
5072
5073         vfr_bp->rep_based_pf = rep_based_pf;
5074         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5075
5076         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5077
5078         return 0;
5079 }
5080
5081 static int
5082 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5083                             const char *value, void *opaque_arg)
5084 {
5085         struct bnxt_representor *vfr_bp = opaque_arg;
5086         unsigned long rep_q_r2f;
5087         char *end = NULL;
5088
5089         if (!value || !opaque_arg) {
5090                 PMD_DRV_LOG(ERR,
5091                             "Invalid parameter passed to rep_q_r2f "
5092                             "devargs.\n");
5093                 return -EINVAL;
5094         }
5095
5096         rep_q_r2f = strtoul(value, &end, 10);
5097         if (end == NULL || *end != '\0' ||
5098             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5099                 PMD_DRV_LOG(ERR,
5100                             "Invalid parameter passed to rep_q_r2f "
5101                             "devargs.\n");
5102                 return -EINVAL;
5103         }
5104
5105         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5106                 PMD_DRV_LOG(ERR,
5107                             "Invalid value passed to rep_q_r2f devargs.\n");
5108                 return -EINVAL;
5109         }
5110
5111         vfr_bp->rep_q_r2f = rep_q_r2f;
5112         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5113         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5114
5115         return 0;
5116 }
5117
5118 static int
5119 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5120                             const char *value, void *opaque_arg)
5121 {
5122         struct bnxt_representor *vfr_bp = opaque_arg;
5123         unsigned long rep_q_f2r;
5124         char *end = NULL;
5125
5126         if (!value || !opaque_arg) {
5127                 PMD_DRV_LOG(ERR,
5128                             "Invalid parameter passed to rep_q_f2r "
5129                             "devargs.\n");
5130                 return -EINVAL;
5131         }
5132
5133         rep_q_f2r = strtoul(value, &end, 10);
5134         if (end == NULL || *end != '\0' ||
5135             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5136                 PMD_DRV_LOG(ERR,
5137                             "Invalid parameter passed to rep_q_f2r "
5138                             "devargs.\n");
5139                 return -EINVAL;
5140         }
5141
5142         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5143                 PMD_DRV_LOG(ERR,
5144                             "Invalid value passed to rep_q_f2r devargs.\n");
5145                 return -EINVAL;
5146         }
5147
5148         vfr_bp->rep_q_f2r = rep_q_f2r;
5149         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5150         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5151
5152         return 0;
5153 }
5154
5155 static int
5156 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5157                              const char *value, void *opaque_arg)
5158 {
5159         struct bnxt_representor *vfr_bp = opaque_arg;
5160         unsigned long rep_fc_r2f;
5161         char *end = NULL;
5162
5163         if (!value || !opaque_arg) {
5164                 PMD_DRV_LOG(ERR,
5165                             "Invalid parameter passed to rep_fc_r2f "
5166                             "devargs.\n");
5167                 return -EINVAL;
5168         }
5169
5170         rep_fc_r2f = strtoul(value, &end, 10);
5171         if (end == NULL || *end != '\0' ||
5172             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5173                 PMD_DRV_LOG(ERR,
5174                             "Invalid parameter passed to rep_fc_r2f "
5175                             "devargs.\n");
5176                 return -EINVAL;
5177         }
5178
5179         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5180                 PMD_DRV_LOG(ERR,
5181                             "Invalid value passed to rep_fc_r2f devargs.\n");
5182                 return -EINVAL;
5183         }
5184
5185         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5186         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5187         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5188
5189         return 0;
5190 }
5191
5192 static int
5193 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5194                              const char *value, void *opaque_arg)
5195 {
5196         struct bnxt_representor *vfr_bp = opaque_arg;
5197         unsigned long rep_fc_f2r;
5198         char *end = NULL;
5199
5200         if (!value || !opaque_arg) {
5201                 PMD_DRV_LOG(ERR,
5202                             "Invalid parameter passed to rep_fc_f2r "
5203                             "devargs.\n");
5204                 return -EINVAL;
5205         }
5206
5207         rep_fc_f2r = strtoul(value, &end, 10);
5208         if (end == NULL || *end != '\0' ||
5209             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5210                 PMD_DRV_LOG(ERR,
5211                             "Invalid parameter passed to rep_fc_f2r "
5212                             "devargs.\n");
5213                 return -EINVAL;
5214         }
5215
5216         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5217                 PMD_DRV_LOG(ERR,
5218                             "Invalid value passed to rep_fc_f2r devargs.\n");
5219                 return -EINVAL;
5220         }
5221
5222         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5223         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5224         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5225
5226         return 0;
5227 }
5228
5229 static void
5230 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5231 {
5232         struct rte_kvargs *kvlist;
5233
5234         if (devargs == NULL)
5235                 return;
5236
5237         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5238         if (kvlist == NULL)
5239                 return;
5240
5241         /*
5242          * Handler for "truflow" devarg.
5243          * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5244          */
5245         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5246                            bnxt_parse_devarg_truflow, bp);
5247
5248         /*
5249          * Handler for "flow_xstat" devarg.
5250          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5251          */
5252         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5253                            bnxt_parse_devarg_flow_xstat, bp);
5254
5255         /*
5256          * Handler for "max_num_kflows" devarg.
5257          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5258          */
5259         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5260                            bnxt_parse_devarg_max_num_kflows, bp);
5261
5262         rte_kvargs_free(kvlist);
5263 }
5264
5265 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5266 {
5267         int rc = 0;
5268
5269         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5270                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5271                 if (rc)
5272                         PMD_DRV_LOG(ERR,
5273                                     "Failed to alloc switch domain: %d\n", rc);
5274                 else
5275                         PMD_DRV_LOG(INFO,
5276                                     "Switch domain allocated %d\n",
5277                                     bp->switch_domain_id);
5278         }
5279
5280         return rc;
5281 }
5282
5283 /* Allocate and initialize various fields in bnxt struct that
5284  * need to be allocated/destroyed only once in the lifetime of the driver
5285  */
5286 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5287 {
5288         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5289         struct bnxt *bp = eth_dev->data->dev_private;
5290         int rc = 0;
5291
5292         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5293
5294         if (bnxt_vf_pciid(pci_dev->id.device_id))
5295                 bp->flags |= BNXT_FLAG_VF;
5296
5297         if (bnxt_p5_device(pci_dev->id.device_id))
5298                 bp->flags |= BNXT_FLAG_CHIP_P5;
5299
5300         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5301             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5302             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5303             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5304                 bp->flags |= BNXT_FLAG_STINGRAY;
5305
5306         if (BNXT_TRUFLOW_EN(bp)) {
5307                 /* extra mbuf field is required to store CFA code from mark */
5308                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5309                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5310                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5311                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5312                 };
5313                 bnxt_cfa_code_dynfield_offset =
5314                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5315                 if (bnxt_cfa_code_dynfield_offset < 0) {
5316                         PMD_DRV_LOG(ERR,
5317                             "Failed to register mbuf field for TruFlow mark\n");
5318                         return -rte_errno;
5319                 }
5320         }
5321
5322         rc = bnxt_map_pci_bars(eth_dev);
5323         if (rc) {
5324                 PMD_DRV_LOG(ERR,
5325                             "Failed to initialize board rc: %x\n", rc);
5326                 return rc;
5327         }
5328
5329         rc = bnxt_alloc_pf_info(bp);
5330         if (rc)
5331                 return rc;
5332
5333         rc = bnxt_alloc_link_info(bp);
5334         if (rc)
5335                 return rc;
5336
5337         rc = bnxt_alloc_parent_info(bp);
5338         if (rc)
5339                 return rc;
5340
5341         rc = bnxt_alloc_hwrm_resources(bp);
5342         if (rc) {
5343                 PMD_DRV_LOG(ERR,
5344                             "Failed to allocate hwrm resource rc: %x\n", rc);
5345                 return rc;
5346         }
5347         rc = bnxt_alloc_leds_info(bp);
5348         if (rc)
5349                 return rc;
5350
5351         rc = bnxt_alloc_cos_queues(bp);
5352         if (rc)
5353                 return rc;
5354
5355         rc = bnxt_init_locks(bp);
5356         if (rc)
5357                 return rc;
5358
5359         rc = bnxt_alloc_switch_domain(bp);
5360         if (rc)
5361                 return rc;
5362
5363         return rc;
5364 }
5365
5366 static int
5367 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5368 {
5369         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5370         static int version_printed;
5371         struct bnxt *bp;
5372         int rc;
5373
5374         if (version_printed++ == 0)
5375                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5376
5377         eth_dev->dev_ops = &bnxt_dev_ops;
5378         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5379         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5380         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5381         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5382         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5383
5384         /*
5385          * For secondary processes, we don't initialise any further
5386          * as primary has already done this work.
5387          */
5388         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5389                 return 0;
5390
5391         rte_eth_copy_pci_info(eth_dev, pci_dev);
5392         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5393
5394         bp = eth_dev->data->dev_private;
5395
5396         /* Parse dev arguments passed on when starting the DPDK application. */
5397         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5398
5399         rc = bnxt_drv_init(eth_dev);
5400         if (rc)
5401                 goto error_free;
5402
5403         rc = bnxt_init_resources(bp, false);
5404         if (rc)
5405                 goto error_free;
5406
5407         rc = bnxt_alloc_stats_mem(bp);
5408         if (rc)
5409                 goto error_free;
5410
5411         PMD_DRV_LOG(INFO,
5412                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5413                     pci_dev->mem_resource[0].phys_addr,
5414                     pci_dev->mem_resource[0].addr);
5415
5416         return 0;
5417
5418 error_free:
5419         bnxt_dev_uninit(eth_dev);
5420         return rc;
5421 }
5422
5423
5424 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5425 {
5426         if (!ctx)
5427                 return;
5428
5429         if (ctx->va)
5430                 rte_free(ctx->va);
5431
5432         ctx->va = NULL;
5433         ctx->dma = RTE_BAD_IOVA;
5434         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5435 }
5436
5437 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5438 {
5439         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5440                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5441                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5442                                   bp->flow_stat->max_fc,
5443                                   false);
5444
5445         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5446                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5447                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5448                                   bp->flow_stat->max_fc,
5449                                   false);
5450
5451         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5452                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5453         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5454
5455         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5456                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5457         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5458
5459         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5460                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5461         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5462
5463         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5464                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5465         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5466 }
5467
5468 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5469 {
5470         bnxt_unregister_fc_ctx_mem(bp);
5471
5472         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5473         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5474         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5475         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5476 }
5477
5478 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5479 {
5480         if (BNXT_FLOW_XSTATS_EN(bp))
5481                 bnxt_uninit_fc_ctx_mem(bp);
5482 }
5483
5484 static void
5485 bnxt_free_error_recovery_info(struct bnxt *bp)
5486 {
5487         rte_free(bp->recovery_info);
5488         bp->recovery_info = NULL;
5489         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5490 }
5491
5492 static int
5493 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5494 {
5495         int rc;
5496
5497         bnxt_free_int(bp);
5498         bnxt_free_mem(bp, reconfig_dev);
5499
5500         bnxt_hwrm_func_buf_unrgtr(bp);
5501         rte_free(bp->pf->vf_req_buf);
5502
5503         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5504         bp->flags &= ~BNXT_FLAG_REGISTERED;
5505         bnxt_free_ctx_mem(bp);
5506         if (!reconfig_dev) {
5507                 bnxt_free_hwrm_resources(bp);
5508                 bnxt_free_error_recovery_info(bp);
5509         }
5510
5511         bnxt_uninit_ctx_mem(bp);
5512
5513         bnxt_free_flow_stats_info(bp);
5514         bnxt_free_rep_info(bp);
5515         rte_free(bp->ptp_cfg);
5516         bp->ptp_cfg = NULL;
5517         return rc;
5518 }
5519
5520 static int
5521 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5522 {
5523         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5524                 return -EPERM;
5525
5526         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5527
5528         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5529                 bnxt_dev_close_op(eth_dev);
5530
5531         return 0;
5532 }
5533
5534 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5535 {
5536         struct bnxt *bp = eth_dev->data->dev_private;
5537         struct rte_eth_dev *vf_rep_eth_dev;
5538         int ret = 0, i;
5539
5540         if (!bp)
5541                 return -EINVAL;
5542
5543         for (i = 0; i < bp->num_reps; i++) {
5544                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5545                 if (!vf_rep_eth_dev)
5546                         continue;
5547                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5548                             vf_rep_eth_dev->data->port_id);
5549                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5550         }
5551         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5552                     eth_dev->data->port_id);
5553         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5554
5555         return ret;
5556 }
5557
5558 static void bnxt_free_rep_info(struct bnxt *bp)
5559 {
5560         rte_free(bp->rep_info);
5561         bp->rep_info = NULL;
5562         rte_free(bp->cfa_code_map);
5563         bp->cfa_code_map = NULL;
5564 }
5565
5566 static int bnxt_init_rep_info(struct bnxt *bp)
5567 {
5568         int i = 0, rc;
5569
5570         if (bp->rep_info)
5571                 return 0;
5572
5573         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5574                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5575                                    0);
5576         if (!bp->rep_info) {
5577                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5578                 return -ENOMEM;
5579         }
5580         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5581                                        sizeof(*bp->cfa_code_map) *
5582                                        BNXT_MAX_CFA_CODE, 0);
5583         if (!bp->cfa_code_map) {
5584                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5585                 bnxt_free_rep_info(bp);
5586                 return -ENOMEM;
5587         }
5588
5589         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5590                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5591
5592         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5593         if (rc) {
5594                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5595                 bnxt_free_rep_info(bp);
5596                 return rc;
5597         }
5598
5599         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5600         if (rc) {
5601                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5602                 bnxt_free_rep_info(bp);
5603                 return rc;
5604         }
5605
5606         return rc;
5607 }
5608
5609 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5610                                struct rte_eth_devargs *eth_da,
5611                                struct rte_eth_dev *backing_eth_dev,
5612                                const char *dev_args)
5613 {
5614         struct rte_eth_dev *vf_rep_eth_dev;
5615         char name[RTE_ETH_NAME_MAX_LEN];
5616         struct bnxt *backing_bp;
5617         uint16_t num_rep;
5618         int i, ret = 0;
5619         struct rte_kvargs *kvlist = NULL;
5620
5621         num_rep = eth_da->nb_representor_ports;
5622         if (num_rep > BNXT_MAX_VF_REPS) {
5623                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5624                             num_rep, BNXT_MAX_VF_REPS);
5625                 return -EINVAL;
5626         }
5627
5628         if (num_rep >= RTE_MAX_ETHPORTS) {
5629                 PMD_DRV_LOG(ERR,
5630                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5631                             num_rep, RTE_MAX_ETHPORTS);
5632                 return -EINVAL;
5633         }
5634
5635         backing_bp = backing_eth_dev->data->dev_private;
5636
5637         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5638                 PMD_DRV_LOG(ERR,
5639                             "Not a PF or trusted VF. No Representor support\n");
5640                 /* Returning an error is not an option.
5641                  * Applications are not handling this correctly
5642                  */
5643                 return 0;
5644         }
5645
5646         if (bnxt_init_rep_info(backing_bp))
5647                 return 0;
5648
5649         for (i = 0; i < num_rep; i++) {
5650                 struct bnxt_representor representor = {
5651                         .vf_id = eth_da->representor_ports[i],
5652                         .switch_domain_id = backing_bp->switch_domain_id,
5653                         .parent_dev = backing_eth_dev
5654                 };
5655
5656                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5657                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5658                                     representor.vf_id, BNXT_MAX_VF_REPS);
5659                         continue;
5660                 }
5661
5662                 /* representor port net_bdf_port */
5663                 snprintf(name, sizeof(name), "net_%s_representor_%d",
5664                          pci_dev->device.name, eth_da->representor_ports[i]);
5665
5666                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5667                 if (kvlist) {
5668                         /*
5669                          * Handler for "rep_is_pf" devarg.
5670                          * Invoked as for ex: "-a 000:00:0d.0,
5671                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5672                          */
5673                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5674                                                  bnxt_parse_devarg_rep_is_pf,
5675                                                  (void *)&representor);
5676                         if (ret) {
5677                                 ret = -EINVAL;
5678                                 goto err;
5679                         }
5680                         /*
5681                          * Handler for "rep_based_pf" devarg.
5682                          * Invoked as for ex: "-a 000:00:0d.0,
5683                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5684                          */
5685                         ret = rte_kvargs_process(kvlist,
5686                                                  BNXT_DEVARG_REP_BASED_PF,
5687                                                  bnxt_parse_devarg_rep_based_pf,
5688                                                  (void *)&representor);
5689                         if (ret) {
5690                                 ret = -EINVAL;
5691                                 goto err;
5692                         }
5693                         /*
5694                          * Handler for "rep_based_pf" devarg.
5695                          * Invoked as for ex: "-a 000:00:0d.0,
5696                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5697                          */
5698                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5699                                                  bnxt_parse_devarg_rep_q_r2f,
5700                                                  (void *)&representor);
5701                         if (ret) {
5702                                 ret = -EINVAL;
5703                                 goto err;
5704                         }
5705                         /*
5706                          * Handler for "rep_based_pf" devarg.
5707                          * Invoked as for ex: "-a 000:00:0d.0,
5708                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5709                          */
5710                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5711                                                  bnxt_parse_devarg_rep_q_f2r,
5712                                                  (void *)&representor);
5713                         if (ret) {
5714                                 ret = -EINVAL;
5715                                 goto err;
5716                         }
5717                         /*
5718                          * Handler for "rep_based_pf" devarg.
5719                          * Invoked as for ex: "-a 000:00:0d.0,
5720                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5721                          */
5722                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5723                                                  bnxt_parse_devarg_rep_fc_r2f,
5724                                                  (void *)&representor);
5725                         if (ret) {
5726                                 ret = -EINVAL;
5727                                 goto err;
5728                         }
5729                         /*
5730                          * Handler for "rep_based_pf" devarg.
5731                          * Invoked as for ex: "-a 000:00:0d.0,
5732                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5733                          */
5734                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5735                                                  bnxt_parse_devarg_rep_fc_f2r,
5736                                                  (void *)&representor);
5737                         if (ret) {
5738                                 ret = -EINVAL;
5739                                 goto err;
5740                         }
5741                 }
5742
5743                 ret = rte_eth_dev_create(&pci_dev->device, name,
5744                                          sizeof(struct bnxt_representor),
5745                                          NULL, NULL,
5746                                          bnxt_representor_init,
5747                                          &representor);
5748                 if (ret) {
5749                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5750                                     "representor %s.", name);
5751                         goto err;
5752                 }
5753
5754                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
5755                 if (!vf_rep_eth_dev) {
5756                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5757                                     " for VF-Rep: %s.", name);
5758                         ret = -ENODEV;
5759                         goto err;
5760                 }
5761
5762                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
5763                             backing_eth_dev->data->port_id);
5764                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5765                                                          vf_rep_eth_dev;
5766                 backing_bp->num_reps++;
5767
5768         }
5769
5770         rte_kvargs_free(kvlist);
5771         return 0;
5772
5773 err:
5774         /* If num_rep > 1, then rollback already created
5775          * ports, since we'll be failing the probe anyway
5776          */
5777         if (num_rep > 1)
5778                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5779         rte_errno = -ret;
5780         rte_kvargs_free(kvlist);
5781
5782         return ret;
5783 }
5784
5785 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5786                           struct rte_pci_device *pci_dev)
5787 {
5788         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5789         struct rte_eth_dev *backing_eth_dev;
5790         uint16_t num_rep;
5791         int ret = 0;
5792
5793         if (pci_dev->device.devargs) {
5794                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5795                                             &eth_da);
5796                 if (ret)
5797                         return ret;
5798         }
5799
5800         num_rep = eth_da.nb_representor_ports;
5801         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5802                     num_rep);
5803
5804         /* We could come here after first level of probe is already invoked
5805          * as part of an application bringup(OVS-DPDK vswitchd), so first check
5806          * for already allocated eth_dev for the backing device (PF/Trusted VF)
5807          */
5808         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5809         if (backing_eth_dev == NULL) {
5810                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5811                                          sizeof(struct bnxt),
5812                                          eth_dev_pci_specific_init, pci_dev,
5813                                          bnxt_dev_init, NULL);
5814
5815                 if (ret || !num_rep)
5816                         return ret;
5817
5818                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5819         }
5820         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
5821                     backing_eth_dev->data->port_id);
5822
5823         if (!num_rep)
5824                 return ret;
5825
5826         /* probe representor ports now */
5827         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
5828                                   pci_dev->device.devargs->args);
5829
5830         return ret;
5831 }
5832
5833 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5834 {
5835         struct rte_eth_dev *eth_dev;
5836
5837         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5838         if (!eth_dev)
5839                 return 0; /* Invoked typically only by OVS-DPDK, by the
5840                            * time it comes here the eth_dev is already
5841                            * deleted by rte_eth_dev_close(), so returning
5842                            * +ve value will at least help in proper cleanup
5843                            */
5844
5845         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
5846         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5847                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5848                         return rte_eth_dev_destroy(eth_dev,
5849                                                    bnxt_representor_uninit);
5850                 else
5851                         return rte_eth_dev_destroy(eth_dev,
5852                                                    bnxt_dev_uninit);
5853         } else {
5854                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5855         }
5856 }
5857
5858 static struct rte_pci_driver bnxt_rte_pmd = {
5859         .id_table = bnxt_pci_id_map,
5860         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5861                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5862                                                   * and OVS-DPDK
5863                                                   */
5864         .probe = bnxt_pci_probe,
5865         .remove = bnxt_pci_remove,
5866 };
5867
5868 static bool
5869 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5870 {
5871         if (strcmp(dev->device->driver->name, drv->driver.name))
5872                 return false;
5873
5874         return true;
5875 }
5876
5877 bool is_bnxt_supported(struct rte_eth_dev *dev)
5878 {
5879         return is_device_supported(dev, &bnxt_rte_pmd);
5880 }
5881
5882 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
5883 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5884 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5885 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");