drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_cpr.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30 #include "bnxt_util.h"
  31
  32 #define DRV_MODULE_NAME         "bnxt"
  33 static const char bnxt_version[] =
  34         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  35 int bnxt_logtype_driver;
  36
  37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  38
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  43 #define BROADCOM_DEV_ID_57301 0x16c8
  44 #define BROADCOM_DEV_ID_57302 0x16c9
  45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  48 #define BROADCOM_DEV_ID_NS2 0x16cd
  49 #define BROADCOM_DEV_ID_57311 0x16ce
  50 #define BROADCOM_DEV_ID_57312 0x16cf
  51 #define BROADCOM_DEV_ID_57402 0x16d0
  52 #define BROADCOM_DEV_ID_57404 0x16d1
  53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  57 #define BROADCOM_DEV_ID_57412 0x16d6
  58 #define BROADCOM_DEV_ID_57414 0x16d7
  59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  62 #define BROADCOM_DEV_ID_57412_MF 0x16de
  63 #define BROADCOM_DEV_ID_57314 0x16df
  64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  75 #define BROADCOM_DEV_ID_57508 0x1750
  76 #define BROADCOM_DEV_ID_57504 0x1751
  77 #define BROADCOM_DEV_ID_57502 0x1752
  78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
  79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
  80 #define BROADCOM_DEV_ID_58802 0xd802
  81 #define BROADCOM_DEV_ID_58804 0xd804
  82 #define BROADCOM_DEV_ID_58808 0x16f0
  83 #define BROADCOM_DEV_ID_58802_VF 0xd800
  84
  85 static const struct rte_pci_id bnxt_pci_id_map[] = {
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  87                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  89                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 131         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
 132         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
 133         { .vendor_id = 0, /* sentinel */ },
 134 };
 135
 136 #define BNXT_ETH_RSS_SUPPORT (  \
 137         ETH_RSS_IPV4 |          \
 138         ETH_RSS_NONFRAG_IPV4_TCP |      \
 139         ETH_RSS_NONFRAG_IPV4_UDP |      \
 140         ETH_RSS_IPV6 |          \
 141         ETH_RSS_NONFRAG_IPV6_TCP |      \
 142         ETH_RSS_NONFRAG_IPV6_UDP)
 143
 144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 145                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 146                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 147                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 148                                      DEV_TX_OFFLOAD_TCP_TSO | \
 149                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 150                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 152                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 153                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 154                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 155                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 156
 157 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 158                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 159                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 160                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 161                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 162                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 163                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 164                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 165                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 166                                      DEV_RX_OFFLOAD_TCP_LRO)
 167
 168 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 169 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 170 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 171 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 172 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 173 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 174 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 175
 176 int is_bnxt_in_error(struct bnxt *bp)
 177 {
 178         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 179                 return -EIO;
 180         if (bp->flags & BNXT_FLAG_FW_RESET)
 181                 return -EBUSY;
 182
 183         return 0;
 184 }
 185
 186 /***********************/
 187
 188 /*
 189  * High level utility functions
 190  */
 191
 192 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 193 {
 194         if (!BNXT_CHIP_THOR(bp))
 195                 return 1;
 196
 197         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 198                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 199                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 200 }
 201
 202 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 203 {
 204         if (!BNXT_CHIP_THOR(bp))
 205                 return HW_HASH_INDEX_SIZE;
 206
 207         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 208 }
 209
 210 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 211 {
 212         bnxt_free_filter_mem(bp);
 213         bnxt_free_vnic_attributes(bp);
 214         bnxt_free_vnic_mem(bp);
 215
 216         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 217          * If the number of rings change across fw update,
 218          * we don't have much choice except to warn the user.
 219          */
 220         if (!reconfig) {
 221                 bnxt_free_stats(bp);
 222                 bnxt_free_tx_rings(bp);
 223                 bnxt_free_rx_rings(bp);
 224         }
 225         bnxt_free_async_cp_ring(bp);
 226 }
 227
 228 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 229 {
 230         int rc;
 231
 232         rc = bnxt_alloc_ring_grps(bp);
 233         if (rc)
 234                 goto alloc_mem_err;
 235
 236         rc = bnxt_alloc_async_ring_struct(bp);
 237         if (rc)
 238                 goto alloc_mem_err;
 239
 240         rc = bnxt_alloc_vnic_mem(bp);
 241         if (rc)
 242                 goto alloc_mem_err;
 243
 244         rc = bnxt_alloc_vnic_attributes(bp);
 245         if (rc)
 246                 goto alloc_mem_err;
 247
 248         rc = bnxt_alloc_filter_mem(bp);
 249         if (rc)
 250                 goto alloc_mem_err;
 251
 252         rc = bnxt_alloc_async_cp_ring(bp);
 253         if (rc)
 254                 goto alloc_mem_err;
 255
 256         return 0;
 257
 258 alloc_mem_err:
 259         bnxt_free_mem(bp, reconfig);
 260         return rc;
 261 }
 262
 263 static int bnxt_init_chip(struct bnxt *bp)
 264 {
 265         struct bnxt_rx_queue *rxq;
 266         struct rte_eth_link new;
 267         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 268         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 269         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 270         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 271         uint32_t intr_vector = 0;
 272         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 273         uint32_t vec = BNXT_MISC_VEC_ID;
 274         unsigned int i, j;
 275         int rc;
 276
 277         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 278                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 279                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 280                 bp->flags |= BNXT_FLAG_JUMBO;
 281         } else {
 282                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 283                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 284                 bp->flags &= ~BNXT_FLAG_JUMBO;
 285         }
 286
 287         /* THOR does not support ring groups.
 288          * But we will use the array to save RSS context IDs.
 289          */
 290         if (BNXT_CHIP_THOR(bp))
 291                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 292
 293         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 294         if (rc) {
 295                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 296                 goto err_out;
 297         }
 298
 299         rc = bnxt_alloc_hwrm_rings(bp);
 300         if (rc) {
 301                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 302                 goto err_out;
 303         }
 304
 305         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 306         if (rc) {
 307                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 308                 goto err_out;
 309         }
 310
 311         rc = bnxt_mq_rx_configure(bp);
 312         if (rc) {
 313                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 314                 goto err_out;
 315         }
 316
 317         /* VNIC configuration */
 318         for (i = 0; i < bp->nr_vnics; i++) {
 319                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 320                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 321
 322                 rc = bnxt_vnic_grp_alloc(bp, vnic);
 323                 if (rc)
 324                         goto err_out;
 325
 326                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 327                             i, vnic, vnic->fw_grp_ids);
 328
 329                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 330                 if (rc) {
 331                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 332                                 i, rc);
 333                         goto err_out;
 334                 }
 335
 336                 /* Alloc RSS context only if RSS mode is enabled */
 337                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 338                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 339
 340                         rc = 0;
 341                         for (j = 0; j < nr_ctxs; j++) {
 342                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 343                                 if (rc)
 344                                         break;
 345                         }
 346                         if (rc) {
 347                                 PMD_DRV_LOG(ERR,
 348                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 349                                   i, j, rc);
 350                                 goto err_out;
 351                         }
 352                         vnic->num_lb_ctxts = nr_ctxs;
 353                 }
 354
 355                 /*
 356                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 357                  * setting is not available at this time, it will not be
 358                  * configured correctly in the CFA.
 359                  */
 360                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 361                         vnic->vlan_strip = true;
 362                 else
 363                         vnic->vlan_strip = false;
 364
 365                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 366                 if (rc) {
 367                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 368                                 i, rc);
 369                         goto err_out;
 370                 }
 371
 372                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 373                 if (rc) {
 374                         PMD_DRV_LOG(ERR,
 375                                 "HWRM vnic %d filter failure rc: %x\n",
 376                                 i, rc);
 377                         goto err_out;
 378                 }
 379
 380                 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 381                         rxq = bp->eth_dev->data->rx_queues[j];
 382
 383                         PMD_DRV_LOG(DEBUG,
 384                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 385                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 386
 387                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 388                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 389                 }
 390
 391                 rc = bnxt_vnic_rss_configure(bp, vnic);
 392                 if (rc) {
 393                         PMD_DRV_LOG(ERR,
 394                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 395                         goto err_out;
 396                 }
 397
 398                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 399
 400                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 401                     DEV_RX_OFFLOAD_TCP_LRO)
 402                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 403                 else
 404                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 405         }
 406         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 407         if (rc) {
 408                 PMD_DRV_LOG(ERR,
 409                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 410                 goto err_out;
 411         }
 412
 413         /* check and configure queue intr-vector mapping */
 414         if ((rte_intr_cap_multiple(intr_handle) ||
 415              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 416             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 417                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 418                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 419                 if (intr_vector > bp->rx_cp_nr_rings) {
 420                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 421                                         bp->rx_cp_nr_rings);
 422                         return -ENOTSUP;
 423                 }
 424                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 425                 if (rc)
 426                         return rc;
 427         }
 428
 429         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 430                 intr_handle->intr_vec =
 431                         rte_zmalloc("intr_vec",
 432                                     bp->eth_dev->data->nb_rx_queues *
 433                                     sizeof(int), 0);
 434                 if (intr_handle->intr_vec == NULL) {
 435                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 436                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 437                         rc = -ENOMEM;
 438                         goto err_disable;
 439                 }
 440                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 441                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 442                          intr_handle->intr_vec, intr_handle->nb_efd,
 443                         intr_handle->max_intr);
 444                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 445                      queue_id++) {
 446                         intr_handle->intr_vec[queue_id] =
 447                                                         vec + BNXT_RX_VEC_START;
 448                         if (vec < base + intr_handle->nb_efd - 1)
 449                                 vec++;
 450                 }
 451         }
 452
 453         /* enable uio/vfio intr/eventfd mapping */
 454         rc = rte_intr_enable(intr_handle);
 455         if (rc)
 456                 goto err_free;
 457
 458         rc = bnxt_get_hwrm_link_config(bp, &new);
 459         if (rc) {
 460                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 461                 goto err_free;
 462         }
 463
 464         if (!bp->link_info.link_up) {
 465                 rc = bnxt_set_hwrm_link_config(bp, true);
 466                 if (rc) {
 467                         PMD_DRV_LOG(ERR,
 468                                 "HWRM link config failure rc: %x\n", rc);
 469                         goto err_free;
 470                 }
 471         }
 472         bnxt_print_link_info(bp->eth_dev);
 473
 474         return 0;
 475
 476 err_free:
 477         rte_free(intr_handle->intr_vec);
 478 err_disable:
 479         rte_intr_efd_disable(intr_handle);
 480 err_out:
 481         /* Some of the error status returned by FW may not be from errno.h */
 482         if (rc > 0)
 483                 rc = -EIO;
 484
 485         return rc;
 486 }
 487
 488 static int bnxt_shutdown_nic(struct bnxt *bp)
 489 {
 490         bnxt_free_all_hwrm_resources(bp);
 491         bnxt_free_all_filters(bp);
 492         bnxt_free_all_vnics(bp);
 493         return 0;
 494 }
 495
 496 static int bnxt_init_nic(struct bnxt *bp)
 497 {
 498         int rc;
 499
 500         if (BNXT_HAS_RING_GRPS(bp)) {
 501                 rc = bnxt_init_ring_grps(bp);
 502                 if (rc)
 503                         return rc;
 504         }
 505
 506         bnxt_init_vnics(bp);
 507         bnxt_init_filters(bp);
 508
 509         return 0;
 510 }
 511
 512 /*
 513  * Device configuration and status function
 514  */
 515
 516 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 517                                 struct rte_eth_dev_info *dev_info)
 518 {
 519         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 520         struct bnxt *bp = eth_dev->data->dev_private;
 521         uint16_t max_vnics, i, j, vpool, vrxq;
 522         unsigned int max_rx_rings;
 523         int rc;
 524
 525         rc = is_bnxt_in_error(bp);
 526         if (rc)
 527                 return rc;
 528
 529         /* MAC Specifics */
 530         dev_info->max_mac_addrs = bp->max_l2_ctx;
 531         dev_info->max_hash_mac_addrs = 0;
 532
 533         /* PF/VF specifics */
 534         if (BNXT_PF(bp))
 535                 dev_info->max_vfs = pdev->max_vfs;
 536
 537         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 538         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 539         dev_info->max_rx_queues = max_rx_rings;
 540         dev_info->max_tx_queues = max_rx_rings;
 541         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 542         dev_info->hash_key_size = 40;
 543         max_vnics = bp->max_vnics;
 544
 545         /* MTU specifics */
 546         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 547         dev_info->max_mtu = BNXT_MAX_MTU;
 548
 549         /* Fast path specifics */
 550         dev_info->min_rx_bufsize = 1;
 551         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 552
 553         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 554         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 555                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 556         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 557         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 558
 559         /* *INDENT-OFF* */
 560         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 561                 .rx_thresh = {
 562                         .pthresh = 8,
 563                         .hthresh = 8,
 564                         .wthresh = 0,
 565                 },
 566                 .rx_free_thresh = 32,
 567                 /* If no descriptors available, pkts are dropped by default */
 568                 .rx_drop_en = 1,
 569         };
 570
 571         dev_info->default_txconf = (struct rte_eth_txconf) {
 572                 .tx_thresh = {
 573                         .pthresh = 32,
 574                         .hthresh = 0,
 575                         .wthresh = 0,
 576                 },
 577                 .tx_free_thresh = 32,
 578                 .tx_rs_thresh = 32,
 579         };
 580         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 581
 582         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 583         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 584         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 585         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 586         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 587
 588         /* *INDENT-ON* */
 589
 590         /*
 591          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 592          *       need further investigation.
 593          */
 594
 595         /* VMDq resources */
 596         vpool = 64; /* ETH_64_POOLS */
 597         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 598         for (i = 0; i < 4; vpool >>= 1, i++) {
 599                 if (max_vnics > vpool) {
 600                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 601                                 if (dev_info->max_rx_queues > vrxq) {
 602                                         if (vpool > vrxq)
 603                                                 vpool = vrxq;
 604                                         goto found;
 605                                 }
 606                         }
 607                         /* Not enough resources to support VMDq */
 608                         break;
 609                 }
 610         }
 611         /* Not enough resources to support VMDq */
 612         vpool = 0;
 613         vrxq = 0;
 614 found:
 615         dev_info->max_vmdq_pools = vpool;
 616         dev_info->vmdq_queue_num = vrxq;
 617
 618         dev_info->vmdq_pool_base = 0;
 619         dev_info->vmdq_queue_base = 0;
 620
 621         return 0;
 622 }
 623
 624 /* Configure the device based on the configuration provided */
 625 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 626 {
 627         struct bnxt *bp = eth_dev->data->dev_private;
 628         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 629         int rc;
 630
 631         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 632         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 633         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 634         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 635
 636         rc = is_bnxt_in_error(bp);
 637         if (rc)
 638                 return rc;
 639
 640         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 641                 rc = bnxt_hwrm_check_vf_rings(bp);
 642                 if (rc) {
 643                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 644                         return -ENOSPC;
 645                 }
 646
 647                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 648                 if (rc) {
 649                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 650                         return -ENOSPC;
 651                 }
 652         } else {
 653                 /* legacy driver needs to get updated values */
 654                 rc = bnxt_hwrm_func_qcaps(bp);
 655                 if (rc) {
 656                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 657                         return rc;
 658                 }
 659         }
 660
 661         /* Inherit new configurations */
 662         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 663             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 664             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 665                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 666             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 667             bp->max_stat_ctx)
 668                 goto resource_error;
 669
 670         if (BNXT_HAS_RING_GRPS(bp) &&
 671             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 672                 goto resource_error;
 673
 674         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 675             bp->max_vnics < eth_dev->data->nb_rx_queues)
 676                 goto resource_error;
 677
 678         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 679         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 680
 681         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 682                 eth_dev->data->mtu =
 683                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 684                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 685                         BNXT_NUM_VLANS;
 686                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 687         }
 688         return 0;
 689
 690 resource_error:
 691         PMD_DRV_LOG(ERR,
 692                     "Insufficient resources to support requested config\n");
 693         PMD_DRV_LOG(ERR,
 694                     "Num Queues Requested: Tx %d, Rx %d\n",
 695                     eth_dev->data->nb_tx_queues,
 696                     eth_dev->data->nb_rx_queues);
 697         PMD_DRV_LOG(ERR,
 698                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 699                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 700                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 701         return -ENOSPC;
 702 }
 703
 704 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 705 {
 706         struct rte_eth_link *link = &eth_dev->data->dev_link;
 707
 708         if (link->link_status)
 709                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 710                         eth_dev->data->port_id,
 711                         (uint32_t)link->link_speed,
 712                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 713                         ("full-duplex") : ("half-duplex\n"));
 714         else
 715                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 716                         eth_dev->data->port_id);
 717 }
 718
 719 /*
 720  * Determine whether the current configuration requires support for scattered
 721  * receive; return 1 if scattered receive is required and 0 if not.
 722  */
 723 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 724 {
 725         uint16_t buf_size;
 726         int i;
 727
 728         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 729                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 730
 731                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 732                                       RTE_PKTMBUF_HEADROOM);
 733                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 734                         return 1;
 735         }
 736         return 0;
 737 }
 738
 739 static eth_rx_burst_t
 740 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 741 {
 742 #ifdef RTE_ARCH_X86
 743 #ifndef RTE_LIBRTE_IEEE1588
 744         /*
 745          * Vector mode receive can be enabled only if scatter rx is not
 746          * in use and rx offloads are limited to VLAN stripping and
 747          * CRC stripping.
 748          */
 749         if (!eth_dev->data->scattered_rx &&
 750             !(eth_dev->data->dev_conf.rxmode.offloads &
 751               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 752                 DEV_RX_OFFLOAD_KEEP_CRC |
 753                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 754                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 755                 DEV_RX_OFFLOAD_UDP_CKSUM |
 756                 DEV_RX_OFFLOAD_TCP_CKSUM |
 757                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 758                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 759                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 760                             eth_dev->data->port_id);
 761                 return bnxt_recv_pkts_vec;
 762         }
 763         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 764                     eth_dev->data->port_id);
 765         PMD_DRV_LOG(INFO,
 766                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 767                     eth_dev->data->port_id,
 768                     eth_dev->data->scattered_rx,
 769                     eth_dev->data->dev_conf.rxmode.offloads);
 770 #endif
 771 #endif
 772         return bnxt_recv_pkts;
 773 }
 774
 775 static eth_tx_burst_t
 776 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 777 {
 778 #ifdef RTE_ARCH_X86
 779 #ifndef RTE_LIBRTE_IEEE1588
 780         /*
 781          * Vector mode transmit can be enabled only if not using scatter rx
 782          * or tx offloads.
 783          */
 784         if (!eth_dev->data->scattered_rx &&
 785             !eth_dev->data->dev_conf.txmode.offloads) {
 786                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 787                             eth_dev->data->port_id);
 788                 return bnxt_xmit_pkts_vec;
 789         }
 790         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 791                     eth_dev->data->port_id);
 792         PMD_DRV_LOG(INFO,
 793                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 794                     eth_dev->data->port_id,
 795                     eth_dev->data->scattered_rx,
 796                     eth_dev->data->dev_conf.txmode.offloads);
 797 #endif
 798 #endif
 799         return bnxt_xmit_pkts;
 800 }
 801
 802 static int bnxt_handle_if_change_status(struct bnxt *bp)
 803 {
 804         int rc;
 805
 806         /* Since fw has undergone a reset and lost all contexts,
 807          * set fatal flag to not issue hwrm during cleanup
 808          */
 809         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 810         bnxt_uninit_resources(bp, true);
 811
 812         /* clear fatal flag so that re-init happens */
 813         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 814         rc = bnxt_init_resources(bp, true);
 815
 816         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 817
 818         return rc;
 819 }
 820
 821 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 822 {
 823         struct bnxt *bp = eth_dev->data->dev_private;
 824         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 825         int vlan_mask = 0;
 826         int rc;
 827
 828         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 829                 PMD_DRV_LOG(ERR,
 830                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 831                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 832         }
 833
 834         bnxt_enable_int(bp);
 835         rc = bnxt_hwrm_if_change(bp, 1);
 836         if (!rc) {
 837                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 838                         rc = bnxt_handle_if_change_status(bp);
 839                         if (rc)
 840                                 return rc;
 841                 }
 842         }
 843
 844         rc = bnxt_init_chip(bp);
 845         if (rc)
 846                 goto error;
 847
 848         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 849
 850         bnxt_link_update_op(eth_dev, 1);
 851
 852         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 853                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 854         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 855                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 856         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 857         if (rc)
 858                 goto error;
 859
 860         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 861         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 862
 863         bp->flags |= BNXT_FLAG_INIT_DONE;
 864         eth_dev->data->dev_started = 1;
 865         bp->dev_stopped = 0;
 866         bnxt_schedule_fw_health_check(bp);
 867         return 0;
 868
 869 error:
 870         bnxt_hwrm_if_change(bp, 0);
 871         bnxt_shutdown_nic(bp);
 872         bnxt_free_tx_mbufs(bp);
 873         bnxt_free_rx_mbufs(bp);
 874         return rc;
 875 }
 876
 877 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 878 {
 879         struct bnxt *bp = eth_dev->data->dev_private;
 880         int rc = 0;
 881
 882         if (!bp->link_info.link_up)
 883                 rc = bnxt_set_hwrm_link_config(bp, true);
 884         if (!rc)
 885                 eth_dev->data->dev_link.link_status = 1;
 886
 887         bnxt_print_link_info(eth_dev);
 888         return 0;
 889 }
 890
 891 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 892 {
 893         struct bnxt *bp = eth_dev->data->dev_private;
 894
 895         eth_dev->data->dev_link.link_status = 0;
 896         bnxt_set_hwrm_link_config(bp, false);
 897         bp->link_info.link_up = 0;
 898
 899         return 0;
 900 }
 901
 902 /* Unload the driver, release resources */
 903 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 904 {
 905         struct bnxt *bp = eth_dev->data->dev_private;
 906         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 907         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 908
 909         eth_dev->data->dev_started = 0;
 910         /* Prevent crashes when queues are still in use */
 911         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 912         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 913
 914         bnxt_disable_int(bp);
 915
 916         /* disable uio/vfio intr/eventfd mapping */
 917         rte_intr_disable(intr_handle);
 918
 919         bnxt_cancel_fw_health_check(bp);
 920
 921         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 922         if (bp->eth_dev->data->dev_started) {
 923                 /* TBD: STOP HW queues DMA */
 924                 eth_dev->data->dev_link.link_status = 0;
 925         }
 926         bnxt_dev_set_link_down_op(eth_dev);
 927         /* Wait for link to be reset and the async notification to process. */
 928         rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
 929
 930         /* Clean queue intr-vector mapping */
 931         rte_intr_efd_disable(intr_handle);
 932         if (intr_handle->intr_vec != NULL) {
 933                 rte_free(intr_handle->intr_vec);
 934                 intr_handle->intr_vec = NULL;
 935         }
 936
 937         bnxt_hwrm_port_clr_stats(bp);
 938         bnxt_free_tx_mbufs(bp);
 939         bnxt_free_rx_mbufs(bp);
 940         /* Process any remaining notifications in default completion queue */
 941         bnxt_int_handler(eth_dev);
 942         bnxt_shutdown_nic(bp);
 943         bnxt_hwrm_if_change(bp, 0);
 944         bp->dev_stopped = 1;
 945 }
 946
 947 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 948 {
 949         struct bnxt *bp = eth_dev->data->dev_private;
 950
 951         if (bp->dev_stopped == 0)
 952                 bnxt_dev_stop_op(eth_dev);
 953
 954         if (eth_dev->data->mac_addrs != NULL) {
 955                 rte_free(eth_dev->data->mac_addrs);
 956                 eth_dev->data->mac_addrs = NULL;
 957         }
 958         if (bp->grp_info != NULL) {
 959                 rte_free(bp->grp_info);
 960                 bp->grp_info = NULL;
 961         }
 962
 963         bnxt_dev_uninit(eth_dev);
 964 }
 965
 966 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 967                                     uint32_t index)
 968 {
 969         struct bnxt *bp = eth_dev->data->dev_private;
 970         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 971         struct bnxt_vnic_info *vnic;
 972         struct bnxt_filter_info *filter, *temp_filter;
 973         uint32_t i;
 974
 975         if (is_bnxt_in_error(bp))
 976                 return;
 977
 978         /*
 979          * Loop through all VNICs from the specified filter flow pools to
 980          * remove the corresponding MAC addr filter
 981          */
 982         for (i = 0; i < bp->nr_vnics; i++) {
 983                 if (!(pool_mask & (1ULL << i)))
 984                         continue;
 985
 986                 vnic = &bp->vnic_info[i];
 987                 filter = STAILQ_FIRST(&vnic->filter);
 988                 while (filter) {
 989                         temp_filter = STAILQ_NEXT(filter, next);
 990                         if (filter->mac_index == index) {
 991                                 STAILQ_REMOVE(&vnic->filter, filter,
 992                                                 bnxt_filter_info, next);
 993                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 994                                 filter->mac_index = INVALID_MAC_INDEX;
 995                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 996                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 997                                                    filter, next);
 998                         }
 999                         filter = temp_filter;
1000                 }
1001         }
1002 }
1003
1004 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1005                                 struct rte_ether_addr *mac_addr,
1006                                 uint32_t index, uint32_t pool)
1007 {
1008         struct bnxt *bp = eth_dev->data->dev_private;
1009         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1010         struct bnxt_filter_info *filter;
1011         int rc = 0;
1012
1013         rc = is_bnxt_in_error(bp);
1014         if (rc)
1015                 return rc;
1016
1017         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1018                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1019                 return -ENOTSUP;
1020         }
1021
1022         if (!vnic) {
1023                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1024                 return -EINVAL;
1025         }
1026         /* Attach requested MAC address to the new l2_filter */
1027         STAILQ_FOREACH(filter, &vnic->filter, next) {
1028                 if (filter->mac_index == index) {
1029                         PMD_DRV_LOG(ERR,
1030                                 "MAC addr already existed for pool %d\n", pool);
1031                         return 0;
1032                 }
1033         }
1034         filter = bnxt_alloc_filter(bp);
1035         if (!filter) {
1036                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1037                 return -ENODEV;
1038         }
1039
1040         filter->mac_index = index;
1041         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1042         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1043
1044         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1045         if (!rc) {
1046                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1047         } else {
1048                 filter->mac_index = INVALID_MAC_INDEX;
1049                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1050                 bnxt_free_filter(bp, filter);
1051         }
1052
1053         return rc;
1054 }
1055
1056 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1057 {
1058         int rc = 0;
1059         struct bnxt *bp = eth_dev->data->dev_private;
1060         struct rte_eth_link new;
1061         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1062
1063         rc = is_bnxt_in_error(bp);
1064         if (rc)
1065                 return rc;
1066
1067         memset(&new, 0, sizeof(new));
1068         do {
1069                 /* Retrieve link info from hardware */
1070                 rc = bnxt_get_hwrm_link_config(bp, &new);
1071                 if (rc) {
1072                         new.link_speed = ETH_LINK_SPEED_100M;
1073                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1074                         PMD_DRV_LOG(ERR,
1075                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1076                         goto out;
1077                 }
1078
1079                 if (!wait_to_complete || new.link_status)
1080                         break;
1081
1082                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1083         } while (cnt--);
1084
1085 out:
1086         /* Timed out or success */
1087         if (new.link_status != eth_dev->data->dev_link.link_status ||
1088         new.link_speed != eth_dev->data->dev_link.link_speed) {
1089                 rte_eth_linkstatus_set(eth_dev, &new);
1090
1091                 _rte_eth_dev_callback_process(eth_dev,
1092                                               RTE_ETH_EVENT_INTR_LSC,
1093                                               NULL);
1094
1095                 bnxt_print_link_info(eth_dev);
1096         }
1097
1098         return rc;
1099 }
1100
1101 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1102 {
1103         struct bnxt *bp = eth_dev->data->dev_private;
1104         struct bnxt_vnic_info *vnic;
1105         uint32_t old_flags;
1106         int rc;
1107
1108         rc = is_bnxt_in_error(bp);
1109         if (rc)
1110                 return rc;
1111
1112         if (bp->vnic_info == NULL)
1113                 return 0;
1114
1115         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1116
1117         old_flags = vnic->flags;
1118         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1119         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1120         if (rc != 0)
1121                 vnic->flags = old_flags;
1122
1123         return rc;
1124 }
1125
1126 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1127 {
1128         struct bnxt *bp = eth_dev->data->dev_private;
1129         struct bnxt_vnic_info *vnic;
1130         uint32_t old_flags;
1131         int rc;
1132
1133         rc = is_bnxt_in_error(bp);
1134         if (rc)
1135                 return rc;
1136
1137         if (bp->vnic_info == NULL)
1138                 return 0;
1139
1140         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1141
1142         old_flags = vnic->flags;
1143         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1144         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1145         if (rc != 0)
1146                 vnic->flags = old_flags;
1147
1148         return rc;
1149 }
1150
1151 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1152 {
1153         struct bnxt *bp = eth_dev->data->dev_private;
1154         struct bnxt_vnic_info *vnic;
1155         uint32_t old_flags;
1156         int rc;
1157
1158         rc = is_bnxt_in_error(bp);
1159         if (rc)
1160                 return rc;
1161
1162         if (bp->vnic_info == NULL)
1163                 return 0;
1164
1165         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1166
1167         old_flags = vnic->flags;
1168         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1169         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1170         if (rc != 0)
1171                 vnic->flags = old_flags;
1172
1173         return rc;
1174 }
1175
1176 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1177 {
1178         struct bnxt *bp = eth_dev->data->dev_private;
1179         struct bnxt_vnic_info *vnic;
1180         uint32_t old_flags;
1181         int rc;
1182
1183         rc = is_bnxt_in_error(bp);
1184         if (rc)
1185                 return rc;
1186
1187         if (bp->vnic_info == NULL)
1188                 return 0;
1189
1190         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1191
1192         old_flags = vnic->flags;
1193         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1194         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1195         if (rc != 0)
1196                 vnic->flags = old_flags;
1197
1198         return rc;
1199 }
1200
1201 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1202 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1203 {
1204         if (qid >= bp->rx_nr_rings)
1205                 return NULL;
1206
1207         return bp->eth_dev->data->rx_queues[qid];
1208 }
1209
1210 /* Return rxq corresponding to a given rss table ring/group ID. */
1211 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1212 {
1213         struct bnxt_rx_queue *rxq;
1214         unsigned int i;
1215
1216         if (!BNXT_HAS_RING_GRPS(bp)) {
1217                 for (i = 0; i < bp->rx_nr_rings; i++) {
1218                         rxq = bp->eth_dev->data->rx_queues[i];
1219                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1220                                 return rxq->index;
1221                 }
1222         } else {
1223                 for (i = 0; i < bp->rx_nr_rings; i++) {
1224                         if (bp->grp_info[i].fw_grp_id == fwr)
1225                                 return i;
1226                 }
1227         }
1228
1229         return INVALID_HW_RING_ID;
1230 }
1231
1232 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1233                             struct rte_eth_rss_reta_entry64 *reta_conf,
1234                             uint16_t reta_size)
1235 {
1236         struct bnxt *bp = eth_dev->data->dev_private;
1237         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1238         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1239         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1240         uint16_t idx, sft;
1241         int i, rc;
1242
1243         rc = is_bnxt_in_error(bp);
1244         if (rc)
1245                 return rc;
1246
1247         if (!vnic->rss_table)
1248                 return -EINVAL;
1249
1250         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1251                 return -EINVAL;
1252
1253         if (reta_size != tbl_size) {
1254                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1255                         "(%d) must equal the size supported by the hardware "
1256                         "(%d)\n", reta_size, tbl_size);
1257                 return -EINVAL;
1258         }
1259
1260         for (i = 0; i < reta_size; i++) {
1261                 struct bnxt_rx_queue *rxq;
1262
1263                 idx = i / RTE_RETA_GROUP_SIZE;
1264                 sft = i % RTE_RETA_GROUP_SIZE;
1265
1266                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1267                         continue;
1268
1269                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1270                 if (!rxq) {
1271                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1272                         return -EINVAL;
1273                 }
1274
1275                 if (BNXT_CHIP_THOR(bp)) {
1276                         vnic->rss_table[i * 2] =
1277                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1278                         vnic->rss_table[i * 2 + 1] =
1279                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1280                 } else {
1281                         vnic->rss_table[i] =
1282                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1283                 }
1284
1285                 vnic->rss_table[i] =
1286                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1287         }
1288
1289         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1290         return 0;
1291 }
1292
1293 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1294                               struct rte_eth_rss_reta_entry64 *reta_conf,
1295                               uint16_t reta_size)
1296 {
1297         struct bnxt *bp = eth_dev->data->dev_private;
1298         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1299         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1300         uint16_t idx, sft, i;
1301         int rc;
1302
1303         rc = is_bnxt_in_error(bp);
1304         if (rc)
1305                 return rc;
1306
1307         /* Retrieve from the default VNIC */
1308         if (!vnic)
1309                 return -EINVAL;
1310         if (!vnic->rss_table)
1311                 return -EINVAL;
1312
1313         if (reta_size != tbl_size) {
1314                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1315                         "(%d) must equal the size supported by the hardware "
1316                         "(%d)\n", reta_size, tbl_size);
1317                 return -EINVAL;
1318         }
1319
1320         for (idx = 0, i = 0; i < reta_size; i++) {
1321                 idx = i / RTE_RETA_GROUP_SIZE;
1322                 sft = i % RTE_RETA_GROUP_SIZE;
1323
1324                 if (reta_conf[idx].mask & (1ULL << sft)) {
1325                         uint16_t qid;
1326
1327                         if (BNXT_CHIP_THOR(bp))
1328                                 qid = bnxt_rss_to_qid(bp,
1329                                                       vnic->rss_table[i * 2]);
1330                         else
1331                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1332
1333                         if (qid == INVALID_HW_RING_ID) {
1334                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1335                                 return -EINVAL;
1336                         }
1337                         reta_conf[idx].reta[sft] = qid;
1338                 }
1339         }
1340
1341         return 0;
1342 }
1343
1344 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1345                                    struct rte_eth_rss_conf *rss_conf)
1346 {
1347         struct bnxt *bp = eth_dev->data->dev_private;
1348         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1349         struct bnxt_vnic_info *vnic;
1350         int rc;
1351
1352         rc = is_bnxt_in_error(bp);
1353         if (rc)
1354                 return rc;
1355
1356         /*
1357          * If RSS enablement were different than dev_configure,
1358          * then return -EINVAL
1359          */
1360         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1361                 if (!rss_conf->rss_hf)
1362                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1363         } else {
1364                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1365                         return -EINVAL;
1366         }
1367
1368         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1369         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1370
1371         /* Update the default RSS VNIC(s) */
1372         vnic = &bp->vnic_info[0];
1373         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1374
1375         /*
1376          * Use the supplied key if the key length is
1377          * acceptable and the rss_key is not NULL
1378          */
1379         if (rss_conf->rss_key && rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1380                 memcpy(vnic->rss_hash_key,
1381                        rss_conf->rss_key,
1382                        rss_conf->rss_key_len);
1383
1384         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1385         return 0;
1386 }
1387
1388 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1389                                      struct rte_eth_rss_conf *rss_conf)
1390 {
1391         struct bnxt *bp = eth_dev->data->dev_private;
1392         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1393         int len, rc;
1394         uint32_t hash_types;
1395
1396         rc = is_bnxt_in_error(bp);
1397         if (rc)
1398                 return rc;
1399
1400         /* RSS configuration is the same for all VNICs */
1401         if (vnic && vnic->rss_hash_key) {
1402                 if (rss_conf->rss_key) {
1403                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1404                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1405                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1406                 }
1407
1408                 hash_types = vnic->hash_type;
1409                 rss_conf->rss_hf = 0;
1410                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1411                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1412                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1413                 }
1414                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1415                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1416                         hash_types &=
1417                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1418                 }
1419                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1420                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1421                         hash_types &=
1422                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1423                 }
1424                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1425                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1426                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1427                 }
1428                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1429                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1430                         hash_types &=
1431                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1432                 }
1433                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1434                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1435                         hash_types &=
1436                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1437                 }
1438                 if (hash_types) {
1439                         PMD_DRV_LOG(ERR,
1440                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1441                                 vnic->hash_type);
1442                         return -ENOTSUP;
1443                 }
1444         } else {
1445                 rss_conf->rss_hf = 0;
1446         }
1447         return 0;
1448 }
1449
1450 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1451                                struct rte_eth_fc_conf *fc_conf)
1452 {
1453         struct bnxt *bp = dev->data->dev_private;
1454         struct rte_eth_link link_info;
1455         int rc;
1456
1457         rc = is_bnxt_in_error(bp);
1458         if (rc)
1459                 return rc;
1460
1461         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1462         if (rc)
1463                 return rc;
1464
1465         memset(fc_conf, 0, sizeof(*fc_conf));
1466         if (bp->link_info.auto_pause)
1467                 fc_conf->autoneg = 1;
1468         switch (bp->link_info.pause) {
1469         case 0:
1470                 fc_conf->mode = RTE_FC_NONE;
1471                 break;
1472         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1473                 fc_conf->mode = RTE_FC_TX_PAUSE;
1474                 break;
1475         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1476                 fc_conf->mode = RTE_FC_RX_PAUSE;
1477                 break;
1478         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1479                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1480                 fc_conf->mode = RTE_FC_FULL;
1481                 break;
1482         }
1483         return 0;
1484 }
1485
1486 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1487                                struct rte_eth_fc_conf *fc_conf)
1488 {
1489         struct bnxt *bp = dev->data->dev_private;
1490         int rc;
1491
1492         rc = is_bnxt_in_error(bp);
1493         if (rc)
1494                 return rc;
1495
1496         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1497                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1498                 return -ENOTSUP;
1499         }
1500
1501         switch (fc_conf->mode) {
1502         case RTE_FC_NONE:
1503                 bp->link_info.auto_pause = 0;
1504                 bp->link_info.force_pause = 0;
1505                 break;
1506         case RTE_FC_RX_PAUSE:
1507                 if (fc_conf->autoneg) {
1508                         bp->link_info.auto_pause =
1509                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1510                         bp->link_info.force_pause = 0;
1511                 } else {
1512                         bp->link_info.auto_pause = 0;
1513                         bp->link_info.force_pause =
1514                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1515                 }
1516                 break;
1517         case RTE_FC_TX_PAUSE:
1518                 if (fc_conf->autoneg) {
1519                         bp->link_info.auto_pause =
1520                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1521                         bp->link_info.force_pause = 0;
1522                 } else {
1523                         bp->link_info.auto_pause = 0;
1524                         bp->link_info.force_pause =
1525                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1526                 }
1527                 break;
1528         case RTE_FC_FULL:
1529                 if (fc_conf->autoneg) {
1530                         bp->link_info.auto_pause =
1531                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1532                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1533                         bp->link_info.force_pause = 0;
1534                 } else {
1535                         bp->link_info.auto_pause = 0;
1536                         bp->link_info.force_pause =
1537                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1538                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1539                 }
1540                 break;
1541         }
1542         return bnxt_set_hwrm_link_config(bp, true);
1543 }
1544
1545 /* Add UDP tunneling port */
1546 static int
1547 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1548                          struct rte_eth_udp_tunnel *udp_tunnel)
1549 {
1550         struct bnxt *bp = eth_dev->data->dev_private;
1551         uint16_t tunnel_type = 0;
1552         int rc = 0;
1553
1554         rc = is_bnxt_in_error(bp);
1555         if (rc)
1556                 return rc;
1557
1558         switch (udp_tunnel->prot_type) {
1559         case RTE_TUNNEL_TYPE_VXLAN:
1560                 if (bp->vxlan_port_cnt) {
1561                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1562                                 udp_tunnel->udp_port);
1563                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1564                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1565                                 return -ENOSPC;
1566                         }
1567                         bp->vxlan_port_cnt++;
1568                         return 0;
1569                 }
1570                 tunnel_type =
1571                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1572                 bp->vxlan_port_cnt++;
1573                 break;
1574         case RTE_TUNNEL_TYPE_GENEVE:
1575                 if (bp->geneve_port_cnt) {
1576                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1577                                 udp_tunnel->udp_port);
1578                         if (bp->geneve_port != udp_tunnel->udp_port) {
1579                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1580                                 return -ENOSPC;
1581                         }
1582                         bp->geneve_port_cnt++;
1583                         return 0;
1584                 }
1585                 tunnel_type =
1586                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1587                 bp->geneve_port_cnt++;
1588                 break;
1589         default:
1590                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1591                 return -ENOTSUP;
1592         }
1593         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1594                                              tunnel_type);
1595         return rc;
1596 }
1597
1598 static int
1599 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1600                          struct rte_eth_udp_tunnel *udp_tunnel)
1601 {
1602         struct bnxt *bp = eth_dev->data->dev_private;
1603         uint16_t tunnel_type = 0;
1604         uint16_t port = 0;
1605         int rc = 0;
1606
1607         rc = is_bnxt_in_error(bp);
1608         if (rc)
1609                 return rc;
1610
1611         switch (udp_tunnel->prot_type) {
1612         case RTE_TUNNEL_TYPE_VXLAN:
1613                 if (!bp->vxlan_port_cnt) {
1614                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1615                         return -EINVAL;
1616                 }
1617                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1618                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1619                                 udp_tunnel->udp_port, bp->vxlan_port);
1620                         return -EINVAL;
1621                 }
1622                 if (--bp->vxlan_port_cnt)
1623                         return 0;
1624
1625                 tunnel_type =
1626                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1627                 port = bp->vxlan_fw_dst_port_id;
1628                 break;
1629         case RTE_TUNNEL_TYPE_GENEVE:
1630                 if (!bp->geneve_port_cnt) {
1631                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1632                         return -EINVAL;
1633                 }
1634                 if (bp->geneve_port != udp_tunnel->udp_port) {
1635                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1636                                 udp_tunnel->udp_port, bp->geneve_port);
1637                         return -EINVAL;
1638                 }
1639                 if (--bp->geneve_port_cnt)
1640                         return 0;
1641
1642                 tunnel_type =
1643                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1644                 port = bp->geneve_fw_dst_port_id;
1645                 break;
1646         default:
1647                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1648                 return -ENOTSUP;
1649         }
1650
1651         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1652         if (!rc) {
1653                 if (tunnel_type ==
1654                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1655                         bp->vxlan_port = 0;
1656                 if (tunnel_type ==
1657                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1658                         bp->geneve_port = 0;
1659         }
1660         return rc;
1661 }
1662
1663 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1664 {
1665         struct bnxt_filter_info *filter;
1666         struct bnxt_vnic_info *vnic;
1667         int rc = 0;
1668         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1669
1670         /* if VLAN exists && VLAN matches vlan_id
1671          *      remove the MAC+VLAN filter
1672          *      add a new MAC only filter
1673          * else
1674          *      VLAN filter doesn't exist, just skip and continue
1675          */
1676         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1677         filter = STAILQ_FIRST(&vnic->filter);
1678         while (filter) {
1679                 /* Search for this matching MAC+VLAN filter */
1680                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1681                     !memcmp(filter->l2_addr,
1682                             bp->mac_addr,
1683                             RTE_ETHER_ADDR_LEN)) {
1684                         /* Delete the filter */
1685                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1686                         if (rc)
1687                                 return rc;
1688                         STAILQ_REMOVE(&vnic->filter, filter,
1689                                       bnxt_filter_info, next);
1690                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1691
1692                         PMD_DRV_LOG(INFO,
1693                                     "Del Vlan filter for %d\n",
1694                                     vlan_id);
1695                         return rc;
1696                 }
1697                 filter = STAILQ_NEXT(filter, next);
1698         }
1699         return -ENOENT;
1700 }
1701
1702 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1703 {
1704         struct bnxt_filter_info *filter;
1705         struct bnxt_vnic_info *vnic;
1706         int rc = 0;
1707         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1708                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1709         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1710
1711         /* Implementation notes on the use of VNIC in this command:
1712          *
1713          * By default, these filters belong to default vnic for the function.
1714          * Once these filters are set up, only destination VNIC can be modified.
1715          * If the destination VNIC is not specified in this command,
1716          * then the HWRM shall only create an l2 context id.
1717          */
1718
1719         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1720         filter = STAILQ_FIRST(&vnic->filter);
1721         /* Check if the VLAN has already been added */
1722         while (filter) {
1723                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1724                     !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1725                         return -EEXIST;
1726
1727                 filter = STAILQ_NEXT(filter, next);
1728         }
1729
1730         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1731          * command to create MAC+VLAN filter with the right flags, enables set.
1732          */
1733         filter = bnxt_alloc_filter(bp);
1734         if (!filter) {
1735                 PMD_DRV_LOG(ERR,
1736                             "MAC/VLAN filter alloc failed\n");
1737                 return -ENOMEM;
1738         }
1739         /* MAC + VLAN ID filter */
1740         filter->l2_ivlan = vlan_id;
1741         filter->l2_ivlan_mask = 0x0FFF;
1742         filter->enables |= en;
1743         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1744         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1745         if (rc) {
1746                 /* Free the newly allocated filter as we were
1747                  * not able to create the filter in hardware.
1748                  */
1749                 filter->fw_l2_filter_id = UINT64_MAX;
1750                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1751                 return rc;
1752         }
1753
1754         /* Add this new filter to the list */
1755         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1756         PMD_DRV_LOG(INFO,
1757                     "Added Vlan filter for %d\n", vlan_id);
1758         return rc;
1759 }
1760
1761 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1762                 uint16_t vlan_id, int on)
1763 {
1764         struct bnxt *bp = eth_dev->data->dev_private;
1765         int rc;
1766
1767         rc = is_bnxt_in_error(bp);
1768         if (rc)
1769                 return rc;
1770
1771         /* These operations apply to ALL existing MAC/VLAN filters */
1772         if (on)
1773                 return bnxt_add_vlan_filter(bp, vlan_id);
1774         else
1775                 return bnxt_del_vlan_filter(bp, vlan_id);
1776 }
1777
1778 static int
1779 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1780 {
1781         struct bnxt *bp = dev->data->dev_private;
1782         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1783         unsigned int i;
1784         int rc;
1785
1786         rc = is_bnxt_in_error(bp);
1787         if (rc)
1788                 return rc;
1789
1790         if (mask & ETH_VLAN_FILTER_MASK) {
1791                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1792                         /* Remove any VLAN filters programmed */
1793                         for (i = 0; i < 4095; i++)
1794                                 bnxt_del_vlan_filter(bp, i);
1795                 }
1796                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1797                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1798         }
1799
1800         if (mask & ETH_VLAN_STRIP_MASK) {
1801                 /* Enable or disable VLAN stripping */
1802                 for (i = 0; i < bp->nr_vnics; i++) {
1803                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1804                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1805                                 vnic->vlan_strip = true;
1806                         else
1807                                 vnic->vlan_strip = false;
1808                         bnxt_hwrm_vnic_cfg(bp, vnic);
1809                 }
1810                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1811                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1812         }
1813
1814         if (mask & ETH_VLAN_EXTEND_MASK) {
1815                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1816                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1817                 else
1818                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1819         }
1820
1821         return 0;
1822 }
1823
1824 static int
1825 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1826                       uint16_t tpid)
1827 {
1828         struct bnxt *bp = dev->data->dev_private;
1829         int qinq = dev->data->dev_conf.rxmode.offloads &
1830                    DEV_RX_OFFLOAD_VLAN_EXTEND;
1831
1832         if (vlan_type != ETH_VLAN_TYPE_INNER &&
1833             vlan_type != ETH_VLAN_TYPE_OUTER) {
1834                 PMD_DRV_LOG(ERR,
1835                             "Unsupported vlan type.");
1836                 return -EINVAL;
1837         }
1838         if (!qinq) {
1839                 PMD_DRV_LOG(ERR,
1840                             "QinQ not enabled. Needs to be ON as we can "
1841                             "accelerate only outer vlan\n");
1842                 return -EINVAL;
1843         }
1844
1845         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1846                 switch (tpid) {
1847                 case RTE_ETHER_TYPE_QINQ:
1848                         bp->outer_tpid_bd =
1849                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1850                                 break;
1851                 case RTE_ETHER_TYPE_VLAN:
1852                         bp->outer_tpid_bd =
1853                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1854                                 break;
1855                 case 0x9100:
1856                         bp->outer_tpid_bd =
1857                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1858                                 break;
1859                 case 0x9200:
1860                         bp->outer_tpid_bd =
1861                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1862                                 break;
1863                 case 0x9300:
1864                         bp->outer_tpid_bd =
1865                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1866                                 break;
1867                 default:
1868                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1869                         return -EINVAL;
1870                 }
1871                 bp->outer_tpid_bd |= tpid;
1872                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1873         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1874                 PMD_DRV_LOG(ERR,
1875                             "Can accelerate only outer vlan in QinQ\n");
1876                 return -EINVAL;
1877         }
1878
1879         return 0;
1880 }
1881
1882 static int
1883 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1884                              struct rte_ether_addr *addr)
1885 {
1886         struct bnxt *bp = dev->data->dev_private;
1887         /* Default Filter is tied to VNIC 0 */
1888         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1889         struct bnxt_filter_info *filter;
1890         int rc;
1891
1892         rc = is_bnxt_in_error(bp);
1893         if (rc)
1894                 return rc;
1895
1896         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1897                 return -EPERM;
1898
1899         if (rte_is_zero_ether_addr(addr))
1900                 return -EINVAL;
1901
1902         STAILQ_FOREACH(filter, &vnic->filter, next) {
1903                 /* Default Filter is at Index 0 */
1904                 if (filter->mac_index != 0)
1905                         continue;
1906
1907                 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
1908                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1909                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
1910                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1911                 filter->enables |=
1912                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1913                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1914
1915                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1916                 if (rc) {
1917                         memcpy(filter->l2_addr, bp->mac_addr,
1918                                RTE_ETHER_ADDR_LEN);
1919                         return rc;
1920                 }
1921
1922                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1923                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1924                 return 0;
1925         }
1926
1927         return 0;
1928 }
1929
1930 static int
1931 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1932                           struct rte_ether_addr *mc_addr_set,
1933                           uint32_t nb_mc_addr)
1934 {
1935         struct bnxt *bp = eth_dev->data->dev_private;
1936         char *mc_addr_list = (char *)mc_addr_set;
1937         struct bnxt_vnic_info *vnic;
1938         uint32_t off = 0, i = 0;
1939         int rc;
1940
1941         rc = is_bnxt_in_error(bp);
1942         if (rc)
1943                 return rc;
1944
1945         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1946
1947         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1948                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1949                 goto allmulti;
1950         }
1951
1952         /* TODO Check for Duplicate mcast addresses */
1953         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1954         for (i = 0; i < nb_mc_addr; i++) {
1955                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1956                         RTE_ETHER_ADDR_LEN);
1957                 off += RTE_ETHER_ADDR_LEN;
1958         }
1959
1960         vnic->mc_addr_cnt = i;
1961
1962 allmulti:
1963         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1964 }
1965
1966 static int
1967 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1968 {
1969         struct bnxt *bp = dev->data->dev_private;
1970         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1971         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1972         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1973         int ret;
1974
1975         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1976                         fw_major, fw_minor, fw_updt);
1977
1978         ret += 1; /* add the size of '\0' */
1979         if (fw_size < (uint32_t)ret)
1980                 return ret;
1981         else
1982                 return 0;
1983 }
1984
1985 static void
1986 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1987         struct rte_eth_rxq_info *qinfo)
1988 {
1989         struct bnxt_rx_queue *rxq;
1990
1991         rxq = dev->data->rx_queues[queue_id];
1992
1993         qinfo->mp = rxq->mb_pool;
1994         qinfo->scattered_rx = dev->data->scattered_rx;
1995         qinfo->nb_desc = rxq->nb_rx_desc;
1996
1997         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1998         qinfo->conf.rx_drop_en = 0;
1999         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2000 }
2001
2002 static void
2003 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2004         struct rte_eth_txq_info *qinfo)
2005 {
2006         struct bnxt_tx_queue *txq;
2007
2008         txq = dev->data->tx_queues[queue_id];
2009
2010         qinfo->nb_desc = txq->nb_tx_desc;
2011
2012         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2013         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2014         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2015
2016         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2017         qinfo->conf.tx_rs_thresh = 0;
2018         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2019 }
2020
2021 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2022 {
2023         struct bnxt *bp = eth_dev->data->dev_private;
2024         uint32_t new_pkt_size;
2025         uint32_t rc = 0;
2026         uint32_t i;
2027
2028         rc = is_bnxt_in_error(bp);
2029         if (rc)
2030                 return rc;
2031
2032         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2033                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2034
2035 #ifdef RTE_ARCH_X86
2036         /*
2037          * If vector-mode tx/rx is active, disallow any MTU change that would
2038          * require scattered receive support.
2039          */
2040         if (eth_dev->data->dev_started &&
2041             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2042              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2043             (new_pkt_size >
2044              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2045                 PMD_DRV_LOG(ERR,
2046                             "MTU change would require scattered rx support. ");
2047                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2048                 return -EINVAL;
2049         }
2050 #endif
2051
2052         if (new_mtu > RTE_ETHER_MTU) {
2053                 bp->flags |= BNXT_FLAG_JUMBO;
2054                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2055                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2056         } else {
2057                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2058                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2059                 bp->flags &= ~BNXT_FLAG_JUMBO;
2060         }
2061
2062         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2063
2064         for (i = 0; i < bp->nr_vnics; i++) {
2065                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2066                 uint16_t size = 0;
2067
2068                 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN +
2069                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2070                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2071                 if (rc)
2072                         break;
2073
2074                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2075                 size -= RTE_PKTMBUF_HEADROOM;
2076
2077                 if (size < new_mtu) {
2078                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2079                         if (rc)
2080                                 return rc;
2081                 }
2082         }
2083
2084         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2085
2086         return rc;
2087 }
2088
2089 static int
2090 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2091 {
2092         struct bnxt *bp = dev->data->dev_private;
2093         uint16_t vlan = bp->vlan;
2094         int rc;
2095
2096         rc = is_bnxt_in_error(bp);
2097         if (rc)
2098                 return rc;
2099
2100         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2101                 PMD_DRV_LOG(ERR,
2102                         "PVID cannot be modified for this function\n");
2103                 return -ENOTSUP;
2104         }
2105         bp->vlan = on ? pvid : 0;
2106
2107         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2108         if (rc)
2109                 bp->vlan = vlan;
2110         return rc;
2111 }
2112
2113 static int
2114 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2115 {
2116         struct bnxt *bp = dev->data->dev_private;
2117         int rc;
2118
2119         rc = is_bnxt_in_error(bp);
2120         if (rc)
2121                 return rc;
2122
2123         return bnxt_hwrm_port_led_cfg(bp, true);
2124 }
2125
2126 static int
2127 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2128 {
2129         struct bnxt *bp = dev->data->dev_private;
2130         int rc;
2131
2132         rc = is_bnxt_in_error(bp);
2133         if (rc)
2134                 return rc;
2135
2136         return bnxt_hwrm_port_led_cfg(bp, false);
2137 }
2138
2139 static uint32_t
2140 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2141 {
2142         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2143         uint32_t desc = 0, raw_cons = 0, cons;
2144         struct bnxt_cp_ring_info *cpr;
2145         struct bnxt_rx_queue *rxq;
2146         struct rx_pkt_cmpl *rxcmp;
2147         int rc;
2148
2149         rc = is_bnxt_in_error(bp);
2150         if (rc)
2151                 return rc;
2152
2153         rxq = dev->data->rx_queues[rx_queue_id];
2154         cpr = rxq->cp_ring;
2155         raw_cons = cpr->cp_raw_cons;
2156
2157         while (1) {
2158                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2159                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2160                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2161
2162                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2163                         break;
2164                 } else {
2165                         raw_cons++;
2166                         desc++;
2167                 }
2168         }
2169
2170         return desc;
2171 }
2172
2173 static int
2174 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2175 {
2176         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2177         struct bnxt_rx_ring_info *rxr;
2178         struct bnxt_cp_ring_info *cpr;
2179         struct bnxt_sw_rx_bd *rx_buf;
2180         struct rx_pkt_cmpl *rxcmp;
2181         uint32_t cons, cp_cons;
2182         int rc;
2183
2184         if (!rxq)
2185                 return -EINVAL;
2186
2187         rc = is_bnxt_in_error(rxq->bp);
2188         if (rc)
2189                 return rc;
2190
2191         cpr = rxq->cp_ring;
2192         rxr = rxq->rx_ring;
2193
2194         if (offset >= rxq->nb_rx_desc)
2195                 return -EINVAL;
2196
2197         cons = RING_CMP(cpr->cp_ring_struct, offset);
2198         cp_cons = cpr->cp_raw_cons;
2199         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2200
2201         if (cons > cp_cons) {
2202                 if (CMPL_VALID(rxcmp, cpr->valid))
2203                         return RTE_ETH_RX_DESC_DONE;
2204         } else {
2205                 if (CMPL_VALID(rxcmp, !cpr->valid))
2206                         return RTE_ETH_RX_DESC_DONE;
2207         }
2208         rx_buf = &rxr->rx_buf_ring[cons];
2209         if (rx_buf->mbuf == NULL)
2210                 return RTE_ETH_RX_DESC_UNAVAIL;
2211
2212
2213         return RTE_ETH_RX_DESC_AVAIL;
2214 }
2215
2216 static int
2217 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2218 {
2219         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2220         struct bnxt_tx_ring_info *txr;
2221         struct bnxt_cp_ring_info *cpr;
2222         struct bnxt_sw_tx_bd *tx_buf;
2223         struct tx_pkt_cmpl *txcmp;
2224         uint32_t cons, cp_cons;
2225         int rc;
2226
2227         if (!txq)
2228                 return -EINVAL;
2229
2230         rc = is_bnxt_in_error(txq->bp);
2231         if (rc)
2232                 return rc;
2233
2234         cpr = txq->cp_ring;
2235         txr = txq->tx_ring;
2236
2237         if (offset >= txq->nb_tx_desc)
2238                 return -EINVAL;
2239
2240         cons = RING_CMP(cpr->cp_ring_struct, offset);
2241         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2242         cp_cons = cpr->cp_raw_cons;
2243
2244         if (cons > cp_cons) {
2245                 if (CMPL_VALID(txcmp, cpr->valid))
2246                         return RTE_ETH_TX_DESC_UNAVAIL;
2247         } else {
2248                 if (CMPL_VALID(txcmp, !cpr->valid))
2249                         return RTE_ETH_TX_DESC_UNAVAIL;
2250         }
2251         tx_buf = &txr->tx_buf_ring[cons];
2252         if (tx_buf->mbuf == NULL)
2253                 return RTE_ETH_TX_DESC_DONE;
2254
2255         return RTE_ETH_TX_DESC_FULL;
2256 }
2257
2258 static struct bnxt_filter_info *
2259 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2260                                 struct rte_eth_ethertype_filter *efilter,
2261                                 struct bnxt_vnic_info *vnic0,
2262                                 struct bnxt_vnic_info *vnic,
2263                                 int *ret)
2264 {
2265         struct bnxt_filter_info *mfilter = NULL;
2266         int match = 0;
2267         *ret = 0;
2268
2269         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2270                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2271                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2272                         " ethertype filter.", efilter->ether_type);
2273                 *ret = -EINVAL;
2274                 goto exit;
2275         }
2276         if (efilter->queue >= bp->rx_nr_rings) {
2277                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2278                 *ret = -EINVAL;
2279                 goto exit;
2280         }
2281
2282         vnic0 = &bp->vnic_info[0];
2283         vnic = &bp->vnic_info[efilter->queue];
2284         if (vnic == NULL) {
2285                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2286                 *ret = -EINVAL;
2287                 goto exit;
2288         }
2289
2290         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2291                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2292                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2293                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2294                              mfilter->flags ==
2295                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2296                              mfilter->ethertype == efilter->ether_type)) {
2297                                 match = 1;
2298                                 break;
2299                         }
2300                 }
2301         } else {
2302                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2303                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2304                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2305                              mfilter->ethertype == efilter->ether_type &&
2306                              mfilter->flags ==
2307                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2308                                 match = 1;
2309                                 break;
2310                         }
2311         }
2312
2313         if (match)
2314                 *ret = -EEXIST;
2315
2316 exit:
2317         return mfilter;
2318 }
2319
2320 static int
2321 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2322                         enum rte_filter_op filter_op,
2323                         void *arg)
2324 {
2325         struct bnxt *bp = dev->data->dev_private;
2326         struct rte_eth_ethertype_filter *efilter =
2327                         (struct rte_eth_ethertype_filter *)arg;
2328         struct bnxt_filter_info *bfilter, *filter1;
2329         struct bnxt_vnic_info *vnic, *vnic0;
2330         int ret;
2331
2332         if (filter_op == RTE_ETH_FILTER_NOP)
2333                 return 0;
2334
2335         if (arg == NULL) {
2336                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2337                             filter_op);
2338                 return -EINVAL;
2339         }
2340
2341         vnic0 = &bp->vnic_info[0];
2342         vnic = &bp->vnic_info[efilter->queue];
2343
2344         switch (filter_op) {
2345         case RTE_ETH_FILTER_ADD:
2346                 bnxt_match_and_validate_ether_filter(bp, efilter,
2347                                                         vnic0, vnic, &ret);
2348                 if (ret < 0)
2349                         return ret;
2350
2351                 bfilter = bnxt_get_unused_filter(bp);
2352                 if (bfilter == NULL) {
2353                         PMD_DRV_LOG(ERR,
2354                                 "Not enough resources for a new filter.\n");
2355                         return -ENOMEM;
2356                 }
2357                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2358                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2359                        RTE_ETHER_ADDR_LEN);
2360                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2361                        RTE_ETHER_ADDR_LEN);
2362                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2363                 bfilter->ethertype = efilter->ether_type;
2364                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2365
2366                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2367                 if (filter1 == NULL) {
2368                         ret = -EINVAL;
2369                         goto cleanup;
2370                 }
2371                 bfilter->enables |=
2372                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2373                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2374
2375                 bfilter->dst_id = vnic->fw_vnic_id;
2376
2377                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2378                         bfilter->flags =
2379                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2380                 }
2381
2382                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2383                 if (ret)
2384                         goto cleanup;
2385                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2386                 break;
2387         case RTE_ETH_FILTER_DELETE:
2388                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2389                                                         vnic0, vnic, &ret);
2390                 if (ret == -EEXIST) {
2391                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2392
2393                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2394                                       next);
2395                         bnxt_free_filter(bp, filter1);
2396                 } else if (ret == 0) {
2397                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2398                 }
2399                 break;
2400         default:
2401                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2402                 ret = -EINVAL;
2403                 goto error;
2404         }
2405         return ret;
2406 cleanup:
2407         bnxt_free_filter(bp, bfilter);
2408 error:
2409         return ret;
2410 }
2411
2412 static inline int
2413 parse_ntuple_filter(struct bnxt *bp,
2414                     struct rte_eth_ntuple_filter *nfilter,
2415                     struct bnxt_filter_info *bfilter)
2416 {
2417         uint32_t en = 0;
2418
2419         if (nfilter->queue >= bp->rx_nr_rings) {
2420                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2421                 return -EINVAL;
2422         }
2423
2424         switch (nfilter->dst_port_mask) {
2425         case UINT16_MAX:
2426                 bfilter->dst_port_mask = -1;
2427                 bfilter->dst_port = nfilter->dst_port;
2428                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2429                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2430                 break;
2431         default:
2432                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2433                 return -EINVAL;
2434         }
2435
2436         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2437         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2438
2439         switch (nfilter->proto_mask) {
2440         case UINT8_MAX:
2441                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2442                         bfilter->ip_protocol = 17;
2443                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2444                         bfilter->ip_protocol = 6;
2445                 else
2446                         return -EINVAL;
2447                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2448                 break;
2449         default:
2450                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2451                 return -EINVAL;
2452         }
2453
2454         switch (nfilter->dst_ip_mask) {
2455         case UINT32_MAX:
2456                 bfilter->dst_ipaddr_mask[0] = -1;
2457                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2458                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2459                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2460                 break;
2461         default:
2462                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2463                 return -EINVAL;
2464         }
2465
2466         switch (nfilter->src_ip_mask) {
2467         case UINT32_MAX:
2468                 bfilter->src_ipaddr_mask[0] = -1;
2469                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2470                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2471                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2472                 break;
2473         default:
2474                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2475                 return -EINVAL;
2476         }
2477
2478         switch (nfilter->src_port_mask) {
2479         case UINT16_MAX:
2480                 bfilter->src_port_mask = -1;
2481                 bfilter->src_port = nfilter->src_port;
2482                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2483                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2484                 break;
2485         default:
2486                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2487                 return -EINVAL;
2488         }
2489
2490         //TODO Priority
2491         //nfilter->priority = (uint8_t)filter->priority;
2492
2493         bfilter->enables = en;
2494         return 0;
2495 }
2496
2497 static struct bnxt_filter_info*
2498 bnxt_match_ntuple_filter(struct bnxt *bp,
2499                          struct bnxt_filter_info *bfilter,
2500                          struct bnxt_vnic_info **mvnic)
2501 {
2502         struct bnxt_filter_info *mfilter = NULL;
2503         int i;
2504
2505         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2506                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2507                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2508                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2509                             bfilter->src_ipaddr_mask[0] ==
2510                             mfilter->src_ipaddr_mask[0] &&
2511                             bfilter->src_port == mfilter->src_port &&
2512                             bfilter->src_port_mask == mfilter->src_port_mask &&
2513                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2514                             bfilter->dst_ipaddr_mask[0] ==
2515                             mfilter->dst_ipaddr_mask[0] &&
2516                             bfilter->dst_port == mfilter->dst_port &&
2517                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2518                             bfilter->flags == mfilter->flags &&
2519                             bfilter->enables == mfilter->enables) {
2520                                 if (mvnic)
2521                                         *mvnic = vnic;
2522                                 return mfilter;
2523                         }
2524                 }
2525         }
2526         return NULL;
2527 }
2528
2529 static int
2530 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2531                        struct rte_eth_ntuple_filter *nfilter,
2532                        enum rte_filter_op filter_op)
2533 {
2534         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2535         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2536         int ret;
2537
2538         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2539                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2540                 return -EINVAL;
2541         }
2542
2543         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2544                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2545                 return -EINVAL;
2546         }
2547
2548         bfilter = bnxt_get_unused_filter(bp);
2549         if (bfilter == NULL) {
2550                 PMD_DRV_LOG(ERR,
2551                         "Not enough resources for a new filter.\n");
2552                 return -ENOMEM;
2553         }
2554         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2555         if (ret < 0)
2556                 goto free_filter;
2557
2558         vnic = &bp->vnic_info[nfilter->queue];
2559         vnic0 = &bp->vnic_info[0];
2560         filter1 = STAILQ_FIRST(&vnic0->filter);
2561         if (filter1 == NULL) {
2562                 ret = -EINVAL;
2563                 goto free_filter;
2564         }
2565
2566         bfilter->dst_id = vnic->fw_vnic_id;
2567         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2568         bfilter->enables |=
2569                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2570         bfilter->ethertype = 0x800;
2571         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2572
2573         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2574
2575         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2576             bfilter->dst_id == mfilter->dst_id) {
2577                 PMD_DRV_LOG(ERR, "filter exists.\n");
2578                 ret = -EEXIST;
2579                 goto free_filter;
2580         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2581                    bfilter->dst_id != mfilter->dst_id) {
2582                 mfilter->dst_id = vnic->fw_vnic_id;
2583                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2584                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2585                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2586                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2587                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2588                 goto free_filter;
2589         }
2590         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2591                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2592                 ret = -ENOENT;
2593                 goto free_filter;
2594         }
2595
2596         if (filter_op == RTE_ETH_FILTER_ADD) {
2597                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2598                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2599                 if (ret)
2600                         goto free_filter;
2601                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2602         } else {
2603                 if (mfilter == NULL) {
2604                         /* This should not happen. But for Coverity! */
2605                         ret = -ENOENT;
2606                         goto free_filter;
2607                 }
2608                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2609
2610                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2611                 bnxt_free_filter(bp, mfilter);
2612                 mfilter->fw_l2_filter_id = -1;
2613                 bnxt_free_filter(bp, bfilter);
2614                 bfilter->fw_l2_filter_id = -1;
2615         }
2616
2617         return 0;
2618 free_filter:
2619         bfilter->fw_l2_filter_id = -1;
2620         bnxt_free_filter(bp, bfilter);
2621         return ret;
2622 }
2623
2624 static int
2625 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2626                         enum rte_filter_op filter_op,
2627                         void *arg)
2628 {
2629         struct bnxt *bp = dev->data->dev_private;
2630         int ret;
2631
2632         if (filter_op == RTE_ETH_FILTER_NOP)
2633                 return 0;
2634
2635         if (arg == NULL) {
2636                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2637                             filter_op);
2638                 return -EINVAL;
2639         }
2640
2641         switch (filter_op) {
2642         case RTE_ETH_FILTER_ADD:
2643                 ret = bnxt_cfg_ntuple_filter(bp,
2644                         (struct rte_eth_ntuple_filter *)arg,
2645                         filter_op);
2646                 break;
2647         case RTE_ETH_FILTER_DELETE:
2648                 ret = bnxt_cfg_ntuple_filter(bp,
2649                         (struct rte_eth_ntuple_filter *)arg,
2650                         filter_op);
2651                 break;
2652         default:
2653                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2654                 ret = -EINVAL;
2655                 break;
2656         }
2657         return ret;
2658 }
2659
2660 static int
2661 bnxt_parse_fdir_filter(struct bnxt *bp,
2662                        struct rte_eth_fdir_filter *fdir,
2663                        struct bnxt_filter_info *filter)
2664 {
2665         enum rte_fdir_mode fdir_mode =
2666                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2667         struct bnxt_vnic_info *vnic0, *vnic;
2668         struct bnxt_filter_info *filter1;
2669         uint32_t en = 0;
2670         int i;
2671
2672         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2673                 return -EINVAL;
2674
2675         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2676         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2677
2678         switch (fdir->input.flow_type) {
2679         case RTE_ETH_FLOW_IPV4:
2680         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2681                 /* FALLTHROUGH */
2682                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2683                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2684                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2685                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2686                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2687                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2688                 filter->ip_addr_type =
2689                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2690                 filter->src_ipaddr_mask[0] = 0xffffffff;
2691                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2692                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2693                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2694                 filter->ethertype = 0x800;
2695                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2696                 break;
2697         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2698                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2699                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2700                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2701                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2702                 filter->dst_port_mask = 0xffff;
2703                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2704                 filter->src_port_mask = 0xffff;
2705                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2706                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2707                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2708                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2709                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2710                 filter->ip_protocol = 6;
2711                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2712                 filter->ip_addr_type =
2713                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2714                 filter->src_ipaddr_mask[0] = 0xffffffff;
2715                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2716                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2717                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2718                 filter->ethertype = 0x800;
2719                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2720                 break;
2721         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2722                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2723                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2724                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2725                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2726                 filter->dst_port_mask = 0xffff;
2727                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2728                 filter->src_port_mask = 0xffff;
2729                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2730                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2731                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2732                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2733                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2734                 filter->ip_protocol = 17;
2735                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2736                 filter->ip_addr_type =
2737                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2738                 filter->src_ipaddr_mask[0] = 0xffffffff;
2739                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2740                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2741                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2742                 filter->ethertype = 0x800;
2743                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2744                 break;
2745         case RTE_ETH_FLOW_IPV6:
2746         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2747                 /* FALLTHROUGH */
2748                 filter->ip_addr_type =
2749                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2750                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2751                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2752                 rte_memcpy(filter->src_ipaddr,
2753                            fdir->input.flow.ipv6_flow.src_ip, 16);
2754                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2755                 rte_memcpy(filter->dst_ipaddr,
2756                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2757                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2758                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2759                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2760                 memset(filter->src_ipaddr_mask, 0xff, 16);
2761                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2762                 filter->ethertype = 0x86dd;
2763                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2764                 break;
2765         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2766                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2767                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2768                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2769                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2770                 filter->dst_port_mask = 0xffff;
2771                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2772                 filter->src_port_mask = 0xffff;
2773                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2774                 filter->ip_addr_type =
2775                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2776                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2777                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2778                 rte_memcpy(filter->src_ipaddr,
2779                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2780                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2781                 rte_memcpy(filter->dst_ipaddr,
2782                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2783                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2784                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2785                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2786                 memset(filter->src_ipaddr_mask, 0xff, 16);
2787                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2788                 filter->ethertype = 0x86dd;
2789                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2790                 break;
2791         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2792                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2793                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2794                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2795                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2796                 filter->dst_port_mask = 0xffff;
2797                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2798                 filter->src_port_mask = 0xffff;
2799                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2800                 filter->ip_addr_type =
2801                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2802                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2803                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2804                 rte_memcpy(filter->src_ipaddr,
2805                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2806                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2807                 rte_memcpy(filter->dst_ipaddr,
2808                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2809                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2810                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2811                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2812                 memset(filter->src_ipaddr_mask, 0xff, 16);
2813                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2814                 filter->ethertype = 0x86dd;
2815                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2816                 break;
2817         case RTE_ETH_FLOW_L2_PAYLOAD:
2818                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2819                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2820                 break;
2821         case RTE_ETH_FLOW_VXLAN:
2822                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2823                         return -EINVAL;
2824                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2825                 filter->tunnel_type =
2826                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2827                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2828                 break;
2829         case RTE_ETH_FLOW_NVGRE:
2830                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2831                         return -EINVAL;
2832                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2833                 filter->tunnel_type =
2834                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2835                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2836                 break;
2837         case RTE_ETH_FLOW_UNKNOWN:
2838         case RTE_ETH_FLOW_RAW:
2839         case RTE_ETH_FLOW_FRAG_IPV4:
2840         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2841         case RTE_ETH_FLOW_FRAG_IPV6:
2842         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2843         case RTE_ETH_FLOW_IPV6_EX:
2844         case RTE_ETH_FLOW_IPV6_TCP_EX:
2845         case RTE_ETH_FLOW_IPV6_UDP_EX:
2846         case RTE_ETH_FLOW_GENEVE:
2847                 /* FALLTHROUGH */
2848         default:
2849                 return -EINVAL;
2850         }
2851
2852         vnic0 = &bp->vnic_info[0];
2853         vnic = &bp->vnic_info[fdir->action.rx_queue];
2854         if (vnic == NULL) {
2855                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2856                 return -EINVAL;
2857         }
2858
2859
2860         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2861                 rte_memcpy(filter->dst_macaddr,
2862                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2863                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2864         }
2865
2866         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2867                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2868                 filter1 = STAILQ_FIRST(&vnic0->filter);
2869                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2870         } else {
2871                 filter->dst_id = vnic->fw_vnic_id;
2872                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2873                         if (filter->dst_macaddr[i] == 0x00)
2874                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2875                         else
2876                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2877         }
2878
2879         if (filter1 == NULL)
2880                 return -EINVAL;
2881
2882         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2883         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2884
2885         filter->enables = en;
2886
2887         return 0;
2888 }
2889
2890 static struct bnxt_filter_info *
2891 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2892                 struct bnxt_vnic_info **mvnic)
2893 {
2894         struct bnxt_filter_info *mf = NULL;
2895         int i;
2896
2897         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2898                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2899
2900                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2901                         if (mf->filter_type == nf->filter_type &&
2902                             mf->flags == nf->flags &&
2903                             mf->src_port == nf->src_port &&
2904                             mf->src_port_mask == nf->src_port_mask &&
2905                             mf->dst_port == nf->dst_port &&
2906                             mf->dst_port_mask == nf->dst_port_mask &&
2907                             mf->ip_protocol == nf->ip_protocol &&
2908                             mf->ip_addr_type == nf->ip_addr_type &&
2909                             mf->ethertype == nf->ethertype &&
2910                             mf->vni == nf->vni &&
2911                             mf->tunnel_type == nf->tunnel_type &&
2912                             mf->l2_ovlan == nf->l2_ovlan &&
2913                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2914                             mf->l2_ivlan == nf->l2_ivlan &&
2915                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2916                             !memcmp(mf->l2_addr, nf->l2_addr,
2917                                     RTE_ETHER_ADDR_LEN) &&
2918                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2919                                     RTE_ETHER_ADDR_LEN) &&
2920                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2921                                     RTE_ETHER_ADDR_LEN) &&
2922                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2923                                     RTE_ETHER_ADDR_LEN) &&
2924                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2925                                     sizeof(nf->src_ipaddr)) &&
2926                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2927                                     sizeof(nf->src_ipaddr_mask)) &&
2928                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2929                                     sizeof(nf->dst_ipaddr)) &&
2930                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2931                                     sizeof(nf->dst_ipaddr_mask))) {
2932                                 if (mvnic)
2933                                         *mvnic = vnic;
2934                                 return mf;
2935                         }
2936                 }
2937         }
2938         return NULL;
2939 }
2940
2941 static int
2942 bnxt_fdir_filter(struct rte_eth_dev *dev,
2943                  enum rte_filter_op filter_op,
2944                  void *arg)
2945 {
2946         struct bnxt *bp = dev->data->dev_private;
2947         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2948         struct bnxt_filter_info *filter, *match;
2949         struct bnxt_vnic_info *vnic, *mvnic;
2950         int ret = 0, i;
2951
2952         if (filter_op == RTE_ETH_FILTER_NOP)
2953                 return 0;
2954
2955         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2956                 return -EINVAL;
2957
2958         switch (filter_op) {
2959         case RTE_ETH_FILTER_ADD:
2960         case RTE_ETH_FILTER_DELETE:
2961                 /* FALLTHROUGH */
2962                 filter = bnxt_get_unused_filter(bp);
2963                 if (filter == NULL) {
2964                         PMD_DRV_LOG(ERR,
2965                                 "Not enough resources for a new flow.\n");
2966                         return -ENOMEM;
2967                 }
2968
2969                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2970                 if (ret != 0)
2971                         goto free_filter;
2972                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2973
2974                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2975                         vnic = &bp->vnic_info[0];
2976                 else
2977                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2978
2979                 match = bnxt_match_fdir(bp, filter, &mvnic);
2980                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2981                         if (match->dst_id == vnic->fw_vnic_id) {
2982                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2983                                 ret = -EEXIST;
2984                                 goto free_filter;
2985                         } else {
2986                                 match->dst_id = vnic->fw_vnic_id;
2987                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2988                                                                   match->dst_id,
2989                                                                   match);
2990                                 STAILQ_REMOVE(&mvnic->filter, match,
2991                                               bnxt_filter_info, next);
2992                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2993                                 PMD_DRV_LOG(ERR,
2994                                         "Filter with matching pattern exist\n");
2995                                 PMD_DRV_LOG(ERR,
2996                                         "Updated it to new destination q\n");
2997                                 goto free_filter;
2998                         }
2999                 }
3000                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3001                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3002                         ret = -ENOENT;
3003                         goto free_filter;
3004                 }
3005
3006                 if (filter_op == RTE_ETH_FILTER_ADD) {
3007                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3008                                                           filter->dst_id,
3009                                                           filter);
3010                         if (ret)
3011                                 goto free_filter;
3012                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3013                 } else {
3014                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3015                         STAILQ_REMOVE(&vnic->filter, match,
3016                                       bnxt_filter_info, next);
3017                         bnxt_free_filter(bp, match);
3018                         filter->fw_l2_filter_id = -1;
3019                         bnxt_free_filter(bp, filter);
3020                 }
3021                 break;
3022         case RTE_ETH_FILTER_FLUSH:
3023                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3024                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3025
3026                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3027                                 if (filter->filter_type ==
3028                                     HWRM_CFA_NTUPLE_FILTER) {
3029                                         ret =
3030                                         bnxt_hwrm_clear_ntuple_filter(bp,
3031                                                                       filter);
3032                                         STAILQ_REMOVE(&vnic->filter, filter,
3033                                                       bnxt_filter_info, next);
3034                                 }
3035                         }
3036                 }
3037                 return ret;
3038         case RTE_ETH_FILTER_UPDATE:
3039         case RTE_ETH_FILTER_STATS:
3040         case RTE_ETH_FILTER_INFO:
3041                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3042                 break;
3043         default:
3044                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3045                 ret = -EINVAL;
3046                 break;
3047         }
3048         return ret;
3049
3050 free_filter:
3051         filter->fw_l2_filter_id = -1;
3052         bnxt_free_filter(bp, filter);
3053         return ret;
3054 }
3055
3056 static int
3057 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3058                     enum rte_filter_type filter_type,
3059                     enum rte_filter_op filter_op, void *arg)
3060 {
3061         int ret = 0;
3062
3063         ret = is_bnxt_in_error(dev->data->dev_private);
3064         if (ret)
3065                 return ret;
3066
3067         switch (filter_type) {
3068         case RTE_ETH_FILTER_TUNNEL:
3069                 PMD_DRV_LOG(ERR,
3070                         "filter type: %d: To be implemented\n", filter_type);
3071                 break;
3072         case RTE_ETH_FILTER_FDIR:
3073                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3074                 break;
3075         case RTE_ETH_FILTER_NTUPLE:
3076                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3077                 break;
3078         case RTE_ETH_FILTER_ETHERTYPE:
3079                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3080                 break;
3081         case RTE_ETH_FILTER_GENERIC:
3082                 if (filter_op != RTE_ETH_FILTER_GET)
3083                         return -EINVAL;
3084                 *(const void **)arg = &bnxt_flow_ops;
3085                 break;
3086         default:
3087                 PMD_DRV_LOG(ERR,
3088                         "Filter type (%d) not supported", filter_type);
3089                 ret = -EINVAL;
3090                 break;
3091         }
3092         return ret;
3093 }
3094
3095 static const uint32_t *
3096 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3097 {
3098         static const uint32_t ptypes[] = {
3099                 RTE_PTYPE_L2_ETHER_VLAN,
3100                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3101                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3102                 RTE_PTYPE_L4_ICMP,
3103                 RTE_PTYPE_L4_TCP,
3104                 RTE_PTYPE_L4_UDP,
3105                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3106                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3107                 RTE_PTYPE_INNER_L4_ICMP,
3108                 RTE_PTYPE_INNER_L4_TCP,
3109                 RTE_PTYPE_INNER_L4_UDP,
3110                 RTE_PTYPE_UNKNOWN
3111         };
3112
3113         if (!dev->rx_pkt_burst)
3114                 return NULL;
3115
3116         return ptypes;
3117 }
3118
3119 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3120                          int reg_win)
3121 {
3122         uint32_t reg_base = *reg_arr & 0xfffff000;
3123         uint32_t win_off;
3124         int i;
3125
3126         for (i = 0; i < count; i++) {
3127                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3128                         return -ERANGE;
3129         }
3130         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3131         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3132         return 0;
3133 }
3134
3135 static int bnxt_map_ptp_regs(struct bnxt *bp)
3136 {
3137         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3138         uint32_t *reg_arr;
3139         int rc, i;
3140
3141         reg_arr = ptp->rx_regs;
3142         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3143         if (rc)
3144                 return rc;
3145
3146         reg_arr = ptp->tx_regs;
3147         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3148         if (rc)
3149                 return rc;
3150
3151         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3152                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3153
3154         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3155                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3156
3157         return 0;
3158 }
3159
3160 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3161 {
3162         rte_write32(0, (uint8_t *)bp->bar0 +
3163                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3164         rte_write32(0, (uint8_t *)bp->bar0 +
3165                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3166 }
3167
3168 static uint64_t bnxt_cc_read(struct bnxt *bp)
3169 {
3170         uint64_t ns;
3171
3172         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3173                               BNXT_GRCPF_REG_SYNC_TIME));
3174         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3175                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3176         return ns;
3177 }
3178
3179 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3180 {
3181         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3182         uint32_t fifo;
3183
3184         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3185                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3186         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3187                 return -EAGAIN;
3188
3189         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3190                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3191         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3192                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3193         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3194                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3195
3196         return 0;
3197 }
3198
3199 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3200 {
3201         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3202         struct bnxt_pf_info *pf = &bp->pf;
3203         uint16_t port_id;
3204         uint32_t fifo;
3205
3206         if (!ptp)
3207                 return -ENODEV;
3208
3209         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3210                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3211         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3212                 return -EAGAIN;
3213
3214         port_id = pf->port_id;
3215         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3216                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3217
3218         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3219                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3220         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3221 /*              bnxt_clr_rx_ts(bp);       TBD  */
3222                 return -EBUSY;
3223         }
3224
3225         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3226                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3227         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3228                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3229
3230         return 0;
3231 }
3232
3233 static int
3234 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3235 {
3236         uint64_t ns;
3237         struct bnxt *bp = dev->data->dev_private;
3238         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3239
3240         if (!ptp)
3241                 return 0;
3242
3243         ns = rte_timespec_to_ns(ts);
3244         /* Set the timecounters to a new value. */
3245         ptp->tc.nsec = ns;
3246
3247         return 0;
3248 }
3249
3250 static int
3251 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3252 {
3253         struct bnxt *bp = dev->data->dev_private;
3254         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3255         uint64_t ns, systime_cycles = 0;
3256         int rc = 0;
3257
3258         if (!ptp)
3259                 return 0;
3260
3261         if (BNXT_CHIP_THOR(bp))
3262                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3263                                              &systime_cycles);
3264         else
3265                 systime_cycles = bnxt_cc_read(bp);
3266
3267         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3268         *ts = rte_ns_to_timespec(ns);
3269
3270         return rc;
3271 }
3272 static int
3273 bnxt_timesync_enable(struct rte_eth_dev *dev)
3274 {
3275         struct bnxt *bp = dev->data->dev_private;
3276         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3277         uint32_t shift = 0;
3278         int rc;
3279
3280         if (!ptp)
3281                 return 0;
3282
3283         ptp->rx_filter = 1;
3284         ptp->tx_tstamp_en = 1;
3285         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3286
3287         rc = bnxt_hwrm_ptp_cfg(bp);
3288         if (rc)
3289                 return rc;
3290
3291         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3292         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3293         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3294
3295         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3296         ptp->tc.cc_shift = shift;
3297         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3298
3299         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3300         ptp->rx_tstamp_tc.cc_shift = shift;
3301         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3302
3303         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3304         ptp->tx_tstamp_tc.cc_shift = shift;
3305         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3306
3307         if (!BNXT_CHIP_THOR(bp))
3308                 bnxt_map_ptp_regs(bp);
3309
3310         return 0;
3311 }
3312
3313 static int
3314 bnxt_timesync_disable(struct rte_eth_dev *dev)
3315 {
3316         struct bnxt *bp = dev->data->dev_private;
3317         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3318
3319         if (!ptp)
3320                 return 0;
3321
3322         ptp->rx_filter = 0;
3323         ptp->tx_tstamp_en = 0;
3324         ptp->rxctl = 0;
3325
3326         bnxt_hwrm_ptp_cfg(bp);
3327
3328         if (!BNXT_CHIP_THOR(bp))
3329                 bnxt_unmap_ptp_regs(bp);
3330
3331         return 0;
3332 }
3333
3334 static int
3335 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3336                                  struct timespec *timestamp,
3337                                  uint32_t flags __rte_unused)
3338 {
3339         struct bnxt *bp = dev->data->dev_private;
3340         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3341         uint64_t rx_tstamp_cycles = 0;
3342         uint64_t ns;
3343
3344         if (!ptp)
3345                 return 0;
3346
3347         if (BNXT_CHIP_THOR(bp))
3348                 rx_tstamp_cycles = ptp->rx_timestamp;
3349         else
3350                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3351
3352         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3353         *timestamp = rte_ns_to_timespec(ns);
3354         return  0;
3355 }
3356
3357 static int
3358 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3359                                  struct timespec *timestamp)
3360 {
3361         struct bnxt *bp = dev->data->dev_private;
3362         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3363         uint64_t tx_tstamp_cycles = 0;
3364         uint64_t ns;
3365         int rc = 0;
3366
3367         if (!ptp)
3368                 return 0;
3369
3370         if (BNXT_CHIP_THOR(bp))
3371                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3372                                              &tx_tstamp_cycles);
3373         else
3374                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3375
3376         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3377         *timestamp = rte_ns_to_timespec(ns);
3378
3379         return rc;
3380 }
3381
3382 static int
3383 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3384 {
3385         struct bnxt *bp = dev->data->dev_private;
3386         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3387
3388         if (!ptp)
3389                 return 0;
3390
3391         ptp->tc.nsec += delta;
3392
3393         return 0;
3394 }
3395
3396 static int
3397 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3398 {
3399         struct bnxt *bp = dev->data->dev_private;
3400         int rc;
3401         uint32_t dir_entries;
3402         uint32_t entry_length;
3403
3404         rc = is_bnxt_in_error(bp);
3405         if (rc)
3406                 return rc;
3407
3408         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3409                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3410                 bp->pdev->addr.devid, bp->pdev->addr.function);
3411
3412         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3413         if (rc != 0)
3414                 return rc;
3415
3416         return dir_entries * entry_length;
3417 }
3418
3419 static int
3420 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3421                 struct rte_dev_eeprom_info *in_eeprom)
3422 {
3423         struct bnxt *bp = dev->data->dev_private;
3424         uint32_t index;
3425         uint32_t offset;
3426         int rc;
3427
3428         rc = is_bnxt_in_error(bp);
3429         if (rc)
3430                 return rc;
3431
3432         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3433                 "len = %d\n", bp->pdev->addr.domain,
3434                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3435                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3436
3437         if (in_eeprom->offset == 0) /* special offset value to get directory */
3438                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3439                                                 in_eeprom->data);
3440
3441         index = in_eeprom->offset >> 24;
3442         offset = in_eeprom->offset & 0xffffff;
3443
3444         if (index != 0)
3445                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3446                                            in_eeprom->length, in_eeprom->data);
3447
3448         return 0;
3449 }
3450
3451 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3452 {
3453         switch (dir_type) {
3454         case BNX_DIR_TYPE_CHIMP_PATCH:
3455         case BNX_DIR_TYPE_BOOTCODE:
3456         case BNX_DIR_TYPE_BOOTCODE_2:
3457         case BNX_DIR_TYPE_APE_FW:
3458         case BNX_DIR_TYPE_APE_PATCH:
3459         case BNX_DIR_TYPE_KONG_FW:
3460         case BNX_DIR_TYPE_KONG_PATCH:
3461         case BNX_DIR_TYPE_BONO_FW:
3462         case BNX_DIR_TYPE_BONO_PATCH:
3463                 /* FALLTHROUGH */
3464                 return true;
3465         }
3466
3467         return false;
3468 }
3469
3470 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3471 {
3472         switch (dir_type) {
3473         case BNX_DIR_TYPE_AVS:
3474         case BNX_DIR_TYPE_EXP_ROM_MBA:
3475         case BNX_DIR_TYPE_PCIE:
3476         case BNX_DIR_TYPE_TSCF_UCODE:
3477         case BNX_DIR_TYPE_EXT_PHY:
3478         case BNX_DIR_TYPE_CCM:
3479         case BNX_DIR_TYPE_ISCSI_BOOT:
3480         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3481         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3482                 /* FALLTHROUGH */
3483                 return true;
3484         }
3485
3486         return false;
3487 }
3488
3489 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3490 {
3491         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3492                 bnxt_dir_type_is_other_exec_format(dir_type);
3493 }
3494
3495 static int
3496 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3497                 struct rte_dev_eeprom_info *in_eeprom)
3498 {
3499         struct bnxt *bp = dev->data->dev_private;
3500         uint8_t index, dir_op;
3501         uint16_t type, ext, ordinal, attr;
3502         int rc;
3503
3504         rc = is_bnxt_in_error(bp);
3505         if (rc)
3506                 return rc;
3507
3508         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3509                 "len = %d\n", bp->pdev->addr.domain,
3510                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3511                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3512
3513         if (!BNXT_PF(bp)) {
3514                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3515                 return -EINVAL;
3516         }
3517
3518         type = in_eeprom->magic >> 16;
3519
3520         if (type == 0xffff) { /* special value for directory operations */
3521                 index = in_eeprom->magic & 0xff;
3522                 dir_op = in_eeprom->magic >> 8;
3523                 if (index == 0)
3524                         return -EINVAL;
3525                 switch (dir_op) {
3526                 case 0x0e: /* erase */
3527                         if (in_eeprom->offset != ~in_eeprom->magic)
3528                                 return -EINVAL;
3529                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3530                 default:
3531                         return -EINVAL;
3532                 }
3533         }
3534
3535         /* Create or re-write an NVM item: */
3536         if (bnxt_dir_type_is_executable(type) == true)
3537                 return -EOPNOTSUPP;
3538         ext = in_eeprom->magic & 0xffff;
3539         ordinal = in_eeprom->offset >> 16;
3540         attr = in_eeprom->offset & 0xffff;
3541
3542         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3543                                      in_eeprom->data, in_eeprom->length);
3544 }
3545
3546 /*
3547  * Initialization
3548  */
3549
3550 static const struct eth_dev_ops bnxt_dev_ops = {
3551         .dev_infos_get = bnxt_dev_info_get_op,
3552         .dev_close = bnxt_dev_close_op,
3553         .dev_configure = bnxt_dev_configure_op,
3554         .dev_start = bnxt_dev_start_op,
3555         .dev_stop = bnxt_dev_stop_op,
3556         .dev_set_link_up = bnxt_dev_set_link_up_op,
3557         .dev_set_link_down = bnxt_dev_set_link_down_op,
3558         .stats_get = bnxt_stats_get_op,
3559         .stats_reset = bnxt_stats_reset_op,
3560         .rx_queue_setup = bnxt_rx_queue_setup_op,
3561         .rx_queue_release = bnxt_rx_queue_release_op,
3562         .tx_queue_setup = bnxt_tx_queue_setup_op,
3563         .tx_queue_release = bnxt_tx_queue_release_op,
3564         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3565         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3566         .reta_update = bnxt_reta_update_op,
3567         .reta_query = bnxt_reta_query_op,
3568         .rss_hash_update = bnxt_rss_hash_update_op,
3569         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3570         .link_update = bnxt_link_update_op,
3571         .promiscuous_enable = bnxt_promiscuous_enable_op,
3572         .promiscuous_disable = bnxt_promiscuous_disable_op,
3573         .allmulticast_enable = bnxt_allmulticast_enable_op,
3574         .allmulticast_disable = bnxt_allmulticast_disable_op,
3575         .mac_addr_add = bnxt_mac_addr_add_op,
3576         .mac_addr_remove = bnxt_mac_addr_remove_op,
3577         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3578         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3579         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3580         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3581         .vlan_filter_set = bnxt_vlan_filter_set_op,
3582         .vlan_offload_set = bnxt_vlan_offload_set_op,
3583         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3584         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3585         .mtu_set = bnxt_mtu_set_op,
3586         .mac_addr_set = bnxt_set_default_mac_addr_op,
3587         .xstats_get = bnxt_dev_xstats_get_op,
3588         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3589         .xstats_reset = bnxt_dev_xstats_reset_op,
3590         .fw_version_get = bnxt_fw_version_get,
3591         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3592         .rxq_info_get = bnxt_rxq_info_get_op,
3593         .txq_info_get = bnxt_txq_info_get_op,
3594         .dev_led_on = bnxt_dev_led_on_op,
3595         .dev_led_off = bnxt_dev_led_off_op,
3596         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3597         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3598         .rx_queue_count = bnxt_rx_queue_count_op,
3599         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3600         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3601         .rx_queue_start = bnxt_rx_queue_start,
3602         .rx_queue_stop = bnxt_rx_queue_stop,
3603         .tx_queue_start = bnxt_tx_queue_start,
3604         .tx_queue_stop = bnxt_tx_queue_stop,
3605         .filter_ctrl = bnxt_filter_ctrl_op,
3606         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3607         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3608         .get_eeprom           = bnxt_get_eeprom_op,
3609         .set_eeprom           = bnxt_set_eeprom_op,
3610         .timesync_enable      = bnxt_timesync_enable,
3611         .timesync_disable     = bnxt_timesync_disable,
3612         .timesync_read_time   = bnxt_timesync_read_time,
3613         .timesync_write_time   = bnxt_timesync_write_time,
3614         .timesync_adjust_time = bnxt_timesync_adjust_time,
3615         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3616         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3617 };
3618
3619 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3620 {
3621         uint32_t offset;
3622
3623         /* Only pre-map the reset GRC registers using window 3 */
3624         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3625                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3626
3627         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3628
3629         return offset;
3630 }
3631
3632 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3633 {
3634         struct bnxt_error_recovery_info *info = bp->recovery_info;
3635         uint32_t reg_base = 0xffffffff;
3636         int i;
3637
3638         /* Only pre-map the monitoring GRC registers using window 2 */
3639         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3640                 uint32_t reg = info->status_regs[i];
3641
3642                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3643                         continue;
3644
3645                 if (reg_base == 0xffffffff)
3646                         reg_base = reg & 0xfffff000;
3647                 if ((reg & 0xfffff000) != reg_base)
3648                         return -ERANGE;
3649
3650                 /* Use mask 0xffc as the Lower 2 bits indicates
3651                  * address space location
3652                  */
3653                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3654                                                 (reg & 0xffc);
3655         }
3656
3657         if (reg_base == 0xffffffff)
3658                 return 0;
3659
3660         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3661                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3662
3663         return 0;
3664 }
3665
3666 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3667 {
3668         struct bnxt_error_recovery_info *info = bp->recovery_info;
3669         uint32_t delay = info->delay_after_reset[index];
3670         uint32_t val = info->reset_reg_val[index];
3671         uint32_t reg = info->reset_reg[index];
3672         uint32_t type, offset;
3673
3674         type = BNXT_FW_STATUS_REG_TYPE(reg);
3675         offset = BNXT_FW_STATUS_REG_OFF(reg);
3676
3677         switch (type) {
3678         case BNXT_FW_STATUS_REG_TYPE_CFG:
3679                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3680                 break;
3681         case BNXT_FW_STATUS_REG_TYPE_GRC:
3682                 offset = bnxt_map_reset_regs(bp, offset);
3683                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3684                 break;
3685         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3686                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3687                 break;
3688         }
3689         /* wait on a specific interval of time until core reset is complete */
3690         if (delay)
3691                 rte_delay_ms(delay);
3692 }
3693
3694 static void bnxt_dev_cleanup(struct bnxt *bp)
3695 {
3696         bnxt_set_hwrm_link_config(bp, false);
3697         bp->link_info.link_up = 0;
3698         if (bp->dev_stopped == 0)
3699                 bnxt_dev_stop_op(bp->eth_dev);
3700
3701         bnxt_uninit_resources(bp, true);
3702 }
3703
3704 static int bnxt_restore_filters(struct bnxt *bp)
3705 {
3706         struct rte_eth_dev *dev = bp->eth_dev;
3707         int ret = 0;
3708
3709         if (dev->data->all_multicast)
3710                 ret = bnxt_allmulticast_enable_op(dev);
3711         if (dev->data->promiscuous)
3712                 ret = bnxt_promiscuous_enable_op(dev);
3713
3714         /* TODO restore other filters as well */
3715         return ret;
3716 }
3717
3718 static void bnxt_dev_recover(void *arg)
3719 {
3720         struct bnxt *bp = arg;
3721         int timeout = bp->fw_reset_max_msecs;
3722         int rc = 0;
3723
3724         /* Clear Error flag so that device re-init should happen */
3725         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3726
3727         do {
3728                 rc = bnxt_hwrm_ver_get(bp);
3729                 if (rc == 0)
3730                         break;
3731                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3732                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3733         } while (rc && timeout);
3734
3735         if (rc) {
3736                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3737                 goto err;
3738         }
3739
3740         rc = bnxt_init_resources(bp, true);
3741         if (rc) {
3742                 PMD_DRV_LOG(ERR,
3743                             "Failed to initialize resources after reset\n");
3744                 goto err;
3745         }
3746         /* clear reset flag as the device is initialized now */
3747         bp->flags &= ~BNXT_FLAG_FW_RESET;
3748
3749         rc = bnxt_dev_start_op(bp->eth_dev);
3750         if (rc) {
3751                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3752                 goto err;
3753         }
3754
3755         rc = bnxt_restore_filters(bp);
3756         if (rc)
3757                 goto err;
3758
3759         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3760         return;
3761 err:
3762         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3763         bnxt_uninit_resources(bp, false);
3764         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3765 }
3766
3767 void bnxt_dev_reset_and_resume(void *arg)
3768 {
3769         struct bnxt *bp = arg;
3770         int rc;
3771
3772         bnxt_dev_cleanup(bp);
3773
3774         bnxt_wait_for_device_shutdown(bp);
3775
3776         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3777                                bnxt_dev_recover, (void *)bp);
3778         if (rc)
3779                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3780 }
3781
3782 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3783 {
3784         struct bnxt_error_recovery_info *info = bp->recovery_info;
3785         uint32_t reg = info->status_regs[index];
3786         uint32_t type, offset, val = 0;
3787
3788         type = BNXT_FW_STATUS_REG_TYPE(reg);
3789         offset = BNXT_FW_STATUS_REG_OFF(reg);
3790
3791         switch (type) {
3792         case BNXT_FW_STATUS_REG_TYPE_CFG:
3793                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3794                 break;
3795         case BNXT_FW_STATUS_REG_TYPE_GRC:
3796                 offset = info->mapped_status_regs[index];
3797                 /* FALLTHROUGH */
3798         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3799                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3800                                        offset));
3801                 break;
3802         }
3803
3804         return val;
3805 }
3806
3807 static int bnxt_fw_reset_all(struct bnxt *bp)
3808 {
3809         struct bnxt_error_recovery_info *info = bp->recovery_info;
3810         uint32_t i;
3811         int rc = 0;
3812
3813         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3814                 /* Reset through master function driver */
3815                 for (i = 0; i < info->reg_array_cnt; i++)
3816                         bnxt_write_fw_reset_reg(bp, i);
3817                 /* Wait for time specified by FW after triggering reset */
3818                 rte_delay_ms(info->master_func_wait_period_after_reset);
3819         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3820                 /* Reset with the help of Kong processor */
3821                 rc = bnxt_hwrm_fw_reset(bp);
3822                 if (rc)
3823                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3824         }
3825
3826         return rc;
3827 }
3828
3829 static void bnxt_fw_reset_cb(void *arg)
3830 {
3831         struct bnxt *bp = arg;
3832         struct bnxt_error_recovery_info *info = bp->recovery_info;
3833         int rc = 0;
3834
3835         /* Only Master function can do FW reset */
3836         if (bnxt_is_master_func(bp) &&
3837             bnxt_is_recovery_enabled(bp)) {
3838                 rc = bnxt_fw_reset_all(bp);
3839                 if (rc) {
3840                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3841                         return;
3842                 }
3843         }
3844
3845         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3846          * EXCEPTION_FATAL_ASYNC event to all the functions
3847          * (including MASTER FUNC). After receiving this Async, all the active
3848          * drivers should treat this case as FW initiated recovery
3849          */
3850         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3851                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3852                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3853
3854                 /* To recover from error */
3855                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3856                                   (void *)bp);
3857         }
3858 }
3859
3860 /* Driver should poll FW heartbeat, reset_counter with the frequency
3861  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3862  * When the driver detects heartbeat stop or change in reset_counter,
3863  * it has to trigger a reset to recover from the error condition.
3864  * A “master PF” is the function who will have the privilege to
3865  * initiate the chimp reset. The master PF will be elected by the
3866  * firmware and will be notified through async message.
3867  */
3868 static void bnxt_check_fw_health(void *arg)
3869 {
3870         struct bnxt *bp = arg;
3871         struct bnxt_error_recovery_info *info = bp->recovery_info;
3872         uint32_t val = 0, wait_msec;
3873
3874         if (!info || !bnxt_is_recovery_enabled(bp) ||
3875             is_bnxt_in_error(bp))
3876                 return;
3877
3878         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3879         if (val == info->last_heart_beat)
3880                 goto reset;
3881
3882         info->last_heart_beat = val;
3883
3884         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3885         if (val != info->last_reset_counter)
3886                 goto reset;
3887
3888         info->last_reset_counter = val;
3889
3890         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3891                           bnxt_check_fw_health, (void *)bp);
3892
3893         return;
3894 reset:
3895         /* Stop DMA to/from device */
3896         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3897         bp->flags |= BNXT_FLAG_FW_RESET;
3898
3899         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3900
3901         if (bnxt_is_master_func(bp))
3902                 wait_msec = info->master_func_wait_period;
3903         else
3904                 wait_msec = info->normal_func_wait_period;
3905
3906         rte_eal_alarm_set(US_PER_MS * wait_msec,
3907                           bnxt_fw_reset_cb, (void *)bp);
3908 }
3909
3910 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3911 {
3912         uint32_t polling_freq;
3913
3914         if (!bnxt_is_recovery_enabled(bp))
3915                 return;
3916
3917         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3918                 return;
3919
3920         polling_freq = bp->recovery_info->driver_polling_freq;
3921
3922         rte_eal_alarm_set(US_PER_MS * polling_freq,
3923                           bnxt_check_fw_health, (void *)bp);
3924         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3925 }
3926
3927 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3928 {
3929         if (!bnxt_is_recovery_enabled(bp))
3930                 return;
3931
3932         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3933         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3934 }
3935
3936 static bool bnxt_vf_pciid(uint16_t id)
3937 {
3938         if (id == BROADCOM_DEV_ID_57304_VF ||
3939             id == BROADCOM_DEV_ID_57406_VF ||
3940             id == BROADCOM_DEV_ID_5731X_VF ||
3941             id == BROADCOM_DEV_ID_5741X_VF ||
3942             id == BROADCOM_DEV_ID_57414_VF ||
3943             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3944             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3945             id == BROADCOM_DEV_ID_58802_VF ||
3946             id == BROADCOM_DEV_ID_57500_VF1 ||
3947             id == BROADCOM_DEV_ID_57500_VF2)
3948                 return true;
3949         return false;
3950 }
3951
3952 bool bnxt_stratus_device(struct bnxt *bp)
3953 {
3954         uint16_t id = bp->pdev->id.device_id;
3955
3956         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3957             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3958             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3959                 return true;
3960         return false;
3961 }
3962
3963 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3964 {
3965         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3966         struct bnxt *bp = eth_dev->data->dev_private;
3967
3968         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3969         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3970         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3971         if (!bp->bar0 || !bp->doorbell_base) {
3972                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3973                 return -ENODEV;
3974         }
3975
3976         bp->eth_dev = eth_dev;
3977         bp->pdev = pci_dev;
3978
3979         return 0;
3980 }
3981
3982 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3983                                   struct bnxt_ctx_pg_info *ctx_pg,
3984                                   uint32_t mem_size,
3985                                   const char *suffix,
3986                                   uint16_t idx)
3987 {
3988         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3989         const struct rte_memzone *mz = NULL;
3990         char mz_name[RTE_MEMZONE_NAMESIZE];
3991         rte_iova_t mz_phys_addr;
3992         uint64_t valid_bits = 0;
3993         uint32_t sz;
3994         int i;
3995
3996         if (!mem_size)
3997                 return 0;
3998
3999         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4000                          BNXT_PAGE_SIZE;
4001         rmem->page_size = BNXT_PAGE_SIZE;
4002         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4003         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4004         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4005
4006         valid_bits = PTU_PTE_VALID;
4007
4008         if (rmem->nr_pages > 1) {
4009                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4010                          "bnxt_ctx_pg_tbl%s_%x_%d",
4011                          suffix, idx, bp->eth_dev->data->port_id);
4012                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4013                 mz = rte_memzone_lookup(mz_name);
4014                 if (!mz) {
4015                         mz = rte_memzone_reserve_aligned(mz_name,
4016                                                 rmem->nr_pages * 8,
4017                                                 SOCKET_ID_ANY,
4018                                                 RTE_MEMZONE_2MB |
4019                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4020                                                 RTE_MEMZONE_IOVA_CONTIG,
4021                                                 BNXT_PAGE_SIZE);
4022                         if (mz == NULL)
4023                                 return -ENOMEM;
4024                 }
4025
4026                 memset(mz->addr, 0, mz->len);
4027                 mz_phys_addr = mz->iova;
4028                 if ((unsigned long)mz->addr == mz_phys_addr) {
4029                         PMD_DRV_LOG(DEBUG,
4030                                     "physical address same as virtual\n");
4031                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4032                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
4033                         if (mz_phys_addr == RTE_BAD_IOVA) {
4034                                 PMD_DRV_LOG(ERR,
4035                                         "unable to map addr to phys memory\n");
4036                                 return -ENOMEM;
4037                         }
4038                 }
4039                 rte_mem_lock_page(((char *)mz->addr));
4040
4041                 rmem->pg_tbl = mz->addr;
4042                 rmem->pg_tbl_map = mz_phys_addr;
4043                 rmem->pg_tbl_mz = mz;
4044         }
4045
4046         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4047                  suffix, idx, bp->eth_dev->data->port_id);
4048         mz = rte_memzone_lookup(mz_name);
4049         if (!mz) {
4050                 mz = rte_memzone_reserve_aligned(mz_name,
4051                                                  mem_size,
4052                                                  SOCKET_ID_ANY,
4053                                                  RTE_MEMZONE_1GB |
4054                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4055                                                  RTE_MEMZONE_IOVA_CONTIG,
4056                                                  BNXT_PAGE_SIZE);
4057                 if (mz == NULL)
4058                         return -ENOMEM;
4059         }
4060
4061         memset(mz->addr, 0, mz->len);
4062         mz_phys_addr = mz->iova;
4063         if ((unsigned long)mz->addr == mz_phys_addr) {
4064                 PMD_DRV_LOG(DEBUG,
4065                             "Memzone physical address same as virtual.\n");
4066                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4067                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4068                         rte_mem_lock_page(((char *)mz->addr) + sz);
4069                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4070                 if (mz_phys_addr == RTE_BAD_IOVA) {
4071                         PMD_DRV_LOG(ERR,
4072                                     "unable to map addr to phys memory\n");
4073                         return -ENOMEM;
4074                 }
4075         }
4076
4077         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4078                 rte_mem_lock_page(((char *)mz->addr) + sz);
4079                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4080                 rmem->dma_arr[i] = mz_phys_addr + sz;
4081
4082                 if (rmem->nr_pages > 1) {
4083                         if (i == rmem->nr_pages - 2 &&
4084                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4085                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4086                         else if (i == rmem->nr_pages - 1 &&
4087                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4088                                 valid_bits |= PTU_PTE_LAST;
4089
4090                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4091                                                            valid_bits);
4092                 }
4093         }
4094
4095         rmem->mz = mz;
4096         if (rmem->vmem_size)
4097                 rmem->vmem = (void **)mz->addr;
4098         rmem->dma_arr[0] = mz_phys_addr;
4099         return 0;
4100 }
4101
4102 static void bnxt_free_ctx_mem(struct bnxt *bp)
4103 {
4104         int i;
4105
4106         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4107                 return;
4108
4109         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4110         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4111         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4112         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4113         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4114         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4115         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4116         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4117         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4118         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4119         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4120
4121         for (i = 0; i < BNXT_MAX_Q; i++) {
4122                 if (bp->ctx->tqm_mem[i])
4123                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4124         }
4125
4126         rte_free(bp->ctx);
4127         bp->ctx = NULL;
4128 }
4129
4130 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4131
4132 #define min_t(type, x, y) ({                    \
4133         type __min1 = (x);                      \
4134         type __min2 = (y);                      \
4135         __min1 < __min2 ? __min1 : __min2; })
4136
4137 #define max_t(type, x, y) ({                    \
4138         type __max1 = (x);                      \
4139         type __max2 = (y);                      \
4140         __max1 > __max2 ? __max1 : __max2; })
4141
4142 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4143
4144 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4145 {
4146         struct bnxt_ctx_pg_info *ctx_pg;
4147         struct bnxt_ctx_mem_info *ctx;
4148         uint32_t mem_size, ena, entries;
4149         int i, rc;
4150
4151         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4152         if (rc) {
4153                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4154                 return rc;
4155         }
4156         ctx = bp->ctx;
4157         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4158                 return 0;
4159
4160         ctx_pg = &ctx->qp_mem;
4161         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4162         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4163         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4164         if (rc)
4165                 return rc;
4166
4167         ctx_pg = &ctx->srq_mem;
4168         ctx_pg->entries = ctx->srq_max_l2_entries;
4169         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4170         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4171         if (rc)
4172                 return rc;
4173
4174         ctx_pg = &ctx->cq_mem;
4175         ctx_pg->entries = ctx->cq_max_l2_entries;
4176         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4177         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4178         if (rc)
4179                 return rc;
4180
4181         ctx_pg = &ctx->vnic_mem;
4182         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4183                 ctx->vnic_max_ring_table_entries;
4184         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4185         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4186         if (rc)
4187                 return rc;
4188
4189         ctx_pg = &ctx->stat_mem;
4190         ctx_pg->entries = ctx->stat_max_entries;
4191         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4192         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4193         if (rc)
4194                 return rc;
4195
4196         entries = ctx->qp_max_l2_entries;
4197         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4198         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4199                           ctx->tqm_max_entries_per_ring);
4200         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4201                 ctx_pg = ctx->tqm_mem[i];
4202                 /* use min tqm entries for now. */
4203                 ctx_pg->entries = entries;
4204                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4205                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4206                 if (rc)
4207                         return rc;
4208                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4209         }
4210
4211         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4212         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4213         if (rc)
4214                 PMD_DRV_LOG(ERR,
4215                             "Failed to configure context mem: rc = %d\n", rc);
4216         else
4217                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4218
4219         return rc;
4220 }
4221
4222 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4223 {
4224         struct rte_pci_device *pci_dev = bp->pdev;
4225         char mz_name[RTE_MEMZONE_NAMESIZE];
4226         const struct rte_memzone *mz = NULL;
4227         uint32_t total_alloc_len;
4228         rte_iova_t mz_phys_addr;
4229
4230         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4231                 return 0;
4232
4233         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4234                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4235                  pci_dev->addr.bus, pci_dev->addr.devid,
4236                  pci_dev->addr.function, "rx_port_stats");
4237         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4238         mz = rte_memzone_lookup(mz_name);
4239         total_alloc_len =
4240                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4241                                        sizeof(struct rx_port_stats_ext) + 512);
4242         if (!mz) {
4243                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4244                                          SOCKET_ID_ANY,
4245                                          RTE_MEMZONE_2MB |
4246                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4247                                          RTE_MEMZONE_IOVA_CONTIG);
4248                 if (mz == NULL)
4249                         return -ENOMEM;
4250         }
4251         memset(mz->addr, 0, mz->len);
4252         mz_phys_addr = mz->iova;
4253         if ((unsigned long)mz->addr == mz_phys_addr) {
4254                 PMD_DRV_LOG(DEBUG,
4255                             "Memzone physical address same as virtual.\n");
4256                 PMD_DRV_LOG(DEBUG,
4257                             "Using rte_mem_virt2iova()\n");
4258                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4259                 if (mz_phys_addr == RTE_BAD_IOVA) {
4260                         PMD_DRV_LOG(ERR,
4261                                     "Can't map address to physical memory\n");
4262                         return -ENOMEM;
4263                 }
4264         }
4265
4266         bp->rx_mem_zone = (const void *)mz;
4267         bp->hw_rx_port_stats = mz->addr;
4268         bp->hw_rx_port_stats_map = mz_phys_addr;
4269
4270         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4271                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4272                  pci_dev->addr.bus, pci_dev->addr.devid,
4273                  pci_dev->addr.function, "tx_port_stats");
4274         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4275         mz = rte_memzone_lookup(mz_name);
4276         total_alloc_len =
4277                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4278                                        sizeof(struct tx_port_stats_ext) + 512);
4279         if (!mz) {
4280                 mz = rte_memzone_reserve(mz_name,
4281                                          total_alloc_len,
4282                                          SOCKET_ID_ANY,
4283                                          RTE_MEMZONE_2MB |
4284                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4285                                          RTE_MEMZONE_IOVA_CONTIG);
4286                 if (mz == NULL)
4287                         return -ENOMEM;
4288         }
4289         memset(mz->addr, 0, mz->len);
4290         mz_phys_addr = mz->iova;
4291         if ((unsigned long)mz->addr == mz_phys_addr) {
4292                 PMD_DRV_LOG(DEBUG,
4293                             "Memzone physical address same as virtual\n");
4294                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4295                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4296                 if (mz_phys_addr == RTE_BAD_IOVA) {
4297                         PMD_DRV_LOG(ERR,
4298                                     "Can't map address to physical memory\n");
4299                         return -ENOMEM;
4300                 }
4301         }
4302
4303         bp->tx_mem_zone = (const void *)mz;
4304         bp->hw_tx_port_stats = mz->addr;
4305         bp->hw_tx_port_stats_map = mz_phys_addr;
4306         bp->flags |= BNXT_FLAG_PORT_STATS;
4307
4308         /* Display extended statistics if FW supports it */
4309         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4310             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4311             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4312                 return 0;
4313
4314         bp->hw_rx_port_stats_ext = (void *)
4315                 ((uint8_t *)bp->hw_rx_port_stats +
4316                  sizeof(struct rx_port_stats));
4317         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4318                 sizeof(struct rx_port_stats);
4319         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4320
4321         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4322             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4323                 bp->hw_tx_port_stats_ext = (void *)
4324                         ((uint8_t *)bp->hw_tx_port_stats +
4325                          sizeof(struct tx_port_stats));
4326                 bp->hw_tx_port_stats_ext_map =
4327                         bp->hw_tx_port_stats_map +
4328                         sizeof(struct tx_port_stats);
4329                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4330         }
4331
4332         return 0;
4333 }
4334
4335 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4336 {
4337         struct bnxt *bp = eth_dev->data->dev_private;
4338         int rc = 0;
4339
4340         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4341                                                RTE_ETHER_ADDR_LEN *
4342                                                bp->max_l2_ctx,
4343                                                0);
4344         if (eth_dev->data->mac_addrs == NULL) {
4345                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4346                 return -ENOMEM;
4347         }
4348
4349         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4350                 if (BNXT_PF(bp))
4351                         return -EINVAL;
4352
4353                 /* Generate a random MAC address, if none was assigned by PF */
4354                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4355                 bnxt_eth_hw_addr_random(bp->mac_addr);
4356                 PMD_DRV_LOG(INFO,
4357                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4358                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4359                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4360
4361                 rc = bnxt_hwrm_set_mac(bp);
4362                 if (!rc)
4363                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4364                                RTE_ETHER_ADDR_LEN);
4365                 return rc;
4366         }
4367
4368         /* Copy the permanent MAC from the FUNC_QCAPS response */
4369         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4370         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4371
4372         return rc;
4373 }
4374
4375 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4376 {
4377         int rc = 0;
4378
4379         /* MAC is already configured in FW */
4380         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4381                 return 0;
4382
4383         /* Restore the old MAC configured */
4384         rc = bnxt_hwrm_set_mac(bp);
4385         if (rc)
4386                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4387
4388         return rc;
4389 }
4390
4391 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4392 {
4393         if (!BNXT_PF(bp))
4394                 return;
4395
4396 #define ALLOW_FUNC(x)   \
4397         { \
4398                 uint32_t arg = (x); \
4399                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4400                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4401         }
4402
4403         /* Forward all requests if firmware is new enough */
4404         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4405              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4406             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4407                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4408         } else {
4409                 PMD_DRV_LOG(WARNING,
4410                             "Firmware too old for VF mailbox functionality\n");
4411                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4412         }
4413
4414         /*
4415          * The following are used for driver cleanup. If we disallow these,
4416          * VF drivers can't clean up cleanly.
4417          */
4418         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4419         ALLOW_FUNC(HWRM_VNIC_FREE);
4420         ALLOW_FUNC(HWRM_RING_FREE);
4421         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4422         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4423         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4424         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4425         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4426         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4427 }
4428
4429 static int bnxt_init_fw(struct bnxt *bp)
4430 {
4431         uint16_t mtu;
4432         int rc = 0;
4433
4434         rc = bnxt_hwrm_ver_get(bp);
4435         if (rc)
4436                 return rc;
4437
4438         rc = bnxt_hwrm_func_reset(bp);
4439         if (rc)
4440                 return -EIO;
4441
4442         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4443         if (rc)
4444                 return rc;
4445
4446         rc = bnxt_hwrm_queue_qportcfg(bp);
4447         if (rc)
4448                 return rc;
4449
4450         /* Get the MAX capabilities for this function */
4451         rc = bnxt_hwrm_func_qcaps(bp);
4452         if (rc)
4453                 return rc;
4454
4455         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4456         if (rc)
4457                 return rc;
4458
4459         /* Get the adapter error recovery support info */
4460         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4461         if (rc)
4462                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4463
4464         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4465             mtu != bp->eth_dev->data->mtu)
4466                 bp->eth_dev->data->mtu = mtu;
4467
4468         bnxt_hwrm_port_led_qcaps(bp);
4469
4470         return 0;
4471 }
4472
4473 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4474 {
4475         int rc;
4476
4477         rc = bnxt_init_fw(bp);
4478         if (rc)
4479                 return rc;
4480
4481         if (!reconfig_dev) {
4482                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4483                 if (rc)
4484                         return rc;
4485         } else {
4486                 rc = bnxt_restore_dflt_mac(bp);
4487                 if (rc)
4488                         return rc;
4489         }
4490
4491         bnxt_config_vf_req_fwd(bp);
4492
4493         rc = bnxt_hwrm_func_driver_register(bp);
4494         if (rc) {
4495                 PMD_DRV_LOG(ERR, "Failed to register driver");
4496                 return -EBUSY;
4497         }
4498
4499         if (BNXT_PF(bp)) {
4500                 if (bp->pdev->max_vfs) {
4501                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4502                         if (rc) {
4503                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4504                                 return rc;
4505                         }
4506                 } else {
4507                         rc = bnxt_hwrm_allocate_pf_only(bp);
4508                         if (rc) {
4509                                 PMD_DRV_LOG(ERR,
4510                                             "Failed to allocate PF resources");
4511                                 return rc;
4512                         }
4513                 }
4514         }
4515
4516         rc = bnxt_alloc_mem(bp, reconfig_dev);
4517         if (rc)
4518                 return rc;
4519
4520         rc = bnxt_setup_int(bp);
4521         if (rc)
4522                 return rc;
4523
4524         bnxt_init_nic(bp);
4525
4526         rc = bnxt_request_int(bp);
4527         if (rc)
4528                 return rc;
4529
4530         return 0;
4531 }
4532
4533 static int
4534 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4535 {
4536         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4537         static int version_printed;
4538         struct bnxt *bp;
4539         int rc;
4540
4541         if (version_printed++ == 0)
4542                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4543
4544         eth_dev->dev_ops = &bnxt_dev_ops;
4545         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4546         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4547
4548         /*
4549          * For secondary processes, we don't initialise any further
4550          * as primary has already done this work.
4551          */
4552         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4553                 return 0;
4554
4555         rte_eth_copy_pci_info(eth_dev, pci_dev);
4556
4557         bp = eth_dev->data->dev_private;
4558
4559         bp->dev_stopped = 1;
4560
4561         if (bnxt_vf_pciid(pci_dev->id.device_id))
4562                 bp->flags |= BNXT_FLAG_VF;
4563
4564         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4565             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4566             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4567             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4568             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4569                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4570
4571         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4572             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4573             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4574             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4575                 bp->flags |= BNXT_FLAG_STINGRAY;
4576
4577         rc = bnxt_init_board(eth_dev);
4578         if (rc) {
4579                 PMD_DRV_LOG(ERR,
4580                             "Failed to initialize board rc: %x\n", rc);
4581                 return rc;
4582         }
4583
4584         rc = bnxt_alloc_hwrm_resources(bp);
4585         if (rc) {
4586                 PMD_DRV_LOG(ERR,
4587                             "Failed to allocate hwrm resource rc: %x\n", rc);
4588                 goto error_free;
4589         }
4590         rc = bnxt_init_resources(bp, false);
4591         if (rc)
4592                 goto error_free;
4593
4594         rc = bnxt_alloc_stats_mem(bp);
4595         if (rc)
4596                 goto error_free;
4597
4598         PMD_DRV_LOG(INFO,
4599                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4600                     pci_dev->mem_resource[0].phys_addr,
4601                     pci_dev->mem_resource[0].addr);
4602
4603         return 0;
4604
4605 error_free:
4606         bnxt_dev_uninit(eth_dev);
4607         return rc;
4608 }
4609
4610 static int
4611 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4612 {
4613         int rc;
4614
4615         bnxt_free_int(bp);
4616         bnxt_free_mem(bp, reconfig_dev);
4617         bnxt_hwrm_func_buf_unrgtr(bp);
4618         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4619         bp->flags &= ~BNXT_FLAG_REGISTERED;
4620         bnxt_free_ctx_mem(bp);
4621         if (!reconfig_dev) {
4622                 bnxt_free_hwrm_resources(bp);
4623
4624                 if (bp->recovery_info != NULL) {
4625                         rte_free(bp->recovery_info);
4626                         bp->recovery_info = NULL;
4627                 }
4628         }
4629
4630         rte_free(bp->ptp_cfg);
4631         bp->ptp_cfg = NULL;
4632         return rc;
4633 }
4634
4635 static int
4636 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4637 {
4638         struct bnxt *bp = eth_dev->data->dev_private;
4639         int rc;
4640
4641         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4642                 return -EPERM;
4643
4644         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4645
4646         rc = bnxt_uninit_resources(bp, false);
4647
4648         if (bp->grp_info != NULL) {
4649                 rte_free(bp->grp_info);
4650                 bp->grp_info = NULL;
4651         }
4652
4653         if (bp->tx_mem_zone) {
4654                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4655                 bp->tx_mem_zone = NULL;
4656         }
4657
4658         if (bp->rx_mem_zone) {
4659                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4660                 bp->rx_mem_zone = NULL;
4661         }
4662
4663         if (bp->dev_stopped == 0)
4664                 bnxt_dev_close_op(eth_dev);
4665         if (bp->pf.vf_info)
4666                 rte_free(bp->pf.vf_info);
4667         eth_dev->dev_ops = NULL;
4668         eth_dev->rx_pkt_burst = NULL;
4669         eth_dev->tx_pkt_burst = NULL;
4670
4671         return rc;
4672 }
4673
4674 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4675         struct rte_pci_device *pci_dev)
4676 {
4677         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4678                 bnxt_dev_init);
4679 }
4680
4681 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4682 {
4683         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4684                 return rte_eth_dev_pci_generic_remove(pci_dev,
4685                                 bnxt_dev_uninit);
4686         else
4687                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4688 }
4689
4690 static struct rte_pci_driver bnxt_rte_pmd = {
4691         .id_table = bnxt_pci_id_map,
4692         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4693         .probe = bnxt_pci_probe,
4694         .remove = bnxt_pci_remove,
4695 };
4696
4697 static bool
4698 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4699 {
4700         if (strcmp(dev->device->driver->name, drv->driver.name))
4701                 return false;
4702
4703         return true;
4704 }
4705
4706 bool is_bnxt_supported(struct rte_eth_dev *dev)
4707 {
4708         return is_device_supported(dev, &bnxt_rte_pmd);
4709 }
4710
4711 RTE_INIT(bnxt_init_log)
4712 {
4713         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4714         if (bnxt_logtype_driver >= 0)
4715                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4716 }
4717
4718 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4719 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4720 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");