drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100
 101 static const char *const bnxt_dev_args[] = {
 102         BNXT_DEVARG_REPRESENTOR,
 103         BNXT_DEVARG_TRUFLOW,
 104         BNXT_DEVARG_FLOW_XSTAT,
 105         BNXT_DEVARG_MAX_NUM_KFLOWS,
 106         BNXT_DEVARG_REP_BASED_PF,
 107         BNXT_DEVARG_REP_IS_PF,
 108         BNXT_DEVARG_REP_Q_R2F,
 109         BNXT_DEVARG_REP_Q_F2R,
 110         BNXT_DEVARG_REP_FC_R2F,
 111         BNXT_DEVARG_REP_FC_F2R,
 112         NULL
 113 };
 114
 115 /*
 116  * truflow == false to disable the feature
 117  * truflow == true to enable the feature
 118  */
 119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 120
 121 /*
 122  * flow_xstat == false to disable the feature
 123  * flow_xstat == true to enable the feature
 124  */
 125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 126
 127 /*
 128  * rep_is_pf == false to indicate VF representor
 129  * rep_is_pf == true to indicate PF representor
 130  */
 131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 132
 133 /*
 134  * rep_based_pf == Physical index of the PF
 135  */
 136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 137 /*
 138  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 139  */
 140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 141
 142 /*
 143  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 144  */
 145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 146
 147 /*
 148  * rep_fc_r2f == Flow control for the representor to endpoint direction
 149  */
 150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 151
 152 /*
 153  * rep_fc_f2r == Flow control for the endpoint to representor direction
 154  */
 155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 156
 157 int bnxt_cfa_code_dynfield_offset = -1;
 158
 159 /*
 160  * max_num_kflows must be >= 32
 161  * and must be a power-of-2 supported value
 162  * return: 1 -> invalid
 163  *         0 -> valid
 164  */
 165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 166 {
 167         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 168                 return 1;
 169         return 0;
 170 }
 171
 172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 178 static void bnxt_dev_recover(void *arg);
 179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 180 static void bnxt_free_rep_info(struct bnxt *bp);
 181
 182 int is_bnxt_in_error(struct bnxt *bp)
 183 {
 184         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 185                 return -EIO;
 186         if (bp->flags & BNXT_FLAG_FW_RESET)
 187                 return -EBUSY;
 188
 189         return 0;
 190 }
 191
 192 /***********************/
 193
 194 /*
 195  * High level utility functions
 196  */
 197
 198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 199 {
 200         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 201                                              BNXT_RSS_TBL_SIZE_P5);
 202
 203         if (!BNXT_CHIP_P5(bp))
 204                 return 1;
 205
 206         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 207                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 208                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 209 }
 210
 211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 212 {
 213         if (!BNXT_CHIP_P5(bp))
 214                 return HW_HASH_INDEX_SIZE;
 215
 216         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 217 }
 218
 219 static void bnxt_free_parent_info(struct bnxt *bp)
 220 {
 221         rte_free(bp->parent);
 222 }
 223
 224 static void bnxt_free_pf_info(struct bnxt *bp)
 225 {
 226         rte_free(bp->pf);
 227 }
 228
 229 static void bnxt_free_link_info(struct bnxt *bp)
 230 {
 231         rte_free(bp->link_info);
 232 }
 233
 234 static void bnxt_free_leds_info(struct bnxt *bp)
 235 {
 236         if (BNXT_VF(bp))
 237                 return;
 238
 239         rte_free(bp->leds);
 240         bp->leds = NULL;
 241 }
 242
 243 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 244 {
 245         rte_free(bp->flow_stat);
 246         bp->flow_stat = NULL;
 247 }
 248
 249 static void bnxt_free_cos_queues(struct bnxt *bp)
 250 {
 251         rte_free(bp->rx_cos_queue);
 252         rte_free(bp->tx_cos_queue);
 253 }
 254
 255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 256 {
 257         bnxt_free_filter_mem(bp);
 258         bnxt_free_vnic_attributes(bp);
 259         bnxt_free_vnic_mem(bp);
 260
 261         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 262          * If the number of rings change across fw update,
 263          * we don't have much choice except to warn the user.
 264          */
 265         if (!reconfig) {
 266                 bnxt_free_stats(bp);
 267                 bnxt_free_tx_rings(bp);
 268                 bnxt_free_rx_rings(bp);
 269         }
 270         bnxt_free_async_cp_ring(bp);
 271         bnxt_free_rxtx_nq_ring(bp);
 272
 273         rte_free(bp->grp_info);
 274         bp->grp_info = NULL;
 275 }
 276
 277 static int bnxt_alloc_parent_info(struct bnxt *bp)
 278 {
 279         bp->parent = rte_zmalloc("bnxt_parent_info",
 280                                  sizeof(struct bnxt_parent_info), 0);
 281         if (bp->parent == NULL)
 282                 return -ENOMEM;
 283
 284         return 0;
 285 }
 286
 287 static int bnxt_alloc_pf_info(struct bnxt *bp)
 288 {
 289         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 290         if (bp->pf == NULL)
 291                 return -ENOMEM;
 292
 293         return 0;
 294 }
 295
 296 static int bnxt_alloc_link_info(struct bnxt *bp)
 297 {
 298         bp->link_info =
 299                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 300         if (bp->link_info == NULL)
 301                 return -ENOMEM;
 302
 303         return 0;
 304 }
 305
 306 static int bnxt_alloc_leds_info(struct bnxt *bp)
 307 {
 308         if (BNXT_VF(bp))
 309                 return 0;
 310
 311         bp->leds = rte_zmalloc("bnxt_leds",
 312                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 313                                0);
 314         if (bp->leds == NULL)
 315                 return -ENOMEM;
 316
 317         return 0;
 318 }
 319
 320 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 321 {
 322         bp->rx_cos_queue =
 323                 rte_zmalloc("bnxt_rx_cosq",
 324                             BNXT_COS_QUEUE_COUNT *
 325                             sizeof(struct bnxt_cos_queue_info),
 326                             0);
 327         if (bp->rx_cos_queue == NULL)
 328                 return -ENOMEM;
 329
 330         bp->tx_cos_queue =
 331                 rte_zmalloc("bnxt_tx_cosq",
 332                             BNXT_COS_QUEUE_COUNT *
 333                             sizeof(struct bnxt_cos_queue_info),
 334                             0);
 335         if (bp->tx_cos_queue == NULL)
 336                 return -ENOMEM;
 337
 338         return 0;
 339 }
 340
 341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 342 {
 343         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 344                                     sizeof(struct bnxt_flow_stat_info), 0);
 345         if (bp->flow_stat == NULL)
 346                 return -ENOMEM;
 347
 348         return 0;
 349 }
 350
 351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 352 {
 353         int rc;
 354
 355         rc = bnxt_alloc_ring_grps(bp);
 356         if (rc)
 357                 goto alloc_mem_err;
 358
 359         rc = bnxt_alloc_async_ring_struct(bp);
 360         if (rc)
 361                 goto alloc_mem_err;
 362
 363         rc = bnxt_alloc_vnic_mem(bp);
 364         if (rc)
 365                 goto alloc_mem_err;
 366
 367         rc = bnxt_alloc_vnic_attributes(bp);
 368         if (rc)
 369                 goto alloc_mem_err;
 370
 371         rc = bnxt_alloc_filter_mem(bp);
 372         if (rc)
 373                 goto alloc_mem_err;
 374
 375         rc = bnxt_alloc_async_cp_ring(bp);
 376         if (rc)
 377                 goto alloc_mem_err;
 378
 379         rc = bnxt_alloc_rxtx_nq_ring(bp);
 380         if (rc)
 381                 goto alloc_mem_err;
 382
 383         if (BNXT_FLOW_XSTATS_EN(bp)) {
 384                 rc = bnxt_alloc_flow_stats_info(bp);
 385                 if (rc)
 386                         goto alloc_mem_err;
 387         }
 388
 389         return 0;
 390
 391 alloc_mem_err:
 392         bnxt_free_mem(bp, reconfig);
 393         return rc;
 394 }
 395
 396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 397 {
 398         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 399         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 400         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 401         struct bnxt_rx_queue *rxq;
 402         unsigned int j;
 403         int rc;
 404
 405         rc = bnxt_vnic_grp_alloc(bp, vnic);
 406         if (rc)
 407                 goto err_out;
 408
 409         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 410                     vnic_id, vnic, vnic->fw_grp_ids);
 411
 412         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 413         if (rc)
 414                 goto err_out;
 415
 416         /* Alloc RSS context only if RSS mode is enabled */
 417         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 418                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 419
 420                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 421                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 422                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 423                         PMD_DRV_LOG(ERR,
 424                                     "Only queues 0-%d will be in RSS table\n",
 425                                     BNXT_RSS_TBL_SIZE_P5 - 1);
 426                 }
 427
 428                 rc = 0;
 429                 for (j = 0; j < nr_ctxs; j++) {
 430                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 431                         if (rc)
 432                                 break;
 433                 }
 434                 if (rc) {
 435                         PMD_DRV_LOG(ERR,
 436                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 437                                     vnic_id, j, rc);
 438                         goto err_out;
 439                 }
 440                 vnic->num_lb_ctxts = nr_ctxs;
 441         }
 442
 443         /*
 444          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 445          * setting is not available at this time, it will not be
 446          * configured correctly in the CFA.
 447          */
 448         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 449                 vnic->vlan_strip = true;
 450         else
 451                 vnic->vlan_strip = false;
 452
 453         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 454         if (rc)
 455                 goto err_out;
 456
 457         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 458         if (rc)
 459                 goto err_out;
 460
 461         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 462                 rxq = bp->eth_dev->data->rx_queues[j];
 463
 464                 PMD_DRV_LOG(DEBUG,
 465                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 466                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 467
 468                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 469                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 470                 else
 471                         vnic->rx_queue_cnt++;
 472         }
 473
 474         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 475
 476         rc = bnxt_vnic_rss_configure(bp, vnic);
 477         if (rc)
 478                 goto err_out;
 479
 480         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 481
 482         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 483                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 484         else
 485                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 486
 487         return 0;
 488 err_out:
 489         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 490                     vnic_id, rc);
 491         return rc;
 492 }
 493
 494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 495 {
 496         int rc = 0;
 497
 498         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 499                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 500         if (rc)
 501                 return rc;
 502
 503         PMD_DRV_LOG(DEBUG,
 504                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 505                     " rx_fc_in_tbl.ctx_id = %d\n",
 506                     bp->flow_stat->rx_fc_in_tbl.va,
 507                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 508                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 509
 510         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 511                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 512         if (rc)
 513                 return rc;
 514
 515         PMD_DRV_LOG(DEBUG,
 516                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 517                     " rx_fc_out_tbl.ctx_id = %d\n",
 518                     bp->flow_stat->rx_fc_out_tbl.va,
 519                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 520                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 521
 522         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 523                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 524         if (rc)
 525                 return rc;
 526
 527         PMD_DRV_LOG(DEBUG,
 528                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 529                     " tx_fc_in_tbl.ctx_id = %d\n",
 530                     bp->flow_stat->tx_fc_in_tbl.va,
 531                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 532                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 533
 534         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 535                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 536         if (rc)
 537                 return rc;
 538
 539         PMD_DRV_LOG(DEBUG,
 540                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 541                     " tx_fc_out_tbl.ctx_id = %d\n",
 542                     bp->flow_stat->tx_fc_out_tbl.va,
 543                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 544                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 545
 546         memset(bp->flow_stat->rx_fc_out_tbl.va,
 547                0,
 548                bp->flow_stat->rx_fc_out_tbl.size);
 549         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 550                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 551                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 552                                        bp->flow_stat->max_fc,
 553                                        true);
 554         if (rc)
 555                 return rc;
 556
 557         memset(bp->flow_stat->tx_fc_out_tbl.va,
 558                0,
 559                bp->flow_stat->tx_fc_out_tbl.size);
 560         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 561                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 562                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 563                                        bp->flow_stat->max_fc,
 564                                        true);
 565
 566         return rc;
 567 }
 568
 569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 570                                   struct bnxt_ctx_mem_buf_info *ctx)
 571 {
 572         if (!ctx)
 573                 return -EINVAL;
 574
 575         ctx->va = rte_zmalloc(type, size, 0);
 576         if (ctx->va == NULL)
 577                 return -ENOMEM;
 578         rte_mem_lock_page(ctx->va);
 579         ctx->size = size;
 580         ctx->dma = rte_mem_virt2iova(ctx->va);
 581         if (ctx->dma == RTE_BAD_IOVA)
 582                 return -ENOMEM;
 583
 584         return 0;
 585 }
 586
 587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 588 {
 589         struct rte_pci_device *pdev = bp->pdev;
 590         char type[RTE_MEMZONE_NAMESIZE];
 591         uint16_t max_fc;
 592         int rc = 0;
 593
 594         max_fc = bp->flow_stat->max_fc;
 595
 596         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 597                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 598         /* 4 bytes for each counter-id */
 599         rc = bnxt_alloc_ctx_mem_buf(type,
 600                                     max_fc * 4,
 601                                     &bp->flow_stat->rx_fc_in_tbl);
 602         if (rc)
 603                 return rc;
 604
 605         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 606                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 607         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 608         rc = bnxt_alloc_ctx_mem_buf(type,
 609                                     max_fc * 16,
 610                                     &bp->flow_stat->rx_fc_out_tbl);
 611         if (rc)
 612                 return rc;
 613
 614         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 615                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 616         /* 4 bytes for each counter-id */
 617         rc = bnxt_alloc_ctx_mem_buf(type,
 618                                     max_fc * 4,
 619                                     &bp->flow_stat->tx_fc_in_tbl);
 620         if (rc)
 621                 return rc;
 622
 623         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 624                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 625         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 626         rc = bnxt_alloc_ctx_mem_buf(type,
 627                                     max_fc * 16,
 628                                     &bp->flow_stat->tx_fc_out_tbl);
 629         if (rc)
 630                 return rc;
 631
 632         rc = bnxt_register_fc_ctx_mem(bp);
 633
 634         return rc;
 635 }
 636
 637 static int bnxt_init_ctx_mem(struct bnxt *bp)
 638 {
 639         int rc = 0;
 640
 641         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 642             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 643             !BNXT_FLOW_XSTATS_EN(bp))
 644                 return 0;
 645
 646         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 647         if (rc)
 648                 return rc;
 649
 650         rc = bnxt_init_fc_ctx_mem(bp);
 651
 652         return rc;
 653 }
 654
 655 static int bnxt_update_phy_setting(struct bnxt *bp)
 656 {
 657         struct rte_eth_link new;
 658         int rc;
 659
 660         rc = bnxt_get_hwrm_link_config(bp, &new);
 661         if (rc) {
 662                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 663                 return rc;
 664         }
 665
 666         /*
 667          * On BCM957508-N2100 adapters, FW will not allow any user other
 668          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 669          * always returns link up. Force phy update always in that case.
 670          */
 671         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 672                 rc = bnxt_set_hwrm_link_config(bp, true);
 673                 if (rc) {
 674                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 675                         return rc;
 676                 }
 677         }
 678
 679         return rc;
 680 }
 681
 682 static int bnxt_init_chip(struct bnxt *bp)
 683 {
 684         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 685         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 686         uint32_t intr_vector = 0;
 687         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 688         uint32_t vec = BNXT_MISC_VEC_ID;
 689         unsigned int i, j;
 690         int rc;
 691
 692         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 693                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 694                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 695                 bp->flags |= BNXT_FLAG_JUMBO;
 696         } else {
 697                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 698                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 699                 bp->flags &= ~BNXT_FLAG_JUMBO;
 700         }
 701
 702         /* THOR does not support ring groups.
 703          * But we will use the array to save RSS context IDs.
 704          */
 705         if (BNXT_CHIP_P5(bp))
 706                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 707
 708         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 709         if (rc) {
 710                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 711                 goto err_out;
 712         }
 713
 714         rc = bnxt_alloc_hwrm_rings(bp);
 715         if (rc) {
 716                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 717                 goto err_out;
 718         }
 719
 720         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 721         if (rc) {
 722                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 723                 goto err_out;
 724         }
 725
 726         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 727                 goto skip_cosq_cfg;
 728
 729         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 730                 if (bp->rx_cos_queue[i].id != 0xff) {
 731                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 732
 733                         if (!vnic) {
 734                                 PMD_DRV_LOG(ERR,
 735                                             "Num pools more than FW profile\n");
 736                                 rc = -EINVAL;
 737                                 goto err_out;
 738                         }
 739                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 740                         bp->rx_cosq_cnt++;
 741                 }
 742         }
 743
 744 skip_cosq_cfg:
 745         rc = bnxt_mq_rx_configure(bp);
 746         if (rc) {
 747                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 748                 goto err_out;
 749         }
 750
 751         /* default vnic 0 */
 752         rc = bnxt_setup_one_vnic(bp, 0);
 753         if (rc)
 754                 goto err_out;
 755         /* VNIC configuration */
 756         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 757                 for (i = 1; i < bp->nr_vnics; i++) {
 758                         rc = bnxt_setup_one_vnic(bp, i);
 759                         if (rc)
 760                                 goto err_out;
 761                 }
 762         }
 763
 764         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 765         if (rc) {
 766                 PMD_DRV_LOG(ERR,
 767                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 768                 goto err_out;
 769         }
 770
 771         /* check and configure queue intr-vector mapping */
 772         if ((rte_intr_cap_multiple(intr_handle) ||
 773              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 774             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 775                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 776                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 777                 if (intr_vector > bp->rx_cp_nr_rings) {
 778                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 779                                         bp->rx_cp_nr_rings);
 780                         return -ENOTSUP;
 781                 }
 782                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 783                 if (rc)
 784                         return rc;
 785         }
 786
 787         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 788                 intr_handle->intr_vec =
 789                         rte_zmalloc("intr_vec",
 790                                     bp->eth_dev->data->nb_rx_queues *
 791                                     sizeof(int), 0);
 792                 if (intr_handle->intr_vec == NULL) {
 793                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 794                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 795                         rc = -ENOMEM;
 796                         goto err_disable;
 797                 }
 798                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 799                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 800                          intr_handle->intr_vec, intr_handle->nb_efd,
 801                         intr_handle->max_intr);
 802                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 803                      queue_id++) {
 804                         intr_handle->intr_vec[queue_id] =
 805                                                         vec + BNXT_RX_VEC_START;
 806                         if (vec < base + intr_handle->nb_efd - 1)
 807                                 vec++;
 808                 }
 809         }
 810
 811         /* enable uio/vfio intr/eventfd mapping */
 812         rc = rte_intr_enable(intr_handle);
 813 #ifndef RTE_EXEC_ENV_FREEBSD
 814         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 815         if (rc)
 816                 goto err_free;
 817 #endif
 818
 819         rc = bnxt_update_phy_setting(bp);
 820         if (rc)
 821                 goto err_free;
 822
 823         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 824         if (!bp->mark_table)
 825                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 826
 827         return 0;
 828
 829 err_free:
 830         rte_free(intr_handle->intr_vec);
 831 err_disable:
 832         rte_intr_efd_disable(intr_handle);
 833 err_out:
 834         /* Some of the error status returned by FW may not be from errno.h */
 835         if (rc > 0)
 836                 rc = -EIO;
 837
 838         return rc;
 839 }
 840
 841 static int bnxt_shutdown_nic(struct bnxt *bp)
 842 {
 843         bnxt_free_all_hwrm_resources(bp);
 844         bnxt_free_all_filters(bp);
 845         bnxt_free_all_vnics(bp);
 846         return 0;
 847 }
 848
 849 /*
 850  * Device configuration and status function
 851  */
 852
 853 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 854 {
 855         uint32_t link_speed = bp->link_info->support_speeds;
 856         uint32_t speed_capa = 0;
 857
 858         /* If PAM4 is configured, use PAM4 supported speed */
 859         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 860                 link_speed = bp->link_info->support_pam4_speeds;
 861
 862         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 863                 speed_capa |= ETH_LINK_SPEED_100M;
 864         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 865                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 866         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 867                 speed_capa |= ETH_LINK_SPEED_1G;
 868         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 869                 speed_capa |= ETH_LINK_SPEED_2_5G;
 870         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 871                 speed_capa |= ETH_LINK_SPEED_10G;
 872         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 873                 speed_capa |= ETH_LINK_SPEED_20G;
 874         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 875                 speed_capa |= ETH_LINK_SPEED_25G;
 876         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 877                 speed_capa |= ETH_LINK_SPEED_40G;
 878         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 879                 speed_capa |= ETH_LINK_SPEED_50G;
 880         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 881                 speed_capa |= ETH_LINK_SPEED_100G;
 882         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 883                 speed_capa |= ETH_LINK_SPEED_50G;
 884         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 885                 speed_capa |= ETH_LINK_SPEED_100G;
 886         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 887                 speed_capa |= ETH_LINK_SPEED_200G;
 888
 889         if (bp->link_info->auto_mode ==
 890             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 891                 speed_capa |= ETH_LINK_SPEED_FIXED;
 892         else
 893                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 894
 895         return speed_capa;
 896 }
 897
 898 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 899                                 struct rte_eth_dev_info *dev_info)
 900 {
 901         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 902         struct bnxt *bp = eth_dev->data->dev_private;
 903         uint16_t max_vnics, i, j, vpool, vrxq;
 904         unsigned int max_rx_rings;
 905         int rc;
 906
 907         rc = is_bnxt_in_error(bp);
 908         if (rc)
 909                 return rc;
 910
 911         /* MAC Specifics */
 912         dev_info->max_mac_addrs = bp->max_l2_ctx;
 913         dev_info->max_hash_mac_addrs = 0;
 914
 915         /* PF/VF specifics */
 916         if (BNXT_PF(bp))
 917                 dev_info->max_vfs = pdev->max_vfs;
 918
 919         max_rx_rings = bnxt_max_rings(bp);
 920         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 921         dev_info->max_rx_queues = max_rx_rings;
 922         dev_info->max_tx_queues = max_rx_rings;
 923         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 924         dev_info->hash_key_size = 40;
 925         max_vnics = bp->max_vnics;
 926
 927         /* MTU specifics */
 928         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 929         dev_info->max_mtu = BNXT_MAX_MTU;
 930
 931         /* Fast path specifics */
 932         dev_info->min_rx_bufsize = 1;
 933         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 934
 935         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 936         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 937                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 938         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 939         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 940                                     dev_info->tx_queue_offload_capa;
 941         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 942
 943         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 944
 945         /* *INDENT-OFF* */
 946         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 947                 .rx_thresh = {
 948                         .pthresh = 8,
 949                         .hthresh = 8,
 950                         .wthresh = 0,
 951                 },
 952                 .rx_free_thresh = 32,
 953                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 954         };
 955
 956         dev_info->default_txconf = (struct rte_eth_txconf) {
 957                 .tx_thresh = {
 958                         .pthresh = 32,
 959                         .hthresh = 0,
 960                         .wthresh = 0,
 961                 },
 962                 .tx_free_thresh = 32,
 963                 .tx_rs_thresh = 32,
 964         };
 965         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 966
 967         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 968         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 969         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 970         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 971         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 972
 973         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 974                 dev_info->switch_info.name = eth_dev->device->name;
 975                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 976                 dev_info->switch_info.port_id =
 977                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 978                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 979         }
 980
 981         /* *INDENT-ON* */
 982
 983         /*
 984          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 985          *       need further investigation.
 986          */
 987
 988         /* VMDq resources */
 989         vpool = 64; /* ETH_64_POOLS */
 990         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 991         for (i = 0; i < 4; vpool >>= 1, i++) {
 992                 if (max_vnics > vpool) {
 993                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 994                                 if (dev_info->max_rx_queues > vrxq) {
 995                                         if (vpool > vrxq)
 996                                                 vpool = vrxq;
 997                                         goto found;
 998                                 }
 999                         }
1000                         /* Not enough resources to support VMDq */
1001                         break;
1002                 }
1003         }
1004         /* Not enough resources to support VMDq */
1005         vpool = 0;
1006         vrxq = 0;
1007 found:
1008         dev_info->max_vmdq_pools = vpool;
1009         dev_info->vmdq_queue_num = vrxq;
1010
1011         dev_info->vmdq_pool_base = 0;
1012         dev_info->vmdq_queue_base = 0;
1013
1014         return 0;
1015 }
1016
1017 /* Configure the device based on the configuration provided */
1018 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1019 {
1020         struct bnxt *bp = eth_dev->data->dev_private;
1021         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1022         int rc;
1023
1024         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1025         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1026         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1027         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1028
1029         rc = is_bnxt_in_error(bp);
1030         if (rc)
1031                 return rc;
1032
1033         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1034                 rc = bnxt_hwrm_check_vf_rings(bp);
1035                 if (rc) {
1036                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1037                         return -ENOSPC;
1038                 }
1039
1040                 /* If a resource has already been allocated - in this case
1041                  * it is the async completion ring, free it. Reallocate it after
1042                  * resource reservation. This will ensure the resource counts
1043                  * are calculated correctly.
1044                  */
1045
1046                 pthread_mutex_lock(&bp->def_cp_lock);
1047
1048                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1049                         bnxt_disable_int(bp);
1050                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1051                 }
1052
1053                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1054                 if (rc) {
1055                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1056                         pthread_mutex_unlock(&bp->def_cp_lock);
1057                         return -ENOSPC;
1058                 }
1059
1060                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1061                         rc = bnxt_alloc_async_cp_ring(bp);
1062                         if (rc) {
1063                                 pthread_mutex_unlock(&bp->def_cp_lock);
1064                                 return rc;
1065                         }
1066                         bnxt_enable_int(bp);
1067                 }
1068
1069                 pthread_mutex_unlock(&bp->def_cp_lock);
1070         }
1071
1072         /* Inherit new configurations */
1073         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1074             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1075             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1076                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1077             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1078             bp->max_stat_ctx)
1079                 goto resource_error;
1080
1081         if (BNXT_HAS_RING_GRPS(bp) &&
1082             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1083                 goto resource_error;
1084
1085         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1086             bp->max_vnics < eth_dev->data->nb_rx_queues)
1087                 goto resource_error;
1088
1089         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1090         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1091
1092         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1093                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1094         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1095
1096         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1097                 eth_dev->data->mtu =
1098                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1099                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1100                         BNXT_NUM_VLANS;
1101                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1102         }
1103         return 0;
1104
1105 resource_error:
1106         PMD_DRV_LOG(ERR,
1107                     "Insufficient resources to support requested config\n");
1108         PMD_DRV_LOG(ERR,
1109                     "Num Queues Requested: Tx %d, Rx %d\n",
1110                     eth_dev->data->nb_tx_queues,
1111                     eth_dev->data->nb_rx_queues);
1112         PMD_DRV_LOG(ERR,
1113                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1114                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1115                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1116         return -ENOSPC;
1117 }
1118
1119 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1120 {
1121         struct rte_eth_link *link = &eth_dev->data->dev_link;
1122
1123         if (link->link_status)
1124                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1125                         eth_dev->data->port_id,
1126                         (uint32_t)link->link_speed,
1127                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1128                         ("full-duplex") : ("half-duplex\n"));
1129         else
1130                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1131                         eth_dev->data->port_id);
1132 }
1133
1134 /*
1135  * Determine whether the current configuration requires support for scattered
1136  * receive; return 1 if scattered receive is required and 0 if not.
1137  */
1138 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1139 {
1140         uint16_t buf_size;
1141         int i;
1142
1143         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1144                 return 1;
1145
1146         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1147                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1148
1149                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1150                                       RTE_PKTMBUF_HEADROOM);
1151                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1152                         return 1;
1153         }
1154         return 0;
1155 }
1156
1157 static eth_rx_burst_t
1158 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1159 {
1160         struct bnxt *bp = eth_dev->data->dev_private;
1161
1162         /* Disable vector mode RX for Stingray2 for now */
1163         if (BNXT_CHIP_SR2(bp)) {
1164                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1165                 return bnxt_recv_pkts;
1166         }
1167
1168 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1169 #ifndef RTE_LIBRTE_IEEE1588
1170         /*
1171          * Vector mode receive can be enabled only if scatter rx is not
1172          * in use and rx offloads are limited to VLAN stripping and
1173          * CRC stripping.
1174          */
1175         if (!eth_dev->data->scattered_rx &&
1176             !(eth_dev->data->dev_conf.rxmode.offloads &
1177               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1178                 DEV_RX_OFFLOAD_KEEP_CRC |
1179                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1180                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1181                 DEV_RX_OFFLOAD_UDP_CKSUM |
1182                 DEV_RX_OFFLOAD_TCP_CKSUM |
1183                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1184                 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1185                 DEV_RX_OFFLOAD_RSS_HASH |
1186                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1187             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1188             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1189                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1190                             eth_dev->data->port_id);
1191                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1192                 return bnxt_recv_pkts_vec;
1193         }
1194         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1195                     eth_dev->data->port_id);
1196         PMD_DRV_LOG(INFO,
1197                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1198                     eth_dev->data->port_id,
1199                     eth_dev->data->scattered_rx,
1200                     eth_dev->data->dev_conf.rxmode.offloads);
1201 #endif
1202 #endif
1203         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1204         return bnxt_recv_pkts;
1205 }
1206
1207 static eth_tx_burst_t
1208 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1209 {
1210         struct bnxt *bp = eth_dev->data->dev_private;
1211
1212         /* Disable vector mode TX for Stingray2 for now */
1213         if (BNXT_CHIP_SR2(bp))
1214                 return bnxt_xmit_pkts;
1215
1216 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1217 #ifndef RTE_LIBRTE_IEEE1588
1218         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1219
1220         /*
1221          * Vector mode transmit can be enabled only if not using scatter rx
1222          * or tx offloads.
1223          */
1224         if (!eth_dev->data->scattered_rx &&
1225             !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1226             !BNXT_TRUFLOW_EN(bp) &&
1227             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1228                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1229                             eth_dev->data->port_id);
1230                 return bnxt_xmit_pkts_vec;
1231         }
1232         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1233                     eth_dev->data->port_id);
1234         PMD_DRV_LOG(INFO,
1235                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1236                     eth_dev->data->port_id,
1237                     eth_dev->data->scattered_rx,
1238                     offloads);
1239 #endif
1240 #endif
1241         return bnxt_xmit_pkts;
1242 }
1243
1244 static int bnxt_handle_if_change_status(struct bnxt *bp)
1245 {
1246         int rc;
1247
1248         /* Since fw has undergone a reset and lost all contexts,
1249          * set fatal flag to not issue hwrm during cleanup
1250          */
1251         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1252         bnxt_uninit_resources(bp, true);
1253
1254         /* clear fatal flag so that re-init happens */
1255         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1256         rc = bnxt_init_resources(bp, true);
1257
1258         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1259
1260         return rc;
1261 }
1262
1263 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1264 {
1265         struct bnxt *bp = eth_dev->data->dev_private;
1266         int rc = 0;
1267
1268         if (!bp->link_info->link_up)
1269                 rc = bnxt_set_hwrm_link_config(bp, true);
1270         if (!rc)
1271                 eth_dev->data->dev_link.link_status = 1;
1272
1273         bnxt_print_link_info(eth_dev);
1274         return rc;
1275 }
1276
1277 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1278 {
1279         struct bnxt *bp = eth_dev->data->dev_private;
1280
1281         eth_dev->data->dev_link.link_status = 0;
1282         bnxt_set_hwrm_link_config(bp, false);
1283         bp->link_info->link_up = 0;
1284
1285         return 0;
1286 }
1287
1288 static void bnxt_free_switch_domain(struct bnxt *bp)
1289 {
1290         int rc = 0;
1291
1292         if (bp->switch_domain_id) {
1293                 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1294                 if (rc)
1295                         PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1296                                     bp->switch_domain_id, rc);
1297         }
1298 }
1299
1300 /* Unload the driver, release resources */
1301 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1302 {
1303         struct bnxt *bp = eth_dev->data->dev_private;
1304         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1305         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1306         struct rte_eth_link link;
1307         int ret;
1308
1309         eth_dev->data->dev_started = 0;
1310         eth_dev->data->scattered_rx = 0;
1311
1312         /* Prevent crashes when queues are still in use */
1313         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1314         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1315
1316         bnxt_disable_int(bp);
1317
1318         /* disable uio/vfio intr/eventfd mapping */
1319         rte_intr_disable(intr_handle);
1320
1321         /* Stop the child representors for this device */
1322         ret = bnxt_rep_stop_all(bp);
1323         if (ret != 0)
1324                 return ret;
1325
1326         /* delete the bnxt ULP port details */
1327         bnxt_ulp_port_deinit(bp);
1328
1329         bnxt_cancel_fw_health_check(bp);
1330
1331         /* Do not bring link down during reset recovery */
1332         if (!is_bnxt_in_error(bp)) {
1333                 bnxt_dev_set_link_down_op(eth_dev);
1334                 /* Wait for link to be reset */
1335                 if (BNXT_SINGLE_PF(bp))
1336                         rte_delay_ms(500);
1337                 /* clear the recorded link status */
1338                 memset(&link, 0, sizeof(link));
1339                 rte_eth_linkstatus_set(eth_dev, &link);
1340         }
1341
1342         /* Clean queue intr-vector mapping */
1343         rte_intr_efd_disable(intr_handle);
1344         if (intr_handle->intr_vec != NULL) {
1345                 rte_free(intr_handle->intr_vec);
1346                 intr_handle->intr_vec = NULL;
1347         }
1348
1349         bnxt_hwrm_port_clr_stats(bp);
1350         bnxt_free_tx_mbufs(bp);
1351         bnxt_free_rx_mbufs(bp);
1352         /* Process any remaining notifications in default completion queue */
1353         bnxt_int_handler(eth_dev);
1354         bnxt_shutdown_nic(bp);
1355         bnxt_hwrm_if_change(bp, false);
1356
1357         rte_free(bp->mark_table);
1358         bp->mark_table = NULL;
1359
1360         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1361         bp->rx_cosq_cnt = 0;
1362         /* All filters are deleted on a port stop. */
1363         if (BNXT_FLOW_XSTATS_EN(bp))
1364                 bp->flow_stat->flow_count = 0;
1365
1366         return 0;
1367 }
1368
1369 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1370 {
1371         struct bnxt *bp = eth_dev->data->dev_private;
1372         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1373         int vlan_mask = 0;
1374         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1375
1376         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1377                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1378                 return -EINVAL;
1379         }
1380
1381         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1382                 PMD_DRV_LOG(ERR,
1383                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1384                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1385
1386         do {
1387                 rc = bnxt_hwrm_if_change(bp, true);
1388                 if (rc == 0 || rc != -EAGAIN)
1389                         break;
1390
1391                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1392         } while (retry_cnt--);
1393
1394         if (rc)
1395                 return rc;
1396
1397         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1398                 rc = bnxt_handle_if_change_status(bp);
1399                 if (rc)
1400                         return rc;
1401         }
1402
1403         bnxt_enable_int(bp);
1404
1405         rc = bnxt_init_chip(bp);
1406         if (rc)
1407                 goto error;
1408
1409         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1410         eth_dev->data->dev_started = 1;
1411
1412         bnxt_link_update_op(eth_dev, 1);
1413
1414         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1415                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1416         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1417                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1418         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1419         if (rc)
1420                 goto error;
1421
1422         /* Initialize bnxt ULP port details */
1423         rc = bnxt_ulp_port_init(bp);
1424         if (rc)
1425                 goto error;
1426
1427         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1428         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1429
1430         bnxt_schedule_fw_health_check(bp);
1431
1432         return 0;
1433
1434 error:
1435         bnxt_dev_stop_op(eth_dev);
1436         return rc;
1437 }
1438
1439 static void
1440 bnxt_uninit_locks(struct bnxt *bp)
1441 {
1442         pthread_mutex_destroy(&bp->flow_lock);
1443         pthread_mutex_destroy(&bp->def_cp_lock);
1444         pthread_mutex_destroy(&bp->health_check_lock);
1445         if (bp->rep_info) {
1446                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1447                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1448         }
1449 }
1450
1451 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1452 {
1453         struct bnxt *bp = eth_dev->data->dev_private;
1454         int ret = 0;
1455
1456         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1457                 return 0;
1458
1459         /* cancel the recovery handler before remove dev */
1460         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1461         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1462         bnxt_cancel_fc_thread(bp);
1463
1464         if (eth_dev->data->dev_started)
1465                 ret = bnxt_dev_stop_op(eth_dev);
1466
1467         bnxt_free_switch_domain(bp);
1468
1469         bnxt_uninit_resources(bp, false);
1470
1471         bnxt_free_leds_info(bp);
1472         bnxt_free_cos_queues(bp);
1473         bnxt_free_link_info(bp);
1474         bnxt_free_pf_info(bp);
1475         bnxt_free_parent_info(bp);
1476         bnxt_uninit_locks(bp);
1477
1478         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1479         bp->tx_mem_zone = NULL;
1480         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1481         bp->rx_mem_zone = NULL;
1482
1483         bnxt_hwrm_free_vf_info(bp);
1484
1485         rte_free(bp->grp_info);
1486         bp->grp_info = NULL;
1487
1488         return ret;
1489 }
1490
1491 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1492                                     uint32_t index)
1493 {
1494         struct bnxt *bp = eth_dev->data->dev_private;
1495         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1496         struct bnxt_vnic_info *vnic;
1497         struct bnxt_filter_info *filter, *temp_filter;
1498         uint32_t i;
1499
1500         if (is_bnxt_in_error(bp))
1501                 return;
1502
1503         /*
1504          * Loop through all VNICs from the specified filter flow pools to
1505          * remove the corresponding MAC addr filter
1506          */
1507         for (i = 0; i < bp->nr_vnics; i++) {
1508                 if (!(pool_mask & (1ULL << i)))
1509                         continue;
1510
1511                 vnic = &bp->vnic_info[i];
1512                 filter = STAILQ_FIRST(&vnic->filter);
1513                 while (filter) {
1514                         temp_filter = STAILQ_NEXT(filter, next);
1515                         if (filter->mac_index == index) {
1516                                 STAILQ_REMOVE(&vnic->filter, filter,
1517                                                 bnxt_filter_info, next);
1518                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1519                                 bnxt_free_filter(bp, filter);
1520                         }
1521                         filter = temp_filter;
1522                 }
1523         }
1524 }
1525
1526 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1527                                struct rte_ether_addr *mac_addr, uint32_t index,
1528                                uint32_t pool)
1529 {
1530         struct bnxt_filter_info *filter;
1531         int rc = 0;
1532
1533         /* Attach requested MAC address to the new l2_filter */
1534         STAILQ_FOREACH(filter, &vnic->filter, next) {
1535                 if (filter->mac_index == index) {
1536                         PMD_DRV_LOG(DEBUG,
1537                                     "MAC addr already existed for pool %d\n",
1538                                     pool);
1539                         return 0;
1540                 }
1541         }
1542
1543         filter = bnxt_alloc_filter(bp);
1544         if (!filter) {
1545                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1546                 return -ENODEV;
1547         }
1548
1549         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1550          * if the MAC that's been programmed now is a different one, then,
1551          * copy that addr to filter->l2_addr
1552          */
1553         if (mac_addr)
1554                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1555         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1556
1557         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1558         if (!rc) {
1559                 filter->mac_index = index;
1560                 if (filter->mac_index == 0)
1561                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1562                 else
1563                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1564         } else {
1565                 bnxt_free_filter(bp, filter);
1566         }
1567
1568         return rc;
1569 }
1570
1571 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1572                                 struct rte_ether_addr *mac_addr,
1573                                 uint32_t index, uint32_t pool)
1574 {
1575         struct bnxt *bp = eth_dev->data->dev_private;
1576         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1577         int rc = 0;
1578
1579         rc = is_bnxt_in_error(bp);
1580         if (rc)
1581                 return rc;
1582
1583         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1584                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1585                 return -ENOTSUP;
1586         }
1587
1588         if (!vnic) {
1589                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1590                 return -EINVAL;
1591         }
1592
1593         /* Filter settings will get applied when port is started */
1594         if (!eth_dev->data->dev_started)
1595                 return 0;
1596
1597         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1598
1599         return rc;
1600 }
1601
1602 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1603 {
1604         int rc = 0;
1605         struct bnxt *bp = eth_dev->data->dev_private;
1606         struct rte_eth_link new;
1607         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1608                         BNXT_MIN_LINK_WAIT_CNT;
1609
1610         rc = is_bnxt_in_error(bp);
1611         if (rc)
1612                 return rc;
1613
1614         memset(&new, 0, sizeof(new));
1615         do {
1616                 /* Retrieve link info from hardware */
1617                 rc = bnxt_get_hwrm_link_config(bp, &new);
1618                 if (rc) {
1619                         new.link_speed = ETH_LINK_SPEED_100M;
1620                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1621                         PMD_DRV_LOG(ERR,
1622                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1623                         goto out;
1624                 }
1625
1626                 if (!wait_to_complete || new.link_status)
1627                         break;
1628
1629                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1630         } while (cnt--);
1631
1632         /* Only single function PF can bring phy down.
1633          * When port is stopped, report link down for VF/MH/NPAR functions.
1634          */
1635         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1636                 memset(&new, 0, sizeof(new));
1637
1638 out:
1639         /* Timed out or success */
1640         if (new.link_status != eth_dev->data->dev_link.link_status ||
1641             new.link_speed != eth_dev->data->dev_link.link_speed) {
1642                 rte_eth_linkstatus_set(eth_dev, &new);
1643
1644                 rte_eth_dev_callback_process(eth_dev,
1645                                              RTE_ETH_EVENT_INTR_LSC,
1646                                              NULL);
1647
1648                 bnxt_print_link_info(eth_dev);
1649         }
1650
1651         return rc;
1652 }
1653
1654 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1655 {
1656         struct bnxt *bp = eth_dev->data->dev_private;
1657         struct bnxt_vnic_info *vnic;
1658         uint32_t old_flags;
1659         int rc;
1660
1661         rc = is_bnxt_in_error(bp);
1662         if (rc)
1663                 return rc;
1664
1665         /* Filter settings will get applied when port is started */
1666         if (!eth_dev->data->dev_started)
1667                 return 0;
1668
1669         if (bp->vnic_info == NULL)
1670                 return 0;
1671
1672         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1673
1674         old_flags = vnic->flags;
1675         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1676         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1677         if (rc != 0)
1678                 vnic->flags = old_flags;
1679
1680         return rc;
1681 }
1682
1683 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1684 {
1685         struct bnxt *bp = eth_dev->data->dev_private;
1686         struct bnxt_vnic_info *vnic;
1687         uint32_t old_flags;
1688         int rc;
1689
1690         rc = is_bnxt_in_error(bp);
1691         if (rc)
1692                 return rc;
1693
1694         /* Filter settings will get applied when port is started */
1695         if (!eth_dev->data->dev_started)
1696                 return 0;
1697
1698         if (bp->vnic_info == NULL)
1699                 return 0;
1700
1701         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1702
1703         old_flags = vnic->flags;
1704         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1705         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1706         if (rc != 0)
1707                 vnic->flags = old_flags;
1708
1709         return rc;
1710 }
1711
1712 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1713 {
1714         struct bnxt *bp = eth_dev->data->dev_private;
1715         struct bnxt_vnic_info *vnic;
1716         uint32_t old_flags;
1717         int rc;
1718
1719         rc = is_bnxt_in_error(bp);
1720         if (rc)
1721                 return rc;
1722
1723         /* Filter settings will get applied when port is started */
1724         if (!eth_dev->data->dev_started)
1725                 return 0;
1726
1727         if (bp->vnic_info == NULL)
1728                 return 0;
1729
1730         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1731
1732         old_flags = vnic->flags;
1733         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1734         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1735         if (rc != 0)
1736                 vnic->flags = old_flags;
1737
1738         return rc;
1739 }
1740
1741 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1742 {
1743         struct bnxt *bp = eth_dev->data->dev_private;
1744         struct bnxt_vnic_info *vnic;
1745         uint32_t old_flags;
1746         int rc;
1747
1748         rc = is_bnxt_in_error(bp);
1749         if (rc)
1750                 return rc;
1751
1752         /* Filter settings will get applied when port is started */
1753         if (!eth_dev->data->dev_started)
1754                 return 0;
1755
1756         if (bp->vnic_info == NULL)
1757                 return 0;
1758
1759         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1760
1761         old_flags = vnic->flags;
1762         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1763         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1764         if (rc != 0)
1765                 vnic->flags = old_flags;
1766
1767         return rc;
1768 }
1769
1770 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1771 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1772 {
1773         if (qid >= bp->rx_nr_rings)
1774                 return NULL;
1775
1776         return bp->eth_dev->data->rx_queues[qid];
1777 }
1778
1779 /* Return rxq corresponding to a given rss table ring/group ID. */
1780 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1781 {
1782         struct bnxt_rx_queue *rxq;
1783         unsigned int i;
1784
1785         if (!BNXT_HAS_RING_GRPS(bp)) {
1786                 for (i = 0; i < bp->rx_nr_rings; i++) {
1787                         rxq = bp->eth_dev->data->rx_queues[i];
1788                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1789                                 return rxq->index;
1790                 }
1791         } else {
1792                 for (i = 0; i < bp->rx_nr_rings; i++) {
1793                         if (bp->grp_info[i].fw_grp_id == fwr)
1794                                 return i;
1795                 }
1796         }
1797
1798         return INVALID_HW_RING_ID;
1799 }
1800
1801 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1802                             struct rte_eth_rss_reta_entry64 *reta_conf,
1803                             uint16_t reta_size)
1804 {
1805         struct bnxt *bp = eth_dev->data->dev_private;
1806         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1807         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1808         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1809         uint16_t idx, sft;
1810         int i, rc;
1811
1812         rc = is_bnxt_in_error(bp);
1813         if (rc)
1814                 return rc;
1815
1816         if (!vnic->rss_table)
1817                 return -EINVAL;
1818
1819         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1820                 return -EINVAL;
1821
1822         if (reta_size != tbl_size) {
1823                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1824                         "(%d) must equal the size supported by the hardware "
1825                         "(%d)\n", reta_size, tbl_size);
1826                 return -EINVAL;
1827         }
1828
1829         for (i = 0; i < reta_size; i++) {
1830                 struct bnxt_rx_queue *rxq;
1831
1832                 idx = i / RTE_RETA_GROUP_SIZE;
1833                 sft = i % RTE_RETA_GROUP_SIZE;
1834
1835                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1836                         continue;
1837
1838                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1839                 if (!rxq) {
1840                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1841                         return -EINVAL;
1842                 }
1843
1844                 if (BNXT_CHIP_P5(bp)) {
1845                         vnic->rss_table[i * 2] =
1846                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1847                         vnic->rss_table[i * 2 + 1] =
1848                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1849                 } else {
1850                         vnic->rss_table[i] =
1851                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1852                 }
1853         }
1854
1855         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1856         return rc;
1857 }
1858
1859 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1860                               struct rte_eth_rss_reta_entry64 *reta_conf,
1861                               uint16_t reta_size)
1862 {
1863         struct bnxt *bp = eth_dev->data->dev_private;
1864         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1865         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1866         uint16_t idx, sft, i;
1867         int rc;
1868
1869         rc = is_bnxt_in_error(bp);
1870         if (rc)
1871                 return rc;
1872
1873         /* Retrieve from the default VNIC */
1874         if (!vnic)
1875                 return -EINVAL;
1876         if (!vnic->rss_table)
1877                 return -EINVAL;
1878
1879         if (reta_size != tbl_size) {
1880                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1881                         "(%d) must equal the size supported by the hardware "
1882                         "(%d)\n", reta_size, tbl_size);
1883                 return -EINVAL;
1884         }
1885
1886         for (idx = 0, i = 0; i < reta_size; i++) {
1887                 idx = i / RTE_RETA_GROUP_SIZE;
1888                 sft = i % RTE_RETA_GROUP_SIZE;
1889
1890                 if (reta_conf[idx].mask & (1ULL << sft)) {
1891                         uint16_t qid;
1892
1893                         if (BNXT_CHIP_P5(bp))
1894                                 qid = bnxt_rss_to_qid(bp,
1895                                                       vnic->rss_table[i * 2]);
1896                         else
1897                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1898
1899                         if (qid == INVALID_HW_RING_ID) {
1900                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1901                                 return -EINVAL;
1902                         }
1903                         reta_conf[idx].reta[sft] = qid;
1904                 }
1905         }
1906
1907         return 0;
1908 }
1909
1910 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1911                                    struct rte_eth_rss_conf *rss_conf)
1912 {
1913         struct bnxt *bp = eth_dev->data->dev_private;
1914         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1915         struct bnxt_vnic_info *vnic;
1916         int rc;
1917
1918         rc = is_bnxt_in_error(bp);
1919         if (rc)
1920                 return rc;
1921
1922         /*
1923          * If RSS enablement were different than dev_configure,
1924          * then return -EINVAL
1925          */
1926         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1927                 if (!rss_conf->rss_hf)
1928                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1929         } else {
1930                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1931                         return -EINVAL;
1932         }
1933
1934         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1935         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1936                rss_conf,
1937                sizeof(*rss_conf));
1938
1939         /* Update the default RSS VNIC(s) */
1940         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1941         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1942         vnic->hash_mode =
1943                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1944                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
1945
1946         /*
1947          * If hashkey is not specified, use the previously configured
1948          * hashkey
1949          */
1950         if (!rss_conf->rss_key)
1951                 goto rss_config;
1952
1953         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1954                 PMD_DRV_LOG(ERR,
1955                             "Invalid hashkey length, should be 16 bytes\n");
1956                 return -EINVAL;
1957         }
1958         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1959
1960 rss_config:
1961         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1962         return rc;
1963 }
1964
1965 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1966                                      struct rte_eth_rss_conf *rss_conf)
1967 {
1968         struct bnxt *bp = eth_dev->data->dev_private;
1969         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1970         int len, rc;
1971         uint32_t hash_types;
1972
1973         rc = is_bnxt_in_error(bp);
1974         if (rc)
1975                 return rc;
1976
1977         /* RSS configuration is the same for all VNICs */
1978         if (vnic && vnic->rss_hash_key) {
1979                 if (rss_conf->rss_key) {
1980                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1981                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1982                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1983                 }
1984
1985                 hash_types = vnic->hash_type;
1986                 rss_conf->rss_hf = 0;
1987                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1988                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1989                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1990                 }
1991                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1992                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1993                         hash_types &=
1994                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1995                 }
1996                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1997                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1998                         hash_types &=
1999                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2000                 }
2001                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2002                         rss_conf->rss_hf |= ETH_RSS_IPV6;
2003                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2004                 }
2005                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2006                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2007                         hash_types &=
2008                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2009                 }
2010                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2011                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2012                         hash_types &=
2013                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2014                 }
2015
2016                 rss_conf->rss_hf |=
2017                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2018
2019                 if (hash_types) {
2020                         PMD_DRV_LOG(ERR,
2021                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2022                                 vnic->hash_type);
2023                         return -ENOTSUP;
2024                 }
2025         } else {
2026                 rss_conf->rss_hf = 0;
2027         }
2028         return 0;
2029 }
2030
2031 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2032                                struct rte_eth_fc_conf *fc_conf)
2033 {
2034         struct bnxt *bp = dev->data->dev_private;
2035         struct rte_eth_link link_info;
2036         int rc;
2037
2038         rc = is_bnxt_in_error(bp);
2039         if (rc)
2040                 return rc;
2041
2042         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2043         if (rc)
2044                 return rc;
2045
2046         memset(fc_conf, 0, sizeof(*fc_conf));
2047         if (bp->link_info->auto_pause)
2048                 fc_conf->autoneg = 1;
2049         switch (bp->link_info->pause) {
2050         case 0:
2051                 fc_conf->mode = RTE_FC_NONE;
2052                 break;
2053         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2054                 fc_conf->mode = RTE_FC_TX_PAUSE;
2055                 break;
2056         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2057                 fc_conf->mode = RTE_FC_RX_PAUSE;
2058                 break;
2059         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2060                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2061                 fc_conf->mode = RTE_FC_FULL;
2062                 break;
2063         }
2064         return 0;
2065 }
2066
2067 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2068                                struct rte_eth_fc_conf *fc_conf)
2069 {
2070         struct bnxt *bp = dev->data->dev_private;
2071         int rc;
2072
2073         rc = is_bnxt_in_error(bp);
2074         if (rc)
2075                 return rc;
2076
2077         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2078                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2079                 return -ENOTSUP;
2080         }
2081
2082         switch (fc_conf->mode) {
2083         case RTE_FC_NONE:
2084                 bp->link_info->auto_pause = 0;
2085                 bp->link_info->force_pause = 0;
2086                 break;
2087         case RTE_FC_RX_PAUSE:
2088                 if (fc_conf->autoneg) {
2089                         bp->link_info->auto_pause =
2090                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2091                         bp->link_info->force_pause = 0;
2092                 } else {
2093                         bp->link_info->auto_pause = 0;
2094                         bp->link_info->force_pause =
2095                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2096                 }
2097                 break;
2098         case RTE_FC_TX_PAUSE:
2099                 if (fc_conf->autoneg) {
2100                         bp->link_info->auto_pause =
2101                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2102                         bp->link_info->force_pause = 0;
2103                 } else {
2104                         bp->link_info->auto_pause = 0;
2105                         bp->link_info->force_pause =
2106                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2107                 }
2108                 break;
2109         case RTE_FC_FULL:
2110                 if (fc_conf->autoneg) {
2111                         bp->link_info->auto_pause =
2112                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2113                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2114                         bp->link_info->force_pause = 0;
2115                 } else {
2116                         bp->link_info->auto_pause = 0;
2117                         bp->link_info->force_pause =
2118                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2119                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2120                 }
2121                 break;
2122         }
2123         return bnxt_set_hwrm_link_config(bp, true);
2124 }
2125
2126 /* Add UDP tunneling port */
2127 static int
2128 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2129                          struct rte_eth_udp_tunnel *udp_tunnel)
2130 {
2131         struct bnxt *bp = eth_dev->data->dev_private;
2132         uint16_t tunnel_type = 0;
2133         int rc = 0;
2134
2135         rc = is_bnxt_in_error(bp);
2136         if (rc)
2137                 return rc;
2138
2139         switch (udp_tunnel->prot_type) {
2140         case RTE_TUNNEL_TYPE_VXLAN:
2141                 if (bp->vxlan_port_cnt) {
2142                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2143                                 udp_tunnel->udp_port);
2144                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2145                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2146                                 return -ENOSPC;
2147                         }
2148                         bp->vxlan_port_cnt++;
2149                         return 0;
2150                 }
2151                 tunnel_type =
2152                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2153                 bp->vxlan_port_cnt++;
2154                 break;
2155         case RTE_TUNNEL_TYPE_GENEVE:
2156                 if (bp->geneve_port_cnt) {
2157                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2158                                 udp_tunnel->udp_port);
2159                         if (bp->geneve_port != udp_tunnel->udp_port) {
2160                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2161                                 return -ENOSPC;
2162                         }
2163                         bp->geneve_port_cnt++;
2164                         return 0;
2165                 }
2166                 tunnel_type =
2167                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2168                 bp->geneve_port_cnt++;
2169                 break;
2170         default:
2171                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2172                 return -ENOTSUP;
2173         }
2174         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2175                                              tunnel_type);
2176         return rc;
2177 }
2178
2179 static int
2180 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2181                          struct rte_eth_udp_tunnel *udp_tunnel)
2182 {
2183         struct bnxt *bp = eth_dev->data->dev_private;
2184         uint16_t tunnel_type = 0;
2185         uint16_t port = 0;
2186         int rc = 0;
2187
2188         rc = is_bnxt_in_error(bp);
2189         if (rc)
2190                 return rc;
2191
2192         switch (udp_tunnel->prot_type) {
2193         case RTE_TUNNEL_TYPE_VXLAN:
2194                 if (!bp->vxlan_port_cnt) {
2195                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2196                         return -EINVAL;
2197                 }
2198                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2199                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2200                                 udp_tunnel->udp_port, bp->vxlan_port);
2201                         return -EINVAL;
2202                 }
2203                 if (--bp->vxlan_port_cnt)
2204                         return 0;
2205
2206                 tunnel_type =
2207                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2208                 port = bp->vxlan_fw_dst_port_id;
2209                 break;
2210         case RTE_TUNNEL_TYPE_GENEVE:
2211                 if (!bp->geneve_port_cnt) {
2212                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2213                         return -EINVAL;
2214                 }
2215                 if (bp->geneve_port != udp_tunnel->udp_port) {
2216                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2217                                 udp_tunnel->udp_port, bp->geneve_port);
2218                         return -EINVAL;
2219                 }
2220                 if (--bp->geneve_port_cnt)
2221                         return 0;
2222
2223                 tunnel_type =
2224                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2225                 port = bp->geneve_fw_dst_port_id;
2226                 break;
2227         default:
2228                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2229                 return -ENOTSUP;
2230         }
2231
2232         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2233         return rc;
2234 }
2235
2236 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2237 {
2238         struct bnxt_filter_info *filter;
2239         struct bnxt_vnic_info *vnic;
2240         int rc = 0;
2241         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2242
2243         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2244         filter = STAILQ_FIRST(&vnic->filter);
2245         while (filter) {
2246                 /* Search for this matching MAC+VLAN filter */
2247                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2248                         /* Delete the filter */
2249                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2250                         if (rc)
2251                                 return rc;
2252                         STAILQ_REMOVE(&vnic->filter, filter,
2253                                       bnxt_filter_info, next);
2254                         bnxt_free_filter(bp, filter);
2255                         PMD_DRV_LOG(INFO,
2256                                     "Deleted vlan filter for %d\n",
2257                                     vlan_id);
2258                         return 0;
2259                 }
2260                 filter = STAILQ_NEXT(filter, next);
2261         }
2262         return -ENOENT;
2263 }
2264
2265 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2266 {
2267         struct bnxt_filter_info *filter;
2268         struct bnxt_vnic_info *vnic;
2269         int rc = 0;
2270         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2271                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2272         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2273
2274         /* Implementation notes on the use of VNIC in this command:
2275          *
2276          * By default, these filters belong to default vnic for the function.
2277          * Once these filters are set up, only destination VNIC can be modified.
2278          * If the destination VNIC is not specified in this command,
2279          * then the HWRM shall only create an l2 context id.
2280          */
2281
2282         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2283         filter = STAILQ_FIRST(&vnic->filter);
2284         /* Check if the VLAN has already been added */
2285         while (filter) {
2286                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2287                         return -EEXIST;
2288
2289                 filter = STAILQ_NEXT(filter, next);
2290         }
2291
2292         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2293          * command to create MAC+VLAN filter with the right flags, enables set.
2294          */
2295         filter = bnxt_alloc_filter(bp);
2296         if (!filter) {
2297                 PMD_DRV_LOG(ERR,
2298                             "MAC/VLAN filter alloc failed\n");
2299                 return -ENOMEM;
2300         }
2301         /* MAC + VLAN ID filter */
2302         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2303          * untagged packets are received
2304          *
2305          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2306          * packets and only the programmed vlan's packets are received
2307          */
2308         filter->l2_ivlan = vlan_id;
2309         filter->l2_ivlan_mask = 0x0FFF;
2310         filter->enables |= en;
2311         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2312
2313         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2314         if (rc) {
2315                 /* Free the newly allocated filter as we were
2316                  * not able to create the filter in hardware.
2317                  */
2318                 bnxt_free_filter(bp, filter);
2319                 return rc;
2320         }
2321
2322         filter->mac_index = 0;
2323         /* Add this new filter to the list */
2324         if (vlan_id == 0)
2325                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2326         else
2327                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2328
2329         PMD_DRV_LOG(INFO,
2330                     "Added Vlan filter for %d\n", vlan_id);
2331         return rc;
2332 }
2333
2334 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2335                 uint16_t vlan_id, int on)
2336 {
2337         struct bnxt *bp = eth_dev->data->dev_private;
2338         int rc;
2339
2340         rc = is_bnxt_in_error(bp);
2341         if (rc)
2342                 return rc;
2343
2344         if (!eth_dev->data->dev_started) {
2345                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2346                 return -EINVAL;
2347         }
2348
2349         /* These operations apply to ALL existing MAC/VLAN filters */
2350         if (on)
2351                 return bnxt_add_vlan_filter(bp, vlan_id);
2352         else
2353                 return bnxt_del_vlan_filter(bp, vlan_id);
2354 }
2355
2356 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2357                                     struct bnxt_vnic_info *vnic)
2358 {
2359         struct bnxt_filter_info *filter;
2360         int rc;
2361
2362         filter = STAILQ_FIRST(&vnic->filter);
2363         while (filter) {
2364                 if (filter->mac_index == 0 &&
2365                     !memcmp(filter->l2_addr, bp->mac_addr,
2366                             RTE_ETHER_ADDR_LEN)) {
2367                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2368                         if (!rc) {
2369                                 STAILQ_REMOVE(&vnic->filter, filter,
2370                                               bnxt_filter_info, next);
2371                                 bnxt_free_filter(bp, filter);
2372                         }
2373                         return rc;
2374                 }
2375                 filter = STAILQ_NEXT(filter, next);
2376         }
2377         return 0;
2378 }
2379
2380 static int
2381 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2382 {
2383         struct bnxt_vnic_info *vnic;
2384         unsigned int i;
2385         int rc;
2386
2387         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2388         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2389                 /* Remove any VLAN filters programmed */
2390                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2391                         bnxt_del_vlan_filter(bp, i);
2392
2393                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2394                 if (rc)
2395                         return rc;
2396         } else {
2397                 /* Default filter will allow packets that match the
2398                  * dest mac. So, it has to be deleted, otherwise, we
2399                  * will endup receiving vlan packets for which the
2400                  * filter is not programmed, when hw-vlan-filter
2401                  * configuration is ON
2402                  */
2403                 bnxt_del_dflt_mac_filter(bp, vnic);
2404                 /* This filter will allow only untagged packets */
2405                 bnxt_add_vlan_filter(bp, 0);
2406         }
2407         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2408                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2409
2410         return 0;
2411 }
2412
2413 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2414 {
2415         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2416         unsigned int i;
2417         int rc;
2418
2419         /* Destroy vnic filters and vnic */
2420         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2421             DEV_RX_OFFLOAD_VLAN_FILTER) {
2422                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2423                         bnxt_del_vlan_filter(bp, i);
2424         }
2425         bnxt_del_dflt_mac_filter(bp, vnic);
2426
2427         rc = bnxt_hwrm_vnic_free(bp, vnic);
2428         if (rc)
2429                 return rc;
2430
2431         rte_free(vnic->fw_grp_ids);
2432         vnic->fw_grp_ids = NULL;
2433
2434         vnic->rx_queue_cnt = 0;
2435
2436         return 0;
2437 }
2438
2439 static int
2440 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2441 {
2442         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2443         int rc;
2444
2445         /* Destroy, recreate and reconfigure the default vnic */
2446         rc = bnxt_free_one_vnic(bp, 0);
2447         if (rc)
2448                 return rc;
2449
2450         /* default vnic 0 */
2451         rc = bnxt_setup_one_vnic(bp, 0);
2452         if (rc)
2453                 return rc;
2454
2455         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2456             DEV_RX_OFFLOAD_VLAN_FILTER) {
2457                 rc = bnxt_add_vlan_filter(bp, 0);
2458                 if (rc)
2459                         return rc;
2460                 rc = bnxt_restore_vlan_filters(bp);
2461                 if (rc)
2462                         return rc;
2463         } else {
2464                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2465                 if (rc)
2466                         return rc;
2467         }
2468
2469         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2470         if (rc)
2471                 return rc;
2472
2473         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2474                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2475
2476         return rc;
2477 }
2478
2479 static int
2480 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2481 {
2482         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2483         struct bnxt *bp = dev->data->dev_private;
2484         int rc;
2485
2486         rc = is_bnxt_in_error(bp);
2487         if (rc)
2488                 return rc;
2489
2490         /* Filter settings will get applied when port is started */
2491         if (!dev->data->dev_started)
2492                 return 0;
2493
2494         if (mask & ETH_VLAN_FILTER_MASK) {
2495                 /* Enable or disable VLAN filtering */
2496                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2497                 if (rc)
2498                         return rc;
2499         }
2500
2501         if (mask & ETH_VLAN_STRIP_MASK) {
2502                 /* Enable or disable VLAN stripping */
2503                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2504                 if (rc)
2505                         return rc;
2506         }
2507
2508         if (mask & ETH_VLAN_EXTEND_MASK) {
2509                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2510                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2511                 else
2512                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2513         }
2514
2515         return 0;
2516 }
2517
2518 static int
2519 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2520                       uint16_t tpid)
2521 {
2522         struct bnxt *bp = dev->data->dev_private;
2523         int qinq = dev->data->dev_conf.rxmode.offloads &
2524                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2525
2526         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2527             vlan_type != ETH_VLAN_TYPE_OUTER) {
2528                 PMD_DRV_LOG(ERR,
2529                             "Unsupported vlan type.");
2530                 return -EINVAL;
2531         }
2532         if (!qinq) {
2533                 PMD_DRV_LOG(ERR,
2534                             "QinQ not enabled. Needs to be ON as we can "
2535                             "accelerate only outer vlan\n");
2536                 return -EINVAL;
2537         }
2538
2539         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2540                 switch (tpid) {
2541                 case RTE_ETHER_TYPE_QINQ:
2542                         bp->outer_tpid_bd =
2543                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2544                                 break;
2545                 case RTE_ETHER_TYPE_VLAN:
2546                         bp->outer_tpid_bd =
2547                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2548                                 break;
2549                 case RTE_ETHER_TYPE_QINQ1:
2550                         bp->outer_tpid_bd =
2551                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2552                                 break;
2553                 case RTE_ETHER_TYPE_QINQ2:
2554                         bp->outer_tpid_bd =
2555                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2556                                 break;
2557                 case RTE_ETHER_TYPE_QINQ3:
2558                         bp->outer_tpid_bd =
2559                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2560                                 break;
2561                 default:
2562                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2563                         return -EINVAL;
2564                 }
2565                 bp->outer_tpid_bd |= tpid;
2566                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2567         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2568                 PMD_DRV_LOG(ERR,
2569                             "Can accelerate only outer vlan in QinQ\n");
2570                 return -EINVAL;
2571         }
2572
2573         return 0;
2574 }
2575
2576 static int
2577 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2578                              struct rte_ether_addr *addr)
2579 {
2580         struct bnxt *bp = dev->data->dev_private;
2581         /* Default Filter is tied to VNIC 0 */
2582         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2583         int rc;
2584
2585         rc = is_bnxt_in_error(bp);
2586         if (rc)
2587                 return rc;
2588
2589         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2590                 return -EPERM;
2591
2592         if (rte_is_zero_ether_addr(addr))
2593                 return -EINVAL;
2594
2595         /* Filter settings will get applied when port is started */
2596         if (!dev->data->dev_started)
2597                 return 0;
2598
2599         /* Check if the requested MAC is already added */
2600         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2601                 return 0;
2602
2603         /* Destroy filter and re-create it */
2604         bnxt_del_dflt_mac_filter(bp, vnic);
2605
2606         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2607         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2608                 /* This filter will allow only untagged packets */
2609                 rc = bnxt_add_vlan_filter(bp, 0);
2610         } else {
2611                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2612         }
2613
2614         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2615         return rc;
2616 }
2617
2618 static int
2619 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2620                           struct rte_ether_addr *mc_addr_set,
2621                           uint32_t nb_mc_addr)
2622 {
2623         struct bnxt *bp = eth_dev->data->dev_private;
2624         char *mc_addr_list = (char *)mc_addr_set;
2625         struct bnxt_vnic_info *vnic;
2626         uint32_t off = 0, i = 0;
2627         int rc;
2628
2629         rc = is_bnxt_in_error(bp);
2630         if (rc)
2631                 return rc;
2632
2633         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2634
2635         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2636                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2637                 goto allmulti;
2638         }
2639
2640         /* TODO Check for Duplicate mcast addresses */
2641         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2642         for (i = 0; i < nb_mc_addr; i++) {
2643                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2644                         RTE_ETHER_ADDR_LEN);
2645                 off += RTE_ETHER_ADDR_LEN;
2646         }
2647
2648         vnic->mc_addr_cnt = i;
2649         if (vnic->mc_addr_cnt)
2650                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2651         else
2652                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2653
2654 allmulti:
2655         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2656 }
2657
2658 static int
2659 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2660 {
2661         struct bnxt *bp = dev->data->dev_private;
2662         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2663         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2664         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2665         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2666         int ret;
2667
2668         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2669                         fw_major, fw_minor, fw_updt, fw_rsvd);
2670
2671         ret += 1; /* add the size of '\0' */
2672         if (fw_size < (uint32_t)ret)
2673                 return ret;
2674         else
2675                 return 0;
2676 }
2677
2678 static void
2679 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2680         struct rte_eth_rxq_info *qinfo)
2681 {
2682         struct bnxt *bp = dev->data->dev_private;
2683         struct bnxt_rx_queue *rxq;
2684
2685         if (is_bnxt_in_error(bp))
2686                 return;
2687
2688         rxq = dev->data->rx_queues[queue_id];
2689
2690         qinfo->mp = rxq->mb_pool;
2691         qinfo->scattered_rx = dev->data->scattered_rx;
2692         qinfo->nb_desc = rxq->nb_rx_desc;
2693
2694         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2695         qinfo->conf.rx_drop_en = rxq->drop_en;
2696         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2697         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2698 }
2699
2700 static void
2701 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2702         struct rte_eth_txq_info *qinfo)
2703 {
2704         struct bnxt *bp = dev->data->dev_private;
2705         struct bnxt_tx_queue *txq;
2706
2707         if (is_bnxt_in_error(bp))
2708                 return;
2709
2710         txq = dev->data->tx_queues[queue_id];
2711
2712         qinfo->nb_desc = txq->nb_tx_desc;
2713
2714         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2715         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2716         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2717
2718         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2719         qinfo->conf.tx_rs_thresh = 0;
2720         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2721         qinfo->conf.offloads = txq->offloads;
2722 }
2723
2724 static const struct {
2725         eth_rx_burst_t pkt_burst;
2726         const char *info;
2727 } bnxt_rx_burst_info[] = {
2728         {bnxt_recv_pkts,        "Scalar"},
2729 #if defined(RTE_ARCH_X86)
2730         {bnxt_recv_pkts_vec,    "Vector SSE"},
2731 #elif defined(RTE_ARCH_ARM64)
2732         {bnxt_recv_pkts_vec,    "Vector Neon"},
2733 #endif
2734 };
2735
2736 static int
2737 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2738                        struct rte_eth_burst_mode *mode)
2739 {
2740         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2741         size_t i;
2742
2743         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2744                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2745                         snprintf(mode->info, sizeof(mode->info), "%s",
2746                                  bnxt_rx_burst_info[i].info);
2747                         return 0;
2748                 }
2749         }
2750
2751         return -EINVAL;
2752 }
2753
2754 static const struct {
2755         eth_tx_burst_t pkt_burst;
2756         const char *info;
2757 } bnxt_tx_burst_info[] = {
2758         {bnxt_xmit_pkts,        "Scalar"},
2759 #if defined(RTE_ARCH_X86)
2760         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2761 #elif defined(RTE_ARCH_ARM64)
2762         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2763 #endif
2764 };
2765
2766 static int
2767 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2768                        struct rte_eth_burst_mode *mode)
2769 {
2770         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2771         size_t i;
2772
2773         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2774                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2775                         snprintf(mode->info, sizeof(mode->info), "%s",
2776                                  bnxt_tx_burst_info[i].info);
2777                         return 0;
2778                 }
2779         }
2780
2781         return -EINVAL;
2782 }
2783
2784 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2785 {
2786         struct bnxt *bp = eth_dev->data->dev_private;
2787         uint32_t new_pkt_size;
2788         uint32_t rc = 0;
2789         uint32_t i;
2790
2791         rc = is_bnxt_in_error(bp);
2792         if (rc)
2793                 return rc;
2794
2795         /* Exit if receive queues are not configured yet */
2796         if (!eth_dev->data->nb_rx_queues)
2797                 return rc;
2798
2799         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2800                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2801
2802         /*
2803          * Disallow any MTU change that would require scattered receive support
2804          * if it is not already enabled.
2805          */
2806         if (eth_dev->data->dev_started &&
2807             !eth_dev->data->scattered_rx &&
2808             (new_pkt_size >
2809              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2810                 PMD_DRV_LOG(ERR,
2811                             "MTU change would require scattered rx support. ");
2812                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2813                 return -EINVAL;
2814         }
2815
2816         if (new_mtu > RTE_ETHER_MTU) {
2817                 bp->flags |= BNXT_FLAG_JUMBO;
2818                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2819                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2820         } else {
2821                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2822                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2823                 bp->flags &= ~BNXT_FLAG_JUMBO;
2824         }
2825
2826         /* Is there a change in mtu setting? */
2827         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2828                 return rc;
2829
2830         for (i = 0; i < bp->nr_vnics; i++) {
2831                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2832                 uint16_t size = 0;
2833
2834                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2835                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2836                 if (rc)
2837                         break;
2838
2839                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2840                 size -= RTE_PKTMBUF_HEADROOM;
2841
2842                 if (size < new_mtu) {
2843                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2844                         if (rc)
2845                                 return rc;
2846                 }
2847         }
2848
2849         if (!rc)
2850                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2851
2852         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2853
2854         return rc;
2855 }
2856
2857 static int
2858 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2859 {
2860         struct bnxt *bp = dev->data->dev_private;
2861         uint16_t vlan = bp->vlan;
2862         int rc;
2863
2864         rc = is_bnxt_in_error(bp);
2865         if (rc)
2866                 return rc;
2867
2868         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2869                 PMD_DRV_LOG(ERR,
2870                         "PVID cannot be modified for this function\n");
2871                 return -ENOTSUP;
2872         }
2873         bp->vlan = on ? pvid : 0;
2874
2875         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2876         if (rc)
2877                 bp->vlan = vlan;
2878         return rc;
2879 }
2880
2881 static int
2882 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2883 {
2884         struct bnxt *bp = dev->data->dev_private;
2885         int rc;
2886
2887         rc = is_bnxt_in_error(bp);
2888         if (rc)
2889                 return rc;
2890
2891         return bnxt_hwrm_port_led_cfg(bp, true);
2892 }
2893
2894 static int
2895 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2896 {
2897         struct bnxt *bp = dev->data->dev_private;
2898         int rc;
2899
2900         rc = is_bnxt_in_error(bp);
2901         if (rc)
2902                 return rc;
2903
2904         return bnxt_hwrm_port_led_cfg(bp, false);
2905 }
2906
2907 static uint32_t
2908 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2909 {
2910         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2911         uint32_t desc = 0, raw_cons = 0, cons;
2912         struct bnxt_cp_ring_info *cpr;
2913         struct bnxt_rx_queue *rxq;
2914         struct rx_pkt_cmpl *rxcmp;
2915         int rc;
2916
2917         rc = is_bnxt_in_error(bp);
2918         if (rc)
2919                 return rc;
2920
2921         rxq = dev->data->rx_queues[rx_queue_id];
2922         cpr = rxq->cp_ring;
2923         raw_cons = cpr->cp_raw_cons;
2924
2925         while (1) {
2926                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2927                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2928                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2929
2930                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2931                         break;
2932                 } else {
2933                         raw_cons++;
2934                         desc++;
2935                 }
2936         }
2937
2938         return desc;
2939 }
2940
2941 static int
2942 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2943 {
2944         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2945         struct bnxt_rx_ring_info *rxr;
2946         struct bnxt_cp_ring_info *cpr;
2947         struct rte_mbuf *rx_buf;
2948         struct rx_pkt_cmpl *rxcmp;
2949         uint32_t cons, cp_cons;
2950         int rc;
2951
2952         if (!rxq)
2953                 return -EINVAL;
2954
2955         rc = is_bnxt_in_error(rxq->bp);
2956         if (rc)
2957                 return rc;
2958
2959         cpr = rxq->cp_ring;
2960         rxr = rxq->rx_ring;
2961
2962         if (offset >= rxq->nb_rx_desc)
2963                 return -EINVAL;
2964
2965         cons = RING_CMP(cpr->cp_ring_struct, offset);
2966         cp_cons = cpr->cp_raw_cons;
2967         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2968
2969         if (cons > cp_cons) {
2970                 if (CMPL_VALID(rxcmp, cpr->valid))
2971                         return RTE_ETH_RX_DESC_DONE;
2972         } else {
2973                 if (CMPL_VALID(rxcmp, !cpr->valid))
2974                         return RTE_ETH_RX_DESC_DONE;
2975         }
2976         rx_buf = rxr->rx_buf_ring[cons];
2977         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2978                 return RTE_ETH_RX_DESC_UNAVAIL;
2979
2980
2981         return RTE_ETH_RX_DESC_AVAIL;
2982 }
2983
2984 static int
2985 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2986 {
2987         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2988         struct bnxt_tx_ring_info *txr;
2989         struct bnxt_cp_ring_info *cpr;
2990         struct bnxt_sw_tx_bd *tx_buf;
2991         struct tx_pkt_cmpl *txcmp;
2992         uint32_t cons, cp_cons;
2993         int rc;
2994
2995         if (!txq)
2996                 return -EINVAL;
2997
2998         rc = is_bnxt_in_error(txq->bp);
2999         if (rc)
3000                 return rc;
3001
3002         cpr = txq->cp_ring;
3003         txr = txq->tx_ring;
3004
3005         if (offset >= txq->nb_tx_desc)
3006                 return -EINVAL;
3007
3008         cons = RING_CMP(cpr->cp_ring_struct, offset);
3009         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3010         cp_cons = cpr->cp_raw_cons;
3011
3012         if (cons > cp_cons) {
3013                 if (CMPL_VALID(txcmp, cpr->valid))
3014                         return RTE_ETH_TX_DESC_UNAVAIL;
3015         } else {
3016                 if (CMPL_VALID(txcmp, !cpr->valid))
3017                         return RTE_ETH_TX_DESC_UNAVAIL;
3018         }
3019         tx_buf = &txr->tx_buf_ring[cons];
3020         if (tx_buf->mbuf == NULL)
3021                 return RTE_ETH_TX_DESC_DONE;
3022
3023         return RTE_ETH_TX_DESC_FULL;
3024 }
3025
3026 int
3027 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3028                     enum rte_filter_type filter_type,
3029                     enum rte_filter_op filter_op, void *arg)
3030 {
3031         struct bnxt *bp = dev->data->dev_private;
3032         int ret = 0;
3033
3034         if (!bp)
3035                 return -EIO;
3036
3037         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3038                 struct bnxt_representor *vfr = dev->data->dev_private;
3039                 bp = vfr->parent_dev->data->dev_private;
3040                 /* parent is deleted while children are still valid */
3041                 if (!bp) {
3042                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3043                                     dev->data->port_id,
3044                                     filter_type,
3045                                     filter_op);
3046                         return -EIO;
3047                 }
3048         }
3049
3050         ret = is_bnxt_in_error(bp);
3051         if (ret)
3052                 return ret;
3053
3054         switch (filter_type) {
3055         case RTE_ETH_FILTER_GENERIC:
3056                 if (filter_op != RTE_ETH_FILTER_GET)
3057                         return -EINVAL;
3058
3059                 /* PMD supports thread-safe flow operations.  rte_flow API
3060                  * functions can avoid mutex for multi-thread safety.
3061                  */
3062                 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3063
3064                 if (BNXT_TRUFLOW_EN(bp))
3065                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3066                 else
3067                         *(const void **)arg = &bnxt_flow_ops;
3068                 break;
3069         default:
3070                 PMD_DRV_LOG(ERR,
3071                         "Filter type (%d) not supported", filter_type);
3072                 ret = -EINVAL;
3073                 break;
3074         }
3075         return ret;
3076 }
3077
3078 static const uint32_t *
3079 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3080 {
3081         static const uint32_t ptypes[] = {
3082                 RTE_PTYPE_L2_ETHER_VLAN,
3083                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3084                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3085                 RTE_PTYPE_L4_ICMP,
3086                 RTE_PTYPE_L4_TCP,
3087                 RTE_PTYPE_L4_UDP,
3088                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3089                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3090                 RTE_PTYPE_INNER_L4_ICMP,
3091                 RTE_PTYPE_INNER_L4_TCP,
3092                 RTE_PTYPE_INNER_L4_UDP,
3093                 RTE_PTYPE_UNKNOWN
3094         };
3095
3096         if (!dev->rx_pkt_burst)
3097                 return NULL;
3098
3099         return ptypes;
3100 }
3101
3102 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3103                          int reg_win)
3104 {
3105         uint32_t reg_base = *reg_arr & 0xfffff000;
3106         uint32_t win_off;
3107         int i;
3108
3109         for (i = 0; i < count; i++) {
3110                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3111                         return -ERANGE;
3112         }
3113         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3114         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3115         return 0;
3116 }
3117
3118 static int bnxt_map_ptp_regs(struct bnxt *bp)
3119 {
3120         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3121         uint32_t *reg_arr;
3122         int rc, i;
3123
3124         reg_arr = ptp->rx_regs;
3125         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3126         if (rc)
3127                 return rc;
3128
3129         reg_arr = ptp->tx_regs;
3130         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3131         if (rc)
3132                 return rc;
3133
3134         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3135                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3136
3137         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3138                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3139
3140         return 0;
3141 }
3142
3143 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3144 {
3145         rte_write32(0, (uint8_t *)bp->bar0 +
3146                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3147         rte_write32(0, (uint8_t *)bp->bar0 +
3148                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3149 }
3150
3151 static uint64_t bnxt_cc_read(struct bnxt *bp)
3152 {
3153         uint64_t ns;
3154
3155         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3156                               BNXT_GRCPF_REG_SYNC_TIME));
3157         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3158                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3159         return ns;
3160 }
3161
3162 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3163 {
3164         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3165         uint32_t fifo;
3166
3167         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3168                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3169         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3170                 return -EAGAIN;
3171
3172         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3173                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3174         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3175                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3176         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3177                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3178
3179         return 0;
3180 }
3181
3182 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3183 {
3184         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3185         struct bnxt_pf_info *pf = bp->pf;
3186         uint16_t port_id;
3187         uint32_t fifo;
3188
3189         if (!ptp)
3190                 return -ENODEV;
3191
3192         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3193                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3194         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3195                 return -EAGAIN;
3196
3197         port_id = pf->port_id;
3198         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3199                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3200
3201         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3202                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3203         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3204 /*              bnxt_clr_rx_ts(bp);       TBD  */
3205                 return -EBUSY;
3206         }
3207
3208         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3209                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3210         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3211                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3212
3213         return 0;
3214 }
3215
3216 static int
3217 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3218 {
3219         uint64_t ns;
3220         struct bnxt *bp = dev->data->dev_private;
3221         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3222
3223         if (!ptp)
3224                 return 0;
3225
3226         ns = rte_timespec_to_ns(ts);
3227         /* Set the timecounters to a new value. */
3228         ptp->tc.nsec = ns;
3229
3230         return 0;
3231 }
3232
3233 static int
3234 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3235 {
3236         struct bnxt *bp = dev->data->dev_private;
3237         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3238         uint64_t ns, systime_cycles = 0;
3239         int rc = 0;
3240
3241         if (!ptp)
3242                 return 0;
3243
3244         if (BNXT_CHIP_P5(bp))
3245                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3246                                              &systime_cycles);
3247         else
3248                 systime_cycles = bnxt_cc_read(bp);
3249
3250         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3251         *ts = rte_ns_to_timespec(ns);
3252
3253         return rc;
3254 }
3255 static int
3256 bnxt_timesync_enable(struct rte_eth_dev *dev)
3257 {
3258         struct bnxt *bp = dev->data->dev_private;
3259         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3260         uint32_t shift = 0;
3261         int rc;
3262
3263         if (!ptp)
3264                 return 0;
3265
3266         ptp->rx_filter = 1;
3267         ptp->tx_tstamp_en = 1;
3268         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3269
3270         rc = bnxt_hwrm_ptp_cfg(bp);
3271         if (rc)
3272                 return rc;
3273
3274         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3275         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3276         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3277
3278         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3279         ptp->tc.cc_shift = shift;
3280         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3281
3282         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3283         ptp->rx_tstamp_tc.cc_shift = shift;
3284         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3285
3286         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3287         ptp->tx_tstamp_tc.cc_shift = shift;
3288         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3289
3290         if (!BNXT_CHIP_P5(bp))
3291                 bnxt_map_ptp_regs(bp);
3292
3293         return 0;
3294 }
3295
3296 static int
3297 bnxt_timesync_disable(struct rte_eth_dev *dev)
3298 {
3299         struct bnxt *bp = dev->data->dev_private;
3300         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3301
3302         if (!ptp)
3303                 return 0;
3304
3305         ptp->rx_filter = 0;
3306         ptp->tx_tstamp_en = 0;
3307         ptp->rxctl = 0;
3308
3309         bnxt_hwrm_ptp_cfg(bp);
3310
3311         if (!BNXT_CHIP_P5(bp))
3312                 bnxt_unmap_ptp_regs(bp);
3313
3314         return 0;
3315 }
3316
3317 static int
3318 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3319                                  struct timespec *timestamp,
3320                                  uint32_t flags __rte_unused)
3321 {
3322         struct bnxt *bp = dev->data->dev_private;
3323         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3324         uint64_t rx_tstamp_cycles = 0;
3325         uint64_t ns;
3326
3327         if (!ptp)
3328                 return 0;
3329
3330         if (BNXT_CHIP_P5(bp))
3331                 rx_tstamp_cycles = ptp->rx_timestamp;
3332         else
3333                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3334
3335         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3336         *timestamp = rte_ns_to_timespec(ns);
3337         return  0;
3338 }
3339
3340 static int
3341 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3342                                  struct timespec *timestamp)
3343 {
3344         struct bnxt *bp = dev->data->dev_private;
3345         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3346         uint64_t tx_tstamp_cycles = 0;
3347         uint64_t ns;
3348         int rc = 0;
3349
3350         if (!ptp)
3351                 return 0;
3352
3353         if (BNXT_CHIP_P5(bp))
3354                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3355                                              &tx_tstamp_cycles);
3356         else
3357                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3358
3359         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3360         *timestamp = rte_ns_to_timespec(ns);
3361
3362         return rc;
3363 }
3364
3365 static int
3366 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3367 {
3368         struct bnxt *bp = dev->data->dev_private;
3369         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3370
3371         if (!ptp)
3372                 return 0;
3373
3374         ptp->tc.nsec += delta;
3375
3376         return 0;
3377 }
3378
3379 static int
3380 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3381 {
3382         struct bnxt *bp = dev->data->dev_private;
3383         int rc;
3384         uint32_t dir_entries;
3385         uint32_t entry_length;
3386
3387         rc = is_bnxt_in_error(bp);
3388         if (rc)
3389                 return rc;
3390
3391         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3392                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3393                     bp->pdev->addr.devid, bp->pdev->addr.function);
3394
3395         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3396         if (rc != 0)
3397                 return rc;
3398
3399         return dir_entries * entry_length;
3400 }
3401
3402 static int
3403 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3404                 struct rte_dev_eeprom_info *in_eeprom)
3405 {
3406         struct bnxt *bp = dev->data->dev_private;
3407         uint32_t index;
3408         uint32_t offset;
3409         int rc;
3410
3411         rc = is_bnxt_in_error(bp);
3412         if (rc)
3413                 return rc;
3414
3415         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3416                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3417                     bp->pdev->addr.devid, bp->pdev->addr.function,
3418                     in_eeprom->offset, in_eeprom->length);
3419
3420         if (in_eeprom->offset == 0) /* special offset value to get directory */
3421                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3422                                                 in_eeprom->data);
3423
3424         index = in_eeprom->offset >> 24;
3425         offset = in_eeprom->offset & 0xffffff;
3426
3427         if (index != 0)
3428                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3429                                            in_eeprom->length, in_eeprom->data);
3430
3431         return 0;
3432 }
3433
3434 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3435 {
3436         switch (dir_type) {
3437         case BNX_DIR_TYPE_CHIMP_PATCH:
3438         case BNX_DIR_TYPE_BOOTCODE:
3439         case BNX_DIR_TYPE_BOOTCODE_2:
3440         case BNX_DIR_TYPE_APE_FW:
3441         case BNX_DIR_TYPE_APE_PATCH:
3442         case BNX_DIR_TYPE_KONG_FW:
3443         case BNX_DIR_TYPE_KONG_PATCH:
3444         case BNX_DIR_TYPE_BONO_FW:
3445         case BNX_DIR_TYPE_BONO_PATCH:
3446                 /* FALLTHROUGH */
3447                 return true;
3448         }
3449
3450         return false;
3451 }
3452
3453 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3454 {
3455         switch (dir_type) {
3456         case BNX_DIR_TYPE_AVS:
3457         case BNX_DIR_TYPE_EXP_ROM_MBA:
3458         case BNX_DIR_TYPE_PCIE:
3459         case BNX_DIR_TYPE_TSCF_UCODE:
3460         case BNX_DIR_TYPE_EXT_PHY:
3461         case BNX_DIR_TYPE_CCM:
3462         case BNX_DIR_TYPE_ISCSI_BOOT:
3463         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3464         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3465                 /* FALLTHROUGH */
3466                 return true;
3467         }
3468
3469         return false;
3470 }
3471
3472 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3473 {
3474         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3475                 bnxt_dir_type_is_other_exec_format(dir_type);
3476 }
3477
3478 static int
3479 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3480                 struct rte_dev_eeprom_info *in_eeprom)
3481 {
3482         struct bnxt *bp = dev->data->dev_private;
3483         uint8_t index, dir_op;
3484         uint16_t type, ext, ordinal, attr;
3485         int rc;
3486
3487         rc = is_bnxt_in_error(bp);
3488         if (rc)
3489                 return rc;
3490
3491         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3492                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3493                     bp->pdev->addr.devid, bp->pdev->addr.function,
3494                     in_eeprom->offset, in_eeprom->length);
3495
3496         if (!BNXT_PF(bp)) {
3497                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3498                 return -EINVAL;
3499         }
3500
3501         type = in_eeprom->magic >> 16;
3502
3503         if (type == 0xffff) { /* special value for directory operations */
3504                 index = in_eeprom->magic & 0xff;
3505                 dir_op = in_eeprom->magic >> 8;
3506                 if (index == 0)
3507                         return -EINVAL;
3508                 switch (dir_op) {
3509                 case 0x0e: /* erase */
3510                         if (in_eeprom->offset != ~in_eeprom->magic)
3511                                 return -EINVAL;
3512                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3513                 default:
3514                         return -EINVAL;
3515                 }
3516         }
3517
3518         /* Create or re-write an NVM item: */
3519         if (bnxt_dir_type_is_executable(type) == true)
3520                 return -EOPNOTSUPP;
3521         ext = in_eeprom->magic & 0xffff;
3522         ordinal = in_eeprom->offset >> 16;
3523         attr = in_eeprom->offset & 0xffff;
3524
3525         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3526                                      in_eeprom->data, in_eeprom->length);
3527 }
3528
3529 /*
3530  * Initialization
3531  */
3532
3533 static const struct eth_dev_ops bnxt_dev_ops = {
3534         .dev_infos_get = bnxt_dev_info_get_op,
3535         .dev_close = bnxt_dev_close_op,
3536         .dev_configure = bnxt_dev_configure_op,
3537         .dev_start = bnxt_dev_start_op,
3538         .dev_stop = bnxt_dev_stop_op,
3539         .dev_set_link_up = bnxt_dev_set_link_up_op,
3540         .dev_set_link_down = bnxt_dev_set_link_down_op,
3541         .stats_get = bnxt_stats_get_op,
3542         .stats_reset = bnxt_stats_reset_op,
3543         .rx_queue_setup = bnxt_rx_queue_setup_op,
3544         .rx_queue_release = bnxt_rx_queue_release_op,
3545         .tx_queue_setup = bnxt_tx_queue_setup_op,
3546         .tx_queue_release = bnxt_tx_queue_release_op,
3547         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3548         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3549         .reta_update = bnxt_reta_update_op,
3550         .reta_query = bnxt_reta_query_op,
3551         .rss_hash_update = bnxt_rss_hash_update_op,
3552         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3553         .link_update = bnxt_link_update_op,
3554         .promiscuous_enable = bnxt_promiscuous_enable_op,
3555         .promiscuous_disable = bnxt_promiscuous_disable_op,
3556         .allmulticast_enable = bnxt_allmulticast_enable_op,
3557         .allmulticast_disable = bnxt_allmulticast_disable_op,
3558         .mac_addr_add = bnxt_mac_addr_add_op,
3559         .mac_addr_remove = bnxt_mac_addr_remove_op,
3560         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3561         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3562         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3563         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3564         .vlan_filter_set = bnxt_vlan_filter_set_op,
3565         .vlan_offload_set = bnxt_vlan_offload_set_op,
3566         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3567         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3568         .mtu_set = bnxt_mtu_set_op,
3569         .mac_addr_set = bnxt_set_default_mac_addr_op,
3570         .xstats_get = bnxt_dev_xstats_get_op,
3571         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3572         .xstats_reset = bnxt_dev_xstats_reset_op,
3573         .fw_version_get = bnxt_fw_version_get,
3574         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3575         .rxq_info_get = bnxt_rxq_info_get_op,
3576         .txq_info_get = bnxt_txq_info_get_op,
3577         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3578         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3579         .dev_led_on = bnxt_dev_led_on_op,
3580         .dev_led_off = bnxt_dev_led_off_op,
3581         .rx_queue_start = bnxt_rx_queue_start,
3582         .rx_queue_stop = bnxt_rx_queue_stop,
3583         .tx_queue_start = bnxt_tx_queue_start,
3584         .tx_queue_stop = bnxt_tx_queue_stop,
3585         .filter_ctrl = bnxt_filter_ctrl_op,
3586         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3587         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3588         .get_eeprom           = bnxt_get_eeprom_op,
3589         .set_eeprom           = bnxt_set_eeprom_op,
3590         .timesync_enable      = bnxt_timesync_enable,
3591         .timesync_disable     = bnxt_timesync_disable,
3592         .timesync_read_time   = bnxt_timesync_read_time,
3593         .timesync_write_time   = bnxt_timesync_write_time,
3594         .timesync_adjust_time = bnxt_timesync_adjust_time,
3595         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3596         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3597 };
3598
3599 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3600 {
3601         uint32_t offset;
3602
3603         /* Only pre-map the reset GRC registers using window 3 */
3604         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3605                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3606
3607         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3608
3609         return offset;
3610 }
3611
3612 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3613 {
3614         struct bnxt_error_recovery_info *info = bp->recovery_info;
3615         uint32_t reg_base = 0xffffffff;
3616         int i;
3617
3618         /* Only pre-map the monitoring GRC registers using window 2 */
3619         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3620                 uint32_t reg = info->status_regs[i];
3621
3622                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3623                         continue;
3624
3625                 if (reg_base == 0xffffffff)
3626                         reg_base = reg & 0xfffff000;
3627                 if ((reg & 0xfffff000) != reg_base)
3628                         return -ERANGE;
3629
3630                 /* Use mask 0xffc as the Lower 2 bits indicates
3631                  * address space location
3632                  */
3633                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3634                                                 (reg & 0xffc);
3635         }
3636
3637         if (reg_base == 0xffffffff)
3638                 return 0;
3639
3640         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3641                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3642
3643         return 0;
3644 }
3645
3646 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3647 {
3648         struct bnxt_error_recovery_info *info = bp->recovery_info;
3649         uint32_t delay = info->delay_after_reset[index];
3650         uint32_t val = info->reset_reg_val[index];
3651         uint32_t reg = info->reset_reg[index];
3652         uint32_t type, offset;
3653
3654         type = BNXT_FW_STATUS_REG_TYPE(reg);
3655         offset = BNXT_FW_STATUS_REG_OFF(reg);
3656
3657         switch (type) {
3658         case BNXT_FW_STATUS_REG_TYPE_CFG:
3659                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3660                 break;
3661         case BNXT_FW_STATUS_REG_TYPE_GRC:
3662                 offset = bnxt_map_reset_regs(bp, offset);
3663                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3664                 break;
3665         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3666                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3667                 break;
3668         }
3669         /* wait on a specific interval of time until core reset is complete */
3670         if (delay)
3671                 rte_delay_ms(delay);
3672 }
3673
3674 static void bnxt_dev_cleanup(struct bnxt *bp)
3675 {
3676         bp->eth_dev->data->dev_link.link_status = 0;
3677         bp->link_info->link_up = 0;
3678         if (bp->eth_dev->data->dev_started)
3679                 bnxt_dev_stop_op(bp->eth_dev);
3680
3681         bnxt_uninit_resources(bp, true);
3682 }
3683
3684 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3685 {
3686         struct rte_eth_dev *dev = bp->eth_dev;
3687         struct rte_vlan_filter_conf *vfc;
3688         int vidx, vbit, rc;
3689         uint16_t vlan_id;
3690
3691         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3692                 vfc = &dev->data->vlan_filter_conf;
3693                 vidx = vlan_id / 64;
3694                 vbit = vlan_id % 64;
3695
3696                 /* Each bit corresponds to a VLAN id */
3697                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3698                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3699                         if (rc)
3700                                 return rc;
3701                 }
3702         }
3703
3704         return 0;
3705 }
3706
3707 static int bnxt_restore_mac_filters(struct bnxt *bp)
3708 {
3709         struct rte_eth_dev *dev = bp->eth_dev;
3710         struct rte_eth_dev_info dev_info;
3711         struct rte_ether_addr *addr;
3712         uint64_t pool_mask;
3713         uint32_t pool = 0;
3714         uint16_t i;
3715         int rc;
3716
3717         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3718                 return 0;
3719
3720         rc = bnxt_dev_info_get_op(dev, &dev_info);
3721         if (rc)
3722                 return rc;
3723
3724         /* replay MAC address configuration */
3725         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3726                 addr = &dev->data->mac_addrs[i];
3727
3728                 /* skip zero address */
3729                 if (rte_is_zero_ether_addr(addr))
3730                         continue;
3731
3732                 pool = 0;
3733                 pool_mask = dev->data->mac_pool_sel[i];
3734
3735                 do {
3736                         if (pool_mask & 1ULL) {
3737                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3738                                 if (rc)
3739                                         return rc;
3740                         }
3741                         pool_mask >>= 1;
3742                         pool++;
3743                 } while (pool_mask);
3744         }
3745
3746         return 0;
3747 }
3748
3749 static int bnxt_restore_filters(struct bnxt *bp)
3750 {
3751         struct rte_eth_dev *dev = bp->eth_dev;
3752         int ret = 0;
3753
3754         if (dev->data->all_multicast) {
3755                 ret = bnxt_allmulticast_enable_op(dev);
3756                 if (ret)
3757                         return ret;
3758         }
3759         if (dev->data->promiscuous) {
3760                 ret = bnxt_promiscuous_enable_op(dev);
3761                 if (ret)
3762                         return ret;
3763         }
3764
3765         ret = bnxt_restore_mac_filters(bp);
3766         if (ret)
3767                 return ret;
3768
3769         ret = bnxt_restore_vlan_filters(bp);
3770         /* TODO restore other filters as well */
3771         return ret;
3772 }
3773
3774 static void bnxt_dev_recover(void *arg)
3775 {
3776         struct bnxt *bp = arg;
3777         int timeout = bp->fw_reset_max_msecs;
3778         int rc = 0;
3779
3780         /* Clear Error flag so that device re-init should happen */
3781         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3782
3783         do {
3784                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
3785                 if (rc == 0)
3786                         break;
3787                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3788                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3789         } while (rc && timeout);
3790
3791         if (rc) {
3792                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3793                 goto err;
3794         }
3795
3796         rc = bnxt_init_resources(bp, true);
3797         if (rc) {
3798                 PMD_DRV_LOG(ERR,
3799                             "Failed to initialize resources after reset\n");
3800                 goto err;
3801         }
3802         /* clear reset flag as the device is initialized now */
3803         bp->flags &= ~BNXT_FLAG_FW_RESET;
3804
3805         rc = bnxt_dev_start_op(bp->eth_dev);
3806         if (rc) {
3807                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3808                 goto err_start;
3809         }
3810
3811         rc = bnxt_restore_filters(bp);
3812         if (rc)
3813                 goto err_start;
3814
3815         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3816         return;
3817 err_start:
3818         bnxt_dev_stop_op(bp->eth_dev);
3819 err:
3820         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3821         bnxt_uninit_resources(bp, false);
3822         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3823 }
3824
3825 void bnxt_dev_reset_and_resume(void *arg)
3826 {
3827         struct bnxt *bp = arg;
3828         int rc;
3829
3830         bnxt_dev_cleanup(bp);
3831
3832         bnxt_wait_for_device_shutdown(bp);
3833
3834         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3835                                bnxt_dev_recover, (void *)bp);
3836         if (rc)
3837                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3838 }
3839
3840 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3841 {
3842         struct bnxt_error_recovery_info *info = bp->recovery_info;
3843         uint32_t reg = info->status_regs[index];
3844         uint32_t type, offset, val = 0;
3845
3846         type = BNXT_FW_STATUS_REG_TYPE(reg);
3847         offset = BNXT_FW_STATUS_REG_OFF(reg);
3848
3849         switch (type) {
3850         case BNXT_FW_STATUS_REG_TYPE_CFG:
3851                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3852                 break;
3853         case BNXT_FW_STATUS_REG_TYPE_GRC:
3854                 offset = info->mapped_status_regs[index];
3855                 /* FALLTHROUGH */
3856         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3857                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3858                                        offset));
3859                 break;
3860         }
3861
3862         return val;
3863 }
3864
3865 static int bnxt_fw_reset_all(struct bnxt *bp)
3866 {
3867         struct bnxt_error_recovery_info *info = bp->recovery_info;
3868         uint32_t i;
3869         int rc = 0;
3870
3871         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3872                 /* Reset through master function driver */
3873                 for (i = 0; i < info->reg_array_cnt; i++)
3874                         bnxt_write_fw_reset_reg(bp, i);
3875                 /* Wait for time specified by FW after triggering reset */
3876                 rte_delay_ms(info->master_func_wait_period_after_reset);
3877         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3878                 /* Reset with the help of Kong processor */
3879                 rc = bnxt_hwrm_fw_reset(bp);
3880                 if (rc)
3881                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3882         }
3883
3884         return rc;
3885 }
3886
3887 static void bnxt_fw_reset_cb(void *arg)
3888 {
3889         struct bnxt *bp = arg;
3890         struct bnxt_error_recovery_info *info = bp->recovery_info;
3891         int rc = 0;
3892
3893         /* Only Master function can do FW reset */
3894         if (bnxt_is_master_func(bp) &&
3895             bnxt_is_recovery_enabled(bp)) {
3896                 rc = bnxt_fw_reset_all(bp);
3897                 if (rc) {
3898                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3899                         return;
3900                 }
3901         }
3902
3903         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3904          * EXCEPTION_FATAL_ASYNC event to all the functions
3905          * (including MASTER FUNC). After receiving this Async, all the active
3906          * drivers should treat this case as FW initiated recovery
3907          */
3908         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3909                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3910                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3911
3912                 /* To recover from error */
3913                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3914                                   (void *)bp);
3915         }
3916 }
3917
3918 /* Driver should poll FW heartbeat, reset_counter with the frequency
3919  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3920  * When the driver detects heartbeat stop or change in reset_counter,
3921  * it has to trigger a reset to recover from the error condition.
3922  * A “master PF” is the function who will have the privilege to
3923  * initiate the chimp reset. The master PF will be elected by the
3924  * firmware and will be notified through async message.
3925  */
3926 static void bnxt_check_fw_health(void *arg)
3927 {
3928         struct bnxt *bp = arg;
3929         struct bnxt_error_recovery_info *info = bp->recovery_info;
3930         uint32_t val = 0, wait_msec;
3931
3932         if (!info || !bnxt_is_recovery_enabled(bp) ||
3933             is_bnxt_in_error(bp))
3934                 return;
3935
3936         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3937         if (val == info->last_heart_beat)
3938                 goto reset;
3939
3940         info->last_heart_beat = val;
3941
3942         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3943         if (val != info->last_reset_counter)
3944                 goto reset;
3945
3946         info->last_reset_counter = val;
3947
3948         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3949                           bnxt_check_fw_health, (void *)bp);
3950
3951         return;
3952 reset:
3953         /* Stop DMA to/from device */
3954         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3955         bp->flags |= BNXT_FLAG_FW_RESET;
3956
3957         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3958
3959         if (bnxt_is_master_func(bp))
3960                 wait_msec = info->master_func_wait_period;
3961         else
3962                 wait_msec = info->normal_func_wait_period;
3963
3964         rte_eal_alarm_set(US_PER_MS * wait_msec,
3965                           bnxt_fw_reset_cb, (void *)bp);
3966 }
3967
3968 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3969 {
3970         uint32_t polling_freq;
3971
3972         pthread_mutex_lock(&bp->health_check_lock);
3973
3974         if (!bnxt_is_recovery_enabled(bp))
3975                 goto done;
3976
3977         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3978                 goto done;
3979
3980         polling_freq = bp->recovery_info->driver_polling_freq;
3981
3982         rte_eal_alarm_set(US_PER_MS * polling_freq,
3983                           bnxt_check_fw_health, (void *)bp);
3984         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3985
3986 done:
3987         pthread_mutex_unlock(&bp->health_check_lock);
3988 }
3989
3990 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3991 {
3992         if (!bnxt_is_recovery_enabled(bp))
3993                 return;
3994
3995         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3996         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3997 }
3998
3999 static bool bnxt_vf_pciid(uint16_t device_id)
4000 {
4001         switch (device_id) {
4002         case BROADCOM_DEV_ID_57304_VF:
4003         case BROADCOM_DEV_ID_57406_VF:
4004         case BROADCOM_DEV_ID_5731X_VF:
4005         case BROADCOM_DEV_ID_5741X_VF:
4006         case BROADCOM_DEV_ID_57414_VF:
4007         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4008         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4009         case BROADCOM_DEV_ID_58802_VF:
4010         case BROADCOM_DEV_ID_57500_VF1:
4011         case BROADCOM_DEV_ID_57500_VF2:
4012         case BROADCOM_DEV_ID_58818_VF:
4013                 /* FALLTHROUGH */
4014                 return true;
4015         default:
4016                 return false;
4017         }
4018 }
4019
4020 /* Phase 5 device */
4021 static bool bnxt_p5_device(uint16_t device_id)
4022 {
4023         switch (device_id) {
4024         case BROADCOM_DEV_ID_57508:
4025         case BROADCOM_DEV_ID_57504:
4026         case BROADCOM_DEV_ID_57502:
4027         case BROADCOM_DEV_ID_57508_MF1:
4028         case BROADCOM_DEV_ID_57504_MF1:
4029         case BROADCOM_DEV_ID_57502_MF1:
4030         case BROADCOM_DEV_ID_57508_MF2:
4031         case BROADCOM_DEV_ID_57504_MF2:
4032         case BROADCOM_DEV_ID_57502_MF2:
4033         case BROADCOM_DEV_ID_57500_VF1:
4034         case BROADCOM_DEV_ID_57500_VF2:
4035         case BROADCOM_DEV_ID_58812:
4036         case BROADCOM_DEV_ID_58814:
4037         case BROADCOM_DEV_ID_58818:
4038         case BROADCOM_DEV_ID_58818_VF:
4039                 /* FALLTHROUGH */
4040                 return true;
4041         default:
4042                 return false;
4043         }
4044 }
4045
4046 bool bnxt_stratus_device(struct bnxt *bp)
4047 {
4048         uint16_t device_id = bp->pdev->id.device_id;
4049
4050         switch (device_id) {
4051         case BROADCOM_DEV_ID_STRATUS_NIC:
4052         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4053         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4054                 /* FALLTHROUGH */
4055                 return true;
4056         default:
4057                 return false;
4058         }
4059 }
4060
4061 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4062 {
4063         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4064         struct bnxt *bp = eth_dev->data->dev_private;
4065
4066         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4067         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4068         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4069         if (!bp->bar0 || !bp->doorbell_base) {
4070                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4071                 return -ENODEV;
4072         }
4073
4074         bp->eth_dev = eth_dev;
4075         bp->pdev = pci_dev;
4076
4077         return 0;
4078 }
4079
4080 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4081                                   struct bnxt_ctx_pg_info *ctx_pg,
4082                                   uint32_t mem_size,
4083                                   const char *suffix,
4084                                   uint16_t idx)
4085 {
4086         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4087         const struct rte_memzone *mz = NULL;
4088         char mz_name[RTE_MEMZONE_NAMESIZE];
4089         rte_iova_t mz_phys_addr;
4090         uint64_t valid_bits = 0;
4091         uint32_t sz;
4092         int i;
4093
4094         if (!mem_size)
4095                 return 0;
4096
4097         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4098                          BNXT_PAGE_SIZE;
4099         rmem->page_size = BNXT_PAGE_SIZE;
4100         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4101         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4102         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4103
4104         valid_bits = PTU_PTE_VALID;
4105
4106         if (rmem->nr_pages > 1) {
4107                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4108                          "bnxt_ctx_pg_tbl%s_%x_%d",
4109                          suffix, idx, bp->eth_dev->data->port_id);
4110                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4111                 mz = rte_memzone_lookup(mz_name);
4112                 if (!mz) {
4113                         mz = rte_memzone_reserve_aligned(mz_name,
4114                                                 rmem->nr_pages * 8,
4115                                                 SOCKET_ID_ANY,
4116                                                 RTE_MEMZONE_2MB |
4117                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4118                                                 RTE_MEMZONE_IOVA_CONTIG,
4119                                                 BNXT_PAGE_SIZE);
4120                         if (mz == NULL)
4121                                 return -ENOMEM;
4122                 }
4123
4124                 memset(mz->addr, 0, mz->len);
4125                 mz_phys_addr = mz->iova;
4126
4127                 rmem->pg_tbl = mz->addr;
4128                 rmem->pg_tbl_map = mz_phys_addr;
4129                 rmem->pg_tbl_mz = mz;
4130         }
4131
4132         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4133                  suffix, idx, bp->eth_dev->data->port_id);
4134         mz = rte_memzone_lookup(mz_name);
4135         if (!mz) {
4136                 mz = rte_memzone_reserve_aligned(mz_name,
4137                                                  mem_size,
4138                                                  SOCKET_ID_ANY,
4139                                                  RTE_MEMZONE_1GB |
4140                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4141                                                  RTE_MEMZONE_IOVA_CONTIG,
4142                                                  BNXT_PAGE_SIZE);
4143                 if (mz == NULL)
4144                         return -ENOMEM;
4145         }
4146
4147         memset(mz->addr, 0, mz->len);
4148         mz_phys_addr = mz->iova;
4149
4150         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4151                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4152                 rmem->dma_arr[i] = mz_phys_addr + sz;
4153
4154                 if (rmem->nr_pages > 1) {
4155                         if (i == rmem->nr_pages - 2 &&
4156                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4157                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4158                         else if (i == rmem->nr_pages - 1 &&
4159                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4160                                 valid_bits |= PTU_PTE_LAST;
4161
4162                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4163                                                            valid_bits);
4164                 }
4165         }
4166
4167         rmem->mz = mz;
4168         if (rmem->vmem_size)
4169                 rmem->vmem = (void **)mz->addr;
4170         rmem->dma_arr[0] = mz_phys_addr;
4171         return 0;
4172 }
4173
4174 static void bnxt_free_ctx_mem(struct bnxt *bp)
4175 {
4176         int i;
4177
4178         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4179                 return;
4180
4181         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4182         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4183         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4184         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4185         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4186         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4187         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4188         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4189         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4190         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4191         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4192
4193         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4194                 if (bp->ctx->tqm_mem[i])
4195                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4196         }
4197
4198         rte_free(bp->ctx);
4199         bp->ctx = NULL;
4200 }
4201
4202 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4203
4204 #define min_t(type, x, y) ({                    \
4205         type __min1 = (x);                      \
4206         type __min2 = (y);                      \
4207         __min1 < __min2 ? __min1 : __min2; })
4208
4209 #define max_t(type, x, y) ({                    \
4210         type __max1 = (x);                      \
4211         type __max2 = (y);                      \
4212         __max1 > __max2 ? __max1 : __max2; })
4213
4214 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4215
4216 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4217 {
4218         struct bnxt_ctx_pg_info *ctx_pg;
4219         struct bnxt_ctx_mem_info *ctx;
4220         uint32_t mem_size, ena, entries;
4221         uint32_t entries_sp, min;
4222         int i, rc;
4223
4224         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4225         if (rc) {
4226                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4227                 return rc;
4228         }
4229         ctx = bp->ctx;
4230         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4231                 return 0;
4232
4233         ctx_pg = &ctx->qp_mem;
4234         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4235         if (ctx->qp_entry_size) {
4236                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4237                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4238                 if (rc)
4239                         return rc;
4240         }
4241
4242         ctx_pg = &ctx->srq_mem;
4243         ctx_pg->entries = ctx->srq_max_l2_entries;
4244         if (ctx->srq_entry_size) {
4245                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4246                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4247                 if (rc)
4248                         return rc;
4249         }
4250
4251         ctx_pg = &ctx->cq_mem;
4252         ctx_pg->entries = ctx->cq_max_l2_entries;
4253         if (ctx->cq_entry_size) {
4254                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4255                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4256                 if (rc)
4257                         return rc;
4258         }
4259
4260         ctx_pg = &ctx->vnic_mem;
4261         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4262                 ctx->vnic_max_ring_table_entries;
4263         if (ctx->vnic_entry_size) {
4264                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4265                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4266                 if (rc)
4267                         return rc;
4268         }
4269
4270         ctx_pg = &ctx->stat_mem;
4271         ctx_pg->entries = ctx->stat_max_entries;
4272         if (ctx->stat_entry_size) {
4273                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4274                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4275                 if (rc)
4276                         return rc;
4277         }
4278
4279         min = ctx->tqm_min_entries_per_ring;
4280
4281         entries_sp = ctx->qp_max_l2_entries +
4282                      ctx->vnic_max_vnic_entries +
4283                      2 * ctx->qp_min_qp1_entries + min;
4284         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4285
4286         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4287         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4288         entries = clamp_t(uint32_t, entries, min,
4289                           ctx->tqm_max_entries_per_ring);
4290         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4291                 ctx_pg = ctx->tqm_mem[i];
4292                 ctx_pg->entries = i ? entries : entries_sp;
4293                 if (ctx->tqm_entry_size) {
4294                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4295                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4296                         if (rc)
4297                                 return rc;
4298                 }
4299                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4300         }
4301
4302         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4303         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4304         if (rc)
4305                 PMD_DRV_LOG(ERR,
4306                             "Failed to configure context mem: rc = %d\n", rc);
4307         else
4308                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4309
4310         return rc;
4311 }
4312
4313 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4314 {
4315         struct rte_pci_device *pci_dev = bp->pdev;
4316         char mz_name[RTE_MEMZONE_NAMESIZE];
4317         const struct rte_memzone *mz = NULL;
4318         uint32_t total_alloc_len;
4319         rte_iova_t mz_phys_addr;
4320
4321         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4322                 return 0;
4323
4324         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4325                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4326                  pci_dev->addr.bus, pci_dev->addr.devid,
4327                  pci_dev->addr.function, "rx_port_stats");
4328         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4329         mz = rte_memzone_lookup(mz_name);
4330         total_alloc_len =
4331                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4332                                        sizeof(struct rx_port_stats_ext) + 512);
4333         if (!mz) {
4334                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4335                                          SOCKET_ID_ANY,
4336                                          RTE_MEMZONE_2MB |
4337                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4338                                          RTE_MEMZONE_IOVA_CONTIG);
4339                 if (mz == NULL)
4340                         return -ENOMEM;
4341         }
4342         memset(mz->addr, 0, mz->len);
4343         mz_phys_addr = mz->iova;
4344
4345         bp->rx_mem_zone = (const void *)mz;
4346         bp->hw_rx_port_stats = mz->addr;
4347         bp->hw_rx_port_stats_map = mz_phys_addr;
4348
4349         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4350                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4351                  pci_dev->addr.bus, pci_dev->addr.devid,
4352                  pci_dev->addr.function, "tx_port_stats");
4353         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4354         mz = rte_memzone_lookup(mz_name);
4355         total_alloc_len =
4356                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4357                                        sizeof(struct tx_port_stats_ext) + 512);
4358         if (!mz) {
4359                 mz = rte_memzone_reserve(mz_name,
4360                                          total_alloc_len,
4361                                          SOCKET_ID_ANY,
4362                                          RTE_MEMZONE_2MB |
4363                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4364                                          RTE_MEMZONE_IOVA_CONTIG);
4365                 if (mz == NULL)
4366                         return -ENOMEM;
4367         }
4368         memset(mz->addr, 0, mz->len);
4369         mz_phys_addr = mz->iova;
4370
4371         bp->tx_mem_zone = (const void *)mz;
4372         bp->hw_tx_port_stats = mz->addr;
4373         bp->hw_tx_port_stats_map = mz_phys_addr;
4374         bp->flags |= BNXT_FLAG_PORT_STATS;
4375
4376         /* Display extended statistics if FW supports it */
4377         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4378             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4379             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4380                 return 0;
4381
4382         bp->hw_rx_port_stats_ext = (void *)
4383                 ((uint8_t *)bp->hw_rx_port_stats +
4384                  sizeof(struct rx_port_stats));
4385         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4386                 sizeof(struct rx_port_stats);
4387         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4388
4389         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4390             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4391                 bp->hw_tx_port_stats_ext = (void *)
4392                         ((uint8_t *)bp->hw_tx_port_stats +
4393                          sizeof(struct tx_port_stats));
4394                 bp->hw_tx_port_stats_ext_map =
4395                         bp->hw_tx_port_stats_map +
4396                         sizeof(struct tx_port_stats);
4397                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4398         }
4399
4400         return 0;
4401 }
4402
4403 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4404 {
4405         struct bnxt *bp = eth_dev->data->dev_private;
4406         int rc = 0;
4407
4408         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4409                                                RTE_ETHER_ADDR_LEN *
4410                                                bp->max_l2_ctx,
4411                                                0);
4412         if (eth_dev->data->mac_addrs == NULL) {
4413                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4414                 return -ENOMEM;
4415         }
4416
4417         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4418                 if (BNXT_PF(bp))
4419                         return -EINVAL;
4420
4421                 /* Generate a random MAC address, if none was assigned by PF */
4422                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4423                 bnxt_eth_hw_addr_random(bp->mac_addr);
4424                 PMD_DRV_LOG(INFO,
4425                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4426                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4427                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4428
4429                 rc = bnxt_hwrm_set_mac(bp);
4430                 if (rc)
4431                         return rc;
4432         }
4433
4434         /* Copy the permanent MAC from the FUNC_QCAPS response */
4435         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4436
4437         return rc;
4438 }
4439
4440 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4441 {
4442         int rc = 0;
4443
4444         /* MAC is already configured in FW */
4445         if (BNXT_HAS_DFLT_MAC_SET(bp))
4446                 return 0;
4447
4448         /* Restore the old MAC configured */
4449         rc = bnxt_hwrm_set_mac(bp);
4450         if (rc)
4451                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4452
4453         return rc;
4454 }
4455
4456 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4457 {
4458         if (!BNXT_PF(bp))
4459                 return;
4460
4461         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4462
4463         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4464                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4465         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4466         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4467         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4468         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4469 }
4470
4471 uint16_t
4472 bnxt_get_svif(uint16_t port_id, bool func_svif,
4473               enum bnxt_ulp_intf_type type)
4474 {
4475         struct rte_eth_dev *eth_dev;
4476         struct bnxt *bp;
4477
4478         eth_dev = &rte_eth_devices[port_id];
4479         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4480                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4481                 if (!vfr)
4482                         return 0;
4483
4484                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4485                         return vfr->svif;
4486
4487                 eth_dev = vfr->parent_dev;
4488         }
4489
4490         bp = eth_dev->data->dev_private;
4491
4492         return func_svif ? bp->func_svif : bp->port_svif;
4493 }
4494
4495 uint16_t
4496 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4497 {
4498         struct rte_eth_dev *eth_dev;
4499         struct bnxt_vnic_info *vnic;
4500         struct bnxt *bp;
4501
4502         eth_dev = &rte_eth_devices[port];
4503         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4504                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4505                 if (!vfr)
4506                         return 0;
4507
4508                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4509                         return vfr->dflt_vnic_id;
4510
4511                 eth_dev = vfr->parent_dev;
4512         }
4513
4514         bp = eth_dev->data->dev_private;
4515
4516         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4517
4518         return vnic->fw_vnic_id;
4519 }
4520
4521 uint16_t
4522 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4523 {
4524         struct rte_eth_dev *eth_dev;
4525         struct bnxt *bp;
4526
4527         eth_dev = &rte_eth_devices[port];
4528         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4529                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4530                 if (!vfr)
4531                         return 0;
4532
4533                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4534                         return vfr->fw_fid;
4535
4536                 eth_dev = vfr->parent_dev;
4537         }
4538
4539         bp = eth_dev->data->dev_private;
4540
4541         return bp->fw_fid;
4542 }
4543
4544 enum bnxt_ulp_intf_type
4545 bnxt_get_interface_type(uint16_t port)
4546 {
4547         struct rte_eth_dev *eth_dev;
4548         struct bnxt *bp;
4549
4550         eth_dev = &rte_eth_devices[port];
4551         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4552                 return BNXT_ULP_INTF_TYPE_VF_REP;
4553
4554         bp = eth_dev->data->dev_private;
4555         if (BNXT_PF(bp))
4556                 return BNXT_ULP_INTF_TYPE_PF;
4557         else if (BNXT_VF_IS_TRUSTED(bp))
4558                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4559         else if (BNXT_VF(bp))
4560                 return BNXT_ULP_INTF_TYPE_VF;
4561
4562         return BNXT_ULP_INTF_TYPE_INVALID;
4563 }
4564
4565 uint16_t
4566 bnxt_get_phy_port_id(uint16_t port_id)
4567 {
4568         struct bnxt_representor *vfr;
4569         struct rte_eth_dev *eth_dev;
4570         struct bnxt *bp;
4571
4572         eth_dev = &rte_eth_devices[port_id];
4573         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4574                 vfr = eth_dev->data->dev_private;
4575                 if (!vfr)
4576                         return 0;
4577
4578                 eth_dev = vfr->parent_dev;
4579         }
4580
4581         bp = eth_dev->data->dev_private;
4582
4583         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4584 }
4585
4586 uint16_t
4587 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4588 {
4589         struct rte_eth_dev *eth_dev;
4590         struct bnxt *bp;
4591
4592         eth_dev = &rte_eth_devices[port_id];
4593         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4594                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4595                 if (!vfr)
4596                         return 0;
4597
4598                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4599                         return vfr->fw_fid - 1;
4600
4601                 eth_dev = vfr->parent_dev;
4602         }
4603
4604         bp = eth_dev->data->dev_private;
4605
4606         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4607 }
4608
4609 uint16_t
4610 bnxt_get_vport(uint16_t port_id)
4611 {
4612         return (1 << bnxt_get_phy_port_id(port_id));
4613 }
4614
4615 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4616 {
4617         struct bnxt_error_recovery_info *info = bp->recovery_info;
4618
4619         if (info) {
4620                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4621                         memset(info, 0, sizeof(*info));
4622                 return;
4623         }
4624
4625         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4626                 return;
4627
4628         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4629                            sizeof(*info), 0);
4630         if (!info)
4631                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4632
4633         bp->recovery_info = info;
4634 }
4635
4636 static void bnxt_check_fw_status(struct bnxt *bp)
4637 {
4638         uint32_t fw_status;
4639
4640         if (!(bp->recovery_info &&
4641               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4642                 return;
4643
4644         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4645         if (fw_status != BNXT_FW_STATUS_HEALTHY)
4646                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4647                             fw_status);
4648 }
4649
4650 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4651 {
4652         struct bnxt_error_recovery_info *info = bp->recovery_info;
4653         uint32_t status_loc;
4654         uint32_t sig_ver;
4655
4656         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4657                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4658         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4659                                    BNXT_GRCP_WINDOW_2_BASE +
4660                                    offsetof(struct hcomm_status,
4661                                             sig_ver)));
4662         /* If the signature is absent, then FW does not support this feature */
4663         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4664             HCOMM_STATUS_SIGNATURE_VAL)
4665                 return 0;
4666
4667         if (!info) {
4668                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4669                                    sizeof(*info), 0);
4670                 if (!info)
4671                         return -ENOMEM;
4672                 bp->recovery_info = info;
4673         } else {
4674                 memset(info, 0, sizeof(*info));
4675         }
4676
4677         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4678                                       BNXT_GRCP_WINDOW_2_BASE +
4679                                       offsetof(struct hcomm_status,
4680                                                fw_status_loc)));
4681
4682         /* Only pre-map the FW health status GRC register */
4683         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4684                 return 0;
4685
4686         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4687         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4688                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4689
4690         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4691                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4692
4693         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4694
4695         return 0;
4696 }
4697
4698 static int bnxt_init_fw(struct bnxt *bp)
4699 {
4700         uint16_t mtu;
4701         int rc = 0;
4702
4703         bp->fw_cap = 0;
4704
4705         rc = bnxt_map_hcomm_fw_status_reg(bp);
4706         if (rc)
4707                 return rc;
4708
4709         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4710         if (rc) {
4711                 bnxt_check_fw_status(bp);
4712                 return rc;
4713         }
4714
4715         rc = bnxt_hwrm_func_reset(bp);
4716         if (rc)
4717                 return -EIO;
4718
4719         rc = bnxt_hwrm_vnic_qcaps(bp);
4720         if (rc)
4721                 return rc;
4722
4723         rc = bnxt_hwrm_queue_qportcfg(bp);
4724         if (rc)
4725                 return rc;
4726
4727         /* Get the MAX capabilities for this function.
4728          * This function also allocates context memory for TQM rings and
4729          * informs the firmware about this allocated backing store memory.
4730          */
4731         rc = bnxt_hwrm_func_qcaps(bp);
4732         if (rc)
4733                 return rc;
4734
4735         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4736         if (rc)
4737                 return rc;
4738
4739         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4740         if (rc)
4741                 return rc;
4742
4743         bnxt_hwrm_port_mac_qcfg(bp);
4744
4745         bnxt_hwrm_parent_pf_qcfg(bp);
4746
4747         bnxt_hwrm_port_phy_qcaps(bp);
4748
4749         bnxt_alloc_error_recovery_info(bp);
4750         /* Get the adapter error recovery support info */
4751         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4752         if (rc)
4753                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4754
4755         bnxt_hwrm_port_led_qcaps(bp);
4756
4757         return 0;
4758 }
4759
4760 static int
4761 bnxt_init_locks(struct bnxt *bp)
4762 {
4763         int err;
4764
4765         err = pthread_mutex_init(&bp->flow_lock, NULL);
4766         if (err) {
4767                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4768                 return err;
4769         }
4770
4771         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4772         if (err) {
4773                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4774                 return err;
4775         }
4776
4777         err = pthread_mutex_init(&bp->health_check_lock, NULL);
4778         if (err)
4779                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
4780         return err;
4781 }
4782
4783 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4784 {
4785         int rc = 0;
4786
4787         rc = bnxt_init_fw(bp);
4788         if (rc)
4789                 return rc;
4790
4791         if (!reconfig_dev) {
4792                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4793                 if (rc)
4794                         return rc;
4795         } else {
4796                 rc = bnxt_restore_dflt_mac(bp);
4797                 if (rc)
4798                         return rc;
4799         }
4800
4801         bnxt_config_vf_req_fwd(bp);
4802
4803         rc = bnxt_hwrm_func_driver_register(bp);
4804         if (rc) {
4805                 PMD_DRV_LOG(ERR, "Failed to register driver");
4806                 return -EBUSY;
4807         }
4808
4809         if (BNXT_PF(bp)) {
4810                 if (bp->pdev->max_vfs) {
4811                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4812                         if (rc) {
4813                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4814                                 return rc;
4815                         }
4816                 } else {
4817                         rc = bnxt_hwrm_allocate_pf_only(bp);
4818                         if (rc) {
4819                                 PMD_DRV_LOG(ERR,
4820                                             "Failed to allocate PF resources");
4821                                 return rc;
4822                         }
4823                 }
4824         }
4825
4826         rc = bnxt_alloc_mem(bp, reconfig_dev);
4827         if (rc)
4828                 return rc;
4829
4830         rc = bnxt_setup_int(bp);
4831         if (rc)
4832                 return rc;
4833
4834         rc = bnxt_request_int(bp);
4835         if (rc)
4836                 return rc;
4837
4838         rc = bnxt_init_ctx_mem(bp);
4839         if (rc) {
4840                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
4841                 return rc;
4842         }
4843
4844         return 0;
4845 }
4846
4847 static int
4848 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4849                           const char *value, void *opaque_arg)
4850 {
4851         struct bnxt *bp = opaque_arg;
4852         unsigned long truflow;
4853         char *end = NULL;
4854
4855         if (!value || !opaque_arg) {
4856                 PMD_DRV_LOG(ERR,
4857                             "Invalid parameter passed to truflow devargs.\n");
4858                 return -EINVAL;
4859         }
4860
4861         truflow = strtoul(value, &end, 10);
4862         if (end == NULL || *end != '\0' ||
4863             (truflow == ULONG_MAX && errno == ERANGE)) {
4864                 PMD_DRV_LOG(ERR,
4865                             "Invalid parameter passed to truflow devargs.\n");
4866                 return -EINVAL;
4867         }
4868
4869         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4870                 PMD_DRV_LOG(ERR,
4871                             "Invalid value passed to truflow devargs.\n");
4872                 return -EINVAL;
4873         }
4874
4875         if (truflow) {
4876                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
4877                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4878         } else {
4879                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
4880                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
4881         }
4882
4883         return 0;
4884 }
4885
4886 static int
4887 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
4888                              const char *value, void *opaque_arg)
4889 {
4890         struct bnxt *bp = opaque_arg;
4891         unsigned long flow_xstat;
4892         char *end = NULL;
4893
4894         if (!value || !opaque_arg) {
4895                 PMD_DRV_LOG(ERR,
4896                             "Invalid parameter passed to flow_xstat devarg.\n");
4897                 return -EINVAL;
4898         }
4899
4900         flow_xstat = strtoul(value, &end, 10);
4901         if (end == NULL || *end != '\0' ||
4902             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
4903                 PMD_DRV_LOG(ERR,
4904                             "Invalid parameter passed to flow_xstat devarg.\n");
4905                 return -EINVAL;
4906         }
4907
4908         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
4909                 PMD_DRV_LOG(ERR,
4910                             "Invalid value passed to flow_xstat devarg.\n");
4911                 return -EINVAL;
4912         }
4913
4914         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
4915         if (BNXT_FLOW_XSTATS_EN(bp))
4916                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
4917
4918         return 0;
4919 }
4920
4921 static int
4922 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
4923                                         const char *value, void *opaque_arg)
4924 {
4925         struct bnxt *bp = opaque_arg;
4926         unsigned long max_num_kflows;
4927         char *end = NULL;
4928
4929         if (!value || !opaque_arg) {
4930                 PMD_DRV_LOG(ERR,
4931                         "Invalid parameter passed to max_num_kflows devarg.\n");
4932                 return -EINVAL;
4933         }
4934
4935         max_num_kflows = strtoul(value, &end, 10);
4936         if (end == NULL || *end != '\0' ||
4937                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
4938                 PMD_DRV_LOG(ERR,
4939                         "Invalid parameter passed to max_num_kflows devarg.\n");
4940                 return -EINVAL;
4941         }
4942
4943         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
4944                 PMD_DRV_LOG(ERR,
4945                         "Invalid value passed to max_num_kflows devarg.\n");
4946                 return -EINVAL;
4947         }
4948
4949         bp->max_num_kflows = max_num_kflows;
4950         if (bp->max_num_kflows)
4951                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
4952                                 max_num_kflows);
4953
4954         return 0;
4955 }
4956
4957 static int
4958 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
4959                             const char *value, void *opaque_arg)
4960 {
4961         struct bnxt_representor *vfr_bp = opaque_arg;
4962         unsigned long rep_is_pf;
4963         char *end = NULL;
4964
4965         if (!value || !opaque_arg) {
4966                 PMD_DRV_LOG(ERR,
4967                             "Invalid parameter passed to rep_is_pf devargs.\n");
4968                 return -EINVAL;
4969         }
4970
4971         rep_is_pf = strtoul(value, &end, 10);
4972         if (end == NULL || *end != '\0' ||
4973             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
4974                 PMD_DRV_LOG(ERR,
4975                             "Invalid parameter passed to rep_is_pf devargs.\n");
4976                 return -EINVAL;
4977         }
4978
4979         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
4980                 PMD_DRV_LOG(ERR,
4981                             "Invalid value passed to rep_is_pf devargs.\n");
4982                 return -EINVAL;
4983         }
4984
4985         vfr_bp->flags |= rep_is_pf;
4986         if (BNXT_REP_PF(vfr_bp))
4987                 PMD_DRV_LOG(INFO, "PF representor\n");
4988         else
4989                 PMD_DRV_LOG(INFO, "VF representor\n");
4990
4991         return 0;
4992 }
4993
4994 static int
4995 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
4996                                const char *value, void *opaque_arg)
4997 {
4998         struct bnxt_representor *vfr_bp = opaque_arg;
4999         unsigned long rep_based_pf;
5000         char *end = NULL;
5001
5002         if (!value || !opaque_arg) {
5003                 PMD_DRV_LOG(ERR,
5004                             "Invalid parameter passed to rep_based_pf "
5005                             "devargs.\n");
5006                 return -EINVAL;
5007         }
5008
5009         rep_based_pf = strtoul(value, &end, 10);
5010         if (end == NULL || *end != '\0' ||
5011             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5012                 PMD_DRV_LOG(ERR,
5013                             "Invalid parameter passed to rep_based_pf "
5014                             "devargs.\n");
5015                 return -EINVAL;
5016         }
5017
5018         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5019                 PMD_DRV_LOG(ERR,
5020                             "Invalid value passed to rep_based_pf devargs.\n");
5021                 return -EINVAL;
5022         }
5023
5024         vfr_bp->rep_based_pf = rep_based_pf;
5025         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5026
5027         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5028
5029         return 0;
5030 }
5031
5032 static int
5033 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5034                             const char *value, void *opaque_arg)
5035 {
5036         struct bnxt_representor *vfr_bp = opaque_arg;
5037         unsigned long rep_q_r2f;
5038         char *end = NULL;
5039
5040         if (!value || !opaque_arg) {
5041                 PMD_DRV_LOG(ERR,
5042                             "Invalid parameter passed to rep_q_r2f "
5043                             "devargs.\n");
5044                 return -EINVAL;
5045         }
5046
5047         rep_q_r2f = strtoul(value, &end, 10);
5048         if (end == NULL || *end != '\0' ||
5049             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5050                 PMD_DRV_LOG(ERR,
5051                             "Invalid parameter passed to rep_q_r2f "
5052                             "devargs.\n");
5053                 return -EINVAL;
5054         }
5055
5056         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5057                 PMD_DRV_LOG(ERR,
5058                             "Invalid value passed to rep_q_r2f devargs.\n");
5059                 return -EINVAL;
5060         }
5061
5062         vfr_bp->rep_q_r2f = rep_q_r2f;
5063         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5064         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5065
5066         return 0;
5067 }
5068
5069 static int
5070 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5071                             const char *value, void *opaque_arg)
5072 {
5073         struct bnxt_representor *vfr_bp = opaque_arg;
5074         unsigned long rep_q_f2r;
5075         char *end = NULL;
5076
5077         if (!value || !opaque_arg) {
5078                 PMD_DRV_LOG(ERR,
5079                             "Invalid parameter passed to rep_q_f2r "
5080                             "devargs.\n");
5081                 return -EINVAL;
5082         }
5083
5084         rep_q_f2r = strtoul(value, &end, 10);
5085         if (end == NULL || *end != '\0' ||
5086             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5087                 PMD_DRV_LOG(ERR,
5088                             "Invalid parameter passed to rep_q_f2r "
5089                             "devargs.\n");
5090                 return -EINVAL;
5091         }
5092
5093         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5094                 PMD_DRV_LOG(ERR,
5095                             "Invalid value passed to rep_q_f2r devargs.\n");
5096                 return -EINVAL;
5097         }
5098
5099         vfr_bp->rep_q_f2r = rep_q_f2r;
5100         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5101         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5102
5103         return 0;
5104 }
5105
5106 static int
5107 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5108                              const char *value, void *opaque_arg)
5109 {
5110         struct bnxt_representor *vfr_bp = opaque_arg;
5111         unsigned long rep_fc_r2f;
5112         char *end = NULL;
5113
5114         if (!value || !opaque_arg) {
5115                 PMD_DRV_LOG(ERR,
5116                             "Invalid parameter passed to rep_fc_r2f "
5117                             "devargs.\n");
5118                 return -EINVAL;
5119         }
5120
5121         rep_fc_r2f = strtoul(value, &end, 10);
5122         if (end == NULL || *end != '\0' ||
5123             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5124                 PMD_DRV_LOG(ERR,
5125                             "Invalid parameter passed to rep_fc_r2f "
5126                             "devargs.\n");
5127                 return -EINVAL;
5128         }
5129
5130         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5131                 PMD_DRV_LOG(ERR,
5132                             "Invalid value passed to rep_fc_r2f devargs.\n");
5133                 return -EINVAL;
5134         }
5135
5136         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5137         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5138         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5139
5140         return 0;
5141 }
5142
5143 static int
5144 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5145                              const char *value, void *opaque_arg)
5146 {
5147         struct bnxt_representor *vfr_bp = opaque_arg;
5148         unsigned long rep_fc_f2r;
5149         char *end = NULL;
5150
5151         if (!value || !opaque_arg) {
5152                 PMD_DRV_LOG(ERR,
5153                             "Invalid parameter passed to rep_fc_f2r "
5154                             "devargs.\n");
5155                 return -EINVAL;
5156         }
5157
5158         rep_fc_f2r = strtoul(value, &end, 10);
5159         if (end == NULL || *end != '\0' ||
5160             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5161                 PMD_DRV_LOG(ERR,
5162                             "Invalid parameter passed to rep_fc_f2r "
5163                             "devargs.\n");
5164                 return -EINVAL;
5165         }
5166
5167         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5168                 PMD_DRV_LOG(ERR,
5169                             "Invalid value passed to rep_fc_f2r devargs.\n");
5170                 return -EINVAL;
5171         }
5172
5173         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5174         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5175         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5176
5177         return 0;
5178 }
5179
5180 static void
5181 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5182 {
5183         struct rte_kvargs *kvlist;
5184
5185         if (devargs == NULL)
5186                 return;
5187
5188         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5189         if (kvlist == NULL)
5190                 return;
5191
5192         /*
5193          * Handler for "truflow" devarg.
5194          * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5195          */
5196         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5197                            bnxt_parse_devarg_truflow, bp);
5198
5199         /*
5200          * Handler for "flow_xstat" devarg.
5201          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5202          */
5203         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5204                            bnxt_parse_devarg_flow_xstat, bp);
5205
5206         /*
5207          * Handler for "max_num_kflows" devarg.
5208          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5209          */
5210         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5211                            bnxt_parse_devarg_max_num_kflows, bp);
5212
5213         rte_kvargs_free(kvlist);
5214 }
5215
5216 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5217 {
5218         int rc = 0;
5219
5220         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5221                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5222                 if (rc)
5223                         PMD_DRV_LOG(ERR,
5224                                     "Failed to alloc switch domain: %d\n", rc);
5225                 else
5226                         PMD_DRV_LOG(INFO,
5227                                     "Switch domain allocated %d\n",
5228                                     bp->switch_domain_id);
5229         }
5230
5231         return rc;
5232 }
5233
5234 static int
5235 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5236 {
5237         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5238         static int version_printed;
5239         struct bnxt *bp;
5240         int rc;
5241
5242         if (version_printed++ == 0)
5243                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5244
5245         eth_dev->dev_ops = &bnxt_dev_ops;
5246         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5247         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5248         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5249         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5250         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5251
5252         /*
5253          * For secondary processes, we don't initialise any further
5254          * as primary has already done this work.
5255          */
5256         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5257                 return 0;
5258
5259         rte_eth_copy_pci_info(eth_dev, pci_dev);
5260         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5261
5262         bp = eth_dev->data->dev_private;
5263
5264         /* Parse dev arguments passed on when starting the DPDK application. */
5265         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5266
5267         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5268
5269         if (bnxt_vf_pciid(pci_dev->id.device_id))
5270                 bp->flags |= BNXT_FLAG_VF;
5271
5272         if (bnxt_p5_device(pci_dev->id.device_id))
5273                 bp->flags |= BNXT_FLAG_CHIP_P5;
5274
5275         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5276             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5277             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5278             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5279                 bp->flags |= BNXT_FLAG_STINGRAY;
5280
5281         if (BNXT_TRUFLOW_EN(bp)) {
5282                 /* extra mbuf field is required to store CFA code from mark */
5283                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5284                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5285                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5286                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5287                 };
5288                 bnxt_cfa_code_dynfield_offset =
5289                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5290                 if (bnxt_cfa_code_dynfield_offset < 0) {
5291                         PMD_DRV_LOG(ERR,
5292                             "Failed to register mbuf field for TruFlow mark\n");
5293                         return -rte_errno;
5294                 }
5295         }
5296
5297         rc = bnxt_init_board(eth_dev);
5298         if (rc) {
5299                 PMD_DRV_LOG(ERR,
5300                             "Failed to initialize board rc: %x\n", rc);
5301                 return rc;
5302         }
5303
5304         rc = bnxt_alloc_pf_info(bp);
5305         if (rc)
5306                 goto error_free;
5307
5308         rc = bnxt_alloc_link_info(bp);
5309         if (rc)
5310                 goto error_free;
5311
5312         rc = bnxt_alloc_parent_info(bp);
5313         if (rc)
5314                 goto error_free;
5315
5316         rc = bnxt_alloc_hwrm_resources(bp);
5317         if (rc) {
5318                 PMD_DRV_LOG(ERR,
5319                             "Failed to allocate hwrm resource rc: %x\n", rc);
5320                 goto error_free;
5321         }
5322         rc = bnxt_alloc_leds_info(bp);
5323         if (rc)
5324                 goto error_free;
5325
5326         rc = bnxt_alloc_cos_queues(bp);
5327         if (rc)
5328                 goto error_free;
5329
5330         rc = bnxt_init_locks(bp);
5331         if (rc)
5332                 goto error_free;
5333
5334         rc = bnxt_init_resources(bp, false);
5335         if (rc)
5336                 goto error_free;
5337
5338         rc = bnxt_alloc_stats_mem(bp);
5339         if (rc)
5340                 goto error_free;
5341
5342         bnxt_alloc_switch_domain(bp);
5343
5344         PMD_DRV_LOG(INFO,
5345                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5346                     pci_dev->mem_resource[0].phys_addr,
5347                     pci_dev->mem_resource[0].addr);
5348
5349         return 0;
5350
5351 error_free:
5352         bnxt_dev_uninit(eth_dev);
5353         return rc;
5354 }
5355
5356
5357 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5358 {
5359         if (!ctx)
5360                 return;
5361
5362         if (ctx->va)
5363                 rte_free(ctx->va);
5364
5365         ctx->va = NULL;
5366         ctx->dma = RTE_BAD_IOVA;
5367         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5368 }
5369
5370 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5371 {
5372         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5373                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5374                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5375                                   bp->flow_stat->max_fc,
5376                                   false);
5377
5378         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5379                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5380                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5381                                   bp->flow_stat->max_fc,
5382                                   false);
5383
5384         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5385                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5386         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5387
5388         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5389                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5390         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5391
5392         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5393                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5394         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5395
5396         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5397                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5398         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5399 }
5400
5401 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5402 {
5403         bnxt_unregister_fc_ctx_mem(bp);
5404
5405         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5406         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5407         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5408         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5409 }
5410
5411 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5412 {
5413         if (BNXT_FLOW_XSTATS_EN(bp))
5414                 bnxt_uninit_fc_ctx_mem(bp);
5415 }
5416
5417 static void
5418 bnxt_free_error_recovery_info(struct bnxt *bp)
5419 {
5420         rte_free(bp->recovery_info);
5421         bp->recovery_info = NULL;
5422         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5423 }
5424
5425 static int
5426 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5427 {
5428         int rc;
5429
5430         bnxt_free_int(bp);
5431         bnxt_free_mem(bp, reconfig_dev);
5432
5433         bnxt_hwrm_func_buf_unrgtr(bp);
5434         rte_free(bp->pf->vf_req_buf);
5435
5436         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5437         bp->flags &= ~BNXT_FLAG_REGISTERED;
5438         bnxt_free_ctx_mem(bp);
5439         if (!reconfig_dev) {
5440                 bnxt_free_hwrm_resources(bp);
5441                 bnxt_free_error_recovery_info(bp);
5442         }
5443
5444         bnxt_uninit_ctx_mem(bp);
5445
5446         bnxt_free_flow_stats_info(bp);
5447         bnxt_free_rep_info(bp);
5448         rte_free(bp->ptp_cfg);
5449         bp->ptp_cfg = NULL;
5450         return rc;
5451 }
5452
5453 static int
5454 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5455 {
5456         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5457                 return -EPERM;
5458
5459         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5460
5461         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5462                 bnxt_dev_close_op(eth_dev);
5463
5464         return 0;
5465 }
5466
5467 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5468 {
5469         struct bnxt *bp = eth_dev->data->dev_private;
5470         struct rte_eth_dev *vf_rep_eth_dev;
5471         int ret = 0, i;
5472
5473         if (!bp)
5474                 return -EINVAL;
5475
5476         for (i = 0; i < bp->num_reps; i++) {
5477                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5478                 if (!vf_rep_eth_dev)
5479                         continue;
5480                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5481                             vf_rep_eth_dev->data->port_id);
5482                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5483         }
5484         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5485                     eth_dev->data->port_id);
5486         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5487
5488         return ret;
5489 }
5490
5491 static void bnxt_free_rep_info(struct bnxt *bp)
5492 {
5493         rte_free(bp->rep_info);
5494         bp->rep_info = NULL;
5495         rte_free(bp->cfa_code_map);
5496         bp->cfa_code_map = NULL;
5497 }
5498
5499 static int bnxt_init_rep_info(struct bnxt *bp)
5500 {
5501         int i = 0, rc;
5502
5503         if (bp->rep_info)
5504                 return 0;
5505
5506         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5507                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5508                                    0);
5509         if (!bp->rep_info) {
5510                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5511                 return -ENOMEM;
5512         }
5513         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5514                                        sizeof(*bp->cfa_code_map) *
5515                                        BNXT_MAX_CFA_CODE, 0);
5516         if (!bp->cfa_code_map) {
5517                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5518                 bnxt_free_rep_info(bp);
5519                 return -ENOMEM;
5520         }
5521
5522         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5523                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5524
5525         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5526         if (rc) {
5527                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5528                 bnxt_free_rep_info(bp);
5529                 return rc;
5530         }
5531
5532         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5533         if (rc) {
5534                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5535                 bnxt_free_rep_info(bp);
5536                 return rc;
5537         }
5538
5539         return rc;
5540 }
5541
5542 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5543                                struct rte_eth_devargs *eth_da,
5544                                struct rte_eth_dev *backing_eth_dev,
5545                                const char *dev_args)
5546 {
5547         struct rte_eth_dev *vf_rep_eth_dev;
5548         char name[RTE_ETH_NAME_MAX_LEN];
5549         struct bnxt *backing_bp;
5550         uint16_t num_rep;
5551         int i, ret = 0;
5552         struct rte_kvargs *kvlist = NULL;
5553
5554         num_rep = eth_da->nb_representor_ports;
5555         if (num_rep > BNXT_MAX_VF_REPS) {
5556                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5557                             num_rep, BNXT_MAX_VF_REPS);
5558                 return -EINVAL;
5559         }
5560
5561         if (num_rep >= RTE_MAX_ETHPORTS) {
5562                 PMD_DRV_LOG(ERR,
5563                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5564                             num_rep, RTE_MAX_ETHPORTS);
5565                 return -EINVAL;
5566         }
5567
5568         backing_bp = backing_eth_dev->data->dev_private;
5569
5570         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5571                 PMD_DRV_LOG(ERR,
5572                             "Not a PF or trusted VF. No Representor support\n");
5573                 /* Returning an error is not an option.
5574                  * Applications are not handling this correctly
5575                  */
5576                 return 0;
5577         }
5578
5579         if (bnxt_init_rep_info(backing_bp))
5580                 return 0;
5581
5582         for (i = 0; i < num_rep; i++) {
5583                 struct bnxt_representor representor = {
5584                         .vf_id = eth_da->representor_ports[i],
5585                         .switch_domain_id = backing_bp->switch_domain_id,
5586                         .parent_dev = backing_eth_dev
5587                 };
5588
5589                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5590                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5591                                     representor.vf_id, BNXT_MAX_VF_REPS);
5592                         continue;
5593                 }
5594
5595                 /* representor port net_bdf_port */
5596                 snprintf(name, sizeof(name), "net_%s_representor_%d",
5597                          pci_dev->device.name, eth_da->representor_ports[i]);
5598
5599                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5600                 if (kvlist) {
5601                         /*
5602                          * Handler for "rep_is_pf" devarg.
5603                          * Invoked as for ex: "-a 000:00:0d.0,
5604                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5605                          */
5606                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5607                                                  bnxt_parse_devarg_rep_is_pf,
5608                                                  (void *)&representor);
5609                         if (ret) {
5610                                 ret = -EINVAL;
5611                                 goto err;
5612                         }
5613                         /*
5614                          * Handler for "rep_based_pf" devarg.
5615                          * Invoked as for ex: "-a 000:00:0d.0,
5616                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5617                          */
5618                         ret = rte_kvargs_process(kvlist,
5619                                                  BNXT_DEVARG_REP_BASED_PF,
5620                                                  bnxt_parse_devarg_rep_based_pf,
5621                                                  (void *)&representor);
5622                         if (ret) {
5623                                 ret = -EINVAL;
5624                                 goto err;
5625                         }
5626                         /*
5627                          * Handler for "rep_based_pf" devarg.
5628                          * Invoked as for ex: "-a 000:00:0d.0,
5629                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5630                          */
5631                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5632                                                  bnxt_parse_devarg_rep_q_r2f,
5633                                                  (void *)&representor);
5634                         if (ret) {
5635                                 ret = -EINVAL;
5636                                 goto err;
5637                         }
5638                         /*
5639                          * Handler for "rep_based_pf" devarg.
5640                          * Invoked as for ex: "-a 000:00:0d.0,
5641                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5642                          */
5643                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5644                                                  bnxt_parse_devarg_rep_q_f2r,
5645                                                  (void *)&representor);
5646                         if (ret) {
5647                                 ret = -EINVAL;
5648                                 goto err;
5649                         }
5650                         /*
5651                          * Handler for "rep_based_pf" devarg.
5652                          * Invoked as for ex: "-a 000:00:0d.0,
5653                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5654                          */
5655                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5656                                                  bnxt_parse_devarg_rep_fc_r2f,
5657                                                  (void *)&representor);
5658                         if (ret) {
5659                                 ret = -EINVAL;
5660                                 goto err;
5661                         }
5662                         /*
5663                          * Handler for "rep_based_pf" devarg.
5664                          * Invoked as for ex: "-a 000:00:0d.0,
5665                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5666                          */
5667                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5668                                                  bnxt_parse_devarg_rep_fc_f2r,
5669                                                  (void *)&representor);
5670                         if (ret) {
5671                                 ret = -EINVAL;
5672                                 goto err;
5673                         }
5674                 }
5675
5676                 ret = rte_eth_dev_create(&pci_dev->device, name,
5677                                          sizeof(struct bnxt_representor),
5678                                          NULL, NULL,
5679                                          bnxt_representor_init,
5680                                          &representor);
5681                 if (ret) {
5682                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5683                                     "representor %s.", name);
5684                         goto err;
5685                 }
5686
5687                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
5688                 if (!vf_rep_eth_dev) {
5689                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5690                                     " for VF-Rep: %s.", name);
5691                         ret = -ENODEV;
5692                         goto err;
5693                 }
5694
5695                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
5696                             backing_eth_dev->data->port_id);
5697                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5698                                                          vf_rep_eth_dev;
5699                 backing_bp->num_reps++;
5700
5701         }
5702
5703         rte_kvargs_free(kvlist);
5704         return 0;
5705
5706 err:
5707         /* If num_rep > 1, then rollback already created
5708          * ports, since we'll be failing the probe anyway
5709          */
5710         if (num_rep > 1)
5711                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5712         rte_errno = -ret;
5713         rte_kvargs_free(kvlist);
5714
5715         return ret;
5716 }
5717
5718 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5719                           struct rte_pci_device *pci_dev)
5720 {
5721         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5722         struct rte_eth_dev *backing_eth_dev;
5723         uint16_t num_rep;
5724         int ret = 0;
5725
5726         if (pci_dev->device.devargs) {
5727                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5728                                             &eth_da);
5729                 if (ret)
5730                         return ret;
5731         }
5732
5733         num_rep = eth_da.nb_representor_ports;
5734         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5735                     num_rep);
5736
5737         /* We could come here after first level of probe is already invoked
5738          * as part of an application bringup(OVS-DPDK vswitchd), so first check
5739          * for already allocated eth_dev for the backing device (PF/Trusted VF)
5740          */
5741         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5742         if (backing_eth_dev == NULL) {
5743                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5744                                          sizeof(struct bnxt),
5745                                          eth_dev_pci_specific_init, pci_dev,
5746                                          bnxt_dev_init, NULL);
5747
5748                 if (ret || !num_rep)
5749                         return ret;
5750
5751                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5752         }
5753         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
5754                     backing_eth_dev->data->port_id);
5755
5756         if (!num_rep)
5757                 return ret;
5758
5759         /* probe representor ports now */
5760         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
5761                                   pci_dev->device.devargs->args);
5762
5763         return ret;
5764 }
5765
5766 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5767 {
5768         struct rte_eth_dev *eth_dev;
5769
5770         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5771         if (!eth_dev)
5772                 return 0; /* Invoked typically only by OVS-DPDK, by the
5773                            * time it comes here the eth_dev is already
5774                            * deleted by rte_eth_dev_close(), so returning
5775                            * +ve value will at least help in proper cleanup
5776                            */
5777
5778         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
5779         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5780                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5781                         return rte_eth_dev_destroy(eth_dev,
5782                                                    bnxt_representor_uninit);
5783                 else
5784                         return rte_eth_dev_destroy(eth_dev,
5785                                                    bnxt_dev_uninit);
5786         } else {
5787                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5788         }
5789 }
5790
5791 static struct rte_pci_driver bnxt_rte_pmd = {
5792         .id_table = bnxt_pci_id_map,
5793         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5794                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5795                                                   * and OVS-DPDK
5796                                                   */
5797         .probe = bnxt_pci_probe,
5798         .remove = bnxt_pci_remove,
5799 };
5800
5801 static bool
5802 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5803 {
5804         if (strcmp(dev->device->driver->name, drv->driver.name))
5805                 return false;
5806
5807         return true;
5808 }
5809
5810 bool is_bnxt_supported(struct rte_eth_dev *dev)
5811 {
5812         return is_device_supported(dev, &bnxt_rte_pmd);
5813 }
5814
5815 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
5816 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5817 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5818 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");