drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31 #include "bnxt_tf_common.h"
  32 #include "ulp_flow_db.h"
  33
  34 #define DRV_MODULE_NAME         "bnxt"
  35 static const char bnxt_version[] =
  36         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  37
  38 /*
  39  * The set of PCI devices this driver supports
  40  */
  41 static const struct rte_pci_id bnxt_pci_id_map[] = {
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  95         { .vendor_id = 0, /* sentinel */ },
  96 };
  97
  98 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  99 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 101 #define BNXT_DEVARG_REPRESENTOR "representor"
 102
 103 static const char *const bnxt_dev_args[] = {
 104         BNXT_DEVARG_REPRESENTOR,
 105         BNXT_DEVARG_TRUFLOW,
 106         BNXT_DEVARG_FLOW_XSTAT,
 107         BNXT_DEVARG_MAX_NUM_KFLOWS,
 108         NULL
 109 };
 110
 111 /*
 112  * truflow == false to disable the feature
 113  * truflow == true to enable the feature
 114  */
 115 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 116
 117 /*
 118  * flow_xstat == false to disable the feature
 119  * flow_xstat == true to enable the feature
 120  */
 121 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 122
 123 /*
 124  * max_num_kflows must be >= 32
 125  * and must be a power-of-2 supported value
 126  * return: 1 -> invalid
 127  *         0 -> valid
 128  */
 129 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 130 {
 131         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 132                 return 1;
 133         return 0;
 134 }
 135
 136 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 137 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 138 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 139 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 140 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 141 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 142 static void bnxt_dev_recover(void *arg);
 143 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 144 static void bnxt_free_rep_info(struct bnxt *bp);
 145
 146 int is_bnxt_in_error(struct bnxt *bp)
 147 {
 148         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 149                 return -EIO;
 150         if (bp->flags & BNXT_FLAG_FW_RESET)
 151                 return -EBUSY;
 152
 153         return 0;
 154 }
 155
 156 /***********************/
 157
 158 /*
 159  * High level utility functions
 160  */
 161
 162 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 163 {
 164         if (!BNXT_CHIP_THOR(bp))
 165                 return 1;
 166
 167         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 168                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 169                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 170 }
 171
 172 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 173 {
 174         if (!BNXT_CHIP_THOR(bp))
 175                 return HW_HASH_INDEX_SIZE;
 176
 177         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 178 }
 179
 180 static void bnxt_free_parent_info(struct bnxt *bp)
 181 {
 182         rte_free(bp->parent);
 183 }
 184
 185 static void bnxt_free_pf_info(struct bnxt *bp)
 186 {
 187         rte_free(bp->pf);
 188 }
 189
 190 static void bnxt_free_link_info(struct bnxt *bp)
 191 {
 192         rte_free(bp->link_info);
 193 }
 194
 195 static void bnxt_free_leds_info(struct bnxt *bp)
 196 {
 197         if (BNXT_VF(bp))
 198                 return;
 199
 200         rte_free(bp->leds);
 201         bp->leds = NULL;
 202 }
 203
 204 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 205 {
 206         rte_free(bp->flow_stat);
 207         bp->flow_stat = NULL;
 208 }
 209
 210 static void bnxt_free_cos_queues(struct bnxt *bp)
 211 {
 212         rte_free(bp->rx_cos_queue);
 213         rte_free(bp->tx_cos_queue);
 214 }
 215
 216 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 217 {
 218         bnxt_free_filter_mem(bp);
 219         bnxt_free_vnic_attributes(bp);
 220         bnxt_free_vnic_mem(bp);
 221
 222         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 223          * If the number of rings change across fw update,
 224          * we don't have much choice except to warn the user.
 225          */
 226         if (!reconfig) {
 227                 bnxt_free_stats(bp);
 228                 bnxt_free_tx_rings(bp);
 229                 bnxt_free_rx_rings(bp);
 230         }
 231         bnxt_free_async_cp_ring(bp);
 232         bnxt_free_rxtx_nq_ring(bp);
 233
 234         rte_free(bp->grp_info);
 235         bp->grp_info = NULL;
 236 }
 237
 238 static int bnxt_alloc_parent_info(struct bnxt *bp)
 239 {
 240         bp->parent = rte_zmalloc("bnxt_parent_info",
 241                                  sizeof(struct bnxt_parent_info), 0);
 242         if (bp->parent == NULL)
 243                 return -ENOMEM;
 244
 245         return 0;
 246 }
 247
 248 static int bnxt_alloc_pf_info(struct bnxt *bp)
 249 {
 250         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 251         if (bp->pf == NULL)
 252                 return -ENOMEM;
 253
 254         return 0;
 255 }
 256
 257 static int bnxt_alloc_link_info(struct bnxt *bp)
 258 {
 259         bp->link_info =
 260                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 261         if (bp->link_info == NULL)
 262                 return -ENOMEM;
 263
 264         return 0;
 265 }
 266
 267 static int bnxt_alloc_leds_info(struct bnxt *bp)
 268 {
 269         if (BNXT_VF(bp))
 270                 return 0;
 271
 272         bp->leds = rte_zmalloc("bnxt_leds",
 273                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 274                                0);
 275         if (bp->leds == NULL)
 276                 return -ENOMEM;
 277
 278         return 0;
 279 }
 280
 281 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 282 {
 283         bp->rx_cos_queue =
 284                 rte_zmalloc("bnxt_rx_cosq",
 285                             BNXT_COS_QUEUE_COUNT *
 286                             sizeof(struct bnxt_cos_queue_info),
 287                             0);
 288         if (bp->rx_cos_queue == NULL)
 289                 return -ENOMEM;
 290
 291         bp->tx_cos_queue =
 292                 rte_zmalloc("bnxt_tx_cosq",
 293                             BNXT_COS_QUEUE_COUNT *
 294                             sizeof(struct bnxt_cos_queue_info),
 295                             0);
 296         if (bp->tx_cos_queue == NULL)
 297                 return -ENOMEM;
 298
 299         return 0;
 300 }
 301
 302 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 303 {
 304         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 305                                     sizeof(struct bnxt_flow_stat_info), 0);
 306         if (bp->flow_stat == NULL)
 307                 return -ENOMEM;
 308
 309         return 0;
 310 }
 311
 312 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 313 {
 314         int rc;
 315
 316         rc = bnxt_alloc_ring_grps(bp);
 317         if (rc)
 318                 goto alloc_mem_err;
 319
 320         rc = bnxt_alloc_async_ring_struct(bp);
 321         if (rc)
 322                 goto alloc_mem_err;
 323
 324         rc = bnxt_alloc_vnic_mem(bp);
 325         if (rc)
 326                 goto alloc_mem_err;
 327
 328         rc = bnxt_alloc_vnic_attributes(bp);
 329         if (rc)
 330                 goto alloc_mem_err;
 331
 332         rc = bnxt_alloc_filter_mem(bp);
 333         if (rc)
 334                 goto alloc_mem_err;
 335
 336         rc = bnxt_alloc_async_cp_ring(bp);
 337         if (rc)
 338                 goto alloc_mem_err;
 339
 340         rc = bnxt_alloc_rxtx_nq_ring(bp);
 341         if (rc)
 342                 goto alloc_mem_err;
 343
 344         if (BNXT_FLOW_XSTATS_EN(bp)) {
 345                 rc = bnxt_alloc_flow_stats_info(bp);
 346                 if (rc)
 347                         goto alloc_mem_err;
 348         }
 349
 350         return 0;
 351
 352 alloc_mem_err:
 353         bnxt_free_mem(bp, reconfig);
 354         return rc;
 355 }
 356
 357 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 358 {
 359         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 360         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 361         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 362         struct bnxt_rx_queue *rxq;
 363         unsigned int j;
 364         int rc;
 365
 366         rc = bnxt_vnic_grp_alloc(bp, vnic);
 367         if (rc)
 368                 goto err_out;
 369
 370         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 371                     vnic_id, vnic, vnic->fw_grp_ids);
 372
 373         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 374         if (rc)
 375                 goto err_out;
 376
 377         /* Alloc RSS context only if RSS mode is enabled */
 378         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 379                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 380
 381                 rc = 0;
 382                 for (j = 0; j < nr_ctxs; j++) {
 383                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 384                         if (rc)
 385                                 break;
 386                 }
 387                 if (rc) {
 388                         PMD_DRV_LOG(ERR,
 389                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 390                                     vnic_id, j, rc);
 391                         goto err_out;
 392                 }
 393                 vnic->num_lb_ctxts = nr_ctxs;
 394         }
 395
 396         /*
 397          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 398          * setting is not available at this time, it will not be
 399          * configured correctly in the CFA.
 400          */
 401         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 402                 vnic->vlan_strip = true;
 403         else
 404                 vnic->vlan_strip = false;
 405
 406         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 407         if (rc)
 408                 goto err_out;
 409
 410         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 411         if (rc)
 412                 goto err_out;
 413
 414         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 415                 rxq = bp->eth_dev->data->rx_queues[j];
 416
 417                 PMD_DRV_LOG(DEBUG,
 418                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 419                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 420
 421                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 422                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 423                 else
 424                         vnic->rx_queue_cnt++;
 425         }
 426
 427         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 428
 429         rc = bnxt_vnic_rss_configure(bp, vnic);
 430         if (rc)
 431                 goto err_out;
 432
 433         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 434
 435         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 436                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 437         else
 438                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 439
 440         return 0;
 441 err_out:
 442         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 443                     vnic_id, rc);
 444         return rc;
 445 }
 446
 447 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 448 {
 449         int rc = 0;
 450
 451         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 452                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 453         if (rc)
 454                 return rc;
 455
 456         PMD_DRV_LOG(DEBUG,
 457                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 458                     " rx_fc_in_tbl.ctx_id = %d\n",
 459                     bp->flow_stat->rx_fc_in_tbl.va,
 460                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 461                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 462
 463         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 464                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 465         if (rc)
 466                 return rc;
 467
 468         PMD_DRV_LOG(DEBUG,
 469                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 470                     " rx_fc_out_tbl.ctx_id = %d\n",
 471                     bp->flow_stat->rx_fc_out_tbl.va,
 472                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 473                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 474
 475         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 476                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 477         if (rc)
 478                 return rc;
 479
 480         PMD_DRV_LOG(DEBUG,
 481                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 482                     " tx_fc_in_tbl.ctx_id = %d\n",
 483                     bp->flow_stat->tx_fc_in_tbl.va,
 484                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 485                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 486
 487         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 488                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 489         if (rc)
 490                 return rc;
 491
 492         PMD_DRV_LOG(DEBUG,
 493                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 494                     " tx_fc_out_tbl.ctx_id = %d\n",
 495                     bp->flow_stat->tx_fc_out_tbl.va,
 496                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 497                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 498
 499         memset(bp->flow_stat->rx_fc_out_tbl.va,
 500                0,
 501                bp->flow_stat->rx_fc_out_tbl.size);
 502         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 503                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 504                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 505                                        bp->flow_stat->max_fc,
 506                                        true);
 507         if (rc)
 508                 return rc;
 509
 510         memset(bp->flow_stat->tx_fc_out_tbl.va,
 511                0,
 512                bp->flow_stat->tx_fc_out_tbl.size);
 513         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 514                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 515                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 516                                        bp->flow_stat->max_fc,
 517                                        true);
 518
 519         return rc;
 520 }
 521
 522 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 523                                   struct bnxt_ctx_mem_buf_info *ctx)
 524 {
 525         if (!ctx)
 526                 return -EINVAL;
 527
 528         ctx->va = rte_zmalloc(type, size, 0);
 529         if (ctx->va == NULL)
 530                 return -ENOMEM;
 531         rte_mem_lock_page(ctx->va);
 532         ctx->size = size;
 533         ctx->dma = rte_mem_virt2iova(ctx->va);
 534         if (ctx->dma == RTE_BAD_IOVA)
 535                 return -ENOMEM;
 536
 537         return 0;
 538 }
 539
 540 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 541 {
 542         struct rte_pci_device *pdev = bp->pdev;
 543         char type[RTE_MEMZONE_NAMESIZE];
 544         uint16_t max_fc;
 545         int rc = 0;
 546
 547         max_fc = bp->flow_stat->max_fc;
 548
 549         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 550                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 551         /* 4 bytes for each counter-id */
 552         rc = bnxt_alloc_ctx_mem_buf(type,
 553                                     max_fc * 4,
 554                                     &bp->flow_stat->rx_fc_in_tbl);
 555         if (rc)
 556                 return rc;
 557
 558         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 559                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 560         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 561         rc = bnxt_alloc_ctx_mem_buf(type,
 562                                     max_fc * 16,
 563                                     &bp->flow_stat->rx_fc_out_tbl);
 564         if (rc)
 565                 return rc;
 566
 567         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 568                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 569         /* 4 bytes for each counter-id */
 570         rc = bnxt_alloc_ctx_mem_buf(type,
 571                                     max_fc * 4,
 572                                     &bp->flow_stat->tx_fc_in_tbl);
 573         if (rc)
 574                 return rc;
 575
 576         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 577                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 578         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 579         rc = bnxt_alloc_ctx_mem_buf(type,
 580                                     max_fc * 16,
 581                                     &bp->flow_stat->tx_fc_out_tbl);
 582         if (rc)
 583                 return rc;
 584
 585         rc = bnxt_register_fc_ctx_mem(bp);
 586
 587         return rc;
 588 }
 589
 590 static int bnxt_init_ctx_mem(struct bnxt *bp)
 591 {
 592         int rc = 0;
 593
 594         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 595             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 596             !BNXT_FLOW_XSTATS_EN(bp))
 597                 return 0;
 598
 599         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 600         if (rc)
 601                 return rc;
 602
 603         rc = bnxt_init_fc_ctx_mem(bp);
 604
 605         return rc;
 606 }
 607
 608 static int bnxt_init_chip(struct bnxt *bp)
 609 {
 610         struct rte_eth_link new;
 611         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 612         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 613         uint32_t intr_vector = 0;
 614         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 615         uint32_t vec = BNXT_MISC_VEC_ID;
 616         unsigned int i, j;
 617         int rc;
 618
 619         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 620                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 621                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 622                 bp->flags |= BNXT_FLAG_JUMBO;
 623         } else {
 624                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 625                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 626                 bp->flags &= ~BNXT_FLAG_JUMBO;
 627         }
 628
 629         /* THOR does not support ring groups.
 630          * But we will use the array to save RSS context IDs.
 631          */
 632         if (BNXT_CHIP_THOR(bp))
 633                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 634
 635         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 636         if (rc) {
 637                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 638                 goto err_out;
 639         }
 640
 641         rc = bnxt_alloc_hwrm_rings(bp);
 642         if (rc) {
 643                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 644                 goto err_out;
 645         }
 646
 647         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 648         if (rc) {
 649                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 650                 goto err_out;
 651         }
 652
 653         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 654                 goto skip_cosq_cfg;
 655
 656         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 657                 if (bp->rx_cos_queue[i].id != 0xff) {
 658                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 659
 660                         if (!vnic) {
 661                                 PMD_DRV_LOG(ERR,
 662                                             "Num pools more than FW profile\n");
 663                                 rc = -EINVAL;
 664                                 goto err_out;
 665                         }
 666                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 667                         bp->rx_cosq_cnt++;
 668                 }
 669         }
 670
 671 skip_cosq_cfg:
 672         rc = bnxt_mq_rx_configure(bp);
 673         if (rc) {
 674                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 675                 goto err_out;
 676         }
 677
 678         /* VNIC configuration */
 679         for (i = 0; i < bp->nr_vnics; i++) {
 680                 rc = bnxt_setup_one_vnic(bp, i);
 681                 if (rc)
 682                         goto err_out;
 683         }
 684
 685         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 686         if (rc) {
 687                 PMD_DRV_LOG(ERR,
 688                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 689                 goto err_out;
 690         }
 691
 692         /* check and configure queue intr-vector mapping */
 693         if ((rte_intr_cap_multiple(intr_handle) ||
 694              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 695             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 696                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 697                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 698                 if (intr_vector > bp->rx_cp_nr_rings) {
 699                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 700                                         bp->rx_cp_nr_rings);
 701                         return -ENOTSUP;
 702                 }
 703                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 704                 if (rc)
 705                         return rc;
 706         }
 707
 708         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 709                 intr_handle->intr_vec =
 710                         rte_zmalloc("intr_vec",
 711                                     bp->eth_dev->data->nb_rx_queues *
 712                                     sizeof(int), 0);
 713                 if (intr_handle->intr_vec == NULL) {
 714                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 715                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 716                         rc = -ENOMEM;
 717                         goto err_disable;
 718                 }
 719                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 720                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 721                          intr_handle->intr_vec, intr_handle->nb_efd,
 722                         intr_handle->max_intr);
 723                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 724                      queue_id++) {
 725                         intr_handle->intr_vec[queue_id] =
 726                                                         vec + BNXT_RX_VEC_START;
 727                         if (vec < base + intr_handle->nb_efd - 1)
 728                                 vec++;
 729                 }
 730         }
 731
 732         /* enable uio/vfio intr/eventfd mapping */
 733         rc = rte_intr_enable(intr_handle);
 734 #ifndef RTE_EXEC_ENV_FREEBSD
 735         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 736         if (rc)
 737                 goto err_free;
 738 #endif
 739
 740         rc = bnxt_get_hwrm_link_config(bp, &new);
 741         if (rc) {
 742                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 743                 goto err_free;
 744         }
 745
 746         if (!bp->link_info->link_up) {
 747                 rc = bnxt_set_hwrm_link_config(bp, true);
 748                 if (rc) {
 749                         PMD_DRV_LOG(ERR,
 750                                 "HWRM link config failure rc: %x\n", rc);
 751                         goto err_free;
 752                 }
 753         }
 754         bnxt_print_link_info(bp->eth_dev);
 755
 756         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 757         if (!bp->mark_table)
 758                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 759
 760         return 0;
 761
 762 err_free:
 763         rte_free(intr_handle->intr_vec);
 764 err_disable:
 765         rte_intr_efd_disable(intr_handle);
 766 err_out:
 767         /* Some of the error status returned by FW may not be from errno.h */
 768         if (rc > 0)
 769                 rc = -EIO;
 770
 771         return rc;
 772 }
 773
 774 static int bnxt_shutdown_nic(struct bnxt *bp)
 775 {
 776         bnxt_free_all_hwrm_resources(bp);
 777         bnxt_free_all_filters(bp);
 778         bnxt_free_all_vnics(bp);
 779         return 0;
 780 }
 781
 782 /*
 783  * Device configuration and status function
 784  */
 785
 786 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 787 {
 788         uint32_t link_speed = bp->link_info->support_speeds;
 789         uint32_t speed_capa = 0;
 790
 791         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 792                 speed_capa |= ETH_LINK_SPEED_100M;
 793         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 794                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 795         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 796                 speed_capa |= ETH_LINK_SPEED_1G;
 797         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 798                 speed_capa |= ETH_LINK_SPEED_2_5G;
 799         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 800                 speed_capa |= ETH_LINK_SPEED_10G;
 801         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 802                 speed_capa |= ETH_LINK_SPEED_20G;
 803         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 804                 speed_capa |= ETH_LINK_SPEED_25G;
 805         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 806                 speed_capa |= ETH_LINK_SPEED_40G;
 807         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 808                 speed_capa |= ETH_LINK_SPEED_50G;
 809         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 810                 speed_capa |= ETH_LINK_SPEED_100G;
 811         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
 812                 speed_capa |= ETH_LINK_SPEED_200G;
 813
 814         if (bp->link_info->auto_mode ==
 815             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 816                 speed_capa |= ETH_LINK_SPEED_FIXED;
 817         else
 818                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 819
 820         return speed_capa;
 821 }
 822
 823 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 824                                 struct rte_eth_dev_info *dev_info)
 825 {
 826         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 827         struct bnxt *bp = eth_dev->data->dev_private;
 828         uint16_t max_vnics, i, j, vpool, vrxq;
 829         unsigned int max_rx_rings;
 830         int rc;
 831
 832         rc = is_bnxt_in_error(bp);
 833         if (rc)
 834                 return rc;
 835
 836         /* MAC Specifics */
 837         dev_info->max_mac_addrs = bp->max_l2_ctx;
 838         dev_info->max_hash_mac_addrs = 0;
 839
 840         /* PF/VF specifics */
 841         if (BNXT_PF(bp))
 842                 dev_info->max_vfs = pdev->max_vfs;
 843
 844         max_rx_rings = BNXT_MAX_RINGS(bp);
 845         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 846         dev_info->max_rx_queues = max_rx_rings;
 847         dev_info->max_tx_queues = max_rx_rings;
 848         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 849         dev_info->hash_key_size = 40;
 850         max_vnics = bp->max_vnics;
 851
 852         /* MTU specifics */
 853         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 854         dev_info->max_mtu = BNXT_MAX_MTU;
 855
 856         /* Fast path specifics */
 857         dev_info->min_rx_bufsize = 1;
 858         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 859
 860         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 861         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 862                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 863         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 864         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 865
 866         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 867
 868         /* *INDENT-OFF* */
 869         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 870                 .rx_thresh = {
 871                         .pthresh = 8,
 872                         .hthresh = 8,
 873                         .wthresh = 0,
 874                 },
 875                 .rx_free_thresh = 32,
 876                 /* If no descriptors available, pkts are dropped by default */
 877                 .rx_drop_en = 1,
 878         };
 879
 880         dev_info->default_txconf = (struct rte_eth_txconf) {
 881                 .tx_thresh = {
 882                         .pthresh = 32,
 883                         .hthresh = 0,
 884                         .wthresh = 0,
 885                 },
 886                 .tx_free_thresh = 32,
 887                 .tx_rs_thresh = 32,
 888         };
 889         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 890
 891         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 892         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 893         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 894         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 895         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 896
 897         /* *INDENT-ON* */
 898
 899         /*
 900          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 901          *       need further investigation.
 902          */
 903
 904         /* VMDq resources */
 905         vpool = 64; /* ETH_64_POOLS */
 906         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 907         for (i = 0; i < 4; vpool >>= 1, i++) {
 908                 if (max_vnics > vpool) {
 909                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 910                                 if (dev_info->max_rx_queues > vrxq) {
 911                                         if (vpool > vrxq)
 912                                                 vpool = vrxq;
 913                                         goto found;
 914                                 }
 915                         }
 916                         /* Not enough resources to support VMDq */
 917                         break;
 918                 }
 919         }
 920         /* Not enough resources to support VMDq */
 921         vpool = 0;
 922         vrxq = 0;
 923 found:
 924         dev_info->max_vmdq_pools = vpool;
 925         dev_info->vmdq_queue_num = vrxq;
 926
 927         dev_info->vmdq_pool_base = 0;
 928         dev_info->vmdq_queue_base = 0;
 929
 930         return 0;
 931 }
 932
 933 /* Configure the device based on the configuration provided */
 934 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 935 {
 936         struct bnxt *bp = eth_dev->data->dev_private;
 937         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 938         int rc;
 939
 940         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 941         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 942         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 943         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 944
 945         rc = is_bnxt_in_error(bp);
 946         if (rc)
 947                 return rc;
 948
 949         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 950                 rc = bnxt_hwrm_check_vf_rings(bp);
 951                 if (rc) {
 952                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 953                         return -ENOSPC;
 954                 }
 955
 956                 /* If a resource has already been allocated - in this case
 957                  * it is the async completion ring, free it. Reallocate it after
 958                  * resource reservation. This will ensure the resource counts
 959                  * are calculated correctly.
 960                  */
 961
 962                 pthread_mutex_lock(&bp->def_cp_lock);
 963
 964                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 965                         bnxt_disable_int(bp);
 966                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 967                 }
 968
 969                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 970                 if (rc) {
 971                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 972                         pthread_mutex_unlock(&bp->def_cp_lock);
 973                         return -ENOSPC;
 974                 }
 975
 976                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 977                         rc = bnxt_alloc_async_cp_ring(bp);
 978                         if (rc) {
 979                                 pthread_mutex_unlock(&bp->def_cp_lock);
 980                                 return rc;
 981                         }
 982                         bnxt_enable_int(bp);
 983                 }
 984
 985                 pthread_mutex_unlock(&bp->def_cp_lock);
 986         } else {
 987                 /* legacy driver needs to get updated values */
 988                 rc = bnxt_hwrm_func_qcaps(bp);
 989                 if (rc) {
 990                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 991                         return rc;
 992                 }
 993         }
 994
 995         /* Inherit new configurations */
 996         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 997             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 998             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 999                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1000             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1001             bp->max_stat_ctx)
1002                 goto resource_error;
1003
1004         if (BNXT_HAS_RING_GRPS(bp) &&
1005             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1006                 goto resource_error;
1007
1008         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1009             bp->max_vnics < eth_dev->data->nb_rx_queues)
1010                 goto resource_error;
1011
1012         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1013         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1014
1015         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1016                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1017         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1018
1019         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1020                 eth_dev->data->mtu =
1021                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1022                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1023                         BNXT_NUM_VLANS;
1024                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1025         }
1026         return 0;
1027
1028 resource_error:
1029         PMD_DRV_LOG(ERR,
1030                     "Insufficient resources to support requested config\n");
1031         PMD_DRV_LOG(ERR,
1032                     "Num Queues Requested: Tx %d, Rx %d\n",
1033                     eth_dev->data->nb_tx_queues,
1034                     eth_dev->data->nb_rx_queues);
1035         PMD_DRV_LOG(ERR,
1036                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1037                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1038                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1039         return -ENOSPC;
1040 }
1041
1042 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1043 {
1044         struct rte_eth_link *link = &eth_dev->data->dev_link;
1045
1046         if (link->link_status)
1047                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1048                         eth_dev->data->port_id,
1049                         (uint32_t)link->link_speed,
1050                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1051                         ("full-duplex") : ("half-duplex\n"));
1052         else
1053                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1054                         eth_dev->data->port_id);
1055 }
1056
1057 /*
1058  * Determine whether the current configuration requires support for scattered
1059  * receive; return 1 if scattered receive is required and 0 if not.
1060  */
1061 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1062 {
1063         uint16_t buf_size;
1064         int i;
1065
1066         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1067                 return 1;
1068
1069         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1070                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1071
1072                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1073                                       RTE_PKTMBUF_HEADROOM);
1074                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1075                         return 1;
1076         }
1077         return 0;
1078 }
1079
1080 static eth_rx_burst_t
1081 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1082 {
1083         struct bnxt *bp = eth_dev->data->dev_private;
1084
1085 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1086 #ifndef RTE_LIBRTE_IEEE1588
1087         /*
1088          * Vector mode receive can be enabled only if scatter rx is not
1089          * in use and rx offloads are limited to VLAN stripping and
1090          * CRC stripping.
1091          */
1092         if (!eth_dev->data->scattered_rx &&
1093             !(eth_dev->data->dev_conf.rxmode.offloads &
1094               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1095                 DEV_RX_OFFLOAD_KEEP_CRC |
1096                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1097                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1098                 DEV_RX_OFFLOAD_UDP_CKSUM |
1099                 DEV_RX_OFFLOAD_TCP_CKSUM |
1100                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1101                 DEV_RX_OFFLOAD_RSS_HASH |
1102                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1103             !BNXT_TRUFLOW_EN(bp)) {
1104                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1105                             eth_dev->data->port_id);
1106                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1107                 return bnxt_recv_pkts_vec;
1108         }
1109         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1110                     eth_dev->data->port_id);
1111         PMD_DRV_LOG(INFO,
1112                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1113                     eth_dev->data->port_id,
1114                     eth_dev->data->scattered_rx,
1115                     eth_dev->data->dev_conf.rxmode.offloads);
1116 #endif
1117 #endif
1118         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1119         return bnxt_recv_pkts;
1120 }
1121
1122 static eth_tx_burst_t
1123 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1124 {
1125 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1126 #ifndef RTE_LIBRTE_IEEE1588
1127         struct bnxt *bp = eth_dev->data->dev_private;
1128
1129         /*
1130          * Vector mode transmit can be enabled only if not using scatter rx
1131          * or tx offloads.
1132          */
1133         if (!eth_dev->data->scattered_rx &&
1134             !eth_dev->data->dev_conf.txmode.offloads &&
1135             !BNXT_TRUFLOW_EN(bp)) {
1136                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1137                             eth_dev->data->port_id);
1138                 return bnxt_xmit_pkts_vec;
1139         }
1140         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1141                     eth_dev->data->port_id);
1142         PMD_DRV_LOG(INFO,
1143                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1144                     eth_dev->data->port_id,
1145                     eth_dev->data->scattered_rx,
1146                     eth_dev->data->dev_conf.txmode.offloads);
1147 #endif
1148 #endif
1149         return bnxt_xmit_pkts;
1150 }
1151
1152 static int bnxt_handle_if_change_status(struct bnxt *bp)
1153 {
1154         int rc;
1155
1156         /* Since fw has undergone a reset and lost all contexts,
1157          * set fatal flag to not issue hwrm during cleanup
1158          */
1159         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1160         bnxt_uninit_resources(bp, true);
1161
1162         /* clear fatal flag so that re-init happens */
1163         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1164         rc = bnxt_init_resources(bp, true);
1165
1166         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1167
1168         return rc;
1169 }
1170
1171 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1172 {
1173         struct bnxt *bp = eth_dev->data->dev_private;
1174         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1175         int vlan_mask = 0;
1176         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1177
1178         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1179                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1180                 return -EINVAL;
1181         }
1182
1183         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1184                 PMD_DRV_LOG(ERR,
1185                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1186                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1187         }
1188
1189         do {
1190                 rc = bnxt_hwrm_if_change(bp, true);
1191                 if (rc == 0 || rc != -EAGAIN)
1192                         break;
1193
1194                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1195         } while (retry_cnt--);
1196
1197         if (rc)
1198                 return rc;
1199
1200         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1201                 rc = bnxt_handle_if_change_status(bp);
1202                 if (rc)
1203                         return rc;
1204         }
1205
1206         bnxt_enable_int(bp);
1207
1208         rc = bnxt_init_chip(bp);
1209         if (rc)
1210                 goto error;
1211
1212         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1213         eth_dev->data->dev_started = 1;
1214
1215         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1216
1217         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1218                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1219         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1220                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1221         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1222         if (rc)
1223                 goto error;
1224
1225         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1226         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1227
1228         pthread_mutex_lock(&bp->def_cp_lock);
1229         bnxt_schedule_fw_health_check(bp);
1230         pthread_mutex_unlock(&bp->def_cp_lock);
1231
1232         bnxt_ulp_init(bp);
1233
1234         return 0;
1235
1236 error:
1237         bnxt_shutdown_nic(bp);
1238         bnxt_free_tx_mbufs(bp);
1239         bnxt_free_rx_mbufs(bp);
1240         bnxt_hwrm_if_change(bp, false);
1241         eth_dev->data->dev_started = 0;
1242         return rc;
1243 }
1244
1245 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1246 {
1247         struct bnxt *bp = eth_dev->data->dev_private;
1248         int rc = 0;
1249
1250         if (!bp->link_info->link_up)
1251                 rc = bnxt_set_hwrm_link_config(bp, true);
1252         if (!rc)
1253                 eth_dev->data->dev_link.link_status = 1;
1254
1255         bnxt_print_link_info(eth_dev);
1256         return rc;
1257 }
1258
1259 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1260 {
1261         struct bnxt *bp = eth_dev->data->dev_private;
1262
1263         eth_dev->data->dev_link.link_status = 0;
1264         bnxt_set_hwrm_link_config(bp, false);
1265         bp->link_info->link_up = 0;
1266
1267         return 0;
1268 }
1269
1270 static void bnxt_free_switch_domain(struct bnxt *bp)
1271 {
1272         if (bp->switch_domain_id)
1273                 rte_eth_switch_domain_free(bp->switch_domain_id);
1274 }
1275
1276 /* Unload the driver, release resources */
1277 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1278 {
1279         struct bnxt *bp = eth_dev->data->dev_private;
1280         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1281         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1282
1283         eth_dev->data->dev_started = 0;
1284         /* Prevent crashes when queues are still in use */
1285         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1286         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1287
1288         bnxt_disable_int(bp);
1289
1290         /* disable uio/vfio intr/eventfd mapping */
1291         rte_intr_disable(intr_handle);
1292
1293         bnxt_ulp_destroy_df_rules(bp, false);
1294         bnxt_ulp_deinit(bp);
1295
1296         bnxt_cancel_fw_health_check(bp);
1297
1298         bnxt_dev_set_link_down_op(eth_dev);
1299
1300         /* Wait for link to be reset and the async notification to process.
1301          * During reset recovery, there is no need to wait and
1302          * VF/NPAR functions do not have privilege to change PHY config.
1303          */
1304         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1305                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1306
1307         /* Clean queue intr-vector mapping */
1308         rte_intr_efd_disable(intr_handle);
1309         if (intr_handle->intr_vec != NULL) {
1310                 rte_free(intr_handle->intr_vec);
1311                 intr_handle->intr_vec = NULL;
1312         }
1313
1314         bnxt_hwrm_port_clr_stats(bp);
1315         bnxt_free_tx_mbufs(bp);
1316         bnxt_free_rx_mbufs(bp);
1317         /* Process any remaining notifications in default completion queue */
1318         bnxt_int_handler(eth_dev);
1319         bnxt_shutdown_nic(bp);
1320         bnxt_hwrm_if_change(bp, false);
1321
1322         rte_free(bp->mark_table);
1323         bp->mark_table = NULL;
1324
1325         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1326         bp->rx_cosq_cnt = 0;
1327         /* All filters are deleted on a port stop. */
1328         if (BNXT_FLOW_XSTATS_EN(bp))
1329                 bp->flow_stat->flow_count = 0;
1330 }
1331
1332 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1333 {
1334         struct bnxt *bp = eth_dev->data->dev_private;
1335
1336         /* cancel the recovery handler before remove dev */
1337         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1338         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1339         bnxt_cancel_fc_thread(bp);
1340
1341         if (eth_dev->data->dev_started)
1342                 bnxt_dev_stop_op(eth_dev);
1343
1344         bnxt_free_switch_domain(bp);
1345
1346         bnxt_uninit_resources(bp, false);
1347
1348         bnxt_free_leds_info(bp);
1349         bnxt_free_cos_queues(bp);
1350         bnxt_free_link_info(bp);
1351         bnxt_free_pf_info(bp);
1352         bnxt_free_parent_info(bp);
1353
1354         eth_dev->dev_ops = NULL;
1355         eth_dev->rx_pkt_burst = NULL;
1356         eth_dev->tx_pkt_burst = NULL;
1357
1358         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1359         bp->tx_mem_zone = NULL;
1360         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1361         bp->rx_mem_zone = NULL;
1362
1363         bnxt_hwrm_free_vf_info(bp);
1364
1365         rte_free(bp->grp_info);
1366         bp->grp_info = NULL;
1367 }
1368
1369 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1370                                     uint32_t index)
1371 {
1372         struct bnxt *bp = eth_dev->data->dev_private;
1373         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1374         struct bnxt_vnic_info *vnic;
1375         struct bnxt_filter_info *filter, *temp_filter;
1376         uint32_t i;
1377
1378         if (is_bnxt_in_error(bp))
1379                 return;
1380
1381         /*
1382          * Loop through all VNICs from the specified filter flow pools to
1383          * remove the corresponding MAC addr filter
1384          */
1385         for (i = 0; i < bp->nr_vnics; i++) {
1386                 if (!(pool_mask & (1ULL << i)))
1387                         continue;
1388
1389                 vnic = &bp->vnic_info[i];
1390                 filter = STAILQ_FIRST(&vnic->filter);
1391                 while (filter) {
1392                         temp_filter = STAILQ_NEXT(filter, next);
1393                         if (filter->mac_index == index) {
1394                                 STAILQ_REMOVE(&vnic->filter, filter,
1395                                                 bnxt_filter_info, next);
1396                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1397                                 bnxt_free_filter(bp, filter);
1398                         }
1399                         filter = temp_filter;
1400                 }
1401         }
1402 }
1403
1404 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1405                                struct rte_ether_addr *mac_addr, uint32_t index,
1406                                uint32_t pool)
1407 {
1408         struct bnxt_filter_info *filter;
1409         int rc = 0;
1410
1411         /* Attach requested MAC address to the new l2_filter */
1412         STAILQ_FOREACH(filter, &vnic->filter, next) {
1413                 if (filter->mac_index == index) {
1414                         PMD_DRV_LOG(DEBUG,
1415                                     "MAC addr already existed for pool %d\n",
1416                                     pool);
1417                         return 0;
1418                 }
1419         }
1420
1421         filter = bnxt_alloc_filter(bp);
1422         if (!filter) {
1423                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1424                 return -ENODEV;
1425         }
1426
1427         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1428          * if the MAC that's been programmed now is a different one, then,
1429          * copy that addr to filter->l2_addr
1430          */
1431         if (mac_addr)
1432                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1433         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1434
1435         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1436         if (!rc) {
1437                 filter->mac_index = index;
1438                 if (filter->mac_index == 0)
1439                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1440                 else
1441                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1442         } else {
1443                 bnxt_free_filter(bp, filter);
1444         }
1445
1446         return rc;
1447 }
1448
1449 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1450                                 struct rte_ether_addr *mac_addr,
1451                                 uint32_t index, uint32_t pool)
1452 {
1453         struct bnxt *bp = eth_dev->data->dev_private;
1454         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1455         int rc = 0;
1456
1457         rc = is_bnxt_in_error(bp);
1458         if (rc)
1459                 return rc;
1460
1461         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1462                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1463                 return -ENOTSUP;
1464         }
1465
1466         if (!vnic) {
1467                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1468                 return -EINVAL;
1469         }
1470
1471         /* Filter settings will get applied when port is started */
1472         if (!eth_dev->data->dev_started)
1473                 return 0;
1474
1475         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1476
1477         return rc;
1478 }
1479
1480 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1481                      bool exp_link_status)
1482 {
1483         int rc = 0;
1484         struct bnxt *bp = eth_dev->data->dev_private;
1485         struct rte_eth_link new;
1486         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1487                   BNXT_LINK_DOWN_WAIT_CNT;
1488
1489         rc = is_bnxt_in_error(bp);
1490         if (rc)
1491                 return rc;
1492
1493         memset(&new, 0, sizeof(new));
1494         do {
1495                 /* Retrieve link info from hardware */
1496                 rc = bnxt_get_hwrm_link_config(bp, &new);
1497                 if (rc) {
1498                         new.link_speed = ETH_LINK_SPEED_100M;
1499                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1500                         PMD_DRV_LOG(ERR,
1501                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1502                         goto out;
1503                 }
1504
1505                 if (!wait_to_complete || new.link_status == exp_link_status)
1506                         break;
1507
1508                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1509         } while (cnt--);
1510
1511 out:
1512         /* Timed out or success */
1513         if (new.link_status != eth_dev->data->dev_link.link_status ||
1514         new.link_speed != eth_dev->data->dev_link.link_speed) {
1515                 rte_eth_linkstatus_set(eth_dev, &new);
1516
1517                 _rte_eth_dev_callback_process(eth_dev,
1518                                               RTE_ETH_EVENT_INTR_LSC,
1519                                               NULL);
1520
1521                 bnxt_print_link_info(eth_dev);
1522         }
1523
1524         return rc;
1525 }
1526
1527 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1528                         int wait_to_complete)
1529 {
1530         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1531 }
1532
1533 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1534 {
1535         struct bnxt *bp = eth_dev->data->dev_private;
1536         struct bnxt_vnic_info *vnic;
1537         uint32_t old_flags;
1538         int rc;
1539
1540         rc = is_bnxt_in_error(bp);
1541         if (rc)
1542                 return rc;
1543
1544         /* Filter settings will get applied when port is started */
1545         if (!eth_dev->data->dev_started)
1546                 return 0;
1547
1548         if (bp->vnic_info == NULL)
1549                 return 0;
1550
1551         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1552
1553         old_flags = vnic->flags;
1554         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1555         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1556         if (rc != 0)
1557                 vnic->flags = old_flags;
1558
1559         return rc;
1560 }
1561
1562 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1563 {
1564         struct bnxt *bp = eth_dev->data->dev_private;
1565         struct bnxt_vnic_info *vnic;
1566         uint32_t old_flags;
1567         int rc;
1568
1569         rc = is_bnxt_in_error(bp);
1570         if (rc)
1571                 return rc;
1572
1573         /* Filter settings will get applied when port is started */
1574         if (!eth_dev->data->dev_started)
1575                 return 0;
1576
1577         if (bp->vnic_info == NULL)
1578                 return 0;
1579
1580         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1581
1582         old_flags = vnic->flags;
1583         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1584         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1585         if (rc != 0)
1586                 vnic->flags = old_flags;
1587
1588         bnxt_ulp_create_df_rules(bp);
1589
1590         return rc;
1591 }
1592
1593 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1594 {
1595         struct bnxt *bp = eth_dev->data->dev_private;
1596         struct bnxt_vnic_info *vnic;
1597         uint32_t old_flags;
1598         int rc;
1599
1600         rc = is_bnxt_in_error(bp);
1601         if (rc)
1602                 return rc;
1603
1604         /* Filter settings will get applied when port is started */
1605         if (!eth_dev->data->dev_started)
1606                 return 0;
1607
1608         if (bp->vnic_info == NULL)
1609                 return 0;
1610
1611         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1612
1613         old_flags = vnic->flags;
1614         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1615         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1616         if (rc != 0)
1617                 vnic->flags = old_flags;
1618
1619         return rc;
1620 }
1621
1622 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1623 {
1624         struct bnxt *bp = eth_dev->data->dev_private;
1625         struct bnxt_vnic_info *vnic;
1626         uint32_t old_flags;
1627         int rc;
1628
1629         rc = is_bnxt_in_error(bp);
1630         if (rc)
1631                 return rc;
1632
1633         /* Filter settings will get applied when port is started */
1634         if (!eth_dev->data->dev_started)
1635                 return 0;
1636
1637         if (bp->vnic_info == NULL)
1638                 return 0;
1639
1640         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1641
1642         old_flags = vnic->flags;
1643         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1644         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1645         if (rc != 0)
1646                 vnic->flags = old_flags;
1647
1648         return rc;
1649 }
1650
1651 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1652 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1653 {
1654         if (qid >= bp->rx_nr_rings)
1655                 return NULL;
1656
1657         return bp->eth_dev->data->rx_queues[qid];
1658 }
1659
1660 /* Return rxq corresponding to a given rss table ring/group ID. */
1661 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1662 {
1663         struct bnxt_rx_queue *rxq;
1664         unsigned int i;
1665
1666         if (!BNXT_HAS_RING_GRPS(bp)) {
1667                 for (i = 0; i < bp->rx_nr_rings; i++) {
1668                         rxq = bp->eth_dev->data->rx_queues[i];
1669                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1670                                 return rxq->index;
1671                 }
1672         } else {
1673                 for (i = 0; i < bp->rx_nr_rings; i++) {
1674                         if (bp->grp_info[i].fw_grp_id == fwr)
1675                                 return i;
1676                 }
1677         }
1678
1679         return INVALID_HW_RING_ID;
1680 }
1681
1682 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1683                             struct rte_eth_rss_reta_entry64 *reta_conf,
1684                             uint16_t reta_size)
1685 {
1686         struct bnxt *bp = eth_dev->data->dev_private;
1687         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1688         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1689         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1690         uint16_t idx, sft;
1691         int i, rc;
1692
1693         rc = is_bnxt_in_error(bp);
1694         if (rc)
1695                 return rc;
1696
1697         if (!vnic->rss_table)
1698                 return -EINVAL;
1699
1700         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1701                 return -EINVAL;
1702
1703         if (reta_size != tbl_size) {
1704                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1705                         "(%d) must equal the size supported by the hardware "
1706                         "(%d)\n", reta_size, tbl_size);
1707                 return -EINVAL;
1708         }
1709
1710         for (i = 0; i < reta_size; i++) {
1711                 struct bnxt_rx_queue *rxq;
1712
1713                 idx = i / RTE_RETA_GROUP_SIZE;
1714                 sft = i % RTE_RETA_GROUP_SIZE;
1715
1716                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1717                         continue;
1718
1719                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1720                 if (!rxq) {
1721                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1722                         return -EINVAL;
1723                 }
1724
1725                 if (BNXT_CHIP_THOR(bp)) {
1726                         vnic->rss_table[i * 2] =
1727                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1728                         vnic->rss_table[i * 2 + 1] =
1729                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1730                 } else {
1731                         vnic->rss_table[i] =
1732                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1733                 }
1734         }
1735
1736         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1737         return 0;
1738 }
1739
1740 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1741                               struct rte_eth_rss_reta_entry64 *reta_conf,
1742                               uint16_t reta_size)
1743 {
1744         struct bnxt *bp = eth_dev->data->dev_private;
1745         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1746         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1747         uint16_t idx, sft, i;
1748         int rc;
1749
1750         rc = is_bnxt_in_error(bp);
1751         if (rc)
1752                 return rc;
1753
1754         /* Retrieve from the default VNIC */
1755         if (!vnic)
1756                 return -EINVAL;
1757         if (!vnic->rss_table)
1758                 return -EINVAL;
1759
1760         if (reta_size != tbl_size) {
1761                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1762                         "(%d) must equal the size supported by the hardware "
1763                         "(%d)\n", reta_size, tbl_size);
1764                 return -EINVAL;
1765         }
1766
1767         for (idx = 0, i = 0; i < reta_size; i++) {
1768                 idx = i / RTE_RETA_GROUP_SIZE;
1769                 sft = i % RTE_RETA_GROUP_SIZE;
1770
1771                 if (reta_conf[idx].mask & (1ULL << sft)) {
1772                         uint16_t qid;
1773
1774                         if (BNXT_CHIP_THOR(bp))
1775                                 qid = bnxt_rss_to_qid(bp,
1776                                                       vnic->rss_table[i * 2]);
1777                         else
1778                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1779
1780                         if (qid == INVALID_HW_RING_ID) {
1781                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1782                                 return -EINVAL;
1783                         }
1784                         reta_conf[idx].reta[sft] = qid;
1785                 }
1786         }
1787
1788         return 0;
1789 }
1790
1791 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1792                                    struct rte_eth_rss_conf *rss_conf)
1793 {
1794         struct bnxt *bp = eth_dev->data->dev_private;
1795         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1796         struct bnxt_vnic_info *vnic;
1797         int rc;
1798
1799         rc = is_bnxt_in_error(bp);
1800         if (rc)
1801                 return rc;
1802
1803         /*
1804          * If RSS enablement were different than dev_configure,
1805          * then return -EINVAL
1806          */
1807         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1808                 if (!rss_conf->rss_hf)
1809                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1810         } else {
1811                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1812                         return -EINVAL;
1813         }
1814
1815         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1816         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1817                rss_conf,
1818                sizeof(*rss_conf));
1819
1820         /* Update the default RSS VNIC(s) */
1821         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1822         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1823
1824         /*
1825          * If hashkey is not specified, use the previously configured
1826          * hashkey
1827          */
1828         if (!rss_conf->rss_key)
1829                 goto rss_config;
1830
1831         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1832                 PMD_DRV_LOG(ERR,
1833                             "Invalid hashkey length, should be 16 bytes\n");
1834                 return -EINVAL;
1835         }
1836         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1837
1838 rss_config:
1839         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1840         return 0;
1841 }
1842
1843 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1844                                      struct rte_eth_rss_conf *rss_conf)
1845 {
1846         struct bnxt *bp = eth_dev->data->dev_private;
1847         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1848         int len, rc;
1849         uint32_t hash_types;
1850
1851         rc = is_bnxt_in_error(bp);
1852         if (rc)
1853                 return rc;
1854
1855         /* RSS configuration is the same for all VNICs */
1856         if (vnic && vnic->rss_hash_key) {
1857                 if (rss_conf->rss_key) {
1858                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1859                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1860                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1861                 }
1862
1863                 hash_types = vnic->hash_type;
1864                 rss_conf->rss_hf = 0;
1865                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1866                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1867                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1868                 }
1869                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1870                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1871                         hash_types &=
1872                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1873                 }
1874                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1875                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1876                         hash_types &=
1877                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1878                 }
1879                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1880                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1881                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1882                 }
1883                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1884                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1885                         hash_types &=
1886                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1887                 }
1888                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1889                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1890                         hash_types &=
1891                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1892                 }
1893                 if (hash_types) {
1894                         PMD_DRV_LOG(ERR,
1895                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1896                                 vnic->hash_type);
1897                         return -ENOTSUP;
1898                 }
1899         } else {
1900                 rss_conf->rss_hf = 0;
1901         }
1902         return 0;
1903 }
1904
1905 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1906                                struct rte_eth_fc_conf *fc_conf)
1907 {
1908         struct bnxt *bp = dev->data->dev_private;
1909         struct rte_eth_link link_info;
1910         int rc;
1911
1912         rc = is_bnxt_in_error(bp);
1913         if (rc)
1914                 return rc;
1915
1916         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1917         if (rc)
1918                 return rc;
1919
1920         memset(fc_conf, 0, sizeof(*fc_conf));
1921         if (bp->link_info->auto_pause)
1922                 fc_conf->autoneg = 1;
1923         switch (bp->link_info->pause) {
1924         case 0:
1925                 fc_conf->mode = RTE_FC_NONE;
1926                 break;
1927         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1928                 fc_conf->mode = RTE_FC_TX_PAUSE;
1929                 break;
1930         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1931                 fc_conf->mode = RTE_FC_RX_PAUSE;
1932                 break;
1933         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1934                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1935                 fc_conf->mode = RTE_FC_FULL;
1936                 break;
1937         }
1938         return 0;
1939 }
1940
1941 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1942                                struct rte_eth_fc_conf *fc_conf)
1943 {
1944         struct bnxt *bp = dev->data->dev_private;
1945         int rc;
1946
1947         rc = is_bnxt_in_error(bp);
1948         if (rc)
1949                 return rc;
1950
1951         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1952                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1953                 return -ENOTSUP;
1954         }
1955
1956         switch (fc_conf->mode) {
1957         case RTE_FC_NONE:
1958                 bp->link_info->auto_pause = 0;
1959                 bp->link_info->force_pause = 0;
1960                 break;
1961         case RTE_FC_RX_PAUSE:
1962                 if (fc_conf->autoneg) {
1963                         bp->link_info->auto_pause =
1964                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1965                         bp->link_info->force_pause = 0;
1966                 } else {
1967                         bp->link_info->auto_pause = 0;
1968                         bp->link_info->force_pause =
1969                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1970                 }
1971                 break;
1972         case RTE_FC_TX_PAUSE:
1973                 if (fc_conf->autoneg) {
1974                         bp->link_info->auto_pause =
1975                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1976                         bp->link_info->force_pause = 0;
1977                 } else {
1978                         bp->link_info->auto_pause = 0;
1979                         bp->link_info->force_pause =
1980                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1981                 }
1982                 break;
1983         case RTE_FC_FULL:
1984                 if (fc_conf->autoneg) {
1985                         bp->link_info->auto_pause =
1986                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1987                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1988                         bp->link_info->force_pause = 0;
1989                 } else {
1990                         bp->link_info->auto_pause = 0;
1991                         bp->link_info->force_pause =
1992                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1993                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1994                 }
1995                 break;
1996         }
1997         return bnxt_set_hwrm_link_config(bp, true);
1998 }
1999
2000 /* Add UDP tunneling port */
2001 static int
2002 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2003                          struct rte_eth_udp_tunnel *udp_tunnel)
2004 {
2005         struct bnxt *bp = eth_dev->data->dev_private;
2006         uint16_t tunnel_type = 0;
2007         int rc = 0;
2008
2009         rc = is_bnxt_in_error(bp);
2010         if (rc)
2011                 return rc;
2012
2013         switch (udp_tunnel->prot_type) {
2014         case RTE_TUNNEL_TYPE_VXLAN:
2015                 if (bp->vxlan_port_cnt) {
2016                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2017                                 udp_tunnel->udp_port);
2018                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2019                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2020                                 return -ENOSPC;
2021                         }
2022                         bp->vxlan_port_cnt++;
2023                         return 0;
2024                 }
2025                 tunnel_type =
2026                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2027                 bp->vxlan_port_cnt++;
2028                 break;
2029         case RTE_TUNNEL_TYPE_GENEVE:
2030                 if (bp->geneve_port_cnt) {
2031                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2032                                 udp_tunnel->udp_port);
2033                         if (bp->geneve_port != udp_tunnel->udp_port) {
2034                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2035                                 return -ENOSPC;
2036                         }
2037                         bp->geneve_port_cnt++;
2038                         return 0;
2039                 }
2040                 tunnel_type =
2041                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2042                 bp->geneve_port_cnt++;
2043                 break;
2044         default:
2045                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2046                 return -ENOTSUP;
2047         }
2048         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2049                                              tunnel_type);
2050         return rc;
2051 }
2052
2053 static int
2054 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2055                          struct rte_eth_udp_tunnel *udp_tunnel)
2056 {
2057         struct bnxt *bp = eth_dev->data->dev_private;
2058         uint16_t tunnel_type = 0;
2059         uint16_t port = 0;
2060         int rc = 0;
2061
2062         rc = is_bnxt_in_error(bp);
2063         if (rc)
2064                 return rc;
2065
2066         switch (udp_tunnel->prot_type) {
2067         case RTE_TUNNEL_TYPE_VXLAN:
2068                 if (!bp->vxlan_port_cnt) {
2069                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2070                         return -EINVAL;
2071                 }
2072                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2073                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2074                                 udp_tunnel->udp_port, bp->vxlan_port);
2075                         return -EINVAL;
2076                 }
2077                 if (--bp->vxlan_port_cnt)
2078                         return 0;
2079
2080                 tunnel_type =
2081                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2082                 port = bp->vxlan_fw_dst_port_id;
2083                 break;
2084         case RTE_TUNNEL_TYPE_GENEVE:
2085                 if (!bp->geneve_port_cnt) {
2086                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2087                         return -EINVAL;
2088                 }
2089                 if (bp->geneve_port != udp_tunnel->udp_port) {
2090                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2091                                 udp_tunnel->udp_port, bp->geneve_port);
2092                         return -EINVAL;
2093                 }
2094                 if (--bp->geneve_port_cnt)
2095                         return 0;
2096
2097                 tunnel_type =
2098                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2099                 port = bp->geneve_fw_dst_port_id;
2100                 break;
2101         default:
2102                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2103                 return -ENOTSUP;
2104         }
2105
2106         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2107         if (!rc) {
2108                 if (tunnel_type ==
2109                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2110                         bp->vxlan_port = 0;
2111                 if (tunnel_type ==
2112                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2113                         bp->geneve_port = 0;
2114         }
2115         return rc;
2116 }
2117
2118 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2119 {
2120         struct bnxt_filter_info *filter;
2121         struct bnxt_vnic_info *vnic;
2122         int rc = 0;
2123         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2124
2125         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2126         filter = STAILQ_FIRST(&vnic->filter);
2127         while (filter) {
2128                 /* Search for this matching MAC+VLAN filter */
2129                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2130                         /* Delete the filter */
2131                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2132                         if (rc)
2133                                 return rc;
2134                         STAILQ_REMOVE(&vnic->filter, filter,
2135                                       bnxt_filter_info, next);
2136                         bnxt_free_filter(bp, filter);
2137                         PMD_DRV_LOG(INFO,
2138                                     "Deleted vlan filter for %d\n",
2139                                     vlan_id);
2140                         return 0;
2141                 }
2142                 filter = STAILQ_NEXT(filter, next);
2143         }
2144         return -ENOENT;
2145 }
2146
2147 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2148 {
2149         struct bnxt_filter_info *filter;
2150         struct bnxt_vnic_info *vnic;
2151         int rc = 0;
2152         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2153                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2154         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2155
2156         /* Implementation notes on the use of VNIC in this command:
2157          *
2158          * By default, these filters belong to default vnic for the function.
2159          * Once these filters are set up, only destination VNIC can be modified.
2160          * If the destination VNIC is not specified in this command,
2161          * then the HWRM shall only create an l2 context id.
2162          */
2163
2164         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2165         filter = STAILQ_FIRST(&vnic->filter);
2166         /* Check if the VLAN has already been added */
2167         while (filter) {
2168                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2169                         return -EEXIST;
2170
2171                 filter = STAILQ_NEXT(filter, next);
2172         }
2173
2174         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2175          * command to create MAC+VLAN filter with the right flags, enables set.
2176          */
2177         filter = bnxt_alloc_filter(bp);
2178         if (!filter) {
2179                 PMD_DRV_LOG(ERR,
2180                             "MAC/VLAN filter alloc failed\n");
2181                 return -ENOMEM;
2182         }
2183         /* MAC + VLAN ID filter */
2184         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2185          * untagged packets are received
2186          *
2187          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2188          * packets and only the programmed vlan's packets are received
2189          */
2190         filter->l2_ivlan = vlan_id;
2191         filter->l2_ivlan_mask = 0x0FFF;
2192         filter->enables |= en;
2193         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2194
2195         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2196         if (rc) {
2197                 /* Free the newly allocated filter as we were
2198                  * not able to create the filter in hardware.
2199                  */
2200                 bnxt_free_filter(bp, filter);
2201                 return rc;
2202         }
2203
2204         filter->mac_index = 0;
2205         /* Add this new filter to the list */
2206         if (vlan_id == 0)
2207                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2208         else
2209                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2210
2211         PMD_DRV_LOG(INFO,
2212                     "Added Vlan filter for %d\n", vlan_id);
2213         return rc;
2214 }
2215
2216 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2217                 uint16_t vlan_id, int on)
2218 {
2219         struct bnxt *bp = eth_dev->data->dev_private;
2220         int rc;
2221
2222         rc = is_bnxt_in_error(bp);
2223         if (rc)
2224                 return rc;
2225
2226         if (!eth_dev->data->dev_started) {
2227                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2228                 return -EINVAL;
2229         }
2230
2231         /* These operations apply to ALL existing MAC/VLAN filters */
2232         if (on)
2233                 return bnxt_add_vlan_filter(bp, vlan_id);
2234         else
2235                 return bnxt_del_vlan_filter(bp, vlan_id);
2236 }
2237
2238 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2239                                     struct bnxt_vnic_info *vnic)
2240 {
2241         struct bnxt_filter_info *filter;
2242         int rc;
2243
2244         filter = STAILQ_FIRST(&vnic->filter);
2245         while (filter) {
2246                 if (filter->mac_index == 0 &&
2247                     !memcmp(filter->l2_addr, bp->mac_addr,
2248                             RTE_ETHER_ADDR_LEN)) {
2249                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2250                         if (!rc) {
2251                                 STAILQ_REMOVE(&vnic->filter, filter,
2252                                               bnxt_filter_info, next);
2253                                 bnxt_free_filter(bp, filter);
2254                         }
2255                         return rc;
2256                 }
2257                 filter = STAILQ_NEXT(filter, next);
2258         }
2259         return 0;
2260 }
2261
2262 static int
2263 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2264 {
2265         struct bnxt_vnic_info *vnic;
2266         unsigned int i;
2267         int rc;
2268
2269         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2270         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2271                 /* Remove any VLAN filters programmed */
2272                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2273                         bnxt_del_vlan_filter(bp, i);
2274
2275                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2276                 if (rc)
2277                         return rc;
2278         } else {
2279                 /* Default filter will allow packets that match the
2280                  * dest mac. So, it has to be deleted, otherwise, we
2281                  * will endup receiving vlan packets for which the
2282                  * filter is not programmed, when hw-vlan-filter
2283                  * configuration is ON
2284                  */
2285                 bnxt_del_dflt_mac_filter(bp, vnic);
2286                 /* This filter will allow only untagged packets */
2287                 bnxt_add_vlan_filter(bp, 0);
2288         }
2289         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2290                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2291
2292         return 0;
2293 }
2294
2295 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2296 {
2297         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2298         unsigned int i;
2299         int rc;
2300
2301         /* Destroy vnic filters and vnic */
2302         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2303             DEV_RX_OFFLOAD_VLAN_FILTER) {
2304                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2305                         bnxt_del_vlan_filter(bp, i);
2306         }
2307         bnxt_del_dflt_mac_filter(bp, vnic);
2308
2309         rc = bnxt_hwrm_vnic_free(bp, vnic);
2310         if (rc)
2311                 return rc;
2312
2313         rte_free(vnic->fw_grp_ids);
2314         vnic->fw_grp_ids = NULL;
2315
2316         vnic->rx_queue_cnt = 0;
2317
2318         return 0;
2319 }
2320
2321 static int
2322 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2323 {
2324         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2325         int rc;
2326
2327         /* Destroy, recreate and reconfigure the default vnic */
2328         rc = bnxt_free_one_vnic(bp, 0);
2329         if (rc)
2330                 return rc;
2331
2332         /* default vnic 0 */
2333         rc = bnxt_setup_one_vnic(bp, 0);
2334         if (rc)
2335                 return rc;
2336
2337         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2338             DEV_RX_OFFLOAD_VLAN_FILTER) {
2339                 rc = bnxt_add_vlan_filter(bp, 0);
2340                 if (rc)
2341                         return rc;
2342                 rc = bnxt_restore_vlan_filters(bp);
2343                 if (rc)
2344                         return rc;
2345         } else {
2346                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2347                 if (rc)
2348                         return rc;
2349         }
2350
2351         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2352         if (rc)
2353                 return rc;
2354
2355         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2356                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2357
2358         return rc;
2359 }
2360
2361 static int
2362 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2363 {
2364         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2365         struct bnxt *bp = dev->data->dev_private;
2366         int rc;
2367
2368         rc = is_bnxt_in_error(bp);
2369         if (rc)
2370                 return rc;
2371
2372         /* Filter settings will get applied when port is started */
2373         if (!dev->data->dev_started)
2374                 return 0;
2375
2376         if (mask & ETH_VLAN_FILTER_MASK) {
2377                 /* Enable or disable VLAN filtering */
2378                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2379                 if (rc)
2380                         return rc;
2381         }
2382
2383         if (mask & ETH_VLAN_STRIP_MASK) {
2384                 /* Enable or disable VLAN stripping */
2385                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2386                 if (rc)
2387                         return rc;
2388         }
2389
2390         if (mask & ETH_VLAN_EXTEND_MASK) {
2391                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2392                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2393                 else
2394                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2395         }
2396
2397         return 0;
2398 }
2399
2400 static int
2401 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2402                       uint16_t tpid)
2403 {
2404         struct bnxt *bp = dev->data->dev_private;
2405         int qinq = dev->data->dev_conf.rxmode.offloads &
2406                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2407
2408         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2409             vlan_type != ETH_VLAN_TYPE_OUTER) {
2410                 PMD_DRV_LOG(ERR,
2411                             "Unsupported vlan type.");
2412                 return -EINVAL;
2413         }
2414         if (!qinq) {
2415                 PMD_DRV_LOG(ERR,
2416                             "QinQ not enabled. Needs to be ON as we can "
2417                             "accelerate only outer vlan\n");
2418                 return -EINVAL;
2419         }
2420
2421         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2422                 switch (tpid) {
2423                 case RTE_ETHER_TYPE_QINQ:
2424                         bp->outer_tpid_bd =
2425                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2426                                 break;
2427                 case RTE_ETHER_TYPE_VLAN:
2428                         bp->outer_tpid_bd =
2429                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2430                                 break;
2431                 case RTE_ETHER_TYPE_QINQ1:
2432                         bp->outer_tpid_bd =
2433                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2434                                 break;
2435                 case RTE_ETHER_TYPE_QINQ2:
2436                         bp->outer_tpid_bd =
2437                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2438                                 break;
2439                 case RTE_ETHER_TYPE_QINQ3:
2440                         bp->outer_tpid_bd =
2441                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2442                                 break;
2443                 default:
2444                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2445                         return -EINVAL;
2446                 }
2447                 bp->outer_tpid_bd |= tpid;
2448                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2449         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2450                 PMD_DRV_LOG(ERR,
2451                             "Can accelerate only outer vlan in QinQ\n");
2452                 return -EINVAL;
2453         }
2454
2455         return 0;
2456 }
2457
2458 static int
2459 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2460                              struct rte_ether_addr *addr)
2461 {
2462         struct bnxt *bp = dev->data->dev_private;
2463         /* Default Filter is tied to VNIC 0 */
2464         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2465         int rc;
2466
2467         rc = is_bnxt_in_error(bp);
2468         if (rc)
2469                 return rc;
2470
2471         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2472                 return -EPERM;
2473
2474         if (rte_is_zero_ether_addr(addr))
2475                 return -EINVAL;
2476
2477         /* Filter settings will get applied when port is started */
2478         if (!dev->data->dev_started)
2479                 return 0;
2480
2481         /* Check if the requested MAC is already added */
2482         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2483                 return 0;
2484
2485         /* Destroy filter and re-create it */
2486         bnxt_del_dflt_mac_filter(bp, vnic);
2487
2488         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2489         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2490                 /* This filter will allow only untagged packets */
2491                 rc = bnxt_add_vlan_filter(bp, 0);
2492         } else {
2493                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2494         }
2495
2496         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2497         return rc;
2498 }
2499
2500 static int
2501 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2502                           struct rte_ether_addr *mc_addr_set,
2503                           uint32_t nb_mc_addr)
2504 {
2505         struct bnxt *bp = eth_dev->data->dev_private;
2506         char *mc_addr_list = (char *)mc_addr_set;
2507         struct bnxt_vnic_info *vnic;
2508         uint32_t off = 0, i = 0;
2509         int rc;
2510
2511         rc = is_bnxt_in_error(bp);
2512         if (rc)
2513                 return rc;
2514
2515         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2516
2517         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2518                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2519                 goto allmulti;
2520         }
2521
2522         /* TODO Check for Duplicate mcast addresses */
2523         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2524         for (i = 0; i < nb_mc_addr; i++) {
2525                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2526                         RTE_ETHER_ADDR_LEN);
2527                 off += RTE_ETHER_ADDR_LEN;
2528         }
2529
2530         vnic->mc_addr_cnt = i;
2531         if (vnic->mc_addr_cnt)
2532                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2533         else
2534                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2535
2536 allmulti:
2537         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2538 }
2539
2540 static int
2541 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2542 {
2543         struct bnxt *bp = dev->data->dev_private;
2544         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2545         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2546         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2547         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2548         int ret;
2549
2550         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2551                         fw_major, fw_minor, fw_updt, fw_rsvd);
2552
2553         ret += 1; /* add the size of '\0' */
2554         if (fw_size < (uint32_t)ret)
2555                 return ret;
2556         else
2557                 return 0;
2558 }
2559
2560 static void
2561 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2562         struct rte_eth_rxq_info *qinfo)
2563 {
2564         struct bnxt *bp = dev->data->dev_private;
2565         struct bnxt_rx_queue *rxq;
2566
2567         if (is_bnxt_in_error(bp))
2568                 return;
2569
2570         rxq = dev->data->rx_queues[queue_id];
2571
2572         qinfo->mp = rxq->mb_pool;
2573         qinfo->scattered_rx = dev->data->scattered_rx;
2574         qinfo->nb_desc = rxq->nb_rx_desc;
2575
2576         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2577         qinfo->conf.rx_drop_en = 0;
2578         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2579 }
2580
2581 static void
2582 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2583         struct rte_eth_txq_info *qinfo)
2584 {
2585         struct bnxt *bp = dev->data->dev_private;
2586         struct bnxt_tx_queue *txq;
2587
2588         if (is_bnxt_in_error(bp))
2589                 return;
2590
2591         txq = dev->data->tx_queues[queue_id];
2592
2593         qinfo->nb_desc = txq->nb_tx_desc;
2594
2595         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2596         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2597         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2598
2599         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2600         qinfo->conf.tx_rs_thresh = 0;
2601         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2602 }
2603
2604 static int
2605 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2606                        struct rte_eth_burst_mode *mode)
2607 {
2608         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2609
2610         if (pkt_burst == bnxt_recv_pkts) {
2611                 snprintf(mode->info, sizeof(mode->info), "%s",
2612                          "Scalar");
2613                 return 0;
2614         }
2615 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2616         if (pkt_burst == bnxt_recv_pkts_vec) {
2617                 snprintf(mode->info, sizeof(mode->info), "%s",
2618                          "Vector SSE");
2619                 return 0;
2620         }
2621 #endif
2622
2623         return -EINVAL;
2624 }
2625
2626 static int
2627 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2628                        struct rte_eth_burst_mode *mode)
2629 {
2630         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2631
2632         if (pkt_burst == bnxt_xmit_pkts) {
2633                 snprintf(mode->info, sizeof(mode->info), "%s",
2634                          "Scalar");
2635                 return 0;
2636         }
2637 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2638         if (pkt_burst == bnxt_xmit_pkts_vec) {
2639                 snprintf(mode->info, sizeof(mode->info), "%s",
2640                          "Vector SSE");
2641                 return 0;
2642         }
2643 #endif
2644
2645         return -EINVAL;
2646 }
2647
2648 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2649 {
2650         struct bnxt *bp = eth_dev->data->dev_private;
2651         uint32_t new_pkt_size;
2652         uint32_t rc = 0;
2653         uint32_t i;
2654
2655         rc = is_bnxt_in_error(bp);
2656         if (rc)
2657                 return rc;
2658
2659         /* Exit if receive queues are not configured yet */
2660         if (!eth_dev->data->nb_rx_queues)
2661                 return rc;
2662
2663         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2664                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2665
2666 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2667         /*
2668          * If vector-mode tx/rx is active, disallow any MTU change that would
2669          * require scattered receive support.
2670          */
2671         if (eth_dev->data->dev_started &&
2672             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2673              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2674             (new_pkt_size >
2675              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2676                 PMD_DRV_LOG(ERR,
2677                             "MTU change would require scattered rx support. ");
2678                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2679                 return -EINVAL;
2680         }
2681 #endif
2682
2683         if (new_mtu > RTE_ETHER_MTU) {
2684                 bp->flags |= BNXT_FLAG_JUMBO;
2685                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2686                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2687         } else {
2688                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2689                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2690                 bp->flags &= ~BNXT_FLAG_JUMBO;
2691         }
2692
2693         /* Is there a change in mtu setting? */
2694         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2695                 return rc;
2696
2697         for (i = 0; i < bp->nr_vnics; i++) {
2698                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2699                 uint16_t size = 0;
2700
2701                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2702                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2703                 if (rc)
2704                         break;
2705
2706                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2707                 size -= RTE_PKTMBUF_HEADROOM;
2708
2709                 if (size < new_mtu) {
2710                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2711                         if (rc)
2712                                 return rc;
2713                 }
2714         }
2715
2716         if (!rc)
2717                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2718
2719         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2720
2721         return rc;
2722 }
2723
2724 static int
2725 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2726 {
2727         struct bnxt *bp = dev->data->dev_private;
2728         uint16_t vlan = bp->vlan;
2729         int rc;
2730
2731         rc = is_bnxt_in_error(bp);
2732         if (rc)
2733                 return rc;
2734
2735         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2736                 PMD_DRV_LOG(ERR,
2737                         "PVID cannot be modified for this function\n");
2738                 return -ENOTSUP;
2739         }
2740         bp->vlan = on ? pvid : 0;
2741
2742         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2743         if (rc)
2744                 bp->vlan = vlan;
2745         return rc;
2746 }
2747
2748 static int
2749 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2750 {
2751         struct bnxt *bp = dev->data->dev_private;
2752         int rc;
2753
2754         rc = is_bnxt_in_error(bp);
2755         if (rc)
2756                 return rc;
2757
2758         return bnxt_hwrm_port_led_cfg(bp, true);
2759 }
2760
2761 static int
2762 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2763 {
2764         struct bnxt *bp = dev->data->dev_private;
2765         int rc;
2766
2767         rc = is_bnxt_in_error(bp);
2768         if (rc)
2769                 return rc;
2770
2771         return bnxt_hwrm_port_led_cfg(bp, false);
2772 }
2773
2774 static uint32_t
2775 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2776 {
2777         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2778         uint32_t desc = 0, raw_cons = 0, cons;
2779         struct bnxt_cp_ring_info *cpr;
2780         struct bnxt_rx_queue *rxq;
2781         struct rx_pkt_cmpl *rxcmp;
2782         int rc;
2783
2784         rc = is_bnxt_in_error(bp);
2785         if (rc)
2786                 return rc;
2787
2788         rxq = dev->data->rx_queues[rx_queue_id];
2789         cpr = rxq->cp_ring;
2790         raw_cons = cpr->cp_raw_cons;
2791
2792         while (1) {
2793                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2794                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2795                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2796
2797                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2798                         break;
2799                 } else {
2800                         raw_cons++;
2801                         desc++;
2802                 }
2803         }
2804
2805         return desc;
2806 }
2807
2808 static int
2809 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2810 {
2811         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2812         struct bnxt_rx_ring_info *rxr;
2813         struct bnxt_cp_ring_info *cpr;
2814         struct bnxt_sw_rx_bd *rx_buf;
2815         struct rx_pkt_cmpl *rxcmp;
2816         uint32_t cons, cp_cons;
2817         int rc;
2818
2819         if (!rxq)
2820                 return -EINVAL;
2821
2822         rc = is_bnxt_in_error(rxq->bp);
2823         if (rc)
2824                 return rc;
2825
2826         cpr = rxq->cp_ring;
2827         rxr = rxq->rx_ring;
2828
2829         if (offset >= rxq->nb_rx_desc)
2830                 return -EINVAL;
2831
2832         cons = RING_CMP(cpr->cp_ring_struct, offset);
2833         cp_cons = cpr->cp_raw_cons;
2834         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2835
2836         if (cons > cp_cons) {
2837                 if (CMPL_VALID(rxcmp, cpr->valid))
2838                         return RTE_ETH_RX_DESC_DONE;
2839         } else {
2840                 if (CMPL_VALID(rxcmp, !cpr->valid))
2841                         return RTE_ETH_RX_DESC_DONE;
2842         }
2843         rx_buf = &rxr->rx_buf_ring[cons];
2844         if (rx_buf->mbuf == NULL)
2845                 return RTE_ETH_RX_DESC_UNAVAIL;
2846
2847
2848         return RTE_ETH_RX_DESC_AVAIL;
2849 }
2850
2851 static int
2852 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2853 {
2854         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2855         struct bnxt_tx_ring_info *txr;
2856         struct bnxt_cp_ring_info *cpr;
2857         struct bnxt_sw_tx_bd *tx_buf;
2858         struct tx_pkt_cmpl *txcmp;
2859         uint32_t cons, cp_cons;
2860         int rc;
2861
2862         if (!txq)
2863                 return -EINVAL;
2864
2865         rc = is_bnxt_in_error(txq->bp);
2866         if (rc)
2867                 return rc;
2868
2869         cpr = txq->cp_ring;
2870         txr = txq->tx_ring;
2871
2872         if (offset >= txq->nb_tx_desc)
2873                 return -EINVAL;
2874
2875         cons = RING_CMP(cpr->cp_ring_struct, offset);
2876         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2877         cp_cons = cpr->cp_raw_cons;
2878
2879         if (cons > cp_cons) {
2880                 if (CMPL_VALID(txcmp, cpr->valid))
2881                         return RTE_ETH_TX_DESC_UNAVAIL;
2882         } else {
2883                 if (CMPL_VALID(txcmp, !cpr->valid))
2884                         return RTE_ETH_TX_DESC_UNAVAIL;
2885         }
2886         tx_buf = &txr->tx_buf_ring[cons];
2887         if (tx_buf->mbuf == NULL)
2888                 return RTE_ETH_TX_DESC_DONE;
2889
2890         return RTE_ETH_TX_DESC_FULL;
2891 }
2892
2893 static struct bnxt_filter_info *
2894 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2895                                 struct rte_eth_ethertype_filter *efilter,
2896                                 struct bnxt_vnic_info *vnic0,
2897                                 struct bnxt_vnic_info *vnic,
2898                                 int *ret)
2899 {
2900         struct bnxt_filter_info *mfilter = NULL;
2901         int match = 0;
2902         *ret = 0;
2903
2904         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2905                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2906                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2907                         " ethertype filter.", efilter->ether_type);
2908                 *ret = -EINVAL;
2909                 goto exit;
2910         }
2911         if (efilter->queue >= bp->rx_nr_rings) {
2912                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2913                 *ret = -EINVAL;
2914                 goto exit;
2915         }
2916
2917         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2918         vnic = &bp->vnic_info[efilter->queue];
2919         if (vnic == NULL) {
2920                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2921                 *ret = -EINVAL;
2922                 goto exit;
2923         }
2924
2925         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2926                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2927                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2928                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2929                              mfilter->flags ==
2930                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2931                              mfilter->ethertype == efilter->ether_type)) {
2932                                 match = 1;
2933                                 break;
2934                         }
2935                 }
2936         } else {
2937                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2938                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2939                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2940                              mfilter->ethertype == efilter->ether_type &&
2941                              mfilter->flags ==
2942                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2943                                 match = 1;
2944                                 break;
2945                         }
2946         }
2947
2948         if (match)
2949                 *ret = -EEXIST;
2950
2951 exit:
2952         return mfilter;
2953 }
2954
2955 static int
2956 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2957                         enum rte_filter_op filter_op,
2958                         void *arg)
2959 {
2960         struct bnxt *bp = dev->data->dev_private;
2961         struct rte_eth_ethertype_filter *efilter =
2962                         (struct rte_eth_ethertype_filter *)arg;
2963         struct bnxt_filter_info *bfilter, *filter1;
2964         struct bnxt_vnic_info *vnic, *vnic0;
2965         int ret;
2966
2967         if (filter_op == RTE_ETH_FILTER_NOP)
2968                 return 0;
2969
2970         if (arg == NULL) {
2971                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2972                             filter_op);
2973                 return -EINVAL;
2974         }
2975
2976         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2977         vnic = &bp->vnic_info[efilter->queue];
2978
2979         switch (filter_op) {
2980         case RTE_ETH_FILTER_ADD:
2981                 bnxt_match_and_validate_ether_filter(bp, efilter,
2982                                                         vnic0, vnic, &ret);
2983                 if (ret < 0)
2984                         return ret;
2985
2986                 bfilter = bnxt_get_unused_filter(bp);
2987                 if (bfilter == NULL) {
2988                         PMD_DRV_LOG(ERR,
2989                                 "Not enough resources for a new filter.\n");
2990                         return -ENOMEM;
2991                 }
2992                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2993                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2994                        RTE_ETHER_ADDR_LEN);
2995                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2996                        RTE_ETHER_ADDR_LEN);
2997                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2998                 bfilter->ethertype = efilter->ether_type;
2999                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3000
3001                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3002                 if (filter1 == NULL) {
3003                         ret = -EINVAL;
3004                         goto cleanup;
3005                 }
3006                 bfilter->enables |=
3007                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3008                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3009
3010                 bfilter->dst_id = vnic->fw_vnic_id;
3011
3012                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3013                         bfilter->flags =
3014                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3015                 }
3016
3017                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3018                 if (ret)
3019                         goto cleanup;
3020                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3021                 break;
3022         case RTE_ETH_FILTER_DELETE:
3023                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3024                                                         vnic0, vnic, &ret);
3025                 if (ret == -EEXIST) {
3026                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3027
3028                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3029                                       next);
3030                         bnxt_free_filter(bp, filter1);
3031                 } else if (ret == 0) {
3032                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3033                 }
3034                 break;
3035         default:
3036                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3037                 ret = -EINVAL;
3038                 goto error;
3039         }
3040         return ret;
3041 cleanup:
3042         bnxt_free_filter(bp, bfilter);
3043 error:
3044         return ret;
3045 }
3046
3047 static inline int
3048 parse_ntuple_filter(struct bnxt *bp,
3049                     struct rte_eth_ntuple_filter *nfilter,
3050                     struct bnxt_filter_info *bfilter)
3051 {
3052         uint32_t en = 0;
3053
3054         if (nfilter->queue >= bp->rx_nr_rings) {
3055                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3056                 return -EINVAL;
3057         }
3058
3059         switch (nfilter->dst_port_mask) {
3060         case UINT16_MAX:
3061                 bfilter->dst_port_mask = -1;
3062                 bfilter->dst_port = nfilter->dst_port;
3063                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3064                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3065                 break;
3066         default:
3067                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3068                 return -EINVAL;
3069         }
3070
3071         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3072         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3073
3074         switch (nfilter->proto_mask) {
3075         case UINT8_MAX:
3076                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3077                         bfilter->ip_protocol = 17;
3078                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3079                         bfilter->ip_protocol = 6;
3080                 else
3081                         return -EINVAL;
3082                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3083                 break;
3084         default:
3085                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3086                 return -EINVAL;
3087         }
3088
3089         switch (nfilter->dst_ip_mask) {
3090         case UINT32_MAX:
3091                 bfilter->dst_ipaddr_mask[0] = -1;
3092                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3093                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3094                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3095                 break;
3096         default:
3097                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3098                 return -EINVAL;
3099         }
3100
3101         switch (nfilter->src_ip_mask) {
3102         case UINT32_MAX:
3103                 bfilter->src_ipaddr_mask[0] = -1;
3104                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3105                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3106                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3107                 break;
3108         default:
3109                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3110                 return -EINVAL;
3111         }
3112
3113         switch (nfilter->src_port_mask) {
3114         case UINT16_MAX:
3115                 bfilter->src_port_mask = -1;
3116                 bfilter->src_port = nfilter->src_port;
3117                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3118                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3119                 break;
3120         default:
3121                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3122                 return -EINVAL;
3123         }
3124
3125         bfilter->enables = en;
3126         return 0;
3127 }
3128
3129 static struct bnxt_filter_info*
3130 bnxt_match_ntuple_filter(struct bnxt *bp,
3131                          struct bnxt_filter_info *bfilter,
3132                          struct bnxt_vnic_info **mvnic)
3133 {
3134         struct bnxt_filter_info *mfilter = NULL;
3135         int i;
3136
3137         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3138                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3139                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3140                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3141                             bfilter->src_ipaddr_mask[0] ==
3142                             mfilter->src_ipaddr_mask[0] &&
3143                             bfilter->src_port == mfilter->src_port &&
3144                             bfilter->src_port_mask == mfilter->src_port_mask &&
3145                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3146                             bfilter->dst_ipaddr_mask[0] ==
3147                             mfilter->dst_ipaddr_mask[0] &&
3148                             bfilter->dst_port == mfilter->dst_port &&
3149                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3150                             bfilter->flags == mfilter->flags &&
3151                             bfilter->enables == mfilter->enables) {
3152                                 if (mvnic)
3153                                         *mvnic = vnic;
3154                                 return mfilter;
3155                         }
3156                 }
3157         }
3158         return NULL;
3159 }
3160
3161 static int
3162 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3163                        struct rte_eth_ntuple_filter *nfilter,
3164                        enum rte_filter_op filter_op)
3165 {
3166         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3167         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3168         int ret;
3169
3170         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3171                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3172                 return -EINVAL;
3173         }
3174
3175         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3176                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3177                 return -EINVAL;
3178         }
3179
3180         bfilter = bnxt_get_unused_filter(bp);
3181         if (bfilter == NULL) {
3182                 PMD_DRV_LOG(ERR,
3183                         "Not enough resources for a new filter.\n");
3184                 return -ENOMEM;
3185         }
3186         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3187         if (ret < 0)
3188                 goto free_filter;
3189
3190         vnic = &bp->vnic_info[nfilter->queue];
3191         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3192         filter1 = STAILQ_FIRST(&vnic0->filter);
3193         if (filter1 == NULL) {
3194                 ret = -EINVAL;
3195                 goto free_filter;
3196         }
3197
3198         bfilter->dst_id = vnic->fw_vnic_id;
3199         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3200         bfilter->enables |=
3201                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3202         bfilter->ethertype = 0x800;
3203         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3204
3205         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3206
3207         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3208             bfilter->dst_id == mfilter->dst_id) {
3209                 PMD_DRV_LOG(ERR, "filter exists.\n");
3210                 ret = -EEXIST;
3211                 goto free_filter;
3212         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3213                    bfilter->dst_id != mfilter->dst_id) {
3214                 mfilter->dst_id = vnic->fw_vnic_id;
3215                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3216                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3217                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3218                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3219                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3220                 goto free_filter;
3221         }
3222         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3223                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3224                 ret = -ENOENT;
3225                 goto free_filter;
3226         }
3227
3228         if (filter_op == RTE_ETH_FILTER_ADD) {
3229                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3230                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3231                 if (ret)
3232                         goto free_filter;
3233                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3234         } else {
3235                 if (mfilter == NULL) {
3236                         /* This should not happen. But for Coverity! */
3237                         ret = -ENOENT;
3238                         goto free_filter;
3239                 }
3240                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3241
3242                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3243                 bnxt_free_filter(bp, mfilter);
3244                 bnxt_free_filter(bp, bfilter);
3245         }
3246
3247         return 0;
3248 free_filter:
3249         bnxt_free_filter(bp, bfilter);
3250         return ret;
3251 }
3252
3253 static int
3254 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3255                         enum rte_filter_op filter_op,
3256                         void *arg)
3257 {
3258         struct bnxt *bp = dev->data->dev_private;
3259         int ret;
3260
3261         if (filter_op == RTE_ETH_FILTER_NOP)
3262                 return 0;
3263
3264         if (arg == NULL) {
3265                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3266                             filter_op);
3267                 return -EINVAL;
3268         }
3269
3270         switch (filter_op) {
3271         case RTE_ETH_FILTER_ADD:
3272                 ret = bnxt_cfg_ntuple_filter(bp,
3273                         (struct rte_eth_ntuple_filter *)arg,
3274                         filter_op);
3275                 break;
3276         case RTE_ETH_FILTER_DELETE:
3277                 ret = bnxt_cfg_ntuple_filter(bp,
3278                         (struct rte_eth_ntuple_filter *)arg,
3279                         filter_op);
3280                 break;
3281         default:
3282                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3283                 ret = -EINVAL;
3284                 break;
3285         }
3286         return ret;
3287 }
3288
3289 static int
3290 bnxt_parse_fdir_filter(struct bnxt *bp,
3291                        struct rte_eth_fdir_filter *fdir,
3292                        struct bnxt_filter_info *filter)
3293 {
3294         enum rte_fdir_mode fdir_mode =
3295                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3296         struct bnxt_vnic_info *vnic0, *vnic;
3297         struct bnxt_filter_info *filter1;
3298         uint32_t en = 0;
3299         int i;
3300
3301         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3302                 return -EINVAL;
3303
3304         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3305         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3306
3307         switch (fdir->input.flow_type) {
3308         case RTE_ETH_FLOW_IPV4:
3309         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3310                 /* FALLTHROUGH */
3311                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3312                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3313                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3314                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3315                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3316                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3317                 filter->ip_addr_type =
3318                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3319                 filter->src_ipaddr_mask[0] = 0xffffffff;
3320                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3321                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3322                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3323                 filter->ethertype = 0x800;
3324                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3325                 break;
3326         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3327                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3328                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3329                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3330                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3331                 filter->dst_port_mask = 0xffff;
3332                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3333                 filter->src_port_mask = 0xffff;
3334                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3335                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3336                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3337                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3338                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3339                 filter->ip_protocol = 6;
3340                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3341                 filter->ip_addr_type =
3342                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3343                 filter->src_ipaddr_mask[0] = 0xffffffff;
3344                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3345                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3346                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3347                 filter->ethertype = 0x800;
3348                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3349                 break;
3350         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3351                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3352                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3353                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3354                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3355                 filter->dst_port_mask = 0xffff;
3356                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3357                 filter->src_port_mask = 0xffff;
3358                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3359                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3360                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3361                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3362                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3363                 filter->ip_protocol = 17;
3364                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3365                 filter->ip_addr_type =
3366                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3367                 filter->src_ipaddr_mask[0] = 0xffffffff;
3368                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3369                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3370                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3371                 filter->ethertype = 0x800;
3372                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3373                 break;
3374         case RTE_ETH_FLOW_IPV6:
3375         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3376                 /* FALLTHROUGH */
3377                 filter->ip_addr_type =
3378                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3379                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3380                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3381                 rte_memcpy(filter->src_ipaddr,
3382                            fdir->input.flow.ipv6_flow.src_ip, 16);
3383                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3384                 rte_memcpy(filter->dst_ipaddr,
3385                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3386                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3387                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3388                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3389                 memset(filter->src_ipaddr_mask, 0xff, 16);
3390                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3391                 filter->ethertype = 0x86dd;
3392                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3393                 break;
3394         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3395                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3396                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3397                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3398                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3399                 filter->dst_port_mask = 0xffff;
3400                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3401                 filter->src_port_mask = 0xffff;
3402                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3403                 filter->ip_addr_type =
3404                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3405                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3406                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3407                 rte_memcpy(filter->src_ipaddr,
3408                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3409                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3410                 rte_memcpy(filter->dst_ipaddr,
3411                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3412                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3413                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3414                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3415                 memset(filter->src_ipaddr_mask, 0xff, 16);
3416                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3417                 filter->ethertype = 0x86dd;
3418                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3419                 break;
3420         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3421                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3422                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3423                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3424                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3425                 filter->dst_port_mask = 0xffff;
3426                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3427                 filter->src_port_mask = 0xffff;
3428                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3429                 filter->ip_addr_type =
3430                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3431                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3432                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3433                 rte_memcpy(filter->src_ipaddr,
3434                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3435                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3436                 rte_memcpy(filter->dst_ipaddr,
3437                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3438                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3439                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3440                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3441                 memset(filter->src_ipaddr_mask, 0xff, 16);
3442                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3443                 filter->ethertype = 0x86dd;
3444                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3445                 break;
3446         case RTE_ETH_FLOW_L2_PAYLOAD:
3447                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3448                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3449                 break;
3450         case RTE_ETH_FLOW_VXLAN:
3451                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3452                         return -EINVAL;
3453                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3454                 filter->tunnel_type =
3455                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3456                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3457                 break;
3458         case RTE_ETH_FLOW_NVGRE:
3459                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3460                         return -EINVAL;
3461                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3462                 filter->tunnel_type =
3463                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3464                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3465                 break;
3466         case RTE_ETH_FLOW_UNKNOWN:
3467         case RTE_ETH_FLOW_RAW:
3468         case RTE_ETH_FLOW_FRAG_IPV4:
3469         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3470         case RTE_ETH_FLOW_FRAG_IPV6:
3471         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3472         case RTE_ETH_FLOW_IPV6_EX:
3473         case RTE_ETH_FLOW_IPV6_TCP_EX:
3474         case RTE_ETH_FLOW_IPV6_UDP_EX:
3475         case RTE_ETH_FLOW_GENEVE:
3476                 /* FALLTHROUGH */
3477         default:
3478                 return -EINVAL;
3479         }
3480
3481         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3482         vnic = &bp->vnic_info[fdir->action.rx_queue];
3483         if (vnic == NULL) {
3484                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3485                 return -EINVAL;
3486         }
3487
3488         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3489                 rte_memcpy(filter->dst_macaddr,
3490                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3491                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3492         }
3493
3494         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3495                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3496                 filter1 = STAILQ_FIRST(&vnic0->filter);
3497                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3498         } else {
3499                 filter->dst_id = vnic->fw_vnic_id;
3500                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3501                         if (filter->dst_macaddr[i] == 0x00)
3502                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3503                         else
3504                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3505         }
3506
3507         if (filter1 == NULL)
3508                 return -EINVAL;
3509
3510         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3511         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3512
3513         filter->enables = en;
3514
3515         return 0;
3516 }
3517
3518 static struct bnxt_filter_info *
3519 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3520                 struct bnxt_vnic_info **mvnic)
3521 {
3522         struct bnxt_filter_info *mf = NULL;
3523         int i;
3524
3525         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3526                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3527
3528                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3529                         if (mf->filter_type == nf->filter_type &&
3530                             mf->flags == nf->flags &&
3531                             mf->src_port == nf->src_port &&
3532                             mf->src_port_mask == nf->src_port_mask &&
3533                             mf->dst_port == nf->dst_port &&
3534                             mf->dst_port_mask == nf->dst_port_mask &&
3535                             mf->ip_protocol == nf->ip_protocol &&
3536                             mf->ip_addr_type == nf->ip_addr_type &&
3537                             mf->ethertype == nf->ethertype &&
3538                             mf->vni == nf->vni &&
3539                             mf->tunnel_type == nf->tunnel_type &&
3540                             mf->l2_ovlan == nf->l2_ovlan &&
3541                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3542                             mf->l2_ivlan == nf->l2_ivlan &&
3543                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3544                             !memcmp(mf->l2_addr, nf->l2_addr,
3545                                     RTE_ETHER_ADDR_LEN) &&
3546                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3547                                     RTE_ETHER_ADDR_LEN) &&
3548                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3549                                     RTE_ETHER_ADDR_LEN) &&
3550                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3551                                     RTE_ETHER_ADDR_LEN) &&
3552                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3553                                     sizeof(nf->src_ipaddr)) &&
3554                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3555                                     sizeof(nf->src_ipaddr_mask)) &&
3556                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3557                                     sizeof(nf->dst_ipaddr)) &&
3558                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3559                                     sizeof(nf->dst_ipaddr_mask))) {
3560                                 if (mvnic)
3561                                         *mvnic = vnic;
3562                                 return mf;
3563                         }
3564                 }
3565         }
3566         return NULL;
3567 }
3568
3569 static int
3570 bnxt_fdir_filter(struct rte_eth_dev *dev,
3571                  enum rte_filter_op filter_op,
3572                  void *arg)
3573 {
3574         struct bnxt *bp = dev->data->dev_private;
3575         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3576         struct bnxt_filter_info *filter, *match;
3577         struct bnxt_vnic_info *vnic, *mvnic;
3578         int ret = 0, i;
3579
3580         if (filter_op == RTE_ETH_FILTER_NOP)
3581                 return 0;
3582
3583         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3584                 return -EINVAL;
3585
3586         switch (filter_op) {
3587         case RTE_ETH_FILTER_ADD:
3588         case RTE_ETH_FILTER_DELETE:
3589                 /* FALLTHROUGH */
3590                 filter = bnxt_get_unused_filter(bp);
3591                 if (filter == NULL) {
3592                         PMD_DRV_LOG(ERR,
3593                                 "Not enough resources for a new flow.\n");
3594                         return -ENOMEM;
3595                 }
3596
3597                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3598                 if (ret != 0)
3599                         goto free_filter;
3600                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3601
3602                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3603                         vnic = &bp->vnic_info[0];
3604                 else
3605                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3606
3607                 match = bnxt_match_fdir(bp, filter, &mvnic);
3608                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3609                         if (match->dst_id == vnic->fw_vnic_id) {
3610                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3611                                 ret = -EEXIST;
3612                                 goto free_filter;
3613                         } else {
3614                                 match->dst_id = vnic->fw_vnic_id;
3615                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3616                                                                   match->dst_id,
3617                                                                   match);
3618                                 STAILQ_REMOVE(&mvnic->filter, match,
3619                                               bnxt_filter_info, next);
3620                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3621                                 PMD_DRV_LOG(ERR,
3622                                         "Filter with matching pattern exist\n");
3623                                 PMD_DRV_LOG(ERR,
3624                                         "Updated it to new destination q\n");
3625                                 goto free_filter;
3626                         }
3627                 }
3628                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3629                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3630                         ret = -ENOENT;
3631                         goto free_filter;
3632                 }
3633
3634                 if (filter_op == RTE_ETH_FILTER_ADD) {
3635                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3636                                                           filter->dst_id,
3637                                                           filter);
3638                         if (ret)
3639                                 goto free_filter;
3640                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3641                 } else {
3642                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3643                         STAILQ_REMOVE(&vnic->filter, match,
3644                                       bnxt_filter_info, next);
3645                         bnxt_free_filter(bp, match);
3646                         bnxt_free_filter(bp, filter);
3647                 }
3648                 break;
3649         case RTE_ETH_FILTER_FLUSH:
3650                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3651                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3652
3653                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3654                                 if (filter->filter_type ==
3655                                     HWRM_CFA_NTUPLE_FILTER) {
3656                                         ret =
3657                                         bnxt_hwrm_clear_ntuple_filter(bp,
3658                                                                       filter);
3659                                         STAILQ_REMOVE(&vnic->filter, filter,
3660                                                       bnxt_filter_info, next);
3661                                 }
3662                         }
3663                 }
3664                 return ret;
3665         case RTE_ETH_FILTER_UPDATE:
3666         case RTE_ETH_FILTER_STATS:
3667         case RTE_ETH_FILTER_INFO:
3668                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3669                 break;
3670         default:
3671                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3672                 ret = -EINVAL;
3673                 break;
3674         }
3675         return ret;
3676
3677 free_filter:
3678         bnxt_free_filter(bp, filter);
3679         return ret;
3680 }
3681
3682 int
3683 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3684                     enum rte_filter_type filter_type,
3685                     enum rte_filter_op filter_op, void *arg)
3686 {
3687         struct bnxt *bp = dev->data->dev_private;
3688         int ret = 0;
3689
3690         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3691                 struct bnxt_vf_representor *vfr = dev->data->dev_private;
3692                 bp = vfr->parent_dev->data->dev_private;
3693         }
3694
3695         ret = is_bnxt_in_error(bp);
3696         if (ret)
3697                 return ret;
3698
3699         switch (filter_type) {
3700         case RTE_ETH_FILTER_TUNNEL:
3701                 PMD_DRV_LOG(ERR,
3702                         "filter type: %d: To be implemented\n", filter_type);
3703                 break;
3704         case RTE_ETH_FILTER_FDIR:
3705                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3706                 break;
3707         case RTE_ETH_FILTER_NTUPLE:
3708                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3709                 break;
3710         case RTE_ETH_FILTER_ETHERTYPE:
3711                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3712                 break;
3713         case RTE_ETH_FILTER_GENERIC:
3714                 if (filter_op != RTE_ETH_FILTER_GET)
3715                         return -EINVAL;
3716                 if (BNXT_TRUFLOW_EN(bp))
3717                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3718                 else
3719                         *(const void **)arg = &bnxt_flow_ops;
3720                 break;
3721         default:
3722                 PMD_DRV_LOG(ERR,
3723                         "Filter type (%d) not supported", filter_type);
3724                 ret = -EINVAL;
3725                 break;
3726         }
3727         return ret;
3728 }
3729
3730 static const uint32_t *
3731 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3732 {
3733         static const uint32_t ptypes[] = {
3734                 RTE_PTYPE_L2_ETHER_VLAN,
3735                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3736                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3737                 RTE_PTYPE_L4_ICMP,
3738                 RTE_PTYPE_L4_TCP,
3739                 RTE_PTYPE_L4_UDP,
3740                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3741                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3742                 RTE_PTYPE_INNER_L4_ICMP,
3743                 RTE_PTYPE_INNER_L4_TCP,
3744                 RTE_PTYPE_INNER_L4_UDP,
3745                 RTE_PTYPE_UNKNOWN
3746         };
3747
3748         if (!dev->rx_pkt_burst)
3749                 return NULL;
3750
3751         return ptypes;
3752 }
3753
3754 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3755                          int reg_win)
3756 {
3757         uint32_t reg_base = *reg_arr & 0xfffff000;
3758         uint32_t win_off;
3759         int i;
3760
3761         for (i = 0; i < count; i++) {
3762                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3763                         return -ERANGE;
3764         }
3765         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3766         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3767         return 0;
3768 }
3769
3770 static int bnxt_map_ptp_regs(struct bnxt *bp)
3771 {
3772         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3773         uint32_t *reg_arr;
3774         int rc, i;
3775
3776         reg_arr = ptp->rx_regs;
3777         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3778         if (rc)
3779                 return rc;
3780
3781         reg_arr = ptp->tx_regs;
3782         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3783         if (rc)
3784                 return rc;
3785
3786         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3787                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3788
3789         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3790                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3791
3792         return 0;
3793 }
3794
3795 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3796 {
3797         rte_write32(0, (uint8_t *)bp->bar0 +
3798                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3799         rte_write32(0, (uint8_t *)bp->bar0 +
3800                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3801 }
3802
3803 static uint64_t bnxt_cc_read(struct bnxt *bp)
3804 {
3805         uint64_t ns;
3806
3807         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3808                               BNXT_GRCPF_REG_SYNC_TIME));
3809         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3810                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3811         return ns;
3812 }
3813
3814 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3815 {
3816         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3817         uint32_t fifo;
3818
3819         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3820                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3821         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3822                 return -EAGAIN;
3823
3824         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3825                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3826         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3827                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3828         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3829                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3830
3831         return 0;
3832 }
3833
3834 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3835 {
3836         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3837         struct bnxt_pf_info *pf = bp->pf;
3838         uint16_t port_id;
3839         uint32_t fifo;
3840
3841         if (!ptp)
3842                 return -ENODEV;
3843
3844         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3845                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3846         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3847                 return -EAGAIN;
3848
3849         port_id = pf->port_id;
3850         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3851                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3852
3853         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3854                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3855         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3856 /*              bnxt_clr_rx_ts(bp);       TBD  */
3857                 return -EBUSY;
3858         }
3859
3860         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3861                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3862         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3863                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3864
3865         return 0;
3866 }
3867
3868 static int
3869 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3870 {
3871         uint64_t ns;
3872         struct bnxt *bp = dev->data->dev_private;
3873         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3874
3875         if (!ptp)
3876                 return 0;
3877
3878         ns = rte_timespec_to_ns(ts);
3879         /* Set the timecounters to a new value. */
3880         ptp->tc.nsec = ns;
3881
3882         return 0;
3883 }
3884
3885 static int
3886 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3887 {
3888         struct bnxt *bp = dev->data->dev_private;
3889         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3890         uint64_t ns, systime_cycles = 0;
3891         int rc = 0;
3892
3893         if (!ptp)
3894                 return 0;
3895
3896         if (BNXT_CHIP_THOR(bp))
3897                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3898                                              &systime_cycles);
3899         else
3900                 systime_cycles = bnxt_cc_read(bp);
3901
3902         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3903         *ts = rte_ns_to_timespec(ns);
3904
3905         return rc;
3906 }
3907 static int
3908 bnxt_timesync_enable(struct rte_eth_dev *dev)
3909 {
3910         struct bnxt *bp = dev->data->dev_private;
3911         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3912         uint32_t shift = 0;
3913         int rc;
3914
3915         if (!ptp)
3916                 return 0;
3917
3918         ptp->rx_filter = 1;
3919         ptp->tx_tstamp_en = 1;
3920         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3921
3922         rc = bnxt_hwrm_ptp_cfg(bp);
3923         if (rc)
3924                 return rc;
3925
3926         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3927         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3928         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3929
3930         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3931         ptp->tc.cc_shift = shift;
3932         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3933
3934         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3935         ptp->rx_tstamp_tc.cc_shift = shift;
3936         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3937
3938         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3939         ptp->tx_tstamp_tc.cc_shift = shift;
3940         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3941
3942         if (!BNXT_CHIP_THOR(bp))
3943                 bnxt_map_ptp_regs(bp);
3944
3945         return 0;
3946 }
3947
3948 static int
3949 bnxt_timesync_disable(struct rte_eth_dev *dev)
3950 {
3951         struct bnxt *bp = dev->data->dev_private;
3952         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3953
3954         if (!ptp)
3955                 return 0;
3956
3957         ptp->rx_filter = 0;
3958         ptp->tx_tstamp_en = 0;
3959         ptp->rxctl = 0;
3960
3961         bnxt_hwrm_ptp_cfg(bp);
3962
3963         if (!BNXT_CHIP_THOR(bp))
3964                 bnxt_unmap_ptp_regs(bp);
3965
3966         return 0;
3967 }
3968
3969 static int
3970 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3971                                  struct timespec *timestamp,
3972                                  uint32_t flags __rte_unused)
3973 {
3974         struct bnxt *bp = dev->data->dev_private;
3975         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3976         uint64_t rx_tstamp_cycles = 0;
3977         uint64_t ns;
3978
3979         if (!ptp)
3980                 return 0;
3981
3982         if (BNXT_CHIP_THOR(bp))
3983                 rx_tstamp_cycles = ptp->rx_timestamp;
3984         else
3985                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3986
3987         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3988         *timestamp = rte_ns_to_timespec(ns);
3989         return  0;
3990 }
3991
3992 static int
3993 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3994                                  struct timespec *timestamp)
3995 {
3996         struct bnxt *bp = dev->data->dev_private;
3997         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3998         uint64_t tx_tstamp_cycles = 0;
3999         uint64_t ns;
4000         int rc = 0;
4001
4002         if (!ptp)
4003                 return 0;
4004
4005         if (BNXT_CHIP_THOR(bp))
4006                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4007                                              &tx_tstamp_cycles);
4008         else
4009                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4010
4011         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4012         *timestamp = rte_ns_to_timespec(ns);
4013
4014         return rc;
4015 }
4016
4017 static int
4018 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4019 {
4020         struct bnxt *bp = dev->data->dev_private;
4021         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4022
4023         if (!ptp)
4024                 return 0;
4025
4026         ptp->tc.nsec += delta;
4027
4028         return 0;
4029 }
4030
4031 static int
4032 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4033 {
4034         struct bnxt *bp = dev->data->dev_private;
4035         int rc;
4036         uint32_t dir_entries;
4037         uint32_t entry_length;
4038
4039         rc = is_bnxt_in_error(bp);
4040         if (rc)
4041                 return rc;
4042
4043         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4044                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4045                     bp->pdev->addr.devid, bp->pdev->addr.function);
4046
4047         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4048         if (rc != 0)
4049                 return rc;
4050
4051         return dir_entries * entry_length;
4052 }
4053
4054 static int
4055 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4056                 struct rte_dev_eeprom_info *in_eeprom)
4057 {
4058         struct bnxt *bp = dev->data->dev_private;
4059         uint32_t index;
4060         uint32_t offset;
4061         int rc;
4062
4063         rc = is_bnxt_in_error(bp);
4064         if (rc)
4065                 return rc;
4066
4067         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4068                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4069                     bp->pdev->addr.devid, bp->pdev->addr.function,
4070                     in_eeprom->offset, in_eeprom->length);
4071
4072         if (in_eeprom->offset == 0) /* special offset value to get directory */
4073                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4074                                                 in_eeprom->data);
4075
4076         index = in_eeprom->offset >> 24;
4077         offset = in_eeprom->offset & 0xffffff;
4078
4079         if (index != 0)
4080                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4081                                            in_eeprom->length, in_eeprom->data);
4082
4083         return 0;
4084 }
4085
4086 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4087 {
4088         switch (dir_type) {
4089         case BNX_DIR_TYPE_CHIMP_PATCH:
4090         case BNX_DIR_TYPE_BOOTCODE:
4091         case BNX_DIR_TYPE_BOOTCODE_2:
4092         case BNX_DIR_TYPE_APE_FW:
4093         case BNX_DIR_TYPE_APE_PATCH:
4094         case BNX_DIR_TYPE_KONG_FW:
4095         case BNX_DIR_TYPE_KONG_PATCH:
4096         case BNX_DIR_TYPE_BONO_FW:
4097         case BNX_DIR_TYPE_BONO_PATCH:
4098                 /* FALLTHROUGH */
4099                 return true;
4100         }
4101
4102         return false;
4103 }
4104
4105 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4106 {
4107         switch (dir_type) {
4108         case BNX_DIR_TYPE_AVS:
4109         case BNX_DIR_TYPE_EXP_ROM_MBA:
4110         case BNX_DIR_TYPE_PCIE:
4111         case BNX_DIR_TYPE_TSCF_UCODE:
4112         case BNX_DIR_TYPE_EXT_PHY:
4113         case BNX_DIR_TYPE_CCM:
4114         case BNX_DIR_TYPE_ISCSI_BOOT:
4115         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4116         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4117                 /* FALLTHROUGH */
4118                 return true;
4119         }
4120
4121         return false;
4122 }
4123
4124 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4125 {
4126         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4127                 bnxt_dir_type_is_other_exec_format(dir_type);
4128 }
4129
4130 static int
4131 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4132                 struct rte_dev_eeprom_info *in_eeprom)
4133 {
4134         struct bnxt *bp = dev->data->dev_private;
4135         uint8_t index, dir_op;
4136         uint16_t type, ext, ordinal, attr;
4137         int rc;
4138
4139         rc = is_bnxt_in_error(bp);
4140         if (rc)
4141                 return rc;
4142
4143         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4144                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4145                     bp->pdev->addr.devid, bp->pdev->addr.function,
4146                     in_eeprom->offset, in_eeprom->length);
4147
4148         if (!BNXT_PF(bp)) {
4149                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4150                 return -EINVAL;
4151         }
4152
4153         type = in_eeprom->magic >> 16;
4154
4155         if (type == 0xffff) { /* special value for directory operations */
4156                 index = in_eeprom->magic & 0xff;
4157                 dir_op = in_eeprom->magic >> 8;
4158                 if (index == 0)
4159                         return -EINVAL;
4160                 switch (dir_op) {
4161                 case 0x0e: /* erase */
4162                         if (in_eeprom->offset != ~in_eeprom->magic)
4163                                 return -EINVAL;
4164                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4165                 default:
4166                         return -EINVAL;
4167                 }
4168         }
4169
4170         /* Create or re-write an NVM item: */
4171         if (bnxt_dir_type_is_executable(type) == true)
4172                 return -EOPNOTSUPP;
4173         ext = in_eeprom->magic & 0xffff;
4174         ordinal = in_eeprom->offset >> 16;
4175         attr = in_eeprom->offset & 0xffff;
4176
4177         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4178                                      in_eeprom->data, in_eeprom->length);
4179 }
4180
4181 /*
4182  * Initialization
4183  */
4184
4185 static const struct eth_dev_ops bnxt_dev_ops = {
4186         .dev_infos_get = bnxt_dev_info_get_op,
4187         .dev_close = bnxt_dev_close_op,
4188         .dev_configure = bnxt_dev_configure_op,
4189         .dev_start = bnxt_dev_start_op,
4190         .dev_stop = bnxt_dev_stop_op,
4191         .dev_set_link_up = bnxt_dev_set_link_up_op,
4192         .dev_set_link_down = bnxt_dev_set_link_down_op,
4193         .stats_get = bnxt_stats_get_op,
4194         .stats_reset = bnxt_stats_reset_op,
4195         .rx_queue_setup = bnxt_rx_queue_setup_op,
4196         .rx_queue_release = bnxt_rx_queue_release_op,
4197         .tx_queue_setup = bnxt_tx_queue_setup_op,
4198         .tx_queue_release = bnxt_tx_queue_release_op,
4199         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4200         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4201         .reta_update = bnxt_reta_update_op,
4202         .reta_query = bnxt_reta_query_op,
4203         .rss_hash_update = bnxt_rss_hash_update_op,
4204         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4205         .link_update = bnxt_link_update_op,
4206         .promiscuous_enable = bnxt_promiscuous_enable_op,
4207         .promiscuous_disable = bnxt_promiscuous_disable_op,
4208         .allmulticast_enable = bnxt_allmulticast_enable_op,
4209         .allmulticast_disable = bnxt_allmulticast_disable_op,
4210         .mac_addr_add = bnxt_mac_addr_add_op,
4211         .mac_addr_remove = bnxt_mac_addr_remove_op,
4212         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4213         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4214         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4215         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4216         .vlan_filter_set = bnxt_vlan_filter_set_op,
4217         .vlan_offload_set = bnxt_vlan_offload_set_op,
4218         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4219         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4220         .mtu_set = bnxt_mtu_set_op,
4221         .mac_addr_set = bnxt_set_default_mac_addr_op,
4222         .xstats_get = bnxt_dev_xstats_get_op,
4223         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4224         .xstats_reset = bnxt_dev_xstats_reset_op,
4225         .fw_version_get = bnxt_fw_version_get,
4226         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4227         .rxq_info_get = bnxt_rxq_info_get_op,
4228         .txq_info_get = bnxt_txq_info_get_op,
4229         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4230         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4231         .dev_led_on = bnxt_dev_led_on_op,
4232         .dev_led_off = bnxt_dev_led_off_op,
4233         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4234         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4235         .rx_queue_count = bnxt_rx_queue_count_op,
4236         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4237         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4238         .rx_queue_start = bnxt_rx_queue_start,
4239         .rx_queue_stop = bnxt_rx_queue_stop,
4240         .tx_queue_start = bnxt_tx_queue_start,
4241         .tx_queue_stop = bnxt_tx_queue_stop,
4242         .filter_ctrl = bnxt_filter_ctrl_op,
4243         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4244         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4245         .get_eeprom           = bnxt_get_eeprom_op,
4246         .set_eeprom           = bnxt_set_eeprom_op,
4247         .timesync_enable      = bnxt_timesync_enable,
4248         .timesync_disable     = bnxt_timesync_disable,
4249         .timesync_read_time   = bnxt_timesync_read_time,
4250         .timesync_write_time   = bnxt_timesync_write_time,
4251         .timesync_adjust_time = bnxt_timesync_adjust_time,
4252         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4253         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4254 };
4255
4256 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4257 {
4258         uint32_t offset;
4259
4260         /* Only pre-map the reset GRC registers using window 3 */
4261         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4262                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4263
4264         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4265
4266         return offset;
4267 }
4268
4269 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4270 {
4271         struct bnxt_error_recovery_info *info = bp->recovery_info;
4272         uint32_t reg_base = 0xffffffff;
4273         int i;
4274
4275         /* Only pre-map the monitoring GRC registers using window 2 */
4276         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4277                 uint32_t reg = info->status_regs[i];
4278
4279                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4280                         continue;
4281
4282                 if (reg_base == 0xffffffff)
4283                         reg_base = reg & 0xfffff000;
4284                 if ((reg & 0xfffff000) != reg_base)
4285                         return -ERANGE;
4286
4287                 /* Use mask 0xffc as the Lower 2 bits indicates
4288                  * address space location
4289                  */
4290                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4291                                                 (reg & 0xffc);
4292         }
4293
4294         if (reg_base == 0xffffffff)
4295                 return 0;
4296
4297         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4298                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4299
4300         return 0;
4301 }
4302
4303 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4304 {
4305         struct bnxt_error_recovery_info *info = bp->recovery_info;
4306         uint32_t delay = info->delay_after_reset[index];
4307         uint32_t val = info->reset_reg_val[index];
4308         uint32_t reg = info->reset_reg[index];
4309         uint32_t type, offset;
4310
4311         type = BNXT_FW_STATUS_REG_TYPE(reg);
4312         offset = BNXT_FW_STATUS_REG_OFF(reg);
4313
4314         switch (type) {
4315         case BNXT_FW_STATUS_REG_TYPE_CFG:
4316                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4317                 break;
4318         case BNXT_FW_STATUS_REG_TYPE_GRC:
4319                 offset = bnxt_map_reset_regs(bp, offset);
4320                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4321                 break;
4322         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4323                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4324                 break;
4325         }
4326         /* wait on a specific interval of time until core reset is complete */
4327         if (delay)
4328                 rte_delay_ms(delay);
4329 }
4330
4331 static void bnxt_dev_cleanup(struct bnxt *bp)
4332 {
4333         bnxt_set_hwrm_link_config(bp, false);
4334         bp->link_info->link_up = 0;
4335         if (bp->eth_dev->data->dev_started)
4336                 bnxt_dev_stop_op(bp->eth_dev);
4337
4338         bnxt_uninit_resources(bp, true);
4339 }
4340
4341 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4342 {
4343         struct rte_eth_dev *dev = bp->eth_dev;
4344         struct rte_vlan_filter_conf *vfc;
4345         int vidx, vbit, rc;
4346         uint16_t vlan_id;
4347
4348         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4349                 vfc = &dev->data->vlan_filter_conf;
4350                 vidx = vlan_id / 64;
4351                 vbit = vlan_id % 64;
4352
4353                 /* Each bit corresponds to a VLAN id */
4354                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4355                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4356                         if (rc)
4357                                 return rc;
4358                 }
4359         }
4360
4361         return 0;
4362 }
4363
4364 static int bnxt_restore_mac_filters(struct bnxt *bp)
4365 {
4366         struct rte_eth_dev *dev = bp->eth_dev;
4367         struct rte_eth_dev_info dev_info;
4368         struct rte_ether_addr *addr;
4369         uint64_t pool_mask;
4370         uint32_t pool = 0;
4371         uint16_t i;
4372         int rc;
4373
4374         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4375                 return 0;
4376
4377         rc = bnxt_dev_info_get_op(dev, &dev_info);
4378         if (rc)
4379                 return rc;
4380
4381         /* replay MAC address configuration */
4382         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4383                 addr = &dev->data->mac_addrs[i];
4384
4385                 /* skip zero address */
4386                 if (rte_is_zero_ether_addr(addr))
4387                         continue;
4388
4389                 pool = 0;
4390                 pool_mask = dev->data->mac_pool_sel[i];
4391
4392                 do {
4393                         if (pool_mask & 1ULL) {
4394                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4395                                 if (rc)
4396                                         return rc;
4397                         }
4398                         pool_mask >>= 1;
4399                         pool++;
4400                 } while (pool_mask);
4401         }
4402
4403         return 0;
4404 }
4405
4406 static int bnxt_restore_filters(struct bnxt *bp)
4407 {
4408         struct rte_eth_dev *dev = bp->eth_dev;
4409         int ret = 0;
4410
4411         if (dev->data->all_multicast) {
4412                 ret = bnxt_allmulticast_enable_op(dev);
4413                 if (ret)
4414                         return ret;
4415         }
4416         if (dev->data->promiscuous) {
4417                 ret = bnxt_promiscuous_enable_op(dev);
4418                 if (ret)
4419                         return ret;
4420         }
4421
4422         ret = bnxt_restore_mac_filters(bp);
4423         if (ret)
4424                 return ret;
4425
4426         ret = bnxt_restore_vlan_filters(bp);
4427         /* TODO restore other filters as well */
4428         return ret;
4429 }
4430
4431 static void bnxt_dev_recover(void *arg)
4432 {
4433         struct bnxt *bp = arg;
4434         int timeout = bp->fw_reset_max_msecs;
4435         int rc = 0;
4436
4437         /* Clear Error flag so that device re-init should happen */
4438         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4439
4440         do {
4441                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4442                 if (rc == 0)
4443                         break;
4444                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4445                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4446         } while (rc && timeout);
4447
4448         if (rc) {
4449                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4450                 goto err;
4451         }
4452
4453         rc = bnxt_init_resources(bp, true);
4454         if (rc) {
4455                 PMD_DRV_LOG(ERR,
4456                             "Failed to initialize resources after reset\n");
4457                 goto err;
4458         }
4459         /* clear reset flag as the device is initialized now */
4460         bp->flags &= ~BNXT_FLAG_FW_RESET;
4461
4462         rc = bnxt_dev_start_op(bp->eth_dev);
4463         if (rc) {
4464                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4465                 goto err_start;
4466         }
4467
4468         rc = bnxt_restore_filters(bp);
4469         if (rc)
4470                 goto err_start;
4471
4472         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4473         return;
4474 err_start:
4475         bnxt_dev_stop_op(bp->eth_dev);
4476 err:
4477         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4478         bnxt_uninit_resources(bp, false);
4479         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4480 }
4481
4482 void bnxt_dev_reset_and_resume(void *arg)
4483 {
4484         struct bnxt *bp = arg;
4485         int rc;
4486
4487         bnxt_dev_cleanup(bp);
4488
4489         bnxt_wait_for_device_shutdown(bp);
4490
4491         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4492                                bnxt_dev_recover, (void *)bp);
4493         if (rc)
4494                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4495 }
4496
4497 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4498 {
4499         struct bnxt_error_recovery_info *info = bp->recovery_info;
4500         uint32_t reg = info->status_regs[index];
4501         uint32_t type, offset, val = 0;
4502
4503         type = BNXT_FW_STATUS_REG_TYPE(reg);
4504         offset = BNXT_FW_STATUS_REG_OFF(reg);
4505
4506         switch (type) {
4507         case BNXT_FW_STATUS_REG_TYPE_CFG:
4508                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4509                 break;
4510         case BNXT_FW_STATUS_REG_TYPE_GRC:
4511                 offset = info->mapped_status_regs[index];
4512                 /* FALLTHROUGH */
4513         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4514                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4515                                        offset));
4516                 break;
4517         }
4518
4519         return val;
4520 }
4521
4522 static int bnxt_fw_reset_all(struct bnxt *bp)
4523 {
4524         struct bnxt_error_recovery_info *info = bp->recovery_info;
4525         uint32_t i;
4526         int rc = 0;
4527
4528         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4529                 /* Reset through master function driver */
4530                 for (i = 0; i < info->reg_array_cnt; i++)
4531                         bnxt_write_fw_reset_reg(bp, i);
4532                 /* Wait for time specified by FW after triggering reset */
4533                 rte_delay_ms(info->master_func_wait_period_after_reset);
4534         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4535                 /* Reset with the help of Kong processor */
4536                 rc = bnxt_hwrm_fw_reset(bp);
4537                 if (rc)
4538                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4539         }
4540
4541         return rc;
4542 }
4543
4544 static void bnxt_fw_reset_cb(void *arg)
4545 {
4546         struct bnxt *bp = arg;
4547         struct bnxt_error_recovery_info *info = bp->recovery_info;
4548         int rc = 0;
4549
4550         /* Only Master function can do FW reset */
4551         if (bnxt_is_master_func(bp) &&
4552             bnxt_is_recovery_enabled(bp)) {
4553                 rc = bnxt_fw_reset_all(bp);
4554                 if (rc) {
4555                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4556                         return;
4557                 }
4558         }
4559
4560         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4561          * EXCEPTION_FATAL_ASYNC event to all the functions
4562          * (including MASTER FUNC). After receiving this Async, all the active
4563          * drivers should treat this case as FW initiated recovery
4564          */
4565         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4566                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4567                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4568
4569                 /* To recover from error */
4570                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4571                                   (void *)bp);
4572         }
4573 }
4574
4575 /* Driver should poll FW heartbeat, reset_counter with the frequency
4576  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4577  * When the driver detects heartbeat stop or change in reset_counter,
4578  * it has to trigger a reset to recover from the error condition.
4579  * A “master PF” is the function who will have the privilege to
4580  * initiate the chimp reset. The master PF will be elected by the
4581  * firmware and will be notified through async message.
4582  */
4583 static void bnxt_check_fw_health(void *arg)
4584 {
4585         struct bnxt *bp = arg;
4586         struct bnxt_error_recovery_info *info = bp->recovery_info;
4587         uint32_t val = 0, wait_msec;
4588
4589         if (!info || !bnxt_is_recovery_enabled(bp) ||
4590             is_bnxt_in_error(bp))
4591                 return;
4592
4593         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4594         if (val == info->last_heart_beat)
4595                 goto reset;
4596
4597         info->last_heart_beat = val;
4598
4599         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4600         if (val != info->last_reset_counter)
4601                 goto reset;
4602
4603         info->last_reset_counter = val;
4604
4605         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4606                           bnxt_check_fw_health, (void *)bp);
4607
4608         return;
4609 reset:
4610         /* Stop DMA to/from device */
4611         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4612         bp->flags |= BNXT_FLAG_FW_RESET;
4613
4614         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4615
4616         if (bnxt_is_master_func(bp))
4617                 wait_msec = info->master_func_wait_period;
4618         else
4619                 wait_msec = info->normal_func_wait_period;
4620
4621         rte_eal_alarm_set(US_PER_MS * wait_msec,
4622                           bnxt_fw_reset_cb, (void *)bp);
4623 }
4624
4625 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4626 {
4627         uint32_t polling_freq;
4628
4629         if (!bnxt_is_recovery_enabled(bp))
4630                 return;
4631
4632         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4633                 return;
4634
4635         polling_freq = bp->recovery_info->driver_polling_freq;
4636
4637         rte_eal_alarm_set(US_PER_MS * polling_freq,
4638                           bnxt_check_fw_health, (void *)bp);
4639         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4640 }
4641
4642 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4643 {
4644         if (!bnxt_is_recovery_enabled(bp))
4645                 return;
4646
4647         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4648         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4649 }
4650
4651 static bool bnxt_vf_pciid(uint16_t device_id)
4652 {
4653         switch (device_id) {
4654         case BROADCOM_DEV_ID_57304_VF:
4655         case BROADCOM_DEV_ID_57406_VF:
4656         case BROADCOM_DEV_ID_5731X_VF:
4657         case BROADCOM_DEV_ID_5741X_VF:
4658         case BROADCOM_DEV_ID_57414_VF:
4659         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4660         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4661         case BROADCOM_DEV_ID_58802_VF:
4662         case BROADCOM_DEV_ID_57500_VF1:
4663         case BROADCOM_DEV_ID_57500_VF2:
4664                 /* FALLTHROUGH */
4665                 return true;
4666         default:
4667                 return false;
4668         }
4669 }
4670
4671 static bool bnxt_thor_device(uint16_t device_id)
4672 {
4673         switch (device_id) {
4674         case BROADCOM_DEV_ID_57508:
4675         case BROADCOM_DEV_ID_57504:
4676         case BROADCOM_DEV_ID_57502:
4677         case BROADCOM_DEV_ID_57508_MF1:
4678         case BROADCOM_DEV_ID_57504_MF1:
4679         case BROADCOM_DEV_ID_57502_MF1:
4680         case BROADCOM_DEV_ID_57508_MF2:
4681         case BROADCOM_DEV_ID_57504_MF2:
4682         case BROADCOM_DEV_ID_57502_MF2:
4683         case BROADCOM_DEV_ID_57500_VF1:
4684         case BROADCOM_DEV_ID_57500_VF2:
4685                 /* FALLTHROUGH */
4686                 return true;
4687         default:
4688                 return false;
4689         }
4690 }
4691
4692 bool bnxt_stratus_device(struct bnxt *bp)
4693 {
4694         uint16_t device_id = bp->pdev->id.device_id;
4695
4696         switch (device_id) {
4697         case BROADCOM_DEV_ID_STRATUS_NIC:
4698         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4699         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4700                 /* FALLTHROUGH */
4701                 return true;
4702         default:
4703                 return false;
4704         }
4705 }
4706
4707 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4708 {
4709         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4710         struct bnxt *bp = eth_dev->data->dev_private;
4711
4712         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4713         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4714         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4715         if (!bp->bar0 || !bp->doorbell_base) {
4716                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4717                 return -ENODEV;
4718         }
4719
4720         bp->eth_dev = eth_dev;
4721         bp->pdev = pci_dev;
4722
4723         return 0;
4724 }
4725
4726 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4727                                   struct bnxt_ctx_pg_info *ctx_pg,
4728                                   uint32_t mem_size,
4729                                   const char *suffix,
4730                                   uint16_t idx)
4731 {
4732         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4733         const struct rte_memzone *mz = NULL;
4734         char mz_name[RTE_MEMZONE_NAMESIZE];
4735         rte_iova_t mz_phys_addr;
4736         uint64_t valid_bits = 0;
4737         uint32_t sz;
4738         int i;
4739
4740         if (!mem_size)
4741                 return 0;
4742
4743         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4744                          BNXT_PAGE_SIZE;
4745         rmem->page_size = BNXT_PAGE_SIZE;
4746         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4747         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4748         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4749
4750         valid_bits = PTU_PTE_VALID;
4751
4752         if (rmem->nr_pages > 1) {
4753                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4754                          "bnxt_ctx_pg_tbl%s_%x_%d",
4755                          suffix, idx, bp->eth_dev->data->port_id);
4756                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4757                 mz = rte_memzone_lookup(mz_name);
4758                 if (!mz) {
4759                         mz = rte_memzone_reserve_aligned(mz_name,
4760                                                 rmem->nr_pages * 8,
4761                                                 SOCKET_ID_ANY,
4762                                                 RTE_MEMZONE_2MB |
4763                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4764                                                 RTE_MEMZONE_IOVA_CONTIG,
4765                                                 BNXT_PAGE_SIZE);
4766                         if (mz == NULL)
4767                                 return -ENOMEM;
4768                 }
4769
4770                 memset(mz->addr, 0, mz->len);
4771                 mz_phys_addr = mz->iova;
4772
4773                 rmem->pg_tbl = mz->addr;
4774                 rmem->pg_tbl_map = mz_phys_addr;
4775                 rmem->pg_tbl_mz = mz;
4776         }
4777
4778         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4779                  suffix, idx, bp->eth_dev->data->port_id);
4780         mz = rte_memzone_lookup(mz_name);
4781         if (!mz) {
4782                 mz = rte_memzone_reserve_aligned(mz_name,
4783                                                  mem_size,
4784                                                  SOCKET_ID_ANY,
4785                                                  RTE_MEMZONE_1GB |
4786                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4787                                                  RTE_MEMZONE_IOVA_CONTIG,
4788                                                  BNXT_PAGE_SIZE);
4789                 if (mz == NULL)
4790                         return -ENOMEM;
4791         }
4792
4793         memset(mz->addr, 0, mz->len);
4794         mz_phys_addr = mz->iova;
4795
4796         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4797                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4798                 rmem->dma_arr[i] = mz_phys_addr + sz;
4799
4800                 if (rmem->nr_pages > 1) {
4801                         if (i == rmem->nr_pages - 2 &&
4802                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4803                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4804                         else if (i == rmem->nr_pages - 1 &&
4805                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4806                                 valid_bits |= PTU_PTE_LAST;
4807
4808                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4809                                                            valid_bits);
4810                 }
4811         }
4812
4813         rmem->mz = mz;
4814         if (rmem->vmem_size)
4815                 rmem->vmem = (void **)mz->addr;
4816         rmem->dma_arr[0] = mz_phys_addr;
4817         return 0;
4818 }
4819
4820 static void bnxt_free_ctx_mem(struct bnxt *bp)
4821 {
4822         int i;
4823
4824         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4825                 return;
4826
4827         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4828         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4829         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4830         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4831         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4832         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4833         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4834         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4835         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4836         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4837         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4838
4839         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4840                 if (bp->ctx->tqm_mem[i])
4841                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4842         }
4843
4844         rte_free(bp->ctx);
4845         bp->ctx = NULL;
4846 }
4847
4848 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4849
4850 #define min_t(type, x, y) ({                    \
4851         type __min1 = (x);                      \
4852         type __min2 = (y);                      \
4853         __min1 < __min2 ? __min1 : __min2; })
4854
4855 #define max_t(type, x, y) ({                    \
4856         type __max1 = (x);                      \
4857         type __max2 = (y);                      \
4858         __max1 > __max2 ? __max1 : __max2; })
4859
4860 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4861
4862 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4863 {
4864         struct bnxt_ctx_pg_info *ctx_pg;
4865         struct bnxt_ctx_mem_info *ctx;
4866         uint32_t mem_size, ena, entries;
4867         uint32_t entries_sp, min;
4868         int i, rc;
4869
4870         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4871         if (rc) {
4872                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4873                 return rc;
4874         }
4875         ctx = bp->ctx;
4876         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4877                 return 0;
4878
4879         ctx_pg = &ctx->qp_mem;
4880         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4881         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4882         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4883         if (rc)
4884                 return rc;
4885
4886         ctx_pg = &ctx->srq_mem;
4887         ctx_pg->entries = ctx->srq_max_l2_entries;
4888         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4889         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4890         if (rc)
4891                 return rc;
4892
4893         ctx_pg = &ctx->cq_mem;
4894         ctx_pg->entries = ctx->cq_max_l2_entries;
4895         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4896         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4897         if (rc)
4898                 return rc;
4899
4900         ctx_pg = &ctx->vnic_mem;
4901         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4902                 ctx->vnic_max_ring_table_entries;
4903         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4904         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4905         if (rc)
4906                 return rc;
4907
4908         ctx_pg = &ctx->stat_mem;
4909         ctx_pg->entries = ctx->stat_max_entries;
4910         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4911         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4912         if (rc)
4913                 return rc;
4914
4915         min = ctx->tqm_min_entries_per_ring;
4916
4917         entries_sp = ctx->qp_max_l2_entries +
4918                      ctx->vnic_max_vnic_entries +
4919                      2 * ctx->qp_min_qp1_entries + min;
4920         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4921
4922         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4923         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4924         entries = clamp_t(uint32_t, entries, min,
4925                           ctx->tqm_max_entries_per_ring);
4926         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4927                 ctx_pg = ctx->tqm_mem[i];
4928                 ctx_pg->entries = i ? entries : entries_sp;
4929                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4930                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4931                 if (rc)
4932                         return rc;
4933                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4934         }
4935
4936         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4937         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4938         if (rc)
4939                 PMD_DRV_LOG(ERR,
4940                             "Failed to configure context mem: rc = %d\n", rc);
4941         else
4942                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4943
4944         return rc;
4945 }
4946
4947 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4948 {
4949         struct rte_pci_device *pci_dev = bp->pdev;
4950         char mz_name[RTE_MEMZONE_NAMESIZE];
4951         const struct rte_memzone *mz = NULL;
4952         uint32_t total_alloc_len;
4953         rte_iova_t mz_phys_addr;
4954
4955         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4956                 return 0;
4957
4958         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4959                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4960                  pci_dev->addr.bus, pci_dev->addr.devid,
4961                  pci_dev->addr.function, "rx_port_stats");
4962         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4963         mz = rte_memzone_lookup(mz_name);
4964         total_alloc_len =
4965                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4966                                        sizeof(struct rx_port_stats_ext) + 512);
4967         if (!mz) {
4968                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4969                                          SOCKET_ID_ANY,
4970                                          RTE_MEMZONE_2MB |
4971                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4972                                          RTE_MEMZONE_IOVA_CONTIG);
4973                 if (mz == NULL)
4974                         return -ENOMEM;
4975         }
4976         memset(mz->addr, 0, mz->len);
4977         mz_phys_addr = mz->iova;
4978
4979         bp->rx_mem_zone = (const void *)mz;
4980         bp->hw_rx_port_stats = mz->addr;
4981         bp->hw_rx_port_stats_map = mz_phys_addr;
4982
4983         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4984                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4985                  pci_dev->addr.bus, pci_dev->addr.devid,
4986                  pci_dev->addr.function, "tx_port_stats");
4987         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4988         mz = rte_memzone_lookup(mz_name);
4989         total_alloc_len =
4990                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4991                                        sizeof(struct tx_port_stats_ext) + 512);
4992         if (!mz) {
4993                 mz = rte_memzone_reserve(mz_name,
4994                                          total_alloc_len,
4995                                          SOCKET_ID_ANY,
4996                                          RTE_MEMZONE_2MB |
4997                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4998                                          RTE_MEMZONE_IOVA_CONTIG);
4999                 if (mz == NULL)
5000                         return -ENOMEM;
5001         }
5002         memset(mz->addr, 0, mz->len);
5003         mz_phys_addr = mz->iova;
5004
5005         bp->tx_mem_zone = (const void *)mz;
5006         bp->hw_tx_port_stats = mz->addr;
5007         bp->hw_tx_port_stats_map = mz_phys_addr;
5008         bp->flags |= BNXT_FLAG_PORT_STATS;
5009
5010         /* Display extended statistics if FW supports it */
5011         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5012             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5013             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5014                 return 0;
5015
5016         bp->hw_rx_port_stats_ext = (void *)
5017                 ((uint8_t *)bp->hw_rx_port_stats +
5018                  sizeof(struct rx_port_stats));
5019         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5020                 sizeof(struct rx_port_stats);
5021         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5022
5023         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5024             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5025                 bp->hw_tx_port_stats_ext = (void *)
5026                         ((uint8_t *)bp->hw_tx_port_stats +
5027                          sizeof(struct tx_port_stats));
5028                 bp->hw_tx_port_stats_ext_map =
5029                         bp->hw_tx_port_stats_map +
5030                         sizeof(struct tx_port_stats);
5031                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5032         }
5033
5034         return 0;
5035 }
5036
5037 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5038 {
5039         struct bnxt *bp = eth_dev->data->dev_private;
5040         int rc = 0;
5041
5042         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5043                                                RTE_ETHER_ADDR_LEN *
5044                                                bp->max_l2_ctx,
5045                                                0);
5046         if (eth_dev->data->mac_addrs == NULL) {
5047                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5048                 return -ENOMEM;
5049         }
5050
5051         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5052                 if (BNXT_PF(bp))
5053                         return -EINVAL;
5054
5055                 /* Generate a random MAC address, if none was assigned by PF */
5056                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5057                 bnxt_eth_hw_addr_random(bp->mac_addr);
5058                 PMD_DRV_LOG(INFO,
5059                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5060                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5061                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5062
5063                 rc = bnxt_hwrm_set_mac(bp);
5064                 if (rc)
5065                         return rc;
5066         }
5067
5068         /* Copy the permanent MAC from the FUNC_QCAPS response */
5069         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5070
5071         return rc;
5072 }
5073
5074 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5075 {
5076         int rc = 0;
5077
5078         /* MAC is already configured in FW */
5079         if (BNXT_HAS_DFLT_MAC_SET(bp))
5080                 return 0;
5081
5082         /* Restore the old MAC configured */
5083         rc = bnxt_hwrm_set_mac(bp);
5084         if (rc)
5085                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5086
5087         return rc;
5088 }
5089
5090 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5091 {
5092         if (!BNXT_PF(bp))
5093                 return;
5094
5095 #define ALLOW_FUNC(x)   \
5096         { \
5097                 uint32_t arg = (x); \
5098                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5099                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5100         }
5101
5102         /* Forward all requests if firmware is new enough */
5103         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5104              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5105             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5106                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5107         } else {
5108                 PMD_DRV_LOG(WARNING,
5109                             "Firmware too old for VF mailbox functionality\n");
5110                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5111         }
5112
5113         /*
5114          * The following are used for driver cleanup. If we disallow these,
5115          * VF drivers can't clean up cleanly.
5116          */
5117         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5118         ALLOW_FUNC(HWRM_VNIC_FREE);
5119         ALLOW_FUNC(HWRM_RING_FREE);
5120         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5121         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5122         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5123         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5124         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5125         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5126 }
5127
5128 uint16_t
5129 bnxt_get_svif(uint16_t port_id, bool func_svif,
5130               enum bnxt_ulp_intf_type type)
5131 {
5132         struct rte_eth_dev *eth_dev;
5133         struct bnxt *bp;
5134
5135         eth_dev = &rte_eth_devices[port_id];
5136         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5137                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5138                 if (!vfr)
5139                         return 0;
5140
5141                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5142                         return vfr->svif;
5143
5144                 eth_dev = vfr->parent_dev;
5145         }
5146
5147         bp = eth_dev->data->dev_private;
5148
5149         return func_svif ? bp->func_svif : bp->port_svif;
5150 }
5151
5152 uint16_t
5153 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5154 {
5155         struct rte_eth_dev *eth_dev;
5156         struct bnxt_vnic_info *vnic;
5157         struct bnxt *bp;
5158
5159         eth_dev = &rte_eth_devices[port];
5160         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5161                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5162                 if (!vfr)
5163                         return 0;
5164
5165                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5166                         return vfr->dflt_vnic_id;
5167
5168                 eth_dev = vfr->parent_dev;
5169         }
5170
5171         bp = eth_dev->data->dev_private;
5172
5173         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5174
5175         return vnic->fw_vnic_id;
5176 }
5177
5178 uint16_t
5179 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5180 {
5181         struct rte_eth_dev *eth_dev;
5182         struct bnxt *bp;
5183
5184         eth_dev = &rte_eth_devices[port];
5185         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5186                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5187                 if (!vfr)
5188                         return 0;
5189
5190                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5191                         return vfr->fw_fid;
5192
5193                 eth_dev = vfr->parent_dev;
5194         }
5195
5196         bp = eth_dev->data->dev_private;
5197
5198         return bp->fw_fid;
5199 }
5200
5201 enum bnxt_ulp_intf_type
5202 bnxt_get_interface_type(uint16_t port)
5203 {
5204         struct rte_eth_dev *eth_dev;
5205         struct bnxt *bp;
5206
5207         eth_dev = &rte_eth_devices[port];
5208         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5209                 return BNXT_ULP_INTF_TYPE_VF_REP;
5210
5211         bp = eth_dev->data->dev_private;
5212         if (BNXT_PF(bp))
5213                 return BNXT_ULP_INTF_TYPE_PF;
5214         else if (BNXT_VF_IS_TRUSTED(bp))
5215                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5216         else if (BNXT_VF(bp))
5217                 return BNXT_ULP_INTF_TYPE_VF;
5218
5219         return BNXT_ULP_INTF_TYPE_INVALID;
5220 }
5221
5222 uint16_t
5223 bnxt_get_phy_port_id(uint16_t port_id)
5224 {
5225         struct bnxt_vf_representor *vfr;
5226         struct rte_eth_dev *eth_dev;
5227         struct bnxt *bp;
5228
5229         eth_dev = &rte_eth_devices[port_id];
5230         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5231                 vfr = eth_dev->data->dev_private;
5232                 if (!vfr)
5233                         return 0;
5234
5235                 eth_dev = vfr->parent_dev;
5236         }
5237
5238         bp = eth_dev->data->dev_private;
5239
5240         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5241 }
5242
5243 uint16_t
5244 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5245 {
5246         struct rte_eth_dev *eth_dev;
5247         struct bnxt *bp;
5248
5249         eth_dev = &rte_eth_devices[port_id];
5250         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5251                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5252                 if (!vfr)
5253                         return 0;
5254
5255                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5256                         return vfr->fw_fid - 1;
5257
5258                 eth_dev = vfr->parent_dev;
5259         }
5260
5261         bp = eth_dev->data->dev_private;
5262
5263         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5264 }
5265
5266 uint16_t
5267 bnxt_get_vport(uint16_t port_id)
5268 {
5269         return (1 << bnxt_get_phy_port_id(port_id));
5270 }
5271
5272 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5273 {
5274         struct bnxt_error_recovery_info *info = bp->recovery_info;
5275
5276         if (info) {
5277                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5278                         memset(info, 0, sizeof(*info));
5279                 return;
5280         }
5281
5282         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5283                 return;
5284
5285         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5286                            sizeof(*info), 0);
5287         if (!info)
5288                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5289
5290         bp->recovery_info = info;
5291 }
5292
5293 static void bnxt_check_fw_status(struct bnxt *bp)
5294 {
5295         uint32_t fw_status;
5296
5297         if (!(bp->recovery_info &&
5298               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5299                 return;
5300
5301         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5302         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5303                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5304                             fw_status);
5305 }
5306
5307 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5308 {
5309         struct bnxt_error_recovery_info *info = bp->recovery_info;
5310         uint32_t status_loc;
5311         uint32_t sig_ver;
5312
5313         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5314                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5315         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5316                                    BNXT_GRCP_WINDOW_2_BASE +
5317                                    offsetof(struct hcomm_status,
5318                                             sig_ver)));
5319         /* If the signature is absent, then FW does not support this feature */
5320         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5321             HCOMM_STATUS_SIGNATURE_VAL)
5322                 return 0;
5323
5324         if (!info) {
5325                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5326                                    sizeof(*info), 0);
5327                 if (!info)
5328                         return -ENOMEM;
5329                 bp->recovery_info = info;
5330         } else {
5331                 memset(info, 0, sizeof(*info));
5332         }
5333
5334         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5335                                       BNXT_GRCP_WINDOW_2_BASE +
5336                                       offsetof(struct hcomm_status,
5337                                                fw_status_loc)));
5338
5339         /* Only pre-map the FW health status GRC register */
5340         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5341                 return 0;
5342
5343         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5344         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5345                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5346
5347         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5348                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5349
5350         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5351
5352         return 0;
5353 }
5354
5355 static int bnxt_init_fw(struct bnxt *bp)
5356 {
5357         uint16_t mtu;
5358         int rc = 0;
5359
5360         bp->fw_cap = 0;
5361
5362         rc = bnxt_map_hcomm_fw_status_reg(bp);
5363         if (rc)
5364                 return rc;
5365
5366         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5367         if (rc) {
5368                 bnxt_check_fw_status(bp);
5369                 return rc;
5370         }
5371
5372         rc = bnxt_hwrm_func_reset(bp);
5373         if (rc)
5374                 return -EIO;
5375
5376         rc = bnxt_hwrm_vnic_qcaps(bp);
5377         if (rc)
5378                 return rc;
5379
5380         rc = bnxt_hwrm_queue_qportcfg(bp);
5381         if (rc)
5382                 return rc;
5383
5384         /* Get the MAX capabilities for this function.
5385          * This function also allocates context memory for TQM rings and
5386          * informs the firmware about this allocated backing store memory.
5387          */
5388         rc = bnxt_hwrm_func_qcaps(bp);
5389         if (rc)
5390                 return rc;
5391
5392         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5393         if (rc)
5394                 return rc;
5395
5396         bnxt_hwrm_port_mac_qcfg(bp);
5397
5398         bnxt_hwrm_parent_pf_qcfg(bp);
5399
5400         bnxt_hwrm_port_phy_qcaps(bp);
5401
5402         bnxt_alloc_error_recovery_info(bp);
5403         /* Get the adapter error recovery support info */
5404         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5405         if (rc)
5406                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5407
5408         bnxt_hwrm_port_led_qcaps(bp);
5409
5410         return 0;
5411 }
5412
5413 static int
5414 bnxt_init_locks(struct bnxt *bp)
5415 {
5416         int err;
5417
5418         err = pthread_mutex_init(&bp->flow_lock, NULL);
5419         if (err) {
5420                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5421                 return err;
5422         }
5423
5424         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5425         if (err)
5426                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5427         return err;
5428 }
5429
5430 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5431 {
5432         int rc = 0;
5433
5434         rc = bnxt_init_fw(bp);
5435         if (rc)
5436                 return rc;
5437
5438         if (!reconfig_dev) {
5439                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5440                 if (rc)
5441                         return rc;
5442         } else {
5443                 rc = bnxt_restore_dflt_mac(bp);
5444                 if (rc)
5445                         return rc;
5446         }
5447
5448         bnxt_config_vf_req_fwd(bp);
5449
5450         rc = bnxt_hwrm_func_driver_register(bp);
5451         if (rc) {
5452                 PMD_DRV_LOG(ERR, "Failed to register driver");
5453                 return -EBUSY;
5454         }
5455
5456         if (BNXT_PF(bp)) {
5457                 if (bp->pdev->max_vfs) {
5458                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5459                         if (rc) {
5460                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5461                                 return rc;
5462                         }
5463                 } else {
5464                         rc = bnxt_hwrm_allocate_pf_only(bp);
5465                         if (rc) {
5466                                 PMD_DRV_LOG(ERR,
5467                                             "Failed to allocate PF resources");
5468                                 return rc;
5469                         }
5470                 }
5471         }
5472
5473         rc = bnxt_alloc_mem(bp, reconfig_dev);
5474         if (rc)
5475                 return rc;
5476
5477         rc = bnxt_setup_int(bp);
5478         if (rc)
5479                 return rc;
5480
5481         rc = bnxt_request_int(bp);
5482         if (rc)
5483                 return rc;
5484
5485         rc = bnxt_init_ctx_mem(bp);
5486         if (rc) {
5487                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5488                 return rc;
5489         }
5490
5491         rc = bnxt_init_locks(bp);
5492         if (rc)
5493                 return rc;
5494
5495         return 0;
5496 }
5497
5498 static int
5499 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5500                           const char *value, void *opaque_arg)
5501 {
5502         struct bnxt *bp = opaque_arg;
5503         unsigned long truflow;
5504         char *end = NULL;
5505
5506         if (!value || !opaque_arg) {
5507                 PMD_DRV_LOG(ERR,
5508                             "Invalid parameter passed to truflow devargs.\n");
5509                 return -EINVAL;
5510         }
5511
5512         truflow = strtoul(value, &end, 10);
5513         if (end == NULL || *end != '\0' ||
5514             (truflow == ULONG_MAX && errno == ERANGE)) {
5515                 PMD_DRV_LOG(ERR,
5516                             "Invalid parameter passed to truflow devargs.\n");
5517                 return -EINVAL;
5518         }
5519
5520         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5521                 PMD_DRV_LOG(ERR,
5522                             "Invalid value passed to truflow devargs.\n");
5523                 return -EINVAL;
5524         }
5525
5526         bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5527         if (BNXT_TRUFLOW_EN(bp))
5528                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5529
5530         return 0;
5531 }
5532
5533 static int
5534 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5535                              const char *value, void *opaque_arg)
5536 {
5537         struct bnxt *bp = opaque_arg;
5538         unsigned long flow_xstat;
5539         char *end = NULL;
5540
5541         if (!value || !opaque_arg) {
5542                 PMD_DRV_LOG(ERR,
5543                             "Invalid parameter passed to flow_xstat devarg.\n");
5544                 return -EINVAL;
5545         }
5546
5547         flow_xstat = strtoul(value, &end, 10);
5548         if (end == NULL || *end != '\0' ||
5549             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5550                 PMD_DRV_LOG(ERR,
5551                             "Invalid parameter passed to flow_xstat devarg.\n");
5552                 return -EINVAL;
5553         }
5554
5555         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5556                 PMD_DRV_LOG(ERR,
5557                             "Invalid value passed to flow_xstat devarg.\n");
5558                 return -EINVAL;
5559         }
5560
5561         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5562         if (BNXT_FLOW_XSTATS_EN(bp))
5563                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5564
5565         return 0;
5566 }
5567
5568 static int
5569 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5570                                         const char *value, void *opaque_arg)
5571 {
5572         struct bnxt *bp = opaque_arg;
5573         unsigned long max_num_kflows;
5574         char *end = NULL;
5575
5576         if (!value || !opaque_arg) {
5577                 PMD_DRV_LOG(ERR,
5578                         "Invalid parameter passed to max_num_kflows devarg.\n");
5579                 return -EINVAL;
5580         }
5581
5582         max_num_kflows = strtoul(value, &end, 10);
5583         if (end == NULL || *end != '\0' ||
5584                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5585                 PMD_DRV_LOG(ERR,
5586                         "Invalid parameter passed to max_num_kflows devarg.\n");
5587                 return -EINVAL;
5588         }
5589
5590         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5591                 PMD_DRV_LOG(ERR,
5592                         "Invalid value passed to max_num_kflows devarg.\n");
5593                 return -EINVAL;
5594         }
5595
5596         bp->max_num_kflows = max_num_kflows;
5597         if (bp->max_num_kflows)
5598                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5599                                 max_num_kflows);
5600
5601         return 0;
5602 }
5603
5604 static void
5605 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5606 {
5607         struct rte_kvargs *kvlist;
5608
5609         if (devargs == NULL)
5610                 return;
5611
5612         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5613         if (kvlist == NULL)
5614                 return;
5615
5616         /*
5617          * Handler for "truflow" devarg.
5618          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5619          */
5620         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5621                            bnxt_parse_devarg_truflow, bp);
5622
5623         /*
5624          * Handler for "flow_xstat" devarg.
5625          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5626          */
5627         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5628                            bnxt_parse_devarg_flow_xstat, bp);
5629
5630         /*
5631          * Handler for "max_num_kflows" devarg.
5632          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5633          */
5634         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5635                            bnxt_parse_devarg_max_num_kflows, bp);
5636
5637         rte_kvargs_free(kvlist);
5638 }
5639
5640 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5641 {
5642         int rc = 0;
5643
5644         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5645                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5646                 if (rc)
5647                         PMD_DRV_LOG(ERR,
5648                                     "Failed to alloc switch domain: %d\n", rc);
5649                 else
5650                         PMD_DRV_LOG(INFO,
5651                                     "Switch domain allocated %d\n",
5652                                     bp->switch_domain_id);
5653         }
5654
5655         return rc;
5656 }
5657
5658 static int
5659 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5660 {
5661         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5662         static int version_printed;
5663         struct bnxt *bp;
5664         int rc;
5665
5666         if (version_printed++ == 0)
5667                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5668
5669         eth_dev->dev_ops = &bnxt_dev_ops;
5670         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5671         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5672
5673         /*
5674          * For secondary processes, we don't initialise any further
5675          * as primary has already done this work.
5676          */
5677         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5678                 return 0;
5679
5680         rte_eth_copy_pci_info(eth_dev, pci_dev);
5681
5682         bp = eth_dev->data->dev_private;
5683
5684         /* Parse dev arguments passed on when starting the DPDK application. */
5685         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5686
5687         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5688
5689         if (bnxt_vf_pciid(pci_dev->id.device_id))
5690                 bp->flags |= BNXT_FLAG_VF;
5691
5692         if (bnxt_thor_device(pci_dev->id.device_id))
5693                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5694
5695         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5696             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5697             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5698             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5699                 bp->flags |= BNXT_FLAG_STINGRAY;
5700
5701         rc = bnxt_init_board(eth_dev);
5702         if (rc) {
5703                 PMD_DRV_LOG(ERR,
5704                             "Failed to initialize board rc: %x\n", rc);
5705                 return rc;
5706         }
5707
5708         rc = bnxt_alloc_pf_info(bp);
5709         if (rc)
5710                 goto error_free;
5711
5712         rc = bnxt_alloc_link_info(bp);
5713         if (rc)
5714                 goto error_free;
5715
5716         rc = bnxt_alloc_parent_info(bp);
5717         if (rc)
5718                 goto error_free;
5719
5720         rc = bnxt_alloc_hwrm_resources(bp);
5721         if (rc) {
5722                 PMD_DRV_LOG(ERR,
5723                             "Failed to allocate hwrm resource rc: %x\n", rc);
5724                 goto error_free;
5725         }
5726         rc = bnxt_alloc_leds_info(bp);
5727         if (rc)
5728                 goto error_free;
5729
5730         rc = bnxt_alloc_cos_queues(bp);
5731         if (rc)
5732                 goto error_free;
5733
5734         rc = bnxt_init_resources(bp, false);
5735         if (rc)
5736                 goto error_free;
5737
5738         rc = bnxt_alloc_stats_mem(bp);
5739         if (rc)
5740                 goto error_free;
5741
5742         bnxt_alloc_switch_domain(bp);
5743
5744         /* Pass the information to the rte_eth_dev_close() that it should also
5745          * release the private port resources.
5746          */
5747         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5748
5749         PMD_DRV_LOG(INFO,
5750                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5751                     pci_dev->mem_resource[0].phys_addr,
5752                     pci_dev->mem_resource[0].addr);
5753
5754         return 0;
5755
5756 error_free:
5757         bnxt_dev_uninit(eth_dev);
5758         return rc;
5759 }
5760
5761
5762 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5763 {
5764         if (!ctx)
5765                 return;
5766
5767         if (ctx->va)
5768                 rte_free(ctx->va);
5769
5770         ctx->va = NULL;
5771         ctx->dma = RTE_BAD_IOVA;
5772         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5773 }
5774
5775 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5776 {
5777         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5778                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5779                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5780                                   bp->flow_stat->max_fc,
5781                                   false);
5782
5783         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5784                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5785                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5786                                   bp->flow_stat->max_fc,
5787                                   false);
5788
5789         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5790                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5791         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5792
5793         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5794                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5795         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5796
5797         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5798                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5799         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5800
5801         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5802                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5803         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5804 }
5805
5806 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5807 {
5808         bnxt_unregister_fc_ctx_mem(bp);
5809
5810         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5811         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5812         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5813         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5814 }
5815
5816 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5817 {
5818         if (BNXT_FLOW_XSTATS_EN(bp))
5819                 bnxt_uninit_fc_ctx_mem(bp);
5820 }
5821
5822 static void
5823 bnxt_free_error_recovery_info(struct bnxt *bp)
5824 {
5825         rte_free(bp->recovery_info);
5826         bp->recovery_info = NULL;
5827         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5828 }
5829
5830 static void
5831 bnxt_uninit_locks(struct bnxt *bp)
5832 {
5833         pthread_mutex_destroy(&bp->flow_lock);
5834         pthread_mutex_destroy(&bp->def_cp_lock);
5835         if (bp->rep_info)
5836                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5837 }
5838
5839 static int
5840 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5841 {
5842         int rc;
5843
5844         bnxt_free_int(bp);
5845         bnxt_free_mem(bp, reconfig_dev);
5846         bnxt_hwrm_func_buf_unrgtr(bp);
5847         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5848         bp->flags &= ~BNXT_FLAG_REGISTERED;
5849         bnxt_free_ctx_mem(bp);
5850         if (!reconfig_dev) {
5851                 bnxt_free_hwrm_resources(bp);
5852                 bnxt_free_error_recovery_info(bp);
5853         }
5854
5855         bnxt_uninit_ctx_mem(bp);
5856
5857         bnxt_uninit_locks(bp);
5858         bnxt_free_flow_stats_info(bp);
5859         bnxt_free_rep_info(bp);
5860         rte_free(bp->ptp_cfg);
5861         bp->ptp_cfg = NULL;
5862         return rc;
5863 }
5864
5865 static int
5866 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5867 {
5868         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5869                 return -EPERM;
5870
5871         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5872
5873         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5874                 bnxt_dev_close_op(eth_dev);
5875
5876         return 0;
5877 }
5878
5879 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5880 {
5881         struct bnxt *bp = eth_dev->data->dev_private;
5882         struct rte_eth_dev *vf_rep_eth_dev;
5883         int ret = 0, i;
5884
5885         if (!bp)
5886                 return -EINVAL;
5887
5888         for (i = 0; i < bp->num_reps; i++) {
5889                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5890                 if (!vf_rep_eth_dev)
5891                         continue;
5892                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
5893         }
5894         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5895
5896         return ret;
5897 }
5898
5899 static void bnxt_free_rep_info(struct bnxt *bp)
5900 {
5901         rte_free(bp->rep_info);
5902         bp->rep_info = NULL;
5903         rte_free(bp->cfa_code_map);
5904         bp->cfa_code_map = NULL;
5905 }
5906
5907 static int bnxt_init_rep_info(struct bnxt *bp)
5908 {
5909         int i = 0, rc;
5910
5911         if (bp->rep_info)
5912                 return 0;
5913
5914         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5915                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5916                                    0);
5917         if (!bp->rep_info) {
5918                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5919                 return -ENOMEM;
5920         }
5921         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5922                                        sizeof(*bp->cfa_code_map) *
5923                                        BNXT_MAX_CFA_CODE, 0);
5924         if (!bp->cfa_code_map) {
5925                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5926                 bnxt_free_rep_info(bp);
5927                 return -ENOMEM;
5928         }
5929
5930         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5931                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5932
5933         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5934         if (rc) {
5935                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5936                 bnxt_free_rep_info(bp);
5937                 return rc;
5938         }
5939         return rc;
5940 }
5941
5942 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5943                                struct rte_eth_devargs eth_da,
5944                                struct rte_eth_dev *backing_eth_dev)
5945 {
5946         struct rte_eth_dev *vf_rep_eth_dev;
5947         char name[RTE_ETH_NAME_MAX_LEN];
5948         struct bnxt *backing_bp;
5949         uint16_t num_rep;
5950         int i, ret = 0;
5951
5952         num_rep = eth_da.nb_representor_ports;
5953         if (num_rep > BNXT_MAX_VF_REPS) {
5954                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5955                             num_rep, BNXT_MAX_VF_REPS);
5956                 return -EINVAL;
5957         }
5958
5959         if (num_rep > RTE_MAX_ETHPORTS) {
5960                 PMD_DRV_LOG(ERR,
5961                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5962                             num_rep, RTE_MAX_ETHPORTS);
5963                 return -EINVAL;
5964         }
5965
5966         backing_bp = backing_eth_dev->data->dev_private;
5967
5968         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5969                 PMD_DRV_LOG(ERR,
5970                             "Not a PF or trusted VF. No Representor support\n");
5971                 /* Returning an error is not an option.
5972                  * Applications are not handling this correctly
5973                  */
5974                 return 0;
5975         }
5976
5977         if (bnxt_init_rep_info(backing_bp))
5978                 return 0;
5979
5980         for (i = 0; i < num_rep; i++) {
5981                 struct bnxt_vf_representor representor = {
5982                         .vf_id = eth_da.representor_ports[i],
5983                         .switch_domain_id = backing_bp->switch_domain_id,
5984                         .parent_dev = backing_eth_dev
5985                 };
5986
5987                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5988                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5989                                     representor.vf_id, BNXT_MAX_VF_REPS);
5990                         continue;
5991                 }
5992
5993                 /* representor port net_bdf_port */
5994                 snprintf(name, sizeof(name), "net_%s_representor_%d",
5995                          pci_dev->device.name, eth_da.representor_ports[i]);
5996
5997                 ret = rte_eth_dev_create(&pci_dev->device, name,
5998                                          sizeof(struct bnxt_vf_representor),
5999                                          NULL, NULL,
6000                                          bnxt_vf_representor_init,
6001                                          &representor);
6002
6003                 if (!ret) {
6004                         vf_rep_eth_dev = rte_eth_dev_allocated(name);
6005                         if (!vf_rep_eth_dev) {
6006                                 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6007                                             " for VF-Rep: %s.", name);
6008                                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6009                                 ret = -ENODEV;
6010                                 return ret;
6011                         }
6012                         backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6013                                 vf_rep_eth_dev;
6014                         backing_bp->num_reps++;
6015                 } else {
6016                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6017                                     "representor %s.", name);
6018                         bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6019                 }
6020         }
6021
6022         return ret;
6023 }
6024
6025 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6026                           struct rte_pci_device *pci_dev)
6027 {
6028         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6029         struct rte_eth_dev *backing_eth_dev;
6030         uint16_t num_rep;
6031         int ret = 0;
6032
6033         if (pci_dev->device.devargs) {
6034                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6035                                             &eth_da);
6036                 if (ret)
6037                         return ret;
6038         }
6039
6040         num_rep = eth_da.nb_representor_ports;
6041         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6042                     num_rep);
6043
6044         /* We could come here after first level of probe is already invoked
6045          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6046          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6047          */
6048         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6049         if (backing_eth_dev == NULL) {
6050                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6051                                          sizeof(struct bnxt),
6052                                          eth_dev_pci_specific_init, pci_dev,
6053                                          bnxt_dev_init, NULL);
6054
6055                 if (ret || !num_rep)
6056                         return ret;
6057
6058                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6059         }
6060
6061         /* probe representor ports now */
6062         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
6063
6064         return ret;
6065 }
6066
6067 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6068 {
6069         struct rte_eth_dev *eth_dev;
6070
6071         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6072         if (!eth_dev)
6073                 return 0; /* Invoked typically only by OVS-DPDK, by the
6074                            * time it comes here the eth_dev is already
6075                            * deleted by rte_eth_dev_close(), so returning
6076                            * +ve value will at least help in proper cleanup
6077                            */
6078
6079         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6080                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6081                         return rte_eth_dev_destroy(eth_dev,
6082                                                    bnxt_vf_representor_uninit);
6083                 else
6084                         return rte_eth_dev_destroy(eth_dev,
6085                                                    bnxt_dev_uninit);
6086         } else {
6087                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6088         }
6089 }
6090
6091 static struct rte_pci_driver bnxt_rte_pmd = {
6092         .id_table = bnxt_pci_id_map,
6093         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6094                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6095                                                   * and OVS-DPDK
6096                                                   */
6097         .probe = bnxt_pci_probe,
6098         .remove = bnxt_pci_remove,
6099 };
6100
6101 static bool
6102 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6103 {
6104         if (strcmp(dev->device->driver->name, drv->driver.name))
6105                 return false;
6106
6107         return true;
6108 }
6109
6110 bool is_bnxt_supported(struct rte_eth_dev *dev)
6111 {
6112         return is_device_supported(dev, &bnxt_rte_pmd);
6113 }
6114
6115 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6116 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6117 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6118 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");