drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_ACCUM_STATS "accum-stats"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100 #define BNXT_DEVARG_APP_ID      "app-id"
 101
 102 static const char *const bnxt_dev_args[] = {
 103         BNXT_DEVARG_REPRESENTOR,
 104         BNXT_DEVARG_ACCUM_STATS,
 105         BNXT_DEVARG_FLOW_XSTAT,
 106         BNXT_DEVARG_MAX_NUM_KFLOWS,
 107         BNXT_DEVARG_REP_BASED_PF,
 108         BNXT_DEVARG_REP_IS_PF,
 109         BNXT_DEVARG_REP_Q_R2F,
 110         BNXT_DEVARG_REP_Q_F2R,
 111         BNXT_DEVARG_REP_FC_R2F,
 112         BNXT_DEVARG_REP_FC_F2R,
 113         BNXT_DEVARG_APP_ID,
 114         NULL
 115 };
 116
 117 /*
 118  * accum-stats == false to disable flow counter accumulation
 119  * accum-stats == true to enable flow counter accumulation
 120  */
 121 #define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)    ((accum_stats) > 1)
 122
 123 /*
 124  * app-id = an non-negative 8-bit number
 125  */
 126 #define BNXT_DEVARG_APP_ID_INVALID(val)                 ((val) > 255)
 127
 128 /*
 129  * flow_xstat == false to disable the feature
 130  * flow_xstat == true to enable the feature
 131  */
 132 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 133
 134 /*
 135  * rep_is_pf == false to indicate VF representor
 136  * rep_is_pf == true to indicate PF representor
 137  */
 138 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 139
 140 /*
 141  * rep_based_pf == Physical index of the PF
 142  */
 143 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 144 /*
 145  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 146  */
 147 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 148
 149 /*
 150  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 151  */
 152 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 153
 154 /*
 155  * rep_fc_r2f == Flow control for the representor to endpoint direction
 156  */
 157 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 158
 159 /*
 160  * rep_fc_f2r == Flow control for the endpoint to representor direction
 161  */
 162 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 163
 164 int bnxt_cfa_code_dynfield_offset = -1;
 165
 166 /*
 167  * max_num_kflows must be >= 32
 168  * and must be a power-of-2 supported value
 169  * return: 1 -> invalid
 170  *         0 -> valid
 171  */
 172 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 173 {
 174         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 175                 return 1;
 176         return 0;
 177 }
 178
 179 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 180 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 181 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 182 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 183 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 184 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 185 static void bnxt_dev_recover(void *arg);
 186 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 187 static void bnxt_free_rep_info(struct bnxt *bp);
 188
 189 int is_bnxt_in_error(struct bnxt *bp)
 190 {
 191         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 192                 return -EIO;
 193         if (bp->flags & BNXT_FLAG_FW_RESET)
 194                 return -EBUSY;
 195
 196         return 0;
 197 }
 198
 199 /***********************/
 200
 201 /*
 202  * High level utility functions
 203  */
 204
 205 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 206 {
 207         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 208                                              BNXT_RSS_TBL_SIZE_P5);
 209
 210         if (!BNXT_CHIP_P5(bp))
 211                 return 1;
 212
 213         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 214                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 215                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 216 }
 217
 218 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 219 {
 220         if (!BNXT_CHIP_P5(bp))
 221                 return HW_HASH_INDEX_SIZE;
 222
 223         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 224 }
 225
 226 static void bnxt_free_parent_info(struct bnxt *bp)
 227 {
 228         rte_free(bp->parent);
 229         bp->parent = NULL;
 230 }
 231
 232 static void bnxt_free_pf_info(struct bnxt *bp)
 233 {
 234         rte_free(bp->pf);
 235         bp->pf = NULL;
 236 }
 237
 238 static void bnxt_free_link_info(struct bnxt *bp)
 239 {
 240         rte_free(bp->link_info);
 241         bp->link_info = NULL;
 242 }
 243
 244 static void bnxt_free_leds_info(struct bnxt *bp)
 245 {
 246         if (BNXT_VF(bp))
 247                 return;
 248
 249         rte_free(bp->leds);
 250         bp->leds = NULL;
 251 }
 252
 253 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 254 {
 255         rte_free(bp->flow_stat);
 256         bp->flow_stat = NULL;
 257 }
 258
 259 static void bnxt_free_cos_queues(struct bnxt *bp)
 260 {
 261         rte_free(bp->rx_cos_queue);
 262         bp->rx_cos_queue = NULL;
 263         rte_free(bp->tx_cos_queue);
 264         bp->tx_cos_queue = NULL;
 265 }
 266
 267 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 268 {
 269         bnxt_free_filter_mem(bp);
 270         bnxt_free_vnic_attributes(bp);
 271         bnxt_free_vnic_mem(bp);
 272
 273         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 274          * If the number of rings change across fw update,
 275          * we don't have much choice except to warn the user.
 276          */
 277         if (!reconfig) {
 278                 bnxt_free_stats(bp);
 279                 bnxt_free_tx_rings(bp);
 280                 bnxt_free_rx_rings(bp);
 281         }
 282         bnxt_free_async_cp_ring(bp);
 283         bnxt_free_rxtx_nq_ring(bp);
 284
 285         rte_free(bp->grp_info);
 286         bp->grp_info = NULL;
 287 }
 288
 289 static int bnxt_alloc_parent_info(struct bnxt *bp)
 290 {
 291         bp->parent = rte_zmalloc("bnxt_parent_info",
 292                                  sizeof(struct bnxt_parent_info), 0);
 293         if (bp->parent == NULL)
 294                 return -ENOMEM;
 295
 296         return 0;
 297 }
 298
 299 static int bnxt_alloc_pf_info(struct bnxt *bp)
 300 {
 301         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 302         if (bp->pf == NULL)
 303                 return -ENOMEM;
 304
 305         return 0;
 306 }
 307
 308 static int bnxt_alloc_link_info(struct bnxt *bp)
 309 {
 310         bp->link_info =
 311                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 312         if (bp->link_info == NULL)
 313                 return -ENOMEM;
 314
 315         return 0;
 316 }
 317
 318 static int bnxt_alloc_leds_info(struct bnxt *bp)
 319 {
 320         if (BNXT_VF(bp))
 321                 return 0;
 322
 323         bp->leds = rte_zmalloc("bnxt_leds",
 324                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 325                                0);
 326         if (bp->leds == NULL)
 327                 return -ENOMEM;
 328
 329         return 0;
 330 }
 331
 332 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 333 {
 334         bp->rx_cos_queue =
 335                 rte_zmalloc("bnxt_rx_cosq",
 336                             BNXT_COS_QUEUE_COUNT *
 337                             sizeof(struct bnxt_cos_queue_info),
 338                             0);
 339         if (bp->rx_cos_queue == NULL)
 340                 return -ENOMEM;
 341
 342         bp->tx_cos_queue =
 343                 rte_zmalloc("bnxt_tx_cosq",
 344                             BNXT_COS_QUEUE_COUNT *
 345                             sizeof(struct bnxt_cos_queue_info),
 346                             0);
 347         if (bp->tx_cos_queue == NULL)
 348                 return -ENOMEM;
 349
 350         return 0;
 351 }
 352
 353 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 354 {
 355         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 356                                     sizeof(struct bnxt_flow_stat_info), 0);
 357         if (bp->flow_stat == NULL)
 358                 return -ENOMEM;
 359
 360         return 0;
 361 }
 362
 363 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 364 {
 365         int rc;
 366
 367         rc = bnxt_alloc_ring_grps(bp);
 368         if (rc)
 369                 goto alloc_mem_err;
 370
 371         rc = bnxt_alloc_async_ring_struct(bp);
 372         if (rc)
 373                 goto alloc_mem_err;
 374
 375         rc = bnxt_alloc_vnic_mem(bp);
 376         if (rc)
 377                 goto alloc_mem_err;
 378
 379         rc = bnxt_alloc_vnic_attributes(bp);
 380         if (rc)
 381                 goto alloc_mem_err;
 382
 383         rc = bnxt_alloc_filter_mem(bp);
 384         if (rc)
 385                 goto alloc_mem_err;
 386
 387         rc = bnxt_alloc_async_cp_ring(bp);
 388         if (rc)
 389                 goto alloc_mem_err;
 390
 391         rc = bnxt_alloc_rxtx_nq_ring(bp);
 392         if (rc)
 393                 goto alloc_mem_err;
 394
 395         if (BNXT_FLOW_XSTATS_EN(bp)) {
 396                 rc = bnxt_alloc_flow_stats_info(bp);
 397                 if (rc)
 398                         goto alloc_mem_err;
 399         }
 400
 401         return 0;
 402
 403 alloc_mem_err:
 404         bnxt_free_mem(bp, reconfig);
 405         return rc;
 406 }
 407
 408 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 409 {
 410         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 411         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 412         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 413         struct bnxt_rx_queue *rxq;
 414         unsigned int j;
 415         int rc;
 416
 417         rc = bnxt_vnic_grp_alloc(bp, vnic);
 418         if (rc)
 419                 goto err_out;
 420
 421         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 422                     vnic_id, vnic, vnic->fw_grp_ids);
 423
 424         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 425         if (rc)
 426                 goto err_out;
 427
 428         /* Alloc RSS context only if RSS mode is enabled */
 429         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 430                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 431
 432                 /* RSS table size in Thor is 512.
 433                  * Cap max Rx rings to same value
 434                  */
 435                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 436                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 437                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 438                         goto err_out;
 439                 }
 440
 441                 rc = 0;
 442                 for (j = 0; j < nr_ctxs; j++) {
 443                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 444                         if (rc)
 445                                 break;
 446                 }
 447                 if (rc) {
 448                         PMD_DRV_LOG(ERR,
 449                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 450                                     vnic_id, j, rc);
 451                         goto err_out;
 452                 }
 453                 vnic->num_lb_ctxts = nr_ctxs;
 454         }
 455
 456         /*
 457          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 458          * setting is not available at this time, it will not be
 459          * configured correctly in the CFA.
 460          */
 461         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 462                 vnic->vlan_strip = true;
 463         else
 464                 vnic->vlan_strip = false;
 465
 466         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 467         if (rc)
 468                 goto err_out;
 469
 470         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 471         if (rc)
 472                 goto err_out;
 473
 474         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 475                 rxq = bp->eth_dev->data->rx_queues[j];
 476
 477                 PMD_DRV_LOG(DEBUG,
 478                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 479                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 480
 481                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 482                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 483                 else
 484                         vnic->rx_queue_cnt++;
 485
 486                 if (!rxq->rx_deferred_start) {
 487                         bp->eth_dev->data->rx_queue_state[j] =
 488                                 RTE_ETH_QUEUE_STATE_STARTED;
 489                         rxq->rx_started = true;
 490                 }
 491         }
 492
 493         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 494
 495         rc = bnxt_vnic_rss_configure(bp, vnic);
 496         if (rc)
 497                 goto err_out;
 498
 499         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 500
 501         rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
 502                                     (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ?
 503                                     true : false);
 504         if (rc)
 505                 goto err_out;
 506
 507         return 0;
 508 err_out:
 509         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 510                     vnic_id, rc);
 511         return rc;
 512 }
 513
 514 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 515 {
 516         int rc = 0;
 517
 518         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 519                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 520         if (rc)
 521                 return rc;
 522
 523         PMD_DRV_LOG(DEBUG,
 524                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 525                     " rx_fc_in_tbl.ctx_id = %d\n",
 526                     bp->flow_stat->rx_fc_in_tbl.va,
 527                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 528                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 529
 530         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 531                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 532         if (rc)
 533                 return rc;
 534
 535         PMD_DRV_LOG(DEBUG,
 536                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 537                     " rx_fc_out_tbl.ctx_id = %d\n",
 538                     bp->flow_stat->rx_fc_out_tbl.va,
 539                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 540                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 541
 542         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 543                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 544         if (rc)
 545                 return rc;
 546
 547         PMD_DRV_LOG(DEBUG,
 548                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 549                     " tx_fc_in_tbl.ctx_id = %d\n",
 550                     bp->flow_stat->tx_fc_in_tbl.va,
 551                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 552                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 553
 554         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 555                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 556         if (rc)
 557                 return rc;
 558
 559         PMD_DRV_LOG(DEBUG,
 560                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 561                     " tx_fc_out_tbl.ctx_id = %d\n",
 562                     bp->flow_stat->tx_fc_out_tbl.va,
 563                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 564                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 565
 566         memset(bp->flow_stat->rx_fc_out_tbl.va,
 567                0,
 568                bp->flow_stat->rx_fc_out_tbl.size);
 569         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 570                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 571                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 572                                        bp->flow_stat->max_fc,
 573                                        true);
 574         if (rc)
 575                 return rc;
 576
 577         memset(bp->flow_stat->tx_fc_out_tbl.va,
 578                0,
 579                bp->flow_stat->tx_fc_out_tbl.size);
 580         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 581                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 582                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 583                                        bp->flow_stat->max_fc,
 584                                        true);
 585
 586         return rc;
 587 }
 588
 589 static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size,
 590                                   struct bnxt_ctx_mem_buf_info *ctx)
 591 {
 592         if (!ctx)
 593                 return -EINVAL;
 594
 595         ctx->va = rte_zmalloc_socket(type, size, 0,
 596                                      bp->eth_dev->device->numa_node);
 597         if (ctx->va == NULL)
 598                 return -ENOMEM;
 599         rte_mem_lock_page(ctx->va);
 600         ctx->size = size;
 601         ctx->dma = rte_mem_virt2iova(ctx->va);
 602         if (ctx->dma == RTE_BAD_IOVA)
 603                 return -ENOMEM;
 604
 605         return 0;
 606 }
 607
 608 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 609 {
 610         struct rte_pci_device *pdev = bp->pdev;
 611         char type[RTE_MEMZONE_NAMESIZE];
 612         uint16_t max_fc;
 613         int rc = 0;
 614
 615         max_fc = bp->flow_stat->max_fc;
 616
 617         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 618                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 619         /* 4 bytes for each counter-id */
 620         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 621                                     max_fc * 4,
 622                                     &bp->flow_stat->rx_fc_in_tbl);
 623         if (rc)
 624                 return rc;
 625
 626         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 627                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 628         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 629         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 630                                     max_fc * 16,
 631                                     &bp->flow_stat->rx_fc_out_tbl);
 632         if (rc)
 633                 return rc;
 634
 635         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 636                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 637         /* 4 bytes for each counter-id */
 638         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 639                                     max_fc * 4,
 640                                     &bp->flow_stat->tx_fc_in_tbl);
 641         if (rc)
 642                 return rc;
 643
 644         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 645                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 646         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 647         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 648                                     max_fc * 16,
 649                                     &bp->flow_stat->tx_fc_out_tbl);
 650         if (rc)
 651                 return rc;
 652
 653         rc = bnxt_register_fc_ctx_mem(bp);
 654
 655         return rc;
 656 }
 657
 658 static int bnxt_init_ctx_mem(struct bnxt *bp)
 659 {
 660         int rc = 0;
 661
 662         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 663             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 664             !BNXT_FLOW_XSTATS_EN(bp))
 665                 return 0;
 666
 667         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 668         if (rc)
 669                 return rc;
 670
 671         rc = bnxt_init_fc_ctx_mem(bp);
 672
 673         return rc;
 674 }
 675
 676 static int bnxt_update_phy_setting(struct bnxt *bp)
 677 {
 678         struct rte_eth_link new;
 679         int rc;
 680
 681         rc = bnxt_get_hwrm_link_config(bp, &new);
 682         if (rc) {
 683                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 684                 return rc;
 685         }
 686
 687         /*
 688          * On BCM957508-N2100 adapters, FW will not allow any user other
 689          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 690          * always returns link up. Force phy update always in that case.
 691          */
 692         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 693                 rc = bnxt_set_hwrm_link_config(bp, true);
 694                 if (rc) {
 695                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 696                         return rc;
 697                 }
 698         }
 699
 700         return rc;
 701 }
 702
 703 static void bnxt_free_prev_ring_stats(struct bnxt *bp)
 704 {
 705         rte_free(bp->prev_rx_ring_stats);
 706         rte_free(bp->prev_tx_ring_stats);
 707
 708         bp->prev_rx_ring_stats = NULL;
 709         bp->prev_tx_ring_stats = NULL;
 710 }
 711
 712 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
 713 {
 714         bp->prev_rx_ring_stats =  rte_zmalloc("bnxt_prev_rx_ring_stats",
 715                                               sizeof(struct bnxt_ring_stats) *
 716                                               bp->rx_cp_nr_rings,
 717                                               0);
 718         if (bp->prev_rx_ring_stats == NULL)
 719                 return -ENOMEM;
 720
 721         bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
 722                                              sizeof(struct bnxt_ring_stats) *
 723                                              bp->tx_cp_nr_rings,
 724                                              0);
 725         if (bp->prev_tx_ring_stats == NULL)
 726                 goto error;
 727
 728         return 0;
 729
 730 error:
 731         bnxt_free_prev_ring_stats(bp);
 732         return -ENOMEM;
 733 }
 734
 735 static int bnxt_start_nic(struct bnxt *bp)
 736 {
 737         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 738         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 739         uint32_t intr_vector = 0;
 740         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 741         uint32_t vec = BNXT_MISC_VEC_ID;
 742         unsigned int i, j;
 743         int rc;
 744
 745         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 746                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 747                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 748                 bp->flags |= BNXT_FLAG_JUMBO;
 749         } else {
 750                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 751                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 752                 bp->flags &= ~BNXT_FLAG_JUMBO;
 753         }
 754
 755         /* THOR does not support ring groups.
 756          * But we will use the array to save RSS context IDs.
 757          */
 758         if (BNXT_CHIP_P5(bp))
 759                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 760
 761         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 762         if (rc) {
 763                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 764                 goto err_out;
 765         }
 766
 767         rc = bnxt_alloc_hwrm_rings(bp);
 768         if (rc) {
 769                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 770                 goto err_out;
 771         }
 772
 773         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 774         if (rc) {
 775                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 776                 goto err_out;
 777         }
 778
 779         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 780                 goto skip_cosq_cfg;
 781
 782         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 783                 if (bp->rx_cos_queue[i].id != 0xff) {
 784                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 785
 786                         if (!vnic) {
 787                                 PMD_DRV_LOG(ERR,
 788                                             "Num pools more than FW profile\n");
 789                                 rc = -EINVAL;
 790                                 goto err_out;
 791                         }
 792                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 793                         bp->rx_cosq_cnt++;
 794                 }
 795         }
 796
 797 skip_cosq_cfg:
 798         rc = bnxt_mq_rx_configure(bp);
 799         if (rc) {
 800                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 801                 goto err_out;
 802         }
 803
 804         /* default vnic 0 */
 805         rc = bnxt_setup_one_vnic(bp, 0);
 806         if (rc)
 807                 goto err_out;
 808         /* VNIC configuration */
 809         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 810                 for (i = 1; i < bp->nr_vnics; i++) {
 811                         rc = bnxt_setup_one_vnic(bp, i);
 812                         if (rc)
 813                                 goto err_out;
 814                 }
 815         }
 816
 817         for (j = 0; j < bp->tx_nr_rings; j++) {
 818                 struct bnxt_tx_queue *txq = bp->tx_queues[j];
 819
 820                 if (!txq->tx_deferred_start) {
 821                         bp->eth_dev->data->tx_queue_state[j] =
 822                                 RTE_ETH_QUEUE_STATE_STARTED;
 823                         txq->tx_started = true;
 824                 }
 825         }
 826
 827         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 828         if (rc) {
 829                 PMD_DRV_LOG(ERR,
 830                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 831                 goto err_out;
 832         }
 833
 834         /* check and configure queue intr-vector mapping */
 835         if ((rte_intr_cap_multiple(intr_handle) ||
 836              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 837             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 838                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 839                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 840                 if (intr_vector > bp->rx_cp_nr_rings) {
 841                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 842                                         bp->rx_cp_nr_rings);
 843                         return -ENOTSUP;
 844                 }
 845                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 846                 if (rc)
 847                         return rc;
 848         }
 849
 850         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 851                 intr_handle->intr_vec =
 852                         rte_zmalloc("intr_vec",
 853                                     bp->eth_dev->data->nb_rx_queues *
 854                                     sizeof(int), 0);
 855                 if (intr_handle->intr_vec == NULL) {
 856                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 857                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 858                         rc = -ENOMEM;
 859                         goto err_out;
 860                 }
 861                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 862                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 863                          intr_handle->intr_vec, intr_handle->nb_efd,
 864                         intr_handle->max_intr);
 865                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 866                      queue_id++) {
 867                         intr_handle->intr_vec[queue_id] =
 868                                                         vec + BNXT_RX_VEC_START;
 869                         if (vec < base + intr_handle->nb_efd - 1)
 870                                 vec++;
 871                 }
 872         }
 873
 874         /* enable uio/vfio intr/eventfd mapping */
 875         rc = rte_intr_enable(intr_handle);
 876 #ifndef RTE_EXEC_ENV_FREEBSD
 877         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 878         if (rc)
 879                 goto err_out;
 880 #endif
 881
 882         rc = bnxt_update_phy_setting(bp);
 883         if (rc)
 884                 goto err_out;
 885
 886         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 887         if (!bp->mark_table)
 888                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 889
 890         return 0;
 891
 892 err_out:
 893         /* Some of the error status returned by FW may not be from errno.h */
 894         if (rc > 0)
 895                 rc = -EIO;
 896
 897         return rc;
 898 }
 899
 900 static int bnxt_shutdown_nic(struct bnxt *bp)
 901 {
 902         bnxt_free_all_hwrm_resources(bp);
 903         bnxt_free_all_filters(bp);
 904         bnxt_free_all_vnics(bp);
 905         return 0;
 906 }
 907
 908 /*
 909  * Device configuration and status function
 910  */
 911
 912 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 913 {
 914         uint32_t link_speed = 0;
 915         uint32_t speed_capa = 0;
 916
 917         if (bp->link_info == NULL)
 918                 return 0;
 919
 920         link_speed = bp->link_info->support_speeds;
 921
 922         /* If PAM4 is configured, use PAM4 supported speed */
 923         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 924                 link_speed = bp->link_info->support_pam4_speeds;
 925
 926         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 927                 speed_capa |= ETH_LINK_SPEED_100M;
 928         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 929                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 930         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 931                 speed_capa |= ETH_LINK_SPEED_1G;
 932         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 933                 speed_capa |= ETH_LINK_SPEED_2_5G;
 934         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 935                 speed_capa |= ETH_LINK_SPEED_10G;
 936         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 937                 speed_capa |= ETH_LINK_SPEED_20G;
 938         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 939                 speed_capa |= ETH_LINK_SPEED_25G;
 940         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 941                 speed_capa |= ETH_LINK_SPEED_40G;
 942         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 943                 speed_capa |= ETH_LINK_SPEED_50G;
 944         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 945                 speed_capa |= ETH_LINK_SPEED_100G;
 946         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 947                 speed_capa |= ETH_LINK_SPEED_50G;
 948         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 949                 speed_capa |= ETH_LINK_SPEED_100G;
 950         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 951                 speed_capa |= ETH_LINK_SPEED_200G;
 952
 953         if (bp->link_info->auto_mode ==
 954             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 955                 speed_capa |= ETH_LINK_SPEED_FIXED;
 956
 957         return speed_capa;
 958 }
 959
 960 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 961                                 struct rte_eth_dev_info *dev_info)
 962 {
 963         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 964         struct bnxt *bp = eth_dev->data->dev_private;
 965         uint16_t max_vnics, i, j, vpool, vrxq;
 966         unsigned int max_rx_rings;
 967         int rc;
 968
 969         rc = is_bnxt_in_error(bp);
 970         if (rc)
 971                 return rc;
 972
 973         /* MAC Specifics */
 974         dev_info->max_mac_addrs = bp->max_l2_ctx;
 975         dev_info->max_hash_mac_addrs = 0;
 976
 977         /* PF/VF specifics */
 978         if (BNXT_PF(bp))
 979                 dev_info->max_vfs = pdev->max_vfs;
 980
 981         max_rx_rings = bnxt_max_rings(bp);
 982         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 983         dev_info->max_rx_queues = max_rx_rings;
 984         dev_info->max_tx_queues = max_rx_rings;
 985         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 986         dev_info->hash_key_size = HW_HASH_KEY_SIZE;
 987         max_vnics = bp->max_vnics;
 988
 989         /* MTU specifics */
 990         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 991         dev_info->max_mtu = BNXT_MAX_MTU;
 992
 993         /* Fast path specifics */
 994         dev_info->min_rx_bufsize = 1;
 995         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 996
 997         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 998         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 999                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
1000         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP)
1001                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_VLAN_STRIP;
1002         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
1003         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
1004                                     dev_info->tx_queue_offload_capa;
1005         if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
1006                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_VLAN_INSERT;
1007         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
1008
1009         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
1010         dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
1011                              RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
1012
1013         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1014                 .rx_thresh = {
1015                         .pthresh = 8,
1016                         .hthresh = 8,
1017                         .wthresh = 0,
1018                 },
1019                 .rx_free_thresh = 32,
1020                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
1021         };
1022
1023         dev_info->default_txconf = (struct rte_eth_txconf) {
1024                 .tx_thresh = {
1025                         .pthresh = 32,
1026                         .hthresh = 0,
1027                         .wthresh = 0,
1028                 },
1029                 .tx_free_thresh = 32,
1030                 .tx_rs_thresh = 32,
1031         };
1032         eth_dev->data->dev_conf.intr_conf.lsc = 1;
1033
1034         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1035         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
1036         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1037         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
1038
1039         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
1040                 dev_info->switch_info.name = eth_dev->device->name;
1041                 dev_info->switch_info.domain_id = bp->switch_domain_id;
1042                 dev_info->switch_info.port_id =
1043                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
1044                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
1045         }
1046
1047         /*
1048          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
1049          *       need further investigation.
1050          */
1051
1052         /* VMDq resources */
1053         vpool = 64; /* ETH_64_POOLS */
1054         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
1055         for (i = 0; i < 4; vpool >>= 1, i++) {
1056                 if (max_vnics > vpool) {
1057                         for (j = 0; j < 5; vrxq >>= 1, j++) {
1058                                 if (dev_info->max_rx_queues > vrxq) {
1059                                         if (vpool > vrxq)
1060                                                 vpool = vrxq;
1061                                         goto found;
1062                                 }
1063                         }
1064                         /* Not enough resources to support VMDq */
1065                         break;
1066                 }
1067         }
1068         /* Not enough resources to support VMDq */
1069         vpool = 0;
1070         vrxq = 0;
1071 found:
1072         dev_info->max_vmdq_pools = vpool;
1073         dev_info->vmdq_queue_num = vrxq;
1074
1075         dev_info->vmdq_pool_base = 0;
1076         dev_info->vmdq_queue_base = 0;
1077
1078         return 0;
1079 }
1080
1081 /* Configure the device based on the configuration provided */
1082 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1083 {
1084         struct bnxt *bp = eth_dev->data->dev_private;
1085         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1086         int rc;
1087
1088         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1089         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1090         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1091         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1092
1093         rc = is_bnxt_in_error(bp);
1094         if (rc)
1095                 return rc;
1096
1097         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1098                 rc = bnxt_hwrm_check_vf_rings(bp);
1099                 if (rc) {
1100                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1101                         return -ENOSPC;
1102                 }
1103
1104                 /* If a resource has already been allocated - in this case
1105                  * it is the async completion ring, free it. Reallocate it after
1106                  * resource reservation. This will ensure the resource counts
1107                  * are calculated correctly.
1108                  */
1109
1110                 pthread_mutex_lock(&bp->def_cp_lock);
1111
1112                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1113                         bnxt_disable_int(bp);
1114                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1115                 }
1116
1117                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1118                 if (rc) {
1119                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1120                         pthread_mutex_unlock(&bp->def_cp_lock);
1121                         return -ENOSPC;
1122                 }
1123
1124                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1125                         rc = bnxt_alloc_async_cp_ring(bp);
1126                         if (rc) {
1127                                 pthread_mutex_unlock(&bp->def_cp_lock);
1128                                 return rc;
1129                         }
1130                         bnxt_enable_int(bp);
1131                 }
1132
1133                 pthread_mutex_unlock(&bp->def_cp_lock);
1134         }
1135
1136         /* Inherit new configurations */
1137         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1138             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1139             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1140                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1141             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1142             bp->max_stat_ctx)
1143                 goto resource_error;
1144
1145         if (BNXT_HAS_RING_GRPS(bp) &&
1146             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1147                 goto resource_error;
1148
1149         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1150             bp->max_vnics < eth_dev->data->nb_rx_queues)
1151                 goto resource_error;
1152
1153         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1154         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1155
1156         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1157                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1158         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1159
1160         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1161                 eth_dev->data->mtu =
1162                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1163                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1164                         BNXT_NUM_VLANS;
1165                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1166         }
1167         return 0;
1168
1169 resource_error:
1170         PMD_DRV_LOG(ERR,
1171                     "Insufficient resources to support requested config\n");
1172         PMD_DRV_LOG(ERR,
1173                     "Num Queues Requested: Tx %d, Rx %d\n",
1174                     eth_dev->data->nb_tx_queues,
1175                     eth_dev->data->nb_rx_queues);
1176         PMD_DRV_LOG(ERR,
1177                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1178                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1179                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1180         return -ENOSPC;
1181 }
1182
1183 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1184 {
1185         struct rte_eth_link *link = &eth_dev->data->dev_link;
1186
1187         if (link->link_status)
1188                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1189                         eth_dev->data->port_id,
1190                         (uint32_t)link->link_speed,
1191                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1192                         ("full-duplex") : ("half-duplex\n"));
1193         else
1194                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1195                         eth_dev->data->port_id);
1196 }
1197
1198 /*
1199  * Determine whether the current configuration requires support for scattered
1200  * receive; return 1 if scattered receive is required and 0 if not.
1201  */
1202 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1203 {
1204         uint16_t buf_size;
1205         int i;
1206
1207         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1208                 return 1;
1209
1210         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1211                 return 1;
1212
1213         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1214                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1215
1216                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1217                                       RTE_PKTMBUF_HEADROOM);
1218                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1219                         return 1;
1220         }
1221         return 0;
1222 }
1223
1224 static eth_rx_burst_t
1225 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1226 {
1227         struct bnxt *bp = eth_dev->data->dev_private;
1228
1229         /* Disable vector mode RX for Stingray2 for now */
1230         if (BNXT_CHIP_SR2(bp)) {
1231                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1232                 return bnxt_recv_pkts;
1233         }
1234
1235 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1236         !defined(RTE_LIBRTE_IEEE1588)
1237
1238         /* Vector mode receive cannot be enabled if scattered rx is in use. */
1239         if (eth_dev->data->scattered_rx)
1240                 goto use_scalar_rx;
1241
1242         /*
1243          * Vector mode receive cannot be enabled if Truflow is enabled or if
1244          * asynchronous completions and receive completions can be placed in
1245          * the same completion ring.
1246          */
1247         if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1248                 goto use_scalar_rx;
1249
1250         /*
1251          * Vector mode receive cannot be enabled if any receive offloads outside
1252          * a limited subset have been enabled.
1253          */
1254         if (eth_dev->data->dev_conf.rxmode.offloads &
1255                 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1256                   DEV_RX_OFFLOAD_KEEP_CRC |
1257                   DEV_RX_OFFLOAD_JUMBO_FRAME |
1258                   DEV_RX_OFFLOAD_IPV4_CKSUM |
1259                   DEV_RX_OFFLOAD_UDP_CKSUM |
1260                   DEV_RX_OFFLOAD_TCP_CKSUM |
1261                   DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1262                   DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1263                   DEV_RX_OFFLOAD_RSS_HASH |
1264                   DEV_RX_OFFLOAD_VLAN_FILTER))
1265                 goto use_scalar_rx;
1266
1267 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1268         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1269             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1270                 PMD_DRV_LOG(INFO,
1271                             "Using AVX2 vector mode receive for port %d\n",
1272                             eth_dev->data->port_id);
1273                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1274                 return bnxt_recv_pkts_vec_avx2;
1275         }
1276  #endif
1277         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1278                 PMD_DRV_LOG(INFO,
1279                             "Using SSE vector mode receive for port %d\n",
1280                             eth_dev->data->port_id);
1281                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1282                 return bnxt_recv_pkts_vec;
1283         }
1284
1285 use_scalar_rx:
1286         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1287                     eth_dev->data->port_id);
1288         PMD_DRV_LOG(INFO,
1289                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1290                     eth_dev->data->port_id,
1291                     eth_dev->data->scattered_rx,
1292                     eth_dev->data->dev_conf.rxmode.offloads);
1293 #endif
1294         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1295         return bnxt_recv_pkts;
1296 }
1297
1298 static eth_tx_burst_t
1299 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1300 {
1301         struct bnxt *bp = eth_dev->data->dev_private;
1302
1303         /* Disable vector mode TX for Stingray2 for now */
1304         if (BNXT_CHIP_SR2(bp))
1305                 return bnxt_xmit_pkts;
1306
1307 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1308         !defined(RTE_LIBRTE_IEEE1588)
1309         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1310
1311         /*
1312          * Vector mode transmit can be enabled only if not using scatter rx
1313          * or tx offloads.
1314          */
1315         if (eth_dev->data->scattered_rx ||
1316             (offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) ||
1317             BNXT_TRUFLOW_EN(bp))
1318                 goto use_scalar_tx;
1319
1320 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1321         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1322             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1323                 PMD_DRV_LOG(INFO,
1324                             "Using AVX2 vector mode transmit for port %d\n",
1325                             eth_dev->data->port_id);
1326                 return bnxt_xmit_pkts_vec_avx2;
1327         }
1328 #endif
1329         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1330                 PMD_DRV_LOG(INFO,
1331                             "Using SSE vector mode transmit for port %d\n",
1332                             eth_dev->data->port_id);
1333                 return bnxt_xmit_pkts_vec;
1334         }
1335
1336 use_scalar_tx:
1337         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1338                     eth_dev->data->port_id);
1339         PMD_DRV_LOG(INFO,
1340                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1341                     eth_dev->data->port_id,
1342                     eth_dev->data->scattered_rx,
1343                     offloads);
1344 #endif
1345         return bnxt_xmit_pkts;
1346 }
1347
1348 static int bnxt_handle_if_change_status(struct bnxt *bp)
1349 {
1350         int rc;
1351
1352         /* Since fw has undergone a reset and lost all contexts,
1353          * set fatal flag to not issue hwrm during cleanup
1354          */
1355         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1356         bnxt_uninit_resources(bp, true);
1357
1358         /* clear fatal flag so that re-init happens */
1359         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1360         rc = bnxt_init_resources(bp, true);
1361
1362         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1363
1364         return rc;
1365 }
1366
1367 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1368 {
1369         struct bnxt *bp = eth_dev->data->dev_private;
1370         int rc = 0;
1371
1372         if (!BNXT_SINGLE_PF(bp))
1373                 return -ENOTSUP;
1374
1375         if (!bp->link_info->link_up)
1376                 rc = bnxt_set_hwrm_link_config(bp, true);
1377         if (!rc)
1378                 eth_dev->data->dev_link.link_status = 1;
1379
1380         bnxt_print_link_info(eth_dev);
1381         return rc;
1382 }
1383
1384 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1385 {
1386         struct bnxt *bp = eth_dev->data->dev_private;
1387
1388         if (!BNXT_SINGLE_PF(bp))
1389                 return -ENOTSUP;
1390
1391         eth_dev->data->dev_link.link_status = 0;
1392         bnxt_set_hwrm_link_config(bp, false);
1393         bp->link_info->link_up = 0;
1394
1395         return 0;
1396 }
1397
1398 static void bnxt_free_switch_domain(struct bnxt *bp)
1399 {
1400         int rc = 0;
1401
1402         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1403                 return;
1404
1405         rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1406         if (rc)
1407                 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1408                             bp->switch_domain_id, rc);
1409 }
1410
1411 static void bnxt_ptp_get_current_time(void *arg)
1412 {
1413         struct bnxt *bp = arg;
1414         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1415         int rc;
1416
1417         rc = is_bnxt_in_error(bp);
1418         if (rc)
1419                 return;
1420
1421         if (!ptp)
1422                 return;
1423
1424         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1425                                 &ptp->current_time);
1426
1427         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1428         if (rc != 0) {
1429                 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1430                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1431         }
1432 }
1433
1434 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1435 {
1436         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1437         int rc;
1438
1439         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1440                 return 0;
1441
1442         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1443                                 &ptp->current_time);
1444
1445         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1446         return rc;
1447 }
1448
1449 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1450 {
1451         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1452                 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1453                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1454         }
1455 }
1456
1457 static void bnxt_ptp_stop(struct bnxt *bp)
1458 {
1459         bnxt_cancel_ptp_alarm(bp);
1460         bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1461 }
1462
1463 static int bnxt_ptp_start(struct bnxt *bp)
1464 {
1465         int rc;
1466
1467         rc = bnxt_schedule_ptp_alarm(bp);
1468         if (rc != 0) {
1469                 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1470         } else {
1471                 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1472                 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1473         }
1474
1475         return rc;
1476 }
1477
1478 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1479 {
1480         struct bnxt *bp = eth_dev->data->dev_private;
1481         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1482         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1483         struct rte_eth_link link;
1484         int ret;
1485
1486         eth_dev->data->dev_started = 0;
1487         eth_dev->data->scattered_rx = 0;
1488
1489         /* Prevent crashes when queues are still in use */
1490         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1491         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1492
1493         bnxt_disable_int(bp);
1494
1495         /* disable uio/vfio intr/eventfd mapping */
1496         rte_intr_disable(intr_handle);
1497
1498         /* Stop the child representors for this device */
1499         ret = bnxt_rep_stop_all(bp);
1500         if (ret != 0)
1501                 return ret;
1502
1503         /* delete the bnxt ULP port details */
1504         bnxt_ulp_port_deinit(bp);
1505
1506         bnxt_cancel_fw_health_check(bp);
1507
1508         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1509                 bnxt_cancel_ptp_alarm(bp);
1510
1511         /* Do not bring link down during reset recovery */
1512         if (!is_bnxt_in_error(bp)) {
1513                 bnxt_dev_set_link_down_op(eth_dev);
1514                 /* Wait for link to be reset */
1515                 if (BNXT_SINGLE_PF(bp))
1516                         rte_delay_ms(500);
1517                 /* clear the recorded link status */
1518                 memset(&link, 0, sizeof(link));
1519                 rte_eth_linkstatus_set(eth_dev, &link);
1520         }
1521
1522         /* Clean queue intr-vector mapping */
1523         rte_intr_efd_disable(intr_handle);
1524         if (intr_handle->intr_vec != NULL) {
1525                 rte_free(intr_handle->intr_vec);
1526                 intr_handle->intr_vec = NULL;
1527         }
1528
1529         bnxt_hwrm_port_clr_stats(bp);
1530         bnxt_free_tx_mbufs(bp);
1531         bnxt_free_rx_mbufs(bp);
1532         /* Process any remaining notifications in default completion queue */
1533         bnxt_int_handler(eth_dev);
1534         bnxt_shutdown_nic(bp);
1535         bnxt_hwrm_if_change(bp, false);
1536
1537         bnxt_free_prev_ring_stats(bp);
1538         rte_free(bp->mark_table);
1539         bp->mark_table = NULL;
1540
1541         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1542         bp->rx_cosq_cnt = 0;
1543         /* All filters are deleted on a port stop. */
1544         if (BNXT_FLOW_XSTATS_EN(bp))
1545                 bp->flow_stat->flow_count = 0;
1546
1547         return 0;
1548 }
1549
1550 /* Unload the driver, release resources */
1551 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1552 {
1553         struct bnxt *bp = eth_dev->data->dev_private;
1554
1555         pthread_mutex_lock(&bp->err_recovery_lock);
1556         if (bp->flags & BNXT_FLAG_FW_RESET) {
1557                 PMD_DRV_LOG(ERR,
1558                             "Adapter recovering from error..Please retry\n");
1559                 pthread_mutex_unlock(&bp->err_recovery_lock);
1560                 return -EAGAIN;
1561         }
1562         pthread_mutex_unlock(&bp->err_recovery_lock);
1563
1564         return bnxt_dev_stop(eth_dev);
1565 }
1566
1567 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1568 {
1569         struct bnxt *bp = eth_dev->data->dev_private;
1570         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1571         int vlan_mask = 0;
1572         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1573
1574         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1575                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1576                 return -EINVAL;
1577         }
1578
1579         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1580                 PMD_DRV_LOG(ERR,
1581                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1582                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1583
1584         do {
1585                 rc = bnxt_hwrm_if_change(bp, true);
1586                 if (rc == 0 || rc != -EAGAIN)
1587                         break;
1588
1589                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1590         } while (retry_cnt--);
1591
1592         if (rc)
1593                 return rc;
1594
1595         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1596                 rc = bnxt_handle_if_change_status(bp);
1597                 if (rc)
1598                         return rc;
1599         }
1600
1601         bnxt_enable_int(bp);
1602
1603         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1604
1605         rc = bnxt_start_nic(bp);
1606         if (rc)
1607                 goto error;
1608
1609         rc = bnxt_alloc_prev_ring_stats(bp);
1610         if (rc)
1611                 goto error;
1612
1613         eth_dev->data->dev_started = 1;
1614
1615         bnxt_link_update_op(eth_dev, 1);
1616
1617         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1618                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1619         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1620                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1621         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1622         if (rc)
1623                 goto error;
1624
1625         /* Initialize bnxt ULP port details */
1626         rc = bnxt_ulp_port_init(bp);
1627         if (rc)
1628                 goto error;
1629
1630         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1631         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1632
1633         bnxt_schedule_fw_health_check(bp);
1634
1635         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1636                 bnxt_schedule_ptp_alarm(bp);
1637
1638         return 0;
1639
1640 error:
1641         bnxt_dev_stop(eth_dev);
1642         return rc;
1643 }
1644
1645 static void
1646 bnxt_uninit_locks(struct bnxt *bp)
1647 {
1648         pthread_mutex_destroy(&bp->flow_lock);
1649         pthread_mutex_destroy(&bp->def_cp_lock);
1650         pthread_mutex_destroy(&bp->health_check_lock);
1651         pthread_mutex_destroy(&bp->err_recovery_lock);
1652         if (bp->rep_info) {
1653                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1654                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1655         }
1656 }
1657
1658 static void bnxt_drv_uninit(struct bnxt *bp)
1659 {
1660         bnxt_free_leds_info(bp);
1661         bnxt_free_cos_queues(bp);
1662         bnxt_free_link_info(bp);
1663         bnxt_free_parent_info(bp);
1664         bnxt_uninit_locks(bp);
1665
1666         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1667         bp->tx_mem_zone = NULL;
1668         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1669         bp->rx_mem_zone = NULL;
1670
1671         bnxt_free_vf_info(bp);
1672         bnxt_free_pf_info(bp);
1673
1674         rte_free(bp->grp_info);
1675         bp->grp_info = NULL;
1676 }
1677
1678 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1679 {
1680         struct bnxt *bp = eth_dev->data->dev_private;
1681         int ret = 0;
1682
1683         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1684                 return 0;
1685
1686         pthread_mutex_lock(&bp->err_recovery_lock);
1687         if (bp->flags & BNXT_FLAG_FW_RESET) {
1688                 PMD_DRV_LOG(ERR,
1689                             "Adapter recovering from error...Please retry\n");
1690                 pthread_mutex_unlock(&bp->err_recovery_lock);
1691                 return -EAGAIN;
1692         }
1693         pthread_mutex_unlock(&bp->err_recovery_lock);
1694
1695         /* cancel the recovery handler before remove dev */
1696         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1697         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1698         bnxt_cancel_fc_thread(bp);
1699
1700         if (eth_dev->data->dev_started)
1701                 ret = bnxt_dev_stop(eth_dev);
1702
1703         bnxt_uninit_resources(bp, false);
1704
1705         bnxt_drv_uninit(bp);
1706
1707         return ret;
1708 }
1709
1710 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1711                                     uint32_t index)
1712 {
1713         struct bnxt *bp = eth_dev->data->dev_private;
1714         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1715         struct bnxt_vnic_info *vnic;
1716         struct bnxt_filter_info *filter, *temp_filter;
1717         uint32_t i;
1718
1719         if (is_bnxt_in_error(bp))
1720                 return;
1721
1722         /*
1723          * Loop through all VNICs from the specified filter flow pools to
1724          * remove the corresponding MAC addr filter
1725          */
1726         for (i = 0; i < bp->nr_vnics; i++) {
1727                 if (!(pool_mask & (1ULL << i)))
1728                         continue;
1729
1730                 vnic = &bp->vnic_info[i];
1731                 filter = STAILQ_FIRST(&vnic->filter);
1732                 while (filter) {
1733                         temp_filter = STAILQ_NEXT(filter, next);
1734                         if (filter->mac_index == index) {
1735                                 STAILQ_REMOVE(&vnic->filter, filter,
1736                                                 bnxt_filter_info, next);
1737                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1738                                 bnxt_free_filter(bp, filter);
1739                         }
1740                         filter = temp_filter;
1741                 }
1742         }
1743 }
1744
1745 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1746                                struct rte_ether_addr *mac_addr, uint32_t index,
1747                                uint32_t pool)
1748 {
1749         struct bnxt_filter_info *filter;
1750         int rc = 0;
1751
1752         /* Attach requested MAC address to the new l2_filter */
1753         STAILQ_FOREACH(filter, &vnic->filter, next) {
1754                 if (filter->mac_index == index) {
1755                         PMD_DRV_LOG(DEBUG,
1756                                     "MAC addr already existed for pool %d\n",
1757                                     pool);
1758                         return 0;
1759                 }
1760         }
1761
1762         filter = bnxt_alloc_filter(bp);
1763         if (!filter) {
1764                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1765                 return -ENODEV;
1766         }
1767
1768         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1769          * if the MAC that's been programmed now is a different one, then,
1770          * copy that addr to filter->l2_addr
1771          */
1772         if (mac_addr)
1773                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1774         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1775
1776         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1777         if (!rc) {
1778                 filter->mac_index = index;
1779                 if (filter->mac_index == 0)
1780                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1781                 else
1782                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1783         } else {
1784                 bnxt_free_filter(bp, filter);
1785         }
1786
1787         return rc;
1788 }
1789
1790 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1791                                 struct rte_ether_addr *mac_addr,
1792                                 uint32_t index, uint32_t pool)
1793 {
1794         struct bnxt *bp = eth_dev->data->dev_private;
1795         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1796         int rc = 0;
1797
1798         rc = is_bnxt_in_error(bp);
1799         if (rc)
1800                 return rc;
1801
1802         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1803                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1804                 return -ENOTSUP;
1805         }
1806
1807         if (!vnic) {
1808                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1809                 return -EINVAL;
1810         }
1811
1812         /* Filter settings will get applied when port is started */
1813         if (!eth_dev->data->dev_started)
1814                 return 0;
1815
1816         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1817
1818         return rc;
1819 }
1820
1821 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1822 {
1823         int rc = 0;
1824         struct bnxt *bp = eth_dev->data->dev_private;
1825         struct rte_eth_link new;
1826         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1827                         BNXT_MIN_LINK_WAIT_CNT;
1828
1829         rc = is_bnxt_in_error(bp);
1830         if (rc)
1831                 return rc;
1832
1833         memset(&new, 0, sizeof(new));
1834
1835         if (bp->link_info == NULL)
1836                 goto out;
1837
1838         do {
1839                 /* Retrieve link info from hardware */
1840                 rc = bnxt_get_hwrm_link_config(bp, &new);
1841                 if (rc) {
1842                         new.link_speed = ETH_LINK_SPEED_100M;
1843                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1844                         PMD_DRV_LOG(ERR,
1845                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1846                         goto out;
1847                 }
1848
1849                 if (!wait_to_complete || new.link_status)
1850                         break;
1851
1852                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1853         } while (cnt--);
1854
1855         /* Only single function PF can bring phy down.
1856          * When port is stopped, report link down for VF/MH/NPAR functions.
1857          */
1858         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1859                 memset(&new, 0, sizeof(new));
1860
1861 out:
1862         /* Timed out or success */
1863         if (new.link_status != eth_dev->data->dev_link.link_status ||
1864             new.link_speed != eth_dev->data->dev_link.link_speed) {
1865                 rte_eth_linkstatus_set(eth_dev, &new);
1866                 bnxt_print_link_info(eth_dev);
1867         }
1868
1869         return rc;
1870 }
1871
1872 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1873 {
1874         struct bnxt *bp = eth_dev->data->dev_private;
1875         struct bnxt_vnic_info *vnic;
1876         uint32_t old_flags;
1877         int rc;
1878
1879         rc = is_bnxt_in_error(bp);
1880         if (rc)
1881                 return rc;
1882
1883         /* Filter settings will get applied when port is started */
1884         if (!eth_dev->data->dev_started)
1885                 return 0;
1886
1887         if (bp->vnic_info == NULL)
1888                 return 0;
1889
1890         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1891
1892         old_flags = vnic->flags;
1893         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1894         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1895         if (rc != 0)
1896                 vnic->flags = old_flags;
1897
1898         return rc;
1899 }
1900
1901 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1902 {
1903         struct bnxt *bp = eth_dev->data->dev_private;
1904         struct bnxt_vnic_info *vnic;
1905         uint32_t old_flags;
1906         int rc;
1907
1908         rc = is_bnxt_in_error(bp);
1909         if (rc)
1910                 return rc;
1911
1912         /* Filter settings will get applied when port is started */
1913         if (!eth_dev->data->dev_started)
1914                 return 0;
1915
1916         if (bp->vnic_info == NULL)
1917                 return 0;
1918
1919         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1920
1921         old_flags = vnic->flags;
1922         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1923         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1924         if (rc != 0)
1925                 vnic->flags = old_flags;
1926
1927         return rc;
1928 }
1929
1930 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1931 {
1932         struct bnxt *bp = eth_dev->data->dev_private;
1933         struct bnxt_vnic_info *vnic;
1934         uint32_t old_flags;
1935         int rc;
1936
1937         rc = is_bnxt_in_error(bp);
1938         if (rc)
1939                 return rc;
1940
1941         /* Filter settings will get applied when port is started */
1942         if (!eth_dev->data->dev_started)
1943                 return 0;
1944
1945         if (bp->vnic_info == NULL)
1946                 return 0;
1947
1948         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1949
1950         old_flags = vnic->flags;
1951         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1952         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1953         if (rc != 0)
1954                 vnic->flags = old_flags;
1955
1956         return rc;
1957 }
1958
1959 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1960 {
1961         struct bnxt *bp = eth_dev->data->dev_private;
1962         struct bnxt_vnic_info *vnic;
1963         uint32_t old_flags;
1964         int rc;
1965
1966         rc = is_bnxt_in_error(bp);
1967         if (rc)
1968                 return rc;
1969
1970         /* Filter settings will get applied when port is started */
1971         if (!eth_dev->data->dev_started)
1972                 return 0;
1973
1974         if (bp->vnic_info == NULL)
1975                 return 0;
1976
1977         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1978
1979         old_flags = vnic->flags;
1980         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1981         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1982         if (rc != 0)
1983                 vnic->flags = old_flags;
1984
1985         return rc;
1986 }
1987
1988 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1989 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1990 {
1991         if (qid >= bp->rx_nr_rings)
1992                 return NULL;
1993
1994         return bp->eth_dev->data->rx_queues[qid];
1995 }
1996
1997 /* Return rxq corresponding to a given rss table ring/group ID. */
1998 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1999 {
2000         struct bnxt_rx_queue *rxq;
2001         unsigned int i;
2002
2003         if (!BNXT_HAS_RING_GRPS(bp)) {
2004                 for (i = 0; i < bp->rx_nr_rings; i++) {
2005                         rxq = bp->eth_dev->data->rx_queues[i];
2006                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
2007                                 return rxq->index;
2008                 }
2009         } else {
2010                 for (i = 0; i < bp->rx_nr_rings; i++) {
2011                         if (bp->grp_info[i].fw_grp_id == fwr)
2012                                 return i;
2013                 }
2014         }
2015
2016         return INVALID_HW_RING_ID;
2017 }
2018
2019 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
2020                             struct rte_eth_rss_reta_entry64 *reta_conf,
2021                             uint16_t reta_size)
2022 {
2023         struct bnxt *bp = eth_dev->data->dev_private;
2024         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2025         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2026         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2027         uint16_t idx, sft;
2028         int i, rc;
2029
2030         rc = is_bnxt_in_error(bp);
2031         if (rc)
2032                 return rc;
2033
2034         if (!vnic->rss_table)
2035                 return -EINVAL;
2036
2037         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
2038                 return -EINVAL;
2039
2040         if (reta_size != tbl_size) {
2041                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2042                         "(%d) must equal the size supported by the hardware "
2043                         "(%d)\n", reta_size, tbl_size);
2044                 return -EINVAL;
2045         }
2046
2047         for (i = 0; i < reta_size; i++) {
2048                 struct bnxt_rx_queue *rxq;
2049
2050                 idx = i / RTE_RETA_GROUP_SIZE;
2051                 sft = i % RTE_RETA_GROUP_SIZE;
2052
2053                 if (!(reta_conf[idx].mask & (1ULL << sft)))
2054                         continue;
2055
2056                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
2057                 if (!rxq) {
2058                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2059                         return -EINVAL;
2060                 }
2061
2062                 if (BNXT_CHIP_P5(bp)) {
2063                         vnic->rss_table[i * 2] =
2064                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2065                         vnic->rss_table[i * 2 + 1] =
2066                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2067                 } else {
2068                         vnic->rss_table[i] =
2069                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2070                 }
2071         }
2072
2073         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2074         return rc;
2075 }
2076
2077 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2078                               struct rte_eth_rss_reta_entry64 *reta_conf,
2079                               uint16_t reta_size)
2080 {
2081         struct bnxt *bp = eth_dev->data->dev_private;
2082         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2083         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2084         uint16_t idx, sft, i;
2085         int rc;
2086
2087         rc = is_bnxt_in_error(bp);
2088         if (rc)
2089                 return rc;
2090
2091         if (!vnic)
2092                 return -EINVAL;
2093         if (!vnic->rss_table)
2094                 return -EINVAL;
2095
2096         if (reta_size != tbl_size) {
2097                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2098                         "(%d) must equal the size supported by the hardware "
2099                         "(%d)\n", reta_size, tbl_size);
2100                 return -EINVAL;
2101         }
2102
2103         for (idx = 0, i = 0; i < reta_size; i++) {
2104                 idx = i / RTE_RETA_GROUP_SIZE;
2105                 sft = i % RTE_RETA_GROUP_SIZE;
2106
2107                 if (reta_conf[idx].mask & (1ULL << sft)) {
2108                         uint16_t qid;
2109
2110                         if (BNXT_CHIP_P5(bp))
2111                                 qid = bnxt_rss_to_qid(bp,
2112                                                       vnic->rss_table[i * 2]);
2113                         else
2114                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2115
2116                         if (qid == INVALID_HW_RING_ID) {
2117                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2118                                 return -EINVAL;
2119                         }
2120                         reta_conf[idx].reta[sft] = qid;
2121                 }
2122         }
2123
2124         return 0;
2125 }
2126
2127 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2128                                    struct rte_eth_rss_conf *rss_conf)
2129 {
2130         struct bnxt *bp = eth_dev->data->dev_private;
2131         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2132         struct bnxt_vnic_info *vnic;
2133         int rc;
2134
2135         rc = is_bnxt_in_error(bp);
2136         if (rc)
2137                 return rc;
2138
2139         /*
2140          * If RSS enablement were different than dev_configure,
2141          * then return -EINVAL
2142          */
2143         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2144                 if (!rss_conf->rss_hf)
2145                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
2146         } else {
2147                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2148                         return -EINVAL;
2149         }
2150
2151         bp->flags |= BNXT_FLAG_UPDATE_HASH;
2152         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
2153                rss_conf,
2154                sizeof(*rss_conf));
2155
2156         /* Update the default RSS VNIC(s) */
2157         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2158         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2159         vnic->hash_mode =
2160                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2161                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
2162
2163         /*
2164          * If hashkey is not specified, use the previously configured
2165          * hashkey
2166          */
2167         if (!rss_conf->rss_key)
2168                 goto rss_config;
2169
2170         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2171                 PMD_DRV_LOG(ERR,
2172                             "Invalid hashkey length, should be %d bytes\n",
2173                             HW_HASH_KEY_SIZE);
2174                 return -EINVAL;
2175         }
2176         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2177
2178 rss_config:
2179         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2180         return rc;
2181 }
2182
2183 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2184                                      struct rte_eth_rss_conf *rss_conf)
2185 {
2186         struct bnxt *bp = eth_dev->data->dev_private;
2187         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2188         int len, rc;
2189         uint32_t hash_types;
2190
2191         rc = is_bnxt_in_error(bp);
2192         if (rc)
2193                 return rc;
2194
2195         /* RSS configuration is the same for all VNICs */
2196         if (vnic && vnic->rss_hash_key) {
2197                 if (rss_conf->rss_key) {
2198                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2199                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2200                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2201                 }
2202
2203                 hash_types = vnic->hash_type;
2204                 rss_conf->rss_hf = 0;
2205                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2206                         rss_conf->rss_hf |= ETH_RSS_IPV4;
2207                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2208                 }
2209                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2210                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2211                         hash_types &=
2212                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2213                 }
2214                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2215                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2216                         hash_types &=
2217                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2218                 }
2219                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2220                         rss_conf->rss_hf |= ETH_RSS_IPV6;
2221                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2222                 }
2223                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2224                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2225                         hash_types &=
2226                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2227                 }
2228                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2229                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2230                         hash_types &=
2231                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2232                 }
2233
2234                 rss_conf->rss_hf |=
2235                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2236
2237                 if (hash_types) {
2238                         PMD_DRV_LOG(ERR,
2239                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2240                                 vnic->hash_type);
2241                         return -ENOTSUP;
2242                 }
2243         } else {
2244                 rss_conf->rss_hf = 0;
2245         }
2246         return 0;
2247 }
2248
2249 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2250                                struct rte_eth_fc_conf *fc_conf)
2251 {
2252         struct bnxt *bp = dev->data->dev_private;
2253         struct rte_eth_link link_info;
2254         int rc;
2255
2256         rc = is_bnxt_in_error(bp);
2257         if (rc)
2258                 return rc;
2259
2260         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2261         if (rc)
2262                 return rc;
2263
2264         memset(fc_conf, 0, sizeof(*fc_conf));
2265         if (bp->link_info->auto_pause)
2266                 fc_conf->autoneg = 1;
2267         switch (bp->link_info->pause) {
2268         case 0:
2269                 fc_conf->mode = RTE_FC_NONE;
2270                 break;
2271         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2272                 fc_conf->mode = RTE_FC_TX_PAUSE;
2273                 break;
2274         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2275                 fc_conf->mode = RTE_FC_RX_PAUSE;
2276                 break;
2277         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2278                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2279                 fc_conf->mode = RTE_FC_FULL;
2280                 break;
2281         }
2282         return 0;
2283 }
2284
2285 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2286                                struct rte_eth_fc_conf *fc_conf)
2287 {
2288         struct bnxt *bp = dev->data->dev_private;
2289         int rc;
2290
2291         rc = is_bnxt_in_error(bp);
2292         if (rc)
2293                 return rc;
2294
2295         if (!BNXT_SINGLE_PF(bp)) {
2296                 PMD_DRV_LOG(ERR,
2297                             "Flow Control Settings cannot be modified on VF or on shared PF\n");
2298                 return -ENOTSUP;
2299         }
2300
2301         switch (fc_conf->mode) {
2302         case RTE_FC_NONE:
2303                 bp->link_info->auto_pause = 0;
2304                 bp->link_info->force_pause = 0;
2305                 break;
2306         case RTE_FC_RX_PAUSE:
2307                 if (fc_conf->autoneg) {
2308                         bp->link_info->auto_pause =
2309                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2310                         bp->link_info->force_pause = 0;
2311                 } else {
2312                         bp->link_info->auto_pause = 0;
2313                         bp->link_info->force_pause =
2314                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2315                 }
2316                 break;
2317         case RTE_FC_TX_PAUSE:
2318                 if (fc_conf->autoneg) {
2319                         bp->link_info->auto_pause =
2320                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2321                         bp->link_info->force_pause = 0;
2322                 } else {
2323                         bp->link_info->auto_pause = 0;
2324                         bp->link_info->force_pause =
2325                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2326                 }
2327                 break;
2328         case RTE_FC_FULL:
2329                 if (fc_conf->autoneg) {
2330                         bp->link_info->auto_pause =
2331                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2332                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2333                         bp->link_info->force_pause = 0;
2334                 } else {
2335                         bp->link_info->auto_pause = 0;
2336                         bp->link_info->force_pause =
2337                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2338                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2339                 }
2340                 break;
2341         }
2342         return bnxt_set_hwrm_link_config(bp, true);
2343 }
2344
2345 /* Add UDP tunneling port */
2346 static int
2347 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2348                          struct rte_eth_udp_tunnel *udp_tunnel)
2349 {
2350         struct bnxt *bp = eth_dev->data->dev_private;
2351         uint16_t tunnel_type = 0;
2352         int rc = 0;
2353
2354         rc = is_bnxt_in_error(bp);
2355         if (rc)
2356                 return rc;
2357
2358         switch (udp_tunnel->prot_type) {
2359         case RTE_TUNNEL_TYPE_VXLAN:
2360                 if (bp->vxlan_port_cnt) {
2361                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2362                                 udp_tunnel->udp_port);
2363                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2364                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2365                                 return -ENOSPC;
2366                         }
2367                         bp->vxlan_port_cnt++;
2368                         return 0;
2369                 }
2370                 tunnel_type =
2371                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2372                 bp->vxlan_port_cnt++;
2373                 break;
2374         case RTE_TUNNEL_TYPE_GENEVE:
2375                 if (bp->geneve_port_cnt) {
2376                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2377                                 udp_tunnel->udp_port);
2378                         if (bp->geneve_port != udp_tunnel->udp_port) {
2379                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2380                                 return -ENOSPC;
2381                         }
2382                         bp->geneve_port_cnt++;
2383                         return 0;
2384                 }
2385                 tunnel_type =
2386                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2387                 bp->geneve_port_cnt++;
2388                 break;
2389         default:
2390                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2391                 return -ENOTSUP;
2392         }
2393         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2394                                              tunnel_type);
2395         return rc;
2396 }
2397
2398 static int
2399 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2400                          struct rte_eth_udp_tunnel *udp_tunnel)
2401 {
2402         struct bnxt *bp = eth_dev->data->dev_private;
2403         uint16_t tunnel_type = 0;
2404         uint16_t port = 0;
2405         int rc = 0;
2406
2407         rc = is_bnxt_in_error(bp);
2408         if (rc)
2409                 return rc;
2410
2411         switch (udp_tunnel->prot_type) {
2412         case RTE_TUNNEL_TYPE_VXLAN:
2413                 if (!bp->vxlan_port_cnt) {
2414                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2415                         return -EINVAL;
2416                 }
2417                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2418                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2419                                 udp_tunnel->udp_port, bp->vxlan_port);
2420                         return -EINVAL;
2421                 }
2422                 if (--bp->vxlan_port_cnt)
2423                         return 0;
2424
2425                 tunnel_type =
2426                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2427                 port = bp->vxlan_fw_dst_port_id;
2428                 break;
2429         case RTE_TUNNEL_TYPE_GENEVE:
2430                 if (!bp->geneve_port_cnt) {
2431                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2432                         return -EINVAL;
2433                 }
2434                 if (bp->geneve_port != udp_tunnel->udp_port) {
2435                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2436                                 udp_tunnel->udp_port, bp->geneve_port);
2437                         return -EINVAL;
2438                 }
2439                 if (--bp->geneve_port_cnt)
2440                         return 0;
2441
2442                 tunnel_type =
2443                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2444                 port = bp->geneve_fw_dst_port_id;
2445                 break;
2446         default:
2447                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2448                 return -ENOTSUP;
2449         }
2450
2451         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2452         return rc;
2453 }
2454
2455 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2456 {
2457         struct bnxt_filter_info *filter;
2458         struct bnxt_vnic_info *vnic;
2459         int rc = 0;
2460         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2461
2462         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2463         filter = STAILQ_FIRST(&vnic->filter);
2464         while (filter) {
2465                 /* Search for this matching MAC+VLAN filter */
2466                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2467                         /* Delete the filter */
2468                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2469                         if (rc)
2470                                 return rc;
2471                         STAILQ_REMOVE(&vnic->filter, filter,
2472                                       bnxt_filter_info, next);
2473                         bnxt_free_filter(bp, filter);
2474                         PMD_DRV_LOG(INFO,
2475                                     "Deleted vlan filter for %d\n",
2476                                     vlan_id);
2477                         return 0;
2478                 }
2479                 filter = STAILQ_NEXT(filter, next);
2480         }
2481         return -ENOENT;
2482 }
2483
2484 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2485 {
2486         struct bnxt_filter_info *filter;
2487         struct bnxt_vnic_info *vnic;
2488         int rc = 0;
2489         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2490                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2491         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2492
2493         /* Implementation notes on the use of VNIC in this command:
2494          *
2495          * By default, these filters belong to default vnic for the function.
2496          * Once these filters are set up, only destination VNIC can be modified.
2497          * If the destination VNIC is not specified in this command,
2498          * then the HWRM shall only create an l2 context id.
2499          */
2500
2501         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2502         filter = STAILQ_FIRST(&vnic->filter);
2503         /* Check if the VLAN has already been added */
2504         while (filter) {
2505                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2506                         return -EEXIST;
2507
2508                 filter = STAILQ_NEXT(filter, next);
2509         }
2510
2511         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2512          * command to create MAC+VLAN filter with the right flags, enables set.
2513          */
2514         filter = bnxt_alloc_filter(bp);
2515         if (!filter) {
2516                 PMD_DRV_LOG(ERR,
2517                             "MAC/VLAN filter alloc failed\n");
2518                 return -ENOMEM;
2519         }
2520         /* MAC + VLAN ID filter */
2521         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2522          * untagged packets are received
2523          *
2524          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2525          * packets and only the programmed vlan's packets are received
2526          */
2527         filter->l2_ivlan = vlan_id;
2528         filter->l2_ivlan_mask = 0x0FFF;
2529         filter->enables |= en;
2530         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2531
2532         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2533         if (rc) {
2534                 /* Free the newly allocated filter as we were
2535                  * not able to create the filter in hardware.
2536                  */
2537                 bnxt_free_filter(bp, filter);
2538                 return rc;
2539         }
2540
2541         filter->mac_index = 0;
2542         /* Add this new filter to the list */
2543         if (vlan_id == 0)
2544                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2545         else
2546                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2547
2548         PMD_DRV_LOG(INFO,
2549                     "Added Vlan filter for %d\n", vlan_id);
2550         return rc;
2551 }
2552
2553 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2554                 uint16_t vlan_id, int on)
2555 {
2556         struct bnxt *bp = eth_dev->data->dev_private;
2557         int rc;
2558
2559         rc = is_bnxt_in_error(bp);
2560         if (rc)
2561                 return rc;
2562
2563         if (!eth_dev->data->dev_started) {
2564                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2565                 return -EINVAL;
2566         }
2567
2568         /* These operations apply to ALL existing MAC/VLAN filters */
2569         if (on)
2570                 return bnxt_add_vlan_filter(bp, vlan_id);
2571         else
2572                 return bnxt_del_vlan_filter(bp, vlan_id);
2573 }
2574
2575 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2576                                     struct bnxt_vnic_info *vnic)
2577 {
2578         struct bnxt_filter_info *filter;
2579         int rc;
2580
2581         filter = STAILQ_FIRST(&vnic->filter);
2582         while (filter) {
2583                 if (filter->mac_index == 0 &&
2584                     !memcmp(filter->l2_addr, bp->mac_addr,
2585                             RTE_ETHER_ADDR_LEN)) {
2586                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2587                         if (!rc) {
2588                                 STAILQ_REMOVE(&vnic->filter, filter,
2589                                               bnxt_filter_info, next);
2590                                 bnxt_free_filter(bp, filter);
2591                         }
2592                         return rc;
2593                 }
2594                 filter = STAILQ_NEXT(filter, next);
2595         }
2596         return 0;
2597 }
2598
2599 static int
2600 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2601 {
2602         struct bnxt_vnic_info *vnic;
2603         unsigned int i;
2604         int rc;
2605
2606         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2607         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2608                 /* Remove any VLAN filters programmed */
2609                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2610                         bnxt_del_vlan_filter(bp, i);
2611
2612                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2613                 if (rc)
2614                         return rc;
2615         } else {
2616                 /* Default filter will allow packets that match the
2617                  * dest mac. So, it has to be deleted, otherwise, we
2618                  * will endup receiving vlan packets for which the
2619                  * filter is not programmed, when hw-vlan-filter
2620                  * configuration is ON
2621                  */
2622                 bnxt_del_dflt_mac_filter(bp, vnic);
2623                 /* This filter will allow only untagged packets */
2624                 bnxt_add_vlan_filter(bp, 0);
2625         }
2626         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2627                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2628
2629         return 0;
2630 }
2631
2632 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2633 {
2634         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2635         unsigned int i;
2636         int rc;
2637
2638         /* Destroy vnic filters and vnic */
2639         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2640             DEV_RX_OFFLOAD_VLAN_FILTER) {
2641                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2642                         bnxt_del_vlan_filter(bp, i);
2643         }
2644         bnxt_del_dflt_mac_filter(bp, vnic);
2645
2646         rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2647         if (rc)
2648                 return rc;
2649
2650         rc = bnxt_hwrm_vnic_free(bp, vnic);
2651         if (rc)
2652                 return rc;
2653
2654         rte_free(vnic->fw_grp_ids);
2655         vnic->fw_grp_ids = NULL;
2656
2657         vnic->rx_queue_cnt = 0;
2658
2659         return 0;
2660 }
2661
2662 static int
2663 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2664 {
2665         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2666         int rc;
2667
2668         /* Destroy, recreate and reconfigure the default vnic */
2669         rc = bnxt_free_one_vnic(bp, 0);
2670         if (rc)
2671                 return rc;
2672
2673         /* default vnic 0 */
2674         rc = bnxt_setup_one_vnic(bp, 0);
2675         if (rc)
2676                 return rc;
2677
2678         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2679             DEV_RX_OFFLOAD_VLAN_FILTER) {
2680                 rc = bnxt_add_vlan_filter(bp, 0);
2681                 if (rc)
2682                         return rc;
2683                 rc = bnxt_restore_vlan_filters(bp);
2684                 if (rc)
2685                         return rc;
2686         } else {
2687                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2688                 if (rc)
2689                         return rc;
2690         }
2691
2692         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2693         if (rc)
2694                 return rc;
2695
2696         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2697                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2698
2699         return rc;
2700 }
2701
2702 static int
2703 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2704 {
2705         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2706         struct bnxt *bp = dev->data->dev_private;
2707         int rc;
2708
2709         rc = is_bnxt_in_error(bp);
2710         if (rc)
2711                 return rc;
2712
2713         /* Filter settings will get applied when port is started */
2714         if (!dev->data->dev_started)
2715                 return 0;
2716
2717         if (mask & ETH_VLAN_FILTER_MASK) {
2718                 /* Enable or disable VLAN filtering */
2719                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2720                 if (rc)
2721                         return rc;
2722         }
2723
2724         if (mask & ETH_VLAN_STRIP_MASK) {
2725                 /* Enable or disable VLAN stripping */
2726                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2727                 if (rc)
2728                         return rc;
2729         }
2730
2731         if (mask & ETH_VLAN_EXTEND_MASK) {
2732                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2733                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2734                 else
2735                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2736         }
2737
2738         return 0;
2739 }
2740
2741 static int
2742 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2743                       uint16_t tpid)
2744 {
2745         struct bnxt *bp = dev->data->dev_private;
2746         int qinq = dev->data->dev_conf.rxmode.offloads &
2747                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2748
2749         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2750             vlan_type != ETH_VLAN_TYPE_OUTER) {
2751                 PMD_DRV_LOG(ERR,
2752                             "Unsupported vlan type.");
2753                 return -EINVAL;
2754         }
2755         if (!qinq) {
2756                 PMD_DRV_LOG(ERR,
2757                             "QinQ not enabled. Needs to be ON as we can "
2758                             "accelerate only outer vlan\n");
2759                 return -EINVAL;
2760         }
2761
2762         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2763                 switch (tpid) {
2764                 case RTE_ETHER_TYPE_QINQ:
2765                         bp->outer_tpid_bd =
2766                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2767                                 break;
2768                 case RTE_ETHER_TYPE_VLAN:
2769                         bp->outer_tpid_bd =
2770                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2771                                 break;
2772                 case RTE_ETHER_TYPE_QINQ1:
2773                         bp->outer_tpid_bd =
2774                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2775                                 break;
2776                 case RTE_ETHER_TYPE_QINQ2:
2777                         bp->outer_tpid_bd =
2778                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2779                                 break;
2780                 case RTE_ETHER_TYPE_QINQ3:
2781                         bp->outer_tpid_bd =
2782                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2783                                 break;
2784                 default:
2785                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2786                         return -EINVAL;
2787                 }
2788                 bp->outer_tpid_bd |= tpid;
2789                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2790         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2791                 PMD_DRV_LOG(ERR,
2792                             "Can accelerate only outer vlan in QinQ\n");
2793                 return -EINVAL;
2794         }
2795
2796         return 0;
2797 }
2798
2799 static int
2800 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2801                              struct rte_ether_addr *addr)
2802 {
2803         struct bnxt *bp = dev->data->dev_private;
2804         /* Default Filter is tied to VNIC 0 */
2805         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2806         int rc;
2807
2808         rc = is_bnxt_in_error(bp);
2809         if (rc)
2810                 return rc;
2811
2812         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2813                 return -EPERM;
2814
2815         if (rte_is_zero_ether_addr(addr))
2816                 return -EINVAL;
2817
2818         /* Filter settings will get applied when port is started */
2819         if (!dev->data->dev_started)
2820                 return 0;
2821
2822         /* Check if the requested MAC is already added */
2823         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2824                 return 0;
2825
2826         /* Destroy filter and re-create it */
2827         bnxt_del_dflt_mac_filter(bp, vnic);
2828
2829         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2830         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2831                 /* This filter will allow only untagged packets */
2832                 rc = bnxt_add_vlan_filter(bp, 0);
2833         } else {
2834                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2835         }
2836
2837         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2838         return rc;
2839 }
2840
2841 static int
2842 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2843                           struct rte_ether_addr *mc_addr_set,
2844                           uint32_t nb_mc_addr)
2845 {
2846         struct bnxt *bp = eth_dev->data->dev_private;
2847         char *mc_addr_list = (char *)mc_addr_set;
2848         struct bnxt_vnic_info *vnic;
2849         uint32_t off = 0, i = 0;
2850         int rc;
2851
2852         rc = is_bnxt_in_error(bp);
2853         if (rc)
2854                 return rc;
2855
2856         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2857
2858         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2859                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2860                 goto allmulti;
2861         }
2862
2863         /* TODO Check for Duplicate mcast addresses */
2864         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2865         for (i = 0; i < nb_mc_addr; i++) {
2866                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2867                         RTE_ETHER_ADDR_LEN);
2868                 off += RTE_ETHER_ADDR_LEN;
2869         }
2870
2871         vnic->mc_addr_cnt = i;
2872         if (vnic->mc_addr_cnt)
2873                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2874         else
2875                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2876
2877 allmulti:
2878         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2879 }
2880
2881 static int
2882 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2883 {
2884         struct bnxt *bp = dev->data->dev_private;
2885         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2886         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2887         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2888         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2889         int ret;
2890
2891         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2892                         fw_major, fw_minor, fw_updt, fw_rsvd);
2893         if (ret < 0)
2894                 return -EINVAL;
2895
2896         ret += 1; /* add the size of '\0' */
2897         if (fw_size < (size_t)ret)
2898                 return ret;
2899         else
2900                 return 0;
2901 }
2902
2903 static void
2904 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2905         struct rte_eth_rxq_info *qinfo)
2906 {
2907         struct bnxt *bp = dev->data->dev_private;
2908         struct bnxt_rx_queue *rxq;
2909
2910         if (is_bnxt_in_error(bp))
2911                 return;
2912
2913         rxq = dev->data->rx_queues[queue_id];
2914
2915         qinfo->mp = rxq->mb_pool;
2916         qinfo->scattered_rx = dev->data->scattered_rx;
2917         qinfo->nb_desc = rxq->nb_rx_desc;
2918
2919         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2920         qinfo->conf.rx_drop_en = rxq->drop_en;
2921         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2922         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2923 }
2924
2925 static void
2926 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2927         struct rte_eth_txq_info *qinfo)
2928 {
2929         struct bnxt *bp = dev->data->dev_private;
2930         struct bnxt_tx_queue *txq;
2931
2932         if (is_bnxt_in_error(bp))
2933                 return;
2934
2935         txq = dev->data->tx_queues[queue_id];
2936
2937         qinfo->nb_desc = txq->nb_tx_desc;
2938
2939         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2940         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2941         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2942
2943         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2944         qinfo->conf.tx_rs_thresh = 0;
2945         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2946         qinfo->conf.offloads = txq->offloads;
2947 }
2948
2949 static const struct {
2950         eth_rx_burst_t pkt_burst;
2951         const char *info;
2952 } bnxt_rx_burst_info[] = {
2953         {bnxt_recv_pkts,                "Scalar"},
2954 #if defined(RTE_ARCH_X86)
2955         {bnxt_recv_pkts_vec,            "Vector SSE"},
2956 #endif
2957 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2958         {bnxt_recv_pkts_vec_avx2,       "Vector AVX2"},
2959 #endif
2960 #if defined(RTE_ARCH_ARM64)
2961         {bnxt_recv_pkts_vec,            "Vector Neon"},
2962 #endif
2963 };
2964
2965 static int
2966 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2967                        struct rte_eth_burst_mode *mode)
2968 {
2969         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2970         size_t i;
2971
2972         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2973                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2974                         snprintf(mode->info, sizeof(mode->info), "%s",
2975                                  bnxt_rx_burst_info[i].info);
2976                         return 0;
2977                 }
2978         }
2979
2980         return -EINVAL;
2981 }
2982
2983 static const struct {
2984         eth_tx_burst_t pkt_burst;
2985         const char *info;
2986 } bnxt_tx_burst_info[] = {
2987         {bnxt_xmit_pkts,                "Scalar"},
2988 #if defined(RTE_ARCH_X86)
2989         {bnxt_xmit_pkts_vec,            "Vector SSE"},
2990 #endif
2991 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2992         {bnxt_xmit_pkts_vec_avx2,       "Vector AVX2"},
2993 #endif
2994 #if defined(RTE_ARCH_ARM64)
2995         {bnxt_xmit_pkts_vec,            "Vector Neon"},
2996 #endif
2997 };
2998
2999 static int
3000 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3001                        struct rte_eth_burst_mode *mode)
3002 {
3003         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3004         size_t i;
3005
3006         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
3007                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
3008                         snprintf(mode->info, sizeof(mode->info), "%s",
3009                                  bnxt_tx_burst_info[i].info);
3010                         return 0;
3011                 }
3012         }
3013
3014         return -EINVAL;
3015 }
3016
3017 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
3018 {
3019         struct bnxt *bp = eth_dev->data->dev_private;
3020         uint32_t new_pkt_size;
3021         uint32_t rc = 0;
3022         uint32_t i;
3023
3024         rc = is_bnxt_in_error(bp);
3025         if (rc)
3026                 return rc;
3027
3028         /* Exit if receive queues are not configured yet */
3029         if (!eth_dev->data->nb_rx_queues)
3030                 return rc;
3031
3032         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
3033                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
3034
3035         /*
3036          * Disallow any MTU change that would require scattered receive support
3037          * if it is not already enabled.
3038          */
3039         if (eth_dev->data->dev_started &&
3040             !eth_dev->data->scattered_rx &&
3041             (new_pkt_size >
3042              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3043                 PMD_DRV_LOG(ERR,
3044                             "MTU change would require scattered rx support. ");
3045                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
3046                 return -EINVAL;
3047         }
3048
3049         if (new_mtu > RTE_ETHER_MTU) {
3050                 bp->flags |= BNXT_FLAG_JUMBO;
3051                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
3052                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3053         } else {
3054                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
3055                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3056                 bp->flags &= ~BNXT_FLAG_JUMBO;
3057         }
3058
3059         /* Is there a change in mtu setting? */
3060         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
3061                 return rc;
3062
3063         for (i = 0; i < bp->nr_vnics; i++) {
3064                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3065                 uint16_t size = 0;
3066
3067                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3068                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3069                 if (rc)
3070                         break;
3071
3072                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3073                 size -= RTE_PKTMBUF_HEADROOM;
3074
3075                 if (size < new_mtu) {
3076                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3077                         if (rc)
3078                                 return rc;
3079                 }
3080         }
3081
3082         if (!rc)
3083                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
3084
3085         if (bnxt_hwrm_config_host_mtu(bp))
3086                 PMD_DRV_LOG(WARNING, "Failed to configure host MTU\n");
3087
3088         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3089
3090         return rc;
3091 }
3092
3093 static int
3094 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3095 {
3096         struct bnxt *bp = dev->data->dev_private;
3097         uint16_t vlan = bp->vlan;
3098         int rc;
3099
3100         rc = is_bnxt_in_error(bp);
3101         if (rc)
3102                 return rc;
3103
3104         if (!BNXT_SINGLE_PF(bp)) {
3105                 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3106                 return -ENOTSUP;
3107         }
3108         bp->vlan = on ? pvid : 0;
3109
3110         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3111         if (rc)
3112                 bp->vlan = vlan;
3113         return rc;
3114 }
3115
3116 static int
3117 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3118 {
3119         struct bnxt *bp = dev->data->dev_private;
3120         int rc;
3121
3122         rc = is_bnxt_in_error(bp);
3123         if (rc)
3124                 return rc;
3125
3126         return bnxt_hwrm_port_led_cfg(bp, true);
3127 }
3128
3129 static int
3130 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3131 {
3132         struct bnxt *bp = dev->data->dev_private;
3133         int rc;
3134
3135         rc = is_bnxt_in_error(bp);
3136         if (rc)
3137                 return rc;
3138
3139         return bnxt_hwrm_port_led_cfg(bp, false);
3140 }
3141
3142 static uint32_t
3143 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3144 {
3145         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3146         struct bnxt_cp_ring_info *cpr;
3147         uint32_t desc = 0, raw_cons, cp_ring_size;
3148         struct bnxt_rx_queue *rxq;
3149         struct rx_pkt_cmpl *rxcmp;
3150         int rc;
3151
3152         rc = is_bnxt_in_error(bp);
3153         if (rc)
3154                 return rc;
3155
3156         rxq = dev->data->rx_queues[rx_queue_id];
3157         cpr = rxq->cp_ring;
3158         raw_cons = cpr->cp_raw_cons;
3159         cp_ring_size = cpr->cp_ring_struct->ring_size;
3160
3161         while (1) {
3162                 uint32_t agg_cnt, cons, cmpl_type;
3163
3164                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3165                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3166
3167                 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3168                         break;
3169
3170                 cmpl_type = CMP_TYPE(rxcmp);
3171
3172                 switch (cmpl_type) {
3173                 case CMPL_BASE_TYPE_RX_L2:
3174                 case CMPL_BASE_TYPE_RX_L2_V2:
3175                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3176                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3177                         desc++;
3178                         break;
3179
3180                 case CMPL_BASE_TYPE_RX_TPA_END:
3181                         if (BNXT_CHIP_P5(rxq->bp)) {
3182                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3183
3184                                 p5_tpa_end = (void *)rxcmp;
3185                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3186                         } else {
3187                                 struct rx_tpa_end_cmpl *tpa_end;
3188
3189                                 tpa_end = (void *)rxcmp;
3190                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3191                         }
3192
3193                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3194                         desc++;
3195                         break;
3196
3197                 default:
3198                         raw_cons += CMP_LEN(cmpl_type);
3199                 }
3200         }
3201
3202         return desc;
3203 }
3204
3205 static int
3206 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3207 {
3208         struct bnxt_rx_queue *rxq = rx_queue;
3209         struct bnxt_cp_ring_info *cpr;
3210         struct bnxt_rx_ring_info *rxr;
3211         uint32_t desc, raw_cons, cp_ring_size;
3212         struct bnxt *bp = rxq->bp;
3213         struct rx_pkt_cmpl *rxcmp;
3214         int rc;
3215
3216         rc = is_bnxt_in_error(bp);
3217         if (rc)
3218                 return rc;
3219
3220         if (offset >= rxq->nb_rx_desc)
3221                 return -EINVAL;
3222
3223         rxr = rxq->rx_ring;
3224         cpr = rxq->cp_ring;
3225         cp_ring_size = cpr->cp_ring_struct->ring_size;
3226
3227         /*
3228          * For the vector receive case, the completion at the requested
3229          * offset can be indexed directly.
3230          */
3231 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3232         if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3233                 struct rx_pkt_cmpl *rxcmp;
3234                 uint32_t cons;
3235
3236                 /* Check status of completion descriptor. */
3237                 raw_cons = cpr->cp_raw_cons +
3238                            offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3239                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3240                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3241
3242                 if (bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3243                         return RTE_ETH_RX_DESC_DONE;
3244
3245                 /* Check whether rx desc has an mbuf attached. */
3246                 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3247                 if (cons >= rxq->rxrearm_start &&
3248                     cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3249                         return RTE_ETH_RX_DESC_UNAVAIL;
3250                 }
3251
3252                 return RTE_ETH_RX_DESC_AVAIL;
3253         }
3254 #endif
3255
3256         /*
3257          * For the non-vector receive case, scan the completion ring to
3258          * locate the completion descriptor for the requested offset.
3259          */
3260         raw_cons = cpr->cp_raw_cons;
3261         desc = 0;
3262         while (1) {
3263                 uint32_t agg_cnt, cons, cmpl_type;
3264
3265                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3266                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3267
3268                 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3269                         break;
3270
3271                 cmpl_type = CMP_TYPE(rxcmp);
3272
3273                 switch (cmpl_type) {
3274                 case CMPL_BASE_TYPE_RX_L2:
3275                 case CMPL_BASE_TYPE_RX_L2_V2:
3276                         if (desc == offset) {
3277                                 cons = rxcmp->opaque;
3278                                 if (rxr->rx_buf_ring[cons])
3279                                         return RTE_ETH_RX_DESC_DONE;
3280                                 else
3281                                         return RTE_ETH_RX_DESC_UNAVAIL;
3282                         }
3283                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3284                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3285                         desc++;
3286                         break;
3287
3288                 case CMPL_BASE_TYPE_RX_TPA_END:
3289                         if (desc == offset)
3290                                 return RTE_ETH_RX_DESC_DONE;
3291
3292                         if (BNXT_CHIP_P5(rxq->bp)) {
3293                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3294
3295                                 p5_tpa_end = (void *)rxcmp;
3296                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3297                         } else {
3298                                 struct rx_tpa_end_cmpl *tpa_end;
3299
3300                                 tpa_end = (void *)rxcmp;
3301                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3302                         }
3303
3304                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3305                         desc++;
3306                         break;
3307
3308                 default:
3309                         raw_cons += CMP_LEN(cmpl_type);
3310                 }
3311         }
3312
3313         return RTE_ETH_RX_DESC_AVAIL;
3314 }
3315
3316 static int
3317 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3318 {
3319         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3320         struct bnxt_cp_ring_info *cpr = txq->cp_ring;
3321         uint32_t ring_mask, raw_cons, nb_tx_pkts = 0;
3322         struct cmpl_base *cp_desc_ring;
3323         int rc;
3324
3325         rc = is_bnxt_in_error(txq->bp);
3326         if (rc)
3327                 return rc;
3328
3329         if (offset >= txq->nb_tx_desc)
3330                 return -EINVAL;
3331
3332         /* Return "desc done" if descriptor is available for use. */
3333         if (bnxt_tx_bds_in_hw(txq) <= offset)
3334                 return RTE_ETH_TX_DESC_DONE;
3335
3336         raw_cons = cpr->cp_raw_cons;
3337         cp_desc_ring = cpr->cp_desc_ring;
3338         ring_mask = cpr->cp_ring_struct->ring_mask;
3339
3340         /* Check to see if hw has posted a completion for the descriptor. */
3341         while (1) {
3342                 struct tx_cmpl *txcmp;
3343                 uint32_t cons;
3344
3345                 cons = RING_CMPL(ring_mask, raw_cons);
3346                 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
3347
3348                 if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1))
3349                         break;
3350
3351                 if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2)
3352                         nb_tx_pkts += rte_le_to_cpu_32(txcmp->opaque);
3353
3354                 if (nb_tx_pkts > offset)
3355                         return RTE_ETH_TX_DESC_DONE;
3356
3357                 raw_cons = NEXT_RAW_CMP(raw_cons);
3358         }
3359
3360         /* Descriptor is pending transmit, not yet completed by hardware. */
3361         return RTE_ETH_TX_DESC_FULL;
3362 }
3363
3364 int
3365 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3366                      const struct rte_flow_ops **ops)
3367 {
3368         struct bnxt *bp = dev->data->dev_private;
3369         int ret = 0;
3370
3371         if (!bp)
3372                 return -EIO;
3373
3374         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3375                 struct bnxt_representor *vfr = dev->data->dev_private;
3376                 bp = vfr->parent_dev->data->dev_private;
3377                 /* parent is deleted while children are still valid */
3378                 if (!bp) {
3379                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3380                                     dev->data->port_id);
3381                         return -EIO;
3382                 }
3383         }
3384
3385         ret = is_bnxt_in_error(bp);
3386         if (ret)
3387                 return ret;
3388
3389         /* PMD supports thread-safe flow operations.  rte_flow API
3390          * functions can avoid mutex for multi-thread safety.
3391          */
3392         dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3393
3394         if (BNXT_TRUFLOW_EN(bp))
3395                 *ops = &bnxt_ulp_rte_flow_ops;
3396         else
3397                 *ops = &bnxt_flow_ops;
3398
3399         return ret;
3400 }
3401
3402 static const uint32_t *
3403 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3404 {
3405         static const uint32_t ptypes[] = {
3406                 RTE_PTYPE_L2_ETHER_VLAN,
3407                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3408                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3409                 RTE_PTYPE_L4_ICMP,
3410                 RTE_PTYPE_L4_TCP,
3411                 RTE_PTYPE_L4_UDP,
3412                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3413                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3414                 RTE_PTYPE_INNER_L4_ICMP,
3415                 RTE_PTYPE_INNER_L4_TCP,
3416                 RTE_PTYPE_INNER_L4_UDP,
3417                 RTE_PTYPE_UNKNOWN
3418         };
3419
3420         if (!dev->rx_pkt_burst)
3421                 return NULL;
3422
3423         return ptypes;
3424 }
3425
3426 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3427                          int reg_win)
3428 {
3429         uint32_t reg_base = *reg_arr & 0xfffff000;
3430         uint32_t win_off;
3431         int i;
3432
3433         for (i = 0; i < count; i++) {
3434                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3435                         return -ERANGE;
3436         }
3437         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3438         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3439         return 0;
3440 }
3441
3442 static int bnxt_map_ptp_regs(struct bnxt *bp)
3443 {
3444         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3445         uint32_t *reg_arr;
3446         int rc, i;
3447
3448         reg_arr = ptp->rx_regs;
3449         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3450         if (rc)
3451                 return rc;
3452
3453         reg_arr = ptp->tx_regs;
3454         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3455         if (rc)
3456                 return rc;
3457
3458         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3459                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3460
3461         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3462                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3463
3464         return 0;
3465 }
3466
3467 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3468 {
3469         rte_write32(0, (uint8_t *)bp->bar0 +
3470                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3471         rte_write32(0, (uint8_t *)bp->bar0 +
3472                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3473 }
3474
3475 static uint64_t bnxt_cc_read(struct bnxt *bp)
3476 {
3477         uint64_t ns;
3478
3479         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3480                               BNXT_GRCPF_REG_SYNC_TIME));
3481         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3482                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3483         return ns;
3484 }
3485
3486 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3487 {
3488         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3489         uint32_t fifo;
3490
3491         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3492                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3493         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3494                 return -EAGAIN;
3495
3496         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3497                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3498         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3499                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3500         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3501                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3502         rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3503
3504         return 0;
3505 }
3506
3507 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3508 {
3509         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3510         struct bnxt_pf_info *pf = bp->pf;
3511         uint16_t port_id;
3512         int i = 0;
3513         uint32_t fifo;
3514
3515         if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3516                 return -EINVAL;
3517
3518         port_id = pf->port_id;
3519         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3520                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3521         while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3522                 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3523                             ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3524                 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3525                                         ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3526                 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3527                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3528                 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3529                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3530                 i++;
3531         }
3532
3533         if (i >= BNXT_PTP_RX_PND_CNT)
3534                 return -EBUSY;
3535
3536         return 0;
3537 }
3538
3539 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3540 {
3541         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3542         struct bnxt_pf_info *pf = bp->pf;
3543         uint16_t port_id;
3544         uint32_t fifo;
3545
3546         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3547                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3548         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3549                 return -EAGAIN;
3550
3551         port_id = pf->port_id;
3552         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3553                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3554
3555         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3556                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3557         if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3558                 return bnxt_clr_rx_ts(bp, ts);
3559
3560         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3561                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3562         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3563                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3564
3565         return 0;
3566 }
3567
3568 static int
3569 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3570 {
3571         uint64_t ns;
3572         struct bnxt *bp = dev->data->dev_private;
3573         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3574
3575         if (!ptp)
3576                 return -ENOTSUP;
3577
3578         ns = rte_timespec_to_ns(ts);
3579         /* Set the timecounters to a new value. */
3580         ptp->tc.nsec = ns;
3581         ptp->tx_tstamp_tc.nsec = ns;
3582         ptp->rx_tstamp_tc.nsec = ns;
3583
3584         return 0;
3585 }
3586
3587 static int
3588 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3589 {
3590         struct bnxt *bp = dev->data->dev_private;
3591         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3592         uint64_t ns, systime_cycles = 0;
3593         int rc = 0;
3594
3595         if (!ptp)
3596                 return -ENOTSUP;
3597
3598         if (BNXT_CHIP_P5(bp))
3599                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3600                                              &systime_cycles);
3601         else
3602                 systime_cycles = bnxt_cc_read(bp);
3603
3604         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3605         *ts = rte_ns_to_timespec(ns);
3606
3607         return rc;
3608 }
3609 static int
3610 bnxt_timesync_enable(struct rte_eth_dev *dev)
3611 {
3612         struct bnxt *bp = dev->data->dev_private;
3613         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3614         uint32_t shift = 0;
3615         int rc;
3616
3617         if (!ptp)
3618                 return -ENOTSUP;
3619
3620         ptp->rx_filter = 1;
3621         ptp->tx_tstamp_en = 1;
3622         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3623
3624         rc = bnxt_hwrm_ptp_cfg(bp);
3625         if (rc)
3626                 return rc;
3627
3628         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3629         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3630         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3631
3632         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3633         ptp->tc.cc_shift = shift;
3634         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3635
3636         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3637         ptp->rx_tstamp_tc.cc_shift = shift;
3638         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3639
3640         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3641         ptp->tx_tstamp_tc.cc_shift = shift;
3642         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3643
3644         if (!BNXT_CHIP_P5(bp))
3645                 bnxt_map_ptp_regs(bp);
3646         else
3647                 rc = bnxt_ptp_start(bp);
3648
3649         return rc;
3650 }
3651
3652 static int
3653 bnxt_timesync_disable(struct rte_eth_dev *dev)
3654 {
3655         struct bnxt *bp = dev->data->dev_private;
3656         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3657
3658         if (!ptp)
3659                 return -ENOTSUP;
3660
3661         ptp->rx_filter = 0;
3662         ptp->tx_tstamp_en = 0;
3663         ptp->rxctl = 0;
3664
3665         bnxt_hwrm_ptp_cfg(bp);
3666
3667         if (!BNXT_CHIP_P5(bp))
3668                 bnxt_unmap_ptp_regs(bp);
3669         else
3670                 bnxt_ptp_stop(bp);
3671
3672         return 0;
3673 }
3674
3675 static int
3676 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3677                                  struct timespec *timestamp,
3678                                  uint32_t flags __rte_unused)
3679 {
3680         struct bnxt *bp = dev->data->dev_private;
3681         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3682         uint64_t rx_tstamp_cycles = 0;
3683         uint64_t ns;
3684
3685         if (!ptp)
3686                 return -ENOTSUP;
3687
3688         if (BNXT_CHIP_P5(bp))
3689                 rx_tstamp_cycles = ptp->rx_timestamp;
3690         else
3691                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3692
3693         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3694         *timestamp = rte_ns_to_timespec(ns);
3695         return  0;
3696 }
3697
3698 static int
3699 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3700                                  struct timespec *timestamp)
3701 {
3702         struct bnxt *bp = dev->data->dev_private;
3703         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3704         uint64_t tx_tstamp_cycles = 0;
3705         uint64_t ns;
3706         int rc = 0;
3707
3708         if (!ptp)
3709                 return -ENOTSUP;
3710
3711         if (BNXT_CHIP_P5(bp))
3712                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3713                                              &tx_tstamp_cycles);
3714         else
3715                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3716
3717         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3718         *timestamp = rte_ns_to_timespec(ns);
3719
3720         return rc;
3721 }
3722
3723 static int
3724 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3725 {
3726         struct bnxt *bp = dev->data->dev_private;
3727         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3728
3729         if (!ptp)
3730                 return -ENOTSUP;
3731
3732         ptp->tc.nsec += delta;
3733         ptp->tx_tstamp_tc.nsec += delta;
3734         ptp->rx_tstamp_tc.nsec += delta;
3735
3736         return 0;
3737 }
3738
3739 static int
3740 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3741 {
3742         struct bnxt *bp = dev->data->dev_private;
3743         int rc;
3744         uint32_t dir_entries;
3745         uint32_t entry_length;
3746
3747         rc = is_bnxt_in_error(bp);
3748         if (rc)
3749                 return rc;
3750
3751         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3752                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3753                     bp->pdev->addr.devid, bp->pdev->addr.function);
3754
3755         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3756         if (rc != 0)
3757                 return rc;
3758
3759         return dir_entries * entry_length;
3760 }
3761
3762 static int
3763 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3764                 struct rte_dev_eeprom_info *in_eeprom)
3765 {
3766         struct bnxt *bp = dev->data->dev_private;
3767         uint32_t index;
3768         uint32_t offset;
3769         int rc;
3770
3771         rc = is_bnxt_in_error(bp);
3772         if (rc)
3773                 return rc;
3774
3775         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3776                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3777                     bp->pdev->addr.devid, bp->pdev->addr.function,
3778                     in_eeprom->offset, in_eeprom->length);
3779
3780         if (in_eeprom->offset == 0) /* special offset value to get directory */
3781                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3782                                                 in_eeprom->data);
3783
3784         index = in_eeprom->offset >> 24;
3785         offset = in_eeprom->offset & 0xffffff;
3786
3787         if (index != 0)
3788                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3789                                            in_eeprom->length, in_eeprom->data);
3790
3791         return 0;
3792 }
3793
3794 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3795 {
3796         switch (dir_type) {
3797         case BNX_DIR_TYPE_CHIMP_PATCH:
3798         case BNX_DIR_TYPE_BOOTCODE:
3799         case BNX_DIR_TYPE_BOOTCODE_2:
3800         case BNX_DIR_TYPE_APE_FW:
3801         case BNX_DIR_TYPE_APE_PATCH:
3802         case BNX_DIR_TYPE_KONG_FW:
3803         case BNX_DIR_TYPE_KONG_PATCH:
3804         case BNX_DIR_TYPE_BONO_FW:
3805         case BNX_DIR_TYPE_BONO_PATCH:
3806                 /* FALLTHROUGH */
3807                 return true;
3808         }
3809
3810         return false;
3811 }
3812
3813 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3814 {
3815         switch (dir_type) {
3816         case BNX_DIR_TYPE_AVS:
3817         case BNX_DIR_TYPE_EXP_ROM_MBA:
3818         case BNX_DIR_TYPE_PCIE:
3819         case BNX_DIR_TYPE_TSCF_UCODE:
3820         case BNX_DIR_TYPE_EXT_PHY:
3821         case BNX_DIR_TYPE_CCM:
3822         case BNX_DIR_TYPE_ISCSI_BOOT:
3823         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3824         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3825                 /* FALLTHROUGH */
3826                 return true;
3827         }
3828
3829         return false;
3830 }
3831
3832 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3833 {
3834         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3835                 bnxt_dir_type_is_other_exec_format(dir_type);
3836 }
3837
3838 static int
3839 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3840                 struct rte_dev_eeprom_info *in_eeprom)
3841 {
3842         struct bnxt *bp = dev->data->dev_private;
3843         uint8_t index, dir_op;
3844         uint16_t type, ext, ordinal, attr;
3845         int rc;
3846
3847         rc = is_bnxt_in_error(bp);
3848         if (rc)
3849                 return rc;
3850
3851         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3852                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3853                     bp->pdev->addr.devid, bp->pdev->addr.function,
3854                     in_eeprom->offset, in_eeprom->length);
3855
3856         if (!BNXT_PF(bp)) {
3857                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3858                 return -EINVAL;
3859         }
3860
3861         type = in_eeprom->magic >> 16;
3862
3863         if (type == 0xffff) { /* special value for directory operations */
3864                 index = in_eeprom->magic & 0xff;
3865                 dir_op = in_eeprom->magic >> 8;
3866                 if (index == 0)
3867                         return -EINVAL;
3868                 switch (dir_op) {
3869                 case 0x0e: /* erase */
3870                         if (in_eeprom->offset != ~in_eeprom->magic)
3871                                 return -EINVAL;
3872                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3873                 default:
3874                         return -EINVAL;
3875                 }
3876         }
3877
3878         /* Create or re-write an NVM item: */
3879         if (bnxt_dir_type_is_executable(type) == true)
3880                 return -EOPNOTSUPP;
3881         ext = in_eeprom->magic & 0xffff;
3882         ordinal = in_eeprom->offset >> 16;
3883         attr = in_eeprom->offset & 0xffff;
3884
3885         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3886                                      in_eeprom->data, in_eeprom->length);
3887 }
3888
3889 static int bnxt_get_module_info(struct rte_eth_dev *dev,
3890                                 struct rte_eth_dev_module_info *modinfo)
3891 {
3892         uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3893         struct bnxt *bp = dev->data->dev_private;
3894         int rc;
3895
3896         /* No point in going further if phy status indicates
3897          * module is not inserted or if it is powered down or
3898          * if it is of type 10GBase-T
3899          */
3900         if (bp->link_info->module_status >
3901             HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) {
3902                 PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n",
3903                             dev->data->port_id);
3904                 return -ENOTSUP;
3905         }
3906
3907         /* This feature is not supported in older firmware versions */
3908         if (bp->hwrm_spec_code < 0x10202) {
3909                 PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n",
3910                             dev->data->port_id);
3911                 return -ENOTSUP;
3912         }
3913
3914         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3915                                                    SFF_DIAG_SUPPORT_OFFSET + 1,
3916                                                    module_info);
3917
3918         if (rc)
3919                 return rc;
3920
3921         switch (module_info[0]) {
3922         case SFF_MODULE_ID_SFP:
3923                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
3924                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
3925                 if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0)
3926                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3927                 break;
3928         case SFF_MODULE_ID_QSFP:
3929         case SFF_MODULE_ID_QSFP_PLUS:
3930                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
3931                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3932                 break;
3933         case SFF_MODULE_ID_QSFP28:
3934                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
3935                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
3936                 if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK)
3937                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN;
3938                 break;
3939         default:
3940                 PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id);
3941                 return -ENOTSUP;
3942         }
3943
3944         PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n",
3945                     dev->data->port_id, modinfo->type, modinfo->eeprom_len);
3946
3947         return 0;
3948 }
3949
3950 static int bnxt_get_module_eeprom(struct rte_eth_dev *dev,
3951                                   struct rte_dev_eeprom_info *info)
3952 {
3953         uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 };
3954         uint32_t offset = info->offset, length = info->length;
3955         uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3956         struct bnxt *bp = dev->data->dev_private;
3957         uint8_t *data = info->data;
3958         uint8_t page = offset >> 7;
3959         uint8_t max_pages = 2;
3960         uint8_t opt_pages;
3961         int rc;
3962
3963         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3964                                                    SFF_DIAG_SUPPORT_OFFSET + 1,
3965                                                    module_info);
3966         if (rc)
3967                 return rc;
3968
3969         switch (module_info[0]) {
3970         case SFF_MODULE_ID_SFP:
3971                 module_info[SFF_DIAG_SUPPORT_OFFSET] = 0;
3972                 if (module_info[SFF_DIAG_SUPPORT_OFFSET]) {
3973                         pg_addr[2] = I2C_DEV_ADDR_A2;
3974                         pg_addr[3] = I2C_DEV_ADDR_A2;
3975                         max_pages = 4;
3976                 }
3977                 break;
3978         case SFF_MODULE_ID_QSFP28:
3979                 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
3980                                                            SFF8636_OPT_PAGES_OFFSET,
3981                                                            1, &opt_pages);
3982                 if (rc)
3983                         return rc;
3984
3985                 if (opt_pages & SFF8636_PAGE1_MASK) {
3986                         pg_addr[2] = I2C_DEV_ADDR_A0;
3987                         max_pages = 3;
3988                 }
3989                 if (opt_pages & SFF8636_PAGE2_MASK) {
3990                         pg_addr[3] = I2C_DEV_ADDR_A0;
3991                         max_pages = 4;
3992                 }
3993                 if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) {
3994                         pg_addr[4] = I2C_DEV_ADDR_A0;
3995                         max_pages = 5;
3996                 }
3997                 break;
3998         default:
3999                 break;
4000         }
4001
4002         memset(data, 0, length);
4003
4004         offset &= 0xff;
4005         while (length && page < max_pages) {
4006                 uint8_t raw_page = page ? page - 1 : 0;
4007                 uint16_t chunk;
4008
4009                 if (pg_addr[page] == I2C_DEV_ADDR_A2)
4010                         raw_page = 0;
4011                 else if (page)
4012                         offset |= 0x80;
4013                 chunk = RTE_MIN(length, 256 - offset);
4014
4015                 if (pg_addr[page]) {
4016                         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page],
4017                                                                    raw_page, offset,
4018                                                                    chunk, data);
4019                         if (rc)
4020                                 return rc;
4021                 }
4022
4023                 data += chunk;
4024                 length -= chunk;
4025                 offset = 0;
4026                 page += 1 + (chunk > 128);
4027         }
4028
4029         return length ? -EINVAL : 0;
4030 }
4031
4032 /*
4033  * Initialization
4034  */
4035
4036 static const struct eth_dev_ops bnxt_dev_ops = {
4037         .dev_infos_get = bnxt_dev_info_get_op,
4038         .dev_close = bnxt_dev_close_op,
4039         .dev_configure = bnxt_dev_configure_op,
4040         .dev_start = bnxt_dev_start_op,
4041         .dev_stop = bnxt_dev_stop_op,
4042         .dev_set_link_up = bnxt_dev_set_link_up_op,
4043         .dev_set_link_down = bnxt_dev_set_link_down_op,
4044         .stats_get = bnxt_stats_get_op,
4045         .stats_reset = bnxt_stats_reset_op,
4046         .rx_queue_setup = bnxt_rx_queue_setup_op,
4047         .rx_queue_release = bnxt_rx_queue_release_op,
4048         .tx_queue_setup = bnxt_tx_queue_setup_op,
4049         .tx_queue_release = bnxt_tx_queue_release_op,
4050         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4051         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4052         .reta_update = bnxt_reta_update_op,
4053         .reta_query = bnxt_reta_query_op,
4054         .rss_hash_update = bnxt_rss_hash_update_op,
4055         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4056         .link_update = bnxt_link_update_op,
4057         .promiscuous_enable = bnxt_promiscuous_enable_op,
4058         .promiscuous_disable = bnxt_promiscuous_disable_op,
4059         .allmulticast_enable = bnxt_allmulticast_enable_op,
4060         .allmulticast_disable = bnxt_allmulticast_disable_op,
4061         .mac_addr_add = bnxt_mac_addr_add_op,
4062         .mac_addr_remove = bnxt_mac_addr_remove_op,
4063         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4064         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4065         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4066         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4067         .vlan_filter_set = bnxt_vlan_filter_set_op,
4068         .vlan_offload_set = bnxt_vlan_offload_set_op,
4069         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4070         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4071         .mtu_set = bnxt_mtu_set_op,
4072         .mac_addr_set = bnxt_set_default_mac_addr_op,
4073         .xstats_get = bnxt_dev_xstats_get_op,
4074         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4075         .xstats_reset = bnxt_dev_xstats_reset_op,
4076         .fw_version_get = bnxt_fw_version_get,
4077         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4078         .rxq_info_get = bnxt_rxq_info_get_op,
4079         .txq_info_get = bnxt_txq_info_get_op,
4080         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4081         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4082         .dev_led_on = bnxt_dev_led_on_op,
4083         .dev_led_off = bnxt_dev_led_off_op,
4084         .rx_queue_start = bnxt_rx_queue_start,
4085         .rx_queue_stop = bnxt_rx_queue_stop,
4086         .tx_queue_start = bnxt_tx_queue_start,
4087         .tx_queue_stop = bnxt_tx_queue_stop,
4088         .flow_ops_get = bnxt_flow_ops_get_op,
4089         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4090         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4091         .get_eeprom           = bnxt_get_eeprom_op,
4092         .set_eeprom           = bnxt_set_eeprom_op,
4093         .get_module_info = bnxt_get_module_info,
4094         .get_module_eeprom = bnxt_get_module_eeprom,
4095         .timesync_enable      = bnxt_timesync_enable,
4096         .timesync_disable     = bnxt_timesync_disable,
4097         .timesync_read_time   = bnxt_timesync_read_time,
4098         .timesync_write_time   = bnxt_timesync_write_time,
4099         .timesync_adjust_time = bnxt_timesync_adjust_time,
4100         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4101         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4102 };
4103
4104 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4105 {
4106         uint32_t offset;
4107
4108         /* Only pre-map the reset GRC registers using window 3 */
4109         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4110                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4111
4112         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4113
4114         return offset;
4115 }
4116
4117 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4118 {
4119         struct bnxt_error_recovery_info *info = bp->recovery_info;
4120         uint32_t reg_base = 0xffffffff;
4121         int i;
4122
4123         /* Only pre-map the monitoring GRC registers using window 2 */
4124         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4125                 uint32_t reg = info->status_regs[i];
4126
4127                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4128                         continue;
4129
4130                 if (reg_base == 0xffffffff)
4131                         reg_base = reg & 0xfffff000;
4132                 if ((reg & 0xfffff000) != reg_base)
4133                         return -ERANGE;
4134
4135                 /* Use mask 0xffc as the Lower 2 bits indicates
4136                  * address space location
4137                  */
4138                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4139                                                 (reg & 0xffc);
4140         }
4141
4142         if (reg_base == 0xffffffff)
4143                 return 0;
4144
4145         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4146                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4147
4148         return 0;
4149 }
4150
4151 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4152 {
4153         struct bnxt_error_recovery_info *info = bp->recovery_info;
4154         uint32_t delay = info->delay_after_reset[index];
4155         uint32_t val = info->reset_reg_val[index];
4156         uint32_t reg = info->reset_reg[index];
4157         uint32_t type, offset;
4158         int ret;
4159
4160         type = BNXT_FW_STATUS_REG_TYPE(reg);
4161         offset = BNXT_FW_STATUS_REG_OFF(reg);
4162
4163         switch (type) {
4164         case BNXT_FW_STATUS_REG_TYPE_CFG:
4165                 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4166                 if (ret < 0) {
4167                         PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
4168                                     val, offset);
4169                         return;
4170                 }
4171                 break;
4172         case BNXT_FW_STATUS_REG_TYPE_GRC:
4173                 offset = bnxt_map_reset_regs(bp, offset);
4174                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4175                 break;
4176         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4177                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4178                 break;
4179         }
4180         /* wait on a specific interval of time until core reset is complete */
4181         if (delay)
4182                 rte_delay_ms(delay);
4183 }
4184
4185 static void bnxt_dev_cleanup(struct bnxt *bp)
4186 {
4187         bp->eth_dev->data->dev_link.link_status = 0;
4188         bp->link_info->link_up = 0;
4189         if (bp->eth_dev->data->dev_started)
4190                 bnxt_dev_stop(bp->eth_dev);
4191
4192         bnxt_uninit_resources(bp, true);
4193 }
4194
4195 static int
4196 bnxt_check_fw_reset_done(struct bnxt *bp)
4197 {
4198         int timeout = bp->fw_reset_max_msecs;
4199         uint16_t val = 0;
4200         int rc;
4201
4202         do {
4203                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4204                 if (rc < 0) {
4205                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4206                         return rc;
4207                 }
4208                 if (val != 0xffff)
4209                         break;
4210                 rte_delay_ms(1);
4211         } while (timeout--);
4212
4213         if (val == 0xffff) {
4214                 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4215                 return -1;
4216         }
4217
4218         return 0;
4219 }
4220
4221 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4222 {
4223         struct rte_eth_dev *dev = bp->eth_dev;
4224         struct rte_vlan_filter_conf *vfc;
4225         int vidx, vbit, rc;
4226         uint16_t vlan_id;
4227
4228         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4229                 vfc = &dev->data->vlan_filter_conf;
4230                 vidx = vlan_id / 64;
4231                 vbit = vlan_id % 64;
4232
4233                 /* Each bit corresponds to a VLAN id */
4234                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4235                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4236                         if (rc)
4237                                 return rc;
4238                 }
4239         }
4240
4241         return 0;
4242 }
4243
4244 static int bnxt_restore_mac_filters(struct bnxt *bp)
4245 {
4246         struct rte_eth_dev *dev = bp->eth_dev;
4247         struct rte_eth_dev_info dev_info;
4248         struct rte_ether_addr *addr;
4249         uint64_t pool_mask;
4250         uint32_t pool = 0;
4251         uint32_t i;
4252         int rc;
4253
4254         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4255                 return 0;
4256
4257         rc = bnxt_dev_info_get_op(dev, &dev_info);
4258         if (rc)
4259                 return rc;
4260
4261         /* replay MAC address configuration */
4262         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4263                 addr = &dev->data->mac_addrs[i];
4264
4265                 /* skip zero address */
4266                 if (rte_is_zero_ether_addr(addr))
4267                         continue;
4268
4269                 pool = 0;
4270                 pool_mask = dev->data->mac_pool_sel[i];
4271
4272                 do {
4273                         if (pool_mask & 1ULL) {
4274                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4275                                 if (rc)
4276                                         return rc;
4277                         }
4278                         pool_mask >>= 1;
4279                         pool++;
4280                 } while (pool_mask);
4281         }
4282
4283         return 0;
4284 }
4285
4286 static int bnxt_restore_filters(struct bnxt *bp)
4287 {
4288         struct rte_eth_dev *dev = bp->eth_dev;
4289         int ret = 0;
4290
4291         if (dev->data->all_multicast) {
4292                 ret = bnxt_allmulticast_enable_op(dev);
4293                 if (ret)
4294                         return ret;
4295         }
4296         if (dev->data->promiscuous) {
4297                 ret = bnxt_promiscuous_enable_op(dev);
4298                 if (ret)
4299                         return ret;
4300         }
4301
4302         ret = bnxt_restore_mac_filters(bp);
4303         if (ret)
4304                 return ret;
4305
4306         ret = bnxt_restore_vlan_filters(bp);
4307         /* TODO restore other filters as well */
4308         return ret;
4309 }
4310
4311 static int bnxt_check_fw_ready(struct bnxt *bp)
4312 {
4313         int timeout = bp->fw_reset_max_msecs;
4314         int rc = 0;
4315
4316         do {
4317                 rc = bnxt_hwrm_poll_ver_get(bp);
4318                 if (rc == 0)
4319                         break;
4320                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4321                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4322         } while (rc && timeout > 0);
4323
4324         if (rc)
4325                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4326
4327         return rc;
4328 }
4329
4330 static void bnxt_dev_recover(void *arg)
4331 {
4332         struct bnxt *bp = arg;
4333         int rc = 0;
4334
4335         pthread_mutex_lock(&bp->err_recovery_lock);
4336
4337         if (!bp->fw_reset_min_msecs) {
4338                 rc = bnxt_check_fw_reset_done(bp);
4339                 if (rc)
4340                         goto err;
4341         }
4342
4343         /* Clear Error flag so that device re-init should happen */
4344         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4345
4346         rc = bnxt_check_fw_ready(bp);
4347         if (rc)
4348                 goto err;
4349
4350         rc = bnxt_init_resources(bp, true);
4351         if (rc) {
4352                 PMD_DRV_LOG(ERR,
4353                             "Failed to initialize resources after reset\n");
4354                 goto err;
4355         }
4356         /* clear reset flag as the device is initialized now */
4357         bp->flags &= ~BNXT_FLAG_FW_RESET;
4358
4359         rc = bnxt_dev_start_op(bp->eth_dev);
4360         if (rc) {
4361                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4362                 goto err_start;
4363         }
4364
4365         rc = bnxt_restore_filters(bp);
4366         if (rc)
4367                 goto err_start;
4368
4369         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4370         pthread_mutex_unlock(&bp->err_recovery_lock);
4371
4372         return;
4373 err_start:
4374         bnxt_dev_stop(bp->eth_dev);
4375 err:
4376         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4377         bnxt_uninit_resources(bp, false);
4378         if (bp->eth_dev->data->dev_conf.intr_conf.rmv)
4379                 rte_eth_dev_callback_process(bp->eth_dev,
4380                                              RTE_ETH_EVENT_INTR_RMV,
4381                                              NULL);
4382         pthread_mutex_unlock(&bp->err_recovery_lock);
4383         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4384 }
4385
4386 void bnxt_dev_reset_and_resume(void *arg)
4387 {
4388         struct bnxt *bp = arg;
4389         uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4390         uint16_t val = 0;
4391         int rc;
4392
4393         bnxt_dev_cleanup(bp);
4394
4395         bnxt_wait_for_device_shutdown(bp);
4396
4397         /* During some fatal firmware error conditions, the PCI config space
4398          * register 0x2e which normally contains the subsystem ID will become
4399          * 0xffff. This register will revert back to the normal value after
4400          * the chip has completed core reset. If we detect this condition,
4401          * we can poll this config register immediately for the value to revert.
4402          */
4403         if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4404                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4405                 if (rc < 0) {
4406                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4407                         return;
4408                 }
4409                 if (val == 0xffff) {
4410                         bp->fw_reset_min_msecs = 0;
4411                         us = 1;
4412                 }
4413         }
4414
4415         rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4416         if (rc)
4417                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4418 }
4419
4420 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4421 {
4422         struct bnxt_error_recovery_info *info = bp->recovery_info;
4423         uint32_t reg = info->status_regs[index];
4424         uint32_t type, offset, val = 0;
4425         int ret = 0;
4426
4427         type = BNXT_FW_STATUS_REG_TYPE(reg);
4428         offset = BNXT_FW_STATUS_REG_OFF(reg);
4429
4430         switch (type) {
4431         case BNXT_FW_STATUS_REG_TYPE_CFG:
4432                 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4433                 if (ret < 0)
4434                         PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4435                                     offset);
4436                 break;
4437         case BNXT_FW_STATUS_REG_TYPE_GRC:
4438                 offset = info->mapped_status_regs[index];
4439                 /* FALLTHROUGH */
4440         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4441                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4442                                        offset));
4443                 break;
4444         }
4445
4446         return val;
4447 }
4448
4449 static int bnxt_fw_reset_all(struct bnxt *bp)
4450 {
4451         struct bnxt_error_recovery_info *info = bp->recovery_info;
4452         uint32_t i;
4453         int rc = 0;
4454
4455         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4456                 /* Reset through primary function driver */
4457                 for (i = 0; i < info->reg_array_cnt; i++)
4458                         bnxt_write_fw_reset_reg(bp, i);
4459                 /* Wait for time specified by FW after triggering reset */
4460                 rte_delay_ms(info->primary_func_wait_period_after_reset);
4461         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4462                 /* Reset with the help of Kong processor */
4463                 rc = bnxt_hwrm_fw_reset(bp);
4464                 if (rc)
4465                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4466         }
4467
4468         return rc;
4469 }
4470
4471 static void bnxt_fw_reset_cb(void *arg)
4472 {
4473         struct bnxt *bp = arg;
4474         struct bnxt_error_recovery_info *info = bp->recovery_info;
4475         int rc = 0;
4476
4477         /* Only Primary function can do FW reset */
4478         if (bnxt_is_primary_func(bp) &&
4479             bnxt_is_recovery_enabled(bp)) {
4480                 rc = bnxt_fw_reset_all(bp);
4481                 if (rc) {
4482                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4483                         return;
4484                 }
4485         }
4486
4487         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4488          * EXCEPTION_FATAL_ASYNC event to all the functions
4489          * (including MASTER FUNC). After receiving this Async, all the active
4490          * drivers should treat this case as FW initiated recovery
4491          */
4492         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4493                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4494                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4495
4496                 /* To recover from error */
4497                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4498                                   (void *)bp);
4499         }
4500 }
4501
4502 /* Driver should poll FW heartbeat, reset_counter with the frequency
4503  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4504  * When the driver detects heartbeat stop or change in reset_counter,
4505  * it has to trigger a reset to recover from the error condition.
4506  * A “primary function” is the function who will have the privilege to
4507  * initiate the chimp reset. The primary function will be elected by the
4508  * firmware and will be notified through async message.
4509  */
4510 static void bnxt_check_fw_health(void *arg)
4511 {
4512         struct bnxt *bp = arg;
4513         struct bnxt_error_recovery_info *info = bp->recovery_info;
4514         uint32_t val = 0, wait_msec;
4515
4516         if (!info || !bnxt_is_recovery_enabled(bp) ||
4517             is_bnxt_in_error(bp))
4518                 return;
4519
4520         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4521         if (val == info->last_heart_beat)
4522                 goto reset;
4523
4524         info->last_heart_beat = val;
4525
4526         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4527         if (val != info->last_reset_counter)
4528                 goto reset;
4529
4530         info->last_reset_counter = val;
4531
4532         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4533                           bnxt_check_fw_health, (void *)bp);
4534
4535         return;
4536 reset:
4537         /* Stop DMA to/from device */
4538         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4539         bp->flags |= BNXT_FLAG_FW_RESET;
4540
4541         bnxt_stop_rxtx(bp);
4542
4543         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4544
4545         if (bnxt_is_primary_func(bp))
4546                 wait_msec = info->primary_func_wait_period;
4547         else
4548                 wait_msec = info->normal_func_wait_period;
4549
4550         rte_eal_alarm_set(US_PER_MS * wait_msec,
4551                           bnxt_fw_reset_cb, (void *)bp);
4552 }
4553
4554 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4555 {
4556         uint32_t polling_freq;
4557
4558         pthread_mutex_lock(&bp->health_check_lock);
4559
4560         if (!bnxt_is_recovery_enabled(bp))
4561                 goto done;
4562
4563         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4564                 goto done;
4565
4566         polling_freq = bp->recovery_info->driver_polling_freq;
4567
4568         rte_eal_alarm_set(US_PER_MS * polling_freq,
4569                           bnxt_check_fw_health, (void *)bp);
4570         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4571
4572 done:
4573         pthread_mutex_unlock(&bp->health_check_lock);
4574 }
4575
4576 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4577 {
4578         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4579         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4580 }
4581
4582 static bool bnxt_vf_pciid(uint16_t device_id)
4583 {
4584         switch (device_id) {
4585         case BROADCOM_DEV_ID_57304_VF:
4586         case BROADCOM_DEV_ID_57406_VF:
4587         case BROADCOM_DEV_ID_5731X_VF:
4588         case BROADCOM_DEV_ID_5741X_VF:
4589         case BROADCOM_DEV_ID_57414_VF:
4590         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4591         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4592         case BROADCOM_DEV_ID_58802_VF:
4593         case BROADCOM_DEV_ID_57500_VF1:
4594         case BROADCOM_DEV_ID_57500_VF2:
4595         case BROADCOM_DEV_ID_58818_VF:
4596                 /* FALLTHROUGH */
4597                 return true;
4598         default:
4599                 return false;
4600         }
4601 }
4602
4603 /* Phase 5 device */
4604 static bool bnxt_p5_device(uint16_t device_id)
4605 {
4606         switch (device_id) {
4607         case BROADCOM_DEV_ID_57508:
4608         case BROADCOM_DEV_ID_57504:
4609         case BROADCOM_DEV_ID_57502:
4610         case BROADCOM_DEV_ID_57508_MF1:
4611         case BROADCOM_DEV_ID_57504_MF1:
4612         case BROADCOM_DEV_ID_57502_MF1:
4613         case BROADCOM_DEV_ID_57508_MF2:
4614         case BROADCOM_DEV_ID_57504_MF2:
4615         case BROADCOM_DEV_ID_57502_MF2:
4616         case BROADCOM_DEV_ID_57500_VF1:
4617         case BROADCOM_DEV_ID_57500_VF2:
4618         case BROADCOM_DEV_ID_58812:
4619         case BROADCOM_DEV_ID_58814:
4620         case BROADCOM_DEV_ID_58818:
4621         case BROADCOM_DEV_ID_58818_VF:
4622                 /* FALLTHROUGH */
4623                 return true;
4624         default:
4625                 return false;
4626         }
4627 }
4628
4629 bool bnxt_stratus_device(struct bnxt *bp)
4630 {
4631         uint16_t device_id = bp->pdev->id.device_id;
4632
4633         switch (device_id) {
4634         case BROADCOM_DEV_ID_STRATUS_NIC:
4635         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4636         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4637                 /* FALLTHROUGH */
4638                 return true;
4639         default:
4640                 return false;
4641         }
4642 }
4643
4644 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4645 {
4646         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4647         struct bnxt *bp = eth_dev->data->dev_private;
4648
4649         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4650         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4651         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4652         if (!bp->bar0 || !bp->doorbell_base) {
4653                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4654                 return -ENODEV;
4655         }
4656
4657         bp->eth_dev = eth_dev;
4658         bp->pdev = pci_dev;
4659
4660         return 0;
4661 }
4662
4663 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4664                                   struct bnxt_ctx_pg_info *ctx_pg,
4665                                   uint32_t mem_size,
4666                                   const char *suffix,
4667                                   uint16_t idx)
4668 {
4669         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4670         const struct rte_memzone *mz = NULL;
4671         char mz_name[RTE_MEMZONE_NAMESIZE];
4672         rte_iova_t mz_phys_addr;
4673         uint64_t valid_bits = 0;
4674         uint32_t sz;
4675         int i;
4676
4677         if (!mem_size)
4678                 return 0;
4679
4680         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4681                          BNXT_PAGE_SIZE;
4682         rmem->page_size = BNXT_PAGE_SIZE;
4683         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4684         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4685         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4686
4687         valid_bits = PTU_PTE_VALID;
4688
4689         if (rmem->nr_pages > 1) {
4690                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4691                          "bnxt_ctx_pg_tbl%s_%x_%d",
4692                          suffix, idx, bp->eth_dev->data->port_id);
4693                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4694                 mz = rte_memzone_lookup(mz_name);
4695                 if (!mz) {
4696                         mz = rte_memzone_reserve_aligned(mz_name,
4697                                                 rmem->nr_pages * 8,
4698                                                 bp->eth_dev->device->numa_node,
4699                                                 RTE_MEMZONE_2MB |
4700                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4701                                                 RTE_MEMZONE_IOVA_CONTIG,
4702                                                 BNXT_PAGE_SIZE);
4703                         if (mz == NULL)
4704                                 return -ENOMEM;
4705                 }
4706
4707                 memset(mz->addr, 0, mz->len);
4708                 mz_phys_addr = mz->iova;
4709
4710                 rmem->pg_tbl = mz->addr;
4711                 rmem->pg_tbl_map = mz_phys_addr;
4712                 rmem->pg_tbl_mz = mz;
4713         }
4714
4715         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4716                  suffix, idx, bp->eth_dev->data->port_id);
4717         mz = rte_memzone_lookup(mz_name);
4718         if (!mz) {
4719                 mz = rte_memzone_reserve_aligned(mz_name,
4720                                                  mem_size,
4721                                                  bp->eth_dev->device->numa_node,
4722                                                  RTE_MEMZONE_1GB |
4723                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4724                                                  RTE_MEMZONE_IOVA_CONTIG,
4725                                                  BNXT_PAGE_SIZE);
4726                 if (mz == NULL)
4727                         return -ENOMEM;
4728         }
4729
4730         memset(mz->addr, 0, mz->len);
4731         mz_phys_addr = mz->iova;
4732
4733         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4734                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4735                 rmem->dma_arr[i] = mz_phys_addr + sz;
4736
4737                 if (rmem->nr_pages > 1) {
4738                         if (i == rmem->nr_pages - 2 &&
4739                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4740                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4741                         else if (i == rmem->nr_pages - 1 &&
4742                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4743                                 valid_bits |= PTU_PTE_LAST;
4744
4745                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4746                                                            valid_bits);
4747                 }
4748         }
4749
4750         rmem->mz = mz;
4751         if (rmem->vmem_size)
4752                 rmem->vmem = (void **)mz->addr;
4753         rmem->dma_arr[0] = mz_phys_addr;
4754         return 0;
4755 }
4756
4757 static void bnxt_free_ctx_mem(struct bnxt *bp)
4758 {
4759         int i;
4760
4761         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4762                 return;
4763
4764         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4765         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4766         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4767         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4768         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4769         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4770         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4771         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4772         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4773         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4774         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4775
4776         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4777                 if (bp->ctx->tqm_mem[i])
4778                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4779         }
4780
4781         rte_free(bp->ctx);
4782         bp->ctx = NULL;
4783 }
4784
4785 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4786
4787 #define min_t(type, x, y) ({                    \
4788         type __min1 = (x);                      \
4789         type __min2 = (y);                      \
4790         __min1 < __min2 ? __min1 : __min2; })
4791
4792 #define max_t(type, x, y) ({                    \
4793         type __max1 = (x);                      \
4794         type __max2 = (y);                      \
4795         __max1 > __max2 ? __max1 : __max2; })
4796
4797 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4798
4799 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4800 {
4801         struct bnxt_ctx_pg_info *ctx_pg;
4802         struct bnxt_ctx_mem_info *ctx;
4803         uint32_t mem_size, ena, entries;
4804         uint32_t entries_sp, min;
4805         int i, rc;
4806
4807         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4808         if (rc) {
4809                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4810                 return rc;
4811         }
4812         ctx = bp->ctx;
4813         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4814                 return 0;
4815
4816         ctx_pg = &ctx->qp_mem;
4817         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4818         if (ctx->qp_entry_size) {
4819                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4820                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4821                 if (rc)
4822                         return rc;
4823         }
4824
4825         ctx_pg = &ctx->srq_mem;
4826         ctx_pg->entries = ctx->srq_max_l2_entries;
4827         if (ctx->srq_entry_size) {
4828                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4829                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4830                 if (rc)
4831                         return rc;
4832         }
4833
4834         ctx_pg = &ctx->cq_mem;
4835         ctx_pg->entries = ctx->cq_max_l2_entries;
4836         if (ctx->cq_entry_size) {
4837                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4838                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4839                 if (rc)
4840                         return rc;
4841         }
4842
4843         ctx_pg = &ctx->vnic_mem;
4844         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4845                 ctx->vnic_max_ring_table_entries;
4846         if (ctx->vnic_entry_size) {
4847                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4848                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4849                 if (rc)
4850                         return rc;
4851         }
4852
4853         ctx_pg = &ctx->stat_mem;
4854         ctx_pg->entries = ctx->stat_max_entries;
4855         if (ctx->stat_entry_size) {
4856                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4857                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4858                 if (rc)
4859                         return rc;
4860         }
4861
4862         min = ctx->tqm_min_entries_per_ring;
4863
4864         entries_sp = ctx->qp_max_l2_entries +
4865                      ctx->vnic_max_vnic_entries +
4866                      2 * ctx->qp_min_qp1_entries + min;
4867         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4868
4869         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4870         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4871         entries = clamp_t(uint32_t, entries, min,
4872                           ctx->tqm_max_entries_per_ring);
4873         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4874                 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4875                  * i > 8 is other ext rings.
4876                  */
4877                 ctx_pg = ctx->tqm_mem[i];
4878                 ctx_pg->entries = i ? entries : entries_sp;
4879                 if (ctx->tqm_entry_size) {
4880                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4881                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4882                                                     "tqm_mem", i);
4883                         if (rc)
4884                                 return rc;
4885                 }
4886                 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4887                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4888                 else
4889                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4890         }
4891
4892         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4893         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4894         if (rc)
4895                 PMD_DRV_LOG(ERR,
4896                             "Failed to configure context mem: rc = %d\n", rc);
4897         else
4898                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4899
4900         return rc;
4901 }
4902
4903 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4904 {
4905         struct rte_pci_device *pci_dev = bp->pdev;
4906         char mz_name[RTE_MEMZONE_NAMESIZE];
4907         const struct rte_memzone *mz = NULL;
4908         uint32_t total_alloc_len;
4909         rte_iova_t mz_phys_addr;
4910
4911         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4912                 return 0;
4913
4914         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4915                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4916                  pci_dev->addr.bus, pci_dev->addr.devid,
4917                  pci_dev->addr.function, "rx_port_stats");
4918         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4919         mz = rte_memzone_lookup(mz_name);
4920         total_alloc_len =
4921                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4922                                        sizeof(struct rx_port_stats_ext) + 512);
4923         if (!mz) {
4924                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4925                                          SOCKET_ID_ANY,
4926                                          RTE_MEMZONE_2MB |
4927                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4928                                          RTE_MEMZONE_IOVA_CONTIG);
4929                 if (mz == NULL)
4930                         return -ENOMEM;
4931         }
4932         memset(mz->addr, 0, mz->len);
4933         mz_phys_addr = mz->iova;
4934
4935         bp->rx_mem_zone = (const void *)mz;
4936         bp->hw_rx_port_stats = mz->addr;
4937         bp->hw_rx_port_stats_map = mz_phys_addr;
4938
4939         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4940                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4941                  pci_dev->addr.bus, pci_dev->addr.devid,
4942                  pci_dev->addr.function, "tx_port_stats");
4943         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4944         mz = rte_memzone_lookup(mz_name);
4945         total_alloc_len =
4946                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4947                                        sizeof(struct tx_port_stats_ext) + 512);
4948         if (!mz) {
4949                 mz = rte_memzone_reserve(mz_name,
4950                                          total_alloc_len,
4951                                          SOCKET_ID_ANY,
4952                                          RTE_MEMZONE_2MB |
4953                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4954                                          RTE_MEMZONE_IOVA_CONTIG);
4955                 if (mz == NULL)
4956                         return -ENOMEM;
4957         }
4958         memset(mz->addr, 0, mz->len);
4959         mz_phys_addr = mz->iova;
4960
4961         bp->tx_mem_zone = (const void *)mz;
4962         bp->hw_tx_port_stats = mz->addr;
4963         bp->hw_tx_port_stats_map = mz_phys_addr;
4964         bp->flags |= BNXT_FLAG_PORT_STATS;
4965
4966         /* Display extended statistics if FW supports it */
4967         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4968             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4969             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4970                 return 0;
4971
4972         bp->hw_rx_port_stats_ext = (void *)
4973                 ((uint8_t *)bp->hw_rx_port_stats +
4974                  sizeof(struct rx_port_stats));
4975         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4976                 sizeof(struct rx_port_stats);
4977         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4978
4979         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4980             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4981                 bp->hw_tx_port_stats_ext = (void *)
4982                         ((uint8_t *)bp->hw_tx_port_stats +
4983                          sizeof(struct tx_port_stats));
4984                 bp->hw_tx_port_stats_ext_map =
4985                         bp->hw_tx_port_stats_map +
4986                         sizeof(struct tx_port_stats);
4987                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4988         }
4989
4990         return 0;
4991 }
4992
4993 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4994 {
4995         struct bnxt *bp = eth_dev->data->dev_private;
4996         int rc = 0;
4997
4998         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4999                                                RTE_ETHER_ADDR_LEN *
5000                                                bp->max_l2_ctx,
5001                                                0);
5002         if (eth_dev->data->mac_addrs == NULL) {
5003                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5004                 return -ENOMEM;
5005         }
5006
5007         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5008                 if (BNXT_PF(bp))
5009                         return -EINVAL;
5010
5011                 /* Generate a random MAC address, if none was assigned by PF */
5012                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5013                 bnxt_eth_hw_addr_random(bp->mac_addr);
5014                 PMD_DRV_LOG(INFO,
5015                             "Assign random MAC:" RTE_ETHER_ADDR_PRT_FMT "\n",
5016                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5017                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5018
5019                 rc = bnxt_hwrm_set_mac(bp);
5020                 if (rc)
5021                         return rc;
5022         }
5023
5024         /* Copy the permanent MAC from the FUNC_QCAPS response */
5025         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5026
5027         return rc;
5028 }
5029
5030 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5031 {
5032         int rc = 0;
5033
5034         /* MAC is already configured in FW */
5035         if (BNXT_HAS_DFLT_MAC_SET(bp))
5036                 return 0;
5037
5038         /* Restore the old MAC configured */
5039         rc = bnxt_hwrm_set_mac(bp);
5040         if (rc)
5041                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5042
5043         return rc;
5044 }
5045
5046 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5047 {
5048         if (!BNXT_PF(bp))
5049                 return;
5050
5051         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5052
5053         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
5054                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
5055         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
5056         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
5057         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
5058         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
5059 }
5060
5061 struct bnxt *
5062 bnxt_get_bp(uint16_t port)
5063 {
5064         struct bnxt *bp;
5065         struct rte_eth_dev *dev;
5066
5067         if (!rte_eth_dev_is_valid_port(port)) {
5068                 PMD_DRV_LOG(ERR, "Invalid port %d\n", port);
5069                 return NULL;
5070         }
5071
5072         dev = &rte_eth_devices[port];
5073         if (!is_bnxt_supported(dev)) {
5074                 PMD_DRV_LOG(ERR, "Device %d not supported\n", port);
5075                 return NULL;
5076         }
5077
5078         bp = (struct bnxt *)dev->data->dev_private;
5079         if (!BNXT_TRUFLOW_EN(bp)) {
5080                 PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n");
5081                 return NULL;
5082         }
5083
5084         return bp;
5085 }
5086
5087 uint16_t
5088 bnxt_get_svif(uint16_t port_id, bool func_svif,
5089               enum bnxt_ulp_intf_type type)
5090 {
5091         struct rte_eth_dev *eth_dev;
5092         struct bnxt *bp;
5093
5094         eth_dev = &rte_eth_devices[port_id];
5095         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5096                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5097                 if (!vfr)
5098                         return 0;
5099
5100                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5101                         return vfr->svif;
5102
5103                 eth_dev = vfr->parent_dev;
5104         }
5105
5106         bp = eth_dev->data->dev_private;
5107
5108         return func_svif ? bp->func_svif : bp->port_svif;
5109 }
5110
5111 void
5112 bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type,
5113                    uint8_t *mac, uint8_t *parent_mac)
5114 {
5115         struct rte_eth_dev *eth_dev;
5116         struct bnxt *bp;
5117
5118         if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF &&
5119             type != BNXT_ULP_INTF_TYPE_PF)
5120                 return;
5121
5122         eth_dev = &rte_eth_devices[port];
5123         bp = eth_dev->data->dev_private;
5124         memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5125
5126         if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5127                 memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN);
5128 }
5129
5130 uint16_t
5131 bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5132 {
5133         struct rte_eth_dev *eth_dev;
5134         struct bnxt *bp;
5135
5136         if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5137                 return 0;
5138
5139         eth_dev = &rte_eth_devices[port];
5140         bp = eth_dev->data->dev_private;
5141
5142         return bp->parent->vnic;
5143 }
5144 uint16_t
5145 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5146 {
5147         struct rte_eth_dev *eth_dev;
5148         struct bnxt_vnic_info *vnic;
5149         struct bnxt *bp;
5150
5151         eth_dev = &rte_eth_devices[port];
5152         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5153                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5154                 if (!vfr)
5155                         return 0;
5156
5157                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5158                         return vfr->dflt_vnic_id;
5159
5160                 eth_dev = vfr->parent_dev;
5161         }
5162
5163         bp = eth_dev->data->dev_private;
5164
5165         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5166
5167         return vnic->fw_vnic_id;
5168 }
5169
5170 uint16_t
5171 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5172 {
5173         struct rte_eth_dev *eth_dev;
5174         struct bnxt *bp;
5175
5176         eth_dev = &rte_eth_devices[port];
5177         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5178                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5179                 if (!vfr)
5180                         return 0;
5181
5182                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5183                         return vfr->fw_fid;
5184
5185                 eth_dev = vfr->parent_dev;
5186         }
5187
5188         bp = eth_dev->data->dev_private;
5189
5190         return bp->fw_fid;
5191 }
5192
5193 enum bnxt_ulp_intf_type
5194 bnxt_get_interface_type(uint16_t port)
5195 {
5196         struct rte_eth_dev *eth_dev;
5197         struct bnxt *bp;
5198
5199         eth_dev = &rte_eth_devices[port];
5200         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5201                 return BNXT_ULP_INTF_TYPE_VF_REP;
5202
5203         bp = eth_dev->data->dev_private;
5204         if (BNXT_PF(bp))
5205                 return BNXT_ULP_INTF_TYPE_PF;
5206         else if (BNXT_VF_IS_TRUSTED(bp))
5207                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5208         else if (BNXT_VF(bp))
5209                 return BNXT_ULP_INTF_TYPE_VF;
5210
5211         return BNXT_ULP_INTF_TYPE_INVALID;
5212 }
5213
5214 uint16_t
5215 bnxt_get_phy_port_id(uint16_t port_id)
5216 {
5217         struct bnxt_representor *vfr;
5218         struct rte_eth_dev *eth_dev;
5219         struct bnxt *bp;
5220
5221         eth_dev = &rte_eth_devices[port_id];
5222         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5223                 vfr = eth_dev->data->dev_private;
5224                 if (!vfr)
5225                         return 0;
5226
5227                 eth_dev = vfr->parent_dev;
5228         }
5229
5230         bp = eth_dev->data->dev_private;
5231
5232         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5233 }
5234
5235 uint16_t
5236 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5237 {
5238         struct rte_eth_dev *eth_dev;
5239         struct bnxt *bp;
5240
5241         eth_dev = &rte_eth_devices[port_id];
5242         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5243                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5244                 if (!vfr)
5245                         return 0;
5246
5247                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5248                         return vfr->fw_fid - 1;
5249
5250                 eth_dev = vfr->parent_dev;
5251         }
5252
5253         bp = eth_dev->data->dev_private;
5254
5255         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5256 }
5257
5258 uint16_t
5259 bnxt_get_vport(uint16_t port_id)
5260 {
5261         return (1 << bnxt_get_phy_port_id(port_id));
5262 }
5263
5264 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5265 {
5266         struct bnxt_error_recovery_info *info = bp->recovery_info;
5267
5268         if (info) {
5269                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5270                         memset(info, 0, sizeof(*info));
5271                 return;
5272         }
5273
5274         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5275                 return;
5276
5277         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5278                            sizeof(*info), 0);
5279         if (!info)
5280                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5281
5282         bp->recovery_info = info;
5283 }
5284
5285 static void bnxt_check_fw_status(struct bnxt *bp)
5286 {
5287         uint32_t fw_status;
5288
5289         if (!(bp->recovery_info &&
5290               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5291                 return;
5292
5293         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5294         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5295                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5296                             fw_status);
5297 }
5298
5299 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5300 {
5301         struct bnxt_error_recovery_info *info = bp->recovery_info;
5302         uint32_t status_loc;
5303         uint32_t sig_ver;
5304
5305         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5306                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5307         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5308                                    BNXT_GRCP_WINDOW_2_BASE +
5309                                    offsetof(struct hcomm_status,
5310                                             sig_ver)));
5311         /* If the signature is absent, then FW does not support this feature */
5312         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5313             HCOMM_STATUS_SIGNATURE_VAL)
5314                 return 0;
5315
5316         if (!info) {
5317                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5318                                    sizeof(*info), 0);
5319                 if (!info)
5320                         return -ENOMEM;
5321                 bp->recovery_info = info;
5322         } else {
5323                 memset(info, 0, sizeof(*info));
5324         }
5325
5326         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5327                                       BNXT_GRCP_WINDOW_2_BASE +
5328                                       offsetof(struct hcomm_status,
5329                                                fw_status_loc)));
5330
5331         /* Only pre-map the FW health status GRC register */
5332         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5333                 return 0;
5334
5335         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5336         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5337                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5338
5339         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5340                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5341
5342         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5343
5344         return 0;
5345 }
5346
5347 /* This function gets the FW version along with the
5348  * capabilities(MAX and current) of the function, vnic,
5349  * error recovery, phy and other chip related info
5350  */
5351 static int bnxt_get_config(struct bnxt *bp)
5352 {
5353         uint16_t mtu;
5354         int rc = 0;
5355
5356         bp->fw_cap = 0;
5357
5358         rc = bnxt_map_hcomm_fw_status_reg(bp);
5359         if (rc)
5360                 return rc;
5361
5362         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5363         if (rc) {
5364                 bnxt_check_fw_status(bp);
5365                 return rc;
5366         }
5367
5368         rc = bnxt_hwrm_func_reset(bp);
5369         if (rc)
5370                 return -EIO;
5371
5372         rc = bnxt_hwrm_vnic_qcaps(bp);
5373         if (rc)
5374                 return rc;
5375
5376         rc = bnxt_hwrm_queue_qportcfg(bp);
5377         if (rc)
5378                 return rc;
5379
5380         /* Get the MAX capabilities for this function.
5381          * This function also allocates context memory for TQM rings and
5382          * informs the firmware about this allocated backing store memory.
5383          */
5384         rc = bnxt_hwrm_func_qcaps(bp);
5385         if (rc)
5386                 return rc;
5387
5388         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5389         if (rc)
5390                 return rc;
5391
5392         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5393         if (rc)
5394                 return rc;
5395
5396         bnxt_hwrm_port_mac_qcfg(bp);
5397
5398         bnxt_hwrm_parent_pf_qcfg(bp);
5399
5400         bnxt_hwrm_port_phy_qcaps(bp);
5401
5402         bnxt_alloc_error_recovery_info(bp);
5403         /* Get the adapter error recovery support info */
5404         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5405         if (rc)
5406                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5407
5408         bnxt_hwrm_port_led_qcaps(bp);
5409
5410         return 0;
5411 }
5412
5413 static int
5414 bnxt_init_locks(struct bnxt *bp)
5415 {
5416         int err;
5417
5418         err = pthread_mutex_init(&bp->flow_lock, NULL);
5419         if (err) {
5420                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5421                 return err;
5422         }
5423
5424         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5425         if (err) {
5426                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5427                 return err;
5428         }
5429
5430         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5431         if (err) {
5432                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5433                 return err;
5434         }
5435
5436         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5437         if (err)
5438                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5439
5440         return err;
5441 }
5442
5443 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5444 {
5445         int rc = 0;
5446
5447         rc = bnxt_get_config(bp);
5448         if (rc)
5449                 return rc;
5450
5451         if (!reconfig_dev) {
5452                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5453                 if (rc)
5454                         return rc;
5455         } else {
5456                 rc = bnxt_restore_dflt_mac(bp);
5457                 if (rc)
5458                         return rc;
5459         }
5460
5461         bnxt_config_vf_req_fwd(bp);
5462
5463         rc = bnxt_hwrm_func_driver_register(bp);
5464         if (rc) {
5465                 PMD_DRV_LOG(ERR, "Failed to register driver");
5466                 return -EBUSY;
5467         }
5468
5469         if (BNXT_PF(bp)) {
5470                 if (bp->pdev->max_vfs) {
5471                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5472                         if (rc) {
5473                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5474                                 return rc;
5475                         }
5476                 } else {
5477                         rc = bnxt_hwrm_allocate_pf_only(bp);
5478                         if (rc) {
5479                                 PMD_DRV_LOG(ERR,
5480                                             "Failed to allocate PF resources");
5481                                 return rc;
5482                         }
5483                 }
5484         }
5485
5486         rc = bnxt_alloc_mem(bp, reconfig_dev);
5487         if (rc)
5488                 return rc;
5489
5490         rc = bnxt_setup_int(bp);
5491         if (rc)
5492                 return rc;
5493
5494         rc = bnxt_request_int(bp);
5495         if (rc)
5496                 return rc;
5497
5498         rc = bnxt_init_ctx_mem(bp);
5499         if (rc) {
5500                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5501                 return rc;
5502         }
5503
5504         return 0;
5505 }
5506
5507 static int
5508 bnxt_parse_devarg_accum_stats(__rte_unused const char *key,
5509                               const char *value, void *opaque_arg)
5510 {
5511         struct bnxt *bp = opaque_arg;
5512         unsigned long accum_stats;
5513         char *end = NULL;
5514
5515         if (!value || !opaque_arg) {
5516                 PMD_DRV_LOG(ERR,
5517                             "Invalid parameter passed to accum-stats devargs.\n");
5518                 return -EINVAL;
5519         }
5520
5521         accum_stats = strtoul(value, &end, 10);
5522         if (end == NULL || *end != '\0' ||
5523             (accum_stats == ULONG_MAX && errno == ERANGE)) {
5524                 PMD_DRV_LOG(ERR,
5525                             "Invalid parameter passed to accum-stats devargs.\n");
5526                 return -EINVAL;
5527         }
5528
5529         if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) {
5530                 PMD_DRV_LOG(ERR,
5531                             "Invalid value passed to accum-stats devargs.\n");
5532                 return -EINVAL;
5533         }
5534
5535         if (accum_stats) {
5536                 bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN;
5537                 PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n");
5538         } else {
5539                 bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN;
5540                 PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n");
5541         }
5542
5543         return 0;
5544 }
5545
5546 static int
5547 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5548                              const char *value, void *opaque_arg)
5549 {
5550         struct bnxt *bp = opaque_arg;
5551         unsigned long flow_xstat;
5552         char *end = NULL;
5553
5554         if (!value || !opaque_arg) {
5555                 PMD_DRV_LOG(ERR,
5556                             "Invalid parameter passed to flow_xstat devarg.\n");
5557                 return -EINVAL;
5558         }
5559
5560         flow_xstat = strtoul(value, &end, 10);
5561         if (end == NULL || *end != '\0' ||
5562             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5563                 PMD_DRV_LOG(ERR,
5564                             "Invalid parameter passed to flow_xstat devarg.\n");
5565                 return -EINVAL;
5566         }
5567
5568         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5569                 PMD_DRV_LOG(ERR,
5570                             "Invalid value passed to flow_xstat devarg.\n");
5571                 return -EINVAL;
5572         }
5573
5574         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5575         if (BNXT_FLOW_XSTATS_EN(bp))
5576                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5577
5578         return 0;
5579 }
5580
5581 static int
5582 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5583                                         const char *value, void *opaque_arg)
5584 {
5585         struct bnxt *bp = opaque_arg;
5586         unsigned long max_num_kflows;
5587         char *end = NULL;
5588
5589         if (!value || !opaque_arg) {
5590                 PMD_DRV_LOG(ERR,
5591                         "Invalid parameter passed to max_num_kflows devarg.\n");
5592                 return -EINVAL;
5593         }
5594
5595         max_num_kflows = strtoul(value, &end, 10);
5596         if (end == NULL || *end != '\0' ||
5597                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5598                 PMD_DRV_LOG(ERR,
5599                         "Invalid parameter passed to max_num_kflows devarg.\n");
5600                 return -EINVAL;
5601         }
5602
5603         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5604                 PMD_DRV_LOG(ERR,
5605                         "Invalid value passed to max_num_kflows devarg.\n");
5606                 return -EINVAL;
5607         }
5608
5609         bp->max_num_kflows = max_num_kflows;
5610         if (bp->max_num_kflows)
5611                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5612                                 max_num_kflows);
5613
5614         return 0;
5615 }
5616
5617 static int
5618 bnxt_parse_devarg_app_id(__rte_unused const char *key,
5619                                  const char *value, void *opaque_arg)
5620 {
5621         struct bnxt *bp = opaque_arg;
5622         unsigned long app_id;
5623         char *end = NULL;
5624
5625         if (!value || !opaque_arg) {
5626                 PMD_DRV_LOG(ERR,
5627                             "Invalid parameter passed to app-id "
5628                             "devargs.\n");
5629                 return -EINVAL;
5630         }
5631
5632         app_id = strtoul(value, &end, 10);
5633         if (end == NULL || *end != '\0' ||
5634             (app_id == ULONG_MAX && errno == ERANGE)) {
5635                 PMD_DRV_LOG(ERR,
5636                             "Invalid parameter passed to app_id "
5637                             "devargs.\n");
5638                 return -EINVAL;
5639         }
5640
5641         if (BNXT_DEVARG_APP_ID_INVALID(app_id)) {
5642                 PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n",
5643                             (uint16_t)app_id);
5644                 return -EINVAL;
5645         }
5646
5647         bp->app_id = app_id;
5648         PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id);
5649
5650         return 0;
5651 }
5652
5653 static int
5654 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5655                             const char *value, void *opaque_arg)
5656 {
5657         struct bnxt_representor *vfr_bp = opaque_arg;
5658         unsigned long rep_is_pf;
5659         char *end = NULL;
5660
5661         if (!value || !opaque_arg) {
5662                 PMD_DRV_LOG(ERR,
5663                             "Invalid parameter passed to rep_is_pf devargs.\n");
5664                 return -EINVAL;
5665         }
5666
5667         rep_is_pf = strtoul(value, &end, 10);
5668         if (end == NULL || *end != '\0' ||
5669             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5670                 PMD_DRV_LOG(ERR,
5671                             "Invalid parameter passed to rep_is_pf devargs.\n");
5672                 return -EINVAL;
5673         }
5674
5675         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5676                 PMD_DRV_LOG(ERR,
5677                             "Invalid value passed to rep_is_pf devargs.\n");
5678                 return -EINVAL;
5679         }
5680
5681         vfr_bp->flags |= rep_is_pf;
5682         if (BNXT_REP_PF(vfr_bp))
5683                 PMD_DRV_LOG(INFO, "PF representor\n");
5684         else
5685                 PMD_DRV_LOG(INFO, "VF representor\n");
5686
5687         return 0;
5688 }
5689
5690 static int
5691 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5692                                const char *value, void *opaque_arg)
5693 {
5694         struct bnxt_representor *vfr_bp = opaque_arg;
5695         unsigned long rep_based_pf;
5696         char *end = NULL;
5697
5698         if (!value || !opaque_arg) {
5699                 PMD_DRV_LOG(ERR,
5700                             "Invalid parameter passed to rep_based_pf "
5701                             "devargs.\n");
5702                 return -EINVAL;
5703         }
5704
5705         rep_based_pf = strtoul(value, &end, 10);
5706         if (end == NULL || *end != '\0' ||
5707             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5708                 PMD_DRV_LOG(ERR,
5709                             "Invalid parameter passed to rep_based_pf "
5710                             "devargs.\n");
5711                 return -EINVAL;
5712         }
5713
5714         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5715                 PMD_DRV_LOG(ERR,
5716                             "Invalid value passed to rep_based_pf devargs.\n");
5717                 return -EINVAL;
5718         }
5719
5720         vfr_bp->rep_based_pf = rep_based_pf;
5721         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5722
5723         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5724
5725         return 0;
5726 }
5727
5728 static int
5729 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5730                             const char *value, void *opaque_arg)
5731 {
5732         struct bnxt_representor *vfr_bp = opaque_arg;
5733         unsigned long rep_q_r2f;
5734         char *end = NULL;
5735
5736         if (!value || !opaque_arg) {
5737                 PMD_DRV_LOG(ERR,
5738                             "Invalid parameter passed to rep_q_r2f "
5739                             "devargs.\n");
5740                 return -EINVAL;
5741         }
5742
5743         rep_q_r2f = strtoul(value, &end, 10);
5744         if (end == NULL || *end != '\0' ||
5745             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5746                 PMD_DRV_LOG(ERR,
5747                             "Invalid parameter passed to rep_q_r2f "
5748                             "devargs.\n");
5749                 return -EINVAL;
5750         }
5751
5752         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5753                 PMD_DRV_LOG(ERR,
5754                             "Invalid value passed to rep_q_r2f devargs.\n");
5755                 return -EINVAL;
5756         }
5757
5758         vfr_bp->rep_q_r2f = rep_q_r2f;
5759         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5760         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5761
5762         return 0;
5763 }
5764
5765 static int
5766 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5767                             const char *value, void *opaque_arg)
5768 {
5769         struct bnxt_representor *vfr_bp = opaque_arg;
5770         unsigned long rep_q_f2r;
5771         char *end = NULL;
5772
5773         if (!value || !opaque_arg) {
5774                 PMD_DRV_LOG(ERR,
5775                             "Invalid parameter passed to rep_q_f2r "
5776                             "devargs.\n");
5777                 return -EINVAL;
5778         }
5779
5780         rep_q_f2r = strtoul(value, &end, 10);
5781         if (end == NULL || *end != '\0' ||
5782             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5783                 PMD_DRV_LOG(ERR,
5784                             "Invalid parameter passed to rep_q_f2r "
5785                             "devargs.\n");
5786                 return -EINVAL;
5787         }
5788
5789         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5790                 PMD_DRV_LOG(ERR,
5791                             "Invalid value passed to rep_q_f2r devargs.\n");
5792                 return -EINVAL;
5793         }
5794
5795         vfr_bp->rep_q_f2r = rep_q_f2r;
5796         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5797         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5798
5799         return 0;
5800 }
5801
5802 static int
5803 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5804                              const char *value, void *opaque_arg)
5805 {
5806         struct bnxt_representor *vfr_bp = opaque_arg;
5807         unsigned long rep_fc_r2f;
5808         char *end = NULL;
5809
5810         if (!value || !opaque_arg) {
5811                 PMD_DRV_LOG(ERR,
5812                             "Invalid parameter passed to rep_fc_r2f "
5813                             "devargs.\n");
5814                 return -EINVAL;
5815         }
5816
5817         rep_fc_r2f = strtoul(value, &end, 10);
5818         if (end == NULL || *end != '\0' ||
5819             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5820                 PMD_DRV_LOG(ERR,
5821                             "Invalid parameter passed to rep_fc_r2f "
5822                             "devargs.\n");
5823                 return -EINVAL;
5824         }
5825
5826         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5827                 PMD_DRV_LOG(ERR,
5828                             "Invalid value passed to rep_fc_r2f devargs.\n");
5829                 return -EINVAL;
5830         }
5831
5832         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5833         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5834         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5835
5836         return 0;
5837 }
5838
5839 static int
5840 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5841                              const char *value, void *opaque_arg)
5842 {
5843         struct bnxt_representor *vfr_bp = opaque_arg;
5844         unsigned long rep_fc_f2r;
5845         char *end = NULL;
5846
5847         if (!value || !opaque_arg) {
5848                 PMD_DRV_LOG(ERR,
5849                             "Invalid parameter passed to rep_fc_f2r "
5850                             "devargs.\n");
5851                 return -EINVAL;
5852         }
5853
5854         rep_fc_f2r = strtoul(value, &end, 10);
5855         if (end == NULL || *end != '\0' ||
5856             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5857                 PMD_DRV_LOG(ERR,
5858                             "Invalid parameter passed to rep_fc_f2r "
5859                             "devargs.\n");
5860                 return -EINVAL;
5861         }
5862
5863         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5864                 PMD_DRV_LOG(ERR,
5865                             "Invalid value passed to rep_fc_f2r devargs.\n");
5866                 return -EINVAL;
5867         }
5868
5869         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5870         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5871         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5872
5873         return 0;
5874 }
5875
5876 static int
5877 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5878 {
5879         struct rte_kvargs *kvlist;
5880         int ret;
5881
5882         if (devargs == NULL)
5883                 return 0;
5884
5885         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5886         if (kvlist == NULL)
5887                 return -EINVAL;
5888
5889         /*
5890          * Handler for "flow_xstat" devarg.
5891          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5892          */
5893         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5894                                  bnxt_parse_devarg_flow_xstat, bp);
5895         if (ret)
5896                 goto err;
5897
5898         /*
5899          * Handler for "accum-stats" devarg.
5900          * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1"
5901          */
5902         rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS,
5903                            bnxt_parse_devarg_accum_stats, bp);
5904         /*
5905          * Handler for "max_num_kflows" devarg.
5906          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5907          */
5908         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5909                                  bnxt_parse_devarg_max_num_kflows, bp);
5910         if (ret)
5911                 goto err;
5912
5913 err:
5914         /*
5915          * Handler for "app-id" devarg.
5916          * Invoked as for ex: "-a 000:00:0d.0,app-id=1"
5917          */
5918         rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID,
5919                            bnxt_parse_devarg_app_id, bp);
5920
5921         rte_kvargs_free(kvlist);
5922         return ret;
5923 }
5924
5925 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5926 {
5927         int rc = 0;
5928
5929         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5930                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5931                 if (rc)
5932                         PMD_DRV_LOG(ERR,
5933                                     "Failed to alloc switch domain: %d\n", rc);
5934                 else
5935                         PMD_DRV_LOG(INFO,
5936                                     "Switch domain allocated %d\n",
5937                                     bp->switch_domain_id);
5938         }
5939
5940         return rc;
5941 }
5942
5943 /* Allocate and initialize various fields in bnxt struct that
5944  * need to be allocated/destroyed only once in the lifetime of the driver
5945  */
5946 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5947 {
5948         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5949         struct bnxt *bp = eth_dev->data->dev_private;
5950         int rc = 0;
5951
5952         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5953
5954         if (bnxt_vf_pciid(pci_dev->id.device_id))
5955                 bp->flags |= BNXT_FLAG_VF;
5956
5957         if (bnxt_p5_device(pci_dev->id.device_id))
5958                 bp->flags |= BNXT_FLAG_CHIP_P5;
5959
5960         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5961             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5962             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5963             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5964                 bp->flags |= BNXT_FLAG_STINGRAY;
5965
5966         if (BNXT_TRUFLOW_EN(bp)) {
5967                 /* extra mbuf field is required to store CFA code from mark */
5968                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5969                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5970                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5971                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5972                 };
5973                 bnxt_cfa_code_dynfield_offset =
5974                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5975                 if (bnxt_cfa_code_dynfield_offset < 0) {
5976                         PMD_DRV_LOG(ERR,
5977                             "Failed to register mbuf field for TruFlow mark\n");
5978                         return -rte_errno;
5979                 }
5980         }
5981
5982         rc = bnxt_map_pci_bars(eth_dev);
5983         if (rc) {
5984                 PMD_DRV_LOG(ERR,
5985                             "Failed to initialize board rc: %x\n", rc);
5986                 return rc;
5987         }
5988
5989         rc = bnxt_alloc_pf_info(bp);
5990         if (rc)
5991                 return rc;
5992
5993         rc = bnxt_alloc_link_info(bp);
5994         if (rc)
5995                 return rc;
5996
5997         rc = bnxt_alloc_parent_info(bp);
5998         if (rc)
5999                 return rc;
6000
6001         rc = bnxt_alloc_hwrm_resources(bp);
6002         if (rc) {
6003                 PMD_DRV_LOG(ERR,
6004                             "Failed to allocate response buffer rc: %x\n", rc);
6005                 return rc;
6006         }
6007         rc = bnxt_alloc_leds_info(bp);
6008         if (rc)
6009                 return rc;
6010
6011         rc = bnxt_alloc_cos_queues(bp);
6012         if (rc)
6013                 return rc;
6014
6015         rc = bnxt_init_locks(bp);
6016         if (rc)
6017                 return rc;
6018
6019         rc = bnxt_alloc_switch_domain(bp);
6020         if (rc)
6021                 return rc;
6022
6023         return rc;
6024 }
6025
6026 static int
6027 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
6028 {
6029         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
6030         static int version_printed;
6031         struct bnxt *bp;
6032         int rc;
6033
6034         if (version_printed++ == 0)
6035                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
6036
6037         eth_dev->dev_ops = &bnxt_dev_ops;
6038         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
6039         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
6040         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
6041         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
6042         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
6043
6044         /*
6045          * For secondary processes, we don't initialise any further
6046          * as primary has already done this work.
6047          */
6048         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6049                 return 0;
6050
6051         rte_eth_copy_pci_info(eth_dev, pci_dev);
6052         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
6053
6054         bp = eth_dev->data->dev_private;
6055
6056         /* Parse dev arguments passed on when starting the DPDK application. */
6057         rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6058         if (rc)
6059                 goto error_free;
6060
6061         rc = bnxt_drv_init(eth_dev);
6062         if (rc)
6063                 goto error_free;
6064
6065         rc = bnxt_init_resources(bp, false);
6066         if (rc)
6067                 goto error_free;
6068
6069         rc = bnxt_alloc_stats_mem(bp);
6070         if (rc)
6071                 goto error_free;
6072
6073         PMD_DRV_LOG(INFO,
6074                     "Found %s device at mem %" PRIX64 ", node addr %pM\n",
6075                     DRV_MODULE_NAME,
6076                     pci_dev->mem_resource[0].phys_addr,
6077                     pci_dev->mem_resource[0].addr);
6078
6079         return 0;
6080
6081 error_free:
6082         bnxt_dev_uninit(eth_dev);
6083         return rc;
6084 }
6085
6086
6087 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6088 {
6089         if (!ctx)
6090                 return;
6091
6092         if (ctx->va)
6093                 rte_free(ctx->va);
6094
6095         ctx->va = NULL;
6096         ctx->dma = RTE_BAD_IOVA;
6097         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6098 }
6099
6100 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6101 {
6102         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6103                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6104                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
6105                                   bp->flow_stat->max_fc,
6106                                   false);
6107
6108         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6109                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6110                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
6111                                   bp->flow_stat->max_fc,
6112                                   false);
6113
6114         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6115                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6116         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6117
6118         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6119                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6120         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6121
6122         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6123                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6124         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6125
6126         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6127                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6128         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6129 }
6130
6131 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6132 {
6133         bnxt_unregister_fc_ctx_mem(bp);
6134
6135         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6136         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6137         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6138         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6139 }
6140
6141 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6142 {
6143         if (BNXT_FLOW_XSTATS_EN(bp))
6144                 bnxt_uninit_fc_ctx_mem(bp);
6145 }
6146
6147 static void
6148 bnxt_free_error_recovery_info(struct bnxt *bp)
6149 {
6150         rte_free(bp->recovery_info);
6151         bp->recovery_info = NULL;
6152         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6153 }
6154
6155 static int
6156 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6157 {
6158         int rc;
6159
6160         bnxt_free_int(bp);
6161         bnxt_free_mem(bp, reconfig_dev);
6162
6163         bnxt_hwrm_func_buf_unrgtr(bp);
6164         if (bp->pf != NULL) {
6165                 rte_free(bp->pf->vf_req_buf);
6166                 bp->pf->vf_req_buf = NULL;
6167         }
6168
6169         rc = bnxt_hwrm_func_driver_unregister(bp);
6170         bp->flags &= ~BNXT_FLAG_REGISTERED;
6171         bnxt_free_ctx_mem(bp);
6172         if (!reconfig_dev) {
6173                 bnxt_free_hwrm_resources(bp);
6174                 bnxt_free_error_recovery_info(bp);
6175         }
6176
6177         bnxt_uninit_ctx_mem(bp);
6178
6179         bnxt_free_flow_stats_info(bp);
6180         if (bp->rep_info != NULL)
6181                 bnxt_free_switch_domain(bp);
6182         bnxt_free_rep_info(bp);
6183         rte_free(bp->ptp_cfg);
6184         bp->ptp_cfg = NULL;
6185         return rc;
6186 }
6187
6188 static int
6189 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6190 {
6191         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6192                 return -EPERM;
6193
6194         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6195
6196         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6197                 bnxt_dev_close_op(eth_dev);
6198
6199         return 0;
6200 }
6201
6202 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6203 {
6204         struct bnxt *bp = eth_dev->data->dev_private;
6205         struct rte_eth_dev *vf_rep_eth_dev;
6206         int ret = 0, i;
6207
6208         if (!bp)
6209                 return -EINVAL;
6210
6211         for (i = 0; i < bp->num_reps; i++) {
6212                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6213                 if (!vf_rep_eth_dev)
6214                         continue;
6215                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6216                             vf_rep_eth_dev->data->port_id);
6217                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6218         }
6219         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6220                     eth_dev->data->port_id);
6221         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6222
6223         return ret;
6224 }
6225
6226 static void bnxt_free_rep_info(struct bnxt *bp)
6227 {
6228         rte_free(bp->rep_info);
6229         bp->rep_info = NULL;
6230         rte_free(bp->cfa_code_map);
6231         bp->cfa_code_map = NULL;
6232 }
6233
6234 static int bnxt_init_rep_info(struct bnxt *bp)
6235 {
6236         int i = 0, rc;
6237
6238         if (bp->rep_info)
6239                 return 0;
6240
6241         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6242                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6243                                    0);
6244         if (!bp->rep_info) {
6245                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6246                 return -ENOMEM;
6247         }
6248         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6249                                        sizeof(*bp->cfa_code_map) *
6250                                        BNXT_MAX_CFA_CODE, 0);
6251         if (!bp->cfa_code_map) {
6252                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6253                 bnxt_free_rep_info(bp);
6254                 return -ENOMEM;
6255         }
6256
6257         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6258                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6259
6260         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6261         if (rc) {
6262                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6263                 bnxt_free_rep_info(bp);
6264                 return rc;
6265         }
6266
6267         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6268         if (rc) {
6269                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6270                 bnxt_free_rep_info(bp);
6271                 return rc;
6272         }
6273
6274         return rc;
6275 }
6276
6277 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6278                                struct rte_eth_devargs *eth_da,
6279                                struct rte_eth_dev *backing_eth_dev,
6280                                const char *dev_args)
6281 {
6282         struct rte_eth_dev *vf_rep_eth_dev;
6283         char name[RTE_ETH_NAME_MAX_LEN];
6284         struct bnxt *backing_bp;
6285         uint16_t num_rep;
6286         int i, ret = 0;
6287         struct rte_kvargs *kvlist = NULL;
6288
6289         if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
6290                 return 0;
6291         if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
6292                 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
6293                             eth_da->type);
6294                 return -ENOTSUP;
6295         }
6296         num_rep = eth_da->nb_representor_ports;
6297         if (num_rep > BNXT_MAX_VF_REPS) {
6298                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6299                             num_rep, BNXT_MAX_VF_REPS);
6300                 return -EINVAL;
6301         }
6302
6303         if (num_rep >= RTE_MAX_ETHPORTS) {
6304                 PMD_DRV_LOG(ERR,
6305                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6306                             num_rep, RTE_MAX_ETHPORTS);
6307                 return -EINVAL;
6308         }
6309
6310         backing_bp = backing_eth_dev->data->dev_private;
6311
6312         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6313                 PMD_DRV_LOG(ERR,
6314                             "Not a PF or trusted VF. No Representor support\n");
6315                 /* Returning an error is not an option.
6316                  * Applications are not handling this correctly
6317                  */
6318                 return 0;
6319         }
6320
6321         if (bnxt_init_rep_info(backing_bp))
6322                 return 0;
6323
6324         for (i = 0; i < num_rep; i++) {
6325                 struct bnxt_representor representor = {
6326                         .vf_id = eth_da->representor_ports[i],
6327                         .switch_domain_id = backing_bp->switch_domain_id,
6328                         .parent_dev = backing_eth_dev
6329                 };
6330
6331                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6332                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6333                                     representor.vf_id, BNXT_MAX_VF_REPS);
6334                         continue;
6335                 }
6336
6337                 /* representor port net_bdf_port */
6338                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6339                          pci_dev->device.name, eth_da->representor_ports[i]);
6340
6341                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6342                 if (kvlist) {
6343                         /*
6344                          * Handler for "rep_is_pf" devarg.
6345                          * Invoked as for ex: "-a 000:00:0d.0,
6346                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6347                          */
6348                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6349                                                  bnxt_parse_devarg_rep_is_pf,
6350                                                  (void *)&representor);
6351                         if (ret) {
6352                                 ret = -EINVAL;
6353                                 goto err;
6354                         }
6355                         /*
6356                          * Handler for "rep_based_pf" devarg.
6357                          * Invoked as for ex: "-a 000:00:0d.0,
6358                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6359                          */
6360                         ret = rte_kvargs_process(kvlist,
6361                                                  BNXT_DEVARG_REP_BASED_PF,
6362                                                  bnxt_parse_devarg_rep_based_pf,
6363                                                  (void *)&representor);
6364                         if (ret) {
6365                                 ret = -EINVAL;
6366                                 goto err;
6367                         }
6368                         /*
6369                          * Handler for "rep_based_pf" devarg.
6370                          * Invoked as for ex: "-a 000:00:0d.0,
6371                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6372                          */
6373                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6374                                                  bnxt_parse_devarg_rep_q_r2f,
6375                                                  (void *)&representor);
6376                         if (ret) {
6377                                 ret = -EINVAL;
6378                                 goto err;
6379                         }
6380                         /*
6381                          * Handler for "rep_based_pf" devarg.
6382                          * Invoked as for ex: "-a 000:00:0d.0,
6383                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6384                          */
6385                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6386                                                  bnxt_parse_devarg_rep_q_f2r,
6387                                                  (void *)&representor);
6388                         if (ret) {
6389                                 ret = -EINVAL;
6390                                 goto err;
6391                         }
6392                         /*
6393                          * Handler for "rep_based_pf" devarg.
6394                          * Invoked as for ex: "-a 000:00:0d.0,
6395                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6396                          */
6397                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6398                                                  bnxt_parse_devarg_rep_fc_r2f,
6399                                                  (void *)&representor);
6400                         if (ret) {
6401                                 ret = -EINVAL;
6402                                 goto err;
6403                         }
6404                         /*
6405                          * Handler for "rep_based_pf" devarg.
6406                          * Invoked as for ex: "-a 000:00:0d.0,
6407                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6408                          */
6409                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6410                                                  bnxt_parse_devarg_rep_fc_f2r,
6411                                                  (void *)&representor);
6412                         if (ret) {
6413                                 ret = -EINVAL;
6414                                 goto err;
6415                         }
6416                 }
6417
6418                 ret = rte_eth_dev_create(&pci_dev->device, name,
6419                                          sizeof(struct bnxt_representor),
6420                                          NULL, NULL,
6421                                          bnxt_representor_init,
6422                                          &representor);
6423                 if (ret) {
6424                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6425                                     "representor %s.", name);
6426                         goto err;
6427                 }
6428
6429                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6430                 if (!vf_rep_eth_dev) {
6431                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6432                                     " for VF-Rep: %s.", name);
6433                         ret = -ENODEV;
6434                         goto err;
6435                 }
6436
6437                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6438                             backing_eth_dev->data->port_id);
6439                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6440                                                          vf_rep_eth_dev;
6441                 backing_bp->num_reps++;
6442
6443         }
6444
6445         rte_kvargs_free(kvlist);
6446         return 0;
6447
6448 err:
6449         /* If num_rep > 1, then rollback already created
6450          * ports, since we'll be failing the probe anyway
6451          */
6452         if (num_rep > 1)
6453                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6454         rte_errno = -ret;
6455         rte_kvargs_free(kvlist);
6456
6457         return ret;
6458 }
6459
6460 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6461                           struct rte_pci_device *pci_dev)
6462 {
6463         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6464         struct rte_eth_dev *backing_eth_dev;
6465         uint16_t num_rep;
6466         int ret = 0;
6467
6468         if (pci_dev->device.devargs) {
6469                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6470                                             &eth_da);
6471                 if (ret)
6472                         return ret;
6473         }
6474
6475         num_rep = eth_da.nb_representor_ports;
6476         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6477                     num_rep);
6478
6479         /* We could come here after first level of probe is already invoked
6480          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6481          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6482          */
6483         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6484         if (backing_eth_dev == NULL) {
6485                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6486                                          sizeof(struct bnxt),
6487                                          eth_dev_pci_specific_init, pci_dev,
6488                                          bnxt_dev_init, NULL);
6489
6490                 if (ret || !num_rep)
6491                         return ret;
6492
6493                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6494         }
6495         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6496                     backing_eth_dev->data->port_id);
6497
6498         if (!num_rep)
6499                 return ret;
6500
6501         /* probe representor ports now */
6502         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
6503                                   pci_dev->device.devargs->args);
6504
6505         return ret;
6506 }
6507
6508 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6509 {
6510         struct rte_eth_dev *eth_dev;
6511
6512         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6513         if (!eth_dev)
6514                 return 0; /* Invoked typically only by OVS-DPDK, by the
6515                            * time it comes here the eth_dev is already
6516                            * deleted by rte_eth_dev_close(), so returning
6517                            * +ve value will at least help in proper cleanup
6518                            */
6519
6520         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6521         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6522                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6523                         return rte_eth_dev_destroy(eth_dev,
6524                                                    bnxt_representor_uninit);
6525                 else
6526                         return rte_eth_dev_destroy(eth_dev,
6527                                                    bnxt_dev_uninit);
6528         } else {
6529                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6530         }
6531 }
6532
6533 static struct rte_pci_driver bnxt_rte_pmd = {
6534         .id_table = bnxt_pci_id_map,
6535         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6536                         RTE_PCI_DRV_INTR_RMV |
6537                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6538                                                   * and OVS-DPDK
6539                                                   */
6540         .probe = bnxt_pci_probe,
6541         .remove = bnxt_pci_remove,
6542 };
6543
6544 static bool
6545 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6546 {
6547         if (strcmp(dev->device->driver->name, drv->driver.name))
6548                 return false;
6549
6550         return true;
6551 }
6552
6553 bool is_bnxt_supported(struct rte_eth_dev *dev)
6554 {
6555         return is_device_supported(dev, &bnxt_rte_pmd);
6556 }
6557
6558 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6559 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6560 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6561 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");