drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  33 int bnxt_logtype_driver;
  34
  35 /*
  36  * The set of PCI devices this driver supports
  37  */
  38 static const struct rte_pci_id bnxt_pci_id_map[] = {
  39         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  40                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  41         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  42                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  43         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  92         { .vendor_id = 0, /* sentinel */ },
  93 };
  94
  95 #define BNXT_ETH_RSS_SUPPORT (  \
  96         ETH_RSS_IPV4 |          \
  97         ETH_RSS_NONFRAG_IPV4_TCP |      \
  98         ETH_RSS_NONFRAG_IPV4_UDP |      \
  99         ETH_RSS_IPV6 |          \
 100         ETH_RSS_NONFRAG_IPV6_TCP |      \
 101         ETH_RSS_NONFRAG_IPV6_UDP)
 102
 103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 104                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 105                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 106                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_TCP_TSO | \
 108                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 109                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 110                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 114                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 115
 116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 117                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 118                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 119                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 120                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 122                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 123                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 124                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 125                                      DEV_RX_OFFLOAD_TCP_LRO | \
 126                                      DEV_RX_OFFLOAD_SCATTER | \
 127                                      DEV_RX_OFFLOAD_RSS_HASH)
 128
 129 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 130 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 131 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 132 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 133 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 134 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 135 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 136
 137 int is_bnxt_in_error(struct bnxt *bp)
 138 {
 139         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 140                 return -EIO;
 141         if (bp->flags & BNXT_FLAG_FW_RESET)
 142                 return -EBUSY;
 143
 144         return 0;
 145 }
 146
 147 /***********************/
 148
 149 /*
 150  * High level utility functions
 151  */
 152
 153 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 154 {
 155         if (!BNXT_CHIP_THOR(bp))
 156                 return 1;
 157
 158         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 159                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 160                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 161 }
 162
 163 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 164 {
 165         if (!BNXT_CHIP_THOR(bp))
 166                 return HW_HASH_INDEX_SIZE;
 167
 168         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 169 }
 170
 171 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 172 {
 173         bnxt_free_filter_mem(bp);
 174         bnxt_free_vnic_attributes(bp);
 175         bnxt_free_vnic_mem(bp);
 176
 177         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 178          * If the number of rings change across fw update,
 179          * we don't have much choice except to warn the user.
 180          */
 181         if (!reconfig) {
 182                 bnxt_free_stats(bp);
 183                 bnxt_free_tx_rings(bp);
 184                 bnxt_free_rx_rings(bp);
 185         }
 186         bnxt_free_async_cp_ring(bp);
 187         bnxt_free_rxtx_nq_ring(bp);
 188
 189         rte_free(bp->grp_info);
 190         bp->grp_info = NULL;
 191 }
 192
 193 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 194 {
 195         int rc;
 196
 197         rc = bnxt_alloc_ring_grps(bp);
 198         if (rc)
 199                 goto alloc_mem_err;
 200
 201         rc = bnxt_alloc_async_ring_struct(bp);
 202         if (rc)
 203                 goto alloc_mem_err;
 204
 205         rc = bnxt_alloc_vnic_mem(bp);
 206         if (rc)
 207                 goto alloc_mem_err;
 208
 209         rc = bnxt_alloc_vnic_attributes(bp);
 210         if (rc)
 211                 goto alloc_mem_err;
 212
 213         rc = bnxt_alloc_filter_mem(bp);
 214         if (rc)
 215                 goto alloc_mem_err;
 216
 217         rc = bnxt_alloc_async_cp_ring(bp);
 218         if (rc)
 219                 goto alloc_mem_err;
 220
 221         rc = bnxt_alloc_rxtx_nq_ring(bp);
 222         if (rc)
 223                 goto alloc_mem_err;
 224
 225         return 0;
 226
 227 alloc_mem_err:
 228         bnxt_free_mem(bp, reconfig);
 229         return rc;
 230 }
 231
 232 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 233 {
 234         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 235         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 236         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 237         struct bnxt_rx_queue *rxq;
 238         unsigned int j;
 239         int rc;
 240
 241         rc = bnxt_vnic_grp_alloc(bp, vnic);
 242         if (rc)
 243                 goto err_out;
 244
 245         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 246                     vnic_id, vnic, vnic->fw_grp_ids);
 247
 248         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 249         if (rc)
 250                 goto err_out;
 251
 252         /* Alloc RSS context only if RSS mode is enabled */
 253         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 254                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 255
 256                 rc = 0;
 257                 for (j = 0; j < nr_ctxs; j++) {
 258                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 259                         if (rc)
 260                                 break;
 261                 }
 262                 if (rc) {
 263                         PMD_DRV_LOG(ERR,
 264                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 265                                     vnic_id, j, rc);
 266                         goto err_out;
 267                 }
 268                 vnic->num_lb_ctxts = nr_ctxs;
 269         }
 270
 271         /*
 272          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 273          * setting is not available at this time, it will not be
 274          * configured correctly in the CFA.
 275          */
 276         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 277                 vnic->vlan_strip = true;
 278         else
 279                 vnic->vlan_strip = false;
 280
 281         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 282         if (rc)
 283                 goto err_out;
 284
 285         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 286         if (rc)
 287                 goto err_out;
 288
 289         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 290                 rxq = bp->eth_dev->data->rx_queues[j];
 291
 292                 PMD_DRV_LOG(DEBUG,
 293                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 294                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 295
 296                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 297                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 298         }
 299
 300         rc = bnxt_vnic_rss_configure(bp, vnic);
 301         if (rc)
 302                 goto err_out;
 303
 304         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 305
 306         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 307                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 308         else
 309                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 310
 311         return 0;
 312 err_out:
 313         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 314                     vnic_id, rc);
 315         return rc;
 316 }
 317
 318 static int bnxt_init_chip(struct bnxt *bp)
 319 {
 320         struct rte_eth_link new;
 321         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 322         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 323         uint32_t intr_vector = 0;
 324         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 325         uint32_t vec = BNXT_MISC_VEC_ID;
 326         unsigned int i, j;
 327         int rc;
 328
 329         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 330                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 331                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 332                 bp->flags |= BNXT_FLAG_JUMBO;
 333         } else {
 334                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 335                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 336                 bp->flags &= ~BNXT_FLAG_JUMBO;
 337         }
 338
 339         /* THOR does not support ring groups.
 340          * But we will use the array to save RSS context IDs.
 341          */
 342         if (BNXT_CHIP_THOR(bp))
 343                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 344
 345         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 346         if (rc) {
 347                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 348                 goto err_out;
 349         }
 350
 351         rc = bnxt_alloc_hwrm_rings(bp);
 352         if (rc) {
 353                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 354                 goto err_out;
 355         }
 356
 357         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 358         if (rc) {
 359                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 360                 goto err_out;
 361         }
 362
 363         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 364                 goto skip_cosq_cfg;
 365
 366         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 367                 if (bp->rx_cos_queue[i].id != 0xff) {
 368                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 369
 370                         if (!vnic) {
 371                                 PMD_DRV_LOG(ERR,
 372                                             "Num pools more than FW profile\n");
 373                                 rc = -EINVAL;
 374                                 goto err_out;
 375                         }
 376                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 377                         bp->rx_cosq_cnt++;
 378                 }
 379         }
 380
 381 skip_cosq_cfg:
 382         rc = bnxt_mq_rx_configure(bp);
 383         if (rc) {
 384                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 385                 goto err_out;
 386         }
 387
 388         /* VNIC configuration */
 389         for (i = 0; i < bp->nr_vnics; i++) {
 390                 rc = bnxt_setup_one_vnic(bp, i);
 391                 if (rc)
 392                         goto err_out;
 393         }
 394
 395         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 396         if (rc) {
 397                 PMD_DRV_LOG(ERR,
 398                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 399                 goto err_out;
 400         }
 401
 402         /* check and configure queue intr-vector mapping */
 403         if ((rte_intr_cap_multiple(intr_handle) ||
 404              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 405             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 406                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 407                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 408                 if (intr_vector > bp->rx_cp_nr_rings) {
 409                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 410                                         bp->rx_cp_nr_rings);
 411                         return -ENOTSUP;
 412                 }
 413                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 414                 if (rc)
 415                         return rc;
 416         }
 417
 418         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 419                 intr_handle->intr_vec =
 420                         rte_zmalloc("intr_vec",
 421                                     bp->eth_dev->data->nb_rx_queues *
 422                                     sizeof(int), 0);
 423                 if (intr_handle->intr_vec == NULL) {
 424                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 425                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 426                         rc = -ENOMEM;
 427                         goto err_disable;
 428                 }
 429                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 430                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 431                          intr_handle->intr_vec, intr_handle->nb_efd,
 432                         intr_handle->max_intr);
 433                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 434                      queue_id++) {
 435                         intr_handle->intr_vec[queue_id] =
 436                                                         vec + BNXT_RX_VEC_START;
 437                         if (vec < base + intr_handle->nb_efd - 1)
 438                                 vec++;
 439                 }
 440         }
 441
 442         /* enable uio/vfio intr/eventfd mapping */
 443         rc = rte_intr_enable(intr_handle);
 444 #ifndef RTE_EXEC_ENV_FREEBSD
 445         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 446         if (rc)
 447                 goto err_free;
 448 #endif
 449
 450         rc = bnxt_get_hwrm_link_config(bp, &new);
 451         if (rc) {
 452                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 453                 goto err_free;
 454         }
 455
 456         if (!bp->link_info.link_up) {
 457                 rc = bnxt_set_hwrm_link_config(bp, true);
 458                 if (rc) {
 459                         PMD_DRV_LOG(ERR,
 460                                 "HWRM link config failure rc: %x\n", rc);
 461                         goto err_free;
 462                 }
 463         }
 464         bnxt_print_link_info(bp->eth_dev);
 465
 466         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 467         if (!bp->mark_table)
 468                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 469
 470         return 0;
 471
 472 err_free:
 473         rte_free(intr_handle->intr_vec);
 474 err_disable:
 475         rte_intr_efd_disable(intr_handle);
 476 err_out:
 477         /* Some of the error status returned by FW may not be from errno.h */
 478         if (rc > 0)
 479                 rc = -EIO;
 480
 481         return rc;
 482 }
 483
 484 static int bnxt_shutdown_nic(struct bnxt *bp)
 485 {
 486         bnxt_free_all_hwrm_resources(bp);
 487         bnxt_free_all_filters(bp);
 488         bnxt_free_all_vnics(bp);
 489         return 0;
 490 }
 491
 492 /*
 493  * Device configuration and status function
 494  */
 495
 496 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 497                                 struct rte_eth_dev_info *dev_info)
 498 {
 499         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 500         struct bnxt *bp = eth_dev->data->dev_private;
 501         uint16_t max_vnics, i, j, vpool, vrxq;
 502         unsigned int max_rx_rings;
 503         int rc;
 504
 505         rc = is_bnxt_in_error(bp);
 506         if (rc)
 507                 return rc;
 508
 509         /* MAC Specifics */
 510         dev_info->max_mac_addrs = bp->max_l2_ctx;
 511         dev_info->max_hash_mac_addrs = 0;
 512
 513         /* PF/VF specifics */
 514         if (BNXT_PF(bp))
 515                 dev_info->max_vfs = pdev->max_vfs;
 516
 517         max_rx_rings = BNXT_MAX_RINGS(bp);
 518         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 519         dev_info->max_rx_queues = max_rx_rings;
 520         dev_info->max_tx_queues = max_rx_rings;
 521         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 522         dev_info->hash_key_size = 40;
 523         max_vnics = bp->max_vnics;
 524
 525         /* MTU specifics */
 526         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 527         dev_info->max_mtu = BNXT_MAX_MTU;
 528
 529         /* Fast path specifics */
 530         dev_info->min_rx_bufsize = 1;
 531         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 532
 533         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 534         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 535                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 536         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 537         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 538
 539         /* *INDENT-OFF* */
 540         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 541                 .rx_thresh = {
 542                         .pthresh = 8,
 543                         .hthresh = 8,
 544                         .wthresh = 0,
 545                 },
 546                 .rx_free_thresh = 32,
 547                 /* If no descriptors available, pkts are dropped by default */
 548                 .rx_drop_en = 1,
 549         };
 550
 551         dev_info->default_txconf = (struct rte_eth_txconf) {
 552                 .tx_thresh = {
 553                         .pthresh = 32,
 554                         .hthresh = 0,
 555                         .wthresh = 0,
 556                 },
 557                 .tx_free_thresh = 32,
 558                 .tx_rs_thresh = 32,
 559         };
 560         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 561
 562         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 563         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 564         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 565         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 566         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 567
 568         /* *INDENT-ON* */
 569
 570         /*
 571          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 572          *       need further investigation.
 573          */
 574
 575         /* VMDq resources */
 576         vpool = 64; /* ETH_64_POOLS */
 577         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 578         for (i = 0; i < 4; vpool >>= 1, i++) {
 579                 if (max_vnics > vpool) {
 580                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 581                                 if (dev_info->max_rx_queues > vrxq) {
 582                                         if (vpool > vrxq)
 583                                                 vpool = vrxq;
 584                                         goto found;
 585                                 }
 586                         }
 587                         /* Not enough resources to support VMDq */
 588                         break;
 589                 }
 590         }
 591         /* Not enough resources to support VMDq */
 592         vpool = 0;
 593         vrxq = 0;
 594 found:
 595         dev_info->max_vmdq_pools = vpool;
 596         dev_info->vmdq_queue_num = vrxq;
 597
 598         dev_info->vmdq_pool_base = 0;
 599         dev_info->vmdq_queue_base = 0;
 600
 601         return 0;
 602 }
 603
 604 /* Configure the device based on the configuration provided */
 605 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 606 {
 607         struct bnxt *bp = eth_dev->data->dev_private;
 608         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 609         int rc;
 610
 611         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 612         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 613         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 614         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 615
 616         rc = is_bnxt_in_error(bp);
 617         if (rc)
 618                 return rc;
 619
 620         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 621                 rc = bnxt_hwrm_check_vf_rings(bp);
 622                 if (rc) {
 623                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 624                         return -ENOSPC;
 625                 }
 626
 627                 /* If a resource has already been allocated - in this case
 628                  * it is the async completion ring, free it. Reallocate it after
 629                  * resource reservation. This will ensure the resource counts
 630                  * are calculated correctly.
 631                  */
 632
 633                 pthread_mutex_lock(&bp->def_cp_lock);
 634
 635                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 636                         bnxt_disable_int(bp);
 637                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 638                 }
 639
 640                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 641                 if (rc) {
 642                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 643                         pthread_mutex_unlock(&bp->def_cp_lock);
 644                         return -ENOSPC;
 645                 }
 646
 647                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 648                         rc = bnxt_alloc_async_cp_ring(bp);
 649                         if (rc) {
 650                                 pthread_mutex_unlock(&bp->def_cp_lock);
 651                                 return rc;
 652                         }
 653                         bnxt_enable_int(bp);
 654                 }
 655
 656                 pthread_mutex_unlock(&bp->def_cp_lock);
 657         } else {
 658                 /* legacy driver needs to get updated values */
 659                 rc = bnxt_hwrm_func_qcaps(bp);
 660                 if (rc) {
 661                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 662                         return rc;
 663                 }
 664         }
 665
 666         /* Inherit new configurations */
 667         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 668             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 669             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 670                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 671             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 672             bp->max_stat_ctx)
 673                 goto resource_error;
 674
 675         if (BNXT_HAS_RING_GRPS(bp) &&
 676             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 677                 goto resource_error;
 678
 679         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 680             bp->max_vnics < eth_dev->data->nb_rx_queues)
 681                 goto resource_error;
 682
 683         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 684         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 685
 686         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 687                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 688         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 689
 690         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 691                 eth_dev->data->mtu =
 692                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 693                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 694                         BNXT_NUM_VLANS;
 695                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 696         }
 697         return 0;
 698
 699 resource_error:
 700         PMD_DRV_LOG(ERR,
 701                     "Insufficient resources to support requested config\n");
 702         PMD_DRV_LOG(ERR,
 703                     "Num Queues Requested: Tx %d, Rx %d\n",
 704                     eth_dev->data->nb_tx_queues,
 705                     eth_dev->data->nb_rx_queues);
 706         PMD_DRV_LOG(ERR,
 707                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 708                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 709                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 710         return -ENOSPC;
 711 }
 712
 713 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 714 {
 715         struct rte_eth_link *link = &eth_dev->data->dev_link;
 716
 717         if (link->link_status)
 718                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 719                         eth_dev->data->port_id,
 720                         (uint32_t)link->link_speed,
 721                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 722                         ("full-duplex") : ("half-duplex\n"));
 723         else
 724                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 725                         eth_dev->data->port_id);
 726 }
 727
 728 /*
 729  * Determine whether the current configuration requires support for scattered
 730  * receive; return 1 if scattered receive is required and 0 if not.
 731  */
 732 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 733 {
 734         uint16_t buf_size;
 735         int i;
 736
 737         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 738                 return 1;
 739
 740         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 741                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 742
 743                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 744                                       RTE_PKTMBUF_HEADROOM);
 745                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 746                         return 1;
 747         }
 748         return 0;
 749 }
 750
 751 static eth_rx_burst_t
 752 bnxt_receive_function(struct rte_eth_dev *eth_dev)
 753 {
 754         struct bnxt *bp = eth_dev->data->dev_private;
 755
 756 #ifdef RTE_ARCH_X86
 757 #ifndef RTE_LIBRTE_IEEE1588
 758         /*
 759          * Vector mode receive can be enabled only if scatter rx is not
 760          * in use and rx offloads are limited to VLAN stripping and
 761          * CRC stripping.
 762          */
 763         if (!eth_dev->data->scattered_rx &&
 764             !(eth_dev->data->dev_conf.rxmode.offloads &
 765               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 766                 DEV_RX_OFFLOAD_KEEP_CRC |
 767                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 768                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 769                 DEV_RX_OFFLOAD_UDP_CKSUM |
 770                 DEV_RX_OFFLOAD_TCP_CKSUM |
 771                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 772                 DEV_RX_OFFLOAD_RSS_HASH |
 773                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 774                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 775                             eth_dev->data->port_id);
 776                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
 777                 return bnxt_recv_pkts_vec;
 778         }
 779         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 780                     eth_dev->data->port_id);
 781         PMD_DRV_LOG(INFO,
 782                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 783                     eth_dev->data->port_id,
 784                     eth_dev->data->scattered_rx,
 785                     eth_dev->data->dev_conf.rxmode.offloads);
 786 #endif
 787 #endif
 788         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
 789         return bnxt_recv_pkts;
 790 }
 791
 792 static eth_tx_burst_t
 793 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 794 {
 795 #ifdef RTE_ARCH_X86
 796 #ifndef RTE_LIBRTE_IEEE1588
 797         /*
 798          * Vector mode transmit can be enabled only if not using scatter rx
 799          * or tx offloads.
 800          */
 801         if (!eth_dev->data->scattered_rx &&
 802             !eth_dev->data->dev_conf.txmode.offloads) {
 803                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 804                             eth_dev->data->port_id);
 805                 return bnxt_xmit_pkts_vec;
 806         }
 807         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 808                     eth_dev->data->port_id);
 809         PMD_DRV_LOG(INFO,
 810                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 811                     eth_dev->data->port_id,
 812                     eth_dev->data->scattered_rx,
 813                     eth_dev->data->dev_conf.txmode.offloads);
 814 #endif
 815 #endif
 816         return bnxt_xmit_pkts;
 817 }
 818
 819 static int bnxt_handle_if_change_status(struct bnxt *bp)
 820 {
 821         int rc;
 822
 823         /* Since fw has undergone a reset and lost all contexts,
 824          * set fatal flag to not issue hwrm during cleanup
 825          */
 826         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 827         bnxt_uninit_resources(bp, true);
 828
 829         /* clear fatal flag so that re-init happens */
 830         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 831         rc = bnxt_init_resources(bp, true);
 832
 833         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 834
 835         return rc;
 836 }
 837
 838 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 839 {
 840         struct bnxt *bp = eth_dev->data->dev_private;
 841         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 842         int vlan_mask = 0;
 843         int rc;
 844
 845         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
 846                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
 847                 return -EINVAL;
 848         }
 849
 850         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 851                 PMD_DRV_LOG(ERR,
 852                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 853                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 854         }
 855
 856         rc = bnxt_hwrm_if_change(bp, 1);
 857         if (!rc) {
 858                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 859                         rc = bnxt_handle_if_change_status(bp);
 860                         if (rc)
 861                                 return rc;
 862                 }
 863         }
 864         bnxt_enable_int(bp);
 865
 866         rc = bnxt_init_chip(bp);
 867         if (rc)
 868                 goto error;
 869
 870         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 871
 872         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
 873
 874         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 875                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 876         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 877                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 878         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 879         if (rc)
 880                 goto error;
 881
 882         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 883         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 884
 885         bp->flags |= BNXT_FLAG_INIT_DONE;
 886         eth_dev->data->dev_started = 1;
 887         bp->dev_stopped = 0;
 888         pthread_mutex_lock(&bp->def_cp_lock);
 889         bnxt_schedule_fw_health_check(bp);
 890         pthread_mutex_unlock(&bp->def_cp_lock);
 891         return 0;
 892
 893 error:
 894         bnxt_hwrm_if_change(bp, 0);
 895         bnxt_shutdown_nic(bp);
 896         bnxt_free_tx_mbufs(bp);
 897         bnxt_free_rx_mbufs(bp);
 898         return rc;
 899 }
 900
 901 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 902 {
 903         struct bnxt *bp = eth_dev->data->dev_private;
 904         int rc = 0;
 905
 906         if (!bp->link_info.link_up)
 907                 rc = bnxt_set_hwrm_link_config(bp, true);
 908         if (!rc)
 909                 eth_dev->data->dev_link.link_status = 1;
 910
 911         bnxt_print_link_info(eth_dev);
 912         return rc;
 913 }
 914
 915 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 916 {
 917         struct bnxt *bp = eth_dev->data->dev_private;
 918
 919         eth_dev->data->dev_link.link_status = 0;
 920         bnxt_set_hwrm_link_config(bp, false);
 921         bp->link_info.link_up = 0;
 922
 923         return 0;
 924 }
 925
 926 /* Unload the driver, release resources */
 927 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 928 {
 929         struct bnxt *bp = eth_dev->data->dev_private;
 930         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 931         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 932
 933         eth_dev->data->dev_started = 0;
 934         /* Prevent crashes when queues are still in use */
 935         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 936         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 937
 938         bnxt_disable_int(bp);
 939
 940         /* disable uio/vfio intr/eventfd mapping */
 941         rte_intr_disable(intr_handle);
 942
 943         bnxt_cancel_fw_health_check(bp);
 944
 945         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 946         if (bp->eth_dev->data->dev_started) {
 947                 /* TBD: STOP HW queues DMA */
 948                 eth_dev->data->dev_link.link_status = 0;
 949         }
 950         bnxt_dev_set_link_down_op(eth_dev);
 951
 952         /* Wait for link to be reset and the async notification to process.
 953          * During reset recovery, there is no need to wait
 954          */
 955         if (!is_bnxt_in_error(bp))
 956                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
 957
 958         /* Clean queue intr-vector mapping */
 959         rte_intr_efd_disable(intr_handle);
 960         if (intr_handle->intr_vec != NULL) {
 961                 rte_free(intr_handle->intr_vec);
 962                 intr_handle->intr_vec = NULL;
 963         }
 964
 965         bnxt_hwrm_port_clr_stats(bp);
 966         bnxt_free_tx_mbufs(bp);
 967         bnxt_free_rx_mbufs(bp);
 968         /* Process any remaining notifications in default completion queue */
 969         bnxt_int_handler(eth_dev);
 970         bnxt_shutdown_nic(bp);
 971         bnxt_hwrm_if_change(bp, 0);
 972         memset(bp->mark_table, 0, BNXT_MARK_TABLE_SZ);
 973         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
 974         bp->dev_stopped = 1;
 975         bp->rx_cosq_cnt = 0;
 976 }
 977
 978 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 979 {
 980         struct bnxt *bp = eth_dev->data->dev_private;
 981
 982         if (bp->dev_stopped == 0)
 983                 bnxt_dev_stop_op(eth_dev);
 984
 985         if (eth_dev->data->mac_addrs != NULL) {
 986                 rte_free(eth_dev->data->mac_addrs);
 987                 eth_dev->data->mac_addrs = NULL;
 988         }
 989         if (bp->grp_info != NULL) {
 990                 rte_free(bp->grp_info);
 991                 bp->grp_info = NULL;
 992         }
 993
 994         rte_free(bp->mark_table);
 995         bp->mark_table = NULL;
 996
 997         bnxt_dev_uninit(eth_dev);
 998 }
 999
1000 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1001                                     uint32_t index)
1002 {
1003         struct bnxt *bp = eth_dev->data->dev_private;
1004         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1005         struct bnxt_vnic_info *vnic;
1006         struct bnxt_filter_info *filter, *temp_filter;
1007         uint32_t i;
1008
1009         if (is_bnxt_in_error(bp))
1010                 return;
1011
1012         /*
1013          * Loop through all VNICs from the specified filter flow pools to
1014          * remove the corresponding MAC addr filter
1015          */
1016         for (i = 0; i < bp->nr_vnics; i++) {
1017                 if (!(pool_mask & (1ULL << i)))
1018                         continue;
1019
1020                 vnic = &bp->vnic_info[i];
1021                 filter = STAILQ_FIRST(&vnic->filter);
1022                 while (filter) {
1023                         temp_filter = STAILQ_NEXT(filter, next);
1024                         if (filter->mac_index == index) {
1025                                 STAILQ_REMOVE(&vnic->filter, filter,
1026                                                 bnxt_filter_info, next);
1027                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1028                                 bnxt_free_filter(bp, filter);
1029                         }
1030                         filter = temp_filter;
1031                 }
1032         }
1033 }
1034
1035 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1036                                struct rte_ether_addr *mac_addr, uint32_t index,
1037                                uint32_t pool)
1038 {
1039         struct bnxt_filter_info *filter;
1040         int rc = 0;
1041
1042         /* Attach requested MAC address to the new l2_filter */
1043         STAILQ_FOREACH(filter, &vnic->filter, next) {
1044                 if (filter->mac_index == index) {
1045                         PMD_DRV_LOG(DEBUG,
1046                                     "MAC addr already existed for pool %d\n",
1047                                     pool);
1048                         return 0;
1049                 }
1050         }
1051
1052         filter = bnxt_alloc_filter(bp);
1053         if (!filter) {
1054                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1055                 return -ENODEV;
1056         }
1057
1058         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1059          * if the MAC that's been programmed now is a different one, then,
1060          * copy that addr to filter->l2_addr
1061          */
1062         if (mac_addr)
1063                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1064         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1065
1066         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1067         if (!rc) {
1068                 filter->mac_index = index;
1069                 if (filter->mac_index == 0)
1070                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1071                 else
1072                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1073         } else {
1074                 bnxt_free_filter(bp, filter);
1075         }
1076
1077         return rc;
1078 }
1079
1080 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1081                                 struct rte_ether_addr *mac_addr,
1082                                 uint32_t index, uint32_t pool)
1083 {
1084         struct bnxt *bp = eth_dev->data->dev_private;
1085         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1086         int rc = 0;
1087
1088         rc = is_bnxt_in_error(bp);
1089         if (rc)
1090                 return rc;
1091
1092         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1093                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1094                 return -ENOTSUP;
1095         }
1096
1097         if (!vnic) {
1098                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1099                 return -EINVAL;
1100         }
1101
1102         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1103
1104         return rc;
1105 }
1106
1107 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1108                      bool exp_link_status)
1109 {
1110         int rc = 0;
1111         struct bnxt *bp = eth_dev->data->dev_private;
1112         struct rte_eth_link new;
1113         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1114                   BNXT_LINK_DOWN_WAIT_CNT;
1115
1116         rc = is_bnxt_in_error(bp);
1117         if (rc)
1118                 return rc;
1119
1120         memset(&new, 0, sizeof(new));
1121         do {
1122                 /* Retrieve link info from hardware */
1123                 rc = bnxt_get_hwrm_link_config(bp, &new);
1124                 if (rc) {
1125                         new.link_speed = ETH_LINK_SPEED_100M;
1126                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1127                         PMD_DRV_LOG(ERR,
1128                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1129                         goto out;
1130                 }
1131
1132                 if (!wait_to_complete || new.link_status == exp_link_status)
1133                         break;
1134
1135                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1136         } while (cnt--);
1137
1138 out:
1139         /* Timed out or success */
1140         if (new.link_status != eth_dev->data->dev_link.link_status ||
1141         new.link_speed != eth_dev->data->dev_link.link_speed) {
1142                 rte_eth_linkstatus_set(eth_dev, &new);
1143
1144                 _rte_eth_dev_callback_process(eth_dev,
1145                                               RTE_ETH_EVENT_INTR_LSC,
1146                                               NULL);
1147
1148                 bnxt_print_link_info(eth_dev);
1149         }
1150
1151         return rc;
1152 }
1153
1154 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1155                                int wait_to_complete)
1156 {
1157         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1158 }
1159
1160 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1161 {
1162         struct bnxt *bp = eth_dev->data->dev_private;
1163         struct bnxt_vnic_info *vnic;
1164         uint32_t old_flags;
1165         int rc;
1166
1167         rc = is_bnxt_in_error(bp);
1168         if (rc)
1169                 return rc;
1170
1171         if (bp->vnic_info == NULL)
1172                 return 0;
1173
1174         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1175
1176         old_flags = vnic->flags;
1177         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1178         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1179         if (rc != 0)
1180                 vnic->flags = old_flags;
1181
1182         return rc;
1183 }
1184
1185 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1186 {
1187         struct bnxt *bp = eth_dev->data->dev_private;
1188         struct bnxt_vnic_info *vnic;
1189         uint32_t old_flags;
1190         int rc;
1191
1192         rc = is_bnxt_in_error(bp);
1193         if (rc)
1194                 return rc;
1195
1196         if (bp->vnic_info == NULL)
1197                 return 0;
1198
1199         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1200
1201         old_flags = vnic->flags;
1202         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1203         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1204         if (rc != 0)
1205                 vnic->flags = old_flags;
1206
1207         return rc;
1208 }
1209
1210 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1211 {
1212         struct bnxt *bp = eth_dev->data->dev_private;
1213         struct bnxt_vnic_info *vnic;
1214         uint32_t old_flags;
1215         int rc;
1216
1217         rc = is_bnxt_in_error(bp);
1218         if (rc)
1219                 return rc;
1220
1221         if (bp->vnic_info == NULL)
1222                 return 0;
1223
1224         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1225
1226         old_flags = vnic->flags;
1227         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1228         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1229         if (rc != 0)
1230                 vnic->flags = old_flags;
1231
1232         return rc;
1233 }
1234
1235 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1236 {
1237         struct bnxt *bp = eth_dev->data->dev_private;
1238         struct bnxt_vnic_info *vnic;
1239         uint32_t old_flags;
1240         int rc;
1241
1242         rc = is_bnxt_in_error(bp);
1243         if (rc)
1244                 return rc;
1245
1246         if (bp->vnic_info == NULL)
1247                 return 0;
1248
1249         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1250
1251         old_flags = vnic->flags;
1252         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1253         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1254         if (rc != 0)
1255                 vnic->flags = old_flags;
1256
1257         return rc;
1258 }
1259
1260 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1261 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1262 {
1263         if (qid >= bp->rx_nr_rings)
1264                 return NULL;
1265
1266         return bp->eth_dev->data->rx_queues[qid];
1267 }
1268
1269 /* Return rxq corresponding to a given rss table ring/group ID. */
1270 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1271 {
1272         struct bnxt_rx_queue *rxq;
1273         unsigned int i;
1274
1275         if (!BNXT_HAS_RING_GRPS(bp)) {
1276                 for (i = 0; i < bp->rx_nr_rings; i++) {
1277                         rxq = bp->eth_dev->data->rx_queues[i];
1278                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1279                                 return rxq->index;
1280                 }
1281         } else {
1282                 for (i = 0; i < bp->rx_nr_rings; i++) {
1283                         if (bp->grp_info[i].fw_grp_id == fwr)
1284                                 return i;
1285                 }
1286         }
1287
1288         return INVALID_HW_RING_ID;
1289 }
1290
1291 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1292                             struct rte_eth_rss_reta_entry64 *reta_conf,
1293                             uint16_t reta_size)
1294 {
1295         struct bnxt *bp = eth_dev->data->dev_private;
1296         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1297         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1298         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1299         uint16_t idx, sft;
1300         int i, rc;
1301
1302         rc = is_bnxt_in_error(bp);
1303         if (rc)
1304                 return rc;
1305
1306         if (!vnic->rss_table)
1307                 return -EINVAL;
1308
1309         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1310                 return -EINVAL;
1311
1312         if (reta_size != tbl_size) {
1313                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1314                         "(%d) must equal the size supported by the hardware "
1315                         "(%d)\n", reta_size, tbl_size);
1316                 return -EINVAL;
1317         }
1318
1319         for (i = 0; i < reta_size; i++) {
1320                 struct bnxt_rx_queue *rxq;
1321
1322                 idx = i / RTE_RETA_GROUP_SIZE;
1323                 sft = i % RTE_RETA_GROUP_SIZE;
1324
1325                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1326                         continue;
1327
1328                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1329                 if (!rxq) {
1330                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1331                         return -EINVAL;
1332                 }
1333
1334                 if (BNXT_CHIP_THOR(bp)) {
1335                         vnic->rss_table[i * 2] =
1336                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1337                         vnic->rss_table[i * 2 + 1] =
1338                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1339                 } else {
1340                         vnic->rss_table[i] =
1341                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1342                 }
1343         }
1344
1345         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1346         return 0;
1347 }
1348
1349 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1350                               struct rte_eth_rss_reta_entry64 *reta_conf,
1351                               uint16_t reta_size)
1352 {
1353         struct bnxt *bp = eth_dev->data->dev_private;
1354         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1355         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1356         uint16_t idx, sft, i;
1357         int rc;
1358
1359         rc = is_bnxt_in_error(bp);
1360         if (rc)
1361                 return rc;
1362
1363         /* Retrieve from the default VNIC */
1364         if (!vnic)
1365                 return -EINVAL;
1366         if (!vnic->rss_table)
1367                 return -EINVAL;
1368
1369         if (reta_size != tbl_size) {
1370                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1371                         "(%d) must equal the size supported by the hardware "
1372                         "(%d)\n", reta_size, tbl_size);
1373                 return -EINVAL;
1374         }
1375
1376         for (idx = 0, i = 0; i < reta_size; i++) {
1377                 idx = i / RTE_RETA_GROUP_SIZE;
1378                 sft = i % RTE_RETA_GROUP_SIZE;
1379
1380                 if (reta_conf[idx].mask & (1ULL << sft)) {
1381                         uint16_t qid;
1382
1383                         if (BNXT_CHIP_THOR(bp))
1384                                 qid = bnxt_rss_to_qid(bp,
1385                                                       vnic->rss_table[i * 2]);
1386                         else
1387                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1388
1389                         if (qid == INVALID_HW_RING_ID) {
1390                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1391                                 return -EINVAL;
1392                         }
1393                         reta_conf[idx].reta[sft] = qid;
1394                 }
1395         }
1396
1397         return 0;
1398 }
1399
1400 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1401                                    struct rte_eth_rss_conf *rss_conf)
1402 {
1403         struct bnxt *bp = eth_dev->data->dev_private;
1404         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1405         struct bnxt_vnic_info *vnic;
1406         int rc;
1407
1408         rc = is_bnxt_in_error(bp);
1409         if (rc)
1410                 return rc;
1411
1412         /*
1413          * If RSS enablement were different than dev_configure,
1414          * then return -EINVAL
1415          */
1416         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1417                 if (!rss_conf->rss_hf)
1418                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1419         } else {
1420                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1421                         return -EINVAL;
1422         }
1423
1424         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1425         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1426
1427         /* Update the default RSS VNIC(s) */
1428         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1429         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1430
1431         /*
1432          * If hashkey is not specified, use the previously configured
1433          * hashkey
1434          */
1435         if (!rss_conf->rss_key)
1436                 goto rss_config;
1437
1438         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1439                 PMD_DRV_LOG(ERR,
1440                             "Invalid hashkey length, should be 16 bytes\n");
1441                 return -EINVAL;
1442         }
1443         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1444
1445 rss_config:
1446         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1447         return 0;
1448 }
1449
1450 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1451                                      struct rte_eth_rss_conf *rss_conf)
1452 {
1453         struct bnxt *bp = eth_dev->data->dev_private;
1454         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1455         int len, rc;
1456         uint32_t hash_types;
1457
1458         rc = is_bnxt_in_error(bp);
1459         if (rc)
1460                 return rc;
1461
1462         /* RSS configuration is the same for all VNICs */
1463         if (vnic && vnic->rss_hash_key) {
1464                 if (rss_conf->rss_key) {
1465                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1466                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1467                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1468                 }
1469
1470                 hash_types = vnic->hash_type;
1471                 rss_conf->rss_hf = 0;
1472                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1473                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1474                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1475                 }
1476                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1477                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1478                         hash_types &=
1479                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1480                 }
1481                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1482                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1483                         hash_types &=
1484                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1485                 }
1486                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1487                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1488                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1489                 }
1490                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1491                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1492                         hash_types &=
1493                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1494                 }
1495                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1496                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1497                         hash_types &=
1498                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1499                 }
1500                 if (hash_types) {
1501                         PMD_DRV_LOG(ERR,
1502                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1503                                 vnic->hash_type);
1504                         return -ENOTSUP;
1505                 }
1506         } else {
1507                 rss_conf->rss_hf = 0;
1508         }
1509         return 0;
1510 }
1511
1512 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1513                                struct rte_eth_fc_conf *fc_conf)
1514 {
1515         struct bnxt *bp = dev->data->dev_private;
1516         struct rte_eth_link link_info;
1517         int rc;
1518
1519         rc = is_bnxt_in_error(bp);
1520         if (rc)
1521                 return rc;
1522
1523         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1524         if (rc)
1525                 return rc;
1526
1527         memset(fc_conf, 0, sizeof(*fc_conf));
1528         if (bp->link_info.auto_pause)
1529                 fc_conf->autoneg = 1;
1530         switch (bp->link_info.pause) {
1531         case 0:
1532                 fc_conf->mode = RTE_FC_NONE;
1533                 break;
1534         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1535                 fc_conf->mode = RTE_FC_TX_PAUSE;
1536                 break;
1537         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1538                 fc_conf->mode = RTE_FC_RX_PAUSE;
1539                 break;
1540         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1541                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1542                 fc_conf->mode = RTE_FC_FULL;
1543                 break;
1544         }
1545         return 0;
1546 }
1547
1548 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1549                                struct rte_eth_fc_conf *fc_conf)
1550 {
1551         struct bnxt *bp = dev->data->dev_private;
1552         int rc;
1553
1554         rc = is_bnxt_in_error(bp);
1555         if (rc)
1556                 return rc;
1557
1558         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1559                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1560                 return -ENOTSUP;
1561         }
1562
1563         switch (fc_conf->mode) {
1564         case RTE_FC_NONE:
1565                 bp->link_info.auto_pause = 0;
1566                 bp->link_info.force_pause = 0;
1567                 break;
1568         case RTE_FC_RX_PAUSE:
1569                 if (fc_conf->autoneg) {
1570                         bp->link_info.auto_pause =
1571                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1572                         bp->link_info.force_pause = 0;
1573                 } else {
1574                         bp->link_info.auto_pause = 0;
1575                         bp->link_info.force_pause =
1576                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1577                 }
1578                 break;
1579         case RTE_FC_TX_PAUSE:
1580                 if (fc_conf->autoneg) {
1581                         bp->link_info.auto_pause =
1582                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1583                         bp->link_info.force_pause = 0;
1584                 } else {
1585                         bp->link_info.auto_pause = 0;
1586                         bp->link_info.force_pause =
1587                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1588                 }
1589                 break;
1590         case RTE_FC_FULL:
1591                 if (fc_conf->autoneg) {
1592                         bp->link_info.auto_pause =
1593                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1594                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1595                         bp->link_info.force_pause = 0;
1596                 } else {
1597                         bp->link_info.auto_pause = 0;
1598                         bp->link_info.force_pause =
1599                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1600                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1601                 }
1602                 break;
1603         }
1604         return bnxt_set_hwrm_link_config(bp, true);
1605 }
1606
1607 /* Add UDP tunneling port */
1608 static int
1609 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1610                          struct rte_eth_udp_tunnel *udp_tunnel)
1611 {
1612         struct bnxt *bp = eth_dev->data->dev_private;
1613         uint16_t tunnel_type = 0;
1614         int rc = 0;
1615
1616         rc = is_bnxt_in_error(bp);
1617         if (rc)
1618                 return rc;
1619
1620         switch (udp_tunnel->prot_type) {
1621         case RTE_TUNNEL_TYPE_VXLAN:
1622                 if (bp->vxlan_port_cnt) {
1623                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1624                                 udp_tunnel->udp_port);
1625                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1626                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1627                                 return -ENOSPC;
1628                         }
1629                         bp->vxlan_port_cnt++;
1630                         return 0;
1631                 }
1632                 tunnel_type =
1633                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1634                 bp->vxlan_port_cnt++;
1635                 break;
1636         case RTE_TUNNEL_TYPE_GENEVE:
1637                 if (bp->geneve_port_cnt) {
1638                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1639                                 udp_tunnel->udp_port);
1640                         if (bp->geneve_port != udp_tunnel->udp_port) {
1641                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1642                                 return -ENOSPC;
1643                         }
1644                         bp->geneve_port_cnt++;
1645                         return 0;
1646                 }
1647                 tunnel_type =
1648                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1649                 bp->geneve_port_cnt++;
1650                 break;
1651         default:
1652                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1653                 return -ENOTSUP;
1654         }
1655         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1656                                              tunnel_type);
1657         return rc;
1658 }
1659
1660 static int
1661 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1662                          struct rte_eth_udp_tunnel *udp_tunnel)
1663 {
1664         struct bnxt *bp = eth_dev->data->dev_private;
1665         uint16_t tunnel_type = 0;
1666         uint16_t port = 0;
1667         int rc = 0;
1668
1669         rc = is_bnxt_in_error(bp);
1670         if (rc)
1671                 return rc;
1672
1673         switch (udp_tunnel->prot_type) {
1674         case RTE_TUNNEL_TYPE_VXLAN:
1675                 if (!bp->vxlan_port_cnt) {
1676                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1677                         return -EINVAL;
1678                 }
1679                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1680                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1681                                 udp_tunnel->udp_port, bp->vxlan_port);
1682                         return -EINVAL;
1683                 }
1684                 if (--bp->vxlan_port_cnt)
1685                         return 0;
1686
1687                 tunnel_type =
1688                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1689                 port = bp->vxlan_fw_dst_port_id;
1690                 break;
1691         case RTE_TUNNEL_TYPE_GENEVE:
1692                 if (!bp->geneve_port_cnt) {
1693                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1694                         return -EINVAL;
1695                 }
1696                 if (bp->geneve_port != udp_tunnel->udp_port) {
1697                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1698                                 udp_tunnel->udp_port, bp->geneve_port);
1699                         return -EINVAL;
1700                 }
1701                 if (--bp->geneve_port_cnt)
1702                         return 0;
1703
1704                 tunnel_type =
1705                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1706                 port = bp->geneve_fw_dst_port_id;
1707                 break;
1708         default:
1709                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1710                 return -ENOTSUP;
1711         }
1712
1713         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1714         if (!rc) {
1715                 if (tunnel_type ==
1716                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1717                         bp->vxlan_port = 0;
1718                 if (tunnel_type ==
1719                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1720                         bp->geneve_port = 0;
1721         }
1722         return rc;
1723 }
1724
1725 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1726 {
1727         struct bnxt_filter_info *filter;
1728         struct bnxt_vnic_info *vnic;
1729         int rc = 0;
1730         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1731
1732         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1733         filter = STAILQ_FIRST(&vnic->filter);
1734         while (filter) {
1735                 /* Search for this matching MAC+VLAN filter */
1736                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1737                         /* Delete the filter */
1738                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1739                         if (rc)
1740                                 return rc;
1741                         STAILQ_REMOVE(&vnic->filter, filter,
1742                                       bnxt_filter_info, next);
1743                         bnxt_free_filter(bp, filter);
1744                         PMD_DRV_LOG(INFO,
1745                                     "Deleted vlan filter for %d\n",
1746                                     vlan_id);
1747                         return 0;
1748                 }
1749                 filter = STAILQ_NEXT(filter, next);
1750         }
1751         return -ENOENT;
1752 }
1753
1754 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1755 {
1756         struct bnxt_filter_info *filter;
1757         struct bnxt_vnic_info *vnic;
1758         int rc = 0;
1759         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1760                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1761         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1762
1763         /* Implementation notes on the use of VNIC in this command:
1764          *
1765          * By default, these filters belong to default vnic for the function.
1766          * Once these filters are set up, only destination VNIC can be modified.
1767          * If the destination VNIC is not specified in this command,
1768          * then the HWRM shall only create an l2 context id.
1769          */
1770
1771         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1772         filter = STAILQ_FIRST(&vnic->filter);
1773         /* Check if the VLAN has already been added */
1774         while (filter) {
1775                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1776                         return -EEXIST;
1777
1778                 filter = STAILQ_NEXT(filter, next);
1779         }
1780
1781         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1782          * command to create MAC+VLAN filter with the right flags, enables set.
1783          */
1784         filter = bnxt_alloc_filter(bp);
1785         if (!filter) {
1786                 PMD_DRV_LOG(ERR,
1787                             "MAC/VLAN filter alloc failed\n");
1788                 return -ENOMEM;
1789         }
1790         /* MAC + VLAN ID filter */
1791         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1792          * untagged packets are received
1793          *
1794          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1795          * packets and only the programmed vlan's packets are received
1796          */
1797         filter->l2_ivlan = vlan_id;
1798         filter->l2_ivlan_mask = 0x0FFF;
1799         filter->enables |= en;
1800         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1801
1802         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1803         if (rc) {
1804                 /* Free the newly allocated filter as we were
1805                  * not able to create the filter in hardware.
1806                  */
1807                 bnxt_free_filter(bp, filter);
1808                 return rc;
1809         }
1810
1811         filter->mac_index = 0;
1812         /* Add this new filter to the list */
1813         if (vlan_id == 0)
1814                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1815         else
1816                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1817
1818         PMD_DRV_LOG(INFO,
1819                     "Added Vlan filter for %d\n", vlan_id);
1820         return rc;
1821 }
1822
1823 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1824                 uint16_t vlan_id, int on)
1825 {
1826         struct bnxt *bp = eth_dev->data->dev_private;
1827         int rc;
1828
1829         rc = is_bnxt_in_error(bp);
1830         if (rc)
1831                 return rc;
1832
1833         /* These operations apply to ALL existing MAC/VLAN filters */
1834         if (on)
1835                 return bnxt_add_vlan_filter(bp, vlan_id);
1836         else
1837                 return bnxt_del_vlan_filter(bp, vlan_id);
1838 }
1839
1840 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1841                                     struct bnxt_vnic_info *vnic)
1842 {
1843         struct bnxt_filter_info *filter;
1844         int rc;
1845
1846         filter = STAILQ_FIRST(&vnic->filter);
1847         while (filter) {
1848                 if (filter->mac_index == 0 &&
1849                     !memcmp(filter->l2_addr, bp->mac_addr,
1850                             RTE_ETHER_ADDR_LEN)) {
1851                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1852                         if (!rc) {
1853                                 STAILQ_REMOVE(&vnic->filter, filter,
1854                                               bnxt_filter_info, next);
1855                                 bnxt_free_filter(bp, filter);
1856                         }
1857                         return rc;
1858                 }
1859                 filter = STAILQ_NEXT(filter, next);
1860         }
1861         return 0;
1862 }
1863
1864 static int
1865 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
1866 {
1867         struct bnxt_vnic_info *vnic;
1868         unsigned int i;
1869         int rc;
1870
1871         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1872         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1873                 /* Remove any VLAN filters programmed */
1874                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1875                         bnxt_del_vlan_filter(bp, i);
1876
1877                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1878                 if (rc)
1879                         return rc;
1880         } else {
1881                 /* Default filter will allow packets that match the
1882                  * dest mac. So, it has to be deleted, otherwise, we
1883                  * will endup receiving vlan packets for which the
1884                  * filter is not programmed, when hw-vlan-filter
1885                  * configuration is ON
1886                  */
1887                 bnxt_del_dflt_mac_filter(bp, vnic);
1888                 /* This filter will allow only untagged packets */
1889                 bnxt_add_vlan_filter(bp, 0);
1890         }
1891         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1892                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1893
1894         return 0;
1895 }
1896
1897 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
1898 {
1899         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
1900         unsigned int i;
1901         int rc;
1902
1903         /* Destroy vnic filters and vnic */
1904         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1905             DEV_RX_OFFLOAD_VLAN_FILTER) {
1906                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1907                         bnxt_del_vlan_filter(bp, i);
1908         }
1909         bnxt_del_dflt_mac_filter(bp, vnic);
1910
1911         rc = bnxt_hwrm_vnic_free(bp, vnic);
1912         if (rc)
1913                 return rc;
1914
1915         rte_free(vnic->fw_grp_ids);
1916         vnic->fw_grp_ids = NULL;
1917
1918         return 0;
1919 }
1920
1921 static int
1922 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
1923 {
1924         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1925         int rc;
1926
1927         /* Destroy, recreate and reconfigure the default vnic */
1928         rc = bnxt_free_one_vnic(bp, 0);
1929         if (rc)
1930                 return rc;
1931
1932         /* default vnic 0 */
1933         rc = bnxt_setup_one_vnic(bp, 0);
1934         if (rc)
1935                 return rc;
1936
1937         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1938             DEV_RX_OFFLOAD_VLAN_FILTER) {
1939                 rc = bnxt_add_vlan_filter(bp, 0);
1940                 bnxt_restore_vlan_filters(bp);
1941         } else {
1942                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1943         }
1944
1945         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1946         if (rc)
1947                 return rc;
1948
1949         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1950                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1951
1952         return rc;
1953 }
1954
1955 static int
1956 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1957 {
1958         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1959         struct bnxt *bp = dev->data->dev_private;
1960         int rc;
1961
1962         rc = is_bnxt_in_error(bp);
1963         if (rc)
1964                 return rc;
1965
1966         if (mask & ETH_VLAN_FILTER_MASK) {
1967                 /* Enable or disable VLAN filtering */
1968                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
1969                 if (rc)
1970                         return rc;
1971         }
1972
1973         if (mask & ETH_VLAN_STRIP_MASK) {
1974                 /* Enable or disable VLAN stripping */
1975                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
1976                 if (rc)
1977                         return rc;
1978         }
1979
1980         if (mask & ETH_VLAN_EXTEND_MASK) {
1981                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1982                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1983                 else
1984                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1985         }
1986
1987         return 0;
1988 }
1989
1990 static int
1991 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1992                       uint16_t tpid)
1993 {
1994         struct bnxt *bp = dev->data->dev_private;
1995         int qinq = dev->data->dev_conf.rxmode.offloads &
1996                    DEV_RX_OFFLOAD_VLAN_EXTEND;
1997
1998         if (vlan_type != ETH_VLAN_TYPE_INNER &&
1999             vlan_type != ETH_VLAN_TYPE_OUTER) {
2000                 PMD_DRV_LOG(ERR,
2001                             "Unsupported vlan type.");
2002                 return -EINVAL;
2003         }
2004         if (!qinq) {
2005                 PMD_DRV_LOG(ERR,
2006                             "QinQ not enabled. Needs to be ON as we can "
2007                             "accelerate only outer vlan\n");
2008                 return -EINVAL;
2009         }
2010
2011         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2012                 switch (tpid) {
2013                 case RTE_ETHER_TYPE_QINQ:
2014                         bp->outer_tpid_bd =
2015                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2016                                 break;
2017                 case RTE_ETHER_TYPE_VLAN:
2018                         bp->outer_tpid_bd =
2019                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2020                                 break;
2021                 case 0x9100:
2022                         bp->outer_tpid_bd =
2023                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2024                                 break;
2025                 case 0x9200:
2026                         bp->outer_tpid_bd =
2027                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2028                                 break;
2029                 case 0x9300:
2030                         bp->outer_tpid_bd =
2031                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2032                                 break;
2033                 default:
2034                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2035                         return -EINVAL;
2036                 }
2037                 bp->outer_tpid_bd |= tpid;
2038                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2039         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2040                 PMD_DRV_LOG(ERR,
2041                             "Can accelerate only outer vlan in QinQ\n");
2042                 return -EINVAL;
2043         }
2044
2045         return 0;
2046 }
2047
2048 static int
2049 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2050                              struct rte_ether_addr *addr)
2051 {
2052         struct bnxt *bp = dev->data->dev_private;
2053         /* Default Filter is tied to VNIC 0 */
2054         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2055         int rc;
2056
2057         rc = is_bnxt_in_error(bp);
2058         if (rc)
2059                 return rc;
2060
2061         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2062                 return -EPERM;
2063
2064         if (rte_is_zero_ether_addr(addr))
2065                 return -EINVAL;
2066
2067         /* Check if the requested MAC is already added */
2068         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2069                 return 0;
2070
2071         /* Destroy filter and re-create it */
2072         bnxt_del_dflt_mac_filter(bp, vnic);
2073
2074         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2075         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2076                 /* This filter will allow only untagged packets */
2077                 rc = bnxt_add_vlan_filter(bp, 0);
2078         } else {
2079                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2080         }
2081
2082         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2083         return rc;
2084 }
2085
2086 static int
2087 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2088                           struct rte_ether_addr *mc_addr_set,
2089                           uint32_t nb_mc_addr)
2090 {
2091         struct bnxt *bp = eth_dev->data->dev_private;
2092         char *mc_addr_list = (char *)mc_addr_set;
2093         struct bnxt_vnic_info *vnic;
2094         uint32_t off = 0, i = 0;
2095         int rc;
2096
2097         rc = is_bnxt_in_error(bp);
2098         if (rc)
2099                 return rc;
2100
2101         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2102
2103         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2104                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2105                 goto allmulti;
2106         }
2107
2108         /* TODO Check for Duplicate mcast addresses */
2109         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2110         for (i = 0; i < nb_mc_addr; i++) {
2111                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2112                         RTE_ETHER_ADDR_LEN);
2113                 off += RTE_ETHER_ADDR_LEN;
2114         }
2115
2116         vnic->mc_addr_cnt = i;
2117         if (vnic->mc_addr_cnt)
2118                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2119         else
2120                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2121
2122 allmulti:
2123         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2124 }
2125
2126 static int
2127 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2128 {
2129         struct bnxt *bp = dev->data->dev_private;
2130         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2131         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2132         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2133         int ret;
2134
2135         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2136                         fw_major, fw_minor, fw_updt);
2137
2138         ret += 1; /* add the size of '\0' */
2139         if (fw_size < (uint32_t)ret)
2140                 return ret;
2141         else
2142                 return 0;
2143 }
2144
2145 static void
2146 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2147         struct rte_eth_rxq_info *qinfo)
2148 {
2149         struct bnxt *bp = dev->data->dev_private;
2150         struct bnxt_rx_queue *rxq;
2151
2152         if (is_bnxt_in_error(bp))
2153                 return;
2154
2155         rxq = dev->data->rx_queues[queue_id];
2156
2157         qinfo->mp = rxq->mb_pool;
2158         qinfo->scattered_rx = dev->data->scattered_rx;
2159         qinfo->nb_desc = rxq->nb_rx_desc;
2160
2161         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2162         qinfo->conf.rx_drop_en = 0;
2163         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2164 }
2165
2166 static void
2167 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2168         struct rte_eth_txq_info *qinfo)
2169 {
2170         struct bnxt *bp = dev->data->dev_private;
2171         struct bnxt_tx_queue *txq;
2172
2173         if (is_bnxt_in_error(bp))
2174                 return;
2175
2176         txq = dev->data->tx_queues[queue_id];
2177
2178         qinfo->nb_desc = txq->nb_tx_desc;
2179
2180         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2181         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2182         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2183
2184         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2185         qinfo->conf.tx_rs_thresh = 0;
2186         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2187 }
2188
2189 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2190 {
2191         struct bnxt *bp = eth_dev->data->dev_private;
2192         uint32_t new_pkt_size;
2193         uint32_t rc = 0;
2194         uint32_t i;
2195
2196         rc = is_bnxt_in_error(bp);
2197         if (rc)
2198                 return rc;
2199
2200         /* Exit if receive queues are not configured yet */
2201         if (!eth_dev->data->nb_rx_queues)
2202                 return rc;
2203
2204         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2205                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2206
2207 #ifdef RTE_ARCH_X86
2208         /*
2209          * If vector-mode tx/rx is active, disallow any MTU change that would
2210          * require scattered receive support.
2211          */
2212         if (eth_dev->data->dev_started &&
2213             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2214              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2215             (new_pkt_size >
2216              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2217                 PMD_DRV_LOG(ERR,
2218                             "MTU change would require scattered rx support. ");
2219                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2220                 return -EINVAL;
2221         }
2222 #endif
2223
2224         if (new_mtu > RTE_ETHER_MTU) {
2225                 bp->flags |= BNXT_FLAG_JUMBO;
2226                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2227                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2228         } else {
2229                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2230                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2231                 bp->flags &= ~BNXT_FLAG_JUMBO;
2232         }
2233
2234         /* Is there a change in mtu setting? */
2235         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2236                 return rc;
2237
2238         for (i = 0; i < bp->nr_vnics; i++) {
2239                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2240                 uint16_t size = 0;
2241
2242                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2243                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2244                 if (rc)
2245                         break;
2246
2247                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2248                 size -= RTE_PKTMBUF_HEADROOM;
2249
2250                 if (size < new_mtu) {
2251                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2252                         if (rc)
2253                                 return rc;
2254                 }
2255         }
2256
2257         if (!rc)
2258                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2259
2260         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2261
2262         return rc;
2263 }
2264
2265 static int
2266 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2267 {
2268         struct bnxt *bp = dev->data->dev_private;
2269         uint16_t vlan = bp->vlan;
2270         int rc;
2271
2272         rc = is_bnxt_in_error(bp);
2273         if (rc)
2274                 return rc;
2275
2276         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2277                 PMD_DRV_LOG(ERR,
2278                         "PVID cannot be modified for this function\n");
2279                 return -ENOTSUP;
2280         }
2281         bp->vlan = on ? pvid : 0;
2282
2283         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2284         if (rc)
2285                 bp->vlan = vlan;
2286         return rc;
2287 }
2288
2289 static int
2290 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2291 {
2292         struct bnxt *bp = dev->data->dev_private;
2293         int rc;
2294
2295         rc = is_bnxt_in_error(bp);
2296         if (rc)
2297                 return rc;
2298
2299         return bnxt_hwrm_port_led_cfg(bp, true);
2300 }
2301
2302 static int
2303 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2304 {
2305         struct bnxt *bp = dev->data->dev_private;
2306         int rc;
2307
2308         rc = is_bnxt_in_error(bp);
2309         if (rc)
2310                 return rc;
2311
2312         return bnxt_hwrm_port_led_cfg(bp, false);
2313 }
2314
2315 static uint32_t
2316 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2317 {
2318         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2319         uint32_t desc = 0, raw_cons = 0, cons;
2320         struct bnxt_cp_ring_info *cpr;
2321         struct bnxt_rx_queue *rxq;
2322         struct rx_pkt_cmpl *rxcmp;
2323         int rc;
2324
2325         rc = is_bnxt_in_error(bp);
2326         if (rc)
2327                 return rc;
2328
2329         rxq = dev->data->rx_queues[rx_queue_id];
2330         cpr = rxq->cp_ring;
2331         raw_cons = cpr->cp_raw_cons;
2332
2333         while (1) {
2334                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2335                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2336                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2337
2338                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2339                         break;
2340                 } else {
2341                         raw_cons++;
2342                         desc++;
2343                 }
2344         }
2345
2346         return desc;
2347 }
2348
2349 static int
2350 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2351 {
2352         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2353         struct bnxt_rx_ring_info *rxr;
2354         struct bnxt_cp_ring_info *cpr;
2355         struct bnxt_sw_rx_bd *rx_buf;
2356         struct rx_pkt_cmpl *rxcmp;
2357         uint32_t cons, cp_cons;
2358         int rc;
2359
2360         if (!rxq)
2361                 return -EINVAL;
2362
2363         rc = is_bnxt_in_error(rxq->bp);
2364         if (rc)
2365                 return rc;
2366
2367         cpr = rxq->cp_ring;
2368         rxr = rxq->rx_ring;
2369
2370         if (offset >= rxq->nb_rx_desc)
2371                 return -EINVAL;
2372
2373         cons = RING_CMP(cpr->cp_ring_struct, offset);
2374         cp_cons = cpr->cp_raw_cons;
2375         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2376
2377         if (cons > cp_cons) {
2378                 if (CMPL_VALID(rxcmp, cpr->valid))
2379                         return RTE_ETH_RX_DESC_DONE;
2380         } else {
2381                 if (CMPL_VALID(rxcmp, !cpr->valid))
2382                         return RTE_ETH_RX_DESC_DONE;
2383         }
2384         rx_buf = &rxr->rx_buf_ring[cons];
2385         if (rx_buf->mbuf == NULL)
2386                 return RTE_ETH_RX_DESC_UNAVAIL;
2387
2388
2389         return RTE_ETH_RX_DESC_AVAIL;
2390 }
2391
2392 static int
2393 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2394 {
2395         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2396         struct bnxt_tx_ring_info *txr;
2397         struct bnxt_cp_ring_info *cpr;
2398         struct bnxt_sw_tx_bd *tx_buf;
2399         struct tx_pkt_cmpl *txcmp;
2400         uint32_t cons, cp_cons;
2401         int rc;
2402
2403         if (!txq)
2404                 return -EINVAL;
2405
2406         rc = is_bnxt_in_error(txq->bp);
2407         if (rc)
2408                 return rc;
2409
2410         cpr = txq->cp_ring;
2411         txr = txq->tx_ring;
2412
2413         if (offset >= txq->nb_tx_desc)
2414                 return -EINVAL;
2415
2416         cons = RING_CMP(cpr->cp_ring_struct, offset);
2417         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2418         cp_cons = cpr->cp_raw_cons;
2419
2420         if (cons > cp_cons) {
2421                 if (CMPL_VALID(txcmp, cpr->valid))
2422                         return RTE_ETH_TX_DESC_UNAVAIL;
2423         } else {
2424                 if (CMPL_VALID(txcmp, !cpr->valid))
2425                         return RTE_ETH_TX_DESC_UNAVAIL;
2426         }
2427         tx_buf = &txr->tx_buf_ring[cons];
2428         if (tx_buf->mbuf == NULL)
2429                 return RTE_ETH_TX_DESC_DONE;
2430
2431         return RTE_ETH_TX_DESC_FULL;
2432 }
2433
2434 static struct bnxt_filter_info *
2435 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2436                                 struct rte_eth_ethertype_filter *efilter,
2437                                 struct bnxt_vnic_info *vnic0,
2438                                 struct bnxt_vnic_info *vnic,
2439                                 int *ret)
2440 {
2441         struct bnxt_filter_info *mfilter = NULL;
2442         int match = 0;
2443         *ret = 0;
2444
2445         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2446                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2447                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2448                         " ethertype filter.", efilter->ether_type);
2449                 *ret = -EINVAL;
2450                 goto exit;
2451         }
2452         if (efilter->queue >= bp->rx_nr_rings) {
2453                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2454                 *ret = -EINVAL;
2455                 goto exit;
2456         }
2457
2458         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2459         vnic = &bp->vnic_info[efilter->queue];
2460         if (vnic == NULL) {
2461                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2462                 *ret = -EINVAL;
2463                 goto exit;
2464         }
2465
2466         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2467                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2468                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2469                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2470                              mfilter->flags ==
2471                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2472                              mfilter->ethertype == efilter->ether_type)) {
2473                                 match = 1;
2474                                 break;
2475                         }
2476                 }
2477         } else {
2478                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2479                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2480                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2481                              mfilter->ethertype == efilter->ether_type &&
2482                              mfilter->flags ==
2483                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2484                                 match = 1;
2485                                 break;
2486                         }
2487         }
2488
2489         if (match)
2490                 *ret = -EEXIST;
2491
2492 exit:
2493         return mfilter;
2494 }
2495
2496 static int
2497 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2498                         enum rte_filter_op filter_op,
2499                         void *arg)
2500 {
2501         struct bnxt *bp = dev->data->dev_private;
2502         struct rte_eth_ethertype_filter *efilter =
2503                         (struct rte_eth_ethertype_filter *)arg;
2504         struct bnxt_filter_info *bfilter, *filter1;
2505         struct bnxt_vnic_info *vnic, *vnic0;
2506         int ret;
2507
2508         if (filter_op == RTE_ETH_FILTER_NOP)
2509                 return 0;
2510
2511         if (arg == NULL) {
2512                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2513                             filter_op);
2514                 return -EINVAL;
2515         }
2516
2517         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2518         vnic = &bp->vnic_info[efilter->queue];
2519
2520         switch (filter_op) {
2521         case RTE_ETH_FILTER_ADD:
2522                 bnxt_match_and_validate_ether_filter(bp, efilter,
2523                                                         vnic0, vnic, &ret);
2524                 if (ret < 0)
2525                         return ret;
2526
2527                 bfilter = bnxt_get_unused_filter(bp);
2528                 if (bfilter == NULL) {
2529                         PMD_DRV_LOG(ERR,
2530                                 "Not enough resources for a new filter.\n");
2531                         return -ENOMEM;
2532                 }
2533                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2534                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2535                        RTE_ETHER_ADDR_LEN);
2536                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2537                        RTE_ETHER_ADDR_LEN);
2538                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2539                 bfilter->ethertype = efilter->ether_type;
2540                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2541
2542                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2543                 if (filter1 == NULL) {
2544                         ret = -EINVAL;
2545                         goto cleanup;
2546                 }
2547                 bfilter->enables |=
2548                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2549                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2550
2551                 bfilter->dst_id = vnic->fw_vnic_id;
2552
2553                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2554                         bfilter->flags =
2555                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2556                 }
2557
2558                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2559                 if (ret)
2560                         goto cleanup;
2561                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2562                 break;
2563         case RTE_ETH_FILTER_DELETE:
2564                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2565                                                         vnic0, vnic, &ret);
2566                 if (ret == -EEXIST) {
2567                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2568
2569                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2570                                       next);
2571                         bnxt_free_filter(bp, filter1);
2572                 } else if (ret == 0) {
2573                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2574                 }
2575                 break;
2576         default:
2577                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2578                 ret = -EINVAL;
2579                 goto error;
2580         }
2581         return ret;
2582 cleanup:
2583         bnxt_free_filter(bp, bfilter);
2584 error:
2585         return ret;
2586 }
2587
2588 static inline int
2589 parse_ntuple_filter(struct bnxt *bp,
2590                     struct rte_eth_ntuple_filter *nfilter,
2591                     struct bnxt_filter_info *bfilter)
2592 {
2593         uint32_t en = 0;
2594
2595         if (nfilter->queue >= bp->rx_nr_rings) {
2596                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2597                 return -EINVAL;
2598         }
2599
2600         switch (nfilter->dst_port_mask) {
2601         case UINT16_MAX:
2602                 bfilter->dst_port_mask = -1;
2603                 bfilter->dst_port = nfilter->dst_port;
2604                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2605                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2606                 break;
2607         default:
2608                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2609                 return -EINVAL;
2610         }
2611
2612         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2613         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2614
2615         switch (nfilter->proto_mask) {
2616         case UINT8_MAX:
2617                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2618                         bfilter->ip_protocol = 17;
2619                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2620                         bfilter->ip_protocol = 6;
2621                 else
2622                         return -EINVAL;
2623                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2624                 break;
2625         default:
2626                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2627                 return -EINVAL;
2628         }
2629
2630         switch (nfilter->dst_ip_mask) {
2631         case UINT32_MAX:
2632                 bfilter->dst_ipaddr_mask[0] = -1;
2633                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2634                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2635                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2636                 break;
2637         default:
2638                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2639                 return -EINVAL;
2640         }
2641
2642         switch (nfilter->src_ip_mask) {
2643         case UINT32_MAX:
2644                 bfilter->src_ipaddr_mask[0] = -1;
2645                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2646                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2647                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2648                 break;
2649         default:
2650                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2651                 return -EINVAL;
2652         }
2653
2654         switch (nfilter->src_port_mask) {
2655         case UINT16_MAX:
2656                 bfilter->src_port_mask = -1;
2657                 bfilter->src_port = nfilter->src_port;
2658                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2659                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2660                 break;
2661         default:
2662                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2663                 return -EINVAL;
2664         }
2665
2666         bfilter->enables = en;
2667         return 0;
2668 }
2669
2670 static struct bnxt_filter_info*
2671 bnxt_match_ntuple_filter(struct bnxt *bp,
2672                          struct bnxt_filter_info *bfilter,
2673                          struct bnxt_vnic_info **mvnic)
2674 {
2675         struct bnxt_filter_info *mfilter = NULL;
2676         int i;
2677
2678         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2679                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2680                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2681                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2682                             bfilter->src_ipaddr_mask[0] ==
2683                             mfilter->src_ipaddr_mask[0] &&
2684                             bfilter->src_port == mfilter->src_port &&
2685                             bfilter->src_port_mask == mfilter->src_port_mask &&
2686                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2687                             bfilter->dst_ipaddr_mask[0] ==
2688                             mfilter->dst_ipaddr_mask[0] &&
2689                             bfilter->dst_port == mfilter->dst_port &&
2690                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2691                             bfilter->flags == mfilter->flags &&
2692                             bfilter->enables == mfilter->enables) {
2693                                 if (mvnic)
2694                                         *mvnic = vnic;
2695                                 return mfilter;
2696                         }
2697                 }
2698         }
2699         return NULL;
2700 }
2701
2702 static int
2703 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2704                        struct rte_eth_ntuple_filter *nfilter,
2705                        enum rte_filter_op filter_op)
2706 {
2707         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2708         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2709         int ret;
2710
2711         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2712                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2713                 return -EINVAL;
2714         }
2715
2716         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2717                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2718                 return -EINVAL;
2719         }
2720
2721         bfilter = bnxt_get_unused_filter(bp);
2722         if (bfilter == NULL) {
2723                 PMD_DRV_LOG(ERR,
2724                         "Not enough resources for a new filter.\n");
2725                 return -ENOMEM;
2726         }
2727         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2728         if (ret < 0)
2729                 goto free_filter;
2730
2731         vnic = &bp->vnic_info[nfilter->queue];
2732         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2733         filter1 = STAILQ_FIRST(&vnic0->filter);
2734         if (filter1 == NULL) {
2735                 ret = -EINVAL;
2736                 goto free_filter;
2737         }
2738
2739         bfilter->dst_id = vnic->fw_vnic_id;
2740         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2741         bfilter->enables |=
2742                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2743         bfilter->ethertype = 0x800;
2744         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2745
2746         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2747
2748         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2749             bfilter->dst_id == mfilter->dst_id) {
2750                 PMD_DRV_LOG(ERR, "filter exists.\n");
2751                 ret = -EEXIST;
2752                 goto free_filter;
2753         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2754                    bfilter->dst_id != mfilter->dst_id) {
2755                 mfilter->dst_id = vnic->fw_vnic_id;
2756                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2757                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2758                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2759                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2760                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2761                 goto free_filter;
2762         }
2763         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2764                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2765                 ret = -ENOENT;
2766                 goto free_filter;
2767         }
2768
2769         if (filter_op == RTE_ETH_FILTER_ADD) {
2770                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2771                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2772                 if (ret)
2773                         goto free_filter;
2774                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2775         } else {
2776                 if (mfilter == NULL) {
2777                         /* This should not happen. But for Coverity! */
2778                         ret = -ENOENT;
2779                         goto free_filter;
2780                 }
2781                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2782
2783                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2784                 bnxt_free_filter(bp, mfilter);
2785                 bnxt_free_filter(bp, bfilter);
2786         }
2787
2788         return 0;
2789 free_filter:
2790         bnxt_free_filter(bp, bfilter);
2791         return ret;
2792 }
2793
2794 static int
2795 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2796                         enum rte_filter_op filter_op,
2797                         void *arg)
2798 {
2799         struct bnxt *bp = dev->data->dev_private;
2800         int ret;
2801
2802         if (filter_op == RTE_ETH_FILTER_NOP)
2803                 return 0;
2804
2805         if (arg == NULL) {
2806                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2807                             filter_op);
2808                 return -EINVAL;
2809         }
2810
2811         switch (filter_op) {
2812         case RTE_ETH_FILTER_ADD:
2813                 ret = bnxt_cfg_ntuple_filter(bp,
2814                         (struct rte_eth_ntuple_filter *)arg,
2815                         filter_op);
2816                 break;
2817         case RTE_ETH_FILTER_DELETE:
2818                 ret = bnxt_cfg_ntuple_filter(bp,
2819                         (struct rte_eth_ntuple_filter *)arg,
2820                         filter_op);
2821                 break;
2822         default:
2823                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2824                 ret = -EINVAL;
2825                 break;
2826         }
2827         return ret;
2828 }
2829
2830 static int
2831 bnxt_parse_fdir_filter(struct bnxt *bp,
2832                        struct rte_eth_fdir_filter *fdir,
2833                        struct bnxt_filter_info *filter)
2834 {
2835         enum rte_fdir_mode fdir_mode =
2836                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2837         struct bnxt_vnic_info *vnic0, *vnic;
2838         struct bnxt_filter_info *filter1;
2839         uint32_t en = 0;
2840         int i;
2841
2842         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2843                 return -EINVAL;
2844
2845         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2846         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2847
2848         switch (fdir->input.flow_type) {
2849         case RTE_ETH_FLOW_IPV4:
2850         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2851                 /* FALLTHROUGH */
2852                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2853                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2854                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2855                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2856                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2857                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2858                 filter->ip_addr_type =
2859                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2860                 filter->src_ipaddr_mask[0] = 0xffffffff;
2861                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2862                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2863                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2864                 filter->ethertype = 0x800;
2865                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2866                 break;
2867         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2868                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2869                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2870                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2871                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2872                 filter->dst_port_mask = 0xffff;
2873                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2874                 filter->src_port_mask = 0xffff;
2875                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2876                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2877                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2878                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2879                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2880                 filter->ip_protocol = 6;
2881                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2882                 filter->ip_addr_type =
2883                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2884                 filter->src_ipaddr_mask[0] = 0xffffffff;
2885                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2886                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2887                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2888                 filter->ethertype = 0x800;
2889                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2890                 break;
2891         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2892                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2893                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2894                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2895                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2896                 filter->dst_port_mask = 0xffff;
2897                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2898                 filter->src_port_mask = 0xffff;
2899                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2900                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2901                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2902                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2903                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2904                 filter->ip_protocol = 17;
2905                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2906                 filter->ip_addr_type =
2907                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2908                 filter->src_ipaddr_mask[0] = 0xffffffff;
2909                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2910                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2911                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2912                 filter->ethertype = 0x800;
2913                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2914                 break;
2915         case RTE_ETH_FLOW_IPV6:
2916         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2917                 /* FALLTHROUGH */
2918                 filter->ip_addr_type =
2919                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2920                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2921                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2922                 rte_memcpy(filter->src_ipaddr,
2923                            fdir->input.flow.ipv6_flow.src_ip, 16);
2924                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2925                 rte_memcpy(filter->dst_ipaddr,
2926                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2927                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2928                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2929                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2930                 memset(filter->src_ipaddr_mask, 0xff, 16);
2931                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2932                 filter->ethertype = 0x86dd;
2933                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2934                 break;
2935         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2936                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2937                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2938                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2939                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2940                 filter->dst_port_mask = 0xffff;
2941                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2942                 filter->src_port_mask = 0xffff;
2943                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2944                 filter->ip_addr_type =
2945                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2946                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2947                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2948                 rte_memcpy(filter->src_ipaddr,
2949                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2950                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2951                 rte_memcpy(filter->dst_ipaddr,
2952                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2953                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2954                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2955                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2956                 memset(filter->src_ipaddr_mask, 0xff, 16);
2957                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2958                 filter->ethertype = 0x86dd;
2959                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2960                 break;
2961         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2962                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2963                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2964                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2965                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2966                 filter->dst_port_mask = 0xffff;
2967                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2968                 filter->src_port_mask = 0xffff;
2969                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2970                 filter->ip_addr_type =
2971                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2972                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2973                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2974                 rte_memcpy(filter->src_ipaddr,
2975                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2976                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2977                 rte_memcpy(filter->dst_ipaddr,
2978                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2979                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2980                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2981                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2982                 memset(filter->src_ipaddr_mask, 0xff, 16);
2983                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2984                 filter->ethertype = 0x86dd;
2985                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2986                 break;
2987         case RTE_ETH_FLOW_L2_PAYLOAD:
2988                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2989                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2990                 break;
2991         case RTE_ETH_FLOW_VXLAN:
2992                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2993                         return -EINVAL;
2994                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2995                 filter->tunnel_type =
2996                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2997                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2998                 break;
2999         case RTE_ETH_FLOW_NVGRE:
3000                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3001                         return -EINVAL;
3002                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3003                 filter->tunnel_type =
3004                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3005                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3006                 break;
3007         case RTE_ETH_FLOW_UNKNOWN:
3008         case RTE_ETH_FLOW_RAW:
3009         case RTE_ETH_FLOW_FRAG_IPV4:
3010         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3011         case RTE_ETH_FLOW_FRAG_IPV6:
3012         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3013         case RTE_ETH_FLOW_IPV6_EX:
3014         case RTE_ETH_FLOW_IPV6_TCP_EX:
3015         case RTE_ETH_FLOW_IPV6_UDP_EX:
3016         case RTE_ETH_FLOW_GENEVE:
3017                 /* FALLTHROUGH */
3018         default:
3019                 return -EINVAL;
3020         }
3021
3022         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3023         vnic = &bp->vnic_info[fdir->action.rx_queue];
3024         if (vnic == NULL) {
3025                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3026                 return -EINVAL;
3027         }
3028
3029         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3030                 rte_memcpy(filter->dst_macaddr,
3031                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3032                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3033         }
3034
3035         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3036                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3037                 filter1 = STAILQ_FIRST(&vnic0->filter);
3038                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3039         } else {
3040                 filter->dst_id = vnic->fw_vnic_id;
3041                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3042                         if (filter->dst_macaddr[i] == 0x00)
3043                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3044                         else
3045                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3046         }
3047
3048         if (filter1 == NULL)
3049                 return -EINVAL;
3050
3051         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3052         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3053
3054         filter->enables = en;
3055
3056         return 0;
3057 }
3058
3059 static struct bnxt_filter_info *
3060 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3061                 struct bnxt_vnic_info **mvnic)
3062 {
3063         struct bnxt_filter_info *mf = NULL;
3064         int i;
3065
3066         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3067                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3068
3069                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3070                         if (mf->filter_type == nf->filter_type &&
3071                             mf->flags == nf->flags &&
3072                             mf->src_port == nf->src_port &&
3073                             mf->src_port_mask == nf->src_port_mask &&
3074                             mf->dst_port == nf->dst_port &&
3075                             mf->dst_port_mask == nf->dst_port_mask &&
3076                             mf->ip_protocol == nf->ip_protocol &&
3077                             mf->ip_addr_type == nf->ip_addr_type &&
3078                             mf->ethertype == nf->ethertype &&
3079                             mf->vni == nf->vni &&
3080                             mf->tunnel_type == nf->tunnel_type &&
3081                             mf->l2_ovlan == nf->l2_ovlan &&
3082                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3083                             mf->l2_ivlan == nf->l2_ivlan &&
3084                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3085                             !memcmp(mf->l2_addr, nf->l2_addr,
3086                                     RTE_ETHER_ADDR_LEN) &&
3087                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3088                                     RTE_ETHER_ADDR_LEN) &&
3089                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3090                                     RTE_ETHER_ADDR_LEN) &&
3091                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3092                                     RTE_ETHER_ADDR_LEN) &&
3093                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3094                                     sizeof(nf->src_ipaddr)) &&
3095                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3096                                     sizeof(nf->src_ipaddr_mask)) &&
3097                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3098                                     sizeof(nf->dst_ipaddr)) &&
3099                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3100                                     sizeof(nf->dst_ipaddr_mask))) {
3101                                 if (mvnic)
3102                                         *mvnic = vnic;
3103                                 return mf;
3104                         }
3105                 }
3106         }
3107         return NULL;
3108 }
3109
3110 static int
3111 bnxt_fdir_filter(struct rte_eth_dev *dev,
3112                  enum rte_filter_op filter_op,
3113                  void *arg)
3114 {
3115         struct bnxt *bp = dev->data->dev_private;
3116         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3117         struct bnxt_filter_info *filter, *match;
3118         struct bnxt_vnic_info *vnic, *mvnic;
3119         int ret = 0, i;
3120
3121         if (filter_op == RTE_ETH_FILTER_NOP)
3122                 return 0;
3123
3124         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3125                 return -EINVAL;
3126
3127         switch (filter_op) {
3128         case RTE_ETH_FILTER_ADD:
3129         case RTE_ETH_FILTER_DELETE:
3130                 /* FALLTHROUGH */
3131                 filter = bnxt_get_unused_filter(bp);
3132                 if (filter == NULL) {
3133                         PMD_DRV_LOG(ERR,
3134                                 "Not enough resources for a new flow.\n");
3135                         return -ENOMEM;
3136                 }
3137
3138                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3139                 if (ret != 0)
3140                         goto free_filter;
3141                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3142
3143                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3144                         vnic = &bp->vnic_info[0];
3145                 else
3146                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3147
3148                 match = bnxt_match_fdir(bp, filter, &mvnic);
3149                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3150                         if (match->dst_id == vnic->fw_vnic_id) {
3151                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3152                                 ret = -EEXIST;
3153                                 goto free_filter;
3154                         } else {
3155                                 match->dst_id = vnic->fw_vnic_id;
3156                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3157                                                                   match->dst_id,
3158                                                                   match);
3159                                 STAILQ_REMOVE(&mvnic->filter, match,
3160                                               bnxt_filter_info, next);
3161                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3162                                 PMD_DRV_LOG(ERR,
3163                                         "Filter with matching pattern exist\n");
3164                                 PMD_DRV_LOG(ERR,
3165                                         "Updated it to new destination q\n");
3166                                 goto free_filter;
3167                         }
3168                 }
3169                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3170                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3171                         ret = -ENOENT;
3172                         goto free_filter;
3173                 }
3174
3175                 if (filter_op == RTE_ETH_FILTER_ADD) {
3176                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3177                                                           filter->dst_id,
3178                                                           filter);
3179                         if (ret)
3180                                 goto free_filter;
3181                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3182                 } else {
3183                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3184                         STAILQ_REMOVE(&vnic->filter, match,
3185                                       bnxt_filter_info, next);
3186                         bnxt_free_filter(bp, match);
3187                         bnxt_free_filter(bp, filter);
3188                 }
3189                 break;
3190         case RTE_ETH_FILTER_FLUSH:
3191                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3192                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3193
3194                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3195                                 if (filter->filter_type ==
3196                                     HWRM_CFA_NTUPLE_FILTER) {
3197                                         ret =
3198                                         bnxt_hwrm_clear_ntuple_filter(bp,
3199                                                                       filter);
3200                                         STAILQ_REMOVE(&vnic->filter, filter,
3201                                                       bnxt_filter_info, next);
3202                                 }
3203                         }
3204                 }
3205                 return ret;
3206         case RTE_ETH_FILTER_UPDATE:
3207         case RTE_ETH_FILTER_STATS:
3208         case RTE_ETH_FILTER_INFO:
3209                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3210                 break;
3211         default:
3212                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3213                 ret = -EINVAL;
3214                 break;
3215         }
3216         return ret;
3217
3218 free_filter:
3219         bnxt_free_filter(bp, filter);
3220         return ret;
3221 }
3222
3223 static int
3224 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3225                     enum rte_filter_type filter_type,
3226                     enum rte_filter_op filter_op, void *arg)
3227 {
3228         int ret = 0;
3229
3230         ret = is_bnxt_in_error(dev->data->dev_private);
3231         if (ret)
3232                 return ret;
3233
3234         switch (filter_type) {
3235         case RTE_ETH_FILTER_TUNNEL:
3236                 PMD_DRV_LOG(ERR,
3237                         "filter type: %d: To be implemented\n", filter_type);
3238                 break;
3239         case RTE_ETH_FILTER_FDIR:
3240                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3241                 break;
3242         case RTE_ETH_FILTER_NTUPLE:
3243                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3244                 break;
3245         case RTE_ETH_FILTER_ETHERTYPE:
3246                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3247                 break;
3248         case RTE_ETH_FILTER_GENERIC:
3249                 if (filter_op != RTE_ETH_FILTER_GET)
3250                         return -EINVAL;
3251                 *(const void **)arg = &bnxt_flow_ops;
3252                 break;
3253         default:
3254                 PMD_DRV_LOG(ERR,
3255                         "Filter type (%d) not supported", filter_type);
3256                 ret = -EINVAL;
3257                 break;
3258         }
3259         return ret;
3260 }
3261
3262 static const uint32_t *
3263 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3264 {
3265         static const uint32_t ptypes[] = {
3266                 RTE_PTYPE_L2_ETHER_VLAN,
3267                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3268                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3269                 RTE_PTYPE_L4_ICMP,
3270                 RTE_PTYPE_L4_TCP,
3271                 RTE_PTYPE_L4_UDP,
3272                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3273                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3274                 RTE_PTYPE_INNER_L4_ICMP,
3275                 RTE_PTYPE_INNER_L4_TCP,
3276                 RTE_PTYPE_INNER_L4_UDP,
3277                 RTE_PTYPE_UNKNOWN
3278         };
3279
3280         if (!dev->rx_pkt_burst)
3281                 return NULL;
3282
3283         return ptypes;
3284 }
3285
3286 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3287                          int reg_win)
3288 {
3289         uint32_t reg_base = *reg_arr & 0xfffff000;
3290         uint32_t win_off;
3291         int i;
3292
3293         for (i = 0; i < count; i++) {
3294                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3295                         return -ERANGE;
3296         }
3297         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3298         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3299         return 0;
3300 }
3301
3302 static int bnxt_map_ptp_regs(struct bnxt *bp)
3303 {
3304         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3305         uint32_t *reg_arr;
3306         int rc, i;
3307
3308         reg_arr = ptp->rx_regs;
3309         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3310         if (rc)
3311                 return rc;
3312
3313         reg_arr = ptp->tx_regs;
3314         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3315         if (rc)
3316                 return rc;
3317
3318         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3319                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3320
3321         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3322                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3323
3324         return 0;
3325 }
3326
3327 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3328 {
3329         rte_write32(0, (uint8_t *)bp->bar0 +
3330                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3331         rte_write32(0, (uint8_t *)bp->bar0 +
3332                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3333 }
3334
3335 static uint64_t bnxt_cc_read(struct bnxt *bp)
3336 {
3337         uint64_t ns;
3338
3339         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3340                               BNXT_GRCPF_REG_SYNC_TIME));
3341         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3342                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3343         return ns;
3344 }
3345
3346 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3347 {
3348         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3349         uint32_t fifo;
3350
3351         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3352                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3353         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3354                 return -EAGAIN;
3355
3356         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3357                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3358         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3359                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3360         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3361                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3362
3363         return 0;
3364 }
3365
3366 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3367 {
3368         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3369         struct bnxt_pf_info *pf = &bp->pf;
3370         uint16_t port_id;
3371         uint32_t fifo;
3372
3373         if (!ptp)
3374                 return -ENODEV;
3375
3376         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3377                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3378         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3379                 return -EAGAIN;
3380
3381         port_id = pf->port_id;
3382         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3383                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3384
3385         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3386                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3387         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3388 /*              bnxt_clr_rx_ts(bp);       TBD  */
3389                 return -EBUSY;
3390         }
3391
3392         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3393                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3394         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3395                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3396
3397         return 0;
3398 }
3399
3400 static int
3401 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3402 {
3403         uint64_t ns;
3404         struct bnxt *bp = dev->data->dev_private;
3405         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3406
3407         if (!ptp)
3408                 return 0;
3409
3410         ns = rte_timespec_to_ns(ts);
3411         /* Set the timecounters to a new value. */
3412         ptp->tc.nsec = ns;
3413
3414         return 0;
3415 }
3416
3417 static int
3418 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3419 {
3420         struct bnxt *bp = dev->data->dev_private;
3421         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3422         uint64_t ns, systime_cycles = 0;
3423         int rc = 0;
3424
3425         if (!ptp)
3426                 return 0;
3427
3428         if (BNXT_CHIP_THOR(bp))
3429                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3430                                              &systime_cycles);
3431         else
3432                 systime_cycles = bnxt_cc_read(bp);
3433
3434         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3435         *ts = rte_ns_to_timespec(ns);
3436
3437         return rc;
3438 }
3439 static int
3440 bnxt_timesync_enable(struct rte_eth_dev *dev)
3441 {
3442         struct bnxt *bp = dev->data->dev_private;
3443         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3444         uint32_t shift = 0;
3445         int rc;
3446
3447         if (!ptp)
3448                 return 0;
3449
3450         ptp->rx_filter = 1;
3451         ptp->tx_tstamp_en = 1;
3452         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3453
3454         rc = bnxt_hwrm_ptp_cfg(bp);
3455         if (rc)
3456                 return rc;
3457
3458         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3459         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3460         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3461
3462         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3463         ptp->tc.cc_shift = shift;
3464         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3465
3466         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3467         ptp->rx_tstamp_tc.cc_shift = shift;
3468         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3469
3470         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3471         ptp->tx_tstamp_tc.cc_shift = shift;
3472         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3473
3474         if (!BNXT_CHIP_THOR(bp))
3475                 bnxt_map_ptp_regs(bp);
3476
3477         return 0;
3478 }
3479
3480 static int
3481 bnxt_timesync_disable(struct rte_eth_dev *dev)
3482 {
3483         struct bnxt *bp = dev->data->dev_private;
3484         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3485
3486         if (!ptp)
3487                 return 0;
3488
3489         ptp->rx_filter = 0;
3490         ptp->tx_tstamp_en = 0;
3491         ptp->rxctl = 0;
3492
3493         bnxt_hwrm_ptp_cfg(bp);
3494
3495         if (!BNXT_CHIP_THOR(bp))
3496                 bnxt_unmap_ptp_regs(bp);
3497
3498         return 0;
3499 }
3500
3501 static int
3502 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3503                                  struct timespec *timestamp,
3504                                  uint32_t flags __rte_unused)
3505 {
3506         struct bnxt *bp = dev->data->dev_private;
3507         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3508         uint64_t rx_tstamp_cycles = 0;
3509         uint64_t ns;
3510
3511         if (!ptp)
3512                 return 0;
3513
3514         if (BNXT_CHIP_THOR(bp))
3515                 rx_tstamp_cycles = ptp->rx_timestamp;
3516         else
3517                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3518
3519         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3520         *timestamp = rte_ns_to_timespec(ns);
3521         return  0;
3522 }
3523
3524 static int
3525 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3526                                  struct timespec *timestamp)
3527 {
3528         struct bnxt *bp = dev->data->dev_private;
3529         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3530         uint64_t tx_tstamp_cycles = 0;
3531         uint64_t ns;
3532         int rc = 0;
3533
3534         if (!ptp)
3535                 return 0;
3536
3537         if (BNXT_CHIP_THOR(bp))
3538                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3539                                              &tx_tstamp_cycles);
3540         else
3541                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3542
3543         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3544         *timestamp = rte_ns_to_timespec(ns);
3545
3546         return rc;
3547 }
3548
3549 static int
3550 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3551 {
3552         struct bnxt *bp = dev->data->dev_private;
3553         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3554
3555         if (!ptp)
3556                 return 0;
3557
3558         ptp->tc.nsec += delta;
3559
3560         return 0;
3561 }
3562
3563 static int
3564 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3565 {
3566         struct bnxt *bp = dev->data->dev_private;
3567         int rc;
3568         uint32_t dir_entries;
3569         uint32_t entry_length;
3570
3571         rc = is_bnxt_in_error(bp);
3572         if (rc)
3573                 return rc;
3574
3575         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3576                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3577                 bp->pdev->addr.devid, bp->pdev->addr.function);
3578
3579         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3580         if (rc != 0)
3581                 return rc;
3582
3583         return dir_entries * entry_length;
3584 }
3585
3586 static int
3587 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3588                 struct rte_dev_eeprom_info *in_eeprom)
3589 {
3590         struct bnxt *bp = dev->data->dev_private;
3591         uint32_t index;
3592         uint32_t offset;
3593         int rc;
3594
3595         rc = is_bnxt_in_error(bp);
3596         if (rc)
3597                 return rc;
3598
3599         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3600                 "len = %d\n", bp->pdev->addr.domain,
3601                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3602                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3603
3604         if (in_eeprom->offset == 0) /* special offset value to get directory */
3605                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3606                                                 in_eeprom->data);
3607
3608         index = in_eeprom->offset >> 24;
3609         offset = in_eeprom->offset & 0xffffff;
3610
3611         if (index != 0)
3612                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3613                                            in_eeprom->length, in_eeprom->data);
3614
3615         return 0;
3616 }
3617
3618 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3619 {
3620         switch (dir_type) {
3621         case BNX_DIR_TYPE_CHIMP_PATCH:
3622         case BNX_DIR_TYPE_BOOTCODE:
3623         case BNX_DIR_TYPE_BOOTCODE_2:
3624         case BNX_DIR_TYPE_APE_FW:
3625         case BNX_DIR_TYPE_APE_PATCH:
3626         case BNX_DIR_TYPE_KONG_FW:
3627         case BNX_DIR_TYPE_KONG_PATCH:
3628         case BNX_DIR_TYPE_BONO_FW:
3629         case BNX_DIR_TYPE_BONO_PATCH:
3630                 /* FALLTHROUGH */
3631                 return true;
3632         }
3633
3634         return false;
3635 }
3636
3637 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3638 {
3639         switch (dir_type) {
3640         case BNX_DIR_TYPE_AVS:
3641         case BNX_DIR_TYPE_EXP_ROM_MBA:
3642         case BNX_DIR_TYPE_PCIE:
3643         case BNX_DIR_TYPE_TSCF_UCODE:
3644         case BNX_DIR_TYPE_EXT_PHY:
3645         case BNX_DIR_TYPE_CCM:
3646         case BNX_DIR_TYPE_ISCSI_BOOT:
3647         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3648         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3649                 /* FALLTHROUGH */
3650                 return true;
3651         }
3652
3653         return false;
3654 }
3655
3656 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3657 {
3658         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3659                 bnxt_dir_type_is_other_exec_format(dir_type);
3660 }
3661
3662 static int
3663 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3664                 struct rte_dev_eeprom_info *in_eeprom)
3665 {
3666         struct bnxt *bp = dev->data->dev_private;
3667         uint8_t index, dir_op;
3668         uint16_t type, ext, ordinal, attr;
3669         int rc;
3670
3671         rc = is_bnxt_in_error(bp);
3672         if (rc)
3673                 return rc;
3674
3675         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3676                 "len = %d\n", bp->pdev->addr.domain,
3677                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3678                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3679
3680         if (!BNXT_PF(bp)) {
3681                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3682                 return -EINVAL;
3683         }
3684
3685         type = in_eeprom->magic >> 16;
3686
3687         if (type == 0xffff) { /* special value for directory operations */
3688                 index = in_eeprom->magic & 0xff;
3689                 dir_op = in_eeprom->magic >> 8;
3690                 if (index == 0)
3691                         return -EINVAL;
3692                 switch (dir_op) {
3693                 case 0x0e: /* erase */
3694                         if (in_eeprom->offset != ~in_eeprom->magic)
3695                                 return -EINVAL;
3696                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3697                 default:
3698                         return -EINVAL;
3699                 }
3700         }
3701
3702         /* Create or re-write an NVM item: */
3703         if (bnxt_dir_type_is_executable(type) == true)
3704                 return -EOPNOTSUPP;
3705         ext = in_eeprom->magic & 0xffff;
3706         ordinal = in_eeprom->offset >> 16;
3707         attr = in_eeprom->offset & 0xffff;
3708
3709         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3710                                      in_eeprom->data, in_eeprom->length);
3711 }
3712
3713 /*
3714  * Initialization
3715  */
3716
3717 static const struct eth_dev_ops bnxt_dev_ops = {
3718         .dev_infos_get = bnxt_dev_info_get_op,
3719         .dev_close = bnxt_dev_close_op,
3720         .dev_configure = bnxt_dev_configure_op,
3721         .dev_start = bnxt_dev_start_op,
3722         .dev_stop = bnxt_dev_stop_op,
3723         .dev_set_link_up = bnxt_dev_set_link_up_op,
3724         .dev_set_link_down = bnxt_dev_set_link_down_op,
3725         .stats_get = bnxt_stats_get_op,
3726         .stats_reset = bnxt_stats_reset_op,
3727         .rx_queue_setup = bnxt_rx_queue_setup_op,
3728         .rx_queue_release = bnxt_rx_queue_release_op,
3729         .tx_queue_setup = bnxt_tx_queue_setup_op,
3730         .tx_queue_release = bnxt_tx_queue_release_op,
3731         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3732         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3733         .reta_update = bnxt_reta_update_op,
3734         .reta_query = bnxt_reta_query_op,
3735         .rss_hash_update = bnxt_rss_hash_update_op,
3736         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3737         .link_update = bnxt_link_update_op,
3738         .promiscuous_enable = bnxt_promiscuous_enable_op,
3739         .promiscuous_disable = bnxt_promiscuous_disable_op,
3740         .allmulticast_enable = bnxt_allmulticast_enable_op,
3741         .allmulticast_disable = bnxt_allmulticast_disable_op,
3742         .mac_addr_add = bnxt_mac_addr_add_op,
3743         .mac_addr_remove = bnxt_mac_addr_remove_op,
3744         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3745         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3746         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3747         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3748         .vlan_filter_set = bnxt_vlan_filter_set_op,
3749         .vlan_offload_set = bnxt_vlan_offload_set_op,
3750         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3751         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3752         .mtu_set = bnxt_mtu_set_op,
3753         .mac_addr_set = bnxt_set_default_mac_addr_op,
3754         .xstats_get = bnxt_dev_xstats_get_op,
3755         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3756         .xstats_reset = bnxt_dev_xstats_reset_op,
3757         .fw_version_get = bnxt_fw_version_get,
3758         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3759         .rxq_info_get = bnxt_rxq_info_get_op,
3760         .txq_info_get = bnxt_txq_info_get_op,
3761         .dev_led_on = bnxt_dev_led_on_op,
3762         .dev_led_off = bnxt_dev_led_off_op,
3763         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3764         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3765         .rx_queue_count = bnxt_rx_queue_count_op,
3766         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3767         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3768         .rx_queue_start = bnxt_rx_queue_start,
3769         .rx_queue_stop = bnxt_rx_queue_stop,
3770         .tx_queue_start = bnxt_tx_queue_start,
3771         .tx_queue_stop = bnxt_tx_queue_stop,
3772         .filter_ctrl = bnxt_filter_ctrl_op,
3773         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3774         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3775         .get_eeprom           = bnxt_get_eeprom_op,
3776         .set_eeprom           = bnxt_set_eeprom_op,
3777         .timesync_enable      = bnxt_timesync_enable,
3778         .timesync_disable     = bnxt_timesync_disable,
3779         .timesync_read_time   = bnxt_timesync_read_time,
3780         .timesync_write_time   = bnxt_timesync_write_time,
3781         .timesync_adjust_time = bnxt_timesync_adjust_time,
3782         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3783         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3784 };
3785
3786 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3787 {
3788         uint32_t offset;
3789
3790         /* Only pre-map the reset GRC registers using window 3 */
3791         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3792                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3793
3794         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3795
3796         return offset;
3797 }
3798
3799 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3800 {
3801         struct bnxt_error_recovery_info *info = bp->recovery_info;
3802         uint32_t reg_base = 0xffffffff;
3803         int i;
3804
3805         /* Only pre-map the monitoring GRC registers using window 2 */
3806         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3807                 uint32_t reg = info->status_regs[i];
3808
3809                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3810                         continue;
3811
3812                 if (reg_base == 0xffffffff)
3813                         reg_base = reg & 0xfffff000;
3814                 if ((reg & 0xfffff000) != reg_base)
3815                         return -ERANGE;
3816
3817                 /* Use mask 0xffc as the Lower 2 bits indicates
3818                  * address space location
3819                  */
3820                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3821                                                 (reg & 0xffc);
3822         }
3823
3824         if (reg_base == 0xffffffff)
3825                 return 0;
3826
3827         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3828                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3829
3830         return 0;
3831 }
3832
3833 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3834 {
3835         struct bnxt_error_recovery_info *info = bp->recovery_info;
3836         uint32_t delay = info->delay_after_reset[index];
3837         uint32_t val = info->reset_reg_val[index];
3838         uint32_t reg = info->reset_reg[index];
3839         uint32_t type, offset;
3840
3841         type = BNXT_FW_STATUS_REG_TYPE(reg);
3842         offset = BNXT_FW_STATUS_REG_OFF(reg);
3843
3844         switch (type) {
3845         case BNXT_FW_STATUS_REG_TYPE_CFG:
3846                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3847                 break;
3848         case BNXT_FW_STATUS_REG_TYPE_GRC:
3849                 offset = bnxt_map_reset_regs(bp, offset);
3850                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3851                 break;
3852         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3853                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3854                 break;
3855         }
3856         /* wait on a specific interval of time until core reset is complete */
3857         if (delay)
3858                 rte_delay_ms(delay);
3859 }
3860
3861 static void bnxt_dev_cleanup(struct bnxt *bp)
3862 {
3863         bnxt_set_hwrm_link_config(bp, false);
3864         bp->link_info.link_up = 0;
3865         if (bp->dev_stopped == 0)
3866                 bnxt_dev_stop_op(bp->eth_dev);
3867
3868         bnxt_uninit_resources(bp, true);
3869 }
3870
3871 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3872 {
3873         struct rte_eth_dev *dev = bp->eth_dev;
3874         struct rte_vlan_filter_conf *vfc;
3875         int vidx, vbit, rc;
3876         uint16_t vlan_id;
3877
3878         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3879                 vfc = &dev->data->vlan_filter_conf;
3880                 vidx = vlan_id / 64;
3881                 vbit = vlan_id % 64;
3882
3883                 /* Each bit corresponds to a VLAN id */
3884                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3885                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3886                         if (rc)
3887                                 return rc;
3888                 }
3889         }
3890
3891         return 0;
3892 }
3893
3894 static int bnxt_restore_mac_filters(struct bnxt *bp)
3895 {
3896         struct rte_eth_dev *dev = bp->eth_dev;
3897         struct rte_eth_dev_info dev_info;
3898         struct rte_ether_addr *addr;
3899         uint64_t pool_mask;
3900         uint32_t pool = 0;
3901         uint16_t i;
3902         int rc;
3903
3904         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
3905                 return 0;
3906
3907         rc = bnxt_dev_info_get_op(dev, &dev_info);
3908         if (rc)
3909                 return rc;
3910
3911         /* replay MAC address configuration */
3912         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3913                 addr = &dev->data->mac_addrs[i];
3914
3915                 /* skip zero address */
3916                 if (rte_is_zero_ether_addr(addr))
3917                         continue;
3918
3919                 pool = 0;
3920                 pool_mask = dev->data->mac_pool_sel[i];
3921
3922                 do {
3923                         if (pool_mask & 1ULL) {
3924                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3925                                 if (rc)
3926                                         return rc;
3927                         }
3928                         pool_mask >>= 1;
3929                         pool++;
3930                 } while (pool_mask);
3931         }
3932
3933         return 0;
3934 }
3935
3936 static int bnxt_restore_filters(struct bnxt *bp)
3937 {
3938         struct rte_eth_dev *dev = bp->eth_dev;
3939         int ret = 0;
3940
3941         if (dev->data->all_multicast)
3942                 ret = bnxt_allmulticast_enable_op(dev);
3943         if (dev->data->promiscuous)
3944                 ret = bnxt_promiscuous_enable_op(dev);
3945
3946         ret = bnxt_restore_mac_filters(bp);
3947         if (ret)
3948                 return ret;
3949
3950         ret = bnxt_restore_vlan_filters(bp);
3951         /* TODO restore other filters as well */
3952         return ret;
3953 }
3954
3955 static void bnxt_dev_recover(void *arg)
3956 {
3957         struct bnxt *bp = arg;
3958         int timeout = bp->fw_reset_max_msecs;
3959         int rc = 0;
3960
3961         /* Clear Error flag so that device re-init should happen */
3962         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3963
3964         do {
3965                 rc = bnxt_hwrm_ver_get(bp);
3966                 if (rc == 0)
3967                         break;
3968                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3969                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3970         } while (rc && timeout);
3971
3972         if (rc) {
3973                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3974                 goto err;
3975         }
3976
3977         rc = bnxt_init_resources(bp, true);
3978         if (rc) {
3979                 PMD_DRV_LOG(ERR,
3980                             "Failed to initialize resources after reset\n");
3981                 goto err;
3982         }
3983         /* clear reset flag as the device is initialized now */
3984         bp->flags &= ~BNXT_FLAG_FW_RESET;
3985
3986         rc = bnxt_dev_start_op(bp->eth_dev);
3987         if (rc) {
3988                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3989                 goto err;
3990         }
3991
3992         rc = bnxt_restore_filters(bp);
3993         if (rc)
3994                 goto err;
3995
3996         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3997         return;
3998 err:
3999         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4000         bnxt_uninit_resources(bp, false);
4001         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4002 }
4003
4004 void bnxt_dev_reset_and_resume(void *arg)
4005 {
4006         struct bnxt *bp = arg;
4007         int rc;
4008
4009         bnxt_dev_cleanup(bp);
4010
4011         bnxt_wait_for_device_shutdown(bp);
4012
4013         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4014                                bnxt_dev_recover, (void *)bp);
4015         if (rc)
4016                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4017 }
4018
4019 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4020 {
4021         struct bnxt_error_recovery_info *info = bp->recovery_info;
4022         uint32_t reg = info->status_regs[index];
4023         uint32_t type, offset, val = 0;
4024
4025         type = BNXT_FW_STATUS_REG_TYPE(reg);
4026         offset = BNXT_FW_STATUS_REG_OFF(reg);
4027
4028         switch (type) {
4029         case BNXT_FW_STATUS_REG_TYPE_CFG:
4030                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4031                 break;
4032         case BNXT_FW_STATUS_REG_TYPE_GRC:
4033                 offset = info->mapped_status_regs[index];
4034                 /* FALLTHROUGH */
4035         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4036                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4037                                        offset));
4038                 break;
4039         }
4040
4041         return val;
4042 }
4043
4044 static int bnxt_fw_reset_all(struct bnxt *bp)
4045 {
4046         struct bnxt_error_recovery_info *info = bp->recovery_info;
4047         uint32_t i;
4048         int rc = 0;
4049
4050         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4051                 /* Reset through master function driver */
4052                 for (i = 0; i < info->reg_array_cnt; i++)
4053                         bnxt_write_fw_reset_reg(bp, i);
4054                 /* Wait for time specified by FW after triggering reset */
4055                 rte_delay_ms(info->master_func_wait_period_after_reset);
4056         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4057                 /* Reset with the help of Kong processor */
4058                 rc = bnxt_hwrm_fw_reset(bp);
4059                 if (rc)
4060                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4061         }
4062
4063         return rc;
4064 }
4065
4066 static void bnxt_fw_reset_cb(void *arg)
4067 {
4068         struct bnxt *bp = arg;
4069         struct bnxt_error_recovery_info *info = bp->recovery_info;
4070         int rc = 0;
4071
4072         /* Only Master function can do FW reset */
4073         if (bnxt_is_master_func(bp) &&
4074             bnxt_is_recovery_enabled(bp)) {
4075                 rc = bnxt_fw_reset_all(bp);
4076                 if (rc) {
4077                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4078                         return;
4079                 }
4080         }
4081
4082         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4083          * EXCEPTION_FATAL_ASYNC event to all the functions
4084          * (including MASTER FUNC). After receiving this Async, all the active
4085          * drivers should treat this case as FW initiated recovery
4086          */
4087         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4088                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4089                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4090
4091                 /* To recover from error */
4092                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4093                                   (void *)bp);
4094         }
4095 }
4096
4097 /* Driver should poll FW heartbeat, reset_counter with the frequency
4098  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4099  * When the driver detects heartbeat stop or change in reset_counter,
4100  * it has to trigger a reset to recover from the error condition.
4101  * A “master PF” is the function who will have the privilege to
4102  * initiate the chimp reset. The master PF will be elected by the
4103  * firmware and will be notified through async message.
4104  */
4105 static void bnxt_check_fw_health(void *arg)
4106 {
4107         struct bnxt *bp = arg;
4108         struct bnxt_error_recovery_info *info = bp->recovery_info;
4109         uint32_t val = 0, wait_msec;
4110
4111         if (!info || !bnxt_is_recovery_enabled(bp) ||
4112             is_bnxt_in_error(bp))
4113                 return;
4114
4115         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4116         if (val == info->last_heart_beat)
4117                 goto reset;
4118
4119         info->last_heart_beat = val;
4120
4121         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4122         if (val != info->last_reset_counter)
4123                 goto reset;
4124
4125         info->last_reset_counter = val;
4126
4127         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4128                           bnxt_check_fw_health, (void *)bp);
4129
4130         return;
4131 reset:
4132         /* Stop DMA to/from device */
4133         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4134         bp->flags |= BNXT_FLAG_FW_RESET;
4135
4136         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4137
4138         if (bnxt_is_master_func(bp))
4139                 wait_msec = info->master_func_wait_period;
4140         else
4141                 wait_msec = info->normal_func_wait_period;
4142
4143         rte_eal_alarm_set(US_PER_MS * wait_msec,
4144                           bnxt_fw_reset_cb, (void *)bp);
4145 }
4146
4147 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4148 {
4149         uint32_t polling_freq;
4150
4151         if (!bnxt_is_recovery_enabled(bp))
4152                 return;
4153
4154         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4155                 return;
4156
4157         polling_freq = bp->recovery_info->driver_polling_freq;
4158
4159         rte_eal_alarm_set(US_PER_MS * polling_freq,
4160                           bnxt_check_fw_health, (void *)bp);
4161         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4162 }
4163
4164 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4165 {
4166         if (!bnxt_is_recovery_enabled(bp))
4167                 return;
4168
4169         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4170         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4171 }
4172
4173 static bool bnxt_vf_pciid(uint16_t device_id)
4174 {
4175         switch (device_id) {
4176         case BROADCOM_DEV_ID_57304_VF:
4177         case BROADCOM_DEV_ID_57406_VF:
4178         case BROADCOM_DEV_ID_5731X_VF:
4179         case BROADCOM_DEV_ID_5741X_VF:
4180         case BROADCOM_DEV_ID_57414_VF:
4181         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4182         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4183         case BROADCOM_DEV_ID_58802_VF:
4184         case BROADCOM_DEV_ID_57500_VF1:
4185         case BROADCOM_DEV_ID_57500_VF2:
4186                 /* FALLTHROUGH */
4187                 return true;
4188         default:
4189                 return false;
4190         }
4191 }
4192
4193 static bool bnxt_thor_device(uint16_t device_id)
4194 {
4195         switch (device_id) {
4196         case BROADCOM_DEV_ID_57508:
4197         case BROADCOM_DEV_ID_57504:
4198         case BROADCOM_DEV_ID_57502:
4199         case BROADCOM_DEV_ID_57508_MF1:
4200         case BROADCOM_DEV_ID_57504_MF1:
4201         case BROADCOM_DEV_ID_57502_MF1:
4202         case BROADCOM_DEV_ID_57508_MF2:
4203         case BROADCOM_DEV_ID_57504_MF2:
4204         case BROADCOM_DEV_ID_57502_MF2:
4205         case BROADCOM_DEV_ID_57500_VF1:
4206         case BROADCOM_DEV_ID_57500_VF2:
4207                 /* FALLTHROUGH */
4208                 return true;
4209         default:
4210                 return false;
4211         }
4212 }
4213
4214 bool bnxt_stratus_device(struct bnxt *bp)
4215 {
4216         uint16_t device_id = bp->pdev->id.device_id;
4217
4218         switch (device_id) {
4219         case BROADCOM_DEV_ID_STRATUS_NIC:
4220         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4221         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4222                 /* FALLTHROUGH */
4223                 return true;
4224         default:
4225                 return false;
4226         }
4227 }
4228
4229 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4230 {
4231         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4232         struct bnxt *bp = eth_dev->data->dev_private;
4233
4234         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4235         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4236         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4237         if (!bp->bar0 || !bp->doorbell_base) {
4238                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4239                 return -ENODEV;
4240         }
4241
4242         bp->eth_dev = eth_dev;
4243         bp->pdev = pci_dev;
4244
4245         return 0;
4246 }
4247
4248 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4249                                   struct bnxt_ctx_pg_info *ctx_pg,
4250                                   uint32_t mem_size,
4251                                   const char *suffix,
4252                                   uint16_t idx)
4253 {
4254         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4255         const struct rte_memzone *mz = NULL;
4256         char mz_name[RTE_MEMZONE_NAMESIZE];
4257         rte_iova_t mz_phys_addr;
4258         uint64_t valid_bits = 0;
4259         uint32_t sz;
4260         int i;
4261
4262         if (!mem_size)
4263                 return 0;
4264
4265         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4266                          BNXT_PAGE_SIZE;
4267         rmem->page_size = BNXT_PAGE_SIZE;
4268         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4269         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4270         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4271
4272         valid_bits = PTU_PTE_VALID;
4273
4274         if (rmem->nr_pages > 1) {
4275                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4276                          "bnxt_ctx_pg_tbl%s_%x_%d",
4277                          suffix, idx, bp->eth_dev->data->port_id);
4278                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4279                 mz = rte_memzone_lookup(mz_name);
4280                 if (!mz) {
4281                         mz = rte_memzone_reserve_aligned(mz_name,
4282                                                 rmem->nr_pages * 8,
4283                                                 SOCKET_ID_ANY,
4284                                                 RTE_MEMZONE_2MB |
4285                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4286                                                 RTE_MEMZONE_IOVA_CONTIG,
4287                                                 BNXT_PAGE_SIZE);
4288                         if (mz == NULL)
4289                                 return -ENOMEM;
4290                 }
4291
4292                 memset(mz->addr, 0, mz->len);
4293                 mz_phys_addr = mz->iova;
4294
4295                 rmem->pg_tbl = mz->addr;
4296                 rmem->pg_tbl_map = mz_phys_addr;
4297                 rmem->pg_tbl_mz = mz;
4298         }
4299
4300         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4301                  suffix, idx, bp->eth_dev->data->port_id);
4302         mz = rte_memzone_lookup(mz_name);
4303         if (!mz) {
4304                 mz = rte_memzone_reserve_aligned(mz_name,
4305                                                  mem_size,
4306                                                  SOCKET_ID_ANY,
4307                                                  RTE_MEMZONE_1GB |
4308                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4309                                                  RTE_MEMZONE_IOVA_CONTIG,
4310                                                  BNXT_PAGE_SIZE);
4311                 if (mz == NULL)
4312                         return -ENOMEM;
4313         }
4314
4315         memset(mz->addr, 0, mz->len);
4316         mz_phys_addr = mz->iova;
4317
4318         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4319                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4320                 rmem->dma_arr[i] = mz_phys_addr + sz;
4321
4322                 if (rmem->nr_pages > 1) {
4323                         if (i == rmem->nr_pages - 2 &&
4324                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4325                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4326                         else if (i == rmem->nr_pages - 1 &&
4327                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4328                                 valid_bits |= PTU_PTE_LAST;
4329
4330                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4331                                                            valid_bits);
4332                 }
4333         }
4334
4335         rmem->mz = mz;
4336         if (rmem->vmem_size)
4337                 rmem->vmem = (void **)mz->addr;
4338         rmem->dma_arr[0] = mz_phys_addr;
4339         return 0;
4340 }
4341
4342 static void bnxt_free_ctx_mem(struct bnxt *bp)
4343 {
4344         int i;
4345
4346         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4347                 return;
4348
4349         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4350         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4351         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4352         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4353         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4354         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4355         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4356         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4357         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4358         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4359         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4360
4361         for (i = 0; i < BNXT_MAX_Q; i++) {
4362                 if (bp->ctx->tqm_mem[i])
4363                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4364         }
4365
4366         rte_free(bp->ctx);
4367         bp->ctx = NULL;
4368 }
4369
4370 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4371
4372 #define min_t(type, x, y) ({                    \
4373         type __min1 = (x);                      \
4374         type __min2 = (y);                      \
4375         __min1 < __min2 ? __min1 : __min2; })
4376
4377 #define max_t(type, x, y) ({                    \
4378         type __max1 = (x);                      \
4379         type __max2 = (y);                      \
4380         __max1 > __max2 ? __max1 : __max2; })
4381
4382 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4383
4384 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4385 {
4386         struct bnxt_ctx_pg_info *ctx_pg;
4387         struct bnxt_ctx_mem_info *ctx;
4388         uint32_t mem_size, ena, entries;
4389         int i, rc;
4390
4391         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4392         if (rc) {
4393                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4394                 return rc;
4395         }
4396         ctx = bp->ctx;
4397         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4398                 return 0;
4399
4400         ctx_pg = &ctx->qp_mem;
4401         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4402         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4403         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4404         if (rc)
4405                 return rc;
4406
4407         ctx_pg = &ctx->srq_mem;
4408         ctx_pg->entries = ctx->srq_max_l2_entries;
4409         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4410         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4411         if (rc)
4412                 return rc;
4413
4414         ctx_pg = &ctx->cq_mem;
4415         ctx_pg->entries = ctx->cq_max_l2_entries;
4416         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4417         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4418         if (rc)
4419                 return rc;
4420
4421         ctx_pg = &ctx->vnic_mem;
4422         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4423                 ctx->vnic_max_ring_table_entries;
4424         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4425         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4426         if (rc)
4427                 return rc;
4428
4429         ctx_pg = &ctx->stat_mem;
4430         ctx_pg->entries = ctx->stat_max_entries;
4431         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4432         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4433         if (rc)
4434                 return rc;
4435
4436         entries = ctx->qp_max_l2_entries +
4437                   ctx->vnic_max_vnic_entries +
4438                   ctx->tqm_min_entries_per_ring;
4439         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4440         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4441                           ctx->tqm_max_entries_per_ring);
4442         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4443                 ctx_pg = ctx->tqm_mem[i];
4444                 /* use min tqm entries for now. */
4445                 ctx_pg->entries = entries;
4446                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4447                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4448                 if (rc)
4449                         return rc;
4450                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4451         }
4452
4453         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4454         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4455         if (rc)
4456                 PMD_DRV_LOG(ERR,
4457                             "Failed to configure context mem: rc = %d\n", rc);
4458         else
4459                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4460
4461         return rc;
4462 }
4463
4464 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4465 {
4466         struct rte_pci_device *pci_dev = bp->pdev;
4467         char mz_name[RTE_MEMZONE_NAMESIZE];
4468         const struct rte_memzone *mz = NULL;
4469         uint32_t total_alloc_len;
4470         rte_iova_t mz_phys_addr;
4471
4472         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4473                 return 0;
4474
4475         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4476                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4477                  pci_dev->addr.bus, pci_dev->addr.devid,
4478                  pci_dev->addr.function, "rx_port_stats");
4479         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4480         mz = rte_memzone_lookup(mz_name);
4481         total_alloc_len =
4482                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4483                                        sizeof(struct rx_port_stats_ext) + 512);
4484         if (!mz) {
4485                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4486                                          SOCKET_ID_ANY,
4487                                          RTE_MEMZONE_2MB |
4488                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4489                                          RTE_MEMZONE_IOVA_CONTIG);
4490                 if (mz == NULL)
4491                         return -ENOMEM;
4492         }
4493         memset(mz->addr, 0, mz->len);
4494         mz_phys_addr = mz->iova;
4495
4496         bp->rx_mem_zone = (const void *)mz;
4497         bp->hw_rx_port_stats = mz->addr;
4498         bp->hw_rx_port_stats_map = mz_phys_addr;
4499
4500         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4501                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4502                  pci_dev->addr.bus, pci_dev->addr.devid,
4503                  pci_dev->addr.function, "tx_port_stats");
4504         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4505         mz = rte_memzone_lookup(mz_name);
4506         total_alloc_len =
4507                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4508                                        sizeof(struct tx_port_stats_ext) + 512);
4509         if (!mz) {
4510                 mz = rte_memzone_reserve(mz_name,
4511                                          total_alloc_len,
4512                                          SOCKET_ID_ANY,
4513                                          RTE_MEMZONE_2MB |
4514                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4515                                          RTE_MEMZONE_IOVA_CONTIG);
4516                 if (mz == NULL)
4517                         return -ENOMEM;
4518         }
4519         memset(mz->addr, 0, mz->len);
4520         mz_phys_addr = mz->iova;
4521
4522         bp->tx_mem_zone = (const void *)mz;
4523         bp->hw_tx_port_stats = mz->addr;
4524         bp->hw_tx_port_stats_map = mz_phys_addr;
4525         bp->flags |= BNXT_FLAG_PORT_STATS;
4526
4527         /* Display extended statistics if FW supports it */
4528         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4529             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4530             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4531                 return 0;
4532
4533         bp->hw_rx_port_stats_ext = (void *)
4534                 ((uint8_t *)bp->hw_rx_port_stats +
4535                  sizeof(struct rx_port_stats));
4536         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4537                 sizeof(struct rx_port_stats);
4538         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4539
4540         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4541             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4542                 bp->hw_tx_port_stats_ext = (void *)
4543                         ((uint8_t *)bp->hw_tx_port_stats +
4544                          sizeof(struct tx_port_stats));
4545                 bp->hw_tx_port_stats_ext_map =
4546                         bp->hw_tx_port_stats_map +
4547                         sizeof(struct tx_port_stats);
4548                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4549         }
4550
4551         return 0;
4552 }
4553
4554 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4555 {
4556         struct bnxt *bp = eth_dev->data->dev_private;
4557         int rc = 0;
4558
4559         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4560                                                RTE_ETHER_ADDR_LEN *
4561                                                bp->max_l2_ctx,
4562                                                0);
4563         if (eth_dev->data->mac_addrs == NULL) {
4564                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4565                 return -ENOMEM;
4566         }
4567
4568         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4569                 if (BNXT_PF(bp))
4570                         return -EINVAL;
4571
4572                 /* Generate a random MAC address, if none was assigned by PF */
4573                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4574                 bnxt_eth_hw_addr_random(bp->mac_addr);
4575                 PMD_DRV_LOG(INFO,
4576                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4577                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4578                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4579
4580                 rc = bnxt_hwrm_set_mac(bp);
4581                 if (!rc)
4582                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4583                                RTE_ETHER_ADDR_LEN);
4584                 return rc;
4585         }
4586
4587         /* Copy the permanent MAC from the FUNC_QCAPS response */
4588         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4589         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4590
4591         return rc;
4592 }
4593
4594 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4595 {
4596         int rc = 0;
4597
4598         /* MAC is already configured in FW */
4599         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4600                 return 0;
4601
4602         /* Restore the old MAC configured */
4603         rc = bnxt_hwrm_set_mac(bp);
4604         if (rc)
4605                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4606
4607         return rc;
4608 }
4609
4610 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4611 {
4612         if (!BNXT_PF(bp))
4613                 return;
4614
4615 #define ALLOW_FUNC(x)   \
4616         { \
4617                 uint32_t arg = (x); \
4618                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4619                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4620         }
4621
4622         /* Forward all requests if firmware is new enough */
4623         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4624              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4625             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4626                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4627         } else {
4628                 PMD_DRV_LOG(WARNING,
4629                             "Firmware too old for VF mailbox functionality\n");
4630                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4631         }
4632
4633         /*
4634          * The following are used for driver cleanup. If we disallow these,
4635          * VF drivers can't clean up cleanly.
4636          */
4637         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4638         ALLOW_FUNC(HWRM_VNIC_FREE);
4639         ALLOW_FUNC(HWRM_RING_FREE);
4640         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4641         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4642         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4643         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4644         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4645         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4646 }
4647
4648 static int bnxt_init_fw(struct bnxt *bp)
4649 {
4650         uint16_t mtu;
4651         int rc = 0;
4652
4653         bp->fw_cap = 0;
4654
4655         rc = bnxt_hwrm_ver_get(bp);
4656         if (rc)
4657                 return rc;
4658
4659         rc = bnxt_hwrm_func_reset(bp);
4660         if (rc)
4661                 return -EIO;
4662
4663         rc = bnxt_hwrm_vnic_qcaps(bp);
4664         if (rc)
4665                 return rc;
4666
4667         rc = bnxt_hwrm_queue_qportcfg(bp);
4668         if (rc)
4669                 return rc;
4670
4671         /* Get the MAX capabilities for this function.
4672          * This function also allocates context memory for TQM rings and
4673          * informs the firmware about this allocated backing store memory.
4674          */
4675         rc = bnxt_hwrm_func_qcaps(bp);
4676         if (rc)
4677                 return rc;
4678
4679         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4680         if (rc)
4681                 return rc;
4682
4683         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4684         if (rc)
4685                 return rc;
4686
4687         /* Get the adapter error recovery support info */
4688         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4689         if (rc)
4690                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4691
4692         bnxt_hwrm_port_led_qcaps(bp);
4693
4694         return 0;
4695 }
4696
4697 static int
4698 bnxt_init_locks(struct bnxt *bp)
4699 {
4700         int err;
4701
4702         err = pthread_mutex_init(&bp->flow_lock, NULL);
4703         if (err) {
4704                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4705                 return err;
4706         }
4707
4708         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4709         if (err)
4710                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4711         return err;
4712 }
4713
4714 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4715 {
4716         int rc;
4717
4718         rc = bnxt_init_fw(bp);
4719         if (rc)
4720                 return rc;
4721
4722         if (!reconfig_dev) {
4723                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4724                 if (rc)
4725                         return rc;
4726         } else {
4727                 rc = bnxt_restore_dflt_mac(bp);
4728                 if (rc)
4729                         return rc;
4730         }
4731
4732         bnxt_config_vf_req_fwd(bp);
4733
4734         rc = bnxt_hwrm_func_driver_register(bp);
4735         if (rc) {
4736                 PMD_DRV_LOG(ERR, "Failed to register driver");
4737                 return -EBUSY;
4738         }
4739
4740         if (BNXT_PF(bp)) {
4741                 if (bp->pdev->max_vfs) {
4742                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4743                         if (rc) {
4744                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4745                                 return rc;
4746                         }
4747                 } else {
4748                         rc = bnxt_hwrm_allocate_pf_only(bp);
4749                         if (rc) {
4750                                 PMD_DRV_LOG(ERR,
4751                                             "Failed to allocate PF resources");
4752                                 return rc;
4753                         }
4754                 }
4755         }
4756
4757         rc = bnxt_alloc_mem(bp, reconfig_dev);
4758         if (rc)
4759                 return rc;
4760
4761         rc = bnxt_setup_int(bp);
4762         if (rc)
4763                 return rc;
4764
4765         rc = bnxt_request_int(bp);
4766         if (rc)
4767                 return rc;
4768
4769         rc = bnxt_init_locks(bp);
4770         if (rc)
4771                 return rc;
4772
4773         return 0;
4774 }
4775
4776 static int
4777 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4778 {
4779         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4780         static int version_printed;
4781         struct bnxt *bp;
4782         int rc;
4783
4784         if (version_printed++ == 0)
4785                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4786
4787         eth_dev->dev_ops = &bnxt_dev_ops;
4788         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4789         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4790
4791         /*
4792          * For secondary processes, we don't initialise any further
4793          * as primary has already done this work.
4794          */
4795         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4796                 return 0;
4797
4798         rte_eth_copy_pci_info(eth_dev, pci_dev);
4799
4800         bp = eth_dev->data->dev_private;
4801
4802         bp->dev_stopped = 1;
4803         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
4804
4805         if (bnxt_vf_pciid(pci_dev->id.device_id))
4806                 bp->flags |= BNXT_FLAG_VF;
4807
4808         if (bnxt_thor_device(pci_dev->id.device_id))
4809                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4810
4811         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4812             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4813             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4814             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4815                 bp->flags |= BNXT_FLAG_STINGRAY;
4816
4817         rc = bnxt_init_board(eth_dev);
4818         if (rc) {
4819                 PMD_DRV_LOG(ERR,
4820                             "Failed to initialize board rc: %x\n", rc);
4821                 return rc;
4822         }
4823
4824         rc = bnxt_alloc_hwrm_resources(bp);
4825         if (rc) {
4826                 PMD_DRV_LOG(ERR,
4827                             "Failed to allocate hwrm resource rc: %x\n", rc);
4828                 goto error_free;
4829         }
4830         rc = bnxt_init_resources(bp, false);
4831         if (rc)
4832                 goto error_free;
4833
4834         rc = bnxt_alloc_stats_mem(bp);
4835         if (rc)
4836                 goto error_free;
4837
4838         PMD_DRV_LOG(INFO,
4839                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4840                     pci_dev->mem_resource[0].phys_addr,
4841                     pci_dev->mem_resource[0].addr);
4842
4843         return 0;
4844
4845 error_free:
4846         bnxt_dev_uninit(eth_dev);
4847         return rc;
4848 }
4849
4850 static void
4851 bnxt_uninit_locks(struct bnxt *bp)
4852 {
4853         pthread_mutex_destroy(&bp->flow_lock);
4854         pthread_mutex_destroy(&bp->def_cp_lock);
4855 }
4856
4857 static int
4858 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4859 {
4860         int rc;
4861
4862         bnxt_free_int(bp);
4863         bnxt_free_mem(bp, reconfig_dev);
4864         bnxt_hwrm_func_buf_unrgtr(bp);
4865         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4866         bp->flags &= ~BNXT_FLAG_REGISTERED;
4867         bnxt_free_ctx_mem(bp);
4868         if (!reconfig_dev) {
4869                 bnxt_free_hwrm_resources(bp);
4870
4871                 if (bp->recovery_info != NULL) {
4872                         rte_free(bp->recovery_info);
4873                         bp->recovery_info = NULL;
4874                 }
4875         }
4876
4877         bnxt_uninit_locks(bp);
4878         rte_free(bp->ptp_cfg);
4879         bp->ptp_cfg = NULL;
4880         return rc;
4881 }
4882
4883 static int
4884 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4885 {
4886         struct bnxt *bp = eth_dev->data->dev_private;
4887         int rc;
4888
4889         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4890                 return -EPERM;
4891
4892         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4893
4894         rc = bnxt_uninit_resources(bp, false);
4895
4896         if (bp->tx_mem_zone) {
4897                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4898                 bp->tx_mem_zone = NULL;
4899         }
4900
4901         if (bp->rx_mem_zone) {
4902                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4903                 bp->rx_mem_zone = NULL;
4904         }
4905
4906         if (bp->dev_stopped == 0)
4907                 bnxt_dev_close_op(eth_dev);
4908         if (bp->pf.vf_info)
4909                 rte_free(bp->pf.vf_info);
4910         eth_dev->dev_ops = NULL;
4911         eth_dev->rx_pkt_burst = NULL;
4912         eth_dev->tx_pkt_burst = NULL;
4913
4914         return rc;
4915 }
4916
4917 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4918         struct rte_pci_device *pci_dev)
4919 {
4920         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4921                 bnxt_dev_init);
4922 }
4923
4924 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4925 {
4926         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4927                 return rte_eth_dev_pci_generic_remove(pci_dev,
4928                                 bnxt_dev_uninit);
4929         else
4930                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4931 }
4932
4933 static struct rte_pci_driver bnxt_rte_pmd = {
4934         .id_table = bnxt_pci_id_map,
4935         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4936         .probe = bnxt_pci_probe,
4937         .remove = bnxt_pci_remove,
4938 };
4939
4940 static bool
4941 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4942 {
4943         if (strcmp(dev->device->driver->name, drv->driver.name))
4944                 return false;
4945
4946         return true;
4947 }
4948
4949 bool is_bnxt_supported(struct rte_eth_dev *dev)
4950 {
4951         return is_device_supported(dev, &bnxt_rte_pmd);
4952 }
4953
4954 RTE_INIT(bnxt_init_log)
4955 {
4956         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4957         if (bnxt_logtype_driver >= 0)
4958                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4959 }
4960
4961 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4962 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4963 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");