drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31 #include "bnxt_tf_common.h"
  32 #include "ulp_flow_db.h"
  33
  34 #define DRV_MODULE_NAME         "bnxt"
  35 static const char bnxt_version[] =
  36         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  37
  38 /*
  39  * The set of PCI devices this driver supports
  40  */
  41 static const struct rte_pci_id bnxt_pci_id_map[] = {
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  95         { .vendor_id = 0, /* sentinel */ },
  96 };
  97
  98 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  99 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 101 #define BNXT_DEVARG_REPRESENTOR "representor"
 102
 103 static const char *const bnxt_dev_args[] = {
 104         BNXT_DEVARG_REPRESENTOR,
 105         BNXT_DEVARG_TRUFLOW,
 106         BNXT_DEVARG_FLOW_XSTAT,
 107         BNXT_DEVARG_MAX_NUM_KFLOWS,
 108         NULL
 109 };
 110
 111 /*
 112  * truflow == false to disable the feature
 113  * truflow == true to enable the feature
 114  */
 115 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 116
 117 /*
 118  * flow_xstat == false to disable the feature
 119  * flow_xstat == true to enable the feature
 120  */
 121 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 122
 123 /*
 124  * max_num_kflows must be >= 32
 125  * and must be a power-of-2 supported value
 126  * return: 1 -> invalid
 127  *         0 -> valid
 128  */
 129 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 130 {
 131         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 132                 return 1;
 133         return 0;
 134 }
 135
 136 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 137 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 138 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 139 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 140 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 141 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 142 static void bnxt_dev_recover(void *arg);
 143 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 144 static void bnxt_free_rep_info(struct bnxt *bp);
 145
 146 int is_bnxt_in_error(struct bnxt *bp)
 147 {
 148         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 149                 return -EIO;
 150         if (bp->flags & BNXT_FLAG_FW_RESET)
 151                 return -EBUSY;
 152
 153         return 0;
 154 }
 155
 156 /***********************/
 157
 158 /*
 159  * High level utility functions
 160  */
 161
 162 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 163 {
 164         if (!BNXT_CHIP_THOR(bp))
 165                 return 1;
 166
 167         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 168                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 169                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 170 }
 171
 172 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 173 {
 174         if (!BNXT_CHIP_THOR(bp))
 175                 return HW_HASH_INDEX_SIZE;
 176
 177         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 178 }
 179
 180 static void bnxt_free_parent_info(struct bnxt *bp)
 181 {
 182         rte_free(bp->parent);
 183 }
 184
 185 static void bnxt_free_pf_info(struct bnxt *bp)
 186 {
 187         rte_free(bp->pf);
 188 }
 189
 190 static void bnxt_free_link_info(struct bnxt *bp)
 191 {
 192         rte_free(bp->link_info);
 193 }
 194
 195 static void bnxt_free_leds_info(struct bnxt *bp)
 196 {
 197         if (BNXT_VF(bp))
 198                 return;
 199
 200         rte_free(bp->leds);
 201         bp->leds = NULL;
 202 }
 203
 204 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 205 {
 206         rte_free(bp->flow_stat);
 207         bp->flow_stat = NULL;
 208 }
 209
 210 static void bnxt_free_cos_queues(struct bnxt *bp)
 211 {
 212         rte_free(bp->rx_cos_queue);
 213         rte_free(bp->tx_cos_queue);
 214 }
 215
 216 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 217 {
 218         bnxt_free_filter_mem(bp);
 219         bnxt_free_vnic_attributes(bp);
 220         bnxt_free_vnic_mem(bp);
 221
 222         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 223          * If the number of rings change across fw update,
 224          * we don't have much choice except to warn the user.
 225          */
 226         if (!reconfig) {
 227                 bnxt_free_stats(bp);
 228                 bnxt_free_tx_rings(bp);
 229                 bnxt_free_rx_rings(bp);
 230         }
 231         bnxt_free_async_cp_ring(bp);
 232         bnxt_free_rxtx_nq_ring(bp);
 233
 234         rte_free(bp->grp_info);
 235         bp->grp_info = NULL;
 236 }
 237
 238 static int bnxt_alloc_parent_info(struct bnxt *bp)
 239 {
 240         bp->parent = rte_zmalloc("bnxt_parent_info",
 241                                  sizeof(struct bnxt_parent_info), 0);
 242         if (bp->parent == NULL)
 243                 return -ENOMEM;
 244
 245         return 0;
 246 }
 247
 248 static int bnxt_alloc_pf_info(struct bnxt *bp)
 249 {
 250         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 251         if (bp->pf == NULL)
 252                 return -ENOMEM;
 253
 254         return 0;
 255 }
 256
 257 static int bnxt_alloc_link_info(struct bnxt *bp)
 258 {
 259         bp->link_info =
 260                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 261         if (bp->link_info == NULL)
 262                 return -ENOMEM;
 263
 264         return 0;
 265 }
 266
 267 static int bnxt_alloc_leds_info(struct bnxt *bp)
 268 {
 269         if (BNXT_VF(bp))
 270                 return 0;
 271
 272         bp->leds = rte_zmalloc("bnxt_leds",
 273                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 274                                0);
 275         if (bp->leds == NULL)
 276                 return -ENOMEM;
 277
 278         return 0;
 279 }
 280
 281 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 282 {
 283         bp->rx_cos_queue =
 284                 rte_zmalloc("bnxt_rx_cosq",
 285                             BNXT_COS_QUEUE_COUNT *
 286                             sizeof(struct bnxt_cos_queue_info),
 287                             0);
 288         if (bp->rx_cos_queue == NULL)
 289                 return -ENOMEM;
 290
 291         bp->tx_cos_queue =
 292                 rte_zmalloc("bnxt_tx_cosq",
 293                             BNXT_COS_QUEUE_COUNT *
 294                             sizeof(struct bnxt_cos_queue_info),
 295                             0);
 296         if (bp->tx_cos_queue == NULL)
 297                 return -ENOMEM;
 298
 299         return 0;
 300 }
 301
 302 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 303 {
 304         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 305                                     sizeof(struct bnxt_flow_stat_info), 0);
 306         if (bp->flow_stat == NULL)
 307                 return -ENOMEM;
 308
 309         return 0;
 310 }
 311
 312 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 313 {
 314         int rc;
 315
 316         rc = bnxt_alloc_ring_grps(bp);
 317         if (rc)
 318                 goto alloc_mem_err;
 319
 320         rc = bnxt_alloc_async_ring_struct(bp);
 321         if (rc)
 322                 goto alloc_mem_err;
 323
 324         rc = bnxt_alloc_vnic_mem(bp);
 325         if (rc)
 326                 goto alloc_mem_err;
 327
 328         rc = bnxt_alloc_vnic_attributes(bp);
 329         if (rc)
 330                 goto alloc_mem_err;
 331
 332         rc = bnxt_alloc_filter_mem(bp);
 333         if (rc)
 334                 goto alloc_mem_err;
 335
 336         rc = bnxt_alloc_async_cp_ring(bp);
 337         if (rc)
 338                 goto alloc_mem_err;
 339
 340         rc = bnxt_alloc_rxtx_nq_ring(bp);
 341         if (rc)
 342                 goto alloc_mem_err;
 343
 344         if (BNXT_FLOW_XSTATS_EN(bp)) {
 345                 rc = bnxt_alloc_flow_stats_info(bp);
 346                 if (rc)
 347                         goto alloc_mem_err;
 348         }
 349
 350         return 0;
 351
 352 alloc_mem_err:
 353         bnxt_free_mem(bp, reconfig);
 354         return rc;
 355 }
 356
 357 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 358 {
 359         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 360         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 361         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 362         struct bnxt_rx_queue *rxq;
 363         unsigned int j;
 364         int rc;
 365
 366         rc = bnxt_vnic_grp_alloc(bp, vnic);
 367         if (rc)
 368                 goto err_out;
 369
 370         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 371                     vnic_id, vnic, vnic->fw_grp_ids);
 372
 373         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 374         if (rc)
 375                 goto err_out;
 376
 377         /* Alloc RSS context only if RSS mode is enabled */
 378         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 379                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 380
 381                 rc = 0;
 382                 for (j = 0; j < nr_ctxs; j++) {
 383                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 384                         if (rc)
 385                                 break;
 386                 }
 387                 if (rc) {
 388                         PMD_DRV_LOG(ERR,
 389                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 390                                     vnic_id, j, rc);
 391                         goto err_out;
 392                 }
 393                 vnic->num_lb_ctxts = nr_ctxs;
 394         }
 395
 396         /*
 397          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 398          * setting is not available at this time, it will not be
 399          * configured correctly in the CFA.
 400          */
 401         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 402                 vnic->vlan_strip = true;
 403         else
 404                 vnic->vlan_strip = false;
 405
 406         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 407         if (rc)
 408                 goto err_out;
 409
 410         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 411         if (rc)
 412                 goto err_out;
 413
 414         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 415                 rxq = bp->eth_dev->data->rx_queues[j];
 416
 417                 PMD_DRV_LOG(DEBUG,
 418                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 419                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 420
 421                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 422                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 423                 else
 424                         vnic->rx_queue_cnt++;
 425         }
 426
 427         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 428
 429         rc = bnxt_vnic_rss_configure(bp, vnic);
 430         if (rc)
 431                 goto err_out;
 432
 433         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 434
 435         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 436                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 437         else
 438                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 439
 440         return 0;
 441 err_out:
 442         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 443                     vnic_id, rc);
 444         return rc;
 445 }
 446
 447 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 448 {
 449         int rc = 0;
 450
 451         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 452                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 453         if (rc)
 454                 return rc;
 455
 456         PMD_DRV_LOG(DEBUG,
 457                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 458                     " rx_fc_in_tbl.ctx_id = %d\n",
 459                     bp->flow_stat->rx_fc_in_tbl.va,
 460                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 461                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 462
 463         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 464                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 465         if (rc)
 466                 return rc;
 467
 468         PMD_DRV_LOG(DEBUG,
 469                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 470                     " rx_fc_out_tbl.ctx_id = %d\n",
 471                     bp->flow_stat->rx_fc_out_tbl.va,
 472                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 473                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 474
 475         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 476                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 477         if (rc)
 478                 return rc;
 479
 480         PMD_DRV_LOG(DEBUG,
 481                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 482                     " tx_fc_in_tbl.ctx_id = %d\n",
 483                     bp->flow_stat->tx_fc_in_tbl.va,
 484                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 485                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 486
 487         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 488                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 489         if (rc)
 490                 return rc;
 491
 492         PMD_DRV_LOG(DEBUG,
 493                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 494                     " tx_fc_out_tbl.ctx_id = %d\n",
 495                     bp->flow_stat->tx_fc_out_tbl.va,
 496                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 497                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 498
 499         memset(bp->flow_stat->rx_fc_out_tbl.va,
 500                0,
 501                bp->flow_stat->rx_fc_out_tbl.size);
 502         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 503                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 504                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 505                                        bp->flow_stat->max_fc,
 506                                        true);
 507         if (rc)
 508                 return rc;
 509
 510         memset(bp->flow_stat->tx_fc_out_tbl.va,
 511                0,
 512                bp->flow_stat->tx_fc_out_tbl.size);
 513         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 514                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 515                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 516                                        bp->flow_stat->max_fc,
 517                                        true);
 518
 519         return rc;
 520 }
 521
 522 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 523                                   struct bnxt_ctx_mem_buf_info *ctx)
 524 {
 525         if (!ctx)
 526                 return -EINVAL;
 527
 528         ctx->va = rte_zmalloc(type, size, 0);
 529         if (ctx->va == NULL)
 530                 return -ENOMEM;
 531         rte_mem_lock_page(ctx->va);
 532         ctx->size = size;
 533         ctx->dma = rte_mem_virt2iova(ctx->va);
 534         if (ctx->dma == RTE_BAD_IOVA)
 535                 return -ENOMEM;
 536
 537         return 0;
 538 }
 539
 540 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 541 {
 542         struct rte_pci_device *pdev = bp->pdev;
 543         char type[RTE_MEMZONE_NAMESIZE];
 544         uint16_t max_fc;
 545         int rc = 0;
 546
 547         max_fc = bp->flow_stat->max_fc;
 548
 549         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 550                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 551         /* 4 bytes for each counter-id */
 552         rc = bnxt_alloc_ctx_mem_buf(type,
 553                                     max_fc * 4,
 554                                     &bp->flow_stat->rx_fc_in_tbl);
 555         if (rc)
 556                 return rc;
 557
 558         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 559                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 560         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 561         rc = bnxt_alloc_ctx_mem_buf(type,
 562                                     max_fc * 16,
 563                                     &bp->flow_stat->rx_fc_out_tbl);
 564         if (rc)
 565                 return rc;
 566
 567         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 568                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 569         /* 4 bytes for each counter-id */
 570         rc = bnxt_alloc_ctx_mem_buf(type,
 571                                     max_fc * 4,
 572                                     &bp->flow_stat->tx_fc_in_tbl);
 573         if (rc)
 574                 return rc;
 575
 576         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 577                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 578         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 579         rc = bnxt_alloc_ctx_mem_buf(type,
 580                                     max_fc * 16,
 581                                     &bp->flow_stat->tx_fc_out_tbl);
 582         if (rc)
 583                 return rc;
 584
 585         rc = bnxt_register_fc_ctx_mem(bp);
 586
 587         return rc;
 588 }
 589
 590 static int bnxt_init_ctx_mem(struct bnxt *bp)
 591 {
 592         int rc = 0;
 593
 594         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 595             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 596             !BNXT_FLOW_XSTATS_EN(bp))
 597                 return 0;
 598
 599         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 600         if (rc)
 601                 return rc;
 602
 603         rc = bnxt_init_fc_ctx_mem(bp);
 604
 605         return rc;
 606 }
 607
 608 static int bnxt_update_phy_setting(struct bnxt *bp)
 609 {
 610         struct rte_eth_link new;
 611         int rc;
 612
 613         rc = bnxt_get_hwrm_link_config(bp, &new);
 614         if (rc) {
 615                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 616                 return rc;
 617         }
 618
 619         /*
 620          * On BCM957508-N2100 adapters, FW will not allow any user other
 621          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 622          * always returns link up. Force phy update always in that case.
 623          */
 624         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 625                 rc = bnxt_set_hwrm_link_config(bp, true);
 626                 if (rc) {
 627                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 628                         return rc;
 629                 }
 630         }
 631
 632         return rc;
 633 }
 634
 635 static int bnxt_init_chip(struct bnxt *bp)
 636 {
 637         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 638         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 639         uint32_t intr_vector = 0;
 640         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 641         uint32_t vec = BNXT_MISC_VEC_ID;
 642         unsigned int i, j;
 643         int rc;
 644
 645         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 646                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 647                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 648                 bp->flags |= BNXT_FLAG_JUMBO;
 649         } else {
 650                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 651                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 652                 bp->flags &= ~BNXT_FLAG_JUMBO;
 653         }
 654
 655         /* THOR does not support ring groups.
 656          * But we will use the array to save RSS context IDs.
 657          */
 658         if (BNXT_CHIP_THOR(bp))
 659                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 660
 661         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 662         if (rc) {
 663                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 664                 goto err_out;
 665         }
 666
 667         rc = bnxt_alloc_hwrm_rings(bp);
 668         if (rc) {
 669                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 670                 goto err_out;
 671         }
 672
 673         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 674         if (rc) {
 675                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 676                 goto err_out;
 677         }
 678
 679         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 680                 goto skip_cosq_cfg;
 681
 682         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 683                 if (bp->rx_cos_queue[i].id != 0xff) {
 684                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 685
 686                         if (!vnic) {
 687                                 PMD_DRV_LOG(ERR,
 688                                             "Num pools more than FW profile\n");
 689                                 rc = -EINVAL;
 690                                 goto err_out;
 691                         }
 692                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 693                         bp->rx_cosq_cnt++;
 694                 }
 695         }
 696
 697 skip_cosq_cfg:
 698         rc = bnxt_mq_rx_configure(bp);
 699         if (rc) {
 700                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 701                 goto err_out;
 702         }
 703
 704         /* VNIC configuration */
 705         for (i = 0; i < bp->nr_vnics; i++) {
 706                 rc = bnxt_setup_one_vnic(bp, i);
 707                 if (rc)
 708                         goto err_out;
 709         }
 710
 711         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 712         if (rc) {
 713                 PMD_DRV_LOG(ERR,
 714                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 715                 goto err_out;
 716         }
 717
 718         /* check and configure queue intr-vector mapping */
 719         if ((rte_intr_cap_multiple(intr_handle) ||
 720              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 721             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 722                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 723                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 724                 if (intr_vector > bp->rx_cp_nr_rings) {
 725                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 726                                         bp->rx_cp_nr_rings);
 727                         return -ENOTSUP;
 728                 }
 729                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 730                 if (rc)
 731                         return rc;
 732         }
 733
 734         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 735                 intr_handle->intr_vec =
 736                         rte_zmalloc("intr_vec",
 737                                     bp->eth_dev->data->nb_rx_queues *
 738                                     sizeof(int), 0);
 739                 if (intr_handle->intr_vec == NULL) {
 740                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 741                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 742                         rc = -ENOMEM;
 743                         goto err_disable;
 744                 }
 745                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 746                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 747                          intr_handle->intr_vec, intr_handle->nb_efd,
 748                         intr_handle->max_intr);
 749                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 750                      queue_id++) {
 751                         intr_handle->intr_vec[queue_id] =
 752                                                         vec + BNXT_RX_VEC_START;
 753                         if (vec < base + intr_handle->nb_efd - 1)
 754                                 vec++;
 755                 }
 756         }
 757
 758         /* enable uio/vfio intr/eventfd mapping */
 759         rc = rte_intr_enable(intr_handle);
 760 #ifndef RTE_EXEC_ENV_FREEBSD
 761         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 762         if (rc)
 763                 goto err_free;
 764 #endif
 765
 766         rc = bnxt_update_phy_setting(bp);
 767         if (rc)
 768                 goto err_free;
 769
 770         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 771         if (!bp->mark_table)
 772                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 773
 774         return 0;
 775
 776 err_free:
 777         rte_free(intr_handle->intr_vec);
 778 err_disable:
 779         rte_intr_efd_disable(intr_handle);
 780 err_out:
 781         /* Some of the error status returned by FW may not be from errno.h */
 782         if (rc > 0)
 783                 rc = -EIO;
 784
 785         return rc;
 786 }
 787
 788 static int bnxt_shutdown_nic(struct bnxt *bp)
 789 {
 790         bnxt_free_all_hwrm_resources(bp);
 791         bnxt_free_all_filters(bp);
 792         bnxt_free_all_vnics(bp);
 793         return 0;
 794 }
 795
 796 /*
 797  * Device configuration and status function
 798  */
 799
 800 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 801 {
 802         uint32_t link_speed = bp->link_info->support_speeds;
 803         uint32_t speed_capa = 0;
 804
 805         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 806                 speed_capa |= ETH_LINK_SPEED_100M;
 807         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 808                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 809         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 810                 speed_capa |= ETH_LINK_SPEED_1G;
 811         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 812                 speed_capa |= ETH_LINK_SPEED_2_5G;
 813         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 814                 speed_capa |= ETH_LINK_SPEED_10G;
 815         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 816                 speed_capa |= ETH_LINK_SPEED_20G;
 817         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 818                 speed_capa |= ETH_LINK_SPEED_25G;
 819         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 820                 speed_capa |= ETH_LINK_SPEED_40G;
 821         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 822                 speed_capa |= ETH_LINK_SPEED_50G;
 823         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 824                 speed_capa |= ETH_LINK_SPEED_100G;
 825         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
 826                 speed_capa |= ETH_LINK_SPEED_200G;
 827
 828         if (bp->link_info->auto_mode ==
 829             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 830                 speed_capa |= ETH_LINK_SPEED_FIXED;
 831         else
 832                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 833
 834         return speed_capa;
 835 }
 836
 837 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 838                                 struct rte_eth_dev_info *dev_info)
 839 {
 840         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 841         struct bnxt *bp = eth_dev->data->dev_private;
 842         uint16_t max_vnics, i, j, vpool, vrxq;
 843         unsigned int max_rx_rings;
 844         int rc;
 845
 846         rc = is_bnxt_in_error(bp);
 847         if (rc)
 848                 return rc;
 849
 850         /* MAC Specifics */
 851         dev_info->max_mac_addrs = bp->max_l2_ctx;
 852         dev_info->max_hash_mac_addrs = 0;
 853
 854         /* PF/VF specifics */
 855         if (BNXT_PF(bp))
 856                 dev_info->max_vfs = pdev->max_vfs;
 857
 858         max_rx_rings = BNXT_MAX_RINGS(bp);
 859         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 860         dev_info->max_rx_queues = max_rx_rings;
 861         dev_info->max_tx_queues = max_rx_rings;
 862         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 863         dev_info->hash_key_size = 40;
 864         max_vnics = bp->max_vnics;
 865
 866         /* MTU specifics */
 867         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 868         dev_info->max_mtu = BNXT_MAX_MTU;
 869
 870         /* Fast path specifics */
 871         dev_info->min_rx_bufsize = 1;
 872         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 873
 874         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 875         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 876                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 877         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 878         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 879
 880         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 881
 882         /* *INDENT-OFF* */
 883         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 884                 .rx_thresh = {
 885                         .pthresh = 8,
 886                         .hthresh = 8,
 887                         .wthresh = 0,
 888                 },
 889                 .rx_free_thresh = 32,
 890                 /* If no descriptors available, pkts are dropped by default */
 891                 .rx_drop_en = 1,
 892         };
 893
 894         dev_info->default_txconf = (struct rte_eth_txconf) {
 895                 .tx_thresh = {
 896                         .pthresh = 32,
 897                         .hthresh = 0,
 898                         .wthresh = 0,
 899                 },
 900                 .tx_free_thresh = 32,
 901                 .tx_rs_thresh = 32,
 902         };
 903         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 904
 905         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 906         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 907         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 908         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 909         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 910
 911         /* *INDENT-ON* */
 912
 913         /*
 914          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 915          *       need further investigation.
 916          */
 917
 918         /* VMDq resources */
 919         vpool = 64; /* ETH_64_POOLS */
 920         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 921         for (i = 0; i < 4; vpool >>= 1, i++) {
 922                 if (max_vnics > vpool) {
 923                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 924                                 if (dev_info->max_rx_queues > vrxq) {
 925                                         if (vpool > vrxq)
 926                                                 vpool = vrxq;
 927                                         goto found;
 928                                 }
 929                         }
 930                         /* Not enough resources to support VMDq */
 931                         break;
 932                 }
 933         }
 934         /* Not enough resources to support VMDq */
 935         vpool = 0;
 936         vrxq = 0;
 937 found:
 938         dev_info->max_vmdq_pools = vpool;
 939         dev_info->vmdq_queue_num = vrxq;
 940
 941         dev_info->vmdq_pool_base = 0;
 942         dev_info->vmdq_queue_base = 0;
 943
 944         return 0;
 945 }
 946
 947 /* Configure the device based on the configuration provided */
 948 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 949 {
 950         struct bnxt *bp = eth_dev->data->dev_private;
 951         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 952         int rc;
 953
 954         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 955         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 956         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 957         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 958
 959         rc = is_bnxt_in_error(bp);
 960         if (rc)
 961                 return rc;
 962
 963         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 964                 rc = bnxt_hwrm_check_vf_rings(bp);
 965                 if (rc) {
 966                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 967                         return -ENOSPC;
 968                 }
 969
 970                 /* If a resource has already been allocated - in this case
 971                  * it is the async completion ring, free it. Reallocate it after
 972                  * resource reservation. This will ensure the resource counts
 973                  * are calculated correctly.
 974                  */
 975
 976                 pthread_mutex_lock(&bp->def_cp_lock);
 977
 978                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 979                         bnxt_disable_int(bp);
 980                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 981                 }
 982
 983                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 984                 if (rc) {
 985                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 986                         pthread_mutex_unlock(&bp->def_cp_lock);
 987                         return -ENOSPC;
 988                 }
 989
 990                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 991                         rc = bnxt_alloc_async_cp_ring(bp);
 992                         if (rc) {
 993                                 pthread_mutex_unlock(&bp->def_cp_lock);
 994                                 return rc;
 995                         }
 996                         bnxt_enable_int(bp);
 997                 }
 998
 999                 pthread_mutex_unlock(&bp->def_cp_lock);
1000         } else {
1001                 /* legacy driver needs to get updated values */
1002                 rc = bnxt_hwrm_func_qcaps(bp);
1003                 if (rc) {
1004                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1005                         return rc;
1006                 }
1007         }
1008
1009         /* Inherit new configurations */
1010         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1011             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1012             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1013                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1014             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1015             bp->max_stat_ctx)
1016                 goto resource_error;
1017
1018         if (BNXT_HAS_RING_GRPS(bp) &&
1019             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1020                 goto resource_error;
1021
1022         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1023             bp->max_vnics < eth_dev->data->nb_rx_queues)
1024                 goto resource_error;
1025
1026         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1027         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1028
1029         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1030                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1031         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1032
1033         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1034                 eth_dev->data->mtu =
1035                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1036                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1037                         BNXT_NUM_VLANS;
1038                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1039         }
1040         return 0;
1041
1042 resource_error:
1043         PMD_DRV_LOG(ERR,
1044                     "Insufficient resources to support requested config\n");
1045         PMD_DRV_LOG(ERR,
1046                     "Num Queues Requested: Tx %d, Rx %d\n",
1047                     eth_dev->data->nb_tx_queues,
1048                     eth_dev->data->nb_rx_queues);
1049         PMD_DRV_LOG(ERR,
1050                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1051                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1052                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1053         return -ENOSPC;
1054 }
1055
1056 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1057 {
1058         struct rte_eth_link *link = &eth_dev->data->dev_link;
1059
1060         if (link->link_status)
1061                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1062                         eth_dev->data->port_id,
1063                         (uint32_t)link->link_speed,
1064                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1065                         ("full-duplex") : ("half-duplex\n"));
1066         else
1067                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1068                         eth_dev->data->port_id);
1069 }
1070
1071 /*
1072  * Determine whether the current configuration requires support for scattered
1073  * receive; return 1 if scattered receive is required and 0 if not.
1074  */
1075 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1076 {
1077         uint16_t buf_size;
1078         int i;
1079
1080         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1081                 return 1;
1082
1083         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1084                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1085
1086                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1087                                       RTE_PKTMBUF_HEADROOM);
1088                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1089                         return 1;
1090         }
1091         return 0;
1092 }
1093
1094 static eth_rx_burst_t
1095 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1096 {
1097         struct bnxt *bp = eth_dev->data->dev_private;
1098
1099 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1100 #ifndef RTE_LIBRTE_IEEE1588
1101         /*
1102          * Vector mode receive can be enabled only if scatter rx is not
1103          * in use and rx offloads are limited to VLAN stripping and
1104          * CRC stripping.
1105          */
1106         if (!eth_dev->data->scattered_rx &&
1107             !(eth_dev->data->dev_conf.rxmode.offloads &
1108               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1109                 DEV_RX_OFFLOAD_KEEP_CRC |
1110                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1111                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1112                 DEV_RX_OFFLOAD_UDP_CKSUM |
1113                 DEV_RX_OFFLOAD_TCP_CKSUM |
1114                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1115                 DEV_RX_OFFLOAD_RSS_HASH |
1116                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1117             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) {
1118                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1119                             eth_dev->data->port_id);
1120                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1121                 return bnxt_recv_pkts_vec;
1122         }
1123         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1124                     eth_dev->data->port_id);
1125         PMD_DRV_LOG(INFO,
1126                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1127                     eth_dev->data->port_id,
1128                     eth_dev->data->scattered_rx,
1129                     eth_dev->data->dev_conf.rxmode.offloads);
1130 #endif
1131 #endif
1132         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1133         return bnxt_recv_pkts;
1134 }
1135
1136 static eth_tx_burst_t
1137 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1138 {
1139 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1140 #ifndef RTE_LIBRTE_IEEE1588
1141         struct bnxt *bp = eth_dev->data->dev_private;
1142
1143         /*
1144          * Vector mode transmit can be enabled only if not using scatter rx
1145          * or tx offloads.
1146          */
1147         if (!eth_dev->data->scattered_rx &&
1148             !eth_dev->data->dev_conf.txmode.offloads &&
1149             !BNXT_TRUFLOW_EN(bp)) {
1150                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1151                             eth_dev->data->port_id);
1152                 return bnxt_xmit_pkts_vec;
1153         }
1154         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1155                     eth_dev->data->port_id);
1156         PMD_DRV_LOG(INFO,
1157                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1158                     eth_dev->data->port_id,
1159                     eth_dev->data->scattered_rx,
1160                     eth_dev->data->dev_conf.txmode.offloads);
1161 #endif
1162 #endif
1163         return bnxt_xmit_pkts;
1164 }
1165
1166 static int bnxt_handle_if_change_status(struct bnxt *bp)
1167 {
1168         int rc;
1169
1170         /* Since fw has undergone a reset and lost all contexts,
1171          * set fatal flag to not issue hwrm during cleanup
1172          */
1173         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1174         bnxt_uninit_resources(bp, true);
1175
1176         /* clear fatal flag so that re-init happens */
1177         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1178         rc = bnxt_init_resources(bp, true);
1179
1180         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1181
1182         return rc;
1183 }
1184
1185 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1186 {
1187         struct bnxt *bp = eth_dev->data->dev_private;
1188         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1189         int vlan_mask = 0;
1190         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1191
1192         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1193                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1194                 return -EINVAL;
1195         }
1196
1197         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1198                 PMD_DRV_LOG(ERR,
1199                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1200                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1201         }
1202
1203         do {
1204                 rc = bnxt_hwrm_if_change(bp, true);
1205                 if (rc == 0 || rc != -EAGAIN)
1206                         break;
1207
1208                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1209         } while (retry_cnt--);
1210
1211         if (rc)
1212                 return rc;
1213
1214         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1215                 rc = bnxt_handle_if_change_status(bp);
1216                 if (rc)
1217                         return rc;
1218         }
1219
1220         bnxt_enable_int(bp);
1221
1222         rc = bnxt_init_chip(bp);
1223         if (rc)
1224                 goto error;
1225
1226         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1227         eth_dev->data->dev_started = 1;
1228
1229         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1230
1231         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1232                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1233         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1234                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1235         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1236         if (rc)
1237                 goto error;
1238
1239         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1240         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1241
1242         pthread_mutex_lock(&bp->def_cp_lock);
1243         bnxt_schedule_fw_health_check(bp);
1244         pthread_mutex_unlock(&bp->def_cp_lock);
1245
1246         bnxt_ulp_init(bp);
1247
1248         return 0;
1249
1250 error:
1251         bnxt_shutdown_nic(bp);
1252         bnxt_free_tx_mbufs(bp);
1253         bnxt_free_rx_mbufs(bp);
1254         bnxt_hwrm_if_change(bp, false);
1255         eth_dev->data->dev_started = 0;
1256         return rc;
1257 }
1258
1259 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1260 {
1261         struct bnxt *bp = eth_dev->data->dev_private;
1262         int rc = 0;
1263
1264         if (!bp->link_info->link_up)
1265                 rc = bnxt_set_hwrm_link_config(bp, true);
1266         if (!rc)
1267                 eth_dev->data->dev_link.link_status = 1;
1268
1269         bnxt_print_link_info(eth_dev);
1270         return rc;
1271 }
1272
1273 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1274 {
1275         struct bnxt *bp = eth_dev->data->dev_private;
1276
1277         eth_dev->data->dev_link.link_status = 0;
1278         bnxt_set_hwrm_link_config(bp, false);
1279         bp->link_info->link_up = 0;
1280
1281         return 0;
1282 }
1283
1284 static void bnxt_free_switch_domain(struct bnxt *bp)
1285 {
1286         if (bp->switch_domain_id)
1287                 rte_eth_switch_domain_free(bp->switch_domain_id);
1288 }
1289
1290 /* Unload the driver, release resources */
1291 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1292 {
1293         struct bnxt *bp = eth_dev->data->dev_private;
1294         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1295         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1296
1297         eth_dev->data->dev_started = 0;
1298         eth_dev->data->scattered_rx = 0;
1299
1300         /* Prevent crashes when queues are still in use */
1301         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1302         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1303
1304         bnxt_disable_int(bp);
1305
1306         /* disable uio/vfio intr/eventfd mapping */
1307         rte_intr_disable(intr_handle);
1308
1309         bnxt_ulp_destroy_df_rules(bp, false);
1310         bnxt_ulp_deinit(bp);
1311
1312         bnxt_cancel_fw_health_check(bp);
1313
1314         bnxt_dev_set_link_down_op(eth_dev);
1315
1316         /* Wait for link to be reset and the async notification to process.
1317          * During reset recovery, there is no need to wait and
1318          * VF/NPAR functions do not have privilege to change PHY config.
1319          */
1320         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1321                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1322
1323         /* Clean queue intr-vector mapping */
1324         rte_intr_efd_disable(intr_handle);
1325         if (intr_handle->intr_vec != NULL) {
1326                 rte_free(intr_handle->intr_vec);
1327                 intr_handle->intr_vec = NULL;
1328         }
1329
1330         bnxt_hwrm_port_clr_stats(bp);
1331         bnxt_free_tx_mbufs(bp);
1332         bnxt_free_rx_mbufs(bp);
1333         /* Process any remaining notifications in default completion queue */
1334         bnxt_int_handler(eth_dev);
1335         bnxt_shutdown_nic(bp);
1336         bnxt_hwrm_if_change(bp, false);
1337
1338         rte_free(bp->mark_table);
1339         bp->mark_table = NULL;
1340
1341         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1342         bp->rx_cosq_cnt = 0;
1343         /* All filters are deleted on a port stop. */
1344         if (BNXT_FLOW_XSTATS_EN(bp))
1345                 bp->flow_stat->flow_count = 0;
1346 }
1347
1348 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1349 {
1350         struct bnxt *bp = eth_dev->data->dev_private;
1351
1352         /* cancel the recovery handler before remove dev */
1353         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1354         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1355         bnxt_cancel_fc_thread(bp);
1356
1357         if (eth_dev->data->dev_started)
1358                 bnxt_dev_stop_op(eth_dev);
1359
1360         bnxt_free_switch_domain(bp);
1361
1362         bnxt_uninit_resources(bp, false);
1363
1364         bnxt_free_leds_info(bp);
1365         bnxt_free_cos_queues(bp);
1366         bnxt_free_link_info(bp);
1367         bnxt_free_pf_info(bp);
1368         bnxt_free_parent_info(bp);
1369
1370         eth_dev->dev_ops = NULL;
1371         eth_dev->rx_pkt_burst = NULL;
1372         eth_dev->tx_pkt_burst = NULL;
1373
1374         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1375         bp->tx_mem_zone = NULL;
1376         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1377         bp->rx_mem_zone = NULL;
1378
1379         bnxt_hwrm_free_vf_info(bp);
1380
1381         rte_free(bp->grp_info);
1382         bp->grp_info = NULL;
1383 }
1384
1385 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1386                                     uint32_t index)
1387 {
1388         struct bnxt *bp = eth_dev->data->dev_private;
1389         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1390         struct bnxt_vnic_info *vnic;
1391         struct bnxt_filter_info *filter, *temp_filter;
1392         uint32_t i;
1393
1394         if (is_bnxt_in_error(bp))
1395                 return;
1396
1397         /*
1398          * Loop through all VNICs from the specified filter flow pools to
1399          * remove the corresponding MAC addr filter
1400          */
1401         for (i = 0; i < bp->nr_vnics; i++) {
1402                 if (!(pool_mask & (1ULL << i)))
1403                         continue;
1404
1405                 vnic = &bp->vnic_info[i];
1406                 filter = STAILQ_FIRST(&vnic->filter);
1407                 while (filter) {
1408                         temp_filter = STAILQ_NEXT(filter, next);
1409                         if (filter->mac_index == index) {
1410                                 STAILQ_REMOVE(&vnic->filter, filter,
1411                                                 bnxt_filter_info, next);
1412                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1413                                 bnxt_free_filter(bp, filter);
1414                         }
1415                         filter = temp_filter;
1416                 }
1417         }
1418 }
1419
1420 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1421                                struct rte_ether_addr *mac_addr, uint32_t index,
1422                                uint32_t pool)
1423 {
1424         struct bnxt_filter_info *filter;
1425         int rc = 0;
1426
1427         /* Attach requested MAC address to the new l2_filter */
1428         STAILQ_FOREACH(filter, &vnic->filter, next) {
1429                 if (filter->mac_index == index) {
1430                         PMD_DRV_LOG(DEBUG,
1431                                     "MAC addr already existed for pool %d\n",
1432                                     pool);
1433                         return 0;
1434                 }
1435         }
1436
1437         filter = bnxt_alloc_filter(bp);
1438         if (!filter) {
1439                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1440                 return -ENODEV;
1441         }
1442
1443         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1444          * if the MAC that's been programmed now is a different one, then,
1445          * copy that addr to filter->l2_addr
1446          */
1447         if (mac_addr)
1448                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1449         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1450
1451         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1452         if (!rc) {
1453                 filter->mac_index = index;
1454                 if (filter->mac_index == 0)
1455                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1456                 else
1457                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1458         } else {
1459                 bnxt_free_filter(bp, filter);
1460         }
1461
1462         return rc;
1463 }
1464
1465 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1466                                 struct rte_ether_addr *mac_addr,
1467                                 uint32_t index, uint32_t pool)
1468 {
1469         struct bnxt *bp = eth_dev->data->dev_private;
1470         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1471         int rc = 0;
1472
1473         rc = is_bnxt_in_error(bp);
1474         if (rc)
1475                 return rc;
1476
1477         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1478                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1479                 return -ENOTSUP;
1480         }
1481
1482         if (!vnic) {
1483                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1484                 return -EINVAL;
1485         }
1486
1487         /* Filter settings will get applied when port is started */
1488         if (!eth_dev->data->dev_started)
1489                 return 0;
1490
1491         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1492
1493         return rc;
1494 }
1495
1496 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1497                      bool exp_link_status)
1498 {
1499         int rc = 0;
1500         struct bnxt *bp = eth_dev->data->dev_private;
1501         struct rte_eth_link new;
1502         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1503                   BNXT_LINK_DOWN_WAIT_CNT;
1504
1505         rc = is_bnxt_in_error(bp);
1506         if (rc)
1507                 return rc;
1508
1509         memset(&new, 0, sizeof(new));
1510         do {
1511                 /* Retrieve link info from hardware */
1512                 rc = bnxt_get_hwrm_link_config(bp, &new);
1513                 if (rc) {
1514                         new.link_speed = ETH_LINK_SPEED_100M;
1515                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1516                         PMD_DRV_LOG(ERR,
1517                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1518                         goto out;
1519                 }
1520
1521                 if (!wait_to_complete || new.link_status == exp_link_status)
1522                         break;
1523
1524                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1525         } while (cnt--);
1526
1527 out:
1528         /* Timed out or success */
1529         if (new.link_status != eth_dev->data->dev_link.link_status ||
1530         new.link_speed != eth_dev->data->dev_link.link_speed) {
1531                 rte_eth_linkstatus_set(eth_dev, &new);
1532
1533                 rte_eth_dev_callback_process(eth_dev,
1534                                              RTE_ETH_EVENT_INTR_LSC,
1535                                              NULL);
1536
1537                 bnxt_print_link_info(eth_dev);
1538         }
1539
1540         return rc;
1541 }
1542
1543 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1544                         int wait_to_complete)
1545 {
1546         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1547 }
1548
1549 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1550 {
1551         struct bnxt *bp = eth_dev->data->dev_private;
1552         struct bnxt_vnic_info *vnic;
1553         uint32_t old_flags;
1554         int rc;
1555
1556         rc = is_bnxt_in_error(bp);
1557         if (rc)
1558                 return rc;
1559
1560         /* Filter settings will get applied when port is started */
1561         if (!eth_dev->data->dev_started)
1562                 return 0;
1563
1564         if (bp->vnic_info == NULL)
1565                 return 0;
1566
1567         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1568
1569         old_flags = vnic->flags;
1570         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1571         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1572         if (rc != 0)
1573                 vnic->flags = old_flags;
1574
1575         return rc;
1576 }
1577
1578 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1579 {
1580         struct bnxt *bp = eth_dev->data->dev_private;
1581         struct bnxt_vnic_info *vnic;
1582         uint32_t old_flags;
1583         int rc;
1584
1585         rc = is_bnxt_in_error(bp);
1586         if (rc)
1587                 return rc;
1588
1589         /* Filter settings will get applied when port is started */
1590         if (!eth_dev->data->dev_started)
1591                 return 0;
1592
1593         if (bp->vnic_info == NULL)
1594                 return 0;
1595
1596         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1597
1598         old_flags = vnic->flags;
1599         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1600         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1601         if (rc != 0)
1602                 vnic->flags = old_flags;
1603
1604         bnxt_ulp_create_df_rules(bp);
1605
1606         return rc;
1607 }
1608
1609 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1610 {
1611         struct bnxt *bp = eth_dev->data->dev_private;
1612         struct bnxt_vnic_info *vnic;
1613         uint32_t old_flags;
1614         int rc;
1615
1616         rc = is_bnxt_in_error(bp);
1617         if (rc)
1618                 return rc;
1619
1620         /* Filter settings will get applied when port is started */
1621         if (!eth_dev->data->dev_started)
1622                 return 0;
1623
1624         if (bp->vnic_info == NULL)
1625                 return 0;
1626
1627         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1628
1629         old_flags = vnic->flags;
1630         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1631         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1632         if (rc != 0)
1633                 vnic->flags = old_flags;
1634
1635         return rc;
1636 }
1637
1638 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1639 {
1640         struct bnxt *bp = eth_dev->data->dev_private;
1641         struct bnxt_vnic_info *vnic;
1642         uint32_t old_flags;
1643         int rc;
1644
1645         rc = is_bnxt_in_error(bp);
1646         if (rc)
1647                 return rc;
1648
1649         /* Filter settings will get applied when port is started */
1650         if (!eth_dev->data->dev_started)
1651                 return 0;
1652
1653         if (bp->vnic_info == NULL)
1654                 return 0;
1655
1656         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1657
1658         old_flags = vnic->flags;
1659         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1660         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1661         if (rc != 0)
1662                 vnic->flags = old_flags;
1663
1664         return rc;
1665 }
1666
1667 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1668 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1669 {
1670         if (qid >= bp->rx_nr_rings)
1671                 return NULL;
1672
1673         return bp->eth_dev->data->rx_queues[qid];
1674 }
1675
1676 /* Return rxq corresponding to a given rss table ring/group ID. */
1677 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1678 {
1679         struct bnxt_rx_queue *rxq;
1680         unsigned int i;
1681
1682         if (!BNXT_HAS_RING_GRPS(bp)) {
1683                 for (i = 0; i < bp->rx_nr_rings; i++) {
1684                         rxq = bp->eth_dev->data->rx_queues[i];
1685                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1686                                 return rxq->index;
1687                 }
1688         } else {
1689                 for (i = 0; i < bp->rx_nr_rings; i++) {
1690                         if (bp->grp_info[i].fw_grp_id == fwr)
1691                                 return i;
1692                 }
1693         }
1694
1695         return INVALID_HW_RING_ID;
1696 }
1697
1698 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1699                             struct rte_eth_rss_reta_entry64 *reta_conf,
1700                             uint16_t reta_size)
1701 {
1702         struct bnxt *bp = eth_dev->data->dev_private;
1703         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1704         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1705         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1706         uint16_t idx, sft;
1707         int i, rc;
1708
1709         rc = is_bnxt_in_error(bp);
1710         if (rc)
1711                 return rc;
1712
1713         if (!vnic->rss_table)
1714                 return -EINVAL;
1715
1716         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1717                 return -EINVAL;
1718
1719         if (reta_size != tbl_size) {
1720                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1721                         "(%d) must equal the size supported by the hardware "
1722                         "(%d)\n", reta_size, tbl_size);
1723                 return -EINVAL;
1724         }
1725
1726         for (i = 0; i < reta_size; i++) {
1727                 struct bnxt_rx_queue *rxq;
1728
1729                 idx = i / RTE_RETA_GROUP_SIZE;
1730                 sft = i % RTE_RETA_GROUP_SIZE;
1731
1732                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1733                         continue;
1734
1735                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1736                 if (!rxq) {
1737                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1738                         return -EINVAL;
1739                 }
1740
1741                 if (BNXT_CHIP_THOR(bp)) {
1742                         vnic->rss_table[i * 2] =
1743                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1744                         vnic->rss_table[i * 2 + 1] =
1745                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1746                 } else {
1747                         vnic->rss_table[i] =
1748                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1749                 }
1750         }
1751
1752         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1753         return 0;
1754 }
1755
1756 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1757                               struct rte_eth_rss_reta_entry64 *reta_conf,
1758                               uint16_t reta_size)
1759 {
1760         struct bnxt *bp = eth_dev->data->dev_private;
1761         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1762         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1763         uint16_t idx, sft, i;
1764         int rc;
1765
1766         rc = is_bnxt_in_error(bp);
1767         if (rc)
1768                 return rc;
1769
1770         /* Retrieve from the default VNIC */
1771         if (!vnic)
1772                 return -EINVAL;
1773         if (!vnic->rss_table)
1774                 return -EINVAL;
1775
1776         if (reta_size != tbl_size) {
1777                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1778                         "(%d) must equal the size supported by the hardware "
1779                         "(%d)\n", reta_size, tbl_size);
1780                 return -EINVAL;
1781         }
1782
1783         for (idx = 0, i = 0; i < reta_size; i++) {
1784                 idx = i / RTE_RETA_GROUP_SIZE;
1785                 sft = i % RTE_RETA_GROUP_SIZE;
1786
1787                 if (reta_conf[idx].mask & (1ULL << sft)) {
1788                         uint16_t qid;
1789
1790                         if (BNXT_CHIP_THOR(bp))
1791                                 qid = bnxt_rss_to_qid(bp,
1792                                                       vnic->rss_table[i * 2]);
1793                         else
1794                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1795
1796                         if (qid == INVALID_HW_RING_ID) {
1797                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1798                                 return -EINVAL;
1799                         }
1800                         reta_conf[idx].reta[sft] = qid;
1801                 }
1802         }
1803
1804         return 0;
1805 }
1806
1807 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1808                                    struct rte_eth_rss_conf *rss_conf)
1809 {
1810         struct bnxt *bp = eth_dev->data->dev_private;
1811         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1812         struct bnxt_vnic_info *vnic;
1813         int rc;
1814
1815         rc = is_bnxt_in_error(bp);
1816         if (rc)
1817                 return rc;
1818
1819         /*
1820          * If RSS enablement were different than dev_configure,
1821          * then return -EINVAL
1822          */
1823         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1824                 if (!rss_conf->rss_hf)
1825                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1826         } else {
1827                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1828                         return -EINVAL;
1829         }
1830
1831         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1832         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1833                rss_conf,
1834                sizeof(*rss_conf));
1835
1836         /* Update the default RSS VNIC(s) */
1837         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1838         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1839
1840         /*
1841          * If hashkey is not specified, use the previously configured
1842          * hashkey
1843          */
1844         if (!rss_conf->rss_key)
1845                 goto rss_config;
1846
1847         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1848                 PMD_DRV_LOG(ERR,
1849                             "Invalid hashkey length, should be 16 bytes\n");
1850                 return -EINVAL;
1851         }
1852         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1853
1854 rss_config:
1855         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1856         return 0;
1857 }
1858
1859 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1860                                      struct rte_eth_rss_conf *rss_conf)
1861 {
1862         struct bnxt *bp = eth_dev->data->dev_private;
1863         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1864         int len, rc;
1865         uint32_t hash_types;
1866
1867         rc = is_bnxt_in_error(bp);
1868         if (rc)
1869                 return rc;
1870
1871         /* RSS configuration is the same for all VNICs */
1872         if (vnic && vnic->rss_hash_key) {
1873                 if (rss_conf->rss_key) {
1874                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1875                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1876                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1877                 }
1878
1879                 hash_types = vnic->hash_type;
1880                 rss_conf->rss_hf = 0;
1881                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1882                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1883                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1884                 }
1885                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1886                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1887                         hash_types &=
1888                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1889                 }
1890                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1891                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1892                         hash_types &=
1893                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1894                 }
1895                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1896                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1897                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1898                 }
1899                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1900                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1901                         hash_types &=
1902                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1903                 }
1904                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1905                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1906                         hash_types &=
1907                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1908                 }
1909                 if (hash_types) {
1910                         PMD_DRV_LOG(ERR,
1911                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1912                                 vnic->hash_type);
1913                         return -ENOTSUP;
1914                 }
1915         } else {
1916                 rss_conf->rss_hf = 0;
1917         }
1918         return 0;
1919 }
1920
1921 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1922                                struct rte_eth_fc_conf *fc_conf)
1923 {
1924         struct bnxt *bp = dev->data->dev_private;
1925         struct rte_eth_link link_info;
1926         int rc;
1927
1928         rc = is_bnxt_in_error(bp);
1929         if (rc)
1930                 return rc;
1931
1932         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1933         if (rc)
1934                 return rc;
1935
1936         memset(fc_conf, 0, sizeof(*fc_conf));
1937         if (bp->link_info->auto_pause)
1938                 fc_conf->autoneg = 1;
1939         switch (bp->link_info->pause) {
1940         case 0:
1941                 fc_conf->mode = RTE_FC_NONE;
1942                 break;
1943         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1944                 fc_conf->mode = RTE_FC_TX_PAUSE;
1945                 break;
1946         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1947                 fc_conf->mode = RTE_FC_RX_PAUSE;
1948                 break;
1949         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1950                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1951                 fc_conf->mode = RTE_FC_FULL;
1952                 break;
1953         }
1954         return 0;
1955 }
1956
1957 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1958                                struct rte_eth_fc_conf *fc_conf)
1959 {
1960         struct bnxt *bp = dev->data->dev_private;
1961         int rc;
1962
1963         rc = is_bnxt_in_error(bp);
1964         if (rc)
1965                 return rc;
1966
1967         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1968                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1969                 return -ENOTSUP;
1970         }
1971
1972         switch (fc_conf->mode) {
1973         case RTE_FC_NONE:
1974                 bp->link_info->auto_pause = 0;
1975                 bp->link_info->force_pause = 0;
1976                 break;
1977         case RTE_FC_RX_PAUSE:
1978                 if (fc_conf->autoneg) {
1979                         bp->link_info->auto_pause =
1980                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1981                         bp->link_info->force_pause = 0;
1982                 } else {
1983                         bp->link_info->auto_pause = 0;
1984                         bp->link_info->force_pause =
1985                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1986                 }
1987                 break;
1988         case RTE_FC_TX_PAUSE:
1989                 if (fc_conf->autoneg) {
1990                         bp->link_info->auto_pause =
1991                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1992                         bp->link_info->force_pause = 0;
1993                 } else {
1994                         bp->link_info->auto_pause = 0;
1995                         bp->link_info->force_pause =
1996                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1997                 }
1998                 break;
1999         case RTE_FC_FULL:
2000                 if (fc_conf->autoneg) {
2001                         bp->link_info->auto_pause =
2002                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2003                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2004                         bp->link_info->force_pause = 0;
2005                 } else {
2006                         bp->link_info->auto_pause = 0;
2007                         bp->link_info->force_pause =
2008                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2009                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2010                 }
2011                 break;
2012         }
2013         return bnxt_set_hwrm_link_config(bp, true);
2014 }
2015
2016 /* Add UDP tunneling port */
2017 static int
2018 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2019                          struct rte_eth_udp_tunnel *udp_tunnel)
2020 {
2021         struct bnxt *bp = eth_dev->data->dev_private;
2022         uint16_t tunnel_type = 0;
2023         int rc = 0;
2024
2025         rc = is_bnxt_in_error(bp);
2026         if (rc)
2027                 return rc;
2028
2029         switch (udp_tunnel->prot_type) {
2030         case RTE_TUNNEL_TYPE_VXLAN:
2031                 if (bp->vxlan_port_cnt) {
2032                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2033                                 udp_tunnel->udp_port);
2034                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2035                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2036                                 return -ENOSPC;
2037                         }
2038                         bp->vxlan_port_cnt++;
2039                         return 0;
2040                 }
2041                 tunnel_type =
2042                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2043                 bp->vxlan_port_cnt++;
2044                 break;
2045         case RTE_TUNNEL_TYPE_GENEVE:
2046                 if (bp->geneve_port_cnt) {
2047                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2048                                 udp_tunnel->udp_port);
2049                         if (bp->geneve_port != udp_tunnel->udp_port) {
2050                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2051                                 return -ENOSPC;
2052                         }
2053                         bp->geneve_port_cnt++;
2054                         return 0;
2055                 }
2056                 tunnel_type =
2057                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2058                 bp->geneve_port_cnt++;
2059                 break;
2060         default:
2061                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2062                 return -ENOTSUP;
2063         }
2064         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2065                                              tunnel_type);
2066         return rc;
2067 }
2068
2069 static int
2070 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2071                          struct rte_eth_udp_tunnel *udp_tunnel)
2072 {
2073         struct bnxt *bp = eth_dev->data->dev_private;
2074         uint16_t tunnel_type = 0;
2075         uint16_t port = 0;
2076         int rc = 0;
2077
2078         rc = is_bnxt_in_error(bp);
2079         if (rc)
2080                 return rc;
2081
2082         switch (udp_tunnel->prot_type) {
2083         case RTE_TUNNEL_TYPE_VXLAN:
2084                 if (!bp->vxlan_port_cnt) {
2085                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2086                         return -EINVAL;
2087                 }
2088                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2089                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2090                                 udp_tunnel->udp_port, bp->vxlan_port);
2091                         return -EINVAL;
2092                 }
2093                 if (--bp->vxlan_port_cnt)
2094                         return 0;
2095
2096                 tunnel_type =
2097                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2098                 port = bp->vxlan_fw_dst_port_id;
2099                 break;
2100         case RTE_TUNNEL_TYPE_GENEVE:
2101                 if (!bp->geneve_port_cnt) {
2102                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2103                         return -EINVAL;
2104                 }
2105                 if (bp->geneve_port != udp_tunnel->udp_port) {
2106                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2107                                 udp_tunnel->udp_port, bp->geneve_port);
2108                         return -EINVAL;
2109                 }
2110                 if (--bp->geneve_port_cnt)
2111                         return 0;
2112
2113                 tunnel_type =
2114                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2115                 port = bp->geneve_fw_dst_port_id;
2116                 break;
2117         default:
2118                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2119                 return -ENOTSUP;
2120         }
2121
2122         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2123         if (!rc) {
2124                 if (tunnel_type ==
2125                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2126                         bp->vxlan_port = 0;
2127                 if (tunnel_type ==
2128                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2129                         bp->geneve_port = 0;
2130         }
2131         return rc;
2132 }
2133
2134 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2135 {
2136         struct bnxt_filter_info *filter;
2137         struct bnxt_vnic_info *vnic;
2138         int rc = 0;
2139         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2140
2141         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2142         filter = STAILQ_FIRST(&vnic->filter);
2143         while (filter) {
2144                 /* Search for this matching MAC+VLAN filter */
2145                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2146                         /* Delete the filter */
2147                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2148                         if (rc)
2149                                 return rc;
2150                         STAILQ_REMOVE(&vnic->filter, filter,
2151                                       bnxt_filter_info, next);
2152                         bnxt_free_filter(bp, filter);
2153                         PMD_DRV_LOG(INFO,
2154                                     "Deleted vlan filter for %d\n",
2155                                     vlan_id);
2156                         return 0;
2157                 }
2158                 filter = STAILQ_NEXT(filter, next);
2159         }
2160         return -ENOENT;
2161 }
2162
2163 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2164 {
2165         struct bnxt_filter_info *filter;
2166         struct bnxt_vnic_info *vnic;
2167         int rc = 0;
2168         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2169                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2170         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2171
2172         /* Implementation notes on the use of VNIC in this command:
2173          *
2174          * By default, these filters belong to default vnic for the function.
2175          * Once these filters are set up, only destination VNIC can be modified.
2176          * If the destination VNIC is not specified in this command,
2177          * then the HWRM shall only create an l2 context id.
2178          */
2179
2180         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2181         filter = STAILQ_FIRST(&vnic->filter);
2182         /* Check if the VLAN has already been added */
2183         while (filter) {
2184                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2185                         return -EEXIST;
2186
2187                 filter = STAILQ_NEXT(filter, next);
2188         }
2189
2190         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2191          * command to create MAC+VLAN filter with the right flags, enables set.
2192          */
2193         filter = bnxt_alloc_filter(bp);
2194         if (!filter) {
2195                 PMD_DRV_LOG(ERR,
2196                             "MAC/VLAN filter alloc failed\n");
2197                 return -ENOMEM;
2198         }
2199         /* MAC + VLAN ID filter */
2200         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2201          * untagged packets are received
2202          *
2203          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2204          * packets and only the programmed vlan's packets are received
2205          */
2206         filter->l2_ivlan = vlan_id;
2207         filter->l2_ivlan_mask = 0x0FFF;
2208         filter->enables |= en;
2209         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2210
2211         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2212         if (rc) {
2213                 /* Free the newly allocated filter as we were
2214                  * not able to create the filter in hardware.
2215                  */
2216                 bnxt_free_filter(bp, filter);
2217                 return rc;
2218         }
2219
2220         filter->mac_index = 0;
2221         /* Add this new filter to the list */
2222         if (vlan_id == 0)
2223                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2224         else
2225                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2226
2227         PMD_DRV_LOG(INFO,
2228                     "Added Vlan filter for %d\n", vlan_id);
2229         return rc;
2230 }
2231
2232 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2233                 uint16_t vlan_id, int on)
2234 {
2235         struct bnxt *bp = eth_dev->data->dev_private;
2236         int rc;
2237
2238         rc = is_bnxt_in_error(bp);
2239         if (rc)
2240                 return rc;
2241
2242         if (!eth_dev->data->dev_started) {
2243                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2244                 return -EINVAL;
2245         }
2246
2247         /* These operations apply to ALL existing MAC/VLAN filters */
2248         if (on)
2249                 return bnxt_add_vlan_filter(bp, vlan_id);
2250         else
2251                 return bnxt_del_vlan_filter(bp, vlan_id);
2252 }
2253
2254 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2255                                     struct bnxt_vnic_info *vnic)
2256 {
2257         struct bnxt_filter_info *filter;
2258         int rc;
2259
2260         filter = STAILQ_FIRST(&vnic->filter);
2261         while (filter) {
2262                 if (filter->mac_index == 0 &&
2263                     !memcmp(filter->l2_addr, bp->mac_addr,
2264                             RTE_ETHER_ADDR_LEN)) {
2265                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2266                         if (!rc) {
2267                                 STAILQ_REMOVE(&vnic->filter, filter,
2268                                               bnxt_filter_info, next);
2269                                 bnxt_free_filter(bp, filter);
2270                         }
2271                         return rc;
2272                 }
2273                 filter = STAILQ_NEXT(filter, next);
2274         }
2275         return 0;
2276 }
2277
2278 static int
2279 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2280 {
2281         struct bnxt_vnic_info *vnic;
2282         unsigned int i;
2283         int rc;
2284
2285         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2286         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2287                 /* Remove any VLAN filters programmed */
2288                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2289                         bnxt_del_vlan_filter(bp, i);
2290
2291                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2292                 if (rc)
2293                         return rc;
2294         } else {
2295                 /* Default filter will allow packets that match the
2296                  * dest mac. So, it has to be deleted, otherwise, we
2297                  * will endup receiving vlan packets for which the
2298                  * filter is not programmed, when hw-vlan-filter
2299                  * configuration is ON
2300                  */
2301                 bnxt_del_dflt_mac_filter(bp, vnic);
2302                 /* This filter will allow only untagged packets */
2303                 bnxt_add_vlan_filter(bp, 0);
2304         }
2305         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2306                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2307
2308         return 0;
2309 }
2310
2311 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2312 {
2313         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2314         unsigned int i;
2315         int rc;
2316
2317         /* Destroy vnic filters and vnic */
2318         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2319             DEV_RX_OFFLOAD_VLAN_FILTER) {
2320                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2321                         bnxt_del_vlan_filter(bp, i);
2322         }
2323         bnxt_del_dflt_mac_filter(bp, vnic);
2324
2325         rc = bnxt_hwrm_vnic_free(bp, vnic);
2326         if (rc)
2327                 return rc;
2328
2329         rte_free(vnic->fw_grp_ids);
2330         vnic->fw_grp_ids = NULL;
2331
2332         vnic->rx_queue_cnt = 0;
2333
2334         return 0;
2335 }
2336
2337 static int
2338 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2339 {
2340         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2341         int rc;
2342
2343         /* Destroy, recreate and reconfigure the default vnic */
2344         rc = bnxt_free_one_vnic(bp, 0);
2345         if (rc)
2346                 return rc;
2347
2348         /* default vnic 0 */
2349         rc = bnxt_setup_one_vnic(bp, 0);
2350         if (rc)
2351                 return rc;
2352
2353         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2354             DEV_RX_OFFLOAD_VLAN_FILTER) {
2355                 rc = bnxt_add_vlan_filter(bp, 0);
2356                 if (rc)
2357                         return rc;
2358                 rc = bnxt_restore_vlan_filters(bp);
2359                 if (rc)
2360                         return rc;
2361         } else {
2362                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2363                 if (rc)
2364                         return rc;
2365         }
2366
2367         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2368         if (rc)
2369                 return rc;
2370
2371         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2372                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2373
2374         return rc;
2375 }
2376
2377 static int
2378 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2379 {
2380         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2381         struct bnxt *bp = dev->data->dev_private;
2382         int rc;
2383
2384         rc = is_bnxt_in_error(bp);
2385         if (rc)
2386                 return rc;
2387
2388         /* Filter settings will get applied when port is started */
2389         if (!dev->data->dev_started)
2390                 return 0;
2391
2392         if (mask & ETH_VLAN_FILTER_MASK) {
2393                 /* Enable or disable VLAN filtering */
2394                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2395                 if (rc)
2396                         return rc;
2397         }
2398
2399         if (mask & ETH_VLAN_STRIP_MASK) {
2400                 /* Enable or disable VLAN stripping */
2401                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2402                 if (rc)
2403                         return rc;
2404         }
2405
2406         if (mask & ETH_VLAN_EXTEND_MASK) {
2407                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2408                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2409                 else
2410                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2411         }
2412
2413         return 0;
2414 }
2415
2416 static int
2417 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2418                       uint16_t tpid)
2419 {
2420         struct bnxt *bp = dev->data->dev_private;
2421         int qinq = dev->data->dev_conf.rxmode.offloads &
2422                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2423
2424         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2425             vlan_type != ETH_VLAN_TYPE_OUTER) {
2426                 PMD_DRV_LOG(ERR,
2427                             "Unsupported vlan type.");
2428                 return -EINVAL;
2429         }
2430         if (!qinq) {
2431                 PMD_DRV_LOG(ERR,
2432                             "QinQ not enabled. Needs to be ON as we can "
2433                             "accelerate only outer vlan\n");
2434                 return -EINVAL;
2435         }
2436
2437         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2438                 switch (tpid) {
2439                 case RTE_ETHER_TYPE_QINQ:
2440                         bp->outer_tpid_bd =
2441                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2442                                 break;
2443                 case RTE_ETHER_TYPE_VLAN:
2444                         bp->outer_tpid_bd =
2445                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2446                                 break;
2447                 case RTE_ETHER_TYPE_QINQ1:
2448                         bp->outer_tpid_bd =
2449                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2450                                 break;
2451                 case RTE_ETHER_TYPE_QINQ2:
2452                         bp->outer_tpid_bd =
2453                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2454                                 break;
2455                 case RTE_ETHER_TYPE_QINQ3:
2456                         bp->outer_tpid_bd =
2457                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2458                                 break;
2459                 default:
2460                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2461                         return -EINVAL;
2462                 }
2463                 bp->outer_tpid_bd |= tpid;
2464                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2465         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2466                 PMD_DRV_LOG(ERR,
2467                             "Can accelerate only outer vlan in QinQ\n");
2468                 return -EINVAL;
2469         }
2470
2471         return 0;
2472 }
2473
2474 static int
2475 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2476                              struct rte_ether_addr *addr)
2477 {
2478         struct bnxt *bp = dev->data->dev_private;
2479         /* Default Filter is tied to VNIC 0 */
2480         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2481         int rc;
2482
2483         rc = is_bnxt_in_error(bp);
2484         if (rc)
2485                 return rc;
2486
2487         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2488                 return -EPERM;
2489
2490         if (rte_is_zero_ether_addr(addr))
2491                 return -EINVAL;
2492
2493         /* Filter settings will get applied when port is started */
2494         if (!dev->data->dev_started)
2495                 return 0;
2496
2497         /* Check if the requested MAC is already added */
2498         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2499                 return 0;
2500
2501         /* Destroy filter and re-create it */
2502         bnxt_del_dflt_mac_filter(bp, vnic);
2503
2504         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2505         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2506                 /* This filter will allow only untagged packets */
2507                 rc = bnxt_add_vlan_filter(bp, 0);
2508         } else {
2509                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2510         }
2511
2512         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2513         return rc;
2514 }
2515
2516 static int
2517 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2518                           struct rte_ether_addr *mc_addr_set,
2519                           uint32_t nb_mc_addr)
2520 {
2521         struct bnxt *bp = eth_dev->data->dev_private;
2522         char *mc_addr_list = (char *)mc_addr_set;
2523         struct bnxt_vnic_info *vnic;
2524         uint32_t off = 0, i = 0;
2525         int rc;
2526
2527         rc = is_bnxt_in_error(bp);
2528         if (rc)
2529                 return rc;
2530
2531         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2532
2533         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2534                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2535                 goto allmulti;
2536         }
2537
2538         /* TODO Check for Duplicate mcast addresses */
2539         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2540         for (i = 0; i < nb_mc_addr; i++) {
2541                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2542                         RTE_ETHER_ADDR_LEN);
2543                 off += RTE_ETHER_ADDR_LEN;
2544         }
2545
2546         vnic->mc_addr_cnt = i;
2547         if (vnic->mc_addr_cnt)
2548                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2549         else
2550                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2551
2552 allmulti:
2553         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2554 }
2555
2556 static int
2557 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2558 {
2559         struct bnxt *bp = dev->data->dev_private;
2560         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2561         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2562         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2563         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2564         int ret;
2565
2566         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2567                         fw_major, fw_minor, fw_updt, fw_rsvd);
2568
2569         ret += 1; /* add the size of '\0' */
2570         if (fw_size < (uint32_t)ret)
2571                 return ret;
2572         else
2573                 return 0;
2574 }
2575
2576 static void
2577 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2578         struct rte_eth_rxq_info *qinfo)
2579 {
2580         struct bnxt *bp = dev->data->dev_private;
2581         struct bnxt_rx_queue *rxq;
2582
2583         if (is_bnxt_in_error(bp))
2584                 return;
2585
2586         rxq = dev->data->rx_queues[queue_id];
2587
2588         qinfo->mp = rxq->mb_pool;
2589         qinfo->scattered_rx = dev->data->scattered_rx;
2590         qinfo->nb_desc = rxq->nb_rx_desc;
2591
2592         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2593         qinfo->conf.rx_drop_en = 0;
2594         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2595 }
2596
2597 static void
2598 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2599         struct rte_eth_txq_info *qinfo)
2600 {
2601         struct bnxt *bp = dev->data->dev_private;
2602         struct bnxt_tx_queue *txq;
2603
2604         if (is_bnxt_in_error(bp))
2605                 return;
2606
2607         txq = dev->data->tx_queues[queue_id];
2608
2609         qinfo->nb_desc = txq->nb_tx_desc;
2610
2611         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2612         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2613         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2614
2615         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2616         qinfo->conf.tx_rs_thresh = 0;
2617         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2618 }
2619
2620 static const struct {
2621         eth_rx_burst_t pkt_burst;
2622         const char *info;
2623 } bnxt_rx_burst_info[] = {
2624         {bnxt_recv_pkts,        "Scalar"},
2625 #if defined(RTE_ARCH_X86)
2626         {bnxt_recv_pkts_vec,    "Vector SSE"},
2627 #elif defined(RTE_ARCH_ARM64)
2628         {bnxt_recv_pkts_vec,    "Vector Neon"},
2629 #endif
2630 };
2631
2632 static int
2633 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2634                        struct rte_eth_burst_mode *mode)
2635 {
2636         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2637         size_t i;
2638
2639         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2640                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2641                         snprintf(mode->info, sizeof(mode->info), "%s",
2642                                  bnxt_rx_burst_info[i].info);
2643                         return 0;
2644                 }
2645         }
2646
2647         return -EINVAL;
2648 }
2649
2650 static const struct {
2651         eth_tx_burst_t pkt_burst;
2652         const char *info;
2653 } bnxt_tx_burst_info[] = {
2654         {bnxt_xmit_pkts,        "Scalar"},
2655 #if defined(RTE_ARCH_X86)
2656         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2657 #elif defined(RTE_ARCH_ARM64)
2658         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2659 #endif
2660 };
2661
2662 static int
2663 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2664                        struct rte_eth_burst_mode *mode)
2665 {
2666         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2667         size_t i;
2668
2669         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2670                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2671                         snprintf(mode->info, sizeof(mode->info), "%s",
2672                                  bnxt_tx_burst_info[i].info);
2673                         return 0;
2674                 }
2675         }
2676
2677         return -EINVAL;
2678 }
2679
2680 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2681 {
2682         struct bnxt *bp = eth_dev->data->dev_private;
2683         uint32_t new_pkt_size;
2684         uint32_t rc = 0;
2685         uint32_t i;
2686
2687         rc = is_bnxt_in_error(bp);
2688         if (rc)
2689                 return rc;
2690
2691         /* Exit if receive queues are not configured yet */
2692         if (!eth_dev->data->nb_rx_queues)
2693                 return rc;
2694
2695         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2696                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2697
2698         /*
2699          * Disallow any MTU change that would require scattered receive support
2700          * if it is not already enabled.
2701          */
2702         if (eth_dev->data->dev_started &&
2703             !eth_dev->data->scattered_rx &&
2704             (new_pkt_size >
2705              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2706                 PMD_DRV_LOG(ERR,
2707                             "MTU change would require scattered rx support. ");
2708                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2709                 return -EINVAL;
2710         }
2711
2712         if (new_mtu > RTE_ETHER_MTU) {
2713                 bp->flags |= BNXT_FLAG_JUMBO;
2714                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2715                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2716         } else {
2717                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2718                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2719                 bp->flags &= ~BNXT_FLAG_JUMBO;
2720         }
2721
2722         /* Is there a change in mtu setting? */
2723         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2724                 return rc;
2725
2726         for (i = 0; i < bp->nr_vnics; i++) {
2727                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2728                 uint16_t size = 0;
2729
2730                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2731                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2732                 if (rc)
2733                         break;
2734
2735                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2736                 size -= RTE_PKTMBUF_HEADROOM;
2737
2738                 if (size < new_mtu) {
2739                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2740                         if (rc)
2741                                 return rc;
2742                 }
2743         }
2744
2745         if (!rc)
2746                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2747
2748         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2749
2750         return rc;
2751 }
2752
2753 static int
2754 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2755 {
2756         struct bnxt *bp = dev->data->dev_private;
2757         uint16_t vlan = bp->vlan;
2758         int rc;
2759
2760         rc = is_bnxt_in_error(bp);
2761         if (rc)
2762                 return rc;
2763
2764         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2765                 PMD_DRV_LOG(ERR,
2766                         "PVID cannot be modified for this function\n");
2767                 return -ENOTSUP;
2768         }
2769         bp->vlan = on ? pvid : 0;
2770
2771         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2772         if (rc)
2773                 bp->vlan = vlan;
2774         return rc;
2775 }
2776
2777 static int
2778 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2779 {
2780         struct bnxt *bp = dev->data->dev_private;
2781         int rc;
2782
2783         rc = is_bnxt_in_error(bp);
2784         if (rc)
2785                 return rc;
2786
2787         return bnxt_hwrm_port_led_cfg(bp, true);
2788 }
2789
2790 static int
2791 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2792 {
2793         struct bnxt *bp = dev->data->dev_private;
2794         int rc;
2795
2796         rc = is_bnxt_in_error(bp);
2797         if (rc)
2798                 return rc;
2799
2800         return bnxt_hwrm_port_led_cfg(bp, false);
2801 }
2802
2803 static uint32_t
2804 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2805 {
2806         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2807         uint32_t desc = 0, raw_cons = 0, cons;
2808         struct bnxt_cp_ring_info *cpr;
2809         struct bnxt_rx_queue *rxq;
2810         struct rx_pkt_cmpl *rxcmp;
2811         int rc;
2812
2813         rc = is_bnxt_in_error(bp);
2814         if (rc)
2815                 return rc;
2816
2817         rxq = dev->data->rx_queues[rx_queue_id];
2818         cpr = rxq->cp_ring;
2819         raw_cons = cpr->cp_raw_cons;
2820
2821         while (1) {
2822                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2823                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2824                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2825
2826                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2827                         break;
2828                 } else {
2829                         raw_cons++;
2830                         desc++;
2831                 }
2832         }
2833
2834         return desc;
2835 }
2836
2837 static int
2838 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2839 {
2840         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2841         struct bnxt_rx_ring_info *rxr;
2842         struct bnxt_cp_ring_info *cpr;
2843         struct rte_mbuf *rx_buf;
2844         struct rx_pkt_cmpl *rxcmp;
2845         uint32_t cons, cp_cons;
2846         int rc;
2847
2848         if (!rxq)
2849                 return -EINVAL;
2850
2851         rc = is_bnxt_in_error(rxq->bp);
2852         if (rc)
2853                 return rc;
2854
2855         cpr = rxq->cp_ring;
2856         rxr = rxq->rx_ring;
2857
2858         if (offset >= rxq->nb_rx_desc)
2859                 return -EINVAL;
2860
2861         cons = RING_CMP(cpr->cp_ring_struct, offset);
2862         cp_cons = cpr->cp_raw_cons;
2863         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2864
2865         if (cons > cp_cons) {
2866                 if (CMPL_VALID(rxcmp, cpr->valid))
2867                         return RTE_ETH_RX_DESC_DONE;
2868         } else {
2869                 if (CMPL_VALID(rxcmp, !cpr->valid))
2870                         return RTE_ETH_RX_DESC_DONE;
2871         }
2872         rx_buf = rxr->rx_buf_ring[cons];
2873         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2874                 return RTE_ETH_RX_DESC_UNAVAIL;
2875
2876
2877         return RTE_ETH_RX_DESC_AVAIL;
2878 }
2879
2880 static int
2881 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2882 {
2883         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2884         struct bnxt_tx_ring_info *txr;
2885         struct bnxt_cp_ring_info *cpr;
2886         struct bnxt_sw_tx_bd *tx_buf;
2887         struct tx_pkt_cmpl *txcmp;
2888         uint32_t cons, cp_cons;
2889         int rc;
2890
2891         if (!txq)
2892                 return -EINVAL;
2893
2894         rc = is_bnxt_in_error(txq->bp);
2895         if (rc)
2896                 return rc;
2897
2898         cpr = txq->cp_ring;
2899         txr = txq->tx_ring;
2900
2901         if (offset >= txq->nb_tx_desc)
2902                 return -EINVAL;
2903
2904         cons = RING_CMP(cpr->cp_ring_struct, offset);
2905         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2906         cp_cons = cpr->cp_raw_cons;
2907
2908         if (cons > cp_cons) {
2909                 if (CMPL_VALID(txcmp, cpr->valid))
2910                         return RTE_ETH_TX_DESC_UNAVAIL;
2911         } else {
2912                 if (CMPL_VALID(txcmp, !cpr->valid))
2913                         return RTE_ETH_TX_DESC_UNAVAIL;
2914         }
2915         tx_buf = &txr->tx_buf_ring[cons];
2916         if (tx_buf->mbuf == NULL)
2917                 return RTE_ETH_TX_DESC_DONE;
2918
2919         return RTE_ETH_TX_DESC_FULL;
2920 }
2921
2922 static struct bnxt_filter_info *
2923 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2924                                 struct rte_eth_ethertype_filter *efilter,
2925                                 struct bnxt_vnic_info *vnic0,
2926                                 struct bnxt_vnic_info *vnic,
2927                                 int *ret)
2928 {
2929         struct bnxt_filter_info *mfilter = NULL;
2930         int match = 0;
2931         *ret = 0;
2932
2933         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2934                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2935                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2936                         " ethertype filter.", efilter->ether_type);
2937                 *ret = -EINVAL;
2938                 goto exit;
2939         }
2940         if (efilter->queue >= bp->rx_nr_rings) {
2941                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2942                 *ret = -EINVAL;
2943                 goto exit;
2944         }
2945
2946         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2947         vnic = &bp->vnic_info[efilter->queue];
2948         if (vnic == NULL) {
2949                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2950                 *ret = -EINVAL;
2951                 goto exit;
2952         }
2953
2954         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2955                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2956                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2957                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2958                              mfilter->flags ==
2959                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2960                              mfilter->ethertype == efilter->ether_type)) {
2961                                 match = 1;
2962                                 break;
2963                         }
2964                 }
2965         } else {
2966                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2967                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2968                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2969                              mfilter->ethertype == efilter->ether_type &&
2970                              mfilter->flags ==
2971                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2972                                 match = 1;
2973                                 break;
2974                         }
2975         }
2976
2977         if (match)
2978                 *ret = -EEXIST;
2979
2980 exit:
2981         return mfilter;
2982 }
2983
2984 static int
2985 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2986                         enum rte_filter_op filter_op,
2987                         void *arg)
2988 {
2989         struct bnxt *bp = dev->data->dev_private;
2990         struct rte_eth_ethertype_filter *efilter =
2991                         (struct rte_eth_ethertype_filter *)arg;
2992         struct bnxt_filter_info *bfilter, *filter1;
2993         struct bnxt_vnic_info *vnic, *vnic0;
2994         int ret;
2995
2996         if (filter_op == RTE_ETH_FILTER_NOP)
2997                 return 0;
2998
2999         if (arg == NULL) {
3000                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3001                             filter_op);
3002                 return -EINVAL;
3003         }
3004
3005         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3006         vnic = &bp->vnic_info[efilter->queue];
3007
3008         switch (filter_op) {
3009         case RTE_ETH_FILTER_ADD:
3010                 bnxt_match_and_validate_ether_filter(bp, efilter,
3011                                                         vnic0, vnic, &ret);
3012                 if (ret < 0)
3013                         return ret;
3014
3015                 bfilter = bnxt_get_unused_filter(bp);
3016                 if (bfilter == NULL) {
3017                         PMD_DRV_LOG(ERR,
3018                                 "Not enough resources for a new filter.\n");
3019                         return -ENOMEM;
3020                 }
3021                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3022                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3023                        RTE_ETHER_ADDR_LEN);
3024                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3025                        RTE_ETHER_ADDR_LEN);
3026                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3027                 bfilter->ethertype = efilter->ether_type;
3028                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3029
3030                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3031                 if (filter1 == NULL) {
3032                         ret = -EINVAL;
3033                         goto cleanup;
3034                 }
3035                 bfilter->enables |=
3036                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3037                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3038
3039                 bfilter->dst_id = vnic->fw_vnic_id;
3040
3041                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3042                         bfilter->flags =
3043                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3044                 }
3045
3046                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3047                 if (ret)
3048                         goto cleanup;
3049                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3050                 break;
3051         case RTE_ETH_FILTER_DELETE:
3052                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3053                                                         vnic0, vnic, &ret);
3054                 if (ret == -EEXIST) {
3055                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3056
3057                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3058                                       next);
3059                         bnxt_free_filter(bp, filter1);
3060                 } else if (ret == 0) {
3061                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3062                 }
3063                 break;
3064         default:
3065                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3066                 ret = -EINVAL;
3067                 goto error;
3068         }
3069         return ret;
3070 cleanup:
3071         bnxt_free_filter(bp, bfilter);
3072 error:
3073         return ret;
3074 }
3075
3076 static inline int
3077 parse_ntuple_filter(struct bnxt *bp,
3078                     struct rte_eth_ntuple_filter *nfilter,
3079                     struct bnxt_filter_info *bfilter)
3080 {
3081         uint32_t en = 0;
3082
3083         if (nfilter->queue >= bp->rx_nr_rings) {
3084                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3085                 return -EINVAL;
3086         }
3087
3088         switch (nfilter->dst_port_mask) {
3089         case UINT16_MAX:
3090                 bfilter->dst_port_mask = -1;
3091                 bfilter->dst_port = nfilter->dst_port;
3092                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3093                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3094                 break;
3095         default:
3096                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3097                 return -EINVAL;
3098         }
3099
3100         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3101         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3102
3103         switch (nfilter->proto_mask) {
3104         case UINT8_MAX:
3105                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3106                         bfilter->ip_protocol = 17;
3107                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3108                         bfilter->ip_protocol = 6;
3109                 else
3110                         return -EINVAL;
3111                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3112                 break;
3113         default:
3114                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3115                 return -EINVAL;
3116         }
3117
3118         switch (nfilter->dst_ip_mask) {
3119         case UINT32_MAX:
3120                 bfilter->dst_ipaddr_mask[0] = -1;
3121                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3122                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3123                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3124                 break;
3125         default:
3126                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3127                 return -EINVAL;
3128         }
3129
3130         switch (nfilter->src_ip_mask) {
3131         case UINT32_MAX:
3132                 bfilter->src_ipaddr_mask[0] = -1;
3133                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3134                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3135                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3136                 break;
3137         default:
3138                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3139                 return -EINVAL;
3140         }
3141
3142         switch (nfilter->src_port_mask) {
3143         case UINT16_MAX:
3144                 bfilter->src_port_mask = -1;
3145                 bfilter->src_port = nfilter->src_port;
3146                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3147                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3148                 break;
3149         default:
3150                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3151                 return -EINVAL;
3152         }
3153
3154         bfilter->enables = en;
3155         return 0;
3156 }
3157
3158 static struct bnxt_filter_info*
3159 bnxt_match_ntuple_filter(struct bnxt *bp,
3160                          struct bnxt_filter_info *bfilter,
3161                          struct bnxt_vnic_info **mvnic)
3162 {
3163         struct bnxt_filter_info *mfilter = NULL;
3164         int i;
3165
3166         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3167                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3168                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3169                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3170                             bfilter->src_ipaddr_mask[0] ==
3171                             mfilter->src_ipaddr_mask[0] &&
3172                             bfilter->src_port == mfilter->src_port &&
3173                             bfilter->src_port_mask == mfilter->src_port_mask &&
3174                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3175                             bfilter->dst_ipaddr_mask[0] ==
3176                             mfilter->dst_ipaddr_mask[0] &&
3177                             bfilter->dst_port == mfilter->dst_port &&
3178                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3179                             bfilter->flags == mfilter->flags &&
3180                             bfilter->enables == mfilter->enables) {
3181                                 if (mvnic)
3182                                         *mvnic = vnic;
3183                                 return mfilter;
3184                         }
3185                 }
3186         }
3187         return NULL;
3188 }
3189
3190 static int
3191 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3192                        struct rte_eth_ntuple_filter *nfilter,
3193                        enum rte_filter_op filter_op)
3194 {
3195         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3196         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3197         int ret;
3198
3199         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3200                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3201                 return -EINVAL;
3202         }
3203
3204         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3205                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3206                 return -EINVAL;
3207         }
3208
3209         bfilter = bnxt_get_unused_filter(bp);
3210         if (bfilter == NULL) {
3211                 PMD_DRV_LOG(ERR,
3212                         "Not enough resources for a new filter.\n");
3213                 return -ENOMEM;
3214         }
3215         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3216         if (ret < 0)
3217                 goto free_filter;
3218
3219         vnic = &bp->vnic_info[nfilter->queue];
3220         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3221         filter1 = STAILQ_FIRST(&vnic0->filter);
3222         if (filter1 == NULL) {
3223                 ret = -EINVAL;
3224                 goto free_filter;
3225         }
3226
3227         bfilter->dst_id = vnic->fw_vnic_id;
3228         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3229         bfilter->enables |=
3230                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3231         bfilter->ethertype = 0x800;
3232         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3233
3234         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3235
3236         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3237             bfilter->dst_id == mfilter->dst_id) {
3238                 PMD_DRV_LOG(ERR, "filter exists.\n");
3239                 ret = -EEXIST;
3240                 goto free_filter;
3241         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3242                    bfilter->dst_id != mfilter->dst_id) {
3243                 mfilter->dst_id = vnic->fw_vnic_id;
3244                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3245                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3246                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3247                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3248                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3249                 goto free_filter;
3250         }
3251         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3252                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3253                 ret = -ENOENT;
3254                 goto free_filter;
3255         }
3256
3257         if (filter_op == RTE_ETH_FILTER_ADD) {
3258                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3259                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3260                 if (ret)
3261                         goto free_filter;
3262                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3263         } else {
3264                 if (mfilter == NULL) {
3265                         /* This should not happen. But for Coverity! */
3266                         ret = -ENOENT;
3267                         goto free_filter;
3268                 }
3269                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3270
3271                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3272                 bnxt_free_filter(bp, mfilter);
3273                 bnxt_free_filter(bp, bfilter);
3274         }
3275
3276         return 0;
3277 free_filter:
3278         bnxt_free_filter(bp, bfilter);
3279         return ret;
3280 }
3281
3282 static int
3283 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3284                         enum rte_filter_op filter_op,
3285                         void *arg)
3286 {
3287         struct bnxt *bp = dev->data->dev_private;
3288         int ret;
3289
3290         if (filter_op == RTE_ETH_FILTER_NOP)
3291                 return 0;
3292
3293         if (arg == NULL) {
3294                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3295                             filter_op);
3296                 return -EINVAL;
3297         }
3298
3299         switch (filter_op) {
3300         case RTE_ETH_FILTER_ADD:
3301                 ret = bnxt_cfg_ntuple_filter(bp,
3302                         (struct rte_eth_ntuple_filter *)arg,
3303                         filter_op);
3304                 break;
3305         case RTE_ETH_FILTER_DELETE:
3306                 ret = bnxt_cfg_ntuple_filter(bp,
3307                         (struct rte_eth_ntuple_filter *)arg,
3308                         filter_op);
3309                 break;
3310         default:
3311                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3312                 ret = -EINVAL;
3313                 break;
3314         }
3315         return ret;
3316 }
3317
3318 static int
3319 bnxt_parse_fdir_filter(struct bnxt *bp,
3320                        struct rte_eth_fdir_filter *fdir,
3321                        struct bnxt_filter_info *filter)
3322 {
3323         enum rte_fdir_mode fdir_mode =
3324                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3325         struct bnxt_vnic_info *vnic0, *vnic;
3326         struct bnxt_filter_info *filter1;
3327         uint32_t en = 0;
3328         int i;
3329
3330         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3331                 return -EINVAL;
3332
3333         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3334         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3335
3336         switch (fdir->input.flow_type) {
3337         case RTE_ETH_FLOW_IPV4:
3338         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3339                 /* FALLTHROUGH */
3340                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3341                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3342                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3343                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3344                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3345                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3346                 filter->ip_addr_type =
3347                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3348                 filter->src_ipaddr_mask[0] = 0xffffffff;
3349                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3350                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3351                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3352                 filter->ethertype = 0x800;
3353                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3354                 break;
3355         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3356                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3357                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3358                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3359                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3360                 filter->dst_port_mask = 0xffff;
3361                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3362                 filter->src_port_mask = 0xffff;
3363                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3364                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3365                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3366                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3367                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3368                 filter->ip_protocol = 6;
3369                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3370                 filter->ip_addr_type =
3371                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3372                 filter->src_ipaddr_mask[0] = 0xffffffff;
3373                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3374                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3375                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3376                 filter->ethertype = 0x800;
3377                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3378                 break;
3379         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3380                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3381                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3382                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3383                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3384                 filter->dst_port_mask = 0xffff;
3385                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3386                 filter->src_port_mask = 0xffff;
3387                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3388                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3389                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3390                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3391                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3392                 filter->ip_protocol = 17;
3393                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3394                 filter->ip_addr_type =
3395                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3396                 filter->src_ipaddr_mask[0] = 0xffffffff;
3397                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3398                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3399                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3400                 filter->ethertype = 0x800;
3401                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3402                 break;
3403         case RTE_ETH_FLOW_IPV6:
3404         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3405                 /* FALLTHROUGH */
3406                 filter->ip_addr_type =
3407                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3408                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3409                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3410                 rte_memcpy(filter->src_ipaddr,
3411                            fdir->input.flow.ipv6_flow.src_ip, 16);
3412                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3413                 rte_memcpy(filter->dst_ipaddr,
3414                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3415                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3416                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3417                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3418                 memset(filter->src_ipaddr_mask, 0xff, 16);
3419                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3420                 filter->ethertype = 0x86dd;
3421                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3422                 break;
3423         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3424                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3425                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3426                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3427                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3428                 filter->dst_port_mask = 0xffff;
3429                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3430                 filter->src_port_mask = 0xffff;
3431                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3432                 filter->ip_addr_type =
3433                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3434                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3435                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3436                 rte_memcpy(filter->src_ipaddr,
3437                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3438                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3439                 rte_memcpy(filter->dst_ipaddr,
3440                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3441                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3442                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3443                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3444                 memset(filter->src_ipaddr_mask, 0xff, 16);
3445                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3446                 filter->ethertype = 0x86dd;
3447                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3448                 break;
3449         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3450                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3451                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3452                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3453                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3454                 filter->dst_port_mask = 0xffff;
3455                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3456                 filter->src_port_mask = 0xffff;
3457                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3458                 filter->ip_addr_type =
3459                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3460                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3461                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3462                 rte_memcpy(filter->src_ipaddr,
3463                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3464                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3465                 rte_memcpy(filter->dst_ipaddr,
3466                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3467                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3468                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3469                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3470                 memset(filter->src_ipaddr_mask, 0xff, 16);
3471                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3472                 filter->ethertype = 0x86dd;
3473                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3474                 break;
3475         case RTE_ETH_FLOW_L2_PAYLOAD:
3476                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3477                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3478                 break;
3479         case RTE_ETH_FLOW_VXLAN:
3480                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3481                         return -EINVAL;
3482                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3483                 filter->tunnel_type =
3484                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3485                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3486                 break;
3487         case RTE_ETH_FLOW_NVGRE:
3488                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3489                         return -EINVAL;
3490                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3491                 filter->tunnel_type =
3492                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3493                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3494                 break;
3495         case RTE_ETH_FLOW_UNKNOWN:
3496         case RTE_ETH_FLOW_RAW:
3497         case RTE_ETH_FLOW_FRAG_IPV4:
3498         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3499         case RTE_ETH_FLOW_FRAG_IPV6:
3500         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3501         case RTE_ETH_FLOW_IPV6_EX:
3502         case RTE_ETH_FLOW_IPV6_TCP_EX:
3503         case RTE_ETH_FLOW_IPV6_UDP_EX:
3504         case RTE_ETH_FLOW_GENEVE:
3505                 /* FALLTHROUGH */
3506         default:
3507                 return -EINVAL;
3508         }
3509
3510         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3511         vnic = &bp->vnic_info[fdir->action.rx_queue];
3512         if (vnic == NULL) {
3513                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3514                 return -EINVAL;
3515         }
3516
3517         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3518                 rte_memcpy(filter->dst_macaddr,
3519                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3520                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3521         }
3522
3523         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3524                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3525                 filter1 = STAILQ_FIRST(&vnic0->filter);
3526                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3527         } else {
3528                 filter->dst_id = vnic->fw_vnic_id;
3529                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3530                         if (filter->dst_macaddr[i] == 0x00)
3531                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3532                         else
3533                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3534         }
3535
3536         if (filter1 == NULL)
3537                 return -EINVAL;
3538
3539         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3540         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3541
3542         filter->enables = en;
3543
3544         return 0;
3545 }
3546
3547 static struct bnxt_filter_info *
3548 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3549                 struct bnxt_vnic_info **mvnic)
3550 {
3551         struct bnxt_filter_info *mf = NULL;
3552         int i;
3553
3554         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3555                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3556
3557                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3558                         if (mf->filter_type == nf->filter_type &&
3559                             mf->flags == nf->flags &&
3560                             mf->src_port == nf->src_port &&
3561                             mf->src_port_mask == nf->src_port_mask &&
3562                             mf->dst_port == nf->dst_port &&
3563                             mf->dst_port_mask == nf->dst_port_mask &&
3564                             mf->ip_protocol == nf->ip_protocol &&
3565                             mf->ip_addr_type == nf->ip_addr_type &&
3566                             mf->ethertype == nf->ethertype &&
3567                             mf->vni == nf->vni &&
3568                             mf->tunnel_type == nf->tunnel_type &&
3569                             mf->l2_ovlan == nf->l2_ovlan &&
3570                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3571                             mf->l2_ivlan == nf->l2_ivlan &&
3572                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3573                             !memcmp(mf->l2_addr, nf->l2_addr,
3574                                     RTE_ETHER_ADDR_LEN) &&
3575                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3576                                     RTE_ETHER_ADDR_LEN) &&
3577                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3578                                     RTE_ETHER_ADDR_LEN) &&
3579                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3580                                     RTE_ETHER_ADDR_LEN) &&
3581                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3582                                     sizeof(nf->src_ipaddr)) &&
3583                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3584                                     sizeof(nf->src_ipaddr_mask)) &&
3585                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3586                                     sizeof(nf->dst_ipaddr)) &&
3587                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3588                                     sizeof(nf->dst_ipaddr_mask))) {
3589                                 if (mvnic)
3590                                         *mvnic = vnic;
3591                                 return mf;
3592                         }
3593                 }
3594         }
3595         return NULL;
3596 }
3597
3598 static int
3599 bnxt_fdir_filter(struct rte_eth_dev *dev,
3600                  enum rte_filter_op filter_op,
3601                  void *arg)
3602 {
3603         struct bnxt *bp = dev->data->dev_private;
3604         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3605         struct bnxt_filter_info *filter, *match;
3606         struct bnxt_vnic_info *vnic, *mvnic;
3607         int ret = 0, i;
3608
3609         if (filter_op == RTE_ETH_FILTER_NOP)
3610                 return 0;
3611
3612         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3613                 return -EINVAL;
3614
3615         switch (filter_op) {
3616         case RTE_ETH_FILTER_ADD:
3617         case RTE_ETH_FILTER_DELETE:
3618                 /* FALLTHROUGH */
3619                 filter = bnxt_get_unused_filter(bp);
3620                 if (filter == NULL) {
3621                         PMD_DRV_LOG(ERR,
3622                                 "Not enough resources for a new flow.\n");
3623                         return -ENOMEM;
3624                 }
3625
3626                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3627                 if (ret != 0)
3628                         goto free_filter;
3629                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3630
3631                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3632                         vnic = &bp->vnic_info[0];
3633                 else
3634                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3635
3636                 match = bnxt_match_fdir(bp, filter, &mvnic);
3637                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3638                         if (match->dst_id == vnic->fw_vnic_id) {
3639                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3640                                 ret = -EEXIST;
3641                                 goto free_filter;
3642                         } else {
3643                                 match->dst_id = vnic->fw_vnic_id;
3644                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3645                                                                   match->dst_id,
3646                                                                   match);
3647                                 STAILQ_REMOVE(&mvnic->filter, match,
3648                                               bnxt_filter_info, next);
3649                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3650                                 PMD_DRV_LOG(ERR,
3651                                         "Filter with matching pattern exist\n");
3652                                 PMD_DRV_LOG(ERR,
3653                                         "Updated it to new destination q\n");
3654                                 goto free_filter;
3655                         }
3656                 }
3657                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3658                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3659                         ret = -ENOENT;
3660                         goto free_filter;
3661                 }
3662
3663                 if (filter_op == RTE_ETH_FILTER_ADD) {
3664                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3665                                                           filter->dst_id,
3666                                                           filter);
3667                         if (ret)
3668                                 goto free_filter;
3669                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3670                 } else {
3671                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3672                         STAILQ_REMOVE(&vnic->filter, match,
3673                                       bnxt_filter_info, next);
3674                         bnxt_free_filter(bp, match);
3675                         bnxt_free_filter(bp, filter);
3676                 }
3677                 break;
3678         case RTE_ETH_FILTER_FLUSH:
3679                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3680                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3681
3682                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3683                                 if (filter->filter_type ==
3684                                     HWRM_CFA_NTUPLE_FILTER) {
3685                                         ret =
3686                                         bnxt_hwrm_clear_ntuple_filter(bp,
3687                                                                       filter);
3688                                         STAILQ_REMOVE(&vnic->filter, filter,
3689                                                       bnxt_filter_info, next);
3690                                 }
3691                         }
3692                 }
3693                 return ret;
3694         case RTE_ETH_FILTER_UPDATE:
3695         case RTE_ETH_FILTER_STATS:
3696         case RTE_ETH_FILTER_INFO:
3697                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3698                 break;
3699         default:
3700                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3701                 ret = -EINVAL;
3702                 break;
3703         }
3704         return ret;
3705
3706 free_filter:
3707         bnxt_free_filter(bp, filter);
3708         return ret;
3709 }
3710
3711 int
3712 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3713                     enum rte_filter_type filter_type,
3714                     enum rte_filter_op filter_op, void *arg)
3715 {
3716         struct bnxt *bp = dev->data->dev_private;
3717         int ret = 0;
3718
3719         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3720                 struct bnxt_vf_representor *vfr = dev->data->dev_private;
3721                 bp = vfr->parent_dev->data->dev_private;
3722         }
3723
3724         ret = is_bnxt_in_error(bp);
3725         if (ret)
3726                 return ret;
3727
3728         switch (filter_type) {
3729         case RTE_ETH_FILTER_TUNNEL:
3730                 PMD_DRV_LOG(ERR,
3731                         "filter type: %d: To be implemented\n", filter_type);
3732                 break;
3733         case RTE_ETH_FILTER_FDIR:
3734                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3735                 break;
3736         case RTE_ETH_FILTER_NTUPLE:
3737                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3738                 break;
3739         case RTE_ETH_FILTER_ETHERTYPE:
3740                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3741                 break;
3742         case RTE_ETH_FILTER_GENERIC:
3743                 if (filter_op != RTE_ETH_FILTER_GET)
3744                         return -EINVAL;
3745                 if (BNXT_TRUFLOW_EN(bp))
3746                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3747                 else
3748                         *(const void **)arg = &bnxt_flow_ops;
3749                 break;
3750         default:
3751                 PMD_DRV_LOG(ERR,
3752                         "Filter type (%d) not supported", filter_type);
3753                 ret = -EINVAL;
3754                 break;
3755         }
3756         return ret;
3757 }
3758
3759 static const uint32_t *
3760 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3761 {
3762         static const uint32_t ptypes[] = {
3763                 RTE_PTYPE_L2_ETHER_VLAN,
3764                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3765                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3766                 RTE_PTYPE_L4_ICMP,
3767                 RTE_PTYPE_L4_TCP,
3768                 RTE_PTYPE_L4_UDP,
3769                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3770                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3771                 RTE_PTYPE_INNER_L4_ICMP,
3772                 RTE_PTYPE_INNER_L4_TCP,
3773                 RTE_PTYPE_INNER_L4_UDP,
3774                 RTE_PTYPE_UNKNOWN
3775         };
3776
3777         if (!dev->rx_pkt_burst)
3778                 return NULL;
3779
3780         return ptypes;
3781 }
3782
3783 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3784                          int reg_win)
3785 {
3786         uint32_t reg_base = *reg_arr & 0xfffff000;
3787         uint32_t win_off;
3788         int i;
3789
3790         for (i = 0; i < count; i++) {
3791                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3792                         return -ERANGE;
3793         }
3794         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3795         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3796         return 0;
3797 }
3798
3799 static int bnxt_map_ptp_regs(struct bnxt *bp)
3800 {
3801         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3802         uint32_t *reg_arr;
3803         int rc, i;
3804
3805         reg_arr = ptp->rx_regs;
3806         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3807         if (rc)
3808                 return rc;
3809
3810         reg_arr = ptp->tx_regs;
3811         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3812         if (rc)
3813                 return rc;
3814
3815         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3816                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3817
3818         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3819                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3820
3821         return 0;
3822 }
3823
3824 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3825 {
3826         rte_write32(0, (uint8_t *)bp->bar0 +
3827                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3828         rte_write32(0, (uint8_t *)bp->bar0 +
3829                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3830 }
3831
3832 static uint64_t bnxt_cc_read(struct bnxt *bp)
3833 {
3834         uint64_t ns;
3835
3836         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3837                               BNXT_GRCPF_REG_SYNC_TIME));
3838         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3839                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3840         return ns;
3841 }
3842
3843 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3844 {
3845         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3846         uint32_t fifo;
3847
3848         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3849                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3850         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3851                 return -EAGAIN;
3852
3853         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3854                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3855         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3856                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3857         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3858                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3859
3860         return 0;
3861 }
3862
3863 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3864 {
3865         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3866         struct bnxt_pf_info *pf = bp->pf;
3867         uint16_t port_id;
3868         uint32_t fifo;
3869
3870         if (!ptp)
3871                 return -ENODEV;
3872
3873         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3874                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3875         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3876                 return -EAGAIN;
3877
3878         port_id = pf->port_id;
3879         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3880                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3881
3882         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3883                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3884         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3885 /*              bnxt_clr_rx_ts(bp);       TBD  */
3886                 return -EBUSY;
3887         }
3888
3889         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3890                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3891         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3892                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3893
3894         return 0;
3895 }
3896
3897 static int
3898 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3899 {
3900         uint64_t ns;
3901         struct bnxt *bp = dev->data->dev_private;
3902         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3903
3904         if (!ptp)
3905                 return 0;
3906
3907         ns = rte_timespec_to_ns(ts);
3908         /* Set the timecounters to a new value. */
3909         ptp->tc.nsec = ns;
3910
3911         return 0;
3912 }
3913
3914 static int
3915 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3916 {
3917         struct bnxt *bp = dev->data->dev_private;
3918         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3919         uint64_t ns, systime_cycles = 0;
3920         int rc = 0;
3921
3922         if (!ptp)
3923                 return 0;
3924
3925         if (BNXT_CHIP_THOR(bp))
3926                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3927                                              &systime_cycles);
3928         else
3929                 systime_cycles = bnxt_cc_read(bp);
3930
3931         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3932         *ts = rte_ns_to_timespec(ns);
3933
3934         return rc;
3935 }
3936 static int
3937 bnxt_timesync_enable(struct rte_eth_dev *dev)
3938 {
3939         struct bnxt *bp = dev->data->dev_private;
3940         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3941         uint32_t shift = 0;
3942         int rc;
3943
3944         if (!ptp)
3945                 return 0;
3946
3947         ptp->rx_filter = 1;
3948         ptp->tx_tstamp_en = 1;
3949         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3950
3951         rc = bnxt_hwrm_ptp_cfg(bp);
3952         if (rc)
3953                 return rc;
3954
3955         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3956         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3957         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3958
3959         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3960         ptp->tc.cc_shift = shift;
3961         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3962
3963         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3964         ptp->rx_tstamp_tc.cc_shift = shift;
3965         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3966
3967         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3968         ptp->tx_tstamp_tc.cc_shift = shift;
3969         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3970
3971         if (!BNXT_CHIP_THOR(bp))
3972                 bnxt_map_ptp_regs(bp);
3973
3974         return 0;
3975 }
3976
3977 static int
3978 bnxt_timesync_disable(struct rte_eth_dev *dev)
3979 {
3980         struct bnxt *bp = dev->data->dev_private;
3981         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3982
3983         if (!ptp)
3984                 return 0;
3985
3986         ptp->rx_filter = 0;
3987         ptp->tx_tstamp_en = 0;
3988         ptp->rxctl = 0;
3989
3990         bnxt_hwrm_ptp_cfg(bp);
3991
3992         if (!BNXT_CHIP_THOR(bp))
3993                 bnxt_unmap_ptp_regs(bp);
3994
3995         return 0;
3996 }
3997
3998 static int
3999 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4000                                  struct timespec *timestamp,
4001                                  uint32_t flags __rte_unused)
4002 {
4003         struct bnxt *bp = dev->data->dev_private;
4004         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4005         uint64_t rx_tstamp_cycles = 0;
4006         uint64_t ns;
4007
4008         if (!ptp)
4009                 return 0;
4010
4011         if (BNXT_CHIP_THOR(bp))
4012                 rx_tstamp_cycles = ptp->rx_timestamp;
4013         else
4014                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4015
4016         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4017         *timestamp = rte_ns_to_timespec(ns);
4018         return  0;
4019 }
4020
4021 static int
4022 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4023                                  struct timespec *timestamp)
4024 {
4025         struct bnxt *bp = dev->data->dev_private;
4026         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4027         uint64_t tx_tstamp_cycles = 0;
4028         uint64_t ns;
4029         int rc = 0;
4030
4031         if (!ptp)
4032                 return 0;
4033
4034         if (BNXT_CHIP_THOR(bp))
4035                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4036                                              &tx_tstamp_cycles);
4037         else
4038                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4039
4040         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4041         *timestamp = rte_ns_to_timespec(ns);
4042
4043         return rc;
4044 }
4045
4046 static int
4047 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4048 {
4049         struct bnxt *bp = dev->data->dev_private;
4050         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4051
4052         if (!ptp)
4053                 return 0;
4054
4055         ptp->tc.nsec += delta;
4056
4057         return 0;
4058 }
4059
4060 static int
4061 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4062 {
4063         struct bnxt *bp = dev->data->dev_private;
4064         int rc;
4065         uint32_t dir_entries;
4066         uint32_t entry_length;
4067
4068         rc = is_bnxt_in_error(bp);
4069         if (rc)
4070                 return rc;
4071
4072         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4073                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4074                     bp->pdev->addr.devid, bp->pdev->addr.function);
4075
4076         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4077         if (rc != 0)
4078                 return rc;
4079
4080         return dir_entries * entry_length;
4081 }
4082
4083 static int
4084 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4085                 struct rte_dev_eeprom_info *in_eeprom)
4086 {
4087         struct bnxt *bp = dev->data->dev_private;
4088         uint32_t index;
4089         uint32_t offset;
4090         int rc;
4091
4092         rc = is_bnxt_in_error(bp);
4093         if (rc)
4094                 return rc;
4095
4096         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4097                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4098                     bp->pdev->addr.devid, bp->pdev->addr.function,
4099                     in_eeprom->offset, in_eeprom->length);
4100
4101         if (in_eeprom->offset == 0) /* special offset value to get directory */
4102                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4103                                                 in_eeprom->data);
4104
4105         index = in_eeprom->offset >> 24;
4106         offset = in_eeprom->offset & 0xffffff;
4107
4108         if (index != 0)
4109                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4110                                            in_eeprom->length, in_eeprom->data);
4111
4112         return 0;
4113 }
4114
4115 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4116 {
4117         switch (dir_type) {
4118         case BNX_DIR_TYPE_CHIMP_PATCH:
4119         case BNX_DIR_TYPE_BOOTCODE:
4120         case BNX_DIR_TYPE_BOOTCODE_2:
4121         case BNX_DIR_TYPE_APE_FW:
4122         case BNX_DIR_TYPE_APE_PATCH:
4123         case BNX_DIR_TYPE_KONG_FW:
4124         case BNX_DIR_TYPE_KONG_PATCH:
4125         case BNX_DIR_TYPE_BONO_FW:
4126         case BNX_DIR_TYPE_BONO_PATCH:
4127                 /* FALLTHROUGH */
4128                 return true;
4129         }
4130
4131         return false;
4132 }
4133
4134 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4135 {
4136         switch (dir_type) {
4137         case BNX_DIR_TYPE_AVS:
4138         case BNX_DIR_TYPE_EXP_ROM_MBA:
4139         case BNX_DIR_TYPE_PCIE:
4140         case BNX_DIR_TYPE_TSCF_UCODE:
4141         case BNX_DIR_TYPE_EXT_PHY:
4142         case BNX_DIR_TYPE_CCM:
4143         case BNX_DIR_TYPE_ISCSI_BOOT:
4144         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4145         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4146                 /* FALLTHROUGH */
4147                 return true;
4148         }
4149
4150         return false;
4151 }
4152
4153 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4154 {
4155         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4156                 bnxt_dir_type_is_other_exec_format(dir_type);
4157 }
4158
4159 static int
4160 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4161                 struct rte_dev_eeprom_info *in_eeprom)
4162 {
4163         struct bnxt *bp = dev->data->dev_private;
4164         uint8_t index, dir_op;
4165         uint16_t type, ext, ordinal, attr;
4166         int rc;
4167
4168         rc = is_bnxt_in_error(bp);
4169         if (rc)
4170                 return rc;
4171
4172         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4173                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4174                     bp->pdev->addr.devid, bp->pdev->addr.function,
4175                     in_eeprom->offset, in_eeprom->length);
4176
4177         if (!BNXT_PF(bp)) {
4178                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4179                 return -EINVAL;
4180         }
4181
4182         type = in_eeprom->magic >> 16;
4183
4184         if (type == 0xffff) { /* special value for directory operations */
4185                 index = in_eeprom->magic & 0xff;
4186                 dir_op = in_eeprom->magic >> 8;
4187                 if (index == 0)
4188                         return -EINVAL;
4189                 switch (dir_op) {
4190                 case 0x0e: /* erase */
4191                         if (in_eeprom->offset != ~in_eeprom->magic)
4192                                 return -EINVAL;
4193                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4194                 default:
4195                         return -EINVAL;
4196                 }
4197         }
4198
4199         /* Create or re-write an NVM item: */
4200         if (bnxt_dir_type_is_executable(type) == true)
4201                 return -EOPNOTSUPP;
4202         ext = in_eeprom->magic & 0xffff;
4203         ordinal = in_eeprom->offset >> 16;
4204         attr = in_eeprom->offset & 0xffff;
4205
4206         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4207                                      in_eeprom->data, in_eeprom->length);
4208 }
4209
4210 /*
4211  * Initialization
4212  */
4213
4214 static const struct eth_dev_ops bnxt_dev_ops = {
4215         .dev_infos_get = bnxt_dev_info_get_op,
4216         .dev_close = bnxt_dev_close_op,
4217         .dev_configure = bnxt_dev_configure_op,
4218         .dev_start = bnxt_dev_start_op,
4219         .dev_stop = bnxt_dev_stop_op,
4220         .dev_set_link_up = bnxt_dev_set_link_up_op,
4221         .dev_set_link_down = bnxt_dev_set_link_down_op,
4222         .stats_get = bnxt_stats_get_op,
4223         .stats_reset = bnxt_stats_reset_op,
4224         .rx_queue_setup = bnxt_rx_queue_setup_op,
4225         .rx_queue_release = bnxt_rx_queue_release_op,
4226         .tx_queue_setup = bnxt_tx_queue_setup_op,
4227         .tx_queue_release = bnxt_tx_queue_release_op,
4228         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4229         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4230         .reta_update = bnxt_reta_update_op,
4231         .reta_query = bnxt_reta_query_op,
4232         .rss_hash_update = bnxt_rss_hash_update_op,
4233         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4234         .link_update = bnxt_link_update_op,
4235         .promiscuous_enable = bnxt_promiscuous_enable_op,
4236         .promiscuous_disable = bnxt_promiscuous_disable_op,
4237         .allmulticast_enable = bnxt_allmulticast_enable_op,
4238         .allmulticast_disable = bnxt_allmulticast_disable_op,
4239         .mac_addr_add = bnxt_mac_addr_add_op,
4240         .mac_addr_remove = bnxt_mac_addr_remove_op,
4241         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4242         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4243         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4244         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4245         .vlan_filter_set = bnxt_vlan_filter_set_op,
4246         .vlan_offload_set = bnxt_vlan_offload_set_op,
4247         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4248         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4249         .mtu_set = bnxt_mtu_set_op,
4250         .mac_addr_set = bnxt_set_default_mac_addr_op,
4251         .xstats_get = bnxt_dev_xstats_get_op,
4252         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4253         .xstats_reset = bnxt_dev_xstats_reset_op,
4254         .fw_version_get = bnxt_fw_version_get,
4255         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4256         .rxq_info_get = bnxt_rxq_info_get_op,
4257         .txq_info_get = bnxt_txq_info_get_op,
4258         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4259         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4260         .dev_led_on = bnxt_dev_led_on_op,
4261         .dev_led_off = bnxt_dev_led_off_op,
4262         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4263         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4264         .rx_queue_start = bnxt_rx_queue_start,
4265         .rx_queue_stop = bnxt_rx_queue_stop,
4266         .tx_queue_start = bnxt_tx_queue_start,
4267         .tx_queue_stop = bnxt_tx_queue_stop,
4268         .filter_ctrl = bnxt_filter_ctrl_op,
4269         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4270         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4271         .get_eeprom           = bnxt_get_eeprom_op,
4272         .set_eeprom           = bnxt_set_eeprom_op,
4273         .timesync_enable      = bnxt_timesync_enable,
4274         .timesync_disable     = bnxt_timesync_disable,
4275         .timesync_read_time   = bnxt_timesync_read_time,
4276         .timesync_write_time   = bnxt_timesync_write_time,
4277         .timesync_adjust_time = bnxt_timesync_adjust_time,
4278         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4279         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4280 };
4281
4282 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4283 {
4284         uint32_t offset;
4285
4286         /* Only pre-map the reset GRC registers using window 3 */
4287         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4288                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4289
4290         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4291
4292         return offset;
4293 }
4294
4295 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4296 {
4297         struct bnxt_error_recovery_info *info = bp->recovery_info;
4298         uint32_t reg_base = 0xffffffff;
4299         int i;
4300
4301         /* Only pre-map the monitoring GRC registers using window 2 */
4302         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4303                 uint32_t reg = info->status_regs[i];
4304
4305                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4306                         continue;
4307
4308                 if (reg_base == 0xffffffff)
4309                         reg_base = reg & 0xfffff000;
4310                 if ((reg & 0xfffff000) != reg_base)
4311                         return -ERANGE;
4312
4313                 /* Use mask 0xffc as the Lower 2 bits indicates
4314                  * address space location
4315                  */
4316                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4317                                                 (reg & 0xffc);
4318         }
4319
4320         if (reg_base == 0xffffffff)
4321                 return 0;
4322
4323         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4324                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4325
4326         return 0;
4327 }
4328
4329 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4330 {
4331         struct bnxt_error_recovery_info *info = bp->recovery_info;
4332         uint32_t delay = info->delay_after_reset[index];
4333         uint32_t val = info->reset_reg_val[index];
4334         uint32_t reg = info->reset_reg[index];
4335         uint32_t type, offset;
4336
4337         type = BNXT_FW_STATUS_REG_TYPE(reg);
4338         offset = BNXT_FW_STATUS_REG_OFF(reg);
4339
4340         switch (type) {
4341         case BNXT_FW_STATUS_REG_TYPE_CFG:
4342                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4343                 break;
4344         case BNXT_FW_STATUS_REG_TYPE_GRC:
4345                 offset = bnxt_map_reset_regs(bp, offset);
4346                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4347                 break;
4348         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4349                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4350                 break;
4351         }
4352         /* wait on a specific interval of time until core reset is complete */
4353         if (delay)
4354                 rte_delay_ms(delay);
4355 }
4356
4357 static void bnxt_dev_cleanup(struct bnxt *bp)
4358 {
4359         bnxt_set_hwrm_link_config(bp, false);
4360         bp->link_info->link_up = 0;
4361         if (bp->eth_dev->data->dev_started)
4362                 bnxt_dev_stop_op(bp->eth_dev);
4363
4364         bnxt_uninit_resources(bp, true);
4365 }
4366
4367 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4368 {
4369         struct rte_eth_dev *dev = bp->eth_dev;
4370         struct rte_vlan_filter_conf *vfc;
4371         int vidx, vbit, rc;
4372         uint16_t vlan_id;
4373
4374         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4375                 vfc = &dev->data->vlan_filter_conf;
4376                 vidx = vlan_id / 64;
4377                 vbit = vlan_id % 64;
4378
4379                 /* Each bit corresponds to a VLAN id */
4380                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4381                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4382                         if (rc)
4383                                 return rc;
4384                 }
4385         }
4386
4387         return 0;
4388 }
4389
4390 static int bnxt_restore_mac_filters(struct bnxt *bp)
4391 {
4392         struct rte_eth_dev *dev = bp->eth_dev;
4393         struct rte_eth_dev_info dev_info;
4394         struct rte_ether_addr *addr;
4395         uint64_t pool_mask;
4396         uint32_t pool = 0;
4397         uint16_t i;
4398         int rc;
4399
4400         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4401                 return 0;
4402
4403         rc = bnxt_dev_info_get_op(dev, &dev_info);
4404         if (rc)
4405                 return rc;
4406
4407         /* replay MAC address configuration */
4408         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4409                 addr = &dev->data->mac_addrs[i];
4410
4411                 /* skip zero address */
4412                 if (rte_is_zero_ether_addr(addr))
4413                         continue;
4414
4415                 pool = 0;
4416                 pool_mask = dev->data->mac_pool_sel[i];
4417
4418                 do {
4419                         if (pool_mask & 1ULL) {
4420                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4421                                 if (rc)
4422                                         return rc;
4423                         }
4424                         pool_mask >>= 1;
4425                         pool++;
4426                 } while (pool_mask);
4427         }
4428
4429         return 0;
4430 }
4431
4432 static int bnxt_restore_filters(struct bnxt *bp)
4433 {
4434         struct rte_eth_dev *dev = bp->eth_dev;
4435         int ret = 0;
4436
4437         if (dev->data->all_multicast) {
4438                 ret = bnxt_allmulticast_enable_op(dev);
4439                 if (ret)
4440                         return ret;
4441         }
4442         if (dev->data->promiscuous) {
4443                 ret = bnxt_promiscuous_enable_op(dev);
4444                 if (ret)
4445                         return ret;
4446         }
4447
4448         ret = bnxt_restore_mac_filters(bp);
4449         if (ret)
4450                 return ret;
4451
4452         ret = bnxt_restore_vlan_filters(bp);
4453         /* TODO restore other filters as well */
4454         return ret;
4455 }
4456
4457 static void bnxt_dev_recover(void *arg)
4458 {
4459         struct bnxt *bp = arg;
4460         int timeout = bp->fw_reset_max_msecs;
4461         int rc = 0;
4462
4463         /* Clear Error flag so that device re-init should happen */
4464         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4465
4466         do {
4467                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4468                 if (rc == 0)
4469                         break;
4470                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4471                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4472         } while (rc && timeout);
4473
4474         if (rc) {
4475                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4476                 goto err;
4477         }
4478
4479         rc = bnxt_init_resources(bp, true);
4480         if (rc) {
4481                 PMD_DRV_LOG(ERR,
4482                             "Failed to initialize resources after reset\n");
4483                 goto err;
4484         }
4485         /* clear reset flag as the device is initialized now */
4486         bp->flags &= ~BNXT_FLAG_FW_RESET;
4487
4488         rc = bnxt_dev_start_op(bp->eth_dev);
4489         if (rc) {
4490                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4491                 goto err_start;
4492         }
4493
4494         rc = bnxt_restore_filters(bp);
4495         if (rc)
4496                 goto err_start;
4497
4498         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4499         return;
4500 err_start:
4501         bnxt_dev_stop_op(bp->eth_dev);
4502 err:
4503         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4504         bnxt_uninit_resources(bp, false);
4505         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4506 }
4507
4508 void bnxt_dev_reset_and_resume(void *arg)
4509 {
4510         struct bnxt *bp = arg;
4511         int rc;
4512
4513         bnxt_dev_cleanup(bp);
4514
4515         bnxt_wait_for_device_shutdown(bp);
4516
4517         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4518                                bnxt_dev_recover, (void *)bp);
4519         if (rc)
4520                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4521 }
4522
4523 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4524 {
4525         struct bnxt_error_recovery_info *info = bp->recovery_info;
4526         uint32_t reg = info->status_regs[index];
4527         uint32_t type, offset, val = 0;
4528
4529         type = BNXT_FW_STATUS_REG_TYPE(reg);
4530         offset = BNXT_FW_STATUS_REG_OFF(reg);
4531
4532         switch (type) {
4533         case BNXT_FW_STATUS_REG_TYPE_CFG:
4534                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4535                 break;
4536         case BNXT_FW_STATUS_REG_TYPE_GRC:
4537                 offset = info->mapped_status_regs[index];
4538                 /* FALLTHROUGH */
4539         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4540                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4541                                        offset));
4542                 break;
4543         }
4544
4545         return val;
4546 }
4547
4548 static int bnxt_fw_reset_all(struct bnxt *bp)
4549 {
4550         struct bnxt_error_recovery_info *info = bp->recovery_info;
4551         uint32_t i;
4552         int rc = 0;
4553
4554         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4555                 /* Reset through master function driver */
4556                 for (i = 0; i < info->reg_array_cnt; i++)
4557                         bnxt_write_fw_reset_reg(bp, i);
4558                 /* Wait for time specified by FW after triggering reset */
4559                 rte_delay_ms(info->master_func_wait_period_after_reset);
4560         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4561                 /* Reset with the help of Kong processor */
4562                 rc = bnxt_hwrm_fw_reset(bp);
4563                 if (rc)
4564                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4565         }
4566
4567         return rc;
4568 }
4569
4570 static void bnxt_fw_reset_cb(void *arg)
4571 {
4572         struct bnxt *bp = arg;
4573         struct bnxt_error_recovery_info *info = bp->recovery_info;
4574         int rc = 0;
4575
4576         /* Only Master function can do FW reset */
4577         if (bnxt_is_master_func(bp) &&
4578             bnxt_is_recovery_enabled(bp)) {
4579                 rc = bnxt_fw_reset_all(bp);
4580                 if (rc) {
4581                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4582                         return;
4583                 }
4584         }
4585
4586         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4587          * EXCEPTION_FATAL_ASYNC event to all the functions
4588          * (including MASTER FUNC). After receiving this Async, all the active
4589          * drivers should treat this case as FW initiated recovery
4590          */
4591         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4592                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4593                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4594
4595                 /* To recover from error */
4596                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4597                                   (void *)bp);
4598         }
4599 }
4600
4601 /* Driver should poll FW heartbeat, reset_counter with the frequency
4602  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4603  * When the driver detects heartbeat stop or change in reset_counter,
4604  * it has to trigger a reset to recover from the error condition.
4605  * A “master PF” is the function who will have the privilege to
4606  * initiate the chimp reset. The master PF will be elected by the
4607  * firmware and will be notified through async message.
4608  */
4609 static void bnxt_check_fw_health(void *arg)
4610 {
4611         struct bnxt *bp = arg;
4612         struct bnxt_error_recovery_info *info = bp->recovery_info;
4613         uint32_t val = 0, wait_msec;
4614
4615         if (!info || !bnxt_is_recovery_enabled(bp) ||
4616             is_bnxt_in_error(bp))
4617                 return;
4618
4619         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4620         if (val == info->last_heart_beat)
4621                 goto reset;
4622
4623         info->last_heart_beat = val;
4624
4625         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4626         if (val != info->last_reset_counter)
4627                 goto reset;
4628
4629         info->last_reset_counter = val;
4630
4631         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4632                           bnxt_check_fw_health, (void *)bp);
4633
4634         return;
4635 reset:
4636         /* Stop DMA to/from device */
4637         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4638         bp->flags |= BNXT_FLAG_FW_RESET;
4639
4640         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4641
4642         if (bnxt_is_master_func(bp))
4643                 wait_msec = info->master_func_wait_period;
4644         else
4645                 wait_msec = info->normal_func_wait_period;
4646
4647         rte_eal_alarm_set(US_PER_MS * wait_msec,
4648                           bnxt_fw_reset_cb, (void *)bp);
4649 }
4650
4651 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4652 {
4653         uint32_t polling_freq;
4654
4655         if (!bnxt_is_recovery_enabled(bp))
4656                 return;
4657
4658         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4659                 return;
4660
4661         polling_freq = bp->recovery_info->driver_polling_freq;
4662
4663         rte_eal_alarm_set(US_PER_MS * polling_freq,
4664                           bnxt_check_fw_health, (void *)bp);
4665         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4666 }
4667
4668 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4669 {
4670         if (!bnxt_is_recovery_enabled(bp))
4671                 return;
4672
4673         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4674         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4675 }
4676
4677 static bool bnxt_vf_pciid(uint16_t device_id)
4678 {
4679         switch (device_id) {
4680         case BROADCOM_DEV_ID_57304_VF:
4681         case BROADCOM_DEV_ID_57406_VF:
4682         case BROADCOM_DEV_ID_5731X_VF:
4683         case BROADCOM_DEV_ID_5741X_VF:
4684         case BROADCOM_DEV_ID_57414_VF:
4685         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4686         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4687         case BROADCOM_DEV_ID_58802_VF:
4688         case BROADCOM_DEV_ID_57500_VF1:
4689         case BROADCOM_DEV_ID_57500_VF2:
4690                 /* FALLTHROUGH */
4691                 return true;
4692         default:
4693                 return false;
4694         }
4695 }
4696
4697 static bool bnxt_thor_device(uint16_t device_id)
4698 {
4699         switch (device_id) {
4700         case BROADCOM_DEV_ID_57508:
4701         case BROADCOM_DEV_ID_57504:
4702         case BROADCOM_DEV_ID_57502:
4703         case BROADCOM_DEV_ID_57508_MF1:
4704         case BROADCOM_DEV_ID_57504_MF1:
4705         case BROADCOM_DEV_ID_57502_MF1:
4706         case BROADCOM_DEV_ID_57508_MF2:
4707         case BROADCOM_DEV_ID_57504_MF2:
4708         case BROADCOM_DEV_ID_57502_MF2:
4709         case BROADCOM_DEV_ID_57500_VF1:
4710         case BROADCOM_DEV_ID_57500_VF2:
4711                 /* FALLTHROUGH */
4712                 return true;
4713         default:
4714                 return false;
4715         }
4716 }
4717
4718 bool bnxt_stratus_device(struct bnxt *bp)
4719 {
4720         uint16_t device_id = bp->pdev->id.device_id;
4721
4722         switch (device_id) {
4723         case BROADCOM_DEV_ID_STRATUS_NIC:
4724         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4725         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4726                 /* FALLTHROUGH */
4727                 return true;
4728         default:
4729                 return false;
4730         }
4731 }
4732
4733 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4734 {
4735         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4736         struct bnxt *bp = eth_dev->data->dev_private;
4737
4738         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4739         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4740         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4741         if (!bp->bar0 || !bp->doorbell_base) {
4742                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4743                 return -ENODEV;
4744         }
4745
4746         bp->eth_dev = eth_dev;
4747         bp->pdev = pci_dev;
4748
4749         return 0;
4750 }
4751
4752 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4753                                   struct bnxt_ctx_pg_info *ctx_pg,
4754                                   uint32_t mem_size,
4755                                   const char *suffix,
4756                                   uint16_t idx)
4757 {
4758         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4759         const struct rte_memzone *mz = NULL;
4760         char mz_name[RTE_MEMZONE_NAMESIZE];
4761         rte_iova_t mz_phys_addr;
4762         uint64_t valid_bits = 0;
4763         uint32_t sz;
4764         int i;
4765
4766         if (!mem_size)
4767                 return 0;
4768
4769         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4770                          BNXT_PAGE_SIZE;
4771         rmem->page_size = BNXT_PAGE_SIZE;
4772         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4773         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4774         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4775
4776         valid_bits = PTU_PTE_VALID;
4777
4778         if (rmem->nr_pages > 1) {
4779                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4780                          "bnxt_ctx_pg_tbl%s_%x_%d",
4781                          suffix, idx, bp->eth_dev->data->port_id);
4782                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4783                 mz = rte_memzone_lookup(mz_name);
4784                 if (!mz) {
4785                         mz = rte_memzone_reserve_aligned(mz_name,
4786                                                 rmem->nr_pages * 8,
4787                                                 SOCKET_ID_ANY,
4788                                                 RTE_MEMZONE_2MB |
4789                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4790                                                 RTE_MEMZONE_IOVA_CONTIG,
4791                                                 BNXT_PAGE_SIZE);
4792                         if (mz == NULL)
4793                                 return -ENOMEM;
4794                 }
4795
4796                 memset(mz->addr, 0, mz->len);
4797                 mz_phys_addr = mz->iova;
4798
4799                 rmem->pg_tbl = mz->addr;
4800                 rmem->pg_tbl_map = mz_phys_addr;
4801                 rmem->pg_tbl_mz = mz;
4802         }
4803
4804         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4805                  suffix, idx, bp->eth_dev->data->port_id);
4806         mz = rte_memzone_lookup(mz_name);
4807         if (!mz) {
4808                 mz = rte_memzone_reserve_aligned(mz_name,
4809                                                  mem_size,
4810                                                  SOCKET_ID_ANY,
4811                                                  RTE_MEMZONE_1GB |
4812                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4813                                                  RTE_MEMZONE_IOVA_CONTIG,
4814                                                  BNXT_PAGE_SIZE);
4815                 if (mz == NULL)
4816                         return -ENOMEM;
4817         }
4818
4819         memset(mz->addr, 0, mz->len);
4820         mz_phys_addr = mz->iova;
4821
4822         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4823                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4824                 rmem->dma_arr[i] = mz_phys_addr + sz;
4825
4826                 if (rmem->nr_pages > 1) {
4827                         if (i == rmem->nr_pages - 2 &&
4828                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4829                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4830                         else if (i == rmem->nr_pages - 1 &&
4831                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4832                                 valid_bits |= PTU_PTE_LAST;
4833
4834                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4835                                                            valid_bits);
4836                 }
4837         }
4838
4839         rmem->mz = mz;
4840         if (rmem->vmem_size)
4841                 rmem->vmem = (void **)mz->addr;
4842         rmem->dma_arr[0] = mz_phys_addr;
4843         return 0;
4844 }
4845
4846 static void bnxt_free_ctx_mem(struct bnxt *bp)
4847 {
4848         int i;
4849
4850         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4851                 return;
4852
4853         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4854         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4855         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4856         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4857         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4858         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4859         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4860         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4861         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4862         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4863         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4864
4865         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4866                 if (bp->ctx->tqm_mem[i])
4867                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4868         }
4869
4870         rte_free(bp->ctx);
4871         bp->ctx = NULL;
4872 }
4873
4874 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4875
4876 #define min_t(type, x, y) ({                    \
4877         type __min1 = (x);                      \
4878         type __min2 = (y);                      \
4879         __min1 < __min2 ? __min1 : __min2; })
4880
4881 #define max_t(type, x, y) ({                    \
4882         type __max1 = (x);                      \
4883         type __max2 = (y);                      \
4884         __max1 > __max2 ? __max1 : __max2; })
4885
4886 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4887
4888 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4889 {
4890         struct bnxt_ctx_pg_info *ctx_pg;
4891         struct bnxt_ctx_mem_info *ctx;
4892         uint32_t mem_size, ena, entries;
4893         uint32_t entries_sp, min;
4894         int i, rc;
4895
4896         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4897         if (rc) {
4898                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4899                 return rc;
4900         }
4901         ctx = bp->ctx;
4902         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4903                 return 0;
4904
4905         ctx_pg = &ctx->qp_mem;
4906         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4907         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4908         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4909         if (rc)
4910                 return rc;
4911
4912         ctx_pg = &ctx->srq_mem;
4913         ctx_pg->entries = ctx->srq_max_l2_entries;
4914         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4915         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4916         if (rc)
4917                 return rc;
4918
4919         ctx_pg = &ctx->cq_mem;
4920         ctx_pg->entries = ctx->cq_max_l2_entries;
4921         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4922         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4923         if (rc)
4924                 return rc;
4925
4926         ctx_pg = &ctx->vnic_mem;
4927         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4928                 ctx->vnic_max_ring_table_entries;
4929         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4930         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4931         if (rc)
4932                 return rc;
4933
4934         ctx_pg = &ctx->stat_mem;
4935         ctx_pg->entries = ctx->stat_max_entries;
4936         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4937         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4938         if (rc)
4939                 return rc;
4940
4941         min = ctx->tqm_min_entries_per_ring;
4942
4943         entries_sp = ctx->qp_max_l2_entries +
4944                      ctx->vnic_max_vnic_entries +
4945                      2 * ctx->qp_min_qp1_entries + min;
4946         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4947
4948         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4949         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4950         entries = clamp_t(uint32_t, entries, min,
4951                           ctx->tqm_max_entries_per_ring);
4952         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4953                 ctx_pg = ctx->tqm_mem[i];
4954                 ctx_pg->entries = i ? entries : entries_sp;
4955                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4956                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4957                 if (rc)
4958                         return rc;
4959                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4960         }
4961
4962         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4963         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4964         if (rc)
4965                 PMD_DRV_LOG(ERR,
4966                             "Failed to configure context mem: rc = %d\n", rc);
4967         else
4968                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4969
4970         return rc;
4971 }
4972
4973 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4974 {
4975         struct rte_pci_device *pci_dev = bp->pdev;
4976         char mz_name[RTE_MEMZONE_NAMESIZE];
4977         const struct rte_memzone *mz = NULL;
4978         uint32_t total_alloc_len;
4979         rte_iova_t mz_phys_addr;
4980
4981         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4982                 return 0;
4983
4984         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4985                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4986                  pci_dev->addr.bus, pci_dev->addr.devid,
4987                  pci_dev->addr.function, "rx_port_stats");
4988         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4989         mz = rte_memzone_lookup(mz_name);
4990         total_alloc_len =
4991                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4992                                        sizeof(struct rx_port_stats_ext) + 512);
4993         if (!mz) {
4994                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4995                                          SOCKET_ID_ANY,
4996                                          RTE_MEMZONE_2MB |
4997                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4998                                          RTE_MEMZONE_IOVA_CONTIG);
4999                 if (mz == NULL)
5000                         return -ENOMEM;
5001         }
5002         memset(mz->addr, 0, mz->len);
5003         mz_phys_addr = mz->iova;
5004
5005         bp->rx_mem_zone = (const void *)mz;
5006         bp->hw_rx_port_stats = mz->addr;
5007         bp->hw_rx_port_stats_map = mz_phys_addr;
5008
5009         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5010                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5011                  pci_dev->addr.bus, pci_dev->addr.devid,
5012                  pci_dev->addr.function, "tx_port_stats");
5013         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5014         mz = rte_memzone_lookup(mz_name);
5015         total_alloc_len =
5016                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5017                                        sizeof(struct tx_port_stats_ext) + 512);
5018         if (!mz) {
5019                 mz = rte_memzone_reserve(mz_name,
5020                                          total_alloc_len,
5021                                          SOCKET_ID_ANY,
5022                                          RTE_MEMZONE_2MB |
5023                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5024                                          RTE_MEMZONE_IOVA_CONTIG);
5025                 if (mz == NULL)
5026                         return -ENOMEM;
5027         }
5028         memset(mz->addr, 0, mz->len);
5029         mz_phys_addr = mz->iova;
5030
5031         bp->tx_mem_zone = (const void *)mz;
5032         bp->hw_tx_port_stats = mz->addr;
5033         bp->hw_tx_port_stats_map = mz_phys_addr;
5034         bp->flags |= BNXT_FLAG_PORT_STATS;
5035
5036         /* Display extended statistics if FW supports it */
5037         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5038             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5039             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5040                 return 0;
5041
5042         bp->hw_rx_port_stats_ext = (void *)
5043                 ((uint8_t *)bp->hw_rx_port_stats +
5044                  sizeof(struct rx_port_stats));
5045         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5046                 sizeof(struct rx_port_stats);
5047         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5048
5049         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5050             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5051                 bp->hw_tx_port_stats_ext = (void *)
5052                         ((uint8_t *)bp->hw_tx_port_stats +
5053                          sizeof(struct tx_port_stats));
5054                 bp->hw_tx_port_stats_ext_map =
5055                         bp->hw_tx_port_stats_map +
5056                         sizeof(struct tx_port_stats);
5057                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5058         }
5059
5060         return 0;
5061 }
5062
5063 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5064 {
5065         struct bnxt *bp = eth_dev->data->dev_private;
5066         int rc = 0;
5067
5068         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5069                                                RTE_ETHER_ADDR_LEN *
5070                                                bp->max_l2_ctx,
5071                                                0);
5072         if (eth_dev->data->mac_addrs == NULL) {
5073                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5074                 return -ENOMEM;
5075         }
5076
5077         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5078                 if (BNXT_PF(bp))
5079                         return -EINVAL;
5080
5081                 /* Generate a random MAC address, if none was assigned by PF */
5082                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5083                 bnxt_eth_hw_addr_random(bp->mac_addr);
5084                 PMD_DRV_LOG(INFO,
5085                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5086                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5087                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5088
5089                 rc = bnxt_hwrm_set_mac(bp);
5090                 if (rc)
5091                         return rc;
5092         }
5093
5094         /* Copy the permanent MAC from the FUNC_QCAPS response */
5095         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5096
5097         return rc;
5098 }
5099
5100 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5101 {
5102         int rc = 0;
5103
5104         /* MAC is already configured in FW */
5105         if (BNXT_HAS_DFLT_MAC_SET(bp))
5106                 return 0;
5107
5108         /* Restore the old MAC configured */
5109         rc = bnxt_hwrm_set_mac(bp);
5110         if (rc)
5111                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5112
5113         return rc;
5114 }
5115
5116 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5117 {
5118         if (!BNXT_PF(bp))
5119                 return;
5120
5121 #define ALLOW_FUNC(x)   \
5122         { \
5123                 uint32_t arg = (x); \
5124                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5125                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5126         }
5127
5128         /* Forward all requests if firmware is new enough */
5129         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5130              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5131             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5132                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5133         } else {
5134                 PMD_DRV_LOG(WARNING,
5135                             "Firmware too old for VF mailbox functionality\n");
5136                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5137         }
5138
5139         /*
5140          * The following are used for driver cleanup. If we disallow these,
5141          * VF drivers can't clean up cleanly.
5142          */
5143         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5144         ALLOW_FUNC(HWRM_VNIC_FREE);
5145         ALLOW_FUNC(HWRM_RING_FREE);
5146         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5147         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5148         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5149         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5150         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5151         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5152 }
5153
5154 uint16_t
5155 bnxt_get_svif(uint16_t port_id, bool func_svif,
5156               enum bnxt_ulp_intf_type type)
5157 {
5158         struct rte_eth_dev *eth_dev;
5159         struct bnxt *bp;
5160
5161         eth_dev = &rte_eth_devices[port_id];
5162         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5163                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5164                 if (!vfr)
5165                         return 0;
5166
5167                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5168                         return vfr->svif;
5169
5170                 eth_dev = vfr->parent_dev;
5171         }
5172
5173         bp = eth_dev->data->dev_private;
5174
5175         return func_svif ? bp->func_svif : bp->port_svif;
5176 }
5177
5178 uint16_t
5179 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5180 {
5181         struct rte_eth_dev *eth_dev;
5182         struct bnxt_vnic_info *vnic;
5183         struct bnxt *bp;
5184
5185         eth_dev = &rte_eth_devices[port];
5186         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5187                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5188                 if (!vfr)
5189                         return 0;
5190
5191                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5192                         return vfr->dflt_vnic_id;
5193
5194                 eth_dev = vfr->parent_dev;
5195         }
5196
5197         bp = eth_dev->data->dev_private;
5198
5199         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5200
5201         return vnic->fw_vnic_id;
5202 }
5203
5204 uint16_t
5205 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5206 {
5207         struct rte_eth_dev *eth_dev;
5208         struct bnxt *bp;
5209
5210         eth_dev = &rte_eth_devices[port];
5211         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5212                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5213                 if (!vfr)
5214                         return 0;
5215
5216                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5217                         return vfr->fw_fid;
5218
5219                 eth_dev = vfr->parent_dev;
5220         }
5221
5222         bp = eth_dev->data->dev_private;
5223
5224         return bp->fw_fid;
5225 }
5226
5227 enum bnxt_ulp_intf_type
5228 bnxt_get_interface_type(uint16_t port)
5229 {
5230         struct rte_eth_dev *eth_dev;
5231         struct bnxt *bp;
5232
5233         eth_dev = &rte_eth_devices[port];
5234         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5235                 return BNXT_ULP_INTF_TYPE_VF_REP;
5236
5237         bp = eth_dev->data->dev_private;
5238         if (BNXT_PF(bp))
5239                 return BNXT_ULP_INTF_TYPE_PF;
5240         else if (BNXT_VF_IS_TRUSTED(bp))
5241                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5242         else if (BNXT_VF(bp))
5243                 return BNXT_ULP_INTF_TYPE_VF;
5244
5245         return BNXT_ULP_INTF_TYPE_INVALID;
5246 }
5247
5248 uint16_t
5249 bnxt_get_phy_port_id(uint16_t port_id)
5250 {
5251         struct bnxt_vf_representor *vfr;
5252         struct rte_eth_dev *eth_dev;
5253         struct bnxt *bp;
5254
5255         eth_dev = &rte_eth_devices[port_id];
5256         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5257                 vfr = eth_dev->data->dev_private;
5258                 if (!vfr)
5259                         return 0;
5260
5261                 eth_dev = vfr->parent_dev;
5262         }
5263
5264         bp = eth_dev->data->dev_private;
5265
5266         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5267 }
5268
5269 uint16_t
5270 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5271 {
5272         struct rte_eth_dev *eth_dev;
5273         struct bnxt *bp;
5274
5275         eth_dev = &rte_eth_devices[port_id];
5276         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5277                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5278                 if (!vfr)
5279                         return 0;
5280
5281                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5282                         return vfr->fw_fid - 1;
5283
5284                 eth_dev = vfr->parent_dev;
5285         }
5286
5287         bp = eth_dev->data->dev_private;
5288
5289         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5290 }
5291
5292 uint16_t
5293 bnxt_get_vport(uint16_t port_id)
5294 {
5295         return (1 << bnxt_get_phy_port_id(port_id));
5296 }
5297
5298 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5299 {
5300         struct bnxt_error_recovery_info *info = bp->recovery_info;
5301
5302         if (info) {
5303                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5304                         memset(info, 0, sizeof(*info));
5305                 return;
5306         }
5307
5308         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5309                 return;
5310
5311         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5312                            sizeof(*info), 0);
5313         if (!info)
5314                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5315
5316         bp->recovery_info = info;
5317 }
5318
5319 static void bnxt_check_fw_status(struct bnxt *bp)
5320 {
5321         uint32_t fw_status;
5322
5323         if (!(bp->recovery_info &&
5324               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5325                 return;
5326
5327         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5328         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5329                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5330                             fw_status);
5331 }
5332
5333 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5334 {
5335         struct bnxt_error_recovery_info *info = bp->recovery_info;
5336         uint32_t status_loc;
5337         uint32_t sig_ver;
5338
5339         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5340                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5341         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5342                                    BNXT_GRCP_WINDOW_2_BASE +
5343                                    offsetof(struct hcomm_status,
5344                                             sig_ver)));
5345         /* If the signature is absent, then FW does not support this feature */
5346         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5347             HCOMM_STATUS_SIGNATURE_VAL)
5348                 return 0;
5349
5350         if (!info) {
5351                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5352                                    sizeof(*info), 0);
5353                 if (!info)
5354                         return -ENOMEM;
5355                 bp->recovery_info = info;
5356         } else {
5357                 memset(info, 0, sizeof(*info));
5358         }
5359
5360         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5361                                       BNXT_GRCP_WINDOW_2_BASE +
5362                                       offsetof(struct hcomm_status,
5363                                                fw_status_loc)));
5364
5365         /* Only pre-map the FW health status GRC register */
5366         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5367                 return 0;
5368
5369         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5370         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5371                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5372
5373         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5374                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5375
5376         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5377
5378         return 0;
5379 }
5380
5381 static int bnxt_init_fw(struct bnxt *bp)
5382 {
5383         uint16_t mtu;
5384         int rc = 0;
5385
5386         bp->fw_cap = 0;
5387
5388         rc = bnxt_map_hcomm_fw_status_reg(bp);
5389         if (rc)
5390                 return rc;
5391
5392         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5393         if (rc) {
5394                 bnxt_check_fw_status(bp);
5395                 return rc;
5396         }
5397
5398         rc = bnxt_hwrm_func_reset(bp);
5399         if (rc)
5400                 return -EIO;
5401
5402         rc = bnxt_hwrm_vnic_qcaps(bp);
5403         if (rc)
5404                 return rc;
5405
5406         rc = bnxt_hwrm_queue_qportcfg(bp);
5407         if (rc)
5408                 return rc;
5409
5410         /* Get the MAX capabilities for this function.
5411          * This function also allocates context memory for TQM rings and
5412          * informs the firmware about this allocated backing store memory.
5413          */
5414         rc = bnxt_hwrm_func_qcaps(bp);
5415         if (rc)
5416                 return rc;
5417
5418         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5419         if (rc)
5420                 return rc;
5421
5422         bnxt_hwrm_port_mac_qcfg(bp);
5423
5424         bnxt_hwrm_parent_pf_qcfg(bp);
5425
5426         bnxt_hwrm_port_phy_qcaps(bp);
5427
5428         bnxt_alloc_error_recovery_info(bp);
5429         /* Get the adapter error recovery support info */
5430         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5431         if (rc)
5432                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5433
5434         bnxt_hwrm_port_led_qcaps(bp);
5435
5436         return 0;
5437 }
5438
5439 static int
5440 bnxt_init_locks(struct bnxt *bp)
5441 {
5442         int err;
5443
5444         err = pthread_mutex_init(&bp->flow_lock, NULL);
5445         if (err) {
5446                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5447                 return err;
5448         }
5449
5450         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5451         if (err)
5452                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5453         return err;
5454 }
5455
5456 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5457 {
5458         int rc = 0;
5459
5460         rc = bnxt_init_fw(bp);
5461         if (rc)
5462                 return rc;
5463
5464         if (!reconfig_dev) {
5465                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5466                 if (rc)
5467                         return rc;
5468         } else {
5469                 rc = bnxt_restore_dflt_mac(bp);
5470                 if (rc)
5471                         return rc;
5472         }
5473
5474         bnxt_config_vf_req_fwd(bp);
5475
5476         rc = bnxt_hwrm_func_driver_register(bp);
5477         if (rc) {
5478                 PMD_DRV_LOG(ERR, "Failed to register driver");
5479                 return -EBUSY;
5480         }
5481
5482         if (BNXT_PF(bp)) {
5483                 if (bp->pdev->max_vfs) {
5484                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5485                         if (rc) {
5486                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5487                                 return rc;
5488                         }
5489                 } else {
5490                         rc = bnxt_hwrm_allocate_pf_only(bp);
5491                         if (rc) {
5492                                 PMD_DRV_LOG(ERR,
5493                                             "Failed to allocate PF resources");
5494                                 return rc;
5495                         }
5496                 }
5497         }
5498
5499         rc = bnxt_alloc_mem(bp, reconfig_dev);
5500         if (rc)
5501                 return rc;
5502
5503         rc = bnxt_setup_int(bp);
5504         if (rc)
5505                 return rc;
5506
5507         rc = bnxt_request_int(bp);
5508         if (rc)
5509                 return rc;
5510
5511         rc = bnxt_init_ctx_mem(bp);
5512         if (rc) {
5513                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5514                 return rc;
5515         }
5516
5517         rc = bnxt_init_locks(bp);
5518         if (rc)
5519                 return rc;
5520
5521         return 0;
5522 }
5523
5524 static int
5525 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5526                           const char *value, void *opaque_arg)
5527 {
5528         struct bnxt *bp = opaque_arg;
5529         unsigned long truflow;
5530         char *end = NULL;
5531
5532         if (!value || !opaque_arg) {
5533                 PMD_DRV_LOG(ERR,
5534                             "Invalid parameter passed to truflow devargs.\n");
5535                 return -EINVAL;
5536         }
5537
5538         truflow = strtoul(value, &end, 10);
5539         if (end == NULL || *end != '\0' ||
5540             (truflow == ULONG_MAX && errno == ERANGE)) {
5541                 PMD_DRV_LOG(ERR,
5542                             "Invalid parameter passed to truflow devargs.\n");
5543                 return -EINVAL;
5544         }
5545
5546         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5547                 PMD_DRV_LOG(ERR,
5548                             "Invalid value passed to truflow devargs.\n");
5549                 return -EINVAL;
5550         }
5551
5552         bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5553         if (BNXT_TRUFLOW_EN(bp))
5554                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5555
5556         return 0;
5557 }
5558
5559 static int
5560 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5561                              const char *value, void *opaque_arg)
5562 {
5563         struct bnxt *bp = opaque_arg;
5564         unsigned long flow_xstat;
5565         char *end = NULL;
5566
5567         if (!value || !opaque_arg) {
5568                 PMD_DRV_LOG(ERR,
5569                             "Invalid parameter passed to flow_xstat devarg.\n");
5570                 return -EINVAL;
5571         }
5572
5573         flow_xstat = strtoul(value, &end, 10);
5574         if (end == NULL || *end != '\0' ||
5575             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5576                 PMD_DRV_LOG(ERR,
5577                             "Invalid parameter passed to flow_xstat devarg.\n");
5578                 return -EINVAL;
5579         }
5580
5581         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5582                 PMD_DRV_LOG(ERR,
5583                             "Invalid value passed to flow_xstat devarg.\n");
5584                 return -EINVAL;
5585         }
5586
5587         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5588         if (BNXT_FLOW_XSTATS_EN(bp))
5589                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5590
5591         return 0;
5592 }
5593
5594 static int
5595 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5596                                         const char *value, void *opaque_arg)
5597 {
5598         struct bnxt *bp = opaque_arg;
5599         unsigned long max_num_kflows;
5600         char *end = NULL;
5601
5602         if (!value || !opaque_arg) {
5603                 PMD_DRV_LOG(ERR,
5604                         "Invalid parameter passed to max_num_kflows devarg.\n");
5605                 return -EINVAL;
5606         }
5607
5608         max_num_kflows = strtoul(value, &end, 10);
5609         if (end == NULL || *end != '\0' ||
5610                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5611                 PMD_DRV_LOG(ERR,
5612                         "Invalid parameter passed to max_num_kflows devarg.\n");
5613                 return -EINVAL;
5614         }
5615
5616         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5617                 PMD_DRV_LOG(ERR,
5618                         "Invalid value passed to max_num_kflows devarg.\n");
5619                 return -EINVAL;
5620         }
5621
5622         bp->max_num_kflows = max_num_kflows;
5623         if (bp->max_num_kflows)
5624                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5625                                 max_num_kflows);
5626
5627         return 0;
5628 }
5629
5630 static void
5631 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5632 {
5633         struct rte_kvargs *kvlist;
5634
5635         if (devargs == NULL)
5636                 return;
5637
5638         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5639         if (kvlist == NULL)
5640                 return;
5641
5642         /*
5643          * Handler for "truflow" devarg.
5644          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5645          */
5646         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5647                            bnxt_parse_devarg_truflow, bp);
5648
5649         /*
5650          * Handler for "flow_xstat" devarg.
5651          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5652          */
5653         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5654                            bnxt_parse_devarg_flow_xstat, bp);
5655
5656         /*
5657          * Handler for "max_num_kflows" devarg.
5658          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5659          */
5660         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5661                            bnxt_parse_devarg_max_num_kflows, bp);
5662
5663         rte_kvargs_free(kvlist);
5664 }
5665
5666 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5667 {
5668         int rc = 0;
5669
5670         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5671                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5672                 if (rc)
5673                         PMD_DRV_LOG(ERR,
5674                                     "Failed to alloc switch domain: %d\n", rc);
5675                 else
5676                         PMD_DRV_LOG(INFO,
5677                                     "Switch domain allocated %d\n",
5678                                     bp->switch_domain_id);
5679         }
5680
5681         return rc;
5682 }
5683
5684 static int
5685 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5686 {
5687         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5688         static int version_printed;
5689         struct bnxt *bp;
5690         int rc;
5691
5692         if (version_printed++ == 0)
5693                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5694
5695         eth_dev->dev_ops = &bnxt_dev_ops;
5696         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5697         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5698         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5699         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5700         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5701
5702         /*
5703          * For secondary processes, we don't initialise any further
5704          * as primary has already done this work.
5705          */
5706         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5707                 return 0;
5708
5709         rte_eth_copy_pci_info(eth_dev, pci_dev);
5710
5711         bp = eth_dev->data->dev_private;
5712
5713         /* Parse dev arguments passed on when starting the DPDK application. */
5714         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5715
5716         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5717
5718         if (bnxt_vf_pciid(pci_dev->id.device_id))
5719                 bp->flags |= BNXT_FLAG_VF;
5720
5721         if (bnxt_thor_device(pci_dev->id.device_id))
5722                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5723
5724         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5725             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5726             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5727             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5728                 bp->flags |= BNXT_FLAG_STINGRAY;
5729
5730         rc = bnxt_init_board(eth_dev);
5731         if (rc) {
5732                 PMD_DRV_LOG(ERR,
5733                             "Failed to initialize board rc: %x\n", rc);
5734                 return rc;
5735         }
5736
5737         rc = bnxt_alloc_pf_info(bp);
5738         if (rc)
5739                 goto error_free;
5740
5741         rc = bnxt_alloc_link_info(bp);
5742         if (rc)
5743                 goto error_free;
5744
5745         rc = bnxt_alloc_parent_info(bp);
5746         if (rc)
5747                 goto error_free;
5748
5749         rc = bnxt_alloc_hwrm_resources(bp);
5750         if (rc) {
5751                 PMD_DRV_LOG(ERR,
5752                             "Failed to allocate hwrm resource rc: %x\n", rc);
5753                 goto error_free;
5754         }
5755         rc = bnxt_alloc_leds_info(bp);
5756         if (rc)
5757                 goto error_free;
5758
5759         rc = bnxt_alloc_cos_queues(bp);
5760         if (rc)
5761                 goto error_free;
5762
5763         rc = bnxt_init_resources(bp, false);
5764         if (rc)
5765                 goto error_free;
5766
5767         rc = bnxt_alloc_stats_mem(bp);
5768         if (rc)
5769                 goto error_free;
5770
5771         bnxt_alloc_switch_domain(bp);
5772
5773         /* Pass the information to the rte_eth_dev_close() that it should also
5774          * release the private port resources.
5775          */
5776         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5777
5778         PMD_DRV_LOG(INFO,
5779                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5780                     pci_dev->mem_resource[0].phys_addr,
5781                     pci_dev->mem_resource[0].addr);
5782
5783         return 0;
5784
5785 error_free:
5786         bnxt_dev_uninit(eth_dev);
5787         return rc;
5788 }
5789
5790
5791 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5792 {
5793         if (!ctx)
5794                 return;
5795
5796         if (ctx->va)
5797                 rte_free(ctx->va);
5798
5799         ctx->va = NULL;
5800         ctx->dma = RTE_BAD_IOVA;
5801         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5802 }
5803
5804 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5805 {
5806         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5807                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5808                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5809                                   bp->flow_stat->max_fc,
5810                                   false);
5811
5812         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5813                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5814                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5815                                   bp->flow_stat->max_fc,
5816                                   false);
5817
5818         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5819                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5820         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5821
5822         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5823                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5824         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5825
5826         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5827                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5828         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5829
5830         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5831                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5832         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5833 }
5834
5835 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5836 {
5837         bnxt_unregister_fc_ctx_mem(bp);
5838
5839         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5840         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5841         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5842         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5843 }
5844
5845 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5846 {
5847         if (BNXT_FLOW_XSTATS_EN(bp))
5848                 bnxt_uninit_fc_ctx_mem(bp);
5849 }
5850
5851 static void
5852 bnxt_free_error_recovery_info(struct bnxt *bp)
5853 {
5854         rte_free(bp->recovery_info);
5855         bp->recovery_info = NULL;
5856         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5857 }
5858
5859 static void
5860 bnxt_uninit_locks(struct bnxt *bp)
5861 {
5862         pthread_mutex_destroy(&bp->flow_lock);
5863         pthread_mutex_destroy(&bp->def_cp_lock);
5864         if (bp->rep_info) {
5865                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5866                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
5867         }
5868 }
5869
5870 static int
5871 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5872 {
5873         int rc;
5874
5875         bnxt_free_int(bp);
5876         bnxt_free_mem(bp, reconfig_dev);
5877         bnxt_hwrm_func_buf_unrgtr(bp);
5878         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5879         bp->flags &= ~BNXT_FLAG_REGISTERED;
5880         bnxt_free_ctx_mem(bp);
5881         if (!reconfig_dev) {
5882                 bnxt_free_hwrm_resources(bp);
5883                 bnxt_free_error_recovery_info(bp);
5884         }
5885
5886         bnxt_uninit_ctx_mem(bp);
5887
5888         bnxt_uninit_locks(bp);
5889         bnxt_free_flow_stats_info(bp);
5890         bnxt_free_rep_info(bp);
5891         rte_free(bp->ptp_cfg);
5892         bp->ptp_cfg = NULL;
5893         return rc;
5894 }
5895
5896 static int
5897 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5898 {
5899         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5900                 return -EPERM;
5901
5902         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5903
5904         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5905                 bnxt_dev_close_op(eth_dev);
5906
5907         return 0;
5908 }
5909
5910 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5911 {
5912         struct bnxt *bp = eth_dev->data->dev_private;
5913         struct rte_eth_dev *vf_rep_eth_dev;
5914         int ret = 0, i;
5915
5916         if (!bp)
5917                 return -EINVAL;
5918
5919         for (i = 0; i < bp->num_reps; i++) {
5920                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5921                 if (!vf_rep_eth_dev)
5922                         continue;
5923                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
5924         }
5925         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5926
5927         return ret;
5928 }
5929
5930 static void bnxt_free_rep_info(struct bnxt *bp)
5931 {
5932         rte_free(bp->rep_info);
5933         bp->rep_info = NULL;
5934         rte_free(bp->cfa_code_map);
5935         bp->cfa_code_map = NULL;
5936 }
5937
5938 static int bnxt_init_rep_info(struct bnxt *bp)
5939 {
5940         int i = 0, rc;
5941
5942         if (bp->rep_info)
5943                 return 0;
5944
5945         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5946                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5947                                    0);
5948         if (!bp->rep_info) {
5949                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5950                 return -ENOMEM;
5951         }
5952         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5953                                        sizeof(*bp->cfa_code_map) *
5954                                        BNXT_MAX_CFA_CODE, 0);
5955         if (!bp->cfa_code_map) {
5956                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5957                 bnxt_free_rep_info(bp);
5958                 return -ENOMEM;
5959         }
5960
5961         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5962                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5963
5964         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5965         if (rc) {
5966                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5967                 bnxt_free_rep_info(bp);
5968                 return rc;
5969         }
5970
5971         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5972         if (rc) {
5973                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5974                 bnxt_free_rep_info(bp);
5975                 return rc;
5976         }
5977
5978         return rc;
5979 }
5980
5981 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5982                                struct rte_eth_devargs eth_da,
5983                                struct rte_eth_dev *backing_eth_dev)
5984 {
5985         struct rte_eth_dev *vf_rep_eth_dev;
5986         char name[RTE_ETH_NAME_MAX_LEN];
5987         struct bnxt *backing_bp;
5988         uint16_t num_rep;
5989         int i, ret = 0;
5990
5991         num_rep = eth_da.nb_representor_ports;
5992         if (num_rep > BNXT_MAX_VF_REPS) {
5993                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5994                             num_rep, BNXT_MAX_VF_REPS);
5995                 return -EINVAL;
5996         }
5997
5998         if (num_rep > RTE_MAX_ETHPORTS) {
5999                 PMD_DRV_LOG(ERR,
6000                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6001                             num_rep, RTE_MAX_ETHPORTS);
6002                 return -EINVAL;
6003         }
6004
6005         backing_bp = backing_eth_dev->data->dev_private;
6006
6007         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6008                 PMD_DRV_LOG(ERR,
6009                             "Not a PF or trusted VF. No Representor support\n");
6010                 /* Returning an error is not an option.
6011                  * Applications are not handling this correctly
6012                  */
6013                 return 0;
6014         }
6015
6016         if (bnxt_init_rep_info(backing_bp))
6017                 return 0;
6018
6019         for (i = 0; i < num_rep; i++) {
6020                 struct bnxt_vf_representor representor = {
6021                         .vf_id = eth_da.representor_ports[i],
6022                         .switch_domain_id = backing_bp->switch_domain_id,
6023                         .parent_dev = backing_eth_dev
6024                 };
6025
6026                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6027                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6028                                     representor.vf_id, BNXT_MAX_VF_REPS);
6029                         continue;
6030                 }
6031
6032                 /* representor port net_bdf_port */
6033                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6034                          pci_dev->device.name, eth_da.representor_ports[i]);
6035
6036                 ret = rte_eth_dev_create(&pci_dev->device, name,
6037                                          sizeof(struct bnxt_vf_representor),
6038                                          NULL, NULL,
6039                                          bnxt_vf_representor_init,
6040                                          &representor);
6041
6042                 if (!ret) {
6043                         vf_rep_eth_dev = rte_eth_dev_allocated(name);
6044                         if (!vf_rep_eth_dev) {
6045                                 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6046                                             " for VF-Rep: %s.", name);
6047                                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6048                                 ret = -ENODEV;
6049                                 return ret;
6050                         }
6051                         backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6052                                 vf_rep_eth_dev;
6053                         backing_bp->num_reps++;
6054                 } else {
6055                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6056                                     "representor %s.", name);
6057                         bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6058                 }
6059         }
6060
6061         return ret;
6062 }
6063
6064 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6065                           struct rte_pci_device *pci_dev)
6066 {
6067         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6068         struct rte_eth_dev *backing_eth_dev;
6069         uint16_t num_rep;
6070         int ret = 0;
6071
6072         if (pci_dev->device.devargs) {
6073                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6074                                             &eth_da);
6075                 if (ret)
6076                         return ret;
6077         }
6078
6079         num_rep = eth_da.nb_representor_ports;
6080         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6081                     num_rep);
6082
6083         /* We could come here after first level of probe is already invoked
6084          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6085          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6086          */
6087         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6088         if (backing_eth_dev == NULL) {
6089                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6090                                          sizeof(struct bnxt),
6091                                          eth_dev_pci_specific_init, pci_dev,
6092                                          bnxt_dev_init, NULL);
6093
6094                 if (ret || !num_rep)
6095                         return ret;
6096
6097                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6098         }
6099
6100         /* probe representor ports now */
6101         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
6102
6103         return ret;
6104 }
6105
6106 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6107 {
6108         struct rte_eth_dev *eth_dev;
6109
6110         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6111         if (!eth_dev)
6112                 return 0; /* Invoked typically only by OVS-DPDK, by the
6113                            * time it comes here the eth_dev is already
6114                            * deleted by rte_eth_dev_close(), so returning
6115                            * +ve value will at least help in proper cleanup
6116                            */
6117
6118         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6119                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6120                         return rte_eth_dev_destroy(eth_dev,
6121                                                    bnxt_vf_representor_uninit);
6122                 else
6123                         return rte_eth_dev_destroy(eth_dev,
6124                                                    bnxt_dev_uninit);
6125         } else {
6126                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6127         }
6128 }
6129
6130 static struct rte_pci_driver bnxt_rte_pmd = {
6131         .id_table = bnxt_pci_id_map,
6132         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6133                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6134                                                   * and OVS-DPDK
6135                                                   */
6136         .probe = bnxt_pci_probe,
6137         .remove = bnxt_pci_remove,
6138 };
6139
6140 static bool
6141 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6142 {
6143         if (strcmp(dev->device->driver->name, drv->driver.name))
6144                 return false;
6145
6146         return true;
6147 }
6148
6149 bool is_bnxt_supported(struct rte_eth_dev *dev)
6150 {
6151         return is_device_supported(dev, &bnxt_rte_pmd);
6152 }
6153
6154 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6155 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6156 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6157 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");