drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29 #include "bnxt_util.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  37
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  42 #define BROADCOM_DEV_ID_57301 0x16c8
  43 #define BROADCOM_DEV_ID_57302 0x16c9
  44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  47 #define BROADCOM_DEV_ID_NS2 0x16cd
  48 #define BROADCOM_DEV_ID_57311 0x16ce
  49 #define BROADCOM_DEV_ID_57312 0x16cf
  50 #define BROADCOM_DEV_ID_57402 0x16d0
  51 #define BROADCOM_DEV_ID_57404 0x16d1
  52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  56 #define BROADCOM_DEV_ID_57412 0x16d6
  57 #define BROADCOM_DEV_ID_57414 0x16d7
  58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  61 #define BROADCOM_DEV_ID_57412_MF 0x16de
  62 #define BROADCOM_DEV_ID_57314 0x16df
  63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  74 #define BROADCOM_DEV_ID_57508 0x1750
  75 #define BROADCOM_DEV_ID_57504 0x1751
  76 #define BROADCOM_DEV_ID_57502 0x1752
  77 #define BROADCOM_DEV_ID_57500_VF 0x1807
  78 #define BROADCOM_DEV_ID_58802 0xd802
  79 #define BROADCOM_DEV_ID_58804 0xd804
  80 #define BROADCOM_DEV_ID_58808 0x16f0
  81 #define BROADCOM_DEV_ID_58802_VF 0xd800
  82
  83 static const struct rte_pci_id bnxt_pci_id_map[] = {
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  85                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  87                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF) },
 130         { .vendor_id = 0, /* sentinel */ },
 131 };
 132
 133 #define BNXT_ETH_RSS_SUPPORT (  \
 134         ETH_RSS_IPV4 |          \
 135         ETH_RSS_NONFRAG_IPV4_TCP |      \
 136         ETH_RSS_NONFRAG_IPV4_UDP |      \
 137         ETH_RSS_IPV6 |          \
 138         ETH_RSS_NONFRAG_IPV6_TCP |      \
 139         ETH_RSS_NONFRAG_IPV6_UDP)
 140
 141 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 142                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 143                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 144                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 145                                      DEV_TX_OFFLOAD_TCP_TSO | \
 146                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 147                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 148                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 149                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 150                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 152
 153 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 154                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 155                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 156                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 157                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 158                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 159                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 160                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 161                                      DEV_RX_OFFLOAD_TCP_LRO)
 162
 163 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 164 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 165 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 166 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 167
 168 /***********************/
 169
 170 /*
 171  * High level utility functions
 172  */
 173
 174 static void bnxt_free_mem(struct bnxt *bp)
 175 {
 176         bnxt_free_filter_mem(bp);
 177         bnxt_free_vnic_attributes(bp);
 178         bnxt_free_vnic_mem(bp);
 179
 180         bnxt_free_stats(bp);
 181         bnxt_free_tx_rings(bp);
 182         bnxt_free_rx_rings(bp);
 183 }
 184
 185 static int bnxt_alloc_mem(struct bnxt *bp)
 186 {
 187         int rc;
 188
 189         rc = bnxt_alloc_vnic_mem(bp);
 190         if (rc)
 191                 goto alloc_mem_err;
 192
 193         rc = bnxt_alloc_vnic_attributes(bp);
 194         if (rc)
 195                 goto alloc_mem_err;
 196
 197         rc = bnxt_alloc_filter_mem(bp);
 198         if (rc)
 199                 goto alloc_mem_err;
 200
 201         return 0;
 202
 203 alloc_mem_err:
 204         bnxt_free_mem(bp);
 205         return rc;
 206 }
 207
 208 static int bnxt_init_chip(struct bnxt *bp)
 209 {
 210         struct bnxt_rx_queue *rxq;
 211         struct rte_eth_link new;
 212         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 213         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 214         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 215         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 216         uint32_t intr_vector = 0;
 217         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 218         uint32_t vec = BNXT_MISC_VEC_ID;
 219         unsigned int i, j;
 220         int rc;
 221
 222         /* disable uio/vfio intr/eventfd mapping */
 223         rte_intr_disable(intr_handle);
 224
 225         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 226                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 227                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 228                 bp->flags |= BNXT_FLAG_JUMBO;
 229         } else {
 230                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 231                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 232                 bp->flags &= ~BNXT_FLAG_JUMBO;
 233         }
 234
 235         /* THOR does not support ring groups.
 236          * But we will use the array to save RSS context IDs.
 237          */
 238         if (BNXT_CHIP_THOR(bp))
 239                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 240
 241         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 242         if (rc) {
 243                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 244                 goto err_out;
 245         }
 246
 247         rc = bnxt_alloc_hwrm_rings(bp);
 248         if (rc) {
 249                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 250                 goto err_out;
 251         }
 252
 253         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 254         if (rc) {
 255                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 256                 goto err_out;
 257         }
 258
 259         rc = bnxt_mq_rx_configure(bp);
 260         if (rc) {
 261                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 262                 goto err_out;
 263         }
 264
 265         /* VNIC configuration */
 266         for (i = 0; i < bp->nr_vnics; i++) {
 267                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 268                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 269                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 270
 271                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 272                 if (!vnic->fw_grp_ids) {
 273                         PMD_DRV_LOG(ERR,
 274                                     "Failed to alloc %d bytes for group ids\n",
 275                                     size);
 276                         rc = -ENOMEM;
 277                         goto err_out;
 278                 }
 279                 memset(vnic->fw_grp_ids, -1, size);
 280
 281                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 282                             i, vnic, vnic->fw_grp_ids);
 283
 284                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 285                 if (rc) {
 286                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 287                                 i, rc);
 288                         goto err_out;
 289                 }
 290
 291                 /* Alloc RSS context only if RSS mode is enabled */
 292                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 293                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
 294                         if (rc) {
 295                                 PMD_DRV_LOG(ERR,
 296                                         "HWRM vnic %d ctx alloc failure rc: %x\n",
 297                                         i, rc);
 298                                 goto err_out;
 299                         }
 300                 }
 301
 302                 /*
 303                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 304                  * setting is not available at this time, it will not be
 305                  * configured correctly in the CFA.
 306                  */
 307                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 308                         vnic->vlan_strip = true;
 309                 else
 310                         vnic->vlan_strip = false;
 311
 312                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 313                 if (rc) {
 314                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 315                                 i, rc);
 316                         goto err_out;
 317                 }
 318
 319                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 320                 if (rc) {
 321                         PMD_DRV_LOG(ERR,
 322                                 "HWRM vnic %d filter failure rc: %x\n",
 323                                 i, rc);
 324                         goto err_out;
 325                 }
 326
 327                 for (j = 0; j < bp->rx_nr_rings; j++) {
 328                         rxq = bp->eth_dev->data->rx_queues[j];
 329
 330                         PMD_DRV_LOG(DEBUG,
 331                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 332                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 333
 334                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 335                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 336                 }
 337
 338                 rc = bnxt_vnic_rss_configure(bp, vnic);
 339                 if (rc) {
 340                         PMD_DRV_LOG(ERR,
 341                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 342                         goto err_out;
 343                 }
 344
 345                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 346
 347                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 348                     DEV_RX_OFFLOAD_TCP_LRO)
 349                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 350                 else
 351                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 352         }
 353         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 354         if (rc) {
 355                 PMD_DRV_LOG(ERR,
 356                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 357                 goto err_out;
 358         }
 359
 360         /* check and configure queue intr-vector mapping */
 361         if ((rte_intr_cap_multiple(intr_handle) ||
 362              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 363             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 364                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 365                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 366                 if (intr_vector > bp->rx_cp_nr_rings) {
 367                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 368                                         bp->rx_cp_nr_rings);
 369                         return -ENOTSUP;
 370                 }
 371                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 372                         return -1;
 373         }
 374
 375         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 376                 intr_handle->intr_vec =
 377                         rte_zmalloc("intr_vec",
 378                                     bp->eth_dev->data->nb_rx_queues *
 379                                     sizeof(int), 0);
 380                 if (intr_handle->intr_vec == NULL) {
 381                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 382                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 383                         return -ENOMEM;
 384                 }
 385                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 386                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 387                          intr_handle->intr_vec, intr_handle->nb_efd,
 388                         intr_handle->max_intr);
 389         }
 390
 391         for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 392              queue_id++) {
 393                 intr_handle->intr_vec[queue_id] = vec;
 394                 if (vec < base + intr_handle->nb_efd - 1)
 395                         vec++;
 396         }
 397
 398         /* enable uio/vfio intr/eventfd mapping */
 399         rte_intr_enable(intr_handle);
 400
 401         rc = bnxt_get_hwrm_link_config(bp, &new);
 402         if (rc) {
 403                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 404                 goto err_out;
 405         }
 406
 407         if (!bp->link_info.link_up) {
 408                 rc = bnxt_set_hwrm_link_config(bp, true);
 409                 if (rc) {
 410                         PMD_DRV_LOG(ERR,
 411                                 "HWRM link config failure rc: %x\n", rc);
 412                         goto err_out;
 413                 }
 414         }
 415         bnxt_print_link_info(bp->eth_dev);
 416
 417         return 0;
 418
 419 err_out:
 420         bnxt_free_all_hwrm_resources(bp);
 421
 422         /* Some of the error status returned by FW may not be from errno.h */
 423         if (rc > 0)
 424                 rc = -EIO;
 425
 426         return rc;
 427 }
 428
 429 static int bnxt_shutdown_nic(struct bnxt *bp)
 430 {
 431         bnxt_free_all_hwrm_resources(bp);
 432         bnxt_free_all_filters(bp);
 433         bnxt_free_all_vnics(bp);
 434         return 0;
 435 }
 436
 437 static int bnxt_init_nic(struct bnxt *bp)
 438 {
 439         int rc;
 440
 441         rc = bnxt_init_ring_grps(bp);
 442         if (rc)
 443                 return rc;
 444
 445         bnxt_init_vnics(bp);
 446         bnxt_init_filters(bp);
 447
 448         return 0;
 449 }
 450
 451 /*
 452  * Device configuration and status function
 453  */
 454
 455 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 456                                   struct rte_eth_dev_info *dev_info)
 457 {
 458         struct bnxt *bp = eth_dev->data->dev_private;
 459         uint16_t max_vnics, i, j, vpool, vrxq;
 460         unsigned int max_rx_rings;
 461
 462         /* MAC Specifics */
 463         dev_info->max_mac_addrs = bp->max_l2_ctx;
 464         dev_info->max_hash_mac_addrs = 0;
 465
 466         /* PF/VF specifics */
 467         if (BNXT_PF(bp))
 468                 dev_info->max_vfs = bp->pdev->max_vfs;
 469         max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
 470         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 471         dev_info->max_rx_queues = max_rx_rings;
 472         dev_info->max_tx_queues = max_rx_rings;
 473         dev_info->reta_size = HW_HASH_INDEX_SIZE;
 474         dev_info->hash_key_size = 40;
 475         max_vnics = bp->max_vnics;
 476
 477         /* Fast path specifics */
 478         dev_info->min_rx_bufsize = 1;
 479         dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
 480                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
 481
 482         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 483         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 484                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 485         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 486         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 487
 488         /* *INDENT-OFF* */
 489         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 490                 .rx_thresh = {
 491                         .pthresh = 8,
 492                         .hthresh = 8,
 493                         .wthresh = 0,
 494                 },
 495                 .rx_free_thresh = 32,
 496                 /* If no descriptors available, pkts are dropped by default */
 497                 .rx_drop_en = 1,
 498         };
 499
 500         dev_info->default_txconf = (struct rte_eth_txconf) {
 501                 .tx_thresh = {
 502                         .pthresh = 32,
 503                         .hthresh = 0,
 504                         .wthresh = 0,
 505                 },
 506                 .tx_free_thresh = 32,
 507                 .tx_rs_thresh = 32,
 508         };
 509         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 510
 511         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 512         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 513         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 514         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 515         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 516
 517         /* *INDENT-ON* */
 518
 519         /*
 520          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 521          *       need further investigation.
 522          */
 523
 524         /* VMDq resources */
 525         vpool = 64; /* ETH_64_POOLS */
 526         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 527         for (i = 0; i < 4; vpool >>= 1, i++) {
 528                 if (max_vnics > vpool) {
 529                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 530                                 if (dev_info->max_rx_queues > vrxq) {
 531                                         if (vpool > vrxq)
 532                                                 vpool = vrxq;
 533                                         goto found;
 534                                 }
 535                         }
 536                         /* Not enough resources to support VMDq */
 537                         break;
 538                 }
 539         }
 540         /* Not enough resources to support VMDq */
 541         vpool = 0;
 542         vrxq = 0;
 543 found:
 544         dev_info->max_vmdq_pools = vpool;
 545         dev_info->vmdq_queue_num = vrxq;
 546
 547         dev_info->vmdq_pool_base = 0;
 548         dev_info->vmdq_queue_base = 0;
 549 }
 550
 551 /* Configure the device based on the configuration provided */
 552 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 553 {
 554         struct bnxt *bp = eth_dev->data->dev_private;
 555         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 556         int rc;
 557
 558         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 559         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 560         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 561         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 562
 563         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 564                 rc = bnxt_hwrm_check_vf_rings(bp);
 565                 if (rc) {
 566                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 567                         return -ENOSPC;
 568                 }
 569
 570                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 571                 if (rc) {
 572                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 573                         return -ENOSPC;
 574                 }
 575         } else {
 576                 /* legacy driver needs to get updated values */
 577                 rc = bnxt_hwrm_func_qcaps(bp);
 578                 if (rc) {
 579                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 580                         return rc;
 581                 }
 582         }
 583
 584         /* Inherit new configurations */
 585         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 586             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 587             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 588             bp->max_cp_rings ||
 589             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 590             bp->max_stat_ctx)
 591                 goto resource_error;
 592
 593         if (BNXT_HAS_RING_GRPS(bp) &&
 594             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 595                 goto resource_error;
 596
 597         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 598             bp->max_vnics < eth_dev->data->nb_rx_queues)
 599                 goto resource_error;
 600
 601         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 602         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 603
 604         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 605                 eth_dev->data->mtu =
 606                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 607                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 608                         BNXT_NUM_VLANS;
 609                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 610         }
 611         return 0;
 612
 613 resource_error:
 614         PMD_DRV_LOG(ERR,
 615                     "Insufficient resources to support requested config\n");
 616         PMD_DRV_LOG(ERR,
 617                     "Num Queues Requested: Tx %d, Rx %d\n",
 618                     eth_dev->data->nb_tx_queues,
 619                     eth_dev->data->nb_rx_queues);
 620         PMD_DRV_LOG(ERR,
 621                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 622                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 623                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 624         return -ENOSPC;
 625 }
 626
 627 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 628 {
 629         struct rte_eth_link *link = &eth_dev->data->dev_link;
 630
 631         if (link->link_status)
 632                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 633                         eth_dev->data->port_id,
 634                         (uint32_t)link->link_speed,
 635                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 636                         ("full-duplex") : ("half-duplex\n"));
 637         else
 638                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 639                         eth_dev->data->port_id);
 640 }
 641
 642 /*
 643  * Determine whether the current configuration requires support for scattered
 644  * receive; return 1 if scattered receive is required and 0 if not.
 645  */
 646 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 647 {
 648         uint16_t buf_size;
 649         int i;
 650
 651         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 652                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 653
 654                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 655                                       RTE_PKTMBUF_HEADROOM);
 656                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 657                         return 1;
 658         }
 659         return 0;
 660 }
 661
 662 static eth_rx_burst_t
 663 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 664 {
 665 #ifdef RTE_ARCH_X86
 666         /*
 667          * Vector mode receive can be enabled only if scatter rx is not
 668          * in use and rx offloads are limited to VLAN stripping and
 669          * CRC stripping.
 670          */
 671         if (!eth_dev->data->scattered_rx &&
 672             !(eth_dev->data->dev_conf.rxmode.offloads &
 673               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 674                 DEV_RX_OFFLOAD_KEEP_CRC |
 675                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 676                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 677                 DEV_RX_OFFLOAD_UDP_CKSUM |
 678                 DEV_RX_OFFLOAD_TCP_CKSUM |
 679                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 680                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 681                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 682                             eth_dev->data->port_id);
 683                 return bnxt_recv_pkts_vec;
 684         }
 685         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 686                     eth_dev->data->port_id);
 687         PMD_DRV_LOG(INFO,
 688                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 689                     eth_dev->data->port_id,
 690                     eth_dev->data->scattered_rx,
 691                     eth_dev->data->dev_conf.rxmode.offloads);
 692 #endif
 693         return bnxt_recv_pkts;
 694 }
 695
 696 static eth_tx_burst_t
 697 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 698 {
 699 #ifdef RTE_ARCH_X86
 700         /*
 701          * Vector mode receive can be enabled only if scatter tx is not
 702          * in use and tx offloads other than VLAN insertion are not
 703          * in use.
 704          */
 705         if (!eth_dev->data->scattered_rx &&
 706             !(eth_dev->data->dev_conf.txmode.offloads &
 707               ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
 708                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 709                             eth_dev->data->port_id);
 710                 return bnxt_xmit_pkts_vec;
 711         }
 712         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 713                     eth_dev->data->port_id);
 714         PMD_DRV_LOG(INFO,
 715                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 716                     eth_dev->data->port_id,
 717                     eth_dev->data->scattered_rx,
 718                     eth_dev->data->dev_conf.txmode.offloads);
 719 #endif
 720         return bnxt_xmit_pkts;
 721 }
 722
 723 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 724 {
 725         struct bnxt *bp = eth_dev->data->dev_private;
 726         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 727         int vlan_mask = 0;
 728         int rc;
 729
 730         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 731                 PMD_DRV_LOG(ERR,
 732                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 733                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 734         }
 735         bp->dev_stopped = 0;
 736
 737         rc = bnxt_init_chip(bp);
 738         if (rc)
 739                 goto error;
 740
 741         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 742
 743         bnxt_link_update_op(eth_dev, 1);
 744
 745         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 746                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 747         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 748                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 749         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 750         if (rc)
 751                 goto error;
 752
 753         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 754         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 755         bp->flags |= BNXT_FLAG_INIT_DONE;
 756         return 0;
 757
 758 error:
 759         bnxt_shutdown_nic(bp);
 760         bnxt_free_tx_mbufs(bp);
 761         bnxt_free_rx_mbufs(bp);
 762         return rc;
 763 }
 764
 765 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 766 {
 767         struct bnxt *bp = eth_dev->data->dev_private;
 768         int rc = 0;
 769
 770         if (!bp->link_info.link_up)
 771                 rc = bnxt_set_hwrm_link_config(bp, true);
 772         if (!rc)
 773                 eth_dev->data->dev_link.link_status = 1;
 774
 775         bnxt_print_link_info(eth_dev);
 776         return 0;
 777 }
 778
 779 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 780 {
 781         struct bnxt *bp = eth_dev->data->dev_private;
 782
 783         eth_dev->data->dev_link.link_status = 0;
 784         bnxt_set_hwrm_link_config(bp, false);
 785         bp->link_info.link_up = 0;
 786
 787         return 0;
 788 }
 789
 790 /* Unload the driver, release resources */
 791 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 792 {
 793         struct bnxt *bp = eth_dev->data->dev_private;
 794
 795         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 796         if (bp->eth_dev->data->dev_started) {
 797                 /* TBD: STOP HW queues DMA */
 798                 eth_dev->data->dev_link.link_status = 0;
 799         }
 800         bnxt_set_hwrm_link_config(bp, false);
 801         bnxt_hwrm_port_clr_stats(bp);
 802         bnxt_free_tx_mbufs(bp);
 803         bnxt_free_rx_mbufs(bp);
 804         bnxt_shutdown_nic(bp);
 805         bp->dev_stopped = 1;
 806 }
 807
 808 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 809 {
 810         struct bnxt *bp = eth_dev->data->dev_private;
 811
 812         if (bp->dev_stopped == 0)
 813                 bnxt_dev_stop_op(eth_dev);
 814
 815         if (eth_dev->data->mac_addrs != NULL) {
 816                 rte_free(eth_dev->data->mac_addrs);
 817                 eth_dev->data->mac_addrs = NULL;
 818         }
 819         if (bp->grp_info != NULL) {
 820                 rte_free(bp->grp_info);
 821                 bp->grp_info = NULL;
 822         }
 823
 824         bnxt_dev_uninit(eth_dev);
 825 }
 826
 827 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 828                                     uint32_t index)
 829 {
 830         struct bnxt *bp = eth_dev->data->dev_private;
 831         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 832         struct bnxt_vnic_info *vnic;
 833         struct bnxt_filter_info *filter, *temp_filter;
 834         uint32_t i;
 835
 836         /*
 837          * Loop through all VNICs from the specified filter flow pools to
 838          * remove the corresponding MAC addr filter
 839          */
 840         for (i = 0; i < bp->nr_vnics; i++) {
 841                 if (!(pool_mask & (1ULL << i)))
 842                         continue;
 843
 844                 vnic = &bp->vnic_info[i];
 845                 filter = STAILQ_FIRST(&vnic->filter);
 846                 while (filter) {
 847                         temp_filter = STAILQ_NEXT(filter, next);
 848                         if (filter->mac_index == index) {
 849                                 STAILQ_REMOVE(&vnic->filter, filter,
 850                                                 bnxt_filter_info, next);
 851                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 852                                 filter->mac_index = INVALID_MAC_INDEX;
 853                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 854                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 855                                                    filter, next);
 856                         }
 857                         filter = temp_filter;
 858                 }
 859         }
 860 }
 861
 862 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 863                                 struct rte_ether_addr *mac_addr,
 864                                 uint32_t index, uint32_t pool)
 865 {
 866         struct bnxt *bp = eth_dev->data->dev_private;
 867         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
 868         struct bnxt_filter_info *filter;
 869
 870         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
 871                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 872                 return -ENOTSUP;
 873         }
 874
 875         if (!vnic) {
 876                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 877                 return -EINVAL;
 878         }
 879         /* Attach requested MAC address to the new l2_filter */
 880         STAILQ_FOREACH(filter, &vnic->filter, next) {
 881                 if (filter->mac_index == index) {
 882                         PMD_DRV_LOG(ERR,
 883                                 "MAC addr already existed for pool %d\n", pool);
 884                         return 0;
 885                 }
 886         }
 887         filter = bnxt_alloc_filter(bp);
 888         if (!filter) {
 889                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 890                 return -ENODEV;
 891         }
 892         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 893         filter->mac_index = index;
 894         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
 895         return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 896 }
 897
 898 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 899 {
 900         int rc = 0;
 901         struct bnxt *bp = eth_dev->data->dev_private;
 902         struct rte_eth_link new;
 903         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 904
 905         memset(&new, 0, sizeof(new));
 906         do {
 907                 /* Retrieve link info from hardware */
 908                 rc = bnxt_get_hwrm_link_config(bp, &new);
 909                 if (rc) {
 910                         new.link_speed = ETH_LINK_SPEED_100M;
 911                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 912                         PMD_DRV_LOG(ERR,
 913                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 914                         goto out;
 915                 }
 916                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 917
 918                 if (!wait_to_complete)
 919                         break;
 920         } while (!new.link_status && cnt--);
 921
 922 out:
 923         /* Timed out or success */
 924         if (new.link_status != eth_dev->data->dev_link.link_status ||
 925         new.link_speed != eth_dev->data->dev_link.link_speed) {
 926                 memcpy(&eth_dev->data->dev_link, &new,
 927                         sizeof(struct rte_eth_link));
 928
 929                 _rte_eth_dev_callback_process(eth_dev,
 930                                               RTE_ETH_EVENT_INTR_LSC,
 931                                               NULL);
 932
 933                 bnxt_print_link_info(eth_dev);
 934         }
 935
 936         return rc;
 937 }
 938
 939 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
 940 {
 941         struct bnxt *bp = eth_dev->data->dev_private;
 942         struct bnxt_vnic_info *vnic;
 943
 944         if (bp->vnic_info == NULL)
 945                 return;
 946
 947         vnic = &bp->vnic_info[0];
 948
 949         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
 950         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 951 }
 952
 953 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
 954 {
 955         struct bnxt *bp = eth_dev->data->dev_private;
 956         struct bnxt_vnic_info *vnic;
 957
 958         if (bp->vnic_info == NULL)
 959                 return;
 960
 961         vnic = &bp->vnic_info[0];
 962
 963         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
 964         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 965 }
 966
 967 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
 968 {
 969         struct bnxt *bp = eth_dev->data->dev_private;
 970         struct bnxt_vnic_info *vnic;
 971
 972         if (bp->vnic_info == NULL)
 973                 return;
 974
 975         vnic = &bp->vnic_info[0];
 976
 977         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
 978         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 979 }
 980
 981 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
 982 {
 983         struct bnxt *bp = eth_dev->data->dev_private;
 984         struct bnxt_vnic_info *vnic;
 985
 986         if (bp->vnic_info == NULL)
 987                 return;
 988
 989         vnic = &bp->vnic_info[0];
 990
 991         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
 992         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 993 }
 994
 995 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
 996 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
 997 {
 998         if (qid >= bp->rx_nr_rings)
 999                 return NULL;
1000
1001         return bp->eth_dev->data->rx_queues[qid];
1002 }
1003
1004 /* Return rxq corresponding to a given rss table ring/group ID. */
1005 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1006 {
1007         unsigned int i;
1008
1009         for (i = 0; i < bp->rx_nr_rings; i++) {
1010                 if (bp->grp_info[i].fw_grp_id == fwr)
1011                         return i;
1012         }
1013
1014         return INVALID_HW_RING_ID;
1015 }
1016
1017 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1018                             struct rte_eth_rss_reta_entry64 *reta_conf,
1019                             uint16_t reta_size)
1020 {
1021         struct bnxt *bp = eth_dev->data->dev_private;
1022         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1023         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1024         uint16_t tbl_size = HW_HASH_INDEX_SIZE;
1025         uint16_t idx, sft;
1026         int i;
1027
1028         if (!vnic->rss_table)
1029                 return -EINVAL;
1030
1031         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1032                 return -EINVAL;
1033
1034         if (reta_size != tbl_size) {
1035                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1036                         "(%d) must equal the size supported by the hardware "
1037                         "(%d)\n", reta_size, tbl_size);
1038                 return -EINVAL;
1039         }
1040
1041         for (i = 0; i < reta_size; i++) {
1042                 struct bnxt_rx_queue *rxq;
1043
1044                 idx = i / RTE_RETA_GROUP_SIZE;
1045                 sft = i % RTE_RETA_GROUP_SIZE;
1046
1047                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1048                         continue;
1049
1050                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1051                 if (!rxq) {
1052                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1053                         return -EINVAL;
1054                 }
1055
1056                 vnic->rss_table[i] =
1057                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1058         }
1059
1060         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1061         return 0;
1062 }
1063
1064 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1065                               struct rte_eth_rss_reta_entry64 *reta_conf,
1066                               uint16_t reta_size)
1067 {
1068         struct bnxt *bp = eth_dev->data->dev_private;
1069         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1070         uint16_t tbl_size = HW_HASH_INDEX_SIZE;
1071         uint16_t idx, sft, i;
1072
1073         /* Retrieve from the default VNIC */
1074         if (!vnic)
1075                 return -EINVAL;
1076         if (!vnic->rss_table)
1077                 return -EINVAL;
1078
1079         if (reta_size != tbl_size) {
1080                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1081                         "(%d) must equal the size supported by the hardware "
1082                         "(%d)\n", reta_size, tbl_size);
1083                 return -EINVAL;
1084         }
1085
1086         for (idx = 0, i = 0; i < reta_size; i++) {
1087                 idx = i / RTE_RETA_GROUP_SIZE;
1088                 sft = i % RTE_RETA_GROUP_SIZE;
1089
1090                 if (reta_conf[idx].mask & (1ULL << sft)) {
1091                         uint16_t qid;
1092
1093                         qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1094
1095                         if (qid == INVALID_HW_RING_ID) {
1096                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1097                                 return -EINVAL;
1098                         }
1099                         reta_conf[idx].reta[sft] = qid;
1100                 }
1101         }
1102
1103         return 0;
1104 }
1105
1106 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1107                                    struct rte_eth_rss_conf *rss_conf)
1108 {
1109         struct bnxt *bp = eth_dev->data->dev_private;
1110         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1111         struct bnxt_vnic_info *vnic;
1112         uint16_t hash_type = 0;
1113         unsigned int i;
1114
1115         /*
1116          * If RSS enablement were different than dev_configure,
1117          * then return -EINVAL
1118          */
1119         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1120                 if (!rss_conf->rss_hf)
1121                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1122         } else {
1123                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1124                         return -EINVAL;
1125         }
1126
1127         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1128         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1129
1130         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1131                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1132         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1133                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1134         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1135                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1136         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1137                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1138         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1139                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1140         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1141                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1142
1143         /* Update the RSS VNIC(s) */
1144         for (i = 0; i < bp->nr_vnics; i++) {
1145                 vnic = &bp->vnic_info[i];
1146                 vnic->hash_type = hash_type;
1147
1148                 /*
1149                  * Use the supplied key if the key length is
1150                  * acceptable and the rss_key is not NULL
1151                  */
1152                 if (rss_conf->rss_key &&
1153                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1154                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1155                                rss_conf->rss_key_len);
1156
1157                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1158         }
1159         return 0;
1160 }
1161
1162 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1163                                      struct rte_eth_rss_conf *rss_conf)
1164 {
1165         struct bnxt *bp = eth_dev->data->dev_private;
1166         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1167         int len;
1168         uint32_t hash_types;
1169
1170         /* RSS configuration is the same for all VNICs */
1171         if (vnic && vnic->rss_hash_key) {
1172                 if (rss_conf->rss_key) {
1173                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1174                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1175                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1176                 }
1177
1178                 hash_types = vnic->hash_type;
1179                 rss_conf->rss_hf = 0;
1180                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1181                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1182                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1183                 }
1184                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1185                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1186                         hash_types &=
1187                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1188                 }
1189                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1190                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1191                         hash_types &=
1192                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1193                 }
1194                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1195                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1196                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1197                 }
1198                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1199                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1200                         hash_types &=
1201                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1202                 }
1203                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1204                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1205                         hash_types &=
1206                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1207                 }
1208                 if (hash_types) {
1209                         PMD_DRV_LOG(ERR,
1210                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1211                                 vnic->hash_type);
1212                         return -ENOTSUP;
1213                 }
1214         } else {
1215                 rss_conf->rss_hf = 0;
1216         }
1217         return 0;
1218 }
1219
1220 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1221                                struct rte_eth_fc_conf *fc_conf)
1222 {
1223         struct bnxt *bp = dev->data->dev_private;
1224         struct rte_eth_link link_info;
1225         int rc;
1226
1227         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1228         if (rc)
1229                 return rc;
1230
1231         memset(fc_conf, 0, sizeof(*fc_conf));
1232         if (bp->link_info.auto_pause)
1233                 fc_conf->autoneg = 1;
1234         switch (bp->link_info.pause) {
1235         case 0:
1236                 fc_conf->mode = RTE_FC_NONE;
1237                 break;
1238         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1239                 fc_conf->mode = RTE_FC_TX_PAUSE;
1240                 break;
1241         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1242                 fc_conf->mode = RTE_FC_RX_PAUSE;
1243                 break;
1244         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1245                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1246                 fc_conf->mode = RTE_FC_FULL;
1247                 break;
1248         }
1249         return 0;
1250 }
1251
1252 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1253                                struct rte_eth_fc_conf *fc_conf)
1254 {
1255         struct bnxt *bp = dev->data->dev_private;
1256
1257         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1258                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1259                 return -ENOTSUP;
1260         }
1261
1262         switch (fc_conf->mode) {
1263         case RTE_FC_NONE:
1264                 bp->link_info.auto_pause = 0;
1265                 bp->link_info.force_pause = 0;
1266                 break;
1267         case RTE_FC_RX_PAUSE:
1268                 if (fc_conf->autoneg) {
1269                         bp->link_info.auto_pause =
1270                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1271                         bp->link_info.force_pause = 0;
1272                 } else {
1273                         bp->link_info.auto_pause = 0;
1274                         bp->link_info.force_pause =
1275                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1276                 }
1277                 break;
1278         case RTE_FC_TX_PAUSE:
1279                 if (fc_conf->autoneg) {
1280                         bp->link_info.auto_pause =
1281                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1282                         bp->link_info.force_pause = 0;
1283                 } else {
1284                         bp->link_info.auto_pause = 0;
1285                         bp->link_info.force_pause =
1286                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1287                 }
1288                 break;
1289         case RTE_FC_FULL:
1290                 if (fc_conf->autoneg) {
1291                         bp->link_info.auto_pause =
1292                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1293                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1294                         bp->link_info.force_pause = 0;
1295                 } else {
1296                         bp->link_info.auto_pause = 0;
1297                         bp->link_info.force_pause =
1298                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1299                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1300                 }
1301                 break;
1302         }
1303         return bnxt_set_hwrm_link_config(bp, true);
1304 }
1305
1306 /* Add UDP tunneling port */
1307 static int
1308 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1309                          struct rte_eth_udp_tunnel *udp_tunnel)
1310 {
1311         struct bnxt *bp = eth_dev->data->dev_private;
1312         uint16_t tunnel_type = 0;
1313         int rc = 0;
1314
1315         switch (udp_tunnel->prot_type) {
1316         case RTE_TUNNEL_TYPE_VXLAN:
1317                 if (bp->vxlan_port_cnt) {
1318                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1319                                 udp_tunnel->udp_port);
1320                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1321                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1322                                 return -ENOSPC;
1323                         }
1324                         bp->vxlan_port_cnt++;
1325                         return 0;
1326                 }
1327                 tunnel_type =
1328                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1329                 bp->vxlan_port_cnt++;
1330                 break;
1331         case RTE_TUNNEL_TYPE_GENEVE:
1332                 if (bp->geneve_port_cnt) {
1333                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1334                                 udp_tunnel->udp_port);
1335                         if (bp->geneve_port != udp_tunnel->udp_port) {
1336                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1337                                 return -ENOSPC;
1338                         }
1339                         bp->geneve_port_cnt++;
1340                         return 0;
1341                 }
1342                 tunnel_type =
1343                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1344                 bp->geneve_port_cnt++;
1345                 break;
1346         default:
1347                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1348                 return -ENOTSUP;
1349         }
1350         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1351                                              tunnel_type);
1352         return rc;
1353 }
1354
1355 static int
1356 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1357                          struct rte_eth_udp_tunnel *udp_tunnel)
1358 {
1359         struct bnxt *bp = eth_dev->data->dev_private;
1360         uint16_t tunnel_type = 0;
1361         uint16_t port = 0;
1362         int rc = 0;
1363
1364         switch (udp_tunnel->prot_type) {
1365         case RTE_TUNNEL_TYPE_VXLAN:
1366                 if (!bp->vxlan_port_cnt) {
1367                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1368                         return -EINVAL;
1369                 }
1370                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1371                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1372                                 udp_tunnel->udp_port, bp->vxlan_port);
1373                         return -EINVAL;
1374                 }
1375                 if (--bp->vxlan_port_cnt)
1376                         return 0;
1377
1378                 tunnel_type =
1379                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1380                 port = bp->vxlan_fw_dst_port_id;
1381                 break;
1382         case RTE_TUNNEL_TYPE_GENEVE:
1383                 if (!bp->geneve_port_cnt) {
1384                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1385                         return -EINVAL;
1386                 }
1387                 if (bp->geneve_port != udp_tunnel->udp_port) {
1388                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1389                                 udp_tunnel->udp_port, bp->geneve_port);
1390                         return -EINVAL;
1391                 }
1392                 if (--bp->geneve_port_cnt)
1393                         return 0;
1394
1395                 tunnel_type =
1396                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1397                 port = bp->geneve_fw_dst_port_id;
1398                 break;
1399         default:
1400                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1401                 return -ENOTSUP;
1402         }
1403
1404         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1405         if (!rc) {
1406                 if (tunnel_type ==
1407                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1408                         bp->vxlan_port = 0;
1409                 if (tunnel_type ==
1410                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1411                         bp->geneve_port = 0;
1412         }
1413         return rc;
1414 }
1415
1416 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1417 {
1418         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1419         struct bnxt_vnic_info *vnic;
1420         unsigned int i;
1421         int rc = 0;
1422         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1423
1424         /* Cycle through all VNICs */
1425         for (i = 0; i < bp->nr_vnics; i++) {
1426                 /*
1427                  * For each VNIC and each associated filter(s)
1428                  * if VLAN exists && VLAN matches vlan_id
1429                  *      remove the MAC+VLAN filter
1430                  *      add a new MAC only filter
1431                  * else
1432                  *      VLAN filter doesn't exist, just skip and continue
1433                  */
1434                 vnic = &bp->vnic_info[i];
1435                 filter = STAILQ_FIRST(&vnic->filter);
1436                 while (filter) {
1437                         temp_filter = STAILQ_NEXT(filter, next);
1438
1439                         if (filter->enables & chk &&
1440                             filter->l2_ovlan == vlan_id) {
1441                                 /* Must delete the filter */
1442                                 STAILQ_REMOVE(&vnic->filter, filter,
1443                                               bnxt_filter_info, next);
1444                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1445                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1446                                                    filter, next);
1447
1448                                 /*
1449                                  * Need to examine to see if the MAC
1450                                  * filter already existed or not before
1451                                  * allocating a new one
1452                                  */
1453
1454                                 new_filter = bnxt_alloc_filter(bp);
1455                                 if (!new_filter) {
1456                                         PMD_DRV_LOG(ERR,
1457                                                         "MAC/VLAN filter alloc failed\n");
1458                                         rc = -ENOMEM;
1459                                         goto exit;
1460                                 }
1461                                 STAILQ_INSERT_TAIL(&vnic->filter,
1462                                                 new_filter, next);
1463                                 /* Inherit MAC from previous filter */
1464                                 new_filter->mac_index =
1465                                         filter->mac_index;
1466                                 memcpy(new_filter->l2_addr, filter->l2_addr,
1467                                        RTE_ETHER_ADDR_LEN);
1468                                 /* MAC only filter */
1469                                 rc = bnxt_hwrm_set_l2_filter(bp,
1470                                                              vnic->fw_vnic_id,
1471                                                              new_filter);
1472                                 if (rc)
1473                                         goto exit;
1474                                 PMD_DRV_LOG(INFO,
1475                                             "Del Vlan filter for %d\n",
1476                                             vlan_id);
1477                         }
1478                         filter = temp_filter;
1479                 }
1480         }
1481 exit:
1482         return rc;
1483 }
1484
1485 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1486 {
1487         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1488         struct bnxt_vnic_info *vnic;
1489         unsigned int i;
1490         int rc = 0;
1491         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1492                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1493         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1494
1495         /* Cycle through all VNICs */
1496         for (i = 0; i < bp->nr_vnics; i++) {
1497                 /*
1498                  * For each VNIC and each associated filter(s)
1499                  * if VLAN exists:
1500                  *   if VLAN matches vlan_id
1501                  *      VLAN filter already exists, just skip and continue
1502                  *   else
1503                  *      add a new MAC+VLAN filter
1504                  * else
1505                  *   Remove the old MAC only filter
1506                  *    Add a new MAC+VLAN filter
1507                  */
1508                 vnic = &bp->vnic_info[i];
1509                 filter = STAILQ_FIRST(&vnic->filter);
1510                 while (filter) {
1511                         temp_filter = STAILQ_NEXT(filter, next);
1512
1513                         if (filter->enables & chk) {
1514                                 if (filter->l2_ivlan == vlan_id)
1515                                         goto cont;
1516                         } else {
1517                                 /* Must delete the MAC filter */
1518                                 STAILQ_REMOVE(&vnic->filter, filter,
1519                                                 bnxt_filter_info, next);
1520                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1521                                 filter->l2_ovlan = 0;
1522                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1523                                                    filter, next);
1524                         }
1525                         new_filter = bnxt_alloc_filter(bp);
1526                         if (!new_filter) {
1527                                 PMD_DRV_LOG(ERR,
1528                                                 "MAC/VLAN filter alloc failed\n");
1529                                 rc = -ENOMEM;
1530                                 goto exit;
1531                         }
1532                         STAILQ_INSERT_TAIL(&vnic->filter, new_filter, next);
1533                         /* Inherit MAC from the previous filter */
1534                         new_filter->mac_index = filter->mac_index;
1535                         memcpy(new_filter->l2_addr, filter->l2_addr,
1536                                RTE_ETHER_ADDR_LEN);
1537                         /* MAC + VLAN ID filter */
1538                         new_filter->l2_ivlan = vlan_id;
1539                         new_filter->l2_ivlan_mask = 0xF000;
1540                         new_filter->enables |= en;
1541                         rc = bnxt_hwrm_set_l2_filter(bp,
1542                                         vnic->fw_vnic_id,
1543                                         new_filter);
1544                         if (rc)
1545                                 goto exit;
1546                         PMD_DRV_LOG(INFO,
1547                                     "Added Vlan filter for %d\n", vlan_id);
1548 cont:
1549                         filter = temp_filter;
1550                 }
1551         }
1552 exit:
1553         return rc;
1554 }
1555
1556 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1557                 uint16_t vlan_id, int on)
1558 {
1559         struct bnxt *bp = eth_dev->data->dev_private;
1560
1561         /* These operations apply to ALL existing MAC/VLAN filters */
1562         if (on)
1563                 return bnxt_add_vlan_filter(bp, vlan_id);
1564         else
1565                 return bnxt_del_vlan_filter(bp, vlan_id);
1566 }
1567
1568 static int
1569 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1570 {
1571         struct bnxt *bp = dev->data->dev_private;
1572         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1573         unsigned int i;
1574
1575         if (mask & ETH_VLAN_FILTER_MASK) {
1576                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1577                         /* Remove any VLAN filters programmed */
1578                         for (i = 0; i < 4095; i++)
1579                                 bnxt_del_vlan_filter(bp, i);
1580                 }
1581                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1582                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1583         }
1584
1585         if (mask & ETH_VLAN_STRIP_MASK) {
1586                 /* Enable or disable VLAN stripping */
1587                 for (i = 0; i < bp->nr_vnics; i++) {
1588                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1589                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1590                                 vnic->vlan_strip = true;
1591                         else
1592                                 vnic->vlan_strip = false;
1593                         bnxt_hwrm_vnic_cfg(bp, vnic);
1594                 }
1595                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1596                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1597         }
1598
1599         if (mask & ETH_VLAN_EXTEND_MASK)
1600                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1601
1602         return 0;
1603 }
1604
1605 static int
1606 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1607                         struct rte_ether_addr *addr)
1608 {
1609         struct bnxt *bp = dev->data->dev_private;
1610         /* Default Filter is tied to VNIC 0 */
1611         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1612         struct bnxt_filter_info *filter;
1613         int rc;
1614
1615         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1616                 return -EPERM;
1617
1618         memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1619
1620         STAILQ_FOREACH(filter, &vnic->filter, next) {
1621                 /* Default Filter is at Index 0 */
1622                 if (filter->mac_index != 0)
1623                         continue;
1624                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1625                 if (rc)
1626                         return rc;
1627                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1628                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1629                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1630                 filter->enables |=
1631                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1632                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1633                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1634                 if (rc)
1635                         return rc;
1636                 filter->mac_index = 0;
1637                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1638         }
1639
1640         return 0;
1641 }
1642
1643 static int
1644 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1645                           struct rte_ether_addr *mc_addr_set,
1646                           uint32_t nb_mc_addr)
1647 {
1648         struct bnxt *bp = eth_dev->data->dev_private;
1649         char *mc_addr_list = (char *)mc_addr_set;
1650         struct bnxt_vnic_info *vnic;
1651         uint32_t off = 0, i = 0;
1652
1653         vnic = &bp->vnic_info[0];
1654
1655         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1656                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1657                 goto allmulti;
1658         }
1659
1660         /* TODO Check for Duplicate mcast addresses */
1661         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1662         for (i = 0; i < nb_mc_addr; i++) {
1663                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1664                         RTE_ETHER_ADDR_LEN);
1665                 off += RTE_ETHER_ADDR_LEN;
1666         }
1667
1668         vnic->mc_addr_cnt = i;
1669
1670 allmulti:
1671         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1672 }
1673
1674 static int
1675 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1676 {
1677         struct bnxt *bp = dev->data->dev_private;
1678         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1679         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1680         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1681         int ret;
1682
1683         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1684                         fw_major, fw_minor, fw_updt);
1685
1686         ret += 1; /* add the size of '\0' */
1687         if (fw_size < (uint32_t)ret)
1688                 return ret;
1689         else
1690                 return 0;
1691 }
1692
1693 static void
1694 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1695         struct rte_eth_rxq_info *qinfo)
1696 {
1697         struct bnxt_rx_queue *rxq;
1698
1699         rxq = dev->data->rx_queues[queue_id];
1700
1701         qinfo->mp = rxq->mb_pool;
1702         qinfo->scattered_rx = dev->data->scattered_rx;
1703         qinfo->nb_desc = rxq->nb_rx_desc;
1704
1705         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1706         qinfo->conf.rx_drop_en = 0;
1707         qinfo->conf.rx_deferred_start = 0;
1708 }
1709
1710 static void
1711 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1712         struct rte_eth_txq_info *qinfo)
1713 {
1714         struct bnxt_tx_queue *txq;
1715
1716         txq = dev->data->tx_queues[queue_id];
1717
1718         qinfo->nb_desc = txq->nb_tx_desc;
1719
1720         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1721         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1722         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1723
1724         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1725         qinfo->conf.tx_rs_thresh = 0;
1726         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1727 }
1728
1729 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1730 {
1731         struct bnxt *bp = eth_dev->data->dev_private;
1732         struct rte_eth_dev_info dev_info;
1733         uint32_t new_pkt_size;
1734         uint32_t rc = 0;
1735         uint32_t i;
1736
1737         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1738                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1739
1740         bnxt_dev_info_get_op(eth_dev, &dev_info);
1741
1742         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1743                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1744                         RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1745                 return -EINVAL;
1746         }
1747
1748 #ifdef RTE_ARCH_X86
1749         /*
1750          * If vector-mode tx/rx is active, disallow any MTU change that would
1751          * require scattered receive support.
1752          */
1753         if (eth_dev->data->dev_started &&
1754             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1755              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1756             (new_pkt_size >
1757              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1758                 PMD_DRV_LOG(ERR,
1759                             "MTU change would require scattered rx support. ");
1760                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1761                 return -EINVAL;
1762         }
1763 #endif
1764
1765         if (new_mtu > RTE_ETHER_MTU) {
1766                 bp->flags |= BNXT_FLAG_JUMBO;
1767                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1768                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1769         } else {
1770                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1771                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1772                 bp->flags &= ~BNXT_FLAG_JUMBO;
1773         }
1774
1775         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1776
1777         eth_dev->data->mtu = new_mtu;
1778         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1779
1780         for (i = 0; i < bp->nr_vnics; i++) {
1781                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1782                 uint16_t size = 0;
1783
1784                 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1785                                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1786                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1787                 if (rc)
1788                         break;
1789
1790                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1791                 size -= RTE_PKTMBUF_HEADROOM;
1792
1793                 if (size < new_mtu) {
1794                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1795                         if (rc)
1796                                 return rc;
1797                 }
1798         }
1799
1800         return rc;
1801 }
1802
1803 static int
1804 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1805 {
1806         struct bnxt *bp = dev->data->dev_private;
1807         uint16_t vlan = bp->vlan;
1808         int rc;
1809
1810         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1811                 PMD_DRV_LOG(ERR,
1812                         "PVID cannot be modified for this function\n");
1813                 return -ENOTSUP;
1814         }
1815         bp->vlan = on ? pvid : 0;
1816
1817         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1818         if (rc)
1819                 bp->vlan = vlan;
1820         return rc;
1821 }
1822
1823 static int
1824 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1825 {
1826         struct bnxt *bp = dev->data->dev_private;
1827
1828         return bnxt_hwrm_port_led_cfg(bp, true);
1829 }
1830
1831 static int
1832 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1833 {
1834         struct bnxt *bp = dev->data->dev_private;
1835
1836         return bnxt_hwrm_port_led_cfg(bp, false);
1837 }
1838
1839 static uint32_t
1840 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1841 {
1842         uint32_t desc = 0, raw_cons = 0, cons;
1843         struct bnxt_cp_ring_info *cpr;
1844         struct bnxt_rx_queue *rxq;
1845         struct rx_pkt_cmpl *rxcmp;
1846         uint16_t cmp_type;
1847         uint8_t cmp = 1;
1848         bool valid;
1849
1850         rxq = dev->data->rx_queues[rx_queue_id];
1851         cpr = rxq->cp_ring;
1852         valid = cpr->valid;
1853
1854         while (raw_cons < rxq->nb_rx_desc) {
1855                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1856                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1857
1858                 if (!CMPL_VALID(rxcmp, valid))
1859                         goto nothing_to_do;
1860                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1861                 cmp_type = CMP_TYPE(rxcmp);
1862                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1863                         cmp = (rte_le_to_cpu_32(
1864                                         ((struct rx_tpa_end_cmpl *)
1865                                          (rxcmp))->agg_bufs_v1) &
1866                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1867                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1868                         desc++;
1869                 } else if (cmp_type == 0x11) {
1870                         desc++;
1871                         cmp = (rxcmp->agg_bufs_v1 &
1872                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1873                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1874                 } else {
1875                         cmp = 1;
1876                 }
1877 nothing_to_do:
1878                 raw_cons += cmp ? cmp : 2;
1879         }
1880
1881         return desc;
1882 }
1883
1884 static int
1885 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1886 {
1887         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1888         struct bnxt_rx_ring_info *rxr;
1889         struct bnxt_cp_ring_info *cpr;
1890         struct bnxt_sw_rx_bd *rx_buf;
1891         struct rx_pkt_cmpl *rxcmp;
1892         uint32_t cons, cp_cons;
1893
1894         if (!rxq)
1895                 return -EINVAL;
1896
1897         cpr = rxq->cp_ring;
1898         rxr = rxq->rx_ring;
1899
1900         if (offset >= rxq->nb_rx_desc)
1901                 return -EINVAL;
1902
1903         cons = RING_CMP(cpr->cp_ring_struct, offset);
1904         cp_cons = cpr->cp_raw_cons;
1905         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1906
1907         if (cons > cp_cons) {
1908                 if (CMPL_VALID(rxcmp, cpr->valid))
1909                         return RTE_ETH_RX_DESC_DONE;
1910         } else {
1911                 if (CMPL_VALID(rxcmp, !cpr->valid))
1912                         return RTE_ETH_RX_DESC_DONE;
1913         }
1914         rx_buf = &rxr->rx_buf_ring[cons];
1915         if (rx_buf->mbuf == NULL)
1916                 return RTE_ETH_RX_DESC_UNAVAIL;
1917
1918
1919         return RTE_ETH_RX_DESC_AVAIL;
1920 }
1921
1922 static int
1923 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1924 {
1925         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1926         struct bnxt_tx_ring_info *txr;
1927         struct bnxt_cp_ring_info *cpr;
1928         struct bnxt_sw_tx_bd *tx_buf;
1929         struct tx_pkt_cmpl *txcmp;
1930         uint32_t cons, cp_cons;
1931
1932         if (!txq)
1933                 return -EINVAL;
1934
1935         cpr = txq->cp_ring;
1936         txr = txq->tx_ring;
1937
1938         if (offset >= txq->nb_tx_desc)
1939                 return -EINVAL;
1940
1941         cons = RING_CMP(cpr->cp_ring_struct, offset);
1942         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1943         cp_cons = cpr->cp_raw_cons;
1944
1945         if (cons > cp_cons) {
1946                 if (CMPL_VALID(txcmp, cpr->valid))
1947                         return RTE_ETH_TX_DESC_UNAVAIL;
1948         } else {
1949                 if (CMPL_VALID(txcmp, !cpr->valid))
1950                         return RTE_ETH_TX_DESC_UNAVAIL;
1951         }
1952         tx_buf = &txr->tx_buf_ring[cons];
1953         if (tx_buf->mbuf == NULL)
1954                 return RTE_ETH_TX_DESC_DONE;
1955
1956         return RTE_ETH_TX_DESC_FULL;
1957 }
1958
1959 static struct bnxt_filter_info *
1960 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1961                                 struct rte_eth_ethertype_filter *efilter,
1962                                 struct bnxt_vnic_info *vnic0,
1963                                 struct bnxt_vnic_info *vnic,
1964                                 int *ret)
1965 {
1966         struct bnxt_filter_info *mfilter = NULL;
1967         int match = 0;
1968         *ret = 0;
1969
1970         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
1971                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
1972                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1973                         " ethertype filter.", efilter->ether_type);
1974                 *ret = -EINVAL;
1975                 goto exit;
1976         }
1977         if (efilter->queue >= bp->rx_nr_rings) {
1978                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1979                 *ret = -EINVAL;
1980                 goto exit;
1981         }
1982
1983         vnic0 = &bp->vnic_info[0];
1984         vnic = &bp->vnic_info[efilter->queue];
1985         if (vnic == NULL) {
1986                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1987                 *ret = -EINVAL;
1988                 goto exit;
1989         }
1990
1991         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1992                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1993                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1994                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
1995                              mfilter->flags ==
1996                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1997                              mfilter->ethertype == efilter->ether_type)) {
1998                                 match = 1;
1999                                 break;
2000                         }
2001                 }
2002         } else {
2003                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2004                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2005                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2006                              mfilter->ethertype == efilter->ether_type &&
2007                              mfilter->flags ==
2008                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2009                                 match = 1;
2010                                 break;
2011                         }
2012         }
2013
2014         if (match)
2015                 *ret = -EEXIST;
2016
2017 exit:
2018         return mfilter;
2019 }
2020
2021 static int
2022 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2023                         enum rte_filter_op filter_op,
2024                         void *arg)
2025 {
2026         struct bnxt *bp = dev->data->dev_private;
2027         struct rte_eth_ethertype_filter *efilter =
2028                         (struct rte_eth_ethertype_filter *)arg;
2029         struct bnxt_filter_info *bfilter, *filter1;
2030         struct bnxt_vnic_info *vnic, *vnic0;
2031         int ret;
2032
2033         if (filter_op == RTE_ETH_FILTER_NOP)
2034                 return 0;
2035
2036         if (arg == NULL) {
2037                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2038                             filter_op);
2039                 return -EINVAL;
2040         }
2041
2042         vnic0 = &bp->vnic_info[0];
2043         vnic = &bp->vnic_info[efilter->queue];
2044
2045         switch (filter_op) {
2046         case RTE_ETH_FILTER_ADD:
2047                 bnxt_match_and_validate_ether_filter(bp, efilter,
2048                                                         vnic0, vnic, &ret);
2049                 if (ret < 0)
2050                         return ret;
2051
2052                 bfilter = bnxt_get_unused_filter(bp);
2053                 if (bfilter == NULL) {
2054                         PMD_DRV_LOG(ERR,
2055                                 "Not enough resources for a new filter.\n");
2056                         return -ENOMEM;
2057                 }
2058                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2059                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2060                        RTE_ETHER_ADDR_LEN);
2061                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2062                        RTE_ETHER_ADDR_LEN);
2063                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2064                 bfilter->ethertype = efilter->ether_type;
2065                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2066
2067                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2068                 if (filter1 == NULL) {
2069                         ret = -1;
2070                         goto cleanup;
2071                 }
2072                 bfilter->enables |=
2073                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2074                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2075
2076                 bfilter->dst_id = vnic->fw_vnic_id;
2077
2078                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2079                         bfilter->flags =
2080                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2081                 }
2082
2083                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2084                 if (ret)
2085                         goto cleanup;
2086                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2087                 break;
2088         case RTE_ETH_FILTER_DELETE:
2089                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2090                                                         vnic0, vnic, &ret);
2091                 if (ret == -EEXIST) {
2092                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2093
2094                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2095                                       next);
2096                         bnxt_free_filter(bp, filter1);
2097                 } else if (ret == 0) {
2098                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2099                 }
2100                 break;
2101         default:
2102                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2103                 ret = -EINVAL;
2104                 goto error;
2105         }
2106         return ret;
2107 cleanup:
2108         bnxt_free_filter(bp, bfilter);
2109 error:
2110         return ret;
2111 }
2112
2113 static inline int
2114 parse_ntuple_filter(struct bnxt *bp,
2115                     struct rte_eth_ntuple_filter *nfilter,
2116                     struct bnxt_filter_info *bfilter)
2117 {
2118         uint32_t en = 0;
2119
2120         if (nfilter->queue >= bp->rx_nr_rings) {
2121                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2122                 return -EINVAL;
2123         }
2124
2125         switch (nfilter->dst_port_mask) {
2126         case UINT16_MAX:
2127                 bfilter->dst_port_mask = -1;
2128                 bfilter->dst_port = nfilter->dst_port;
2129                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2130                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2131                 break;
2132         default:
2133                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2134                 return -EINVAL;
2135         }
2136
2137         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2138         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2139
2140         switch (nfilter->proto_mask) {
2141         case UINT8_MAX:
2142                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2143                         bfilter->ip_protocol = 17;
2144                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2145                         bfilter->ip_protocol = 6;
2146                 else
2147                         return -EINVAL;
2148                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2149                 break;
2150         default:
2151                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2152                 return -EINVAL;
2153         }
2154
2155         switch (nfilter->dst_ip_mask) {
2156         case UINT32_MAX:
2157                 bfilter->dst_ipaddr_mask[0] = -1;
2158                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2159                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2160                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2161                 break;
2162         default:
2163                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2164                 return -EINVAL;
2165         }
2166
2167         switch (nfilter->src_ip_mask) {
2168         case UINT32_MAX:
2169                 bfilter->src_ipaddr_mask[0] = -1;
2170                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2171                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2172                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2173                 break;
2174         default:
2175                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2176                 return -EINVAL;
2177         }
2178
2179         switch (nfilter->src_port_mask) {
2180         case UINT16_MAX:
2181                 bfilter->src_port_mask = -1;
2182                 bfilter->src_port = nfilter->src_port;
2183                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2184                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2185                 break;
2186         default:
2187                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2188                 return -EINVAL;
2189         }
2190
2191         //TODO Priority
2192         //nfilter->priority = (uint8_t)filter->priority;
2193
2194         bfilter->enables = en;
2195         return 0;
2196 }
2197
2198 static struct bnxt_filter_info*
2199 bnxt_match_ntuple_filter(struct bnxt *bp,
2200                          struct bnxt_filter_info *bfilter,
2201                          struct bnxt_vnic_info **mvnic)
2202 {
2203         struct bnxt_filter_info *mfilter = NULL;
2204         int i;
2205
2206         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2207                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2208                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2209                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2210                             bfilter->src_ipaddr_mask[0] ==
2211                             mfilter->src_ipaddr_mask[0] &&
2212                             bfilter->src_port == mfilter->src_port &&
2213                             bfilter->src_port_mask == mfilter->src_port_mask &&
2214                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2215                             bfilter->dst_ipaddr_mask[0] ==
2216                             mfilter->dst_ipaddr_mask[0] &&
2217                             bfilter->dst_port == mfilter->dst_port &&
2218                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2219                             bfilter->flags == mfilter->flags &&
2220                             bfilter->enables == mfilter->enables) {
2221                                 if (mvnic)
2222                                         *mvnic = vnic;
2223                                 return mfilter;
2224                         }
2225                 }
2226         }
2227         return NULL;
2228 }
2229
2230 static int
2231 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2232                        struct rte_eth_ntuple_filter *nfilter,
2233                        enum rte_filter_op filter_op)
2234 {
2235         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2236         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2237         int ret;
2238
2239         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2240                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2241                 return -EINVAL;
2242         }
2243
2244         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2245                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2246                 return -EINVAL;
2247         }
2248
2249         bfilter = bnxt_get_unused_filter(bp);
2250         if (bfilter == NULL) {
2251                 PMD_DRV_LOG(ERR,
2252                         "Not enough resources for a new filter.\n");
2253                 return -ENOMEM;
2254         }
2255         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2256         if (ret < 0)
2257                 goto free_filter;
2258
2259         vnic = &bp->vnic_info[nfilter->queue];
2260         vnic0 = &bp->vnic_info[0];
2261         filter1 = STAILQ_FIRST(&vnic0->filter);
2262         if (filter1 == NULL) {
2263                 ret = -1;
2264                 goto free_filter;
2265         }
2266
2267         bfilter->dst_id = vnic->fw_vnic_id;
2268         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2269         bfilter->enables |=
2270                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2271         bfilter->ethertype = 0x800;
2272         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2273
2274         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2275
2276         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2277             bfilter->dst_id == mfilter->dst_id) {
2278                 PMD_DRV_LOG(ERR, "filter exists.\n");
2279                 ret = -EEXIST;
2280                 goto free_filter;
2281         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2282                    bfilter->dst_id != mfilter->dst_id) {
2283                 mfilter->dst_id = vnic->fw_vnic_id;
2284                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2285                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2286                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2287                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2288                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2289                 goto free_filter;
2290         }
2291         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2292                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2293                 ret = -ENOENT;
2294                 goto free_filter;
2295         }
2296
2297         if (filter_op == RTE_ETH_FILTER_ADD) {
2298                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2299                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2300                 if (ret)
2301                         goto free_filter;
2302                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2303         } else {
2304                 if (mfilter == NULL) {
2305                         /* This should not happen. But for Coverity! */
2306                         ret = -ENOENT;
2307                         goto free_filter;
2308                 }
2309                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2310
2311                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2312                 bnxt_free_filter(bp, mfilter);
2313                 mfilter->fw_l2_filter_id = -1;
2314                 bnxt_free_filter(bp, bfilter);
2315                 bfilter->fw_l2_filter_id = -1;
2316         }
2317
2318         return 0;
2319 free_filter:
2320         bfilter->fw_l2_filter_id = -1;
2321         bnxt_free_filter(bp, bfilter);
2322         return ret;
2323 }
2324
2325 static int
2326 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2327                         enum rte_filter_op filter_op,
2328                         void *arg)
2329 {
2330         struct bnxt *bp = dev->data->dev_private;
2331         int ret;
2332
2333         if (filter_op == RTE_ETH_FILTER_NOP)
2334                 return 0;
2335
2336         if (arg == NULL) {
2337                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2338                             filter_op);
2339                 return -EINVAL;
2340         }
2341
2342         switch (filter_op) {
2343         case RTE_ETH_FILTER_ADD:
2344                 ret = bnxt_cfg_ntuple_filter(bp,
2345                         (struct rte_eth_ntuple_filter *)arg,
2346                         filter_op);
2347                 break;
2348         case RTE_ETH_FILTER_DELETE:
2349                 ret = bnxt_cfg_ntuple_filter(bp,
2350                         (struct rte_eth_ntuple_filter *)arg,
2351                         filter_op);
2352                 break;
2353         default:
2354                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2355                 ret = -EINVAL;
2356                 break;
2357         }
2358         return ret;
2359 }
2360
2361 static int
2362 bnxt_parse_fdir_filter(struct bnxt *bp,
2363                        struct rte_eth_fdir_filter *fdir,
2364                        struct bnxt_filter_info *filter)
2365 {
2366         enum rte_fdir_mode fdir_mode =
2367                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2368         struct bnxt_vnic_info *vnic0, *vnic;
2369         struct bnxt_filter_info *filter1;
2370         uint32_t en = 0;
2371         int i;
2372
2373         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2374                 return -EINVAL;
2375
2376         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2377         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2378
2379         switch (fdir->input.flow_type) {
2380         case RTE_ETH_FLOW_IPV4:
2381         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2382                 /* FALLTHROUGH */
2383                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2384                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2385                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2386                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2387                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2388                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2389                 filter->ip_addr_type =
2390                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2391                 filter->src_ipaddr_mask[0] = 0xffffffff;
2392                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2393                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2394                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2395                 filter->ethertype = 0x800;
2396                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2397                 break;
2398         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2399                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2400                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2401                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2402                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2403                 filter->dst_port_mask = 0xffff;
2404                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2405                 filter->src_port_mask = 0xffff;
2406                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2407                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2408                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2409                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2410                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2411                 filter->ip_protocol = 6;
2412                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2413                 filter->ip_addr_type =
2414                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2415                 filter->src_ipaddr_mask[0] = 0xffffffff;
2416                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2417                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2418                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2419                 filter->ethertype = 0x800;
2420                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2421                 break;
2422         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2423                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2424                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2425                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2426                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2427                 filter->dst_port_mask = 0xffff;
2428                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2429                 filter->src_port_mask = 0xffff;
2430                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2431                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2432                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2433                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2434                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2435                 filter->ip_protocol = 17;
2436                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2437                 filter->ip_addr_type =
2438                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2439                 filter->src_ipaddr_mask[0] = 0xffffffff;
2440                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2441                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2442                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2443                 filter->ethertype = 0x800;
2444                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2445                 break;
2446         case RTE_ETH_FLOW_IPV6:
2447         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2448                 /* FALLTHROUGH */
2449                 filter->ip_addr_type =
2450                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2451                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2452                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2453                 rte_memcpy(filter->src_ipaddr,
2454                            fdir->input.flow.ipv6_flow.src_ip, 16);
2455                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2456                 rte_memcpy(filter->dst_ipaddr,
2457                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2458                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2459                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2460                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2461                 memset(filter->src_ipaddr_mask, 0xff, 16);
2462                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2463                 filter->ethertype = 0x86dd;
2464                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2465                 break;
2466         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2467                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2468                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2469                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2470                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2471                 filter->dst_port_mask = 0xffff;
2472                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2473                 filter->src_port_mask = 0xffff;
2474                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2475                 filter->ip_addr_type =
2476                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2477                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2478                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2479                 rte_memcpy(filter->src_ipaddr,
2480                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2481                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2482                 rte_memcpy(filter->dst_ipaddr,
2483                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2484                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2485                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2486                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2487                 memset(filter->src_ipaddr_mask, 0xff, 16);
2488                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2489                 filter->ethertype = 0x86dd;
2490                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2491                 break;
2492         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2493                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2494                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2495                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2496                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2497                 filter->dst_port_mask = 0xffff;
2498                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2499                 filter->src_port_mask = 0xffff;
2500                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2501                 filter->ip_addr_type =
2502                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2503                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2504                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2505                 rte_memcpy(filter->src_ipaddr,
2506                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2507                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2508                 rte_memcpy(filter->dst_ipaddr,
2509                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2510                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2511                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2512                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2513                 memset(filter->src_ipaddr_mask, 0xff, 16);
2514                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2515                 filter->ethertype = 0x86dd;
2516                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2517                 break;
2518         case RTE_ETH_FLOW_L2_PAYLOAD:
2519                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2520                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2521                 break;
2522         case RTE_ETH_FLOW_VXLAN:
2523                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2524                         return -EINVAL;
2525                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2526                 filter->tunnel_type =
2527                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2528                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2529                 break;
2530         case RTE_ETH_FLOW_NVGRE:
2531                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2532                         return -EINVAL;
2533                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2534                 filter->tunnel_type =
2535                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2536                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2537                 break;
2538         case RTE_ETH_FLOW_UNKNOWN:
2539         case RTE_ETH_FLOW_RAW:
2540         case RTE_ETH_FLOW_FRAG_IPV4:
2541         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2542         case RTE_ETH_FLOW_FRAG_IPV6:
2543         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2544         case RTE_ETH_FLOW_IPV6_EX:
2545         case RTE_ETH_FLOW_IPV6_TCP_EX:
2546         case RTE_ETH_FLOW_IPV6_UDP_EX:
2547         case RTE_ETH_FLOW_GENEVE:
2548                 /* FALLTHROUGH */
2549         default:
2550                 return -EINVAL;
2551         }
2552
2553         vnic0 = &bp->vnic_info[0];
2554         vnic = &bp->vnic_info[fdir->action.rx_queue];
2555         if (vnic == NULL) {
2556                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2557                 return -EINVAL;
2558         }
2559
2560
2561         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2562                 rte_memcpy(filter->dst_macaddr,
2563                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2564                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2565         }
2566
2567         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2568                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2569                 filter1 = STAILQ_FIRST(&vnic0->filter);
2570                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2571         } else {
2572                 filter->dst_id = vnic->fw_vnic_id;
2573                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2574                         if (filter->dst_macaddr[i] == 0x00)
2575                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2576                         else
2577                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2578         }
2579
2580         if (filter1 == NULL)
2581                 return -EINVAL;
2582
2583         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2584         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2585
2586         filter->enables = en;
2587
2588         return 0;
2589 }
2590
2591 static struct bnxt_filter_info *
2592 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2593                 struct bnxt_vnic_info **mvnic)
2594 {
2595         struct bnxt_filter_info *mf = NULL;
2596         int i;
2597
2598         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2599                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2600
2601                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2602                         if (mf->filter_type == nf->filter_type &&
2603                             mf->flags == nf->flags &&
2604                             mf->src_port == nf->src_port &&
2605                             mf->src_port_mask == nf->src_port_mask &&
2606                             mf->dst_port == nf->dst_port &&
2607                             mf->dst_port_mask == nf->dst_port_mask &&
2608                             mf->ip_protocol == nf->ip_protocol &&
2609                             mf->ip_addr_type == nf->ip_addr_type &&
2610                             mf->ethertype == nf->ethertype &&
2611                             mf->vni == nf->vni &&
2612                             mf->tunnel_type == nf->tunnel_type &&
2613                             mf->l2_ovlan == nf->l2_ovlan &&
2614                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2615                             mf->l2_ivlan == nf->l2_ivlan &&
2616                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2617                             !memcmp(mf->l2_addr, nf->l2_addr,
2618                                     RTE_ETHER_ADDR_LEN) &&
2619                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2620                                     RTE_ETHER_ADDR_LEN) &&
2621                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2622                                     RTE_ETHER_ADDR_LEN) &&
2623                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2624                                     RTE_ETHER_ADDR_LEN) &&
2625                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2626                                     sizeof(nf->src_ipaddr)) &&
2627                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2628                                     sizeof(nf->src_ipaddr_mask)) &&
2629                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2630                                     sizeof(nf->dst_ipaddr)) &&
2631                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2632                                     sizeof(nf->dst_ipaddr_mask))) {
2633                                 if (mvnic)
2634                                         *mvnic = vnic;
2635                                 return mf;
2636                         }
2637                 }
2638         }
2639         return NULL;
2640 }
2641
2642 static int
2643 bnxt_fdir_filter(struct rte_eth_dev *dev,
2644                  enum rte_filter_op filter_op,
2645                  void *arg)
2646 {
2647         struct bnxt *bp = dev->data->dev_private;
2648         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2649         struct bnxt_filter_info *filter, *match;
2650         struct bnxt_vnic_info *vnic, *mvnic;
2651         int ret = 0, i;
2652
2653         if (filter_op == RTE_ETH_FILTER_NOP)
2654                 return 0;
2655
2656         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2657                 return -EINVAL;
2658
2659         switch (filter_op) {
2660         case RTE_ETH_FILTER_ADD:
2661         case RTE_ETH_FILTER_DELETE:
2662                 /* FALLTHROUGH */
2663                 filter = bnxt_get_unused_filter(bp);
2664                 if (filter == NULL) {
2665                         PMD_DRV_LOG(ERR,
2666                                 "Not enough resources for a new flow.\n");
2667                         return -ENOMEM;
2668                 }
2669
2670                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2671                 if (ret != 0)
2672                         goto free_filter;
2673                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2674
2675                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2676                         vnic = &bp->vnic_info[0];
2677                 else
2678                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2679
2680                 match = bnxt_match_fdir(bp, filter, &mvnic);
2681                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2682                         if (match->dst_id == vnic->fw_vnic_id) {
2683                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2684                                 ret = -EEXIST;
2685                                 goto free_filter;
2686                         } else {
2687                                 match->dst_id = vnic->fw_vnic_id;
2688                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2689                                                                   match->dst_id,
2690                                                                   match);
2691                                 STAILQ_REMOVE(&mvnic->filter, match,
2692                                               bnxt_filter_info, next);
2693                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2694                                 PMD_DRV_LOG(ERR,
2695                                         "Filter with matching pattern exist\n");
2696                                 PMD_DRV_LOG(ERR,
2697                                         "Updated it to new destination q\n");
2698                                 goto free_filter;
2699                         }
2700                 }
2701                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2702                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2703                         ret = -ENOENT;
2704                         goto free_filter;
2705                 }
2706
2707                 if (filter_op == RTE_ETH_FILTER_ADD) {
2708                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2709                                                           filter->dst_id,
2710                                                           filter);
2711                         if (ret)
2712                                 goto free_filter;
2713                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2714                 } else {
2715                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2716                         STAILQ_REMOVE(&vnic->filter, match,
2717                                       bnxt_filter_info, next);
2718                         bnxt_free_filter(bp, match);
2719                         filter->fw_l2_filter_id = -1;
2720                         bnxt_free_filter(bp, filter);
2721                 }
2722                 break;
2723         case RTE_ETH_FILTER_FLUSH:
2724                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2725                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2726
2727                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2728                                 if (filter->filter_type ==
2729                                     HWRM_CFA_NTUPLE_FILTER) {
2730                                         ret =
2731                                         bnxt_hwrm_clear_ntuple_filter(bp,
2732                                                                       filter);
2733                                         STAILQ_REMOVE(&vnic->filter, filter,
2734                                                       bnxt_filter_info, next);
2735                                 }
2736                         }
2737                 }
2738                 return ret;
2739         case RTE_ETH_FILTER_UPDATE:
2740         case RTE_ETH_FILTER_STATS:
2741         case RTE_ETH_FILTER_INFO:
2742                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2743                 break;
2744         default:
2745                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2746                 ret = -EINVAL;
2747                 break;
2748         }
2749         return ret;
2750
2751 free_filter:
2752         filter->fw_l2_filter_id = -1;
2753         bnxt_free_filter(bp, filter);
2754         return ret;
2755 }
2756
2757 static int
2758 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2759                     enum rte_filter_type filter_type,
2760                     enum rte_filter_op filter_op, void *arg)
2761 {
2762         int ret = 0;
2763
2764         switch (filter_type) {
2765         case RTE_ETH_FILTER_TUNNEL:
2766                 PMD_DRV_LOG(ERR,
2767                         "filter type: %d: To be implemented\n", filter_type);
2768                 break;
2769         case RTE_ETH_FILTER_FDIR:
2770                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2771                 break;
2772         case RTE_ETH_FILTER_NTUPLE:
2773                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2774                 break;
2775         case RTE_ETH_FILTER_ETHERTYPE:
2776                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2777                 break;
2778         case RTE_ETH_FILTER_GENERIC:
2779                 if (filter_op != RTE_ETH_FILTER_GET)
2780                         return -EINVAL;
2781                 *(const void **)arg = &bnxt_flow_ops;
2782                 break;
2783         default:
2784                 PMD_DRV_LOG(ERR,
2785                         "Filter type (%d) not supported", filter_type);
2786                 ret = -EINVAL;
2787                 break;
2788         }
2789         return ret;
2790 }
2791
2792 static const uint32_t *
2793 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2794 {
2795         static const uint32_t ptypes[] = {
2796                 RTE_PTYPE_L2_ETHER_VLAN,
2797                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2798                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2799                 RTE_PTYPE_L4_ICMP,
2800                 RTE_PTYPE_L4_TCP,
2801                 RTE_PTYPE_L4_UDP,
2802                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2803                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2804                 RTE_PTYPE_INNER_L4_ICMP,
2805                 RTE_PTYPE_INNER_L4_TCP,
2806                 RTE_PTYPE_INNER_L4_UDP,
2807                 RTE_PTYPE_UNKNOWN
2808         };
2809
2810         if (!dev->rx_pkt_burst)
2811                 return NULL;
2812
2813         return ptypes;
2814 }
2815
2816 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2817                          int reg_win)
2818 {
2819         uint32_t reg_base = *reg_arr & 0xfffff000;
2820         uint32_t win_off;
2821         int i;
2822
2823         for (i = 0; i < count; i++) {
2824                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2825                         return -ERANGE;
2826         }
2827         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2828         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2829         return 0;
2830 }
2831
2832 static int bnxt_map_ptp_regs(struct bnxt *bp)
2833 {
2834         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2835         uint32_t *reg_arr;
2836         int rc, i;
2837
2838         reg_arr = ptp->rx_regs;
2839         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2840         if (rc)
2841                 return rc;
2842
2843         reg_arr = ptp->tx_regs;
2844         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2845         if (rc)
2846                 return rc;
2847
2848         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2849                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2850
2851         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2852                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2853
2854         return 0;
2855 }
2856
2857 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2858 {
2859         rte_write32(0, (uint8_t *)bp->bar0 +
2860                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2861         rte_write32(0, (uint8_t *)bp->bar0 +
2862                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2863 }
2864
2865 static uint64_t bnxt_cc_read(struct bnxt *bp)
2866 {
2867         uint64_t ns;
2868
2869         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2870                               BNXT_GRCPF_REG_SYNC_TIME));
2871         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2872                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2873         return ns;
2874 }
2875
2876 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2877 {
2878         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2879         uint32_t fifo;
2880
2881         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2882                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2883         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2884                 return -EAGAIN;
2885
2886         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2887                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2888         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2889                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2890         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2891                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2892
2893         return 0;
2894 }
2895
2896 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2897 {
2898         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2899         struct bnxt_pf_info *pf = &bp->pf;
2900         uint16_t port_id;
2901         uint32_t fifo;
2902
2903         if (!ptp)
2904                 return -ENODEV;
2905
2906         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2907                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2908         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2909                 return -EAGAIN;
2910
2911         port_id = pf->port_id;
2912         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2913                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2914
2915         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2916                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2917         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2918 /*              bnxt_clr_rx_ts(bp);       TBD  */
2919                 return -EBUSY;
2920         }
2921
2922         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2923                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2924         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2925                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2926
2927         return 0;
2928 }
2929
2930 static int
2931 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2932 {
2933         uint64_t ns;
2934         struct bnxt *bp = dev->data->dev_private;
2935         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2936
2937         if (!ptp)
2938                 return 0;
2939
2940         ns = rte_timespec_to_ns(ts);
2941         /* Set the timecounters to a new value. */
2942         ptp->tc.nsec = ns;
2943
2944         return 0;
2945 }
2946
2947 static int
2948 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2949 {
2950         uint64_t ns, systime_cycles;
2951         struct bnxt *bp = dev->data->dev_private;
2952         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2953
2954         if (!ptp)
2955                 return 0;
2956
2957         systime_cycles = bnxt_cc_read(bp);
2958         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2959         *ts = rte_ns_to_timespec(ns);
2960
2961         return 0;
2962 }
2963 static int
2964 bnxt_timesync_enable(struct rte_eth_dev *dev)
2965 {
2966         struct bnxt *bp = dev->data->dev_private;
2967         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2968         uint32_t shift = 0;
2969
2970         if (!ptp)
2971                 return 0;
2972
2973         ptp->rx_filter = 1;
2974         ptp->tx_tstamp_en = 1;
2975         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2976
2977         if (!bnxt_hwrm_ptp_cfg(bp))
2978                 bnxt_map_ptp_regs(bp);
2979
2980         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2981         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2982         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2983
2984         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2985         ptp->tc.cc_shift = shift;
2986         ptp->tc.nsec_mask = (1ULL << shift) - 1;
2987
2988         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2989         ptp->rx_tstamp_tc.cc_shift = shift;
2990         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2991
2992         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2993         ptp->tx_tstamp_tc.cc_shift = shift;
2994         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2995
2996         return 0;
2997 }
2998
2999 static int
3000 bnxt_timesync_disable(struct rte_eth_dev *dev)
3001 {
3002         struct bnxt *bp = dev->data->dev_private;
3003         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3004
3005         if (!ptp)
3006                 return 0;
3007
3008         ptp->rx_filter = 0;
3009         ptp->tx_tstamp_en = 0;
3010         ptp->rxctl = 0;
3011
3012         bnxt_hwrm_ptp_cfg(bp);
3013
3014         bnxt_unmap_ptp_regs(bp);
3015
3016         return 0;
3017 }
3018
3019 static int
3020 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3021                                  struct timespec *timestamp,
3022                                  uint32_t flags __rte_unused)
3023 {
3024         struct bnxt *bp = dev->data->dev_private;
3025         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3026         uint64_t rx_tstamp_cycles = 0;
3027         uint64_t ns;
3028
3029         if (!ptp)
3030                 return 0;
3031
3032         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3033         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3034         *timestamp = rte_ns_to_timespec(ns);
3035         return  0;
3036 }
3037
3038 static int
3039 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3040                                  struct timespec *timestamp)
3041 {
3042         struct bnxt *bp = dev->data->dev_private;
3043         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3044         uint64_t tx_tstamp_cycles = 0;
3045         uint64_t ns;
3046
3047         if (!ptp)
3048                 return 0;
3049
3050         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3051         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3052         *timestamp = rte_ns_to_timespec(ns);
3053
3054         return 0;
3055 }
3056
3057 static int
3058 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3059 {
3060         struct bnxt *bp = dev->data->dev_private;
3061         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3062
3063         if (!ptp)
3064                 return 0;
3065
3066         ptp->tc.nsec += delta;
3067
3068         return 0;
3069 }
3070
3071 static int
3072 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3073 {
3074         struct bnxt *bp = dev->data->dev_private;
3075         int rc;
3076         uint32_t dir_entries;
3077         uint32_t entry_length;
3078
3079         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3080                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3081                 bp->pdev->addr.devid, bp->pdev->addr.function);
3082
3083         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3084         if (rc != 0)
3085                 return rc;
3086
3087         return dir_entries * entry_length;
3088 }
3089
3090 static int
3091 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3092                 struct rte_dev_eeprom_info *in_eeprom)
3093 {
3094         struct bnxt *bp = dev->data->dev_private;
3095         uint32_t index;
3096         uint32_t offset;
3097
3098         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3099                 "len = %d\n", bp->pdev->addr.domain,
3100                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3101                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3102
3103         if (in_eeprom->offset == 0) /* special offset value to get directory */
3104                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3105                                                 in_eeprom->data);
3106
3107         index = in_eeprom->offset >> 24;
3108         offset = in_eeprom->offset & 0xffffff;
3109
3110         if (index != 0)
3111                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3112                                            in_eeprom->length, in_eeprom->data);
3113
3114         return 0;
3115 }
3116
3117 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3118 {
3119         switch (dir_type) {
3120         case BNX_DIR_TYPE_CHIMP_PATCH:
3121         case BNX_DIR_TYPE_BOOTCODE:
3122         case BNX_DIR_TYPE_BOOTCODE_2:
3123         case BNX_DIR_TYPE_APE_FW:
3124         case BNX_DIR_TYPE_APE_PATCH:
3125         case BNX_DIR_TYPE_KONG_FW:
3126         case BNX_DIR_TYPE_KONG_PATCH:
3127         case BNX_DIR_TYPE_BONO_FW:
3128         case BNX_DIR_TYPE_BONO_PATCH:
3129                 /* FALLTHROUGH */
3130                 return true;
3131         }
3132
3133         return false;
3134 }
3135
3136 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3137 {
3138         switch (dir_type) {
3139         case BNX_DIR_TYPE_AVS:
3140         case BNX_DIR_TYPE_EXP_ROM_MBA:
3141         case BNX_DIR_TYPE_PCIE:
3142         case BNX_DIR_TYPE_TSCF_UCODE:
3143         case BNX_DIR_TYPE_EXT_PHY:
3144         case BNX_DIR_TYPE_CCM:
3145         case BNX_DIR_TYPE_ISCSI_BOOT:
3146         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3147         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3148                 /* FALLTHROUGH */
3149                 return true;
3150         }
3151
3152         return false;
3153 }
3154
3155 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3156 {
3157         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3158                 bnxt_dir_type_is_other_exec_format(dir_type);
3159 }
3160
3161 static int
3162 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3163                 struct rte_dev_eeprom_info *in_eeprom)
3164 {
3165         struct bnxt *bp = dev->data->dev_private;
3166         uint8_t index, dir_op;
3167         uint16_t type, ext, ordinal, attr;
3168
3169         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3170                 "len = %d\n", bp->pdev->addr.domain,
3171                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3172                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3173
3174         if (!BNXT_PF(bp)) {
3175                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3176                 return -EINVAL;
3177         }
3178
3179         type = in_eeprom->magic >> 16;
3180
3181         if (type == 0xffff) { /* special value for directory operations */
3182                 index = in_eeprom->magic & 0xff;
3183                 dir_op = in_eeprom->magic >> 8;
3184                 if (index == 0)
3185                         return -EINVAL;
3186                 switch (dir_op) {
3187                 case 0x0e: /* erase */
3188                         if (in_eeprom->offset != ~in_eeprom->magic)
3189                                 return -EINVAL;
3190                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3191                 default:
3192                         return -EINVAL;
3193                 }
3194         }
3195
3196         /* Create or re-write an NVM item: */
3197         if (bnxt_dir_type_is_executable(type) == true)
3198                 return -EOPNOTSUPP;
3199         ext = in_eeprom->magic & 0xffff;
3200         ordinal = in_eeprom->offset >> 16;
3201         attr = in_eeprom->offset & 0xffff;
3202
3203         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3204                                      in_eeprom->data, in_eeprom->length);
3205         return 0;
3206 }
3207
3208 /*
3209  * Initialization
3210  */
3211
3212 static const struct eth_dev_ops bnxt_dev_ops = {
3213         .dev_infos_get = bnxt_dev_info_get_op,
3214         .dev_close = bnxt_dev_close_op,
3215         .dev_configure = bnxt_dev_configure_op,
3216         .dev_start = bnxt_dev_start_op,
3217         .dev_stop = bnxt_dev_stop_op,
3218         .dev_set_link_up = bnxt_dev_set_link_up_op,
3219         .dev_set_link_down = bnxt_dev_set_link_down_op,
3220         .stats_get = bnxt_stats_get_op,
3221         .stats_reset = bnxt_stats_reset_op,
3222         .rx_queue_setup = bnxt_rx_queue_setup_op,
3223         .rx_queue_release = bnxt_rx_queue_release_op,
3224         .tx_queue_setup = bnxt_tx_queue_setup_op,
3225         .tx_queue_release = bnxt_tx_queue_release_op,
3226         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3227         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3228         .reta_update = bnxt_reta_update_op,
3229         .reta_query = bnxt_reta_query_op,
3230         .rss_hash_update = bnxt_rss_hash_update_op,
3231         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3232         .link_update = bnxt_link_update_op,
3233         .promiscuous_enable = bnxt_promiscuous_enable_op,
3234         .promiscuous_disable = bnxt_promiscuous_disable_op,
3235         .allmulticast_enable = bnxt_allmulticast_enable_op,
3236         .allmulticast_disable = bnxt_allmulticast_disable_op,
3237         .mac_addr_add = bnxt_mac_addr_add_op,
3238         .mac_addr_remove = bnxt_mac_addr_remove_op,
3239         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3240         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3241         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3242         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3243         .vlan_filter_set = bnxt_vlan_filter_set_op,
3244         .vlan_offload_set = bnxt_vlan_offload_set_op,
3245         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3246         .mtu_set = bnxt_mtu_set_op,
3247         .mac_addr_set = bnxt_set_default_mac_addr_op,
3248         .xstats_get = bnxt_dev_xstats_get_op,
3249         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3250         .xstats_reset = bnxt_dev_xstats_reset_op,
3251         .fw_version_get = bnxt_fw_version_get,
3252         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3253         .rxq_info_get = bnxt_rxq_info_get_op,
3254         .txq_info_get = bnxt_txq_info_get_op,
3255         .dev_led_on = bnxt_dev_led_on_op,
3256         .dev_led_off = bnxt_dev_led_off_op,
3257         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3258         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3259         .rx_queue_count = bnxt_rx_queue_count_op,
3260         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3261         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3262         .rx_queue_start = bnxt_rx_queue_start,
3263         .rx_queue_stop = bnxt_rx_queue_stop,
3264         .tx_queue_start = bnxt_tx_queue_start,
3265         .tx_queue_stop = bnxt_tx_queue_stop,
3266         .filter_ctrl = bnxt_filter_ctrl_op,
3267         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3268         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3269         .get_eeprom           = bnxt_get_eeprom_op,
3270         .set_eeprom           = bnxt_set_eeprom_op,
3271         .timesync_enable      = bnxt_timesync_enable,
3272         .timesync_disable     = bnxt_timesync_disable,
3273         .timesync_read_time   = bnxt_timesync_read_time,
3274         .timesync_write_time   = bnxt_timesync_write_time,
3275         .timesync_adjust_time = bnxt_timesync_adjust_time,
3276         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3277         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3278 };
3279
3280 static bool bnxt_vf_pciid(uint16_t id)
3281 {
3282         if (id == BROADCOM_DEV_ID_57304_VF ||
3283             id == BROADCOM_DEV_ID_57406_VF ||
3284             id == BROADCOM_DEV_ID_5731X_VF ||
3285             id == BROADCOM_DEV_ID_5741X_VF ||
3286             id == BROADCOM_DEV_ID_57414_VF ||
3287             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3288             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3289             id == BROADCOM_DEV_ID_58802_VF ||
3290             id == BROADCOM_DEV_ID_57500_VF)
3291                 return true;
3292         return false;
3293 }
3294
3295 bool bnxt_stratus_device(struct bnxt *bp)
3296 {
3297         uint16_t id = bp->pdev->id.device_id;
3298
3299         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3300             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3301             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3302                 return true;
3303         return false;
3304 }
3305
3306 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3307 {
3308         struct bnxt *bp = eth_dev->data->dev_private;
3309         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3310         int rc;
3311
3312         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3313         if (!pci_dev->mem_resource[0].addr) {
3314                 PMD_DRV_LOG(ERR,
3315                         "Cannot find PCI device base address, aborting\n");
3316                 rc = -ENODEV;
3317                 goto init_err_disable;
3318         }
3319
3320         bp->eth_dev = eth_dev;
3321         bp->pdev = pci_dev;
3322
3323         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3324         if (!bp->bar0) {
3325                 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3326                 rc = -ENOMEM;
3327                 goto init_err_release;
3328         }
3329
3330         if (!pci_dev->mem_resource[2].addr) {
3331                 PMD_DRV_LOG(ERR,
3332                             "Cannot find PCI device BAR 2 address, aborting\n");
3333                 rc = -ENODEV;
3334                 goto init_err_release;
3335         } else {
3336                 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3337         }
3338
3339         return 0;
3340
3341 init_err_release:
3342         if (bp->bar0)
3343                 bp->bar0 = NULL;
3344         if (bp->doorbell_base)
3345                 bp->doorbell_base = NULL;
3346
3347 init_err_disable:
3348
3349         return rc;
3350 }
3351
3352 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3353                                   struct bnxt_ctx_pg_info *ctx_pg,
3354                                   uint32_t mem_size,
3355                                   const char *suffix,
3356                                   uint16_t idx)
3357 {
3358         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3359         const struct rte_memzone *mz = NULL;
3360         char mz_name[RTE_MEMZONE_NAMESIZE];
3361         rte_iova_t mz_phys_addr;
3362         uint64_t valid_bits = 0;
3363         uint32_t sz;
3364         int i;
3365
3366         if (!mem_size)
3367                 return 0;
3368
3369         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3370                          BNXT_PAGE_SIZE;
3371         rmem->page_size = BNXT_PAGE_SIZE;
3372         rmem->pg_arr = ctx_pg->ctx_pg_arr;
3373         rmem->dma_arr = ctx_pg->ctx_dma_arr;
3374         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3375
3376         valid_bits = PTU_PTE_VALID;
3377
3378         if (rmem->nr_pages > 1) {
3379                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_pg_tbl%s_%x",
3380                          suffix, idx);
3381                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3382                 mz = rte_memzone_lookup(mz_name);
3383                 if (!mz) {
3384                         mz = rte_memzone_reserve_aligned(mz_name,
3385                                                 rmem->nr_pages * 8,
3386                                                 SOCKET_ID_ANY,
3387                                                 RTE_MEMZONE_2MB |
3388                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
3389                                                 RTE_MEMZONE_IOVA_CONTIG,
3390                                                 BNXT_PAGE_SIZE);
3391                         if (mz == NULL)
3392                                 return -ENOMEM;
3393                 }
3394
3395                 memset(mz->addr, 0, mz->len);
3396                 mz_phys_addr = mz->iova;
3397                 if ((unsigned long)mz->addr == mz_phys_addr) {
3398                         PMD_DRV_LOG(WARNING,
3399                                 "Memzone physical address same as virtual.\n");
3400                         PMD_DRV_LOG(WARNING,
3401                                     "Using rte_mem_virt2iova()\n");
3402                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3403                         if (mz_phys_addr == 0) {
3404                                 PMD_DRV_LOG(ERR,
3405                                         "unable to map addr to phys memory\n");
3406                                 return -ENOMEM;
3407                         }
3408                 }
3409                 rte_mem_lock_page(((char *)mz->addr));
3410
3411                 rmem->pg_tbl = mz->addr;
3412                 rmem->pg_tbl_map = mz_phys_addr;
3413                 rmem->pg_tbl_mz = mz;
3414         }
3415
3416         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x", suffix, idx);
3417         mz = rte_memzone_lookup(mz_name);
3418         if (!mz) {
3419                 mz = rte_memzone_reserve_aligned(mz_name,
3420                                                  mem_size,
3421                                                  SOCKET_ID_ANY,
3422                                                  RTE_MEMZONE_1GB |
3423                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
3424                                                  RTE_MEMZONE_IOVA_CONTIG,
3425                                                  BNXT_PAGE_SIZE);
3426                 if (mz == NULL)
3427                         return -ENOMEM;
3428         }
3429
3430         memset(mz->addr, 0, mz->len);
3431         mz_phys_addr = mz->iova;
3432         if ((unsigned long)mz->addr == mz_phys_addr) {
3433                 PMD_DRV_LOG(WARNING,
3434                             "Memzone physical address same as virtual.\n");
3435                 PMD_DRV_LOG(WARNING,
3436                             "Using rte_mem_virt2iova()\n");
3437                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3438                         rte_mem_lock_page(((char *)mz->addr) + sz);
3439                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3440                 if (mz_phys_addr == RTE_BAD_IOVA) {
3441                         PMD_DRV_LOG(ERR,
3442                                     "unable to map addr to phys memory\n");
3443                         return -ENOMEM;
3444                 }
3445         }
3446
3447         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3448                 rte_mem_lock_page(((char *)mz->addr) + sz);
3449                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3450                 rmem->dma_arr[i] = mz_phys_addr + sz;
3451
3452                 if (rmem->nr_pages > 1) {
3453                         if (i == rmem->nr_pages - 2 &&
3454                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3455                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3456                         else if (i == rmem->nr_pages - 1 &&
3457                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3458                                 valid_bits |= PTU_PTE_LAST;
3459
3460                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3461                                                            valid_bits);
3462                 }
3463         }
3464
3465         rmem->mz = mz;
3466         if (rmem->vmem_size)
3467                 rmem->vmem = (void **)mz->addr;
3468         rmem->dma_arr[0] = mz_phys_addr;
3469         return 0;
3470 }
3471
3472 static void bnxt_free_ctx_mem(struct bnxt *bp)
3473 {
3474         int i;
3475
3476         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3477                 return;
3478
3479         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3480         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3481         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3482         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3483         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3484         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3485         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3486         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3487         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3488         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3489         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3490
3491         for (i = 0; i < BNXT_MAX_Q; i++) {
3492                 if (bp->ctx->tqm_mem[i])
3493                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3494         }
3495
3496         rte_free(bp->ctx);
3497         bp->ctx = NULL;
3498 }
3499
3500 #define roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
3501
3502 #define min_t(type, x, y) ({                    \
3503         type __min1 = (x);                      \
3504         type __min2 = (y);                      \
3505         __min1 < __min2 ? __min1 : __min2; })
3506
3507 #define max_t(type, x, y) ({                    \
3508         type __max1 = (x);                      \
3509         type __max2 = (y);                      \
3510         __max1 > __max2 ? __max1 : __max2; })
3511
3512 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
3513
3514 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3515 {
3516         struct bnxt_ctx_pg_info *ctx_pg;
3517         struct bnxt_ctx_mem_info *ctx;
3518         uint32_t mem_size, ena, entries;
3519         int i, rc;
3520
3521         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3522         if (rc) {
3523                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3524                 return rc;
3525         }
3526         ctx = bp->ctx;
3527         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3528                 return 0;
3529
3530         ctx_pg = &ctx->qp_mem;
3531         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3532         mem_size = ctx->qp_entry_size * ctx_pg->entries;
3533         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3534         if (rc)
3535                 return rc;
3536
3537         ctx_pg = &ctx->srq_mem;
3538         ctx_pg->entries = ctx->srq_max_l2_entries;
3539         mem_size = ctx->srq_entry_size * ctx_pg->entries;
3540         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3541         if (rc)
3542                 return rc;
3543
3544         ctx_pg = &ctx->cq_mem;
3545         ctx_pg->entries = ctx->cq_max_l2_entries;
3546         mem_size = ctx->cq_entry_size * ctx_pg->entries;
3547         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3548         if (rc)
3549                 return rc;
3550
3551         ctx_pg = &ctx->vnic_mem;
3552         ctx_pg->entries = ctx->vnic_max_vnic_entries +
3553                 ctx->vnic_max_ring_table_entries;
3554         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3555         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3556         if (rc)
3557                 return rc;
3558
3559         ctx_pg = &ctx->stat_mem;
3560         ctx_pg->entries = ctx->stat_max_entries;
3561         mem_size = ctx->stat_entry_size * ctx_pg->entries;
3562         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3563         if (rc)
3564                 return rc;
3565
3566         entries = ctx->qp_max_l2_entries;
3567         entries = roundup(entries, ctx->tqm_entries_multiple);
3568         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3569                           ctx->tqm_max_entries_per_ring);
3570         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3571                 ctx_pg = ctx->tqm_mem[i];
3572                 /* use min tqm entries for now. */
3573                 ctx_pg->entries = entries;
3574                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3575                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3576                 if (rc)
3577                         return rc;
3578                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3579         }
3580
3581         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3582         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3583         if (rc)
3584                 PMD_DRV_LOG(ERR,
3585                             "Failed to configure context mem: rc = %d\n", rc);
3586         else
3587                 ctx->flags |= BNXT_CTX_FLAG_INITED;
3588
3589         return 0;
3590 }
3591
3592 #define ALLOW_FUNC(x)   \
3593         { \
3594                 typeof(x) arg = (x); \
3595                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3596                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3597         }
3598 static int
3599 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3600 {
3601         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3602         char mz_name[RTE_MEMZONE_NAMESIZE];
3603         const struct rte_memzone *mz = NULL;
3604         static int version_printed;
3605         uint32_t total_alloc_len;
3606         rte_iova_t mz_phys_addr;
3607         struct bnxt *bp;
3608         int rc;
3609
3610         if (version_printed++ == 0)
3611                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3612
3613         rte_eth_copy_pci_info(eth_dev, pci_dev);
3614
3615         bp = eth_dev->data->dev_private;
3616
3617         bp->dev_stopped = 1;
3618
3619         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3620                 goto skip_init;
3621
3622         if (bnxt_vf_pciid(pci_dev->id.device_id))
3623                 bp->flags |= BNXT_FLAG_VF;
3624
3625         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
3626             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
3627             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
3628             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF)
3629                 bp->flags |= BNXT_FLAG_THOR_CHIP;
3630
3631         rc = bnxt_init_board(eth_dev);
3632         if (rc) {
3633                 PMD_DRV_LOG(ERR,
3634                         "Board initialization failed rc: %x\n", rc);
3635                 goto error;
3636         }
3637 skip_init:
3638         eth_dev->dev_ops = &bnxt_dev_ops;
3639         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3640         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3641         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3642                 return 0;
3643
3644         if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3645                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3646                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3647                          pci_dev->addr.bus, pci_dev->addr.devid,
3648                          pci_dev->addr.function, "rx_port_stats");
3649                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3650                 mz = rte_memzone_lookup(mz_name);
3651                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3652                                         sizeof(struct rx_port_stats) +
3653                                         sizeof(struct rx_port_stats_ext) +
3654                                         512);
3655                 if (!mz) {
3656                         mz = rte_memzone_reserve(mz_name, total_alloc_len,
3657                                         SOCKET_ID_ANY,
3658                                         RTE_MEMZONE_2MB |
3659                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3660                                         RTE_MEMZONE_IOVA_CONTIG);
3661                         if (mz == NULL)
3662                                 return -ENOMEM;
3663                 }
3664                 memset(mz->addr, 0, mz->len);
3665                 mz_phys_addr = mz->iova;
3666                 if ((unsigned long)mz->addr == mz_phys_addr) {
3667                         PMD_DRV_LOG(INFO,
3668                                 "Memzone physical address same as virtual using rte_mem_virt2iova()\n");
3669                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3670                         if (mz_phys_addr == 0) {
3671                                 PMD_DRV_LOG(ERR,
3672                                 "unable to map address to physical memory\n");
3673                                 return -ENOMEM;
3674                         }
3675                 }
3676
3677                 bp->rx_mem_zone = (const void *)mz;
3678                 bp->hw_rx_port_stats = mz->addr;
3679                 bp->hw_rx_port_stats_map = mz_phys_addr;
3680
3681                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3682                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3683                          pci_dev->addr.bus, pci_dev->addr.devid,
3684                          pci_dev->addr.function, "tx_port_stats");
3685                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3686                 mz = rte_memzone_lookup(mz_name);
3687                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3688                                         sizeof(struct tx_port_stats) +
3689                                         sizeof(struct tx_port_stats_ext) +
3690                                         512);
3691                 if (!mz) {
3692                         mz = rte_memzone_reserve(mz_name,
3693                                         total_alloc_len,
3694                                         SOCKET_ID_ANY,
3695                                         RTE_MEMZONE_2MB |
3696                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3697                                         RTE_MEMZONE_IOVA_CONTIG);
3698                         if (mz == NULL)
3699                                 return -ENOMEM;
3700                 }
3701                 memset(mz->addr, 0, mz->len);
3702                 mz_phys_addr = mz->iova;
3703                 if ((unsigned long)mz->addr == mz_phys_addr) {
3704                         PMD_DRV_LOG(WARNING,
3705                                 "Memzone physical address same as virtual.\n");
3706                         PMD_DRV_LOG(WARNING,
3707                                 "Using rte_mem_virt2iova()\n");
3708                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3709                         if (mz_phys_addr == 0) {
3710                                 PMD_DRV_LOG(ERR,
3711                                 "unable to map address to physical memory\n");
3712                                 return -ENOMEM;
3713                         }
3714                 }
3715
3716                 bp->tx_mem_zone = (const void *)mz;
3717                 bp->hw_tx_port_stats = mz->addr;
3718                 bp->hw_tx_port_stats_map = mz_phys_addr;
3719
3720                 bp->flags |= BNXT_FLAG_PORT_STATS;
3721
3722                 /* Display extended statistics if FW supports it */
3723                 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3724                     bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0)
3725                         goto skip_ext_stats;
3726
3727                 bp->hw_rx_port_stats_ext = (void *)
3728                         (bp->hw_rx_port_stats + sizeof(struct rx_port_stats));
3729                 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3730                         sizeof(struct rx_port_stats);
3731                 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3732
3733
3734                 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2) {
3735                         bp->hw_tx_port_stats_ext = (void *)
3736                         (bp->hw_tx_port_stats + sizeof(struct tx_port_stats));
3737                         bp->hw_tx_port_stats_ext_map =
3738                                 bp->hw_tx_port_stats_map +
3739                                 sizeof(struct tx_port_stats);
3740                         bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3741                 }
3742         }
3743
3744 skip_ext_stats:
3745         rc = bnxt_alloc_hwrm_resources(bp);
3746         if (rc) {
3747                 PMD_DRV_LOG(ERR,
3748                         "hwrm resource allocation failure rc: %x\n", rc);
3749                 goto error_free;
3750         }
3751         rc = bnxt_hwrm_ver_get(bp);
3752         if (rc)
3753                 goto error_free;
3754
3755         rc = bnxt_hwrm_func_reset(bp);
3756         if (rc) {
3757                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3758                 rc = -EIO;
3759                 goto error_free;
3760         }
3761
3762         rc = bnxt_hwrm_queue_qportcfg(bp);
3763         if (rc) {
3764                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3765                 goto error_free;
3766         }
3767         /* Get the MAX capabilities for this function */
3768         rc = bnxt_hwrm_func_qcaps(bp);
3769         if (rc) {
3770                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3771                 goto error_free;
3772         }
3773         if (bp->max_tx_rings == 0) {
3774                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3775                 rc = -EBUSY;
3776                 goto error_free;
3777         }
3778         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3779                                         RTE_ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3780         if (eth_dev->data->mac_addrs == NULL) {
3781                 PMD_DRV_LOG(ERR,
3782                         "Failed to alloc %u bytes needed to store MAC addr tbl",
3783                         RTE_ETHER_ADDR_LEN * bp->max_l2_ctx);
3784                 rc = -ENOMEM;
3785                 goto error_free;
3786         }
3787
3788         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3789                 PMD_DRV_LOG(ERR,
3790                             "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3791                             bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3792                             bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3793                             bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3794                 rc = -EINVAL;
3795                 goto error_free;
3796         }
3797         /* Copy the permanent MAC from the qcap response address now. */
3798         memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3799         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3800
3801         /* THOR does not support ring groups.
3802          * But we will use the array to save RSS context IDs.
3803          */
3804         if (BNXT_CHIP_THOR(bp)) {
3805                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
3806         } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3807                 /* 1 ring is for default completion ring */
3808                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3809                 rc = -ENOSPC;
3810                 goto error_free;
3811         }
3812
3813         bp->grp_info = rte_zmalloc("bnxt_grp_info",
3814                                 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3815         if (!bp->grp_info) {
3816                 PMD_DRV_LOG(ERR,
3817                         "Failed to alloc %zu bytes to store group info table\n",
3818                         sizeof(*bp->grp_info) * bp->max_ring_grps);
3819                 rc = -ENOMEM;
3820                 goto error_free;
3821         }
3822
3823         /* Forward all requests if firmware is new enough */
3824         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3825             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3826             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3827                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3828         } else {
3829                 PMD_DRV_LOG(WARNING,
3830                         "Firmware too old for VF mailbox functionality\n");
3831                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3832         }
3833
3834         /*
3835          * The following are used for driver cleanup.  If we disallow these,
3836          * VF drivers can't clean up cleanly.
3837          */
3838         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3839         ALLOW_FUNC(HWRM_VNIC_FREE);
3840         ALLOW_FUNC(HWRM_RING_FREE);
3841         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3842         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3843         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3844         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3845         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3846         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3847         rc = bnxt_hwrm_func_driver_register(bp);
3848         if (rc) {
3849                 PMD_DRV_LOG(ERR,
3850                         "Failed to register driver");
3851                 rc = -EBUSY;
3852                 goto error_free;
3853         }
3854
3855         PMD_DRV_LOG(INFO,
3856                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3857                 pci_dev->mem_resource[0].phys_addr,
3858                 pci_dev->mem_resource[0].addr);
3859
3860         rc = bnxt_hwrm_func_qcfg(bp);
3861         if (rc) {
3862                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3863                 goto error_free;
3864         }
3865
3866         if (BNXT_PF(bp)) {
3867                 //if (bp->pf.active_vfs) {
3868                         // TODO: Deallocate VF resources?
3869                 //}
3870                 if (bp->pdev->max_vfs) {
3871                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3872                         if (rc) {
3873                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3874                                 goto error_free;
3875                         }
3876                 } else {
3877                         rc = bnxt_hwrm_allocate_pf_only(bp);
3878                         if (rc) {
3879                                 PMD_DRV_LOG(ERR,
3880                                         "Failed to allocate PF resources\n");
3881                                 goto error_free;
3882                         }
3883                 }
3884         }
3885
3886         bnxt_hwrm_port_led_qcaps(bp);
3887
3888         rc = bnxt_setup_int(bp);
3889         if (rc)
3890                 goto error_free;
3891
3892         rc = bnxt_alloc_mem(bp);
3893         if (rc)
3894                 goto error_free_int;
3895
3896         rc = bnxt_request_int(bp);
3897         if (rc)
3898                 goto error_free_int;
3899
3900         bnxt_enable_int(bp);
3901         bnxt_init_nic(bp);
3902
3903         return 0;
3904
3905 error_free_int:
3906         bnxt_disable_int(bp);
3907         bnxt_hwrm_func_buf_unrgtr(bp);
3908         bnxt_free_int(bp);
3909         bnxt_free_mem(bp);
3910 error_free:
3911         bnxt_dev_uninit(eth_dev);
3912 error:
3913         return rc;
3914 }
3915
3916 static int
3917 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3918 {
3919         struct bnxt *bp = eth_dev->data->dev_private;
3920         int rc;
3921
3922         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3923                 return -EPERM;
3924
3925         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3926         bnxt_disable_int(bp);
3927         bnxt_free_int(bp);
3928         bnxt_free_mem(bp);
3929         if (bp->grp_info != NULL) {
3930                 rte_free(bp->grp_info);
3931                 bp->grp_info = NULL;
3932         }
3933         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3934         bnxt_free_hwrm_resources(bp);
3935
3936         if (bp->tx_mem_zone) {
3937                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3938                 bp->tx_mem_zone = NULL;
3939         }
3940
3941         if (bp->rx_mem_zone) {
3942                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3943                 bp->rx_mem_zone = NULL;
3944         }
3945
3946         if (bp->dev_stopped == 0)
3947                 bnxt_dev_close_op(eth_dev);
3948         if (bp->pf.vf_info)
3949                 rte_free(bp->pf.vf_info);
3950         bnxt_free_ctx_mem(bp);
3951         eth_dev->dev_ops = NULL;
3952         eth_dev->rx_pkt_burst = NULL;
3953         eth_dev->tx_pkt_burst = NULL;
3954
3955         return rc;
3956 }
3957
3958 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3959         struct rte_pci_device *pci_dev)
3960 {
3961         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3962                 bnxt_dev_init);
3963 }
3964
3965 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3966 {
3967         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3968                 return rte_eth_dev_pci_generic_remove(pci_dev,
3969                                 bnxt_dev_uninit);
3970         else
3971                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3972 }
3973
3974 static struct rte_pci_driver bnxt_rte_pmd = {
3975         .id_table = bnxt_pci_id_map,
3976         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3977                 RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_IOVA_AS_VA,
3978         .probe = bnxt_pci_probe,
3979         .remove = bnxt_pci_remove,
3980 };
3981
3982 static bool
3983 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3984 {
3985         if (strcmp(dev->device->driver->name, drv->driver.name))
3986                 return false;
3987
3988         return true;
3989 }
3990
3991 bool is_bnxt_supported(struct rte_eth_dev *dev)
3992 {
3993         return is_device_supported(dev, &bnxt_rte_pmd);
3994 }
3995
3996 RTE_INIT(bnxt_init_log)
3997 {
3998         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
3999         if (bnxt_logtype_driver >= 0)
4000                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4001 }
4002
4003 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4004 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4005 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");