drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29 #include "bnxt_util.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  37
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  42 #define BROADCOM_DEV_ID_57301 0x16c8
  43 #define BROADCOM_DEV_ID_57302 0x16c9
  44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  47 #define BROADCOM_DEV_ID_NS2 0x16cd
  48 #define BROADCOM_DEV_ID_57311 0x16ce
  49 #define BROADCOM_DEV_ID_57312 0x16cf
  50 #define BROADCOM_DEV_ID_57402 0x16d0
  51 #define BROADCOM_DEV_ID_57404 0x16d1
  52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  56 #define BROADCOM_DEV_ID_57412 0x16d6
  57 #define BROADCOM_DEV_ID_57414 0x16d7
  58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  61 #define BROADCOM_DEV_ID_57412_MF 0x16de
  62 #define BROADCOM_DEV_ID_57314 0x16df
  63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  74 #define BROADCOM_DEV_ID_58802 0xd802
  75 #define BROADCOM_DEV_ID_58804 0xd804
  76 #define BROADCOM_DEV_ID_58808 0x16f0
  77 #define BROADCOM_DEV_ID_58802_VF 0xd800
  78
  79 static const struct rte_pci_id bnxt_pci_id_map[] = {
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  81                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  83                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 122         { .vendor_id = 0, /* sentinel */ },
 123 };
 124
 125 #define BNXT_ETH_RSS_SUPPORT (  \
 126         ETH_RSS_IPV4 |          \
 127         ETH_RSS_NONFRAG_IPV4_TCP |      \
 128         ETH_RSS_NONFRAG_IPV4_UDP |      \
 129         ETH_RSS_IPV6 |          \
 130         ETH_RSS_NONFRAG_IPV6_TCP |      \
 131         ETH_RSS_NONFRAG_IPV6_UDP)
 132
 133 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 134                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 135                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 136                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 137                                      DEV_TX_OFFLOAD_TCP_TSO | \
 138                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 139                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 140                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 141                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 142                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 143                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 144
 145 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 146                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 147                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 148                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 149                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 150                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 151                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 152                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 153                                      DEV_RX_OFFLOAD_TCP_LRO)
 154
 155 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 156 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 157 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 158 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 159
 160 /***********************/
 161
 162 /*
 163  * High level utility functions
 164  */
 165
 166 static void bnxt_free_mem(struct bnxt *bp)
 167 {
 168         bnxt_free_filter_mem(bp);
 169         bnxt_free_vnic_attributes(bp);
 170         bnxt_free_vnic_mem(bp);
 171
 172         bnxt_free_stats(bp);
 173         bnxt_free_tx_rings(bp);
 174         bnxt_free_rx_rings(bp);
 175 }
 176
 177 static int bnxt_alloc_mem(struct bnxt *bp)
 178 {
 179         int rc;
 180
 181         rc = bnxt_alloc_vnic_mem(bp);
 182         if (rc)
 183                 goto alloc_mem_err;
 184
 185         rc = bnxt_alloc_vnic_attributes(bp);
 186         if (rc)
 187                 goto alloc_mem_err;
 188
 189         rc = bnxt_alloc_filter_mem(bp);
 190         if (rc)
 191                 goto alloc_mem_err;
 192
 193         return 0;
 194
 195 alloc_mem_err:
 196         bnxt_free_mem(bp);
 197         return rc;
 198 }
 199
 200 static int bnxt_init_chip(struct bnxt *bp)
 201 {
 202         struct bnxt_rx_queue *rxq;
 203         struct rte_eth_link new;
 204         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 205         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 206         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 207         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 208         uint32_t intr_vector = 0;
 209         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 210         uint32_t vec = BNXT_MISC_VEC_ID;
 211         unsigned int i, j;
 212         int rc;
 213
 214         /* disable uio/vfio intr/eventfd mapping */
 215         rte_intr_disable(intr_handle);
 216
 217         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 218                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 219                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 220                 bp->flags |= BNXT_FLAG_JUMBO;
 221         } else {
 222                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 223                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 224                 bp->flags &= ~BNXT_FLAG_JUMBO;
 225         }
 226
 227         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 228         if (rc) {
 229                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 230                 goto err_out;
 231         }
 232
 233         rc = bnxt_alloc_hwrm_rings(bp);
 234         if (rc) {
 235                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 236                 goto err_out;
 237         }
 238
 239         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 240         if (rc) {
 241                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 242                 goto err_out;
 243         }
 244
 245         rc = bnxt_mq_rx_configure(bp);
 246         if (rc) {
 247                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 248                 goto err_out;
 249         }
 250
 251         /* VNIC configuration */
 252         for (i = 0; i < bp->nr_vnics; i++) {
 253                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 254                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 255                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 256
 257                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 258                 if (!vnic->fw_grp_ids) {
 259                         PMD_DRV_LOG(ERR,
 260                                     "Failed to alloc %d bytes for group ids\n",
 261                                     size);
 262                         rc = -ENOMEM;
 263                         goto err_out;
 264                 }
 265                 memset(vnic->fw_grp_ids, -1, size);
 266
 267                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 268                             i, vnic, vnic->fw_grp_ids);
 269
 270                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 271                 if (rc) {
 272                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 273                                 i, rc);
 274                         goto err_out;
 275                 }
 276
 277                 /* Alloc RSS context only if RSS mode is enabled */
 278                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 279                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
 280                         if (rc) {
 281                                 PMD_DRV_LOG(ERR,
 282                                         "HWRM vnic %d ctx alloc failure rc: %x\n",
 283                                         i, rc);
 284                                 goto err_out;
 285                         }
 286                 }
 287
 288                 /*
 289                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 290                  * setting is not available at this time, it will not be
 291                  * configured correctly in the CFA.
 292                  */
 293                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 294                         vnic->vlan_strip = true;
 295                 else
 296                         vnic->vlan_strip = false;
 297
 298                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 299                 if (rc) {
 300                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 301                                 i, rc);
 302                         goto err_out;
 303                 }
 304
 305                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 306                 if (rc) {
 307                         PMD_DRV_LOG(ERR,
 308                                 "HWRM vnic %d filter failure rc: %x\n",
 309                                 i, rc);
 310                         goto err_out;
 311                 }
 312
 313                 for (j = 0; j < bp->rx_nr_rings; j++) {
 314                         rxq = bp->eth_dev->data->rx_queues[j];
 315
 316                         PMD_DRV_LOG(DEBUG,
 317                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 318                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 319
 320                         if (rxq->rx_deferred_start)
 321                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 322                 }
 323
 324                 rc = bnxt_vnic_rss_configure(bp, vnic);
 325                 if (rc) {
 326                         PMD_DRV_LOG(ERR,
 327                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 328                         goto err_out;
 329                 }
 330
 331                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 332
 333                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 334                     DEV_RX_OFFLOAD_TCP_LRO)
 335                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 336                 else
 337                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 338         }
 339         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 340         if (rc) {
 341                 PMD_DRV_LOG(ERR,
 342                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 343                 goto err_out;
 344         }
 345
 346         /* check and configure queue intr-vector mapping */
 347         if ((rte_intr_cap_multiple(intr_handle) ||
 348              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 349             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 350                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 351                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 352                 if (intr_vector > bp->rx_cp_nr_rings) {
 353                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 354                                         bp->rx_cp_nr_rings);
 355                         return -ENOTSUP;
 356                 }
 357                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 358                         return -1;
 359         }
 360
 361         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 362                 intr_handle->intr_vec =
 363                         rte_zmalloc("intr_vec",
 364                                     bp->eth_dev->data->nb_rx_queues *
 365                                     sizeof(int), 0);
 366                 if (intr_handle->intr_vec == NULL) {
 367                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 368                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 369                         return -ENOMEM;
 370                 }
 371                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 372                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 373                          intr_handle->intr_vec, intr_handle->nb_efd,
 374                         intr_handle->max_intr);
 375         }
 376
 377         for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 378              queue_id++) {
 379                 intr_handle->intr_vec[queue_id] = vec;
 380                 if (vec < base + intr_handle->nb_efd - 1)
 381                         vec++;
 382         }
 383
 384         /* enable uio/vfio intr/eventfd mapping */
 385         rte_intr_enable(intr_handle);
 386
 387         rc = bnxt_get_hwrm_link_config(bp, &new);
 388         if (rc) {
 389                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 390                 goto err_out;
 391         }
 392
 393         if (!bp->link_info.link_up) {
 394                 rc = bnxt_set_hwrm_link_config(bp, true);
 395                 if (rc) {
 396                         PMD_DRV_LOG(ERR,
 397                                 "HWRM link config failure rc: %x\n", rc);
 398                         goto err_out;
 399                 }
 400         }
 401         bnxt_print_link_info(bp->eth_dev);
 402
 403         return 0;
 404
 405 err_out:
 406         bnxt_free_all_hwrm_resources(bp);
 407
 408         /* Some of the error status returned by FW may not be from errno.h */
 409         if (rc > 0)
 410                 rc = -EIO;
 411
 412         return rc;
 413 }
 414
 415 static int bnxt_shutdown_nic(struct bnxt *bp)
 416 {
 417         bnxt_free_all_hwrm_resources(bp);
 418         bnxt_free_all_filters(bp);
 419         bnxt_free_all_vnics(bp);
 420         return 0;
 421 }
 422
 423 static int bnxt_init_nic(struct bnxt *bp)
 424 {
 425         int rc;
 426
 427         rc = bnxt_init_ring_grps(bp);
 428         if (rc)
 429                 return rc;
 430
 431         bnxt_init_vnics(bp);
 432         bnxt_init_filters(bp);
 433
 434         return 0;
 435 }
 436
 437 /*
 438  * Device configuration and status function
 439  */
 440
 441 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 442                                   struct rte_eth_dev_info *dev_info)
 443 {
 444         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 445         uint16_t max_vnics, i, j, vpool, vrxq;
 446         unsigned int max_rx_rings;
 447
 448         /* MAC Specifics */
 449         dev_info->max_mac_addrs = bp->max_l2_ctx;
 450         dev_info->max_hash_mac_addrs = 0;
 451
 452         /* PF/VF specifics */
 453         if (BNXT_PF(bp))
 454                 dev_info->max_vfs = bp->pdev->max_vfs;
 455         max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
 456         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 457         dev_info->max_rx_queues = max_rx_rings;
 458         dev_info->max_tx_queues = max_rx_rings;
 459         dev_info->reta_size = HW_HASH_INDEX_SIZE;
 460         dev_info->hash_key_size = 40;
 461         max_vnics = bp->max_vnics;
 462
 463         /* Fast path specifics */
 464         dev_info->min_rx_bufsize = 1;
 465         dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
 466                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
 467
 468         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 469         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 470                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 471         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 472         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 473
 474         /* *INDENT-OFF* */
 475         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 476                 .rx_thresh = {
 477                         .pthresh = 8,
 478                         .hthresh = 8,
 479                         .wthresh = 0,
 480                 },
 481                 .rx_free_thresh = 32,
 482                 /* If no descriptors available, pkts are dropped by default */
 483                 .rx_drop_en = 1,
 484         };
 485
 486         dev_info->default_txconf = (struct rte_eth_txconf) {
 487                 .tx_thresh = {
 488                         .pthresh = 32,
 489                         .hthresh = 0,
 490                         .wthresh = 0,
 491                 },
 492                 .tx_free_thresh = 32,
 493                 .tx_rs_thresh = 32,
 494         };
 495         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 496
 497         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 498         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 499         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 500         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 501         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 502
 503         /* *INDENT-ON* */
 504
 505         /*
 506          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 507          *       need further investigation.
 508          */
 509
 510         /* VMDq resources */
 511         vpool = 64; /* ETH_64_POOLS */
 512         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 513         for (i = 0; i < 4; vpool >>= 1, i++) {
 514                 if (max_vnics > vpool) {
 515                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 516                                 if (dev_info->max_rx_queues > vrxq) {
 517                                         if (vpool > vrxq)
 518                                                 vpool = vrxq;
 519                                         goto found;
 520                                 }
 521                         }
 522                         /* Not enough resources to support VMDq */
 523                         break;
 524                 }
 525         }
 526         /* Not enough resources to support VMDq */
 527         vpool = 0;
 528         vrxq = 0;
 529 found:
 530         dev_info->max_vmdq_pools = vpool;
 531         dev_info->vmdq_queue_num = vrxq;
 532
 533         dev_info->vmdq_pool_base = 0;
 534         dev_info->vmdq_queue_base = 0;
 535 }
 536
 537 /* Configure the device based on the configuration provided */
 538 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 539 {
 540         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 541         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 542         int rc;
 543
 544         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 545         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 546         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 547         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 548
 549         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 550                 rc = bnxt_hwrm_check_vf_rings(bp);
 551                 if (rc) {
 552                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 553                         return -ENOSPC;
 554                 }
 555
 556                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 557                 if (rc) {
 558                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 559                         return -ENOSPC;
 560                 }
 561         } else {
 562                 /* legacy driver needs to get updated values */
 563                 rc = bnxt_hwrm_func_qcaps(bp);
 564                 if (rc) {
 565                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 566                         return rc;
 567                 }
 568         }
 569
 570         /* Inherit new configurations */
 571         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 572             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 573             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 574             bp->max_cp_rings ||
 575             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 576             bp->max_stat_ctx ||
 577             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps ||
 578             (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 579              bp->max_vnics < eth_dev->data->nb_rx_queues)) {
 580                 PMD_DRV_LOG(ERR,
 581                         "Insufficient resources to support requested config\n");
 582                 PMD_DRV_LOG(ERR,
 583                         "Num Queues Requested: Tx %d, Rx %d\n",
 584                         eth_dev->data->nb_tx_queues,
 585                         eth_dev->data->nb_rx_queues);
 586                 PMD_DRV_LOG(ERR,
 587                         "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 588                         bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 589                         bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 590                 return -ENOSPC;
 591         }
 592
 593         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 594         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 595
 596         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 597                 eth_dev->data->mtu =
 598                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 599                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 600                         BNXT_NUM_VLANS;
 601                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 602         }
 603         return 0;
 604 }
 605
 606 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 607 {
 608         struct rte_eth_link *link = &eth_dev->data->dev_link;
 609
 610         if (link->link_status)
 611                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 612                         eth_dev->data->port_id,
 613                         (uint32_t)link->link_speed,
 614                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 615                         ("full-duplex") : ("half-duplex\n"));
 616         else
 617                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 618                         eth_dev->data->port_id);
 619 }
 620
 621 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
 622 {
 623         bnxt_print_link_info(eth_dev);
 624         return 0;
 625 }
 626
 627 /*
 628  * Determine whether the current configuration requires support for scattered
 629  * receive; return 1 if scattered receive is required and 0 if not.
 630  */
 631 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 632 {
 633         uint16_t buf_size;
 634         int i;
 635
 636         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 637                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 638
 639                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 640                                       RTE_PKTMBUF_HEADROOM);
 641                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 642                         return 1;
 643         }
 644         return 0;
 645 }
 646
 647 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 648 {
 649         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 650         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 651         int vlan_mask = 0;
 652         int rc;
 653
 654         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 655                 PMD_DRV_LOG(ERR,
 656                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 657                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 658         }
 659         bp->dev_stopped = 0;
 660
 661         rc = bnxt_init_chip(bp);
 662         if (rc)
 663                 goto error;
 664
 665         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 666
 667         bnxt_link_update_op(eth_dev, 1);
 668
 669         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 670                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 671         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 672                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 673         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 674         if (rc)
 675                 goto error;
 676
 677         bp->flags |= BNXT_FLAG_INIT_DONE;
 678         return 0;
 679
 680 error:
 681         bnxt_shutdown_nic(bp);
 682         bnxt_free_tx_mbufs(bp);
 683         bnxt_free_rx_mbufs(bp);
 684         return rc;
 685 }
 686
 687 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 688 {
 689         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 690         int rc = 0;
 691
 692         if (!bp->link_info.link_up)
 693                 rc = bnxt_set_hwrm_link_config(bp, true);
 694         if (!rc)
 695                 eth_dev->data->dev_link.link_status = 1;
 696
 697         bnxt_print_link_info(eth_dev);
 698         return 0;
 699 }
 700
 701 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 702 {
 703         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 704
 705         eth_dev->data->dev_link.link_status = 0;
 706         bnxt_set_hwrm_link_config(bp, false);
 707         bp->link_info.link_up = 0;
 708
 709         return 0;
 710 }
 711
 712 /* Unload the driver, release resources */
 713 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 714 {
 715         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 716
 717         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 718         if (bp->eth_dev->data->dev_started) {
 719                 /* TBD: STOP HW queues DMA */
 720                 eth_dev->data->dev_link.link_status = 0;
 721         }
 722         bnxt_set_hwrm_link_config(bp, false);
 723         bnxt_hwrm_port_clr_stats(bp);
 724         bnxt_free_tx_mbufs(bp);
 725         bnxt_free_rx_mbufs(bp);
 726         bnxt_shutdown_nic(bp);
 727         bp->dev_stopped = 1;
 728 }
 729
 730 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 731 {
 732         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 733
 734         if (bp->dev_stopped == 0)
 735                 bnxt_dev_stop_op(eth_dev);
 736
 737         if (eth_dev->data->mac_addrs != NULL) {
 738                 rte_free(eth_dev->data->mac_addrs);
 739                 eth_dev->data->mac_addrs = NULL;
 740         }
 741         if (bp->grp_info != NULL) {
 742                 rte_free(bp->grp_info);
 743                 bp->grp_info = NULL;
 744         }
 745
 746         bnxt_dev_uninit(eth_dev);
 747 }
 748
 749 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 750                                     uint32_t index)
 751 {
 752         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 753         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 754         struct bnxt_vnic_info *vnic;
 755         struct bnxt_filter_info *filter, *temp_filter;
 756         uint32_t i;
 757
 758         /*
 759          * Loop through all VNICs from the specified filter flow pools to
 760          * remove the corresponding MAC addr filter
 761          */
 762         for (i = 0; i < bp->nr_vnics; i++) {
 763                 if (!(pool_mask & (1ULL << i)))
 764                         continue;
 765
 766                 vnic = &bp->vnic_info[i];
 767                 filter = STAILQ_FIRST(&vnic->filter);
 768                 while (filter) {
 769                         temp_filter = STAILQ_NEXT(filter, next);
 770                         if (filter->mac_index == index) {
 771                                 STAILQ_REMOVE(&vnic->filter, filter,
 772                                                 bnxt_filter_info, next);
 773                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 774                                 filter->mac_index = INVALID_MAC_INDEX;
 775                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 776                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 777                                                    filter, next);
 778                         }
 779                         filter = temp_filter;
 780                 }
 781         }
 782 }
 783
 784 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 785                                 struct rte_ether_addr *mac_addr,
 786                                 uint32_t index, uint32_t pool)
 787 {
 788         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 789         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
 790         struct bnxt_filter_info *filter;
 791
 792         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
 793                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 794                 return -ENOTSUP;
 795         }
 796
 797         if (!vnic) {
 798                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 799                 return -EINVAL;
 800         }
 801         /* Attach requested MAC address to the new l2_filter */
 802         STAILQ_FOREACH(filter, &vnic->filter, next) {
 803                 if (filter->mac_index == index) {
 804                         PMD_DRV_LOG(ERR,
 805                                 "MAC addr already existed for pool %d\n", pool);
 806                         return 0;
 807                 }
 808         }
 809         filter = bnxt_alloc_filter(bp);
 810         if (!filter) {
 811                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 812                 return -ENODEV;
 813         }
 814         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 815         filter->mac_index = index;
 816         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
 817         return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 818 }
 819
 820 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 821 {
 822         int rc = 0;
 823         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 824         struct rte_eth_link new;
 825         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 826
 827         memset(&new, 0, sizeof(new));
 828         do {
 829                 /* Retrieve link info from hardware */
 830                 rc = bnxt_get_hwrm_link_config(bp, &new);
 831                 if (rc) {
 832                         new.link_speed = ETH_LINK_SPEED_100M;
 833                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 834                         PMD_DRV_LOG(ERR,
 835                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 836                         goto out;
 837                 }
 838                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 839
 840                 if (!wait_to_complete)
 841                         break;
 842         } while (!new.link_status && cnt--);
 843
 844 out:
 845         /* Timed out or success */
 846         if (new.link_status != eth_dev->data->dev_link.link_status ||
 847         new.link_speed != eth_dev->data->dev_link.link_speed) {
 848                 memcpy(&eth_dev->data->dev_link, &new,
 849                         sizeof(struct rte_eth_link));
 850
 851                 _rte_eth_dev_callback_process(eth_dev,
 852                                               RTE_ETH_EVENT_INTR_LSC,
 853                                               NULL);
 854
 855                 bnxt_print_link_info(eth_dev);
 856         }
 857
 858         return rc;
 859 }
 860
 861 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
 862 {
 863         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 864         struct bnxt_vnic_info *vnic;
 865
 866         if (bp->vnic_info == NULL)
 867                 return;
 868
 869         vnic = &bp->vnic_info[0];
 870
 871         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
 872         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 873 }
 874
 875 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
 876 {
 877         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 878         struct bnxt_vnic_info *vnic;
 879
 880         if (bp->vnic_info == NULL)
 881                 return;
 882
 883         vnic = &bp->vnic_info[0];
 884
 885         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
 886         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 887 }
 888
 889 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
 890 {
 891         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 892         struct bnxt_vnic_info *vnic;
 893
 894         if (bp->vnic_info == NULL)
 895                 return;
 896
 897         vnic = &bp->vnic_info[0];
 898
 899         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
 900         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 901 }
 902
 903 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
 904 {
 905         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 906         struct bnxt_vnic_info *vnic;
 907
 908         if (bp->vnic_info == NULL)
 909                 return;
 910
 911         vnic = &bp->vnic_info[0];
 912
 913         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
 914         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 915 }
 916
 917 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
 918                             struct rte_eth_rss_reta_entry64 *reta_conf,
 919                             uint16_t reta_size)
 920 {
 921         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 922         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 923         struct bnxt_vnic_info *vnic;
 924         int i;
 925
 926         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
 927                 return -EINVAL;
 928
 929         if (reta_size != HW_HASH_INDEX_SIZE) {
 930                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
 931                         "(%d) must equal the size supported by the hardware "
 932                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 933                 return -EINVAL;
 934         }
 935         /* Update the RSS VNIC(s) */
 936         for (i = 0; i < bp->max_vnics; i++) {
 937                 vnic = &bp->vnic_info[i];
 938                 memcpy(vnic->rss_table, reta_conf, reta_size);
 939                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 940         }
 941         return 0;
 942 }
 943
 944 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
 945                               struct rte_eth_rss_reta_entry64 *reta_conf,
 946                               uint16_t reta_size)
 947 {
 948         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 949         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 950         struct rte_intr_handle *intr_handle
 951                 = &bp->pdev->intr_handle;
 952
 953         /* Retrieve from the default VNIC */
 954         if (!vnic)
 955                 return -EINVAL;
 956         if (!vnic->rss_table)
 957                 return -EINVAL;
 958
 959         if (reta_size != HW_HASH_INDEX_SIZE) {
 960                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
 961                         "(%d) must equal the size supported by the hardware "
 962                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 963                 return -EINVAL;
 964         }
 965         /* EW - need to revisit here copying from uint64_t to uint16_t */
 966         memcpy(reta_conf, vnic->rss_table, reta_size);
 967
 968         if (rte_intr_allow_others(intr_handle)) {
 969                 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
 970                         bnxt_dev_lsc_intr_setup(eth_dev);
 971         }
 972
 973         return 0;
 974 }
 975
 976 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
 977                                    struct rte_eth_rss_conf *rss_conf)
 978 {
 979         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 980         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 981         struct bnxt_vnic_info *vnic;
 982         uint16_t hash_type = 0;
 983         unsigned int i;
 984
 985         /*
 986          * If RSS enablement were different than dev_configure,
 987          * then return -EINVAL
 988          */
 989         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
 990                 if (!rss_conf->rss_hf)
 991                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
 992         } else {
 993                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
 994                         return -EINVAL;
 995         }
 996
 997         bp->flags |= BNXT_FLAG_UPDATE_HASH;
 998         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
 999
1000         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1001                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1002         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1003                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1004         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1005                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1006         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1007                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1008         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1009                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1010         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1011                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1012
1013         /* Update the RSS VNIC(s) */
1014         for (i = 0; i < bp->nr_vnics; i++) {
1015                 vnic = &bp->vnic_info[i];
1016                 vnic->hash_type = hash_type;
1017
1018                 /*
1019                  * Use the supplied key if the key length is
1020                  * acceptable and the rss_key is not NULL
1021                  */
1022                 if (rss_conf->rss_key &&
1023                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1024                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1025                                rss_conf->rss_key_len);
1026
1027                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1028         }
1029         return 0;
1030 }
1031
1032 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1033                                      struct rte_eth_rss_conf *rss_conf)
1034 {
1035         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1036         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1037         int len;
1038         uint32_t hash_types;
1039
1040         /* RSS configuration is the same for all VNICs */
1041         if (vnic && vnic->rss_hash_key) {
1042                 if (rss_conf->rss_key) {
1043                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1044                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1045                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1046                 }
1047
1048                 hash_types = vnic->hash_type;
1049                 rss_conf->rss_hf = 0;
1050                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1051                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1052                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1053                 }
1054                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1055                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1056                         hash_types &=
1057                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1058                 }
1059                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1060                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1061                         hash_types &=
1062                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1063                 }
1064                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1065                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1066                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1067                 }
1068                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1069                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1070                         hash_types &=
1071                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1072                 }
1073                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1074                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1075                         hash_types &=
1076                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1077                 }
1078                 if (hash_types) {
1079                         PMD_DRV_LOG(ERR,
1080                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1081                                 vnic->hash_type);
1082                         return -ENOTSUP;
1083                 }
1084         } else {
1085                 rss_conf->rss_hf = 0;
1086         }
1087         return 0;
1088 }
1089
1090 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1091                                struct rte_eth_fc_conf *fc_conf)
1092 {
1093         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1094         struct rte_eth_link link_info;
1095         int rc;
1096
1097         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1098         if (rc)
1099                 return rc;
1100
1101         memset(fc_conf, 0, sizeof(*fc_conf));
1102         if (bp->link_info.auto_pause)
1103                 fc_conf->autoneg = 1;
1104         switch (bp->link_info.pause) {
1105         case 0:
1106                 fc_conf->mode = RTE_FC_NONE;
1107                 break;
1108         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1109                 fc_conf->mode = RTE_FC_TX_PAUSE;
1110                 break;
1111         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1112                 fc_conf->mode = RTE_FC_RX_PAUSE;
1113                 break;
1114         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1115                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1116                 fc_conf->mode = RTE_FC_FULL;
1117                 break;
1118         }
1119         return 0;
1120 }
1121
1122 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1123                                struct rte_eth_fc_conf *fc_conf)
1124 {
1125         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1126
1127         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1128                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1129                 return -ENOTSUP;
1130         }
1131
1132         switch (fc_conf->mode) {
1133         case RTE_FC_NONE:
1134                 bp->link_info.auto_pause = 0;
1135                 bp->link_info.force_pause = 0;
1136                 break;
1137         case RTE_FC_RX_PAUSE:
1138                 if (fc_conf->autoneg) {
1139                         bp->link_info.auto_pause =
1140                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1141                         bp->link_info.force_pause = 0;
1142                 } else {
1143                         bp->link_info.auto_pause = 0;
1144                         bp->link_info.force_pause =
1145                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1146                 }
1147                 break;
1148         case RTE_FC_TX_PAUSE:
1149                 if (fc_conf->autoneg) {
1150                         bp->link_info.auto_pause =
1151                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1152                         bp->link_info.force_pause = 0;
1153                 } else {
1154                         bp->link_info.auto_pause = 0;
1155                         bp->link_info.force_pause =
1156                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1157                 }
1158                 break;
1159         case RTE_FC_FULL:
1160                 if (fc_conf->autoneg) {
1161                         bp->link_info.auto_pause =
1162                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1163                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1164                         bp->link_info.force_pause = 0;
1165                 } else {
1166                         bp->link_info.auto_pause = 0;
1167                         bp->link_info.force_pause =
1168                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1169                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1170                 }
1171                 break;
1172         }
1173         return bnxt_set_hwrm_link_config(bp, true);
1174 }
1175
1176 /* Add UDP tunneling port */
1177 static int
1178 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1179                          struct rte_eth_udp_tunnel *udp_tunnel)
1180 {
1181         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1182         uint16_t tunnel_type = 0;
1183         int rc = 0;
1184
1185         switch (udp_tunnel->prot_type) {
1186         case RTE_TUNNEL_TYPE_VXLAN:
1187                 if (bp->vxlan_port_cnt) {
1188                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1189                                 udp_tunnel->udp_port);
1190                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1191                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1192                                 return -ENOSPC;
1193                         }
1194                         bp->vxlan_port_cnt++;
1195                         return 0;
1196                 }
1197                 tunnel_type =
1198                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1199                 bp->vxlan_port_cnt++;
1200                 break;
1201         case RTE_TUNNEL_TYPE_GENEVE:
1202                 if (bp->geneve_port_cnt) {
1203                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1204                                 udp_tunnel->udp_port);
1205                         if (bp->geneve_port != udp_tunnel->udp_port) {
1206                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1207                                 return -ENOSPC;
1208                         }
1209                         bp->geneve_port_cnt++;
1210                         return 0;
1211                 }
1212                 tunnel_type =
1213                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1214                 bp->geneve_port_cnt++;
1215                 break;
1216         default:
1217                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1218                 return -ENOTSUP;
1219         }
1220         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1221                                              tunnel_type);
1222         return rc;
1223 }
1224
1225 static int
1226 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1227                          struct rte_eth_udp_tunnel *udp_tunnel)
1228 {
1229         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1230         uint16_t tunnel_type = 0;
1231         uint16_t port = 0;
1232         int rc = 0;
1233
1234         switch (udp_tunnel->prot_type) {
1235         case RTE_TUNNEL_TYPE_VXLAN:
1236                 if (!bp->vxlan_port_cnt) {
1237                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1238                         return -EINVAL;
1239                 }
1240                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1241                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1242                                 udp_tunnel->udp_port, bp->vxlan_port);
1243                         return -EINVAL;
1244                 }
1245                 if (--bp->vxlan_port_cnt)
1246                         return 0;
1247
1248                 tunnel_type =
1249                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1250                 port = bp->vxlan_fw_dst_port_id;
1251                 break;
1252         case RTE_TUNNEL_TYPE_GENEVE:
1253                 if (!bp->geneve_port_cnt) {
1254                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1255                         return -EINVAL;
1256                 }
1257                 if (bp->geneve_port != udp_tunnel->udp_port) {
1258                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1259                                 udp_tunnel->udp_port, bp->geneve_port);
1260                         return -EINVAL;
1261                 }
1262                 if (--bp->geneve_port_cnt)
1263                         return 0;
1264
1265                 tunnel_type =
1266                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1267                 port = bp->geneve_fw_dst_port_id;
1268                 break;
1269         default:
1270                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1271                 return -ENOTSUP;
1272         }
1273
1274         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1275         if (!rc) {
1276                 if (tunnel_type ==
1277                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1278                         bp->vxlan_port = 0;
1279                 if (tunnel_type ==
1280                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1281                         bp->geneve_port = 0;
1282         }
1283         return rc;
1284 }
1285
1286 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1287 {
1288         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1289         struct bnxt_vnic_info *vnic;
1290         unsigned int i;
1291         int rc = 0;
1292         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1293
1294         /* Cycle through all VNICs */
1295         for (i = 0; i < bp->nr_vnics; i++) {
1296                 /*
1297                  * For each VNIC and each associated filter(s)
1298                  * if VLAN exists && VLAN matches vlan_id
1299                  *      remove the MAC+VLAN filter
1300                  *      add a new MAC only filter
1301                  * else
1302                  *      VLAN filter doesn't exist, just skip and continue
1303                  */
1304                 vnic = &bp->vnic_info[i];
1305                 filter = STAILQ_FIRST(&vnic->filter);
1306                 while (filter) {
1307                         temp_filter = STAILQ_NEXT(filter, next);
1308
1309                         if (filter->enables & chk &&
1310                             filter->l2_ovlan == vlan_id) {
1311                                 /* Must delete the filter */
1312                                 STAILQ_REMOVE(&vnic->filter, filter,
1313                                               bnxt_filter_info, next);
1314                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1315                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1316                                                    filter, next);
1317
1318                                 /*
1319                                  * Need to examine to see if the MAC
1320                                  * filter already existed or not before
1321                                  * allocating a new one
1322                                  */
1323
1324                                 new_filter = bnxt_alloc_filter(bp);
1325                                 if (!new_filter) {
1326                                         PMD_DRV_LOG(ERR,
1327                                                         "MAC/VLAN filter alloc failed\n");
1328                                         rc = -ENOMEM;
1329                                         goto exit;
1330                                 }
1331                                 STAILQ_INSERT_TAIL(&vnic->filter,
1332                                                 new_filter, next);
1333                                 /* Inherit MAC from previous filter */
1334                                 new_filter->mac_index =
1335                                         filter->mac_index;
1336                                 memcpy(new_filter->l2_addr, filter->l2_addr,
1337                                        RTE_ETHER_ADDR_LEN);
1338                                 /* MAC only filter */
1339                                 rc = bnxt_hwrm_set_l2_filter(bp,
1340                                                              vnic->fw_vnic_id,
1341                                                              new_filter);
1342                                 if (rc)
1343                                         goto exit;
1344                                 PMD_DRV_LOG(INFO,
1345                                             "Del Vlan filter for %d\n",
1346                                             vlan_id);
1347                         }
1348                         filter = temp_filter;
1349                 }
1350         }
1351 exit:
1352         return rc;
1353 }
1354
1355 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1356 {
1357         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1358         struct bnxt_vnic_info *vnic;
1359         unsigned int i;
1360         int rc = 0;
1361         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1362                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1363         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1364
1365         /* Cycle through all VNICs */
1366         for (i = 0; i < bp->nr_vnics; i++) {
1367                 /*
1368                  * For each VNIC and each associated filter(s)
1369                  * if VLAN exists:
1370                  *   if VLAN matches vlan_id
1371                  *      VLAN filter already exists, just skip and continue
1372                  *   else
1373                  *      add a new MAC+VLAN filter
1374                  * else
1375                  *   Remove the old MAC only filter
1376                  *    Add a new MAC+VLAN filter
1377                  */
1378                 vnic = &bp->vnic_info[i];
1379                 filter = STAILQ_FIRST(&vnic->filter);
1380                 while (filter) {
1381                         temp_filter = STAILQ_NEXT(filter, next);
1382
1383                         if (filter->enables & chk) {
1384                                 if (filter->l2_ivlan == vlan_id)
1385                                         goto cont;
1386                         } else {
1387                                 /* Must delete the MAC filter */
1388                                 STAILQ_REMOVE(&vnic->filter, filter,
1389                                                 bnxt_filter_info, next);
1390                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1391                                 filter->l2_ovlan = 0;
1392                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1393                                                    filter, next);
1394                         }
1395                         new_filter = bnxt_alloc_filter(bp);
1396                         if (!new_filter) {
1397                                 PMD_DRV_LOG(ERR,
1398                                                 "MAC/VLAN filter alloc failed\n");
1399                                 rc = -ENOMEM;
1400                                 goto exit;
1401                         }
1402                         STAILQ_INSERT_TAIL(&vnic->filter, new_filter, next);
1403                         /* Inherit MAC from the previous filter */
1404                         new_filter->mac_index = filter->mac_index;
1405                         memcpy(new_filter->l2_addr, filter->l2_addr,
1406                                RTE_ETHER_ADDR_LEN);
1407                         /* MAC + VLAN ID filter */
1408                         new_filter->l2_ivlan = vlan_id;
1409                         new_filter->l2_ivlan_mask = 0xF000;
1410                         new_filter->enables |= en;
1411                         rc = bnxt_hwrm_set_l2_filter(bp,
1412                                         vnic->fw_vnic_id,
1413                                         new_filter);
1414                         if (rc)
1415                                 goto exit;
1416                         PMD_DRV_LOG(INFO,
1417                                     "Added Vlan filter for %d\n", vlan_id);
1418 cont:
1419                         filter = temp_filter;
1420                 }
1421         }
1422 exit:
1423         return rc;
1424 }
1425
1426 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1427                 uint16_t vlan_id, int on)
1428 {
1429         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1430
1431         /* These operations apply to ALL existing MAC/VLAN filters */
1432         if (on)
1433                 return bnxt_add_vlan_filter(bp, vlan_id);
1434         else
1435                 return bnxt_del_vlan_filter(bp, vlan_id);
1436 }
1437
1438 static int
1439 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1440 {
1441         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1442         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1443         unsigned int i;
1444
1445         if (mask & ETH_VLAN_FILTER_MASK) {
1446                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1447                         /* Remove any VLAN filters programmed */
1448                         for (i = 0; i < 4095; i++)
1449                                 bnxt_del_vlan_filter(bp, i);
1450                 }
1451                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1452                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1453         }
1454
1455         if (mask & ETH_VLAN_STRIP_MASK) {
1456                 /* Enable or disable VLAN stripping */
1457                 for (i = 0; i < bp->nr_vnics; i++) {
1458                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1459                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1460                                 vnic->vlan_strip = true;
1461                         else
1462                                 vnic->vlan_strip = false;
1463                         bnxt_hwrm_vnic_cfg(bp, vnic);
1464                 }
1465                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1466                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1467         }
1468
1469         if (mask & ETH_VLAN_EXTEND_MASK)
1470                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1471
1472         return 0;
1473 }
1474
1475 static int
1476 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1477                         struct rte_ether_addr *addr)
1478 {
1479         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1480         /* Default Filter is tied to VNIC 0 */
1481         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1482         struct bnxt_filter_info *filter;
1483         int rc;
1484
1485         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1486                 return -EPERM;
1487
1488         memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1489
1490         STAILQ_FOREACH(filter, &vnic->filter, next) {
1491                 /* Default Filter is at Index 0 */
1492                 if (filter->mac_index != 0)
1493                         continue;
1494                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1495                 if (rc)
1496                         return rc;
1497                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1498                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1499                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1500                 filter->enables |=
1501                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1502                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1503                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1504                 if (rc)
1505                         return rc;
1506                 filter->mac_index = 0;
1507                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1508         }
1509
1510         return 0;
1511 }
1512
1513 static int
1514 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1515                           struct rte_ether_addr *mc_addr_set,
1516                           uint32_t nb_mc_addr)
1517 {
1518         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1519         char *mc_addr_list = (char *)mc_addr_set;
1520         struct bnxt_vnic_info *vnic;
1521         uint32_t off = 0, i = 0;
1522
1523         vnic = &bp->vnic_info[0];
1524
1525         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1526                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1527                 goto allmulti;
1528         }
1529
1530         /* TODO Check for Duplicate mcast addresses */
1531         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1532         for (i = 0; i < nb_mc_addr; i++) {
1533                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1534                         RTE_ETHER_ADDR_LEN);
1535                 off += RTE_ETHER_ADDR_LEN;
1536         }
1537
1538         vnic->mc_addr_cnt = i;
1539
1540 allmulti:
1541         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1542 }
1543
1544 static int
1545 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1546 {
1547         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1548         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1549         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1550         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1551         int ret;
1552
1553         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1554                         fw_major, fw_minor, fw_updt);
1555
1556         ret += 1; /* add the size of '\0' */
1557         if (fw_size < (uint32_t)ret)
1558                 return ret;
1559         else
1560                 return 0;
1561 }
1562
1563 static void
1564 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1565         struct rte_eth_rxq_info *qinfo)
1566 {
1567         struct bnxt_rx_queue *rxq;
1568
1569         rxq = dev->data->rx_queues[queue_id];
1570
1571         qinfo->mp = rxq->mb_pool;
1572         qinfo->scattered_rx = dev->data->scattered_rx;
1573         qinfo->nb_desc = rxq->nb_rx_desc;
1574
1575         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1576         qinfo->conf.rx_drop_en = 0;
1577         qinfo->conf.rx_deferred_start = 0;
1578 }
1579
1580 static void
1581 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1582         struct rte_eth_txq_info *qinfo)
1583 {
1584         struct bnxt_tx_queue *txq;
1585
1586         txq = dev->data->tx_queues[queue_id];
1587
1588         qinfo->nb_desc = txq->nb_tx_desc;
1589
1590         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1591         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1592         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1593
1594         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1595         qinfo->conf.tx_rs_thresh = 0;
1596         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1597 }
1598
1599 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1600 {
1601         struct bnxt *bp = eth_dev->data->dev_private;
1602         struct rte_eth_dev_info dev_info;
1603         uint32_t rc = 0;
1604         uint32_t i;
1605
1606         bnxt_dev_info_get_op(eth_dev, &dev_info);
1607
1608         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1609                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1610                         RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1611                 return -EINVAL;
1612         }
1613
1614         if (new_mtu > RTE_ETHER_MTU) {
1615                 bp->flags |= BNXT_FLAG_JUMBO;
1616                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1617                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1618         } else {
1619                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1620                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1621                 bp->flags &= ~BNXT_FLAG_JUMBO;
1622         }
1623
1624         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1625                 new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1626                 VLAN_TAG_SIZE * 2;
1627
1628         eth_dev->data->mtu = new_mtu;
1629         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1630
1631         for (i = 0; i < bp->nr_vnics; i++) {
1632                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1633                 uint16_t size = 0;
1634
1635                 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1636                                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1637                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1638                 if (rc)
1639                         break;
1640
1641                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1642                 size -= RTE_PKTMBUF_HEADROOM;
1643
1644                 if (size < new_mtu) {
1645                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1646                         if (rc)
1647                                 return rc;
1648                 }
1649         }
1650
1651         return rc;
1652 }
1653
1654 static int
1655 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1656 {
1657         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1658         uint16_t vlan = bp->vlan;
1659         int rc;
1660
1661         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1662                 PMD_DRV_LOG(ERR,
1663                         "PVID cannot be modified for this function\n");
1664                 return -ENOTSUP;
1665         }
1666         bp->vlan = on ? pvid : 0;
1667
1668         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1669         if (rc)
1670                 bp->vlan = vlan;
1671         return rc;
1672 }
1673
1674 static int
1675 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1676 {
1677         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1678
1679         return bnxt_hwrm_port_led_cfg(bp, true);
1680 }
1681
1682 static int
1683 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1684 {
1685         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1686
1687         return bnxt_hwrm_port_led_cfg(bp, false);
1688 }
1689
1690 static uint32_t
1691 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1692 {
1693         uint32_t desc = 0, raw_cons = 0, cons;
1694         struct bnxt_cp_ring_info *cpr;
1695         struct bnxt_rx_queue *rxq;
1696         struct rx_pkt_cmpl *rxcmp;
1697         uint16_t cmp_type;
1698         uint8_t cmp = 1;
1699         bool valid;
1700
1701         rxq = dev->data->rx_queues[rx_queue_id];
1702         cpr = rxq->cp_ring;
1703         valid = cpr->valid;
1704
1705         while (raw_cons < rxq->nb_rx_desc) {
1706                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1707                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1708
1709                 if (!CMPL_VALID(rxcmp, valid))
1710                         goto nothing_to_do;
1711                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1712                 cmp_type = CMP_TYPE(rxcmp);
1713                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1714                         cmp = (rte_le_to_cpu_32(
1715                                         ((struct rx_tpa_end_cmpl *)
1716                                          (rxcmp))->agg_bufs_v1) &
1717                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1718                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1719                         desc++;
1720                 } else if (cmp_type == 0x11) {
1721                         desc++;
1722                         cmp = (rxcmp->agg_bufs_v1 &
1723                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1724                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1725                 } else {
1726                         cmp = 1;
1727                 }
1728 nothing_to_do:
1729                 raw_cons += cmp ? cmp : 2;
1730         }
1731
1732         return desc;
1733 }
1734
1735 static int
1736 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1737 {
1738         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1739         struct bnxt_rx_ring_info *rxr;
1740         struct bnxt_cp_ring_info *cpr;
1741         struct bnxt_sw_rx_bd *rx_buf;
1742         struct rx_pkt_cmpl *rxcmp;
1743         uint32_t cons, cp_cons;
1744
1745         if (!rxq)
1746                 return -EINVAL;
1747
1748         cpr = rxq->cp_ring;
1749         rxr = rxq->rx_ring;
1750
1751         if (offset >= rxq->nb_rx_desc)
1752                 return -EINVAL;
1753
1754         cons = RING_CMP(cpr->cp_ring_struct, offset);
1755         cp_cons = cpr->cp_raw_cons;
1756         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1757
1758         if (cons > cp_cons) {
1759                 if (CMPL_VALID(rxcmp, cpr->valid))
1760                         return RTE_ETH_RX_DESC_DONE;
1761         } else {
1762                 if (CMPL_VALID(rxcmp, !cpr->valid))
1763                         return RTE_ETH_RX_DESC_DONE;
1764         }
1765         rx_buf = &rxr->rx_buf_ring[cons];
1766         if (rx_buf->mbuf == NULL)
1767                 return RTE_ETH_RX_DESC_UNAVAIL;
1768
1769
1770         return RTE_ETH_RX_DESC_AVAIL;
1771 }
1772
1773 static int
1774 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1775 {
1776         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1777         struct bnxt_tx_ring_info *txr;
1778         struct bnxt_cp_ring_info *cpr;
1779         struct bnxt_sw_tx_bd *tx_buf;
1780         struct tx_pkt_cmpl *txcmp;
1781         uint32_t cons, cp_cons;
1782
1783         if (!txq)
1784                 return -EINVAL;
1785
1786         cpr = txq->cp_ring;
1787         txr = txq->tx_ring;
1788
1789         if (offset >= txq->nb_tx_desc)
1790                 return -EINVAL;
1791
1792         cons = RING_CMP(cpr->cp_ring_struct, offset);
1793         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1794         cp_cons = cpr->cp_raw_cons;
1795
1796         if (cons > cp_cons) {
1797                 if (CMPL_VALID(txcmp, cpr->valid))
1798                         return RTE_ETH_TX_DESC_UNAVAIL;
1799         } else {
1800                 if (CMPL_VALID(txcmp, !cpr->valid))
1801                         return RTE_ETH_TX_DESC_UNAVAIL;
1802         }
1803         tx_buf = &txr->tx_buf_ring[cons];
1804         if (tx_buf->mbuf == NULL)
1805                 return RTE_ETH_TX_DESC_DONE;
1806
1807         return RTE_ETH_TX_DESC_FULL;
1808 }
1809
1810 static struct bnxt_filter_info *
1811 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1812                                 struct rte_eth_ethertype_filter *efilter,
1813                                 struct bnxt_vnic_info *vnic0,
1814                                 struct bnxt_vnic_info *vnic,
1815                                 int *ret)
1816 {
1817         struct bnxt_filter_info *mfilter = NULL;
1818         int match = 0;
1819         *ret = 0;
1820
1821         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
1822                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
1823                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1824                         " ethertype filter.", efilter->ether_type);
1825                 *ret = -EINVAL;
1826                 goto exit;
1827         }
1828         if (efilter->queue >= bp->rx_nr_rings) {
1829                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1830                 *ret = -EINVAL;
1831                 goto exit;
1832         }
1833
1834         vnic0 = &bp->vnic_info[0];
1835         vnic = &bp->vnic_info[efilter->queue];
1836         if (vnic == NULL) {
1837                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1838                 *ret = -EINVAL;
1839                 goto exit;
1840         }
1841
1842         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1843                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1844                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1845                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
1846                              mfilter->flags ==
1847                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1848                              mfilter->ethertype == efilter->ether_type)) {
1849                                 match = 1;
1850                                 break;
1851                         }
1852                 }
1853         } else {
1854                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1855                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1856                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
1857                              mfilter->ethertype == efilter->ether_type &&
1858                              mfilter->flags ==
1859                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1860                                 match = 1;
1861                                 break;
1862                         }
1863         }
1864
1865         if (match)
1866                 *ret = -EEXIST;
1867
1868 exit:
1869         return mfilter;
1870 }
1871
1872 static int
1873 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1874                         enum rte_filter_op filter_op,
1875                         void *arg)
1876 {
1877         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1878         struct rte_eth_ethertype_filter *efilter =
1879                         (struct rte_eth_ethertype_filter *)arg;
1880         struct bnxt_filter_info *bfilter, *filter1;
1881         struct bnxt_vnic_info *vnic, *vnic0;
1882         int ret;
1883
1884         if (filter_op == RTE_ETH_FILTER_NOP)
1885                 return 0;
1886
1887         if (arg == NULL) {
1888                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1889                             filter_op);
1890                 return -EINVAL;
1891         }
1892
1893         vnic0 = &bp->vnic_info[0];
1894         vnic = &bp->vnic_info[efilter->queue];
1895
1896         switch (filter_op) {
1897         case RTE_ETH_FILTER_ADD:
1898                 bnxt_match_and_validate_ether_filter(bp, efilter,
1899                                                         vnic0, vnic, &ret);
1900                 if (ret < 0)
1901                         return ret;
1902
1903                 bfilter = bnxt_get_unused_filter(bp);
1904                 if (bfilter == NULL) {
1905                         PMD_DRV_LOG(ERR,
1906                                 "Not enough resources for a new filter.\n");
1907                         return -ENOMEM;
1908                 }
1909                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1910                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1911                        RTE_ETHER_ADDR_LEN);
1912                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1913                        RTE_ETHER_ADDR_LEN);
1914                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1915                 bfilter->ethertype = efilter->ether_type;
1916                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1917
1918                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1919                 if (filter1 == NULL) {
1920                         ret = -1;
1921                         goto cleanup;
1922                 }
1923                 bfilter->enables |=
1924                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1925                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1926
1927                 bfilter->dst_id = vnic->fw_vnic_id;
1928
1929                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1930                         bfilter->flags =
1931                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1932                 }
1933
1934                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1935                 if (ret)
1936                         goto cleanup;
1937                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1938                 break;
1939         case RTE_ETH_FILTER_DELETE:
1940                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1941                                                         vnic0, vnic, &ret);
1942                 if (ret == -EEXIST) {
1943                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1944
1945                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1946                                       next);
1947                         bnxt_free_filter(bp, filter1);
1948                 } else if (ret == 0) {
1949                         PMD_DRV_LOG(ERR, "No matching filter found\n");
1950                 }
1951                 break;
1952         default:
1953                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
1954                 ret = -EINVAL;
1955                 goto error;
1956         }
1957         return ret;
1958 cleanup:
1959         bnxt_free_filter(bp, bfilter);
1960 error:
1961         return ret;
1962 }
1963
1964 static inline int
1965 parse_ntuple_filter(struct bnxt *bp,
1966                     struct rte_eth_ntuple_filter *nfilter,
1967                     struct bnxt_filter_info *bfilter)
1968 {
1969         uint32_t en = 0;
1970
1971         if (nfilter->queue >= bp->rx_nr_rings) {
1972                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
1973                 return -EINVAL;
1974         }
1975
1976         switch (nfilter->dst_port_mask) {
1977         case UINT16_MAX:
1978                 bfilter->dst_port_mask = -1;
1979                 bfilter->dst_port = nfilter->dst_port;
1980                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1981                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1982                 break;
1983         default:
1984                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
1985                 return -EINVAL;
1986         }
1987
1988         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1989         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1990
1991         switch (nfilter->proto_mask) {
1992         case UINT8_MAX:
1993                 if (nfilter->proto == 17) /* IPPROTO_UDP */
1994                         bfilter->ip_protocol = 17;
1995                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1996                         bfilter->ip_protocol = 6;
1997                 else
1998                         return -EINVAL;
1999                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2000                 break;
2001         default:
2002                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2003                 return -EINVAL;
2004         }
2005
2006         switch (nfilter->dst_ip_mask) {
2007         case UINT32_MAX:
2008                 bfilter->dst_ipaddr_mask[0] = -1;
2009                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2010                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2011                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2012                 break;
2013         default:
2014                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2015                 return -EINVAL;
2016         }
2017
2018         switch (nfilter->src_ip_mask) {
2019         case UINT32_MAX:
2020                 bfilter->src_ipaddr_mask[0] = -1;
2021                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2022                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2023                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2024                 break;
2025         default:
2026                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2027                 return -EINVAL;
2028         }
2029
2030         switch (nfilter->src_port_mask) {
2031         case UINT16_MAX:
2032                 bfilter->src_port_mask = -1;
2033                 bfilter->src_port = nfilter->src_port;
2034                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2035                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2036                 break;
2037         default:
2038                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2039                 return -EINVAL;
2040         }
2041
2042         //TODO Priority
2043         //nfilter->priority = (uint8_t)filter->priority;
2044
2045         bfilter->enables = en;
2046         return 0;
2047 }
2048
2049 static struct bnxt_filter_info*
2050 bnxt_match_ntuple_filter(struct bnxt *bp,
2051                          struct bnxt_filter_info *bfilter,
2052                          struct bnxt_vnic_info **mvnic)
2053 {
2054         struct bnxt_filter_info *mfilter = NULL;
2055         int i;
2056
2057         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2058                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2059                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2060                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2061                             bfilter->src_ipaddr_mask[0] ==
2062                             mfilter->src_ipaddr_mask[0] &&
2063                             bfilter->src_port == mfilter->src_port &&
2064                             bfilter->src_port_mask == mfilter->src_port_mask &&
2065                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2066                             bfilter->dst_ipaddr_mask[0] ==
2067                             mfilter->dst_ipaddr_mask[0] &&
2068                             bfilter->dst_port == mfilter->dst_port &&
2069                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2070                             bfilter->flags == mfilter->flags &&
2071                             bfilter->enables == mfilter->enables) {
2072                                 if (mvnic)
2073                                         *mvnic = vnic;
2074                                 return mfilter;
2075                         }
2076                 }
2077         }
2078         return NULL;
2079 }
2080
2081 static int
2082 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2083                        struct rte_eth_ntuple_filter *nfilter,
2084                        enum rte_filter_op filter_op)
2085 {
2086         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2087         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2088         int ret;
2089
2090         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2091                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2092                 return -EINVAL;
2093         }
2094
2095         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2096                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2097                 return -EINVAL;
2098         }
2099
2100         bfilter = bnxt_get_unused_filter(bp);
2101         if (bfilter == NULL) {
2102                 PMD_DRV_LOG(ERR,
2103                         "Not enough resources for a new filter.\n");
2104                 return -ENOMEM;
2105         }
2106         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2107         if (ret < 0)
2108                 goto free_filter;
2109
2110         vnic = &bp->vnic_info[nfilter->queue];
2111         vnic0 = &bp->vnic_info[0];
2112         filter1 = STAILQ_FIRST(&vnic0->filter);
2113         if (filter1 == NULL) {
2114                 ret = -1;
2115                 goto free_filter;
2116         }
2117
2118         bfilter->dst_id = vnic->fw_vnic_id;
2119         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2120         bfilter->enables |=
2121                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2122         bfilter->ethertype = 0x800;
2123         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2124
2125         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2126
2127         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2128             bfilter->dst_id == mfilter->dst_id) {
2129                 PMD_DRV_LOG(ERR, "filter exists.\n");
2130                 ret = -EEXIST;
2131                 goto free_filter;
2132         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2133                    bfilter->dst_id != mfilter->dst_id) {
2134                 mfilter->dst_id = vnic->fw_vnic_id;
2135                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2136                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2137                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2138                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2139                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2140                 goto free_filter;
2141         }
2142         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2143                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2144                 ret = -ENOENT;
2145                 goto free_filter;
2146         }
2147
2148         if (filter_op == RTE_ETH_FILTER_ADD) {
2149                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2150                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2151                 if (ret)
2152                         goto free_filter;
2153                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2154         } else {
2155                 if (mfilter == NULL) {
2156                         /* This should not happen. But for Coverity! */
2157                         ret = -ENOENT;
2158                         goto free_filter;
2159                 }
2160                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2161
2162                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2163                 bnxt_free_filter(bp, mfilter);
2164                 mfilter->fw_l2_filter_id = -1;
2165                 bnxt_free_filter(bp, bfilter);
2166                 bfilter->fw_l2_filter_id = -1;
2167         }
2168
2169         return 0;
2170 free_filter:
2171         bfilter->fw_l2_filter_id = -1;
2172         bnxt_free_filter(bp, bfilter);
2173         return ret;
2174 }
2175
2176 static int
2177 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2178                         enum rte_filter_op filter_op,
2179                         void *arg)
2180 {
2181         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2182         int ret;
2183
2184         if (filter_op == RTE_ETH_FILTER_NOP)
2185                 return 0;
2186
2187         if (arg == NULL) {
2188                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2189                             filter_op);
2190                 return -EINVAL;
2191         }
2192
2193         switch (filter_op) {
2194         case RTE_ETH_FILTER_ADD:
2195                 ret = bnxt_cfg_ntuple_filter(bp,
2196                         (struct rte_eth_ntuple_filter *)arg,
2197                         filter_op);
2198                 break;
2199         case RTE_ETH_FILTER_DELETE:
2200                 ret = bnxt_cfg_ntuple_filter(bp,
2201                         (struct rte_eth_ntuple_filter *)arg,
2202                         filter_op);
2203                 break;
2204         default:
2205                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2206                 ret = -EINVAL;
2207                 break;
2208         }
2209         return ret;
2210 }
2211
2212 static int
2213 bnxt_parse_fdir_filter(struct bnxt *bp,
2214                        struct rte_eth_fdir_filter *fdir,
2215                        struct bnxt_filter_info *filter)
2216 {
2217         enum rte_fdir_mode fdir_mode =
2218                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2219         struct bnxt_vnic_info *vnic0, *vnic;
2220         struct bnxt_filter_info *filter1;
2221         uint32_t en = 0;
2222         int i;
2223
2224         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2225                 return -EINVAL;
2226
2227         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2228         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2229
2230         switch (fdir->input.flow_type) {
2231         case RTE_ETH_FLOW_IPV4:
2232         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2233                 /* FALLTHROUGH */
2234                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2235                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2236                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2237                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2238                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2239                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2240                 filter->ip_addr_type =
2241                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2242                 filter->src_ipaddr_mask[0] = 0xffffffff;
2243                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2244                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2245                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2246                 filter->ethertype = 0x800;
2247                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2248                 break;
2249         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2250                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2251                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2252                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2253                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2254                 filter->dst_port_mask = 0xffff;
2255                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2256                 filter->src_port_mask = 0xffff;
2257                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2258                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2259                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2260                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2261                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2262                 filter->ip_protocol = 6;
2263                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2264                 filter->ip_addr_type =
2265                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2266                 filter->src_ipaddr_mask[0] = 0xffffffff;
2267                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2268                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2269                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2270                 filter->ethertype = 0x800;
2271                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2272                 break;
2273         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2274                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2275                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2276                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2277                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2278                 filter->dst_port_mask = 0xffff;
2279                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2280                 filter->src_port_mask = 0xffff;
2281                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2282                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2283                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2284                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2285                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2286                 filter->ip_protocol = 17;
2287                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2288                 filter->ip_addr_type =
2289                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2290                 filter->src_ipaddr_mask[0] = 0xffffffff;
2291                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2292                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2293                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2294                 filter->ethertype = 0x800;
2295                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2296                 break;
2297         case RTE_ETH_FLOW_IPV6:
2298         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2299                 /* FALLTHROUGH */
2300                 filter->ip_addr_type =
2301                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2302                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2303                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2304                 rte_memcpy(filter->src_ipaddr,
2305                            fdir->input.flow.ipv6_flow.src_ip, 16);
2306                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2307                 rte_memcpy(filter->dst_ipaddr,
2308                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2309                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2310                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2311                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2312                 memset(filter->src_ipaddr_mask, 0xff, 16);
2313                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2314                 filter->ethertype = 0x86dd;
2315                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2316                 break;
2317         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2318                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2319                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2320                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2321                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2322                 filter->dst_port_mask = 0xffff;
2323                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2324                 filter->src_port_mask = 0xffff;
2325                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2326                 filter->ip_addr_type =
2327                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2328                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2329                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2330                 rte_memcpy(filter->src_ipaddr,
2331                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2332                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2333                 rte_memcpy(filter->dst_ipaddr,
2334                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2335                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2336                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2337                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2338                 memset(filter->src_ipaddr_mask, 0xff, 16);
2339                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2340                 filter->ethertype = 0x86dd;
2341                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2342                 break;
2343         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2344                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2345                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2346                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2347                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2348                 filter->dst_port_mask = 0xffff;
2349                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2350                 filter->src_port_mask = 0xffff;
2351                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2352                 filter->ip_addr_type =
2353                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2354                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2355                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2356                 rte_memcpy(filter->src_ipaddr,
2357                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2358                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2359                 rte_memcpy(filter->dst_ipaddr,
2360                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2361                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2362                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2363                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2364                 memset(filter->src_ipaddr_mask, 0xff, 16);
2365                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2366                 filter->ethertype = 0x86dd;
2367                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2368                 break;
2369         case RTE_ETH_FLOW_L2_PAYLOAD:
2370                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2371                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2372                 break;
2373         case RTE_ETH_FLOW_VXLAN:
2374                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2375                         return -EINVAL;
2376                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2377                 filter->tunnel_type =
2378                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2379                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2380                 break;
2381         case RTE_ETH_FLOW_NVGRE:
2382                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2383                         return -EINVAL;
2384                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2385                 filter->tunnel_type =
2386                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2387                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2388                 break;
2389         case RTE_ETH_FLOW_UNKNOWN:
2390         case RTE_ETH_FLOW_RAW:
2391         case RTE_ETH_FLOW_FRAG_IPV4:
2392         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2393         case RTE_ETH_FLOW_FRAG_IPV6:
2394         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2395         case RTE_ETH_FLOW_IPV6_EX:
2396         case RTE_ETH_FLOW_IPV6_TCP_EX:
2397         case RTE_ETH_FLOW_IPV6_UDP_EX:
2398         case RTE_ETH_FLOW_GENEVE:
2399                 /* FALLTHROUGH */
2400         default:
2401                 return -EINVAL;
2402         }
2403
2404         vnic0 = &bp->vnic_info[0];
2405         vnic = &bp->vnic_info[fdir->action.rx_queue];
2406         if (vnic == NULL) {
2407                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2408                 return -EINVAL;
2409         }
2410
2411
2412         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2413                 rte_memcpy(filter->dst_macaddr,
2414                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2415                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2416         }
2417
2418         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2419                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2420                 filter1 = STAILQ_FIRST(&vnic0->filter);
2421                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2422         } else {
2423                 filter->dst_id = vnic->fw_vnic_id;
2424                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2425                         if (filter->dst_macaddr[i] == 0x00)
2426                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2427                         else
2428                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2429         }
2430
2431         if (filter1 == NULL)
2432                 return -EINVAL;
2433
2434         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2435         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2436
2437         filter->enables = en;
2438
2439         return 0;
2440 }
2441
2442 static struct bnxt_filter_info *
2443 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2444                 struct bnxt_vnic_info **mvnic)
2445 {
2446         struct bnxt_filter_info *mf = NULL;
2447         int i;
2448
2449         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2450                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2451
2452                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2453                         if (mf->filter_type == nf->filter_type &&
2454                             mf->flags == nf->flags &&
2455                             mf->src_port == nf->src_port &&
2456                             mf->src_port_mask == nf->src_port_mask &&
2457                             mf->dst_port == nf->dst_port &&
2458                             mf->dst_port_mask == nf->dst_port_mask &&
2459                             mf->ip_protocol == nf->ip_protocol &&
2460                             mf->ip_addr_type == nf->ip_addr_type &&
2461                             mf->ethertype == nf->ethertype &&
2462                             mf->vni == nf->vni &&
2463                             mf->tunnel_type == nf->tunnel_type &&
2464                             mf->l2_ovlan == nf->l2_ovlan &&
2465                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2466                             mf->l2_ivlan == nf->l2_ivlan &&
2467                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2468                             !memcmp(mf->l2_addr, nf->l2_addr,
2469                                     RTE_ETHER_ADDR_LEN) &&
2470                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2471                                     RTE_ETHER_ADDR_LEN) &&
2472                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2473                                     RTE_ETHER_ADDR_LEN) &&
2474                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2475                                     RTE_ETHER_ADDR_LEN) &&
2476                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2477                                     sizeof(nf->src_ipaddr)) &&
2478                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2479                                     sizeof(nf->src_ipaddr_mask)) &&
2480                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2481                                     sizeof(nf->dst_ipaddr)) &&
2482                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2483                                     sizeof(nf->dst_ipaddr_mask))) {
2484                                 if (mvnic)
2485                                         *mvnic = vnic;
2486                                 return mf;
2487                         }
2488                 }
2489         }
2490         return NULL;
2491 }
2492
2493 static int
2494 bnxt_fdir_filter(struct rte_eth_dev *dev,
2495                  enum rte_filter_op filter_op,
2496                  void *arg)
2497 {
2498         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2499         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2500         struct bnxt_filter_info *filter, *match;
2501         struct bnxt_vnic_info *vnic, *mvnic;
2502         int ret = 0, i;
2503
2504         if (filter_op == RTE_ETH_FILTER_NOP)
2505                 return 0;
2506
2507         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2508                 return -EINVAL;
2509
2510         switch (filter_op) {
2511         case RTE_ETH_FILTER_ADD:
2512         case RTE_ETH_FILTER_DELETE:
2513                 /* FALLTHROUGH */
2514                 filter = bnxt_get_unused_filter(bp);
2515                 if (filter == NULL) {
2516                         PMD_DRV_LOG(ERR,
2517                                 "Not enough resources for a new flow.\n");
2518                         return -ENOMEM;
2519                 }
2520
2521                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2522                 if (ret != 0)
2523                         goto free_filter;
2524                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2525
2526                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2527                         vnic = &bp->vnic_info[0];
2528                 else
2529                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2530
2531                 match = bnxt_match_fdir(bp, filter, &mvnic);
2532                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2533                         if (match->dst_id == vnic->fw_vnic_id) {
2534                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2535                                 ret = -EEXIST;
2536                                 goto free_filter;
2537                         } else {
2538                                 match->dst_id = vnic->fw_vnic_id;
2539                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2540                                                                   match->dst_id,
2541                                                                   match);
2542                                 STAILQ_REMOVE(&mvnic->filter, match,
2543                                               bnxt_filter_info, next);
2544                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2545                                 PMD_DRV_LOG(ERR,
2546                                         "Filter with matching pattern exist\n");
2547                                 PMD_DRV_LOG(ERR,
2548                                         "Updated it to new destination q\n");
2549                                 goto free_filter;
2550                         }
2551                 }
2552                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2553                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2554                         ret = -ENOENT;
2555                         goto free_filter;
2556                 }
2557
2558                 if (filter_op == RTE_ETH_FILTER_ADD) {
2559                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2560                                                           filter->dst_id,
2561                                                           filter);
2562                         if (ret)
2563                                 goto free_filter;
2564                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2565                 } else {
2566                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2567                         STAILQ_REMOVE(&vnic->filter, match,
2568                                       bnxt_filter_info, next);
2569                         bnxt_free_filter(bp, match);
2570                         filter->fw_l2_filter_id = -1;
2571                         bnxt_free_filter(bp, filter);
2572                 }
2573                 break;
2574         case RTE_ETH_FILTER_FLUSH:
2575                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2576                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2577
2578                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2579                                 if (filter->filter_type ==
2580                                     HWRM_CFA_NTUPLE_FILTER) {
2581                                         ret =
2582                                         bnxt_hwrm_clear_ntuple_filter(bp,
2583                                                                       filter);
2584                                         STAILQ_REMOVE(&vnic->filter, filter,
2585                                                       bnxt_filter_info, next);
2586                                 }
2587                         }
2588                 }
2589                 return ret;
2590         case RTE_ETH_FILTER_UPDATE:
2591         case RTE_ETH_FILTER_STATS:
2592         case RTE_ETH_FILTER_INFO:
2593                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2594                 break;
2595         default:
2596                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2597                 ret = -EINVAL;
2598                 break;
2599         }
2600         return ret;
2601
2602 free_filter:
2603         filter->fw_l2_filter_id = -1;
2604         bnxt_free_filter(bp, filter);
2605         return ret;
2606 }
2607
2608 static int
2609 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2610                     enum rte_filter_type filter_type,
2611                     enum rte_filter_op filter_op, void *arg)
2612 {
2613         int ret = 0;
2614
2615         switch (filter_type) {
2616         case RTE_ETH_FILTER_TUNNEL:
2617                 PMD_DRV_LOG(ERR,
2618                         "filter type: %d: To be implemented\n", filter_type);
2619                 break;
2620         case RTE_ETH_FILTER_FDIR:
2621                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2622                 break;
2623         case RTE_ETH_FILTER_NTUPLE:
2624                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2625                 break;
2626         case RTE_ETH_FILTER_ETHERTYPE:
2627                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2628                 break;
2629         case RTE_ETH_FILTER_GENERIC:
2630                 if (filter_op != RTE_ETH_FILTER_GET)
2631                         return -EINVAL;
2632                 *(const void **)arg = &bnxt_flow_ops;
2633                 break;
2634         default:
2635                 PMD_DRV_LOG(ERR,
2636                         "Filter type (%d) not supported", filter_type);
2637                 ret = -EINVAL;
2638                 break;
2639         }
2640         return ret;
2641 }
2642
2643 static const uint32_t *
2644 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2645 {
2646         static const uint32_t ptypes[] = {
2647                 RTE_PTYPE_L2_ETHER_VLAN,
2648                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2649                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2650                 RTE_PTYPE_L4_ICMP,
2651                 RTE_PTYPE_L4_TCP,
2652                 RTE_PTYPE_L4_UDP,
2653                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2654                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2655                 RTE_PTYPE_INNER_L4_ICMP,
2656                 RTE_PTYPE_INNER_L4_TCP,
2657                 RTE_PTYPE_INNER_L4_UDP,
2658                 RTE_PTYPE_UNKNOWN
2659         };
2660
2661         if (dev->rx_pkt_burst == bnxt_recv_pkts)
2662                 return ptypes;
2663         return NULL;
2664 }
2665
2666 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2667                          int reg_win)
2668 {
2669         uint32_t reg_base = *reg_arr & 0xfffff000;
2670         uint32_t win_off;
2671         int i;
2672
2673         for (i = 0; i < count; i++) {
2674                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2675                         return -ERANGE;
2676         }
2677         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2678         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2679         return 0;
2680 }
2681
2682 static int bnxt_map_ptp_regs(struct bnxt *bp)
2683 {
2684         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2685         uint32_t *reg_arr;
2686         int rc, i;
2687
2688         reg_arr = ptp->rx_regs;
2689         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2690         if (rc)
2691                 return rc;
2692
2693         reg_arr = ptp->tx_regs;
2694         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2695         if (rc)
2696                 return rc;
2697
2698         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2699                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2700
2701         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2702                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2703
2704         return 0;
2705 }
2706
2707 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2708 {
2709         rte_write32(0, (uint8_t *)bp->bar0 +
2710                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2711         rte_write32(0, (uint8_t *)bp->bar0 +
2712                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2713 }
2714
2715 static uint64_t bnxt_cc_read(struct bnxt *bp)
2716 {
2717         uint64_t ns;
2718
2719         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2720                               BNXT_GRCPF_REG_SYNC_TIME));
2721         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2722                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2723         return ns;
2724 }
2725
2726 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2727 {
2728         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2729         uint32_t fifo;
2730
2731         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2732                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2733         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2734                 return -EAGAIN;
2735
2736         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2737                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2738         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2739                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2740         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2741                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2742
2743         return 0;
2744 }
2745
2746 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2747 {
2748         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2749         struct bnxt_pf_info *pf = &bp->pf;
2750         uint16_t port_id;
2751         uint32_t fifo;
2752
2753         if (!ptp)
2754                 return -ENODEV;
2755
2756         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2757                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2758         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2759                 return -EAGAIN;
2760
2761         port_id = pf->port_id;
2762         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2763                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2764
2765         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2766                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2767         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2768 /*              bnxt_clr_rx_ts(bp);       TBD  */
2769                 return -EBUSY;
2770         }
2771
2772         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2773                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2774         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2775                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2776
2777         return 0;
2778 }
2779
2780 static int
2781 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2782 {
2783         uint64_t ns;
2784         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2785         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2786
2787         if (!ptp)
2788                 return 0;
2789
2790         ns = rte_timespec_to_ns(ts);
2791         /* Set the timecounters to a new value. */
2792         ptp->tc.nsec = ns;
2793
2794         return 0;
2795 }
2796
2797 static int
2798 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2799 {
2800         uint64_t ns, systime_cycles;
2801         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2802         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2803
2804         if (!ptp)
2805                 return 0;
2806
2807         systime_cycles = bnxt_cc_read(bp);
2808         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2809         *ts = rte_ns_to_timespec(ns);
2810
2811         return 0;
2812 }
2813 static int
2814 bnxt_timesync_enable(struct rte_eth_dev *dev)
2815 {
2816         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2817         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2818         uint32_t shift = 0;
2819
2820         if (!ptp)
2821                 return 0;
2822
2823         ptp->rx_filter = 1;
2824         ptp->tx_tstamp_en = 1;
2825         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2826
2827         if (!bnxt_hwrm_ptp_cfg(bp))
2828                 bnxt_map_ptp_regs(bp);
2829
2830         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2831         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2832         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2833
2834         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2835         ptp->tc.cc_shift = shift;
2836         ptp->tc.nsec_mask = (1ULL << shift) - 1;
2837
2838         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2839         ptp->rx_tstamp_tc.cc_shift = shift;
2840         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2841
2842         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2843         ptp->tx_tstamp_tc.cc_shift = shift;
2844         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2845
2846         return 0;
2847 }
2848
2849 static int
2850 bnxt_timesync_disable(struct rte_eth_dev *dev)
2851 {
2852         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2853         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2854
2855         if (!ptp)
2856                 return 0;
2857
2858         ptp->rx_filter = 0;
2859         ptp->tx_tstamp_en = 0;
2860         ptp->rxctl = 0;
2861
2862         bnxt_hwrm_ptp_cfg(bp);
2863
2864         bnxt_unmap_ptp_regs(bp);
2865
2866         return 0;
2867 }
2868
2869 static int
2870 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2871                                  struct timespec *timestamp,
2872                                  uint32_t flags __rte_unused)
2873 {
2874         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2875         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2876         uint64_t rx_tstamp_cycles = 0;
2877         uint64_t ns;
2878
2879         if (!ptp)
2880                 return 0;
2881
2882         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2883         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2884         *timestamp = rte_ns_to_timespec(ns);
2885         return  0;
2886 }
2887
2888 static int
2889 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2890                                  struct timespec *timestamp)
2891 {
2892         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2893         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2894         uint64_t tx_tstamp_cycles = 0;
2895         uint64_t ns;
2896
2897         if (!ptp)
2898                 return 0;
2899
2900         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2901         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2902         *timestamp = rte_ns_to_timespec(ns);
2903
2904         return 0;
2905 }
2906
2907 static int
2908 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2909 {
2910         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2911         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2912
2913         if (!ptp)
2914                 return 0;
2915
2916         ptp->tc.nsec += delta;
2917
2918         return 0;
2919 }
2920
2921 static int
2922 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2923 {
2924         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2925         int rc;
2926         uint32_t dir_entries;
2927         uint32_t entry_length;
2928
2929         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
2930                 bp->pdev->addr.domain, bp->pdev->addr.bus,
2931                 bp->pdev->addr.devid, bp->pdev->addr.function);
2932
2933         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2934         if (rc != 0)
2935                 return rc;
2936
2937         return dir_entries * entry_length;
2938 }
2939
2940 static int
2941 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2942                 struct rte_dev_eeprom_info *in_eeprom)
2943 {
2944         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2945         uint32_t index;
2946         uint32_t offset;
2947
2948         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2949                 "len = %d\n", bp->pdev->addr.domain,
2950                 bp->pdev->addr.bus, bp->pdev->addr.devid,
2951                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2952
2953         if (in_eeprom->offset == 0) /* special offset value to get directory */
2954                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2955                                                 in_eeprom->data);
2956
2957         index = in_eeprom->offset >> 24;
2958         offset = in_eeprom->offset & 0xffffff;
2959
2960         if (index != 0)
2961                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2962                                            in_eeprom->length, in_eeprom->data);
2963
2964         return 0;
2965 }
2966
2967 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2968 {
2969         switch (dir_type) {
2970         case BNX_DIR_TYPE_CHIMP_PATCH:
2971         case BNX_DIR_TYPE_BOOTCODE:
2972         case BNX_DIR_TYPE_BOOTCODE_2:
2973         case BNX_DIR_TYPE_APE_FW:
2974         case BNX_DIR_TYPE_APE_PATCH:
2975         case BNX_DIR_TYPE_KONG_FW:
2976         case BNX_DIR_TYPE_KONG_PATCH:
2977         case BNX_DIR_TYPE_BONO_FW:
2978         case BNX_DIR_TYPE_BONO_PATCH:
2979                 /* FALLTHROUGH */
2980                 return true;
2981         }
2982
2983         return false;
2984 }
2985
2986 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2987 {
2988         switch (dir_type) {
2989         case BNX_DIR_TYPE_AVS:
2990         case BNX_DIR_TYPE_EXP_ROM_MBA:
2991         case BNX_DIR_TYPE_PCIE:
2992         case BNX_DIR_TYPE_TSCF_UCODE:
2993         case BNX_DIR_TYPE_EXT_PHY:
2994         case BNX_DIR_TYPE_CCM:
2995         case BNX_DIR_TYPE_ISCSI_BOOT:
2996         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2997         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2998                 /* FALLTHROUGH */
2999                 return true;
3000         }
3001
3002         return false;
3003 }
3004
3005 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3006 {
3007         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3008                 bnxt_dir_type_is_other_exec_format(dir_type);
3009 }
3010
3011 static int
3012 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3013                 struct rte_dev_eeprom_info *in_eeprom)
3014 {
3015         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3016         uint8_t index, dir_op;
3017         uint16_t type, ext, ordinal, attr;
3018
3019         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3020                 "len = %d\n", bp->pdev->addr.domain,
3021                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3022                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3023
3024         if (!BNXT_PF(bp)) {
3025                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3026                 return -EINVAL;
3027         }
3028
3029         type = in_eeprom->magic >> 16;
3030
3031         if (type == 0xffff) { /* special value for directory operations */
3032                 index = in_eeprom->magic & 0xff;
3033                 dir_op = in_eeprom->magic >> 8;
3034                 if (index == 0)
3035                         return -EINVAL;
3036                 switch (dir_op) {
3037                 case 0x0e: /* erase */
3038                         if (in_eeprom->offset != ~in_eeprom->magic)
3039                                 return -EINVAL;
3040                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3041                 default:
3042                         return -EINVAL;
3043                 }
3044         }
3045
3046         /* Create or re-write an NVM item: */
3047         if (bnxt_dir_type_is_executable(type) == true)
3048                 return -EOPNOTSUPP;
3049         ext = in_eeprom->magic & 0xffff;
3050         ordinal = in_eeprom->offset >> 16;
3051         attr = in_eeprom->offset & 0xffff;
3052
3053         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3054                                      in_eeprom->data, in_eeprom->length);
3055         return 0;
3056 }
3057
3058 /*
3059  * Initialization
3060  */
3061
3062 static const struct eth_dev_ops bnxt_dev_ops = {
3063         .dev_infos_get = bnxt_dev_info_get_op,
3064         .dev_close = bnxt_dev_close_op,
3065         .dev_configure = bnxt_dev_configure_op,
3066         .dev_start = bnxt_dev_start_op,
3067         .dev_stop = bnxt_dev_stop_op,
3068         .dev_set_link_up = bnxt_dev_set_link_up_op,
3069         .dev_set_link_down = bnxt_dev_set_link_down_op,
3070         .stats_get = bnxt_stats_get_op,
3071         .stats_reset = bnxt_stats_reset_op,
3072         .rx_queue_setup = bnxt_rx_queue_setup_op,
3073         .rx_queue_release = bnxt_rx_queue_release_op,
3074         .tx_queue_setup = bnxt_tx_queue_setup_op,
3075         .tx_queue_release = bnxt_tx_queue_release_op,
3076         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3077         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3078         .reta_update = bnxt_reta_update_op,
3079         .reta_query = bnxt_reta_query_op,
3080         .rss_hash_update = bnxt_rss_hash_update_op,
3081         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3082         .link_update = bnxt_link_update_op,
3083         .promiscuous_enable = bnxt_promiscuous_enable_op,
3084         .promiscuous_disable = bnxt_promiscuous_disable_op,
3085         .allmulticast_enable = bnxt_allmulticast_enable_op,
3086         .allmulticast_disable = bnxt_allmulticast_disable_op,
3087         .mac_addr_add = bnxt_mac_addr_add_op,
3088         .mac_addr_remove = bnxt_mac_addr_remove_op,
3089         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3090         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3091         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3092         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3093         .vlan_filter_set = bnxt_vlan_filter_set_op,
3094         .vlan_offload_set = bnxt_vlan_offload_set_op,
3095         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3096         .mtu_set = bnxt_mtu_set_op,
3097         .mac_addr_set = bnxt_set_default_mac_addr_op,
3098         .xstats_get = bnxt_dev_xstats_get_op,
3099         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3100         .xstats_reset = bnxt_dev_xstats_reset_op,
3101         .fw_version_get = bnxt_fw_version_get,
3102         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3103         .rxq_info_get = bnxt_rxq_info_get_op,
3104         .txq_info_get = bnxt_txq_info_get_op,
3105         .dev_led_on = bnxt_dev_led_on_op,
3106         .dev_led_off = bnxt_dev_led_off_op,
3107         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3108         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3109         .rx_queue_count = bnxt_rx_queue_count_op,
3110         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3111         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3112         .rx_queue_start = bnxt_rx_queue_start,
3113         .rx_queue_stop = bnxt_rx_queue_stop,
3114         .tx_queue_start = bnxt_tx_queue_start,
3115         .tx_queue_stop = bnxt_tx_queue_stop,
3116         .filter_ctrl = bnxt_filter_ctrl_op,
3117         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3118         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3119         .get_eeprom           = bnxt_get_eeprom_op,
3120         .set_eeprom           = bnxt_set_eeprom_op,
3121         .timesync_enable      = bnxt_timesync_enable,
3122         .timesync_disable     = bnxt_timesync_disable,
3123         .timesync_read_time   = bnxt_timesync_read_time,
3124         .timesync_write_time   = bnxt_timesync_write_time,
3125         .timesync_adjust_time = bnxt_timesync_adjust_time,
3126         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3127         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3128 };
3129
3130 static bool bnxt_vf_pciid(uint16_t id)
3131 {
3132         if (id == BROADCOM_DEV_ID_57304_VF ||
3133             id == BROADCOM_DEV_ID_57406_VF ||
3134             id == BROADCOM_DEV_ID_5731X_VF ||
3135             id == BROADCOM_DEV_ID_5741X_VF ||
3136             id == BROADCOM_DEV_ID_57414_VF ||
3137             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3138             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3139             id == BROADCOM_DEV_ID_58802_VF)
3140                 return true;
3141         return false;
3142 }
3143
3144 bool bnxt_stratus_device(struct bnxt *bp)
3145 {
3146         uint16_t id = bp->pdev->id.device_id;
3147
3148         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3149             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3150             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3151                 return true;
3152         return false;
3153 }
3154
3155 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3156 {
3157         struct bnxt *bp = eth_dev->data->dev_private;
3158         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3159         int rc;
3160
3161         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3162         if (!pci_dev->mem_resource[0].addr) {
3163                 PMD_DRV_LOG(ERR,
3164                         "Cannot find PCI device base address, aborting\n");
3165                 rc = -ENODEV;
3166                 goto init_err_disable;
3167         }
3168
3169         bp->eth_dev = eth_dev;
3170         bp->pdev = pci_dev;
3171
3172         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3173         if (!bp->bar0) {
3174                 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3175                 rc = -ENOMEM;
3176                 goto init_err_release;
3177         }
3178
3179         if (!pci_dev->mem_resource[2].addr) {
3180                 PMD_DRV_LOG(ERR,
3181                             "Cannot find PCI device BAR 2 address, aborting\n");
3182                 rc = -ENODEV;
3183                 goto init_err_release;
3184         } else {
3185                 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3186         }
3187
3188         return 0;
3189
3190 init_err_release:
3191         if (bp->bar0)
3192                 bp->bar0 = NULL;
3193         if (bp->doorbell_base)
3194                 bp->doorbell_base = NULL;
3195
3196 init_err_disable:
3197
3198         return rc;
3199 }
3200
3201
3202 #define ALLOW_FUNC(x)   \
3203         { \
3204                 typeof(x) arg = (x); \
3205                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3206                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3207         }
3208 static int
3209 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3210 {
3211         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3212         char mz_name[RTE_MEMZONE_NAMESIZE];
3213         const struct rte_memzone *mz = NULL;
3214         static int version_printed;
3215         uint32_t total_alloc_len;
3216         rte_iova_t mz_phys_addr;
3217         struct bnxt *bp;
3218         int rc;
3219
3220         if (version_printed++ == 0)
3221                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3222
3223         rte_eth_copy_pci_info(eth_dev, pci_dev);
3224
3225         bp = eth_dev->data->dev_private;
3226
3227         bp->dev_stopped = 1;
3228
3229         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3230                 goto skip_init;
3231
3232         if (bnxt_vf_pciid(pci_dev->id.device_id))
3233                 bp->flags |= BNXT_FLAG_VF;
3234
3235         rc = bnxt_init_board(eth_dev);
3236         if (rc) {
3237                 PMD_DRV_LOG(ERR,
3238                         "Board initialization failed rc: %x\n", rc);
3239                 goto error;
3240         }
3241 skip_init:
3242         eth_dev->dev_ops = &bnxt_dev_ops;
3243         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3244         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3245         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3246                 return 0;
3247
3248         if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3249                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3250                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3251                          pci_dev->addr.bus, pci_dev->addr.devid,
3252                          pci_dev->addr.function, "rx_port_stats");
3253                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3254                 mz = rte_memzone_lookup(mz_name);
3255                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3256                                         sizeof(struct rx_port_stats) +
3257                                         sizeof(struct rx_port_stats_ext) +
3258                                         512);
3259                 if (!mz) {
3260                         mz = rte_memzone_reserve(mz_name, total_alloc_len,
3261                                         SOCKET_ID_ANY,
3262                                         RTE_MEMZONE_2MB |
3263                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3264                                         RTE_MEMZONE_IOVA_CONTIG);
3265                         if (mz == NULL)
3266                                 return -ENOMEM;
3267                 }
3268                 memset(mz->addr, 0, mz->len);
3269                 mz_phys_addr = mz->iova;
3270                 if ((unsigned long)mz->addr == mz_phys_addr) {
3271                         PMD_DRV_LOG(INFO,
3272                                 "Memzone physical address same as virtual using rte_mem_virt2iova()\n");
3273                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3274                         if (mz_phys_addr == 0) {
3275                                 PMD_DRV_LOG(ERR,
3276                                 "unable to map address to physical memory\n");
3277                                 return -ENOMEM;
3278                         }
3279                 }
3280
3281                 bp->rx_mem_zone = (const void *)mz;
3282                 bp->hw_rx_port_stats = mz->addr;
3283                 bp->hw_rx_port_stats_map = mz_phys_addr;
3284
3285                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3286                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3287                          pci_dev->addr.bus, pci_dev->addr.devid,
3288                          pci_dev->addr.function, "tx_port_stats");
3289                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3290                 mz = rte_memzone_lookup(mz_name);
3291                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3292                                         sizeof(struct tx_port_stats) +
3293                                         sizeof(struct tx_port_stats_ext) +
3294                                         512);
3295                 if (!mz) {
3296                         mz = rte_memzone_reserve(mz_name,
3297                                         total_alloc_len,
3298                                         SOCKET_ID_ANY,
3299                                         RTE_MEMZONE_2MB |
3300                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3301                                         RTE_MEMZONE_IOVA_CONTIG);
3302                         if (mz == NULL)
3303                                 return -ENOMEM;
3304                 }
3305                 memset(mz->addr, 0, mz->len);
3306                 mz_phys_addr = mz->iova;
3307                 if ((unsigned long)mz->addr == mz_phys_addr) {
3308                         PMD_DRV_LOG(WARNING,
3309                                 "Memzone physical address same as virtual.\n");
3310                         PMD_DRV_LOG(WARNING,
3311                                 "Using rte_mem_virt2iova()\n");
3312                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3313                         if (mz_phys_addr == 0) {
3314                                 PMD_DRV_LOG(ERR,
3315                                 "unable to map address to physical memory\n");
3316                                 return -ENOMEM;
3317                         }
3318                 }
3319
3320                 bp->tx_mem_zone = (const void *)mz;
3321                 bp->hw_tx_port_stats = mz->addr;
3322                 bp->hw_tx_port_stats_map = mz_phys_addr;
3323
3324                 bp->flags |= BNXT_FLAG_PORT_STATS;
3325
3326                 /* Display extended statistics if FW supports it */
3327                 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3328                     bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0)
3329                         goto skip_ext_stats;
3330
3331                 bp->hw_rx_port_stats_ext = (void *)
3332                         (bp->hw_rx_port_stats + sizeof(struct rx_port_stats));
3333                 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3334                         sizeof(struct rx_port_stats);
3335                 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3336
3337
3338                 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2) {
3339                         bp->hw_tx_port_stats_ext = (void *)
3340                         (bp->hw_tx_port_stats + sizeof(struct tx_port_stats));
3341                         bp->hw_tx_port_stats_ext_map =
3342                                 bp->hw_tx_port_stats_map +
3343                                 sizeof(struct tx_port_stats);
3344                         bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3345                 }
3346         }
3347
3348 skip_ext_stats:
3349         rc = bnxt_alloc_hwrm_resources(bp);
3350         if (rc) {
3351                 PMD_DRV_LOG(ERR,
3352                         "hwrm resource allocation failure rc: %x\n", rc);
3353                 goto error_free;
3354         }
3355         rc = bnxt_hwrm_ver_get(bp);
3356         if (rc)
3357                 goto error_free;
3358         rc = bnxt_hwrm_queue_qportcfg(bp);
3359         if (rc) {
3360                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3361                 goto error_free;
3362         }
3363
3364         rc = bnxt_hwrm_func_qcfg(bp);
3365         if (rc) {
3366                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3367                 goto error_free;
3368         }
3369
3370         /* Get the MAX capabilities for this function */
3371         rc = bnxt_hwrm_func_qcaps(bp);
3372         if (rc) {
3373                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3374                 goto error_free;
3375         }
3376         if (bp->max_tx_rings == 0) {
3377                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3378                 rc = -EBUSY;
3379                 goto error_free;
3380         }
3381         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3382                                         RTE_ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3383         if (eth_dev->data->mac_addrs == NULL) {
3384                 PMD_DRV_LOG(ERR,
3385                         "Failed to alloc %u bytes needed to store MAC addr tbl",
3386                         RTE_ETHER_ADDR_LEN * bp->max_l2_ctx);
3387                 rc = -ENOMEM;
3388                 goto error_free;
3389         }
3390
3391         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3392                 PMD_DRV_LOG(ERR,
3393                             "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3394                             bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3395                             bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3396                             bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3397                 rc = -EINVAL;
3398                 goto error_free;
3399         }
3400         /* Copy the permanent MAC from the qcap response address now. */
3401         memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3402         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3403
3404         if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3405                 /* 1 ring is for default completion ring */
3406                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3407                 rc = -ENOSPC;
3408                 goto error_free;
3409         }
3410
3411         bp->grp_info = rte_zmalloc("bnxt_grp_info",
3412                                 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3413         if (!bp->grp_info) {
3414                 PMD_DRV_LOG(ERR,
3415                         "Failed to alloc %zu bytes to store group info table\n",
3416                         sizeof(*bp->grp_info) * bp->max_ring_grps);
3417                 rc = -ENOMEM;
3418                 goto error_free;
3419         }
3420
3421         /* Forward all requests if firmware is new enough */
3422         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3423             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3424             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3425                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3426         } else {
3427                 PMD_DRV_LOG(WARNING,
3428                         "Firmware too old for VF mailbox functionality\n");
3429                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3430         }
3431
3432         /*
3433          * The following are used for driver cleanup.  If we disallow these,
3434          * VF drivers can't clean up cleanly.
3435          */
3436         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3437         ALLOW_FUNC(HWRM_VNIC_FREE);
3438         ALLOW_FUNC(HWRM_RING_FREE);
3439         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3440         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3441         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3442         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3443         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3444         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3445         rc = bnxt_hwrm_func_driver_register(bp);
3446         if (rc) {
3447                 PMD_DRV_LOG(ERR,
3448                         "Failed to register driver");
3449                 rc = -EBUSY;
3450                 goto error_free;
3451         }
3452
3453         PMD_DRV_LOG(INFO,
3454                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3455                 pci_dev->mem_resource[0].phys_addr,
3456                 pci_dev->mem_resource[0].addr);
3457
3458         rc = bnxt_hwrm_func_reset(bp);
3459         if (rc) {
3460                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3461                 rc = -EIO;
3462                 goto error_free;
3463         }
3464
3465         if (BNXT_PF(bp)) {
3466                 //if (bp->pf.active_vfs) {
3467                         // TODO: Deallocate VF resources?
3468                 //}
3469                 if (bp->pdev->max_vfs) {
3470                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3471                         if (rc) {
3472                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3473                                 goto error_free;
3474                         }
3475                 } else {
3476                         rc = bnxt_hwrm_allocate_pf_only(bp);
3477                         if (rc) {
3478                                 PMD_DRV_LOG(ERR,
3479                                         "Failed to allocate PF resources\n");
3480                                 goto error_free;
3481                         }
3482                 }
3483         }
3484
3485         bnxt_hwrm_port_led_qcaps(bp);
3486
3487         rc = bnxt_setup_int(bp);
3488         if (rc)
3489                 goto error_free;
3490
3491         rc = bnxt_alloc_mem(bp);
3492         if (rc)
3493                 goto error_free_int;
3494
3495         rc = bnxt_request_int(bp);
3496         if (rc)
3497                 goto error_free_int;
3498
3499         bnxt_enable_int(bp);
3500         bnxt_init_nic(bp);
3501
3502         return 0;
3503
3504 error_free_int:
3505         bnxt_disable_int(bp);
3506         bnxt_hwrm_func_buf_unrgtr(bp);
3507         bnxt_free_int(bp);
3508         bnxt_free_mem(bp);
3509 error_free:
3510         bnxt_dev_uninit(eth_dev);
3511 error:
3512         return rc;
3513 }
3514
3515 static int
3516 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3517 {
3518         struct bnxt *bp = eth_dev->data->dev_private;
3519         int rc;
3520
3521         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3522                 return -EPERM;
3523
3524         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3525         bnxt_disable_int(bp);
3526         bnxt_free_int(bp);
3527         bnxt_free_mem(bp);
3528         if (bp->grp_info != NULL) {
3529                 rte_free(bp->grp_info);
3530                 bp->grp_info = NULL;
3531         }
3532         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3533         bnxt_free_hwrm_resources(bp);
3534
3535         if (bp->tx_mem_zone) {
3536                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3537                 bp->tx_mem_zone = NULL;
3538         }
3539
3540         if (bp->rx_mem_zone) {
3541                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3542                 bp->rx_mem_zone = NULL;
3543         }
3544
3545         if (bp->dev_stopped == 0)
3546                 bnxt_dev_close_op(eth_dev);
3547         if (bp->pf.vf_info)
3548                 rte_free(bp->pf.vf_info);
3549         eth_dev->dev_ops = NULL;
3550         eth_dev->rx_pkt_burst = NULL;
3551         eth_dev->tx_pkt_burst = NULL;
3552
3553         return rc;
3554 }
3555
3556 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3557         struct rte_pci_device *pci_dev)
3558 {
3559         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3560                 bnxt_dev_init);
3561 }
3562
3563 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3564 {
3565         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3566                 return rte_eth_dev_pci_generic_remove(pci_dev,
3567                                 bnxt_dev_uninit);
3568         else
3569                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3570 }
3571
3572 static struct rte_pci_driver bnxt_rte_pmd = {
3573         .id_table = bnxt_pci_id_map,
3574         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3575                 RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_IOVA_AS_VA,
3576         .probe = bnxt_pci_probe,
3577         .remove = bnxt_pci_remove,
3578 };
3579
3580 static bool
3581 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3582 {
3583         if (strcmp(dev->device->driver->name, drv->driver.name))
3584                 return false;
3585
3586         return true;
3587 }
3588
3589 bool is_bnxt_supported(struct rte_eth_dev *dev)
3590 {
3591         return is_device_supported(dev, &bnxt_rte_pmd);
3592 }
3593
3594 RTE_INIT(bnxt_init_log)
3595 {
3596         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
3597         if (bnxt_logtype_driver >= 0)
3598                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
3599 }
3600
3601 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3602 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3603 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");