1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
6 #ifndef _BNXT_FILTER_H_
7 #define _BNXT_FILTER_H_
13 #define BNXT_FLOW_L2_VALID_FLAG BIT(0)
14 #define BNXT_FLOW_L2_SRC_VALID_FLAG BIT(1)
15 #define BNXT_FLOW_L2_INNER_SRC_VALID_FLAG BIT(2)
16 #define BNXT_FLOW_L2_DST_VALID_FLAG BIT(3)
17 #define BNXT_FLOW_L2_INNER_DST_VALID_FLAG BIT(4)
19 struct bnxt_filter_info {
20 STAILQ_ENTRY(bnxt_filter_info) next;
21 uint64_t fw_l2_filter_id;
22 struct bnxt_filter_info *matching_l2_fltr_ptr;
23 uint64_t fw_em_filter_id;
24 uint64_t fw_ntuple_filter_id;
25 #define INVALID_MAC_INDEX ((uint16_t)-1)
27 #define HWRM_CFA_L2_FILTER 0
28 #define HWRM_CFA_EM_FILTER 1
29 #define HWRM_CFA_NTUPLE_FILTER 2
30 #define HWRM_CFA_TUNNEL_REDIRECT_FILTER 3
34 /* Filter Characteristics */
38 uint8_t l2_addr[RTE_ETHER_ADDR_LEN];
39 uint8_t l2_addr_mask[RTE_ETHER_ADDR_LEN];
42 uint16_t l2_ovlan_mask;
44 uint16_t l2_ivlan_mask;
45 uint8_t t_l2_addr[RTE_ETHER_ADDR_LEN];
46 uint8_t t_l2_addr_mask[RTE_ETHER_ADDR_LEN];
48 uint16_t t_l2_ovlan_mask;
50 uint16_t t_l2_ivlan_mask;
52 uint16_t mirror_vnic_id;
55 uint64_t l2_filter_id_hint;
58 uint8_t src_macaddr[6];
59 uint8_t dst_macaddr[6];
60 uint32_t dst_ipaddr[4];
61 uint32_t dst_ipaddr_mask[4];
62 uint32_t src_ipaddr[4];
63 uint32_t src_ipaddr_mask[4];
65 uint16_t dst_port_mask;
67 uint16_t src_port_mask;
69 uint16_t ip_addr_type;
74 struct bnxt_filter_info *bnxt_alloc_filter(struct bnxt *bp);
75 struct bnxt_filter_info *bnxt_alloc_vf_filter(struct bnxt *bp, uint16_t vf);
76 void bnxt_init_filters(struct bnxt *bp);
77 void bnxt_free_all_filters(struct bnxt *bp);
78 void bnxt_free_filter_mem(struct bnxt *bp);
79 int bnxt_alloc_filter_mem(struct bnxt *bp);
80 struct bnxt_filter_info *bnxt_get_unused_filter(struct bnxt *bp);
81 void bnxt_free_filter(struct bnxt *bp, struct bnxt_filter_info *filter);
82 struct bnxt_filter_info *bnxt_get_l2_filter(struct bnxt *bp,
83 struct bnxt_filter_info *nf, struct bnxt_vnic_info *vnic);
85 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_MACADDR \
86 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR
87 #define EM_FLOW_ALLOC_INPUT_EN_SRC_MACADDR \
88 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR
89 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR \
90 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR
91 #define EM_FLOW_ALLOC_INPUT_EN_DST_MACADDR \
92 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR
93 #define NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE \
94 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE
95 #define EM_FLOW_ALLOC_INPUT_EN_ETHERTYPE \
96 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE
97 #define EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID \
98 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID
99 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR \
100 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR
101 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK \
102 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK
103 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR \
104 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR
105 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK \
106 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK
107 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT \
108 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT
109 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK \
110 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK
111 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT \
112 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT
113 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK \
114 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK
115 #define NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO \
116 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL
117 #define EM_FLOW_ALLOC_INPUT_EN_SRC_IPADDR \
118 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR
119 #define EM_FLOW_ALLOC_INPUT_EN_DST_IPADDR \
120 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR
121 #define EM_FLOW_ALLOC_INPUT_EN_SRC_PORT \
122 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT
123 #define EM_FLOW_ALLOC_INPUT_EN_DST_PORT \
124 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT
125 #define EM_FLOW_ALLOC_INPUT_EN_IP_PROTO \
126 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL
127 #define EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
128 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
129 #define NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
130 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
131 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN \
132 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN
133 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE \
134 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE
135 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE \
136 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE
137 #define L2_FILTER_ALLOC_INPUT_EN_L2_ADDR_MASK \
138 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK
139 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_UDP \
140 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
141 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_TCP \
142 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP
143 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
144 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN
145 #define NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
146 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4
147 #define NTUPLE_FLTR_ALLOC_INPUT_EN_MIRROR_VNIC_ID \
148 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID
149 #define NTUPLE_FLTR_ALLOC_INPUT_EN_MIRROR_VNIC_ID \
150 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID