drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         /* For VER_GET command, set timeout as 50ms */
 104         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 105                 timeout = HWRM_CMD_TIMEOUT;
 106         else
 107                 timeout = bp->hwrm_cmd_timeout;
 108
 109         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 110             msg_len > bp->max_req_len) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 127         }
 128
 129         /* Write request msg to hwrm channel */
 130         for (i = 0; i < msg_len; i += 4) {
 131                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 132                 rte_write32(*data, bar);
 133                 data++;
 134         }
 135
 136         /* Zero the rest of the request space */
 137         for (; i < max_req_len; i += 4) {
 138                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 139                 rte_write32(0, bar);
 140         }
 141
 142         /* Ring channel doorbell */
 143         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 144         rte_write32(1, bar);
 145         /*
 146          * Make sure the channel doorbell ring command complete before
 147          * reading the response to avoid getting stale or invalid
 148          * responses.
 149          */
 150         rte_io_mb();
 151
 152         /* Poll for the valid bit */
 153         for (i = 0; i < timeout; i++) {
 154                 /* Sanity check on the resp->resp_len */
 155                 rte_cio_rmb();
 156                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 157                         /* Last byte of resp contains the valid key */
 158                         valid = (uint8_t *)resp + resp->resp_len - 1;
 159                         if (*valid == HWRM_RESP_VALID_KEY)
 160                                 break;
 161                 }
 162                 rte_delay_us(1);
 163         }
 164
 165         if (i >= timeout) {
 166                 /* Suppress VER_GET timeout messages during reset recovery */
 167                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 168                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 169                         return -ETIMEDOUT;
 170
 171                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 172                             req->req_type);
 173                 return -ETIMEDOUT;
 174         }
 175         return 0;
 176 }
 177
 178 /*
 179  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 180  * spinlock, and does initial processing.
 181  *
 182  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 183  * releases the spinlock only if it returns. If the regular int return codes
 184  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 185  * directly, rather it should be copied and modified to suit the function.
 186  *
 187  * HWRM_UNLOCK() must be called after all response processing is completed.
 188  */
 189 #define HWRM_PREP(req, type, kong) do { \
 190         rte_spinlock_lock(&bp->hwrm_lock); \
 191         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 192         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 193         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 194         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 195                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 196         req.target_id = rte_cpu_to_le_16(0xffff); \
 197         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 198 } while (0)
 199
 200 #define HWRM_CHECK_RESULT_SILENT() do {\
 201         if (rc) { \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 return rc; \
 204         } \
 205         if (resp->error_code) { \
 206                 rc = rte_le_to_cpu_16(resp->error_code); \
 207                 rte_spinlock_unlock(&bp->hwrm_lock); \
 208                 return rc; \
 209         } \
 210 } while (0)
 211
 212 #define HWRM_CHECK_RESULT() do {\
 213         if (rc) { \
 214                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 215                 rte_spinlock_unlock(&bp->hwrm_lock); \
 216                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 217                         rc = -EACCES; \
 218                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 219                         rc = -ENOSPC; \
 220                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 221                         rc = -EINVAL; \
 222                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 223                         rc = -ENOTSUP; \
 224                 else if (rc > 0) \
 225                         rc = -EIO; \
 226                 return rc; \
 227         } \
 228         if (resp->error_code) { \
 229                 rc = rte_le_to_cpu_16(resp->error_code); \
 230                 if (resp->resp_len >= 16) { \
 231                         struct hwrm_err_output *tmp_hwrm_err_op = \
 232                                                 (void *)resp; \
 233                         PMD_DRV_LOG(ERR, \
 234                                 "error %d:%d:%08x:%04x\n", \
 235                                 rc, tmp_hwrm_err_op->cmd_err, \
 236                                 rte_le_to_cpu_32(\
 237                                         tmp_hwrm_err_op->opaque_0), \
 238                                 rte_le_to_cpu_16(\
 239                                         tmp_hwrm_err_op->opaque_1)); \
 240                 } else { \
 241                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 242                 } \
 243                 rte_spinlock_unlock(&bp->hwrm_lock); \
 244                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 245                         rc = -EACCES; \
 246                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 247                         rc = -ENOSPC; \
 248                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 249                         rc = -EINVAL; \
 250                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 251                         rc = -ENOTSUP; \
 252                 else if (rc > 0) \
 253                         rc = -EIO; \
 254                 return rc; \
 255         } \
 256 } while (0)
 257
 258 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 259
 260 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 261 {
 262         int rc = 0;
 263         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 264         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268         req.mask = 0;
 269
 270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 271
 272         HWRM_CHECK_RESULT();
 273         HWRM_UNLOCK();
 274
 275         return rc;
 276 }
 277
 278 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 279                                  struct bnxt_vnic_info *vnic,
 280                                  uint16_t vlan_count,
 281                                  struct bnxt_vlan_table_entry *vlan_table)
 282 {
 283         int rc = 0;
 284         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 285         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 286         uint32_t mask = 0;
 287
 288         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 289                 return rc;
 290
 291         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 292         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 293
 294         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 295                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 296         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 297                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 298
 299         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 300                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 301
 302         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 303                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 304         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 305                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 306                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 307                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 308         }
 309         if (vlan_table) {
 310                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 311                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 312                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 313                          rte_mem_virt2iova(vlan_table));
 314                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 315         }
 316         req.mask = rte_cpu_to_le_32(mask);
 317
 318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 319
 320         HWRM_CHECK_RESULT();
 321         HWRM_UNLOCK();
 322
 323         return rc;
 324 }
 325
 326 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 327                         uint16_t vlan_count,
 328                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 329 {
 330         int rc = 0;
 331         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 332         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 333                                                 bp->hwrm_cmd_resp_addr;
 334
 335         /*
 336          * Older HWRM versions did not support this command, and the set_rx_mask
 337          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 338          * removed from set_rx_mask call, and this command was added.
 339          *
 340          * This command is also present from 1.7.8.11 and higher,
 341          * as well as 1.7.8.0
 342          */
 343         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 344                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 345                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 346                                         (11)))
 347                                 return 0;
 348                 }
 349         }
 350         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 351         req.fid = rte_cpu_to_le_16(fid);
 352
 353         req.vlan_tag_mask_tbl_addr =
 354                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 355         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         return rc;
 363 }
 364
 365 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 366                            struct bnxt_filter_info *filter)
 367 {
 368         int rc = 0;
 369         struct bnxt_filter_info *l2_filter = filter;
 370         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 371         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 372
 373         if (filter->fw_l2_filter_id == UINT64_MAX)
 374                 return 0;
 375
 376         if (filter->matching_l2_fltr_ptr)
 377                 l2_filter = filter->matching_l2_fltr_ptr;
 378
 379         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 380                     filter, l2_filter, l2_filter->l2_ref_cnt);
 381
 382         if (l2_filter->l2_ref_cnt > 0)
 383                 l2_filter->l2_ref_cnt--;
 384
 385         if (l2_filter->l2_ref_cnt > 0)
 386                 return 0;
 387
 388         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 389
 390         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 391
 392         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 393
 394         HWRM_CHECK_RESULT();
 395         HWRM_UNLOCK();
 396
 397         filter->fw_l2_filter_id = UINT64_MAX;
 398
 399         return 0;
 400 }
 401
 402 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 403                          uint16_t dst_id,
 404                          struct bnxt_filter_info *filter)
 405 {
 406         int rc = 0;
 407         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 408         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 409         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 410         const struct rte_eth_vmdq_rx_conf *conf =
 411                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 412         uint32_t enables = 0;
 413         uint16_t j = dst_id - 1;
 414
 415         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 416         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 417             conf->pool_map[j].pools & (1UL << j)) {
 418                 PMD_DRV_LOG(DEBUG,
 419                         "Add vlan %u to vmdq pool %u\n",
 420                         conf->pool_map[j].vlan_id, j);
 421
 422                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 423                 filter->enables |=
 424                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 425                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 426         }
 427
 428         if (filter->fw_l2_filter_id != UINT64_MAX)
 429                 bnxt_hwrm_clear_l2_filter(bp, filter);
 430
 431         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 432
 433         req.flags = rte_cpu_to_le_32(filter->flags);
 434
 435         enables = filter->enables |
 436               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 437         req.dst_id = rte_cpu_to_le_16(dst_id);
 438
 439         if (enables &
 440             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 441                 memcpy(req.l2_addr, filter->l2_addr,
 442                        RTE_ETHER_ADDR_LEN);
 443         if (enables &
 444             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 445                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 446                        RTE_ETHER_ADDR_LEN);
 447         if (enables &
 448             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 449                 req.l2_ovlan = filter->l2_ovlan;
 450         if (enables &
 451             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 452                 req.l2_ivlan = filter->l2_ivlan;
 453         if (enables &
 454             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 455                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 456         if (enables &
 457             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 458                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 459         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 460                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 461         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 462                 req.src_type = filter->src_type;
 463         if (filter->pri_hint) {
 464                 req.pri_hint = filter->pri_hint;
 465                 req.l2_filter_id_hint =
 466                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 467         }
 468
 469         req.enables = rte_cpu_to_le_32(enables);
 470
 471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 472
 473         HWRM_CHECK_RESULT();
 474
 475         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 482 {
 483         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 484         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 485         uint32_t flags = 0;
 486         int rc;
 487
 488         if (!ptp)
 489                 return 0;
 490
 491         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 492
 493         if (ptp->rx_filter)
 494                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 495         else
 496                 flags |=
 497                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 498         if (ptp->tx_tstamp_en)
 499                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 500         else
 501                 flags |=
 502                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 503         req.flags = rte_cpu_to_le_32(flags);
 504         req.enables = rte_cpu_to_le_32
 505                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 506         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 507
 508         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 509         HWRM_UNLOCK();
 510
 511         return rc;
 512 }
 513
 514 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 515 {
 516         int rc = 0;
 517         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 518         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 519         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 520
 521         if (ptp)
 522                 return 0;
 523
 524         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 525
 526         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 527
 528         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 529
 530         HWRM_CHECK_RESULT();
 531
 532         if (!BNXT_CHIP_THOR(bp) &&
 533             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 534                 return 0;
 535
 536         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 537                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 538
 539         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 540         if (!ptp)
 541                 return -ENOMEM;
 542
 543         if (!BNXT_CHIP_THOR(bp)) {
 544                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 545                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 546                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 547                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 548                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 549                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 550                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 551                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 552                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 553                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 554                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 555                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 556                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 557                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 558                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 559                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 560                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 561                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 562         }
 563
 564         ptp->bp = bp;
 565         bp->ptp_cfg = ptp;
 566
 567         return 0;
 568 }
 569
 570 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 571 {
 572         int rc = 0;
 573         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 574         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 575         uint16_t new_max_vfs;
 576         uint32_t flags;
 577         int i;
 578
 579         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 580
 581         req.fid = rte_cpu_to_le_16(0xffff);
 582
 583         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 584
 585         HWRM_CHECK_RESULT();
 586
 587         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 588         flags = rte_le_to_cpu_32(resp->flags);
 589         if (BNXT_PF(bp)) {
 590                 bp->pf.port_id = resp->port_id;
 591                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 592                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 593                 new_max_vfs = bp->pdev->max_vfs;
 594                 if (new_max_vfs != bp->pf.max_vfs) {
 595                         if (bp->pf.vf_info)
 596                                 rte_free(bp->pf.vf_info);
 597                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 598                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 599                         bp->pf.max_vfs = new_max_vfs;
 600                         for (i = 0; i < new_max_vfs; i++) {
 601                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 602                                 bp->pf.vf_info[i].vlan_table =
 603                                         rte_zmalloc("VF VLAN table",
 604                                                     getpagesize(),
 605                                                     getpagesize());
 606                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 607                                         PMD_DRV_LOG(ERR,
 608                                         "Fail to alloc VLAN table for VF %d\n",
 609                                         i);
 610                                 else
 611                                         rte_mem_lock_page(
 612                                                 bp->pf.vf_info[i].vlan_table);
 613                                 bp->pf.vf_info[i].vlan_as_table =
 614                                         rte_zmalloc("VF VLAN AS table",
 615                                                     getpagesize(),
 616                                                     getpagesize());
 617                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 618                                         PMD_DRV_LOG(ERR,
 619                                         "Alloc VLAN AS table for VF %d fail\n",
 620                                         i);
 621                                 else
 622                                         rte_mem_lock_page(
 623                                                bp->pf.vf_info[i].vlan_as_table);
 624                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 625                         }
 626                 }
 627         }
 628
 629         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 630         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 631         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 632         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 633         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 634         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 635         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 636         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 637         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 638         if (!BNXT_CHIP_THOR(bp))
 639                 bp->max_l2_ctx += bp->max_rx_em_flows;
 640         /* TODO: For now, do not support VMDq/RFS on VFs. */
 641         if (BNXT_PF(bp)) {
 642                 if (bp->pf.max_vfs)
 643                         bp->max_vnics = 1;
 644                 else
 645                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 646         } else {
 647                 bp->max_vnics = 1;
 648         }
 649         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 650         if (BNXT_PF(bp)) {
 651                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 652                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 653                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 654                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 655                         HWRM_UNLOCK();
 656                         bnxt_hwrm_ptp_qcfg(bp);
 657                 }
 658         }
 659
 660         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 661                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 662
 663         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 664                 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 665                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 666         } else {
 667                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 668         }
 669
 670         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 671                 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 672         else
 673                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 674
 675         HWRM_UNLOCK();
 676
 677         return rc;
 678 }
 679
 680 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 681 {
 682         int rc;
 683
 684         rc = __bnxt_hwrm_func_qcaps(bp);
 685         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 686                 rc = bnxt_alloc_ctx_mem(bp);
 687                 if (rc)
 688                         return rc;
 689
 690                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 691                 if (!rc)
 692                         bp->flags |= BNXT_FLAG_NEW_RM;
 693         }
 694
 695         return rc;
 696 }
 697
 698 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 699 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 700 {
 701         int rc = 0;
 702         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 703         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 704
 705         HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 706
 707         req.target_id = rte_cpu_to_le_16(0xffff);
 708
 709         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 710
 711         HWRM_CHECK_RESULT();
 712
 713         if (rte_le_to_cpu_32(resp->flags) &
 714             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 715                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 716                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 717         }
 718
 719         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 720
 721         HWRM_UNLOCK();
 722
 723         return rc;
 724 }
 725
 726 int bnxt_hwrm_func_reset(struct bnxt *bp)
 727 {
 728         int rc = 0;
 729         struct hwrm_func_reset_input req = {.req_type = 0 };
 730         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 731
 732         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 733
 734         req.enables = rte_cpu_to_le_32(0);
 735
 736         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 737
 738         HWRM_CHECK_RESULT();
 739         HWRM_UNLOCK();
 740
 741         return rc;
 742 }
 743
 744 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 745 {
 746         int rc;
 747         uint32_t flags = 0;
 748         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 749         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 750
 751         if (bp->flags & BNXT_FLAG_REGISTERED)
 752                 return 0;
 753
 754         flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 755         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 756                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 757
 758         /* PFs and trusted VFs should indicate the support of the
 759          * Master capability on non Stingray platform
 760          */
 761         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 762                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 763
 764         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 765         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 766                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 767         req.ver_maj = RTE_VER_YEAR;
 768         req.ver_min = RTE_VER_MONTH;
 769         req.ver_upd = RTE_VER_MINOR;
 770
 771         if (BNXT_PF(bp)) {
 772                 req.enables |= rte_cpu_to_le_32(
 773                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 774                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 775                        RTE_MIN(sizeof(req.vf_req_fwd),
 776                                sizeof(bp->pf.vf_req_fwd)));
 777
 778                 /*
 779                  * PF can sniff HWRM API issued by VF. This can be set up by
 780                  * linux driver and inherited by the DPDK PF driver. Clear
 781                  * this HWRM sniffer list in FW because DPDK PF driver does
 782                  * not support this.
 783                  */
 784                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 785         }
 786
 787         req.flags = rte_cpu_to_le_32(flags);
 788
 789         req.async_event_fwd[0] |=
 790                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 791                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 792                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 793                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 794                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 795         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 796                 req.async_event_fwd[0] |=
 797                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 798         req.async_event_fwd[1] |=
 799                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 800                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 801
 802         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 803
 804         HWRM_CHECK_RESULT();
 805
 806         flags = rte_le_to_cpu_32(resp->flags);
 807         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 808                 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
 809
 810         HWRM_UNLOCK();
 811
 812         bp->flags |= BNXT_FLAG_REGISTERED;
 813
 814         return rc;
 815 }
 816
 817 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 818 {
 819         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 820                 return 0;
 821
 822         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 823 }
 824
 825 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 826 {
 827         int rc;
 828         uint32_t flags = 0;
 829         uint32_t enables;
 830         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 831         struct hwrm_func_vf_cfg_input req = {0};
 832
 833         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 834
 835         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 836                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 837                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 838                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 839                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 840
 841         if (BNXT_HAS_RING_GRPS(bp)) {
 842                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 843                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 844         }
 845
 846         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 847         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 848                                             AGG_RING_MULTIPLIER);
 849         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 850         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 851                                               bp->tx_nr_rings +
 852                                               BNXT_NUM_ASYNC_CPR(bp));
 853         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 854         if (bp->vf_resv_strategy ==
 855             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 856                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 857                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 858                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 859                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 860                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 861                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 862         }
 863
 864         if (test)
 865                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 866                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 867                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 868                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 869                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 870                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 871
 872         if (test && BNXT_HAS_RING_GRPS(bp))
 873                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 874
 875         req.flags = rte_cpu_to_le_32(flags);
 876         req.enables |= rte_cpu_to_le_32(enables);
 877
 878         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 879
 880         if (test)
 881                 HWRM_CHECK_RESULT_SILENT();
 882         else
 883                 HWRM_CHECK_RESULT();
 884
 885         HWRM_UNLOCK();
 886         return rc;
 887 }
 888
 889 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 890 {
 891         int rc;
 892         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 893         struct hwrm_func_resource_qcaps_input req = {0};
 894
 895         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 896         req.fid = rte_cpu_to_le_16(0xffff);
 897
 898         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 899
 900         HWRM_CHECK_RESULT();
 901
 902         if (BNXT_VF(bp)) {
 903                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 904                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 905                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 906                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 907                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 908                 /* func_resource_qcaps does not return max_rx_em_flows.
 909                  * So use the value provided by func_qcaps.
 910                  */
 911                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 912                 if (!BNXT_CHIP_THOR(bp))
 913                         bp->max_l2_ctx += bp->max_rx_em_flows;
 914                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 915                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 916         }
 917         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 918         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 919         if (bp->vf_resv_strategy >
 920             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 921                 bp->vf_resv_strategy =
 922                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 923
 924         HWRM_UNLOCK();
 925         return rc;
 926 }
 927
 928 int bnxt_hwrm_ver_get(struct bnxt *bp)
 929 {
 930         int rc = 0;
 931         struct hwrm_ver_get_input req = {.req_type = 0 };
 932         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 933         uint32_t fw_version;
 934         uint16_t max_resp_len;
 935         char type[RTE_MEMZONE_NAMESIZE];
 936         uint32_t dev_caps_cfg;
 937
 938         bp->max_req_len = HWRM_MAX_REQ_LEN;
 939         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 940
 941         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 942         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 943         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 944
 945         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 946
 947         if (bp->flags & BNXT_FLAG_FW_RESET)
 948                 HWRM_CHECK_RESULT_SILENT();
 949         else
 950                 HWRM_CHECK_RESULT();
 951
 952         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 953                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 954                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 955                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 956         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 957                      (resp->hwrm_fw_min_8b << 16) |
 958                      (resp->hwrm_fw_bld_8b << 8) |
 959                      resp->hwrm_fw_rsvd_8b;
 960         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 961                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 962
 963         fw_version = resp->hwrm_intf_maj_8b << 16;
 964         fw_version |= resp->hwrm_intf_min_8b << 8;
 965         fw_version |= resp->hwrm_intf_upd_8b;
 966         bp->hwrm_spec_code = fw_version;
 967
 968         /* def_req_timeout value is in milliseconds */
 969         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
 970         /* convert timeout to usec */
 971         bp->hwrm_cmd_timeout *= 1000;
 972         if (!bp->hwrm_cmd_timeout)
 973                 bp->hwrm_cmd_timeout = HWRM_CMD_TIMEOUT;
 974
 975         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 976                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 977                 rc = -EINVAL;
 978                 goto error;
 979         }
 980
 981         if (bp->max_req_len > resp->max_req_win_len) {
 982                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 983                 rc = -EINVAL;
 984         }
 985         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 986         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 987         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 988                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 989
 990         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 991         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 992
 993         if (bp->max_resp_len != max_resp_len) {
 994                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 995                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 996                         bp->pdev->addr.devid, bp->pdev->addr.function);
 997
 998                 rte_free(bp->hwrm_cmd_resp_addr);
 999
1000                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1001                 if (bp->hwrm_cmd_resp_addr == NULL) {
1002                         rc = -ENOMEM;
1003                         goto error;
1004                 }
1005                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1006                 bp->hwrm_cmd_resp_dma_addr =
1007                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1008                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1009                         PMD_DRV_LOG(ERR,
1010                         "Unable to map response buffer to physical memory.\n");
1011                         rc = -ENOMEM;
1012                         goto error;
1013                 }
1014                 bp->max_resp_len = max_resp_len;
1015         }
1016
1017         if ((dev_caps_cfg &
1018                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1019             (dev_caps_cfg &
1020              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1021                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1022                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1023         }
1024
1025         if (((dev_caps_cfg &
1026               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1027              (dev_caps_cfg &
1028               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1029             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1030                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1031                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1032                         bp->pdev->addr.devid, bp->pdev->addr.function);
1033
1034                 rte_free(bp->hwrm_short_cmd_req_addr);
1035
1036                 bp->hwrm_short_cmd_req_addr =
1037                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1038                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1039                         rc = -ENOMEM;
1040                         goto error;
1041                 }
1042                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1043                 bp->hwrm_short_cmd_req_dma_addr =
1044                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1045                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1046                         rte_free(bp->hwrm_short_cmd_req_addr);
1047                         PMD_DRV_LOG(ERR,
1048                                 "Unable to map buffer to physical memory.\n");
1049                         rc = -ENOMEM;
1050                         goto error;
1051                 }
1052         }
1053         if (dev_caps_cfg &
1054             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1055                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1056                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1057         }
1058         if (dev_caps_cfg &
1059             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1060                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1061         if (dev_caps_cfg &
1062             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1063                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1064                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1065         }
1066
1067 error:
1068         HWRM_UNLOCK();
1069         return rc;
1070 }
1071
1072 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1073 {
1074         int rc;
1075         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1076         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1077
1078         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1079                 return 0;
1080
1081         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1082         req.flags = flags;
1083
1084         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1085
1086         HWRM_CHECK_RESULT();
1087         HWRM_UNLOCK();
1088
1089         return rc;
1090 }
1091
1092 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1093 {
1094         int rc = 0;
1095         struct hwrm_port_phy_cfg_input req = {0};
1096         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1097         uint32_t enables = 0;
1098
1099         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1100
1101         if (conf->link_up) {
1102                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1103                 if (bp->link_info.auto_mode && conf->link_speed) {
1104                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1105                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1106                 }
1107
1108                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1109                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1110                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1111                 /*
1112                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1113                  * any auto mode, even "none".
1114                  */
1115                 if (!conf->link_speed) {
1116                         /* No speeds specified. Enable AutoNeg - all speeds */
1117                         req.auto_mode =
1118                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1119                 }
1120                 /* AutoNeg - Advertise speeds specified. */
1121                 if (conf->auto_link_speed_mask &&
1122                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1123                         req.auto_mode =
1124                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1125                         req.auto_link_speed_mask =
1126                                 conf->auto_link_speed_mask;
1127                         enables |=
1128                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1129                 }
1130
1131                 req.auto_duplex = conf->duplex;
1132                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1133                 req.auto_pause = conf->auto_pause;
1134                 req.force_pause = conf->force_pause;
1135                 /* Set force_pause if there is no auto or if there is a force */
1136                 if (req.auto_pause && !req.force_pause)
1137                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1138                 else
1139                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1140
1141                 req.enables = rte_cpu_to_le_32(enables);
1142         } else {
1143                 req.flags =
1144                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1145                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1146         }
1147
1148         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1149
1150         HWRM_CHECK_RESULT();
1151         HWRM_UNLOCK();
1152
1153         return rc;
1154 }
1155
1156 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1157                                    struct bnxt_link_info *link_info)
1158 {
1159         int rc = 0;
1160         struct hwrm_port_phy_qcfg_input req = {0};
1161         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1162
1163         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1164
1165         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1166
1167         HWRM_CHECK_RESULT();
1168
1169         link_info->phy_link_status = resp->link;
1170         link_info->link_up =
1171                 (link_info->phy_link_status ==
1172                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1173         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1174         link_info->duplex = resp->duplex_cfg;
1175         link_info->pause = resp->pause;
1176         link_info->auto_pause = resp->auto_pause;
1177         link_info->force_pause = resp->force_pause;
1178         link_info->auto_mode = resp->auto_mode;
1179         link_info->phy_type = resp->phy_type;
1180         link_info->media_type = resp->media_type;
1181
1182         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1183         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1184         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1185         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1186         link_info->phy_ver[0] = resp->phy_maj;
1187         link_info->phy_ver[1] = resp->phy_min;
1188         link_info->phy_ver[2] = resp->phy_bld;
1189
1190         HWRM_UNLOCK();
1191
1192         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1193         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1194         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1195         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1196         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1197                     link_info->auto_link_speed_mask);
1198         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1199                     link_info->force_link_speed);
1200
1201         return rc;
1202 }
1203
1204 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1205 {
1206         int rc = 0;
1207         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1208         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1209         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1210         int i;
1211
1212 get_rx_info:
1213         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1214
1215         req.flags = rte_cpu_to_le_32(dir);
1216         /* HWRM Version >= 1.9.1 */
1217         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1218                 req.drv_qmap_cap =
1219                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1220         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1221
1222         HWRM_CHECK_RESULT();
1223
1224         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1225                 GET_TX_QUEUE_INFO(0);
1226                 GET_TX_QUEUE_INFO(1);
1227                 GET_TX_QUEUE_INFO(2);
1228                 GET_TX_QUEUE_INFO(3);
1229                 GET_TX_QUEUE_INFO(4);
1230                 GET_TX_QUEUE_INFO(5);
1231                 GET_TX_QUEUE_INFO(6);
1232                 GET_TX_QUEUE_INFO(7);
1233         } else  {
1234                 GET_RX_QUEUE_INFO(0);
1235                 GET_RX_QUEUE_INFO(1);
1236                 GET_RX_QUEUE_INFO(2);
1237                 GET_RX_QUEUE_INFO(3);
1238                 GET_RX_QUEUE_INFO(4);
1239                 GET_RX_QUEUE_INFO(5);
1240                 GET_RX_QUEUE_INFO(6);
1241                 GET_RX_QUEUE_INFO(7);
1242         }
1243
1244         HWRM_UNLOCK();
1245
1246         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1247                 goto done;
1248
1249         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1250                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1251         } else {
1252                 int j;
1253
1254                 /* iterate and find the COSq profile to use for Tx */
1255                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1256                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1257                                 if (bp->tx_cos_queue[i].id != 0xff)
1258                                         bp->tx_cosq_id[j++] =
1259                                                 bp->tx_cos_queue[i].id;
1260                         }
1261                 } else {
1262                         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1263                                 if (bp->tx_cos_queue[i].profile ==
1264                                         HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1265                                         bp->tx_cosq_id[0] =
1266                                                 bp->tx_cos_queue[i].id;
1267                                         break;
1268                                 }
1269                         }
1270                 }
1271         }
1272
1273         bp->max_tc = resp->max_configurable_queues;
1274         bp->max_lltc = resp->max_configurable_lossless_queues;
1275         if (bp->max_tc > BNXT_MAX_QUEUE)
1276                 bp->max_tc = BNXT_MAX_QUEUE;
1277         bp->max_q = bp->max_tc;
1278
1279         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1280                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1281                 goto get_rx_info;
1282         }
1283
1284 done:
1285         return rc;
1286 }
1287
1288 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1289                          struct bnxt_ring *ring,
1290                          uint32_t ring_type, uint32_t map_index,
1291                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1292                          uint16_t tx_cosq_id)
1293 {
1294         int rc = 0;
1295         uint32_t enables = 0;
1296         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1297         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1298         struct rte_mempool *mb_pool;
1299         uint16_t rx_buf_size;
1300
1301         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1302
1303         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1304         req.fbo = rte_cpu_to_le_32(0);
1305         /* Association of ring index with doorbell index */
1306         req.logical_id = rte_cpu_to_le_16(map_index);
1307         req.length = rte_cpu_to_le_32(ring->ring_size);
1308
1309         switch (ring_type) {
1310         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1311                 req.ring_type = ring_type;
1312                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1313                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1314                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1315                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1316                         enables |=
1317                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1318                 break;
1319         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1320                 req.ring_type = ring_type;
1321                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1322                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1323                 if (BNXT_CHIP_THOR(bp)) {
1324                         mb_pool = bp->rx_queues[0]->mb_pool;
1325                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1326                                       RTE_PKTMBUF_HEADROOM;
1327                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1328                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1329                         enables |=
1330                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1331                 }
1332                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1333                         enables |=
1334                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1335                 break;
1336         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1337                 req.ring_type = ring_type;
1338                 if (BNXT_HAS_NQ(bp)) {
1339                         /* Association of cp ring with nq */
1340                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1341                         enables |=
1342                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1343                 }
1344                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1345                 break;
1346         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1347                 req.ring_type = ring_type;
1348                 req.page_size = BNXT_PAGE_SHFT;
1349                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1350                 break;
1351         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1352                 req.ring_type = ring_type;
1353                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1354
1355                 mb_pool = bp->rx_queues[0]->mb_pool;
1356                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1357                               RTE_PKTMBUF_HEADROOM;
1358                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1359                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1360
1361                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1362                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1363                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1364                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1365                 break;
1366         default:
1367                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1368                         ring_type);
1369                 HWRM_UNLOCK();
1370                 return -EINVAL;
1371         }
1372         req.enables = rte_cpu_to_le_32(enables);
1373
1374         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1375
1376         if (rc || resp->error_code) {
1377                 if (rc == 0 && resp->error_code)
1378                         rc = rte_le_to_cpu_16(resp->error_code);
1379                 switch (ring_type) {
1380                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1381                         PMD_DRV_LOG(ERR,
1382                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1383                         HWRM_UNLOCK();
1384                         return rc;
1385                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1386                         PMD_DRV_LOG(ERR,
1387                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1388                         HWRM_UNLOCK();
1389                         return rc;
1390                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1391                         PMD_DRV_LOG(ERR,
1392                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1393                                     rc);
1394                         HWRM_UNLOCK();
1395                         return rc;
1396                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1397                         PMD_DRV_LOG(ERR,
1398                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1399                         HWRM_UNLOCK();
1400                         return rc;
1401                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1402                         PMD_DRV_LOG(ERR,
1403                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1404                         HWRM_UNLOCK();
1405                         return rc;
1406                 default:
1407                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1408                         HWRM_UNLOCK();
1409                         return rc;
1410                 }
1411         }
1412
1413         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1414         HWRM_UNLOCK();
1415         return rc;
1416 }
1417
1418 int bnxt_hwrm_ring_free(struct bnxt *bp,
1419                         struct bnxt_ring *ring, uint32_t ring_type)
1420 {
1421         int rc;
1422         struct hwrm_ring_free_input req = {.req_type = 0 };
1423         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1424
1425         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1426
1427         req.ring_type = ring_type;
1428         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1429
1430         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1431
1432         if (rc || resp->error_code) {
1433                 if (rc == 0 && resp->error_code)
1434                         rc = rte_le_to_cpu_16(resp->error_code);
1435                 HWRM_UNLOCK();
1436
1437                 switch (ring_type) {
1438                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1439                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1440                                 rc);
1441                         return rc;
1442                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1443                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1444                                 rc);
1445                         return rc;
1446                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1447                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1448                                 rc);
1449                         return rc;
1450                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1451                         PMD_DRV_LOG(ERR,
1452                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1453                         return rc;
1454                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1455                         PMD_DRV_LOG(ERR,
1456                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1457                         return rc;
1458                 default:
1459                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1460                         return rc;
1461                 }
1462         }
1463         HWRM_UNLOCK();
1464         return 0;
1465 }
1466
1467 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1468 {
1469         int rc = 0;
1470         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1471         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1472
1473         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1474
1475         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1476         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1477         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1478         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1479
1480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1481
1482         HWRM_CHECK_RESULT();
1483
1484         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1485
1486         HWRM_UNLOCK();
1487
1488         return rc;
1489 }
1490
1491 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1492 {
1493         int rc;
1494         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1495         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1496
1497         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1498
1499         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1500
1501         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1502
1503         HWRM_CHECK_RESULT();
1504         HWRM_UNLOCK();
1505
1506         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1507         return rc;
1508 }
1509
1510 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1511 {
1512         int rc = 0;
1513         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1514         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1515
1516         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1517                 return rc;
1518
1519         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1520
1521         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1522
1523         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1524
1525         HWRM_CHECK_RESULT();
1526         HWRM_UNLOCK();
1527
1528         return rc;
1529 }
1530
1531 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1532                                 unsigned int idx __rte_unused)
1533 {
1534         int rc;
1535         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1536         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1537
1538         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1539
1540         req.update_period_ms = rte_cpu_to_le_32(0);
1541
1542         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1543
1544         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1545
1546         HWRM_CHECK_RESULT();
1547
1548         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1549
1550         HWRM_UNLOCK();
1551
1552         return rc;
1553 }
1554
1555 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1556                                 unsigned int idx __rte_unused)
1557 {
1558         int rc;
1559         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1560         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1561
1562         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1563
1564         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1565
1566         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1567
1568         HWRM_CHECK_RESULT();
1569         HWRM_UNLOCK();
1570
1571         return rc;
1572 }
1573
1574 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1575 {
1576         int rc = 0, i, j;
1577         struct hwrm_vnic_alloc_input req = { 0 };
1578         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1579
1580         if (!BNXT_HAS_RING_GRPS(bp))
1581                 goto skip_ring_grps;
1582
1583         /* map ring groups to this vnic */
1584         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1585                 vnic->start_grp_id, vnic->end_grp_id);
1586         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1587                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1588
1589         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1590         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1591         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1592         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1593
1594 skip_ring_grps:
1595         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1596         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1597
1598         if (vnic->func_default)
1599                 req.flags =
1600                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1601         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1602
1603         HWRM_CHECK_RESULT();
1604
1605         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1606         HWRM_UNLOCK();
1607         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1608         return rc;
1609 }
1610
1611 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1612                                         struct bnxt_vnic_info *vnic,
1613                                         struct bnxt_plcmodes_cfg *pmode)
1614 {
1615         int rc = 0;
1616         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1617         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1618
1619         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1620
1621         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1622
1623         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1624
1625         HWRM_CHECK_RESULT();
1626
1627         pmode->flags = rte_le_to_cpu_32(resp->flags);
1628         /* dflt_vnic bit doesn't exist in the _cfg command */
1629         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1630         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1631         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1632         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1633
1634         HWRM_UNLOCK();
1635
1636         return rc;
1637 }
1638
1639 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1640                                        struct bnxt_vnic_info *vnic,
1641                                        struct bnxt_plcmodes_cfg *pmode)
1642 {
1643         int rc = 0;
1644         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1645         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1646
1647         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1648                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1649                 return rc;
1650         }
1651
1652         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1653
1654         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1655         req.flags = rte_cpu_to_le_32(pmode->flags);
1656         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1657         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1658         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1659         req.enables = rte_cpu_to_le_32(
1660             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1661             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1662             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1663         );
1664
1665         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1666
1667         HWRM_CHECK_RESULT();
1668         HWRM_UNLOCK();
1669
1670         return rc;
1671 }
1672
1673 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1674 {
1675         int rc = 0;
1676         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1677         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1678         struct bnxt_plcmodes_cfg pmodes = { 0 };
1679         uint32_t ctx_enable_flag = 0;
1680         uint32_t enables = 0;
1681
1682         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1683                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1684                 return rc;
1685         }
1686
1687         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1688         if (rc)
1689                 return rc;
1690
1691         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1692
1693         if (BNXT_CHIP_THOR(bp)) {
1694                 struct bnxt_rx_queue *rxq =
1695                         bp->eth_dev->data->rx_queues[vnic->start_grp_id];
1696                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1697                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1698
1699                 req.default_rx_ring_id =
1700                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1701                 req.default_cmpl_ring_id =
1702                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1703                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1704                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1705                 goto config_mru;
1706         }
1707
1708         /* Only RSS support for now TBD: COS & LB */
1709         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1710         if (vnic->lb_rule != 0xffff)
1711                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1712         if (vnic->cos_rule != 0xffff)
1713                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1714         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1715                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1716                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1717         }
1718         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1719                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1720                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1721         }
1722
1723         enables |= ctx_enable_flag;
1724         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1725         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1726         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1727         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1728
1729 config_mru:
1730         req.enables = rte_cpu_to_le_32(enables);
1731         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1732         req.mru = rte_cpu_to_le_16(vnic->mru);
1733         /* Configure default VNIC only once. */
1734         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1735                 req.flags |=
1736                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1737                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1738         }
1739         if (vnic->vlan_strip)
1740                 req.flags |=
1741                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1742         if (vnic->bd_stall)
1743                 req.flags |=
1744                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1745         if (vnic->roce_dual)
1746                 req.flags |= rte_cpu_to_le_32(
1747                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1748         if (vnic->roce_only)
1749                 req.flags |= rte_cpu_to_le_32(
1750                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1751         if (vnic->rss_dflt_cr)
1752                 req.flags |= rte_cpu_to_le_32(
1753                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1754
1755         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1756
1757         HWRM_CHECK_RESULT();
1758         HWRM_UNLOCK();
1759
1760         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1761
1762         return rc;
1763 }
1764
1765 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1766                 int16_t fw_vf_id)
1767 {
1768         int rc = 0;
1769         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1770         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1771
1772         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1773                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1774                 return rc;
1775         }
1776         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1777
1778         req.enables =
1779                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1780         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1781         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1782
1783         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1784
1785         HWRM_CHECK_RESULT();
1786
1787         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1788         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1789         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1790         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1791         vnic->mru = rte_le_to_cpu_16(resp->mru);
1792         vnic->func_default = rte_le_to_cpu_32(
1793                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1794         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1795                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1796         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1797                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1798         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1799                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1800         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1801                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1802         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1803                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1804
1805         HWRM_UNLOCK();
1806
1807         return rc;
1808 }
1809
1810 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1811                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1812 {
1813         int rc = 0;
1814         uint16_t ctx_id;
1815         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1816         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1817                                                 bp->hwrm_cmd_resp_addr;
1818
1819         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1820
1821         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1822         HWRM_CHECK_RESULT();
1823
1824         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1825         if (!BNXT_HAS_RING_GRPS(bp))
1826                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1827         else if (ctx_idx == 0)
1828                 vnic->rss_rule = ctx_id;
1829
1830         HWRM_UNLOCK();
1831
1832         return rc;
1833 }
1834
1835 static
1836 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1837                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1838 {
1839         int rc = 0;
1840         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1841         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1842                                                 bp->hwrm_cmd_resp_addr;
1843
1844         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1845                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1846                 return rc;
1847         }
1848         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1849
1850         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1851
1852         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1853
1854         HWRM_CHECK_RESULT();
1855         HWRM_UNLOCK();
1856
1857         return rc;
1858 }
1859
1860 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1861 {
1862         int rc = 0;
1863
1864         if (BNXT_CHIP_THOR(bp)) {
1865                 int j;
1866
1867                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1868                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1869                                                       vnic,
1870                                                       vnic->fw_grp_ids[j]);
1871                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1872                 }
1873                 vnic->num_lb_ctxts = 0;
1874         } else {
1875                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1876                 vnic->rss_rule = INVALID_HW_RING_ID;
1877         }
1878
1879         return rc;
1880 }
1881
1882 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1883 {
1884         int rc = 0;
1885         struct hwrm_vnic_free_input req = {.req_type = 0 };
1886         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1887
1888         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1889                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1890                 return rc;
1891         }
1892
1893         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1894
1895         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1896
1897         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1898
1899         HWRM_CHECK_RESULT();
1900         HWRM_UNLOCK();
1901
1902         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1903         /* Configure default VNIC again if necessary. */
1904         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1905                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1906
1907         return rc;
1908 }
1909
1910 static int
1911 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1912 {
1913         int i;
1914         int rc = 0;
1915         int nr_ctxs = vnic->num_lb_ctxts;
1916         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1917         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1918
1919         for (i = 0; i < nr_ctxs; i++) {
1920                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1921
1922                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1923                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1924                 req.hash_mode_flags = vnic->hash_mode;
1925
1926                 req.hash_key_tbl_addr =
1927                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1928
1929                 req.ring_grp_tbl_addr =
1930                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1931                                          i * HW_HASH_INDEX_SIZE);
1932                 req.ring_table_pair_index = i;
1933                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1934
1935                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1936                                             BNXT_USE_CHIMP_MB);
1937
1938                 HWRM_CHECK_RESULT();
1939                 HWRM_UNLOCK();
1940         }
1941
1942         return rc;
1943 }
1944
1945 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1946                            struct bnxt_vnic_info *vnic)
1947 {
1948         int rc = 0;
1949         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1950         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1951
1952         if (!vnic->rss_table)
1953                 return 0;
1954
1955         if (BNXT_CHIP_THOR(bp))
1956                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1957
1958         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1959
1960         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1961         req.hash_mode_flags = vnic->hash_mode;
1962
1963         req.ring_grp_tbl_addr =
1964             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1965         req.hash_key_tbl_addr =
1966             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1967         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1968         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1969
1970         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1971
1972         HWRM_CHECK_RESULT();
1973         HWRM_UNLOCK();
1974
1975         return rc;
1976 }
1977
1978 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1979                         struct bnxt_vnic_info *vnic)
1980 {
1981         int rc = 0;
1982         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1983         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1984         uint16_t size;
1985
1986         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1987                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1988                 return rc;
1989         }
1990
1991         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1992
1993         req.flags = rte_cpu_to_le_32(
1994                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1995
1996         req.enables = rte_cpu_to_le_32(
1997                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1998
1999         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2000         size -= RTE_PKTMBUF_HEADROOM;
2001         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2002
2003         req.jumbo_thresh = rte_cpu_to_le_16(size);
2004         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2005
2006         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2007
2008         HWRM_CHECK_RESULT();
2009         HWRM_UNLOCK();
2010
2011         return rc;
2012 }
2013
2014 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2015                         struct bnxt_vnic_info *vnic, bool enable)
2016 {
2017         int rc = 0;
2018         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2019         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2020
2021         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2022                 if (enable)
2023                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2024                 return -ENOTSUP;
2025         }
2026
2027         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2028                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2029                 return 0;
2030         }
2031
2032         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2033
2034         if (enable) {
2035                 req.enables = rte_cpu_to_le_32(
2036                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2037                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2038                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2039                 req.flags = rte_cpu_to_le_32(
2040                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2041                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2042                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2043                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2044                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2045                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2046                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2047                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2048                 req.min_agg_len = rte_cpu_to_le_32(512);
2049         }
2050         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2051
2052         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2053
2054         HWRM_CHECK_RESULT();
2055         HWRM_UNLOCK();
2056
2057         return rc;
2058 }
2059
2060 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2061 {
2062         struct hwrm_func_cfg_input req = {0};
2063         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2064         int rc;
2065
2066         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2067         req.enables = rte_cpu_to_le_32(
2068                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2069         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2070         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2071
2072         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2073
2074         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2075         HWRM_CHECK_RESULT();
2076         HWRM_UNLOCK();
2077
2078         bp->pf.vf_info[vf].random_mac = false;
2079
2080         return rc;
2081 }
2082
2083 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2084                                   uint64_t *dropped)
2085 {
2086         int rc = 0;
2087         struct hwrm_func_qstats_input req = {.req_type = 0};
2088         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2089
2090         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2091
2092         req.fid = rte_cpu_to_le_16(fid);
2093
2094         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2095
2096         HWRM_CHECK_RESULT();
2097
2098         if (dropped)
2099                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2100
2101         HWRM_UNLOCK();
2102
2103         return rc;
2104 }
2105
2106 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2107                           struct rte_eth_stats *stats)
2108 {
2109         int rc = 0;
2110         struct hwrm_func_qstats_input req = {.req_type = 0};
2111         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2112
2113         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2114
2115         req.fid = rte_cpu_to_le_16(fid);
2116
2117         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2118
2119         HWRM_CHECK_RESULT();
2120
2121         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2122         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2123         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2124         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2125         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2126         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2127
2128         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2129         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2130         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2131         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2132         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2133         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2134
2135         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2136         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2137         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2138
2139         HWRM_UNLOCK();
2140
2141         return rc;
2142 }
2143
2144 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2145 {
2146         int rc = 0;
2147         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2148         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2149
2150         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2151
2152         req.fid = rte_cpu_to_le_16(fid);
2153
2154         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2155
2156         HWRM_CHECK_RESULT();
2157         HWRM_UNLOCK();
2158
2159         return rc;
2160 }
2161
2162 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2163 {
2164         unsigned int i;
2165         int rc = 0;
2166
2167         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2168                 struct bnxt_tx_queue *txq;
2169                 struct bnxt_rx_queue *rxq;
2170                 struct bnxt_cp_ring_info *cpr;
2171
2172                 if (i >= bp->rx_cp_nr_rings) {
2173                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2174                         cpr = txq->cp_ring;
2175                 } else {
2176                         rxq = bp->rx_queues[i];
2177                         cpr = rxq->cp_ring;
2178                 }
2179
2180                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2181                 if (rc)
2182                         return rc;
2183         }
2184         return 0;
2185 }
2186
2187 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2188 {
2189         int rc;
2190         unsigned int i;
2191         struct bnxt_cp_ring_info *cpr;
2192
2193         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2194
2195                 if (i >= bp->rx_cp_nr_rings) {
2196                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2197                 } else {
2198                         cpr = bp->rx_queues[i]->cp_ring;
2199                         if (BNXT_HAS_RING_GRPS(bp))
2200                                 bp->grp_info[i].fw_stats_ctx = -1;
2201                 }
2202                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2203                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2204                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2205                         if (rc)
2206                                 return rc;
2207                 }
2208         }
2209         return 0;
2210 }
2211
2212 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2213 {
2214         unsigned int i;
2215         int rc = 0;
2216
2217         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2218                 struct bnxt_tx_queue *txq;
2219                 struct bnxt_rx_queue *rxq;
2220                 struct bnxt_cp_ring_info *cpr;
2221
2222                 if (i >= bp->rx_cp_nr_rings) {
2223                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2224                         cpr = txq->cp_ring;
2225                 } else {
2226                         rxq = bp->rx_queues[i];
2227                         cpr = rxq->cp_ring;
2228                 }
2229
2230                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2231
2232                 if (rc)
2233                         return rc;
2234         }
2235         return rc;
2236 }
2237
2238 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2239 {
2240         uint16_t idx;
2241         uint32_t rc = 0;
2242
2243         if (!BNXT_HAS_RING_GRPS(bp))
2244                 return 0;
2245
2246         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2247
2248                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2249                         continue;
2250
2251                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2252
2253                 if (rc)
2254                         return rc;
2255         }
2256         return rc;
2257 }
2258
2259 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2260 {
2261         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2262
2263         bnxt_hwrm_ring_free(bp, cp_ring,
2264                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2265         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2266         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2267                                      sizeof(*cpr->cp_desc_ring));
2268         cpr->cp_raw_cons = 0;
2269         cpr->valid = 0;
2270 }
2271
2272 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2273 {
2274         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2275
2276         bnxt_hwrm_ring_free(bp, cp_ring,
2277                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2278         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2279         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2280                         sizeof(*cpr->cp_desc_ring));
2281         cpr->cp_raw_cons = 0;
2282         cpr->valid = 0;
2283 }
2284
2285 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2286 {
2287         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2288         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2289         struct bnxt_ring *ring = rxr->rx_ring_struct;
2290         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2291
2292         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2293                 bnxt_hwrm_ring_free(bp, ring,
2294                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2295                 ring->fw_ring_id = INVALID_HW_RING_ID;
2296                 if (BNXT_HAS_RING_GRPS(bp))
2297                         bp->grp_info[queue_index].rx_fw_ring_id =
2298                                                         INVALID_HW_RING_ID;
2299                 memset(rxr->rx_desc_ring, 0,
2300                        rxr->rx_ring_struct->ring_size *
2301                        sizeof(*rxr->rx_desc_ring));
2302                 memset(rxr->rx_buf_ring, 0,
2303                        rxr->rx_ring_struct->ring_size *
2304                        sizeof(*rxr->rx_buf_ring));
2305                 rxr->rx_prod = 0;
2306         }
2307         ring = rxr->ag_ring_struct;
2308         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2309                 bnxt_hwrm_ring_free(bp, ring,
2310                                     BNXT_CHIP_THOR(bp) ?
2311                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2312                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2313                 ring->fw_ring_id = INVALID_HW_RING_ID;
2314                 memset(rxr->ag_buf_ring, 0,
2315                        rxr->ag_ring_struct->ring_size *
2316                        sizeof(*rxr->ag_buf_ring));
2317                 rxr->ag_prod = 0;
2318                 if (BNXT_HAS_RING_GRPS(bp))
2319                         bp->grp_info[queue_index].ag_fw_ring_id =
2320                                                         INVALID_HW_RING_ID;
2321         }
2322         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2323                 bnxt_free_cp_ring(bp, cpr);
2324
2325         if (BNXT_HAS_RING_GRPS(bp))
2326                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2327 }
2328
2329 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2330 {
2331         unsigned int i;
2332
2333         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2334                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2335                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2336                 struct bnxt_ring *ring = txr->tx_ring_struct;
2337                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2338
2339                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2340                         bnxt_hwrm_ring_free(bp, ring,
2341                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2342                         ring->fw_ring_id = INVALID_HW_RING_ID;
2343                         memset(txr->tx_desc_ring, 0,
2344                                         txr->tx_ring_struct->ring_size *
2345                                         sizeof(*txr->tx_desc_ring));
2346                         memset(txr->tx_buf_ring, 0,
2347                                         txr->tx_ring_struct->ring_size *
2348                                         sizeof(*txr->tx_buf_ring));
2349                         txr->tx_prod = 0;
2350                         txr->tx_cons = 0;
2351                 }
2352                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2353                         bnxt_free_cp_ring(bp, cpr);
2354                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2355                 }
2356         }
2357
2358         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2359                 bnxt_free_hwrm_rx_ring(bp, i);
2360
2361         return 0;
2362 }
2363
2364 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2365 {
2366         uint16_t i;
2367         uint32_t rc = 0;
2368
2369         if (!BNXT_HAS_RING_GRPS(bp))
2370                 return 0;
2371
2372         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2373                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2374                 if (rc)
2375                         return rc;
2376         }
2377         return rc;
2378 }
2379
2380 /*
2381  * HWRM utility functions
2382  */
2383
2384 void bnxt_free_hwrm_resources(struct bnxt *bp)
2385 {
2386         /* Release memzone */
2387         rte_free(bp->hwrm_cmd_resp_addr);
2388         rte_free(bp->hwrm_short_cmd_req_addr);
2389         bp->hwrm_cmd_resp_addr = NULL;
2390         bp->hwrm_short_cmd_req_addr = NULL;
2391         bp->hwrm_cmd_resp_dma_addr = 0;
2392         bp->hwrm_short_cmd_req_dma_addr = 0;
2393 }
2394
2395 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2396 {
2397         struct rte_pci_device *pdev = bp->pdev;
2398         char type[RTE_MEMZONE_NAMESIZE];
2399
2400         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2401                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2402         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2403         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2404         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2405         if (bp->hwrm_cmd_resp_addr == NULL)
2406                 return -ENOMEM;
2407         bp->hwrm_cmd_resp_dma_addr =
2408                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2409         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2410                 PMD_DRV_LOG(ERR,
2411                         "unable to map response address to physical memory\n");
2412                 return -ENOMEM;
2413         }
2414         rte_spinlock_init(&bp->hwrm_lock);
2415
2416         return 0;
2417 }
2418
2419 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2420 {
2421         struct bnxt_filter_info *filter;
2422         int rc = 0;
2423
2424         STAILQ_FOREACH(filter, &vnic->filter, next) {
2425                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2426                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2427                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2428                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2429                 else
2430                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2431                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2432                 bnxt_free_filter(bp, filter);
2433         }
2434         return rc;
2435 }
2436
2437 static int
2438 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2439 {
2440         struct bnxt_filter_info *filter;
2441         struct rte_flow *flow;
2442         int rc = 0;
2443
2444         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2445                 flow = STAILQ_FIRST(&vnic->flow_list);
2446                 filter = flow->filter;
2447                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2448                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2449                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2450                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2451                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2452                 else
2453                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2454
2455                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2456                 rte_free(flow);
2457         }
2458         return rc;
2459 }
2460
2461 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2462 {
2463         struct bnxt_filter_info *filter;
2464         int rc = 0;
2465
2466         STAILQ_FOREACH(filter, &vnic->filter, next) {
2467                 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2468                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2469                                                      filter);
2470                 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2471                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2472                                                          filter);
2473                 } else {
2474                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2475                                                      filter);
2476                         if (!rc)
2477                                 filter->dflt = 1;
2478                 }
2479                 if (rc)
2480                         break;
2481         }
2482         return rc;
2483 }
2484
2485 void bnxt_free_tunnel_ports(struct bnxt *bp)
2486 {
2487         if (bp->vxlan_port_cnt)
2488                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2489                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2490         bp->vxlan_port = 0;
2491         if (bp->geneve_port_cnt)
2492                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2493                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2494         bp->geneve_port = 0;
2495 }
2496
2497 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2498 {
2499         int i;
2500
2501         if (bp->vnic_info == NULL)
2502                 return;
2503
2504         /*
2505          * Cleanup VNICs in reverse order, to make sure the L2 filter
2506          * from vnic0 is last to be cleaned up.
2507          */
2508         for (i = bp->max_vnics - 1; i >= 0; i--) {
2509                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2510
2511                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2512                         continue;
2513
2514                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2515
2516                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2517
2518                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2519
2520                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2521
2522                 bnxt_hwrm_vnic_free(bp, vnic);
2523
2524                 rte_free(vnic->fw_grp_ids);
2525         }
2526         /* Ring resources */
2527         bnxt_free_all_hwrm_rings(bp);
2528         bnxt_free_all_hwrm_ring_grps(bp);
2529         bnxt_free_all_hwrm_stat_ctxs(bp);
2530         bnxt_free_tunnel_ports(bp);
2531 }
2532
2533 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2534 {
2535         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2536
2537         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2538                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2539
2540         switch (conf_link_speed) {
2541         case ETH_LINK_SPEED_10M_HD:
2542         case ETH_LINK_SPEED_100M_HD:
2543                 /* FALLTHROUGH */
2544                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2545         }
2546         return hw_link_duplex;
2547 }
2548
2549 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2550 {
2551         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2552 }
2553
2554 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2555 {
2556         uint16_t eth_link_speed = 0;
2557
2558         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2559                 return ETH_LINK_SPEED_AUTONEG;
2560
2561         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2562         case ETH_LINK_SPEED_100M:
2563         case ETH_LINK_SPEED_100M_HD:
2564                 /* FALLTHROUGH */
2565                 eth_link_speed =
2566                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2567                 break;
2568         case ETH_LINK_SPEED_1G:
2569                 eth_link_speed =
2570                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2571                 break;
2572         case ETH_LINK_SPEED_2_5G:
2573                 eth_link_speed =
2574                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2575                 break;
2576         case ETH_LINK_SPEED_10G:
2577                 eth_link_speed =
2578                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2579                 break;
2580         case ETH_LINK_SPEED_20G:
2581                 eth_link_speed =
2582                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2583                 break;
2584         case ETH_LINK_SPEED_25G:
2585                 eth_link_speed =
2586                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2587                 break;
2588         case ETH_LINK_SPEED_40G:
2589                 eth_link_speed =
2590                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2591                 break;
2592         case ETH_LINK_SPEED_50G:
2593                 eth_link_speed =
2594                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2595                 break;
2596         case ETH_LINK_SPEED_100G:
2597                 eth_link_speed =
2598                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2599                 break;
2600         default:
2601                 PMD_DRV_LOG(ERR,
2602                         "Unsupported link speed %d; default to AUTO\n",
2603                         conf_link_speed);
2604                 break;
2605         }
2606         return eth_link_speed;
2607 }
2608
2609 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2610                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2611                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2612                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2613
2614 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2615 {
2616         uint32_t one_speed;
2617
2618         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2619                 return 0;
2620
2621         if (link_speed & ETH_LINK_SPEED_FIXED) {
2622                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2623
2624                 if (one_speed & (one_speed - 1)) {
2625                         PMD_DRV_LOG(ERR,
2626                                 "Invalid advertised speeds (%u) for port %u\n",
2627                                 link_speed, port_id);
2628                         return -EINVAL;
2629                 }
2630                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2631                         PMD_DRV_LOG(ERR,
2632                                 "Unsupported advertised speed (%u) for port %u\n",
2633                                 link_speed, port_id);
2634                         return -EINVAL;
2635                 }
2636         } else {
2637                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2638                         PMD_DRV_LOG(ERR,
2639                                 "Unsupported advertised speeds (%u) for port %u\n",
2640                                 link_speed, port_id);
2641                         return -EINVAL;
2642                 }
2643         }
2644         return 0;
2645 }
2646
2647 static uint16_t
2648 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2649 {
2650         uint16_t ret = 0;
2651
2652         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2653                 if (bp->link_info.support_speeds)
2654                         return bp->link_info.support_speeds;
2655                 link_speed = BNXT_SUPPORTED_SPEEDS;
2656         }
2657
2658         if (link_speed & ETH_LINK_SPEED_100M)
2659                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2660         if (link_speed & ETH_LINK_SPEED_100M_HD)
2661                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2662         if (link_speed & ETH_LINK_SPEED_1G)
2663                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2664         if (link_speed & ETH_LINK_SPEED_2_5G)
2665                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2666         if (link_speed & ETH_LINK_SPEED_10G)
2667                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2668         if (link_speed & ETH_LINK_SPEED_20G)
2669                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2670         if (link_speed & ETH_LINK_SPEED_25G)
2671                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2672         if (link_speed & ETH_LINK_SPEED_40G)
2673                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2674         if (link_speed & ETH_LINK_SPEED_50G)
2675                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2676         if (link_speed & ETH_LINK_SPEED_100G)
2677                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2678         return ret;
2679 }
2680
2681 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2682 {
2683         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2684
2685         switch (hw_link_speed) {
2686         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2687                 eth_link_speed = ETH_SPEED_NUM_100M;
2688                 break;
2689         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2690                 eth_link_speed = ETH_SPEED_NUM_1G;
2691                 break;
2692         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2693                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2694                 break;
2695         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2696                 eth_link_speed = ETH_SPEED_NUM_10G;
2697                 break;
2698         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2699                 eth_link_speed = ETH_SPEED_NUM_20G;
2700                 break;
2701         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2702                 eth_link_speed = ETH_SPEED_NUM_25G;
2703                 break;
2704         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2705                 eth_link_speed = ETH_SPEED_NUM_40G;
2706                 break;
2707         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2708                 eth_link_speed = ETH_SPEED_NUM_50G;
2709                 break;
2710         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2711                 eth_link_speed = ETH_SPEED_NUM_100G;
2712                 break;
2713         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2714         default:
2715                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2716                         hw_link_speed);
2717                 break;
2718         }
2719         return eth_link_speed;
2720 }
2721
2722 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2723 {
2724         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2725
2726         switch (hw_link_duplex) {
2727         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2728         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2729                 /* FALLTHROUGH */
2730                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2731                 break;
2732         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2733                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2734                 break;
2735         default:
2736                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2737                         hw_link_duplex);
2738                 break;
2739         }
2740         return eth_link_duplex;
2741 }
2742
2743 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2744 {
2745         int rc = 0;
2746         struct bnxt_link_info *link_info = &bp->link_info;
2747
2748         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2749         if (rc) {
2750                 PMD_DRV_LOG(ERR,
2751                         "Get link config failed with rc %d\n", rc);
2752                 goto exit;
2753         }
2754         if (link_info->link_speed)
2755                 link->link_speed =
2756                         bnxt_parse_hw_link_speed(link_info->link_speed);
2757         else
2758                 link->link_speed = ETH_SPEED_NUM_NONE;
2759         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2760         link->link_status = link_info->link_up;
2761         link->link_autoneg = link_info->auto_mode ==
2762                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2763                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2764 exit:
2765         return rc;
2766 }
2767
2768 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2769 {
2770         int rc = 0;
2771         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2772         struct bnxt_link_info link_req;
2773         uint16_t speed, autoneg;
2774
2775         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2776                 return 0;
2777
2778         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2779                         bp->eth_dev->data->port_id);
2780         if (rc)
2781                 goto error;
2782
2783         memset(&link_req, 0, sizeof(link_req));
2784         link_req.link_up = link_up;
2785         if (!link_up)
2786                 goto port_phy_cfg;
2787
2788         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2789         if (BNXT_CHIP_THOR(bp) &&
2790             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2791                 /* 40G is not supported as part of media auto detect.
2792                  * The speed should be forced and autoneg disabled
2793                  * to configure 40G speed.
2794                  */
2795                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2796                 autoneg = 0;
2797         }
2798
2799         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2800         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2801         /* Autoneg can be done only when the FW allows.
2802          * When user configures fixed speed of 40G and later changes to
2803          * any other speed, auto_link_speed/force_link_speed is still set
2804          * to 40G until link comes up at new speed.
2805          */
2806         if (autoneg == 1 &&
2807             !(!BNXT_CHIP_THOR(bp) &&
2808               (bp->link_info.auto_link_speed ||
2809                bp->link_info.force_link_speed))) {
2810                 link_req.phy_flags |=
2811                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2812                 link_req.auto_link_speed_mask =
2813                         bnxt_parse_eth_link_speed_mask(bp,
2814                                                        dev_conf->link_speeds);
2815         } else {
2816                 if (bp->link_info.phy_type ==
2817                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2818                     bp->link_info.phy_type ==
2819                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2820                     bp->link_info.media_type ==
2821                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2822                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2823                         return -EINVAL;
2824                 }
2825
2826                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2827                 /* If user wants a particular speed try that first. */
2828                 if (speed)
2829                         link_req.link_speed = speed;
2830                 else if (bp->link_info.force_link_speed)
2831                         link_req.link_speed = bp->link_info.force_link_speed;
2832                 else
2833                         link_req.link_speed = bp->link_info.auto_link_speed;
2834         }
2835         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2836         link_req.auto_pause = bp->link_info.auto_pause;
2837         link_req.force_pause = bp->link_info.force_pause;
2838
2839 port_phy_cfg:
2840         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2841         if (rc) {
2842                 PMD_DRV_LOG(ERR,
2843                         "Set link config failed with rc %d\n", rc);
2844         }
2845
2846 error:
2847         return rc;
2848 }
2849
2850 /* JIRA 22088 */
2851 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2852 {
2853         struct hwrm_func_qcfg_input req = {0};
2854         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2855         uint16_t flags;
2856         int rc = 0;
2857
2858         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2859         req.fid = rte_cpu_to_le_16(0xffff);
2860
2861         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2862
2863         HWRM_CHECK_RESULT();
2864
2865         /* Hard Coded.. 0xfff VLAN ID mask */
2866         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2867         flags = rte_le_to_cpu_16(resp->flags);
2868         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2869                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2870
2871         if (BNXT_VF(bp) &&
2872             !BNXT_VF_IS_TRUSTED(bp) &&
2873             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2874                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2875                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2876         } else if (BNXT_VF(bp) &&
2877                    BNXT_VF_IS_TRUSTED(bp) &&
2878                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2879                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2880                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2881         }
2882
2883         if (mtu)
2884                 *mtu = rte_le_to_cpu_16(resp->mtu);
2885
2886         switch (resp->port_partition_type) {
2887         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2888         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2889         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2890                 /* FALLTHROUGH */
2891                 bp->port_partition_type = resp->port_partition_type;
2892                 break;
2893         default:
2894                 bp->port_partition_type = 0;
2895                 break;
2896         }
2897
2898         HWRM_UNLOCK();
2899
2900         return rc;
2901 }
2902
2903 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2904                                    struct hwrm_func_qcaps_output *qcaps)
2905 {
2906         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2907         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2908                sizeof(qcaps->mac_address));
2909         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2910         qcaps->max_rx_rings = fcfg->num_rx_rings;
2911         qcaps->max_tx_rings = fcfg->num_tx_rings;
2912         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2913         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2914         qcaps->max_vfs = 0;
2915         qcaps->first_vf_id = 0;
2916         qcaps->max_vnics = fcfg->num_vnics;
2917         qcaps->max_decap_records = 0;
2918         qcaps->max_encap_records = 0;
2919         qcaps->max_tx_wm_flows = 0;
2920         qcaps->max_tx_em_flows = 0;
2921         qcaps->max_rx_wm_flows = 0;
2922         qcaps->max_rx_em_flows = 0;
2923         qcaps->max_flow_id = 0;
2924         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2925         qcaps->max_sp_tx_rings = 0;
2926         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2927 }
2928
2929 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2930 {
2931         struct hwrm_func_cfg_input req = {0};
2932         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2933         uint32_t enables;
2934         int rc;
2935
2936         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2937                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2938                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2939                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2940                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2941                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2942                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2943                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2944                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2945
2946         if (BNXT_HAS_RING_GRPS(bp)) {
2947                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2948                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2949         } else if (BNXT_HAS_NQ(bp)) {
2950                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2951                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2952         }
2953
2954         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2955         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2956         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
2957         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2958         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2959         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2960         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2961         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2962         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2963         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2964         req.fid = rte_cpu_to_le_16(0xffff);
2965         req.enables = rte_cpu_to_le_32(enables);
2966
2967         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2968
2969         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2970
2971         HWRM_CHECK_RESULT();
2972         HWRM_UNLOCK();
2973
2974         return rc;
2975 }
2976
2977 static void populate_vf_func_cfg_req(struct bnxt *bp,
2978                                      struct hwrm_func_cfg_input *req,
2979                                      int num_vfs)
2980 {
2981         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2982                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2983                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2984                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2985                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2986                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2987                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2988                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2989                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2990                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2991
2992         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2993                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2994                                     BNXT_NUM_VLANS);
2995         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
2996         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2997                                                 (num_vfs + 1));
2998         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2999         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3000                                                (num_vfs + 1));
3001         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3002         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3003         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3004         /* TODO: For now, do not support VMDq/RFS on VFs. */
3005         req->num_vnics = rte_cpu_to_le_16(1);
3006         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3007                                                  (num_vfs + 1));
3008 }
3009
3010 static void add_random_mac_if_needed(struct bnxt *bp,
3011                                      struct hwrm_func_cfg_input *cfg_req,
3012                                      int vf)
3013 {
3014         struct rte_ether_addr mac;
3015
3016         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3017                 return;
3018
3019         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3020                 cfg_req->enables |=
3021                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3022                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3023                 bp->pf.vf_info[vf].random_mac = true;
3024         } else {
3025                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3026                         RTE_ETHER_ADDR_LEN);
3027         }
3028 }
3029
3030 static void reserve_resources_from_vf(struct bnxt *bp,
3031                                       struct hwrm_func_cfg_input *cfg_req,
3032                                       int vf)
3033 {
3034         struct hwrm_func_qcaps_input req = {0};
3035         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3036         int rc;
3037
3038         /* Get the actual allocated values now */
3039         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3040         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3041         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3042
3043         if (rc) {
3044                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3045                 copy_func_cfg_to_qcaps(cfg_req, resp);
3046         } else if (resp->error_code) {
3047                 rc = rte_le_to_cpu_16(resp->error_code);
3048                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3049                 copy_func_cfg_to_qcaps(cfg_req, resp);
3050         }
3051
3052         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3053         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3054         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3055         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3056         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3057         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3058         /*
3059          * TODO: While not supporting VMDq with VFs, max_vnics is always
3060          * forced to 1 in this case
3061          */
3062         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3063         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3064
3065         HWRM_UNLOCK();
3066 }
3067
3068 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3069 {
3070         struct hwrm_func_qcfg_input req = {0};
3071         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3072         int rc;
3073
3074         /* Check for zero MAC address */
3075         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3076         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3077         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3078         HWRM_CHECK_RESULT();
3079         rc = rte_le_to_cpu_16(resp->vlan);
3080
3081         HWRM_UNLOCK();
3082
3083         return rc;
3084 }
3085
3086 static int update_pf_resource_max(struct bnxt *bp)
3087 {
3088         struct hwrm_func_qcfg_input req = {0};
3089         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3090         int rc;
3091
3092         /* And copy the allocated numbers into the pf struct */
3093         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3094         req.fid = rte_cpu_to_le_16(0xffff);
3095         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3096         HWRM_CHECK_RESULT();
3097
3098         /* Only TX ring value reflects actual allocation? TODO */
3099         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3100         bp->pf.evb_mode = resp->evb_mode;
3101
3102         HWRM_UNLOCK();
3103
3104         return rc;
3105 }
3106
3107 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3108 {
3109         int rc;
3110
3111         if (!BNXT_PF(bp)) {
3112                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3113                 return -EINVAL;
3114         }
3115
3116         rc = bnxt_hwrm_func_qcaps(bp);
3117         if (rc)
3118                 return rc;
3119
3120         bp->pf.func_cfg_flags &=
3121                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3122                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3123         bp->pf.func_cfg_flags |=
3124                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3125         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3126         rc = __bnxt_hwrm_func_qcaps(bp);
3127         return rc;
3128 }
3129
3130 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3131 {
3132         struct hwrm_func_cfg_input req = {0};
3133         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3134         int i;
3135         size_t sz;
3136         int rc = 0;
3137         size_t req_buf_sz;
3138
3139         if (!BNXT_PF(bp)) {
3140                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3141                 return -EINVAL;
3142         }
3143
3144         rc = bnxt_hwrm_func_qcaps(bp);
3145
3146         if (rc)
3147                 return rc;
3148
3149         bp->pf.active_vfs = num_vfs;
3150
3151         /*
3152          * First, configure the PF to only use one TX ring.  This ensures that
3153          * there are enough rings for all VFs.
3154          *
3155          * If we don't do this, when we call func_alloc() later, we will lock
3156          * extra rings to the PF that won't be available during func_cfg() of
3157          * the VFs.
3158          *
3159          * This has been fixed with firmware versions above 20.6.54
3160          */
3161         bp->pf.func_cfg_flags &=
3162                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3163                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3164         bp->pf.func_cfg_flags |=
3165                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3166         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3167         if (rc)
3168                 return rc;
3169
3170         /*
3171          * Now, create and register a buffer to hold forwarded VF requests
3172          */
3173         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3174         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3175                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3176         if (bp->pf.vf_req_buf == NULL) {
3177                 rc = -ENOMEM;
3178                 goto error_free;
3179         }
3180         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3181                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3182         for (i = 0; i < num_vfs; i++)
3183                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3184                                         (i * HWRM_MAX_REQ_LEN);
3185
3186         rc = bnxt_hwrm_func_buf_rgtr(bp);
3187         if (rc)
3188                 goto error_free;
3189
3190         populate_vf_func_cfg_req(bp, &req, num_vfs);
3191
3192         bp->pf.active_vfs = 0;
3193         for (i = 0; i < num_vfs; i++) {
3194                 add_random_mac_if_needed(bp, &req, i);
3195
3196                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3197                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3198                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3199                 rc = bnxt_hwrm_send_message(bp,
3200                                             &req,
3201                                             sizeof(req),
3202                                             BNXT_USE_CHIMP_MB);
3203
3204                 /* Clear enable flag for next pass */
3205                 req.enables &= ~rte_cpu_to_le_32(
3206                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3207
3208                 if (rc || resp->error_code) {
3209                         PMD_DRV_LOG(ERR,
3210                                 "Failed to initizlie VF %d\n", i);
3211                         PMD_DRV_LOG(ERR,
3212                                 "Not all VFs available. (%d, %d)\n",
3213                                 rc, resp->error_code);
3214                         HWRM_UNLOCK();
3215                         break;
3216                 }
3217
3218                 HWRM_UNLOCK();
3219
3220                 reserve_resources_from_vf(bp, &req, i);
3221                 bp->pf.active_vfs++;
3222                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3223         }
3224
3225         /*
3226          * Now configure the PF to use "the rest" of the resources
3227          * We're using STD_TX_RING_MODE here though which will limit the TX
3228          * rings.  This will allow QoS to function properly.  Not setting this
3229          * will cause PF rings to break bandwidth settings.
3230          */
3231         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3232         if (rc)
3233                 goto error_free;
3234
3235         rc = update_pf_resource_max(bp);
3236         if (rc)
3237                 goto error_free;
3238
3239         return rc;
3240
3241 error_free:
3242         bnxt_hwrm_func_buf_unrgtr(bp);
3243         return rc;
3244 }
3245
3246 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3247 {
3248         struct hwrm_func_cfg_input req = {0};
3249         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3250         int rc;
3251
3252         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3253
3254         req.fid = rte_cpu_to_le_16(0xffff);
3255         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3256         req.evb_mode = bp->pf.evb_mode;
3257
3258         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3259         HWRM_CHECK_RESULT();
3260         HWRM_UNLOCK();
3261
3262         return rc;
3263 }
3264
3265 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3266                                 uint8_t tunnel_type)
3267 {
3268         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3269         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3270         int rc = 0;
3271
3272         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3273         req.tunnel_type = tunnel_type;
3274         req.tunnel_dst_port_val = port;
3275         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3276         HWRM_CHECK_RESULT();
3277
3278         switch (tunnel_type) {
3279         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3280                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3281                 bp->vxlan_port = port;
3282                 break;
3283         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3284                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3285                 bp->geneve_port = port;
3286                 break;
3287         default:
3288                 break;
3289         }
3290
3291         HWRM_UNLOCK();
3292
3293         return rc;
3294 }
3295
3296 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3297                                 uint8_t tunnel_type)
3298 {
3299         struct hwrm_tunnel_dst_port_free_input req = {0};
3300         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3301         int rc = 0;
3302
3303         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3304
3305         req.tunnel_type = tunnel_type;
3306         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3307         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3308
3309         HWRM_CHECK_RESULT();
3310         HWRM_UNLOCK();
3311
3312         return rc;
3313 }
3314
3315 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3316                                         uint32_t flags)
3317 {
3318         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3319         struct hwrm_func_cfg_input req = {0};
3320         int rc;
3321
3322         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3323
3324         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3325         req.flags = rte_cpu_to_le_32(flags);
3326         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3327
3328         HWRM_CHECK_RESULT();
3329         HWRM_UNLOCK();
3330
3331         return rc;
3332 }
3333
3334 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3335 {
3336         uint32_t *flag = flagp;
3337
3338         vnic->flags = *flag;
3339 }
3340
3341 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3342 {
3343         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3344 }
3345
3346 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3347 {
3348         int rc = 0;
3349         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3350         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3351
3352         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3353
3354         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3355         req.req_buf_page_size = rte_cpu_to_le_16(
3356                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3357         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3358         req.req_buf_page_addr0 =
3359                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3360         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3361                 PMD_DRV_LOG(ERR,
3362                         "unable to map buffer address to physical memory\n");
3363                 return -ENOMEM;
3364         }
3365
3366         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3367
3368         HWRM_CHECK_RESULT();
3369         HWRM_UNLOCK();
3370
3371         return rc;
3372 }
3373
3374 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3375 {
3376         int rc = 0;
3377         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3378         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3379
3380         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3381                 return 0;
3382
3383         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3384
3385         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3386
3387         HWRM_CHECK_RESULT();
3388         HWRM_UNLOCK();
3389
3390         return rc;
3391 }
3392
3393 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3394 {
3395         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3396         struct hwrm_func_cfg_input req = {0};
3397         int rc;
3398
3399         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3400
3401         req.fid = rte_cpu_to_le_16(0xffff);
3402         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3403         req.enables = rte_cpu_to_le_32(
3404                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3405         req.async_event_cr = rte_cpu_to_le_16(
3406                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3407         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3408
3409         HWRM_CHECK_RESULT();
3410         HWRM_UNLOCK();
3411
3412         return rc;
3413 }
3414
3415 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3416 {
3417         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3418         struct hwrm_func_vf_cfg_input req = {0};
3419         int rc;
3420
3421         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3422
3423         req.enables = rte_cpu_to_le_32(
3424                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3425         req.async_event_cr = rte_cpu_to_le_16(
3426                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3427         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3428
3429         HWRM_CHECK_RESULT();
3430         HWRM_UNLOCK();
3431
3432         return rc;
3433 }
3434
3435 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3436 {
3437         struct hwrm_func_cfg_input req = {0};
3438         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3439         uint16_t dflt_vlan, fid;
3440         uint32_t func_cfg_flags;
3441         int rc = 0;
3442
3443         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3444
3445         if (is_vf) {
3446                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3447                 fid = bp->pf.vf_info[vf].fid;
3448                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3449         } else {
3450                 fid = rte_cpu_to_le_16(0xffff);
3451                 func_cfg_flags = bp->pf.func_cfg_flags;
3452                 dflt_vlan = bp->vlan;
3453         }
3454
3455         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3456         req.fid = rte_cpu_to_le_16(fid);
3457         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3458         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3459
3460         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3461
3462         HWRM_CHECK_RESULT();
3463         HWRM_UNLOCK();
3464
3465         return rc;
3466 }
3467
3468 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3469                         uint16_t max_bw, uint16_t enables)
3470 {
3471         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3472         struct hwrm_func_cfg_input req = {0};
3473         int rc;
3474
3475         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3476
3477         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3478         req.enables |= rte_cpu_to_le_32(enables);
3479         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3480         req.max_bw = rte_cpu_to_le_32(max_bw);
3481         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3482
3483         HWRM_CHECK_RESULT();
3484         HWRM_UNLOCK();
3485
3486         return rc;
3487 }
3488
3489 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3490 {
3491         struct hwrm_func_cfg_input req = {0};
3492         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3493         int rc = 0;
3494
3495         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3496
3497         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3498         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3499         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3500         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3501
3502         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3503
3504         HWRM_CHECK_RESULT();
3505         HWRM_UNLOCK();
3506
3507         return rc;
3508 }
3509
3510 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3511 {
3512         int rc;
3513
3514         if (BNXT_PF(bp))
3515                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3516         else
3517                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3518
3519         return rc;
3520 }
3521
3522 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3523                               void *encaped, size_t ec_size)
3524 {
3525         int rc = 0;
3526         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3527         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3528
3529         if (ec_size > sizeof(req.encap_request))
3530                 return -1;
3531
3532         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3533
3534         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3535         memcpy(req.encap_request, encaped, ec_size);
3536
3537         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3538
3539         HWRM_CHECK_RESULT();
3540         HWRM_UNLOCK();
3541
3542         return rc;
3543 }
3544
3545 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3546                                        struct rte_ether_addr *mac)
3547 {
3548         struct hwrm_func_qcfg_input req = {0};
3549         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3550         int rc;
3551
3552         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3553
3554         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3555         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3556
3557         HWRM_CHECK_RESULT();
3558
3559         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3560
3561         HWRM_UNLOCK();
3562
3563         return rc;
3564 }
3565
3566 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3567                             void *encaped, size_t ec_size)
3568 {
3569         int rc = 0;
3570         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3571         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3572
3573         if (ec_size > sizeof(req.encap_request))
3574                 return -1;
3575
3576         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3577
3578         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3579         memcpy(req.encap_request, encaped, ec_size);
3580
3581         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3582
3583         HWRM_CHECK_RESULT();
3584         HWRM_UNLOCK();
3585
3586         return rc;
3587 }
3588
3589 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3590                          struct rte_eth_stats *stats, uint8_t rx)
3591 {
3592         int rc = 0;
3593         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3594         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3595
3596         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3597
3598         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3599
3600         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3601
3602         HWRM_CHECK_RESULT();
3603
3604         if (rx) {
3605                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3606                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3607                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3608                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3609                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3610                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3611                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3612                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3613         } else {
3614                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3615                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3616                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3617                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3618                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3619                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3620         }
3621
3622         HWRM_UNLOCK();
3623
3624         return rc;
3625 }
3626
3627 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3628 {
3629         struct hwrm_port_qstats_input req = {0};
3630         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3631         struct bnxt_pf_info *pf = &bp->pf;
3632         int rc;
3633
3634         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3635
3636         req.port_id = rte_cpu_to_le_16(pf->port_id);
3637         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3638         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3639         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3640
3641         HWRM_CHECK_RESULT();
3642         HWRM_UNLOCK();
3643
3644         return rc;
3645 }
3646
3647 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3648 {
3649         struct hwrm_port_clr_stats_input req = {0};
3650         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3651         struct bnxt_pf_info *pf = &bp->pf;
3652         int rc;
3653
3654         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3655         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3656             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3657                 return 0;
3658
3659         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3660
3661         req.port_id = rte_cpu_to_le_16(pf->port_id);
3662         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3663
3664         HWRM_CHECK_RESULT();
3665         HWRM_UNLOCK();
3666
3667         return rc;
3668 }
3669
3670 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3671 {
3672         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3673         struct hwrm_port_led_qcaps_input req = {0};
3674         int rc;
3675
3676         if (BNXT_VF(bp))
3677                 return 0;
3678
3679         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3680         req.port_id = bp->pf.port_id;
3681         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3682
3683         HWRM_CHECK_RESULT();
3684
3685         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3686                 unsigned int i;
3687
3688                 bp->num_leds = resp->num_leds;
3689                 memcpy(bp->leds, &resp->led0_id,
3690                         sizeof(bp->leds[0]) * bp->num_leds);
3691                 for (i = 0; i < bp->num_leds; i++) {
3692                         struct bnxt_led_info *led = &bp->leds[i];
3693
3694                         uint16_t caps = led->led_state_caps;
3695
3696                         if (!led->led_group_id ||
3697                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3698                                 bp->num_leds = 0;
3699                                 break;
3700                         }
3701                 }
3702         }
3703
3704         HWRM_UNLOCK();
3705
3706         return rc;
3707 }
3708
3709 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3710 {
3711         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3712         struct hwrm_port_led_cfg_input req = {0};
3713         struct bnxt_led_cfg *led_cfg;
3714         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3715         uint16_t duration = 0;
3716         int rc, i;
3717
3718         if (!bp->num_leds || BNXT_VF(bp))
3719                 return -EOPNOTSUPP;
3720
3721         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3722
3723         if (led_on) {
3724                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3725                 duration = rte_cpu_to_le_16(500);
3726         }
3727         req.port_id = bp->pf.port_id;
3728         req.num_leds = bp->num_leds;
3729         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3730         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3731                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3732                 led_cfg->led_id = bp->leds[i].led_id;
3733                 led_cfg->led_state = led_state;
3734                 led_cfg->led_blink_on = duration;
3735                 led_cfg->led_blink_off = duration;
3736                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3737         }
3738
3739         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3740
3741         HWRM_CHECK_RESULT();
3742         HWRM_UNLOCK();
3743
3744         return rc;
3745 }
3746
3747 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3748                                uint32_t *length)
3749 {
3750         int rc;
3751         struct hwrm_nvm_get_dir_info_input req = {0};
3752         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3753
3754         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3755
3756         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3757
3758         HWRM_CHECK_RESULT();
3759
3760         *entries = rte_le_to_cpu_32(resp->entries);
3761         *length = rte_le_to_cpu_32(resp->entry_length);
3762
3763         HWRM_UNLOCK();
3764         return rc;
3765 }
3766
3767 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3768 {
3769         int rc;
3770         uint32_t dir_entries;
3771         uint32_t entry_length;
3772         uint8_t *buf;
3773         size_t buflen;
3774         rte_iova_t dma_handle;
3775         struct hwrm_nvm_get_dir_entries_input req = {0};
3776         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3777
3778         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3779         if (rc != 0)
3780                 return rc;
3781
3782         *data++ = dir_entries;
3783         *data++ = entry_length;
3784         len -= 2;
3785         memset(data, 0xff, len);
3786
3787         buflen = dir_entries * entry_length;
3788         buf = rte_malloc("nvm_dir", buflen, 0);
3789         rte_mem_lock_page(buf);
3790         if (buf == NULL)
3791                 return -ENOMEM;
3792         dma_handle = rte_mem_virt2iova(buf);
3793         if (dma_handle == RTE_BAD_IOVA) {
3794                 PMD_DRV_LOG(ERR,
3795                         "unable to map response address to physical memory\n");
3796                 return -ENOMEM;
3797         }
3798         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3799         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3800         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3801
3802         if (rc == 0)
3803                 memcpy(data, buf, len > buflen ? buflen : len);
3804
3805         rte_free(buf);
3806         HWRM_CHECK_RESULT();
3807         HWRM_UNLOCK();
3808
3809         return rc;
3810 }
3811
3812 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3813                              uint32_t offset, uint32_t length,
3814                              uint8_t *data)
3815 {
3816         int rc;
3817         uint8_t *buf;
3818         rte_iova_t dma_handle;
3819         struct hwrm_nvm_read_input req = {0};
3820         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3821
3822         buf = rte_malloc("nvm_item", length, 0);
3823         rte_mem_lock_page(buf);
3824         if (!buf)
3825                 return -ENOMEM;
3826
3827         dma_handle = rte_mem_virt2iova(buf);
3828         if (dma_handle == RTE_BAD_IOVA) {
3829                 PMD_DRV_LOG(ERR,
3830                         "unable to map response address to physical memory\n");
3831                 return -ENOMEM;
3832         }
3833         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3834         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3835         req.dir_idx = rte_cpu_to_le_16(index);
3836         req.offset = rte_cpu_to_le_32(offset);
3837         req.len = rte_cpu_to_le_32(length);
3838         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3839         if (rc == 0)
3840                 memcpy(data, buf, length);
3841
3842         rte_free(buf);
3843         HWRM_CHECK_RESULT();
3844         HWRM_UNLOCK();
3845
3846         return rc;
3847 }
3848
3849 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3850 {
3851         int rc;
3852         struct hwrm_nvm_erase_dir_entry_input req = {0};
3853         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3854
3855         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3856         req.dir_idx = rte_cpu_to_le_16(index);
3857         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3858         HWRM_CHECK_RESULT();
3859         HWRM_UNLOCK();
3860
3861         return rc;
3862 }
3863
3864
3865 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3866                           uint16_t dir_ordinal, uint16_t dir_ext,
3867                           uint16_t dir_attr, const uint8_t *data,
3868                           size_t data_len)
3869 {
3870         int rc;
3871         struct hwrm_nvm_write_input req = {0};
3872         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3873         rte_iova_t dma_handle;
3874         uint8_t *buf;
3875
3876         buf = rte_malloc("nvm_write", data_len, 0);
3877         rte_mem_lock_page(buf);
3878         if (!buf)
3879                 return -ENOMEM;
3880
3881         dma_handle = rte_mem_virt2iova(buf);
3882         if (dma_handle == RTE_BAD_IOVA) {
3883                 PMD_DRV_LOG(ERR,
3884                         "unable to map response address to physical memory\n");
3885                 return -ENOMEM;
3886         }
3887         memcpy(buf, data, data_len);
3888
3889         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3890
3891         req.dir_type = rte_cpu_to_le_16(dir_type);
3892         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3893         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3894         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3895         req.dir_data_length = rte_cpu_to_le_32(data_len);
3896         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3897
3898         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3899
3900         rte_free(buf);
3901         HWRM_CHECK_RESULT();
3902         HWRM_UNLOCK();
3903
3904         return rc;
3905 }
3906
3907 static void
3908 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3909 {
3910         uint32_t *count = cbdata;
3911
3912         *count = *count + 1;
3913 }
3914
3915 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3916                                      struct bnxt_vnic_info *vnic __rte_unused)
3917 {
3918         return 0;
3919 }
3920
3921 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3922 {
3923         uint32_t count = 0;
3924
3925         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3926             &count, bnxt_vnic_count_hwrm_stub);
3927
3928         return count;
3929 }
3930
3931 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3932                                         uint16_t *vnic_ids)
3933 {
3934         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3935         struct hwrm_func_vf_vnic_ids_query_output *resp =
3936                                                 bp->hwrm_cmd_resp_addr;
3937         int rc;
3938
3939         /* First query all VNIC ids */
3940         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3941
3942         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3943         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3944         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3945
3946         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3947                 HWRM_UNLOCK();
3948                 PMD_DRV_LOG(ERR,
3949                 "unable to map VNIC ID table address to physical memory\n");
3950                 return -ENOMEM;
3951         }
3952         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3953         HWRM_CHECK_RESULT();
3954         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3955
3956         HWRM_UNLOCK();
3957
3958         return rc;
3959 }
3960
3961 /*
3962  * This function queries the VNIC IDs  for a specified VF. It then calls
3963  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3964  * Then it calls the hwrm_cb function to program this new vnic configuration.
3965  */
3966 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3967         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3968         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3969 {
3970         struct bnxt_vnic_info vnic;
3971         int rc = 0;
3972         int i, num_vnic_ids;
3973         uint16_t *vnic_ids;
3974         size_t vnic_id_sz;
3975         size_t sz;
3976
3977         /* First query all VNIC ids */
3978         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3979         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3980                         RTE_CACHE_LINE_SIZE);
3981         if (vnic_ids == NULL)
3982                 return -ENOMEM;
3983
3984         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3985                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3986
3987         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3988
3989         if (num_vnic_ids < 0)
3990                 return num_vnic_ids;
3991
3992         /* Retrieve VNIC, update bd_stall then update */
3993
3994         for (i = 0; i < num_vnic_ids; i++) {
3995                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3996                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3997                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3998                 if (rc)
3999                         break;
4000                 if (vnic.mru <= 4)      /* Indicates unallocated */
4001                         continue;
4002
4003                 vnic_cb(&vnic, cbdata);
4004
4005                 rc = hwrm_cb(bp, &vnic);
4006                 if (rc)
4007                         break;
4008         }
4009
4010         rte_free(vnic_ids);
4011
4012         return rc;
4013 }
4014
4015 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4016                                               bool on)
4017 {
4018         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4019         struct hwrm_func_cfg_input req = {0};
4020         int rc;
4021
4022         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4023
4024         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4025         req.enables |= rte_cpu_to_le_32(
4026                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4027         req.vlan_antispoof_mode = on ?
4028                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4029                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4030         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4031
4032         HWRM_CHECK_RESULT();
4033         HWRM_UNLOCK();
4034
4035         return rc;
4036 }
4037
4038 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4039 {
4040         struct bnxt_vnic_info vnic;
4041         uint16_t *vnic_ids;
4042         size_t vnic_id_sz;
4043         int num_vnic_ids, i;
4044         size_t sz;
4045         int rc;
4046
4047         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4048         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4049                         RTE_CACHE_LINE_SIZE);
4050         if (vnic_ids == NULL)
4051                 return -ENOMEM;
4052
4053         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4054                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4055
4056         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4057         if (rc <= 0)
4058                 goto exit;
4059         num_vnic_ids = rc;
4060
4061         /*
4062          * Loop through to find the default VNIC ID.
4063          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4064          * by sending the hwrm_func_qcfg command to the firmware.
4065          */
4066         for (i = 0; i < num_vnic_ids; i++) {
4067                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4068                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4069                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4070                                         bp->pf.first_vf_id + vf);
4071                 if (rc)
4072                         goto exit;
4073                 if (vnic.func_default) {
4074                         rte_free(vnic_ids);
4075                         return vnic.fw_vnic_id;
4076                 }
4077         }
4078         /* Could not find a default VNIC. */
4079         PMD_DRV_LOG(ERR, "No default VNIC\n");
4080 exit:
4081         rte_free(vnic_ids);
4082         return rc;
4083 }
4084
4085 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4086                          uint16_t dst_id,
4087                          struct bnxt_filter_info *filter)
4088 {
4089         int rc = 0;
4090         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4091         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4092         uint32_t enables = 0;
4093
4094         if (filter->fw_em_filter_id != UINT64_MAX)
4095                 bnxt_hwrm_clear_em_filter(bp, filter);
4096
4097         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4098
4099         req.flags = rte_cpu_to_le_32(filter->flags);
4100
4101         enables = filter->enables |
4102               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4103         req.dst_id = rte_cpu_to_le_16(dst_id);
4104
4105         if (filter->ip_addr_type) {
4106                 req.ip_addr_type = filter->ip_addr_type;
4107                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4108         }
4109         if (enables &
4110             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4111                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4112         if (enables &
4113             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4114                 memcpy(req.src_macaddr, filter->src_macaddr,
4115                        RTE_ETHER_ADDR_LEN);
4116         if (enables &
4117             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4118                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4119                        RTE_ETHER_ADDR_LEN);
4120         if (enables &
4121             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4122                 req.ovlan_vid = filter->l2_ovlan;
4123         if (enables &
4124             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4125                 req.ivlan_vid = filter->l2_ivlan;
4126         if (enables &
4127             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4128                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4129         if (enables &
4130             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4131                 req.ip_protocol = filter->ip_protocol;
4132         if (enables &
4133             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4134                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4135         if (enables &
4136             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4137                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4138         if (enables &
4139             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4140                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4141         if (enables &
4142             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4143                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4144         if (enables &
4145             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4146                 req.mirror_vnic_id = filter->mirror_vnic_id;
4147
4148         req.enables = rte_cpu_to_le_32(enables);
4149
4150         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4151
4152         HWRM_CHECK_RESULT();
4153
4154         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4155         HWRM_UNLOCK();
4156
4157         return rc;
4158 }
4159
4160 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4161 {
4162         int rc = 0;
4163         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4164         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4165
4166         if (filter->fw_em_filter_id == UINT64_MAX)
4167                 return 0;
4168
4169         PMD_DRV_LOG(ERR, "Clear EM filter\n");
4170         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4171
4172         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4173
4174         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4175
4176         HWRM_CHECK_RESULT();
4177         HWRM_UNLOCK();
4178
4179         filter->fw_em_filter_id = UINT64_MAX;
4180         filter->fw_l2_filter_id = UINT64_MAX;
4181
4182         return 0;
4183 }
4184
4185 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4186                          uint16_t dst_id,
4187                          struct bnxt_filter_info *filter)
4188 {
4189         int rc = 0;
4190         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4191         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4192                                                 bp->hwrm_cmd_resp_addr;
4193         uint32_t enables = 0;
4194
4195         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4196                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4197
4198         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4199
4200         req.flags = rte_cpu_to_le_32(filter->flags);
4201
4202         enables = filter->enables |
4203               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4204         req.dst_id = rte_cpu_to_le_16(dst_id);
4205
4206         if (filter->ip_addr_type) {
4207                 req.ip_addr_type = filter->ip_addr_type;
4208                 enables |=
4209                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4210         }
4211         if (enables &
4212             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4213                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4214         if (enables &
4215             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4216                 memcpy(req.src_macaddr, filter->src_macaddr,
4217                        RTE_ETHER_ADDR_LEN);
4218         if (enables &
4219             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4220                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4221         if (enables &
4222             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4223                 req.ip_protocol = filter->ip_protocol;
4224         if (enables &
4225             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4226                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4227         if (enables &
4228             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4229                 req.src_ipaddr_mask[0] =
4230                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4231         if (enables &
4232             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4233                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4234         if (enables &
4235             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4236                 req.dst_ipaddr_mask[0] =
4237                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4238         if (enables &
4239             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4240                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4241         if (enables &
4242             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4243                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4244         if (enables &
4245             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4246                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4247         if (enables &
4248             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4249                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4250         if (enables &
4251             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4252                 req.mirror_vnic_id = filter->mirror_vnic_id;
4253
4254         req.enables = rte_cpu_to_le_32(enables);
4255
4256         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4257
4258         HWRM_CHECK_RESULT();
4259
4260         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4261         HWRM_UNLOCK();
4262
4263         return rc;
4264 }
4265
4266 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4267                                 struct bnxt_filter_info *filter)
4268 {
4269         int rc = 0;
4270         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4271         struct hwrm_cfa_ntuple_filter_free_output *resp =
4272                                                 bp->hwrm_cmd_resp_addr;
4273
4274         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4275                 return 0;
4276
4277         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4278
4279         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4280
4281         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4282
4283         HWRM_CHECK_RESULT();
4284         HWRM_UNLOCK();
4285
4286         filter->fw_ntuple_filter_id = UINT64_MAX;
4287
4288         return 0;
4289 }
4290
4291 static int
4292 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4293 {
4294         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4295         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4296         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4297         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4298         uint16_t *ring_tbl = vnic->rss_table;
4299         int nr_ctxs = vnic->num_lb_ctxts;
4300         int max_rings = bp->rx_nr_rings;
4301         int i, j, k, cnt;
4302         int rc = 0;
4303
4304         for (i = 0, k = 0; i < nr_ctxs; i++) {
4305                 struct bnxt_rx_ring_info *rxr;
4306                 struct bnxt_cp_ring_info *cpr;
4307
4308                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4309
4310                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4311                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4312                 req.hash_mode_flags = vnic->hash_mode;
4313
4314                 req.ring_grp_tbl_addr =
4315                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4316                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4317                                      2 * sizeof(*ring_tbl));
4318                 req.hash_key_tbl_addr =
4319                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4320
4321                 req.ring_table_pair_index = i;
4322                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4323
4324                 for (j = 0; j < 64; j++) {
4325                         uint16_t ring_id;
4326
4327                         /* Find next active ring. */
4328                         for (cnt = 0; cnt < max_rings; cnt++) {
4329                                 if (rx_queue_state[k] !=
4330                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4331                                         break;
4332                                 if (++k == max_rings)
4333                                         k = 0;
4334                         }
4335
4336                         /* Return if no rings are active. */
4337                         if (cnt == max_rings)
4338                                 return 0;
4339
4340                         /* Add rx/cp ring pair to RSS table. */
4341                         rxr = rxqs[k]->rx_ring;
4342                         cpr = rxqs[k]->cp_ring;
4343
4344                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4345                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4346                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4347                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4348
4349                         if (++k == max_rings)
4350                                 k = 0;
4351                 }
4352                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4353                                             BNXT_USE_CHIMP_MB);
4354
4355                 HWRM_CHECK_RESULT();
4356                 HWRM_UNLOCK();
4357         }
4358
4359         return rc;
4360 }
4361
4362 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4363 {
4364         unsigned int rss_idx, fw_idx, i;
4365
4366         if (!(vnic->rss_table && vnic->hash_type))
4367                 return 0;
4368
4369         if (BNXT_CHIP_THOR(bp))
4370                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4371
4372         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4373                 return 0;
4374
4375         if (vnic->rss_table && vnic->hash_type) {
4376                 /*
4377                  * Fill the RSS hash & redirection table with
4378                  * ring group ids for all VNICs
4379                  */
4380                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4381                         rss_idx++, fw_idx++) {
4382                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4383                                 fw_idx %= bp->rx_cp_nr_rings;
4384                                 if (vnic->fw_grp_ids[fw_idx] !=
4385                                     INVALID_HW_RING_ID)
4386                                         break;
4387                                 fw_idx++;
4388                         }
4389                         if (i == bp->rx_cp_nr_rings)
4390                                 return 0;
4391                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4392                 }
4393                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4394         }
4395
4396         return 0;
4397 }
4398
4399 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4400         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4401 {
4402         uint16_t flags;
4403
4404         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4405
4406         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4407         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4408
4409         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4410         req->num_cmpl_dma_aggr_during_int =
4411                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4412
4413         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4414
4415         /* min timer set to 1/2 of interrupt timer */
4416         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4417
4418         /* buf timer set to 1/4 of interrupt timer */
4419         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4420
4421         req->cmpl_aggr_dma_tmr_during_int =
4422                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4423
4424         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4425                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4426         req->flags = rte_cpu_to_le_16(flags);
4427 }
4428
4429 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4430                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4431 {
4432         struct hwrm_ring_aggint_qcaps_input req = {0};
4433         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4434         uint32_t enables;
4435         uint16_t flags;
4436         int rc;
4437
4438         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4439         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4440         HWRM_CHECK_RESULT();
4441
4442         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4443         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4444
4445         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4446                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4447         agg_req->flags = rte_cpu_to_le_16(flags);
4448         enables =
4449          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4450          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4451         agg_req->enables = rte_cpu_to_le_32(enables);
4452
4453         HWRM_UNLOCK();
4454         return rc;
4455 }
4456
4457 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4458                         struct bnxt_coal *coal, uint16_t ring_id)
4459 {
4460         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4461         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4462                                                 bp->hwrm_cmd_resp_addr;
4463         int rc;
4464
4465         /* Set ring coalesce parameters only for 100G NICs */
4466         if (BNXT_CHIP_THOR(bp)) {
4467                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4468                         return -1;
4469         } else if (bnxt_stratus_device(bp)) {
4470                 bnxt_hwrm_set_coal_params(coal, &req);
4471         } else {
4472                 return 0;
4473         }
4474
4475         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4476         req.ring_id = rte_cpu_to_le_16(ring_id);
4477         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4478         HWRM_CHECK_RESULT();
4479         HWRM_UNLOCK();
4480         return 0;
4481 }
4482
4483 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4484 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4485 {
4486         struct hwrm_func_backing_store_qcaps_input req = {0};
4487         struct hwrm_func_backing_store_qcaps_output *resp =
4488                 bp->hwrm_cmd_resp_addr;
4489         struct bnxt_ctx_pg_info *ctx_pg;
4490         struct bnxt_ctx_mem_info *ctx;
4491         int total_alloc_len;
4492         int rc, i;
4493
4494         if (!BNXT_CHIP_THOR(bp) ||
4495             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4496             BNXT_VF(bp) ||
4497             bp->ctx)
4498                 return 0;
4499
4500         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4501         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4502         HWRM_CHECK_RESULT_SILENT();
4503
4504         total_alloc_len = sizeof(*ctx);
4505         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4506                           RTE_CACHE_LINE_SIZE);
4507         if (!ctx) {
4508                 rc = -ENOMEM;
4509                 goto ctx_err;
4510         }
4511
4512         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4513                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4514                             RTE_CACHE_LINE_SIZE);
4515         if (!ctx_pg) {
4516                 rc = -ENOMEM;
4517                 goto ctx_err;
4518         }
4519         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4520                 ctx->tqm_mem[i] = ctx_pg;
4521
4522         bp->ctx = ctx;
4523         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4524         ctx->qp_min_qp1_entries =
4525                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4526         ctx->qp_max_l2_entries =
4527                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4528         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4529         ctx->srq_max_l2_entries =
4530                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4531         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4532         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4533         ctx->cq_max_l2_entries =
4534                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4535         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4536         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4537         ctx->vnic_max_vnic_entries =
4538                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4539         ctx->vnic_max_ring_table_entries =
4540                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4541         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4542         ctx->stat_max_entries =
4543                 rte_le_to_cpu_32(resp->stat_max_entries);
4544         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4545         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4546         ctx->tqm_min_entries_per_ring =
4547                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4548         ctx->tqm_max_entries_per_ring =
4549                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4550         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4551         if (!ctx->tqm_entries_multiple)
4552                 ctx->tqm_entries_multiple = 1;
4553         ctx->mrav_max_entries =
4554                 rte_le_to_cpu_32(resp->mrav_max_entries);
4555         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4556         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4557         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4558 ctx_err:
4559         HWRM_UNLOCK();
4560         return rc;
4561 }
4562
4563 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4564 {
4565         struct hwrm_func_backing_store_cfg_input req = {0};
4566         struct hwrm_func_backing_store_cfg_output *resp =
4567                 bp->hwrm_cmd_resp_addr;
4568         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4569         struct bnxt_ctx_pg_info *ctx_pg;
4570         uint32_t *num_entries;
4571         uint64_t *pg_dir;
4572         uint8_t *pg_attr;
4573         uint32_t ena;
4574         int i, rc;
4575
4576         if (!ctx)
4577                 return 0;
4578
4579         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4580         req.enables = rte_cpu_to_le_32(enables);
4581
4582         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4583                 ctx_pg = &ctx->qp_mem;
4584                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4585                 req.qp_num_qp1_entries =
4586                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4587                 req.qp_num_l2_entries =
4588                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4589                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4590                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4591                                       &req.qpc_pg_size_qpc_lvl,
4592                                       &req.qpc_page_dir);
4593         }
4594
4595         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4596                 ctx_pg = &ctx->srq_mem;
4597                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4598                 req.srq_num_l2_entries =
4599                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4600                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4601                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4602                                       &req.srq_pg_size_srq_lvl,
4603                                       &req.srq_page_dir);
4604         }
4605
4606         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4607                 ctx_pg = &ctx->cq_mem;
4608                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4609                 req.cq_num_l2_entries =
4610                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4611                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4612                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4613                                       &req.cq_pg_size_cq_lvl,
4614                                       &req.cq_page_dir);
4615         }
4616
4617         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4618                 ctx_pg = &ctx->vnic_mem;
4619                 req.vnic_num_vnic_entries =
4620                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4621                 req.vnic_num_ring_table_entries =
4622                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4623                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4624                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4625                                       &req.vnic_pg_size_vnic_lvl,
4626                                       &req.vnic_page_dir);
4627         }
4628
4629         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4630                 ctx_pg = &ctx->stat_mem;
4631                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4632                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4633                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4634                                       &req.stat_pg_size_stat_lvl,
4635                                       &req.stat_page_dir);
4636         }
4637
4638         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4639         num_entries = &req.tqm_sp_num_entries;
4640         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4641         pg_dir = &req.tqm_sp_page_dir;
4642         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4643         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4644                 if (!(enables & ena))
4645                         continue;
4646
4647                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4648
4649                 ctx_pg = ctx->tqm_mem[i];
4650                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4651                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4652         }
4653
4654         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4655         HWRM_CHECK_RESULT();
4656         HWRM_UNLOCK();
4657
4658         return rc;
4659 }
4660
4661 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4662 {
4663         struct hwrm_port_qstats_ext_input req = {0};
4664         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4665         struct bnxt_pf_info *pf = &bp->pf;
4666         int rc;
4667
4668         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4669               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4670                 return 0;
4671
4672         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4673
4674         req.port_id = rte_cpu_to_le_16(pf->port_id);
4675         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4676                 req.tx_stat_host_addr =
4677                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4678                 req.tx_stat_size =
4679                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4680         }
4681         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4682                 req.rx_stat_host_addr =
4683                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4684                 req.rx_stat_size =
4685                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4686         }
4687         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4688
4689         if (rc) {
4690                 bp->fw_rx_port_stats_ext_size = 0;
4691                 bp->fw_tx_port_stats_ext_size = 0;
4692         } else {
4693                 bp->fw_rx_port_stats_ext_size =
4694                         rte_le_to_cpu_16(resp->rx_stat_size);
4695                 bp->fw_tx_port_stats_ext_size =
4696                         rte_le_to_cpu_16(resp->tx_stat_size);
4697         }
4698
4699         HWRM_CHECK_RESULT();
4700         HWRM_UNLOCK();
4701
4702         return rc;
4703 }
4704
4705 int
4706 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4707 {
4708         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4709         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4710                 bp->hwrm_cmd_resp_addr;
4711         int rc = 0;
4712
4713         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4714         req.tunnel_type = type;
4715         req.dest_fid = bp->fw_fid;
4716         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4717         HWRM_CHECK_RESULT();
4718
4719         HWRM_UNLOCK();
4720
4721         return rc;
4722 }
4723
4724 int
4725 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4726 {
4727         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4728         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4729                 bp->hwrm_cmd_resp_addr;
4730         int rc = 0;
4731
4732         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4733         req.tunnel_type = type;
4734         req.dest_fid = bp->fw_fid;
4735         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4736         HWRM_CHECK_RESULT();
4737
4738         HWRM_UNLOCK();
4739
4740         return rc;
4741 }
4742
4743 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4744 {
4745         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4746         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4747                 bp->hwrm_cmd_resp_addr;
4748         int rc = 0;
4749
4750         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4751         req.src_fid = bp->fw_fid;
4752         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4753         HWRM_CHECK_RESULT();
4754
4755         if (type)
4756                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4757
4758         HWRM_UNLOCK();
4759
4760         return rc;
4761 }
4762
4763 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4764                                    uint16_t *dst_fid)
4765 {
4766         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4767         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4768                 bp->hwrm_cmd_resp_addr;
4769         int rc = 0;
4770
4771         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4772         req.src_fid = bp->fw_fid;
4773         req.tunnel_type = tun_type;
4774         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4775         HWRM_CHECK_RESULT();
4776
4777         if (dst_fid)
4778                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4779
4780         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4781
4782         HWRM_UNLOCK();
4783
4784         return rc;
4785 }
4786
4787 int bnxt_hwrm_set_mac(struct bnxt *bp)
4788 {
4789         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4790         struct hwrm_func_vf_cfg_input req = {0};
4791         int rc = 0;
4792
4793         if (!BNXT_VF(bp))
4794                 return 0;
4795
4796         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4797
4798         req.enables =
4799                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4800         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4801
4802         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4803
4804         HWRM_CHECK_RESULT();
4805
4806         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4807         HWRM_UNLOCK();
4808
4809         return rc;
4810 }
4811
4812 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4813 {
4814         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4815         struct hwrm_func_drv_if_change_input req = {0};
4816         uint32_t flags;
4817         int rc;
4818
4819         if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4820                 return 0;
4821
4822         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4823          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4824          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4825          */
4826         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4827                 return 0;
4828
4829         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4830
4831         if (up)
4832                 req.flags =
4833                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4834
4835         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4836
4837         HWRM_CHECK_RESULT();
4838         flags = rte_le_to_cpu_32(resp->flags);
4839         HWRM_UNLOCK();
4840
4841         if (!up)
4842                 return 0;
4843
4844         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4845                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4846                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4847         }
4848
4849         return 0;
4850 }
4851
4852 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4853 {
4854         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4855         struct bnxt_error_recovery_info *info = bp->recovery_info;
4856         struct hwrm_error_recovery_qcfg_input req = {0};
4857         uint32_t flags = 0;
4858         unsigned int i;
4859         int rc;
4860
4861         /* Older FW does not have error recovery support */
4862         if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4863                 return 0;
4864
4865         if (!info) {
4866                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4867                                    sizeof(*info), 0);
4868                 bp->recovery_info = info;
4869                 if (info == NULL)
4870                         return -ENOMEM;
4871         } else {
4872                 memset(info, 0, sizeof(*info));
4873         }
4874
4875         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4876
4877         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4878
4879         HWRM_CHECK_RESULT();
4880
4881         flags = rte_le_to_cpu_32(resp->flags);
4882         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4883                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4884         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4885                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4886
4887         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4888             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4889                 rc = -EINVAL;
4890                 goto err;
4891         }
4892
4893         /* FW returned values are in units of 100msec */
4894         info->driver_polling_freq =
4895                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4896         info->master_func_wait_period =
4897                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4898         info->normal_func_wait_period =
4899                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4900         info->master_func_wait_period_after_reset =
4901                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4902         info->max_bailout_time_after_reset =
4903                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4904         info->status_regs[BNXT_FW_STATUS_REG] =
4905                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4906         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4907                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4908         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4909                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4910         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4911                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4912         info->reg_array_cnt =
4913                 rte_le_to_cpu_32(resp->reg_array_cnt);
4914
4915         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4916                 rc = -EINVAL;
4917                 goto err;
4918         }
4919
4920         for (i = 0; i < info->reg_array_cnt; i++) {
4921                 info->reset_reg[i] =
4922                         rte_le_to_cpu_32(resp->reset_reg[i]);
4923                 info->reset_reg_val[i] =
4924                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4925                 info->delay_after_reset[i] =
4926                         resp->delay_after_reset[i];
4927         }
4928 err:
4929         HWRM_UNLOCK();
4930
4931         /* Map the FW status registers */
4932         if (!rc)
4933                 rc = bnxt_map_fw_health_status_regs(bp);
4934
4935         if (rc) {
4936                 rte_free(bp->recovery_info);
4937                 bp->recovery_info = NULL;
4938         }
4939         return rc;
4940 }
4941
4942 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4943 {
4944         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4945         struct hwrm_fw_reset_input req = {0};
4946         int rc;
4947
4948         if (!BNXT_PF(bp))
4949                 return -EOPNOTSUPP;
4950
4951         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4952
4953         req.embedded_proc_type =
4954                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4955         req.selfrst_status =
4956                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4957         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4958
4959         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4960                                     BNXT_USE_KONG(bp));
4961
4962         HWRM_CHECK_RESULT();
4963         HWRM_UNLOCK();
4964
4965         return rc;
4966 }
4967
4968 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4969 {
4970         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4971         struct hwrm_port_ts_query_input req = {0};
4972         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4973         uint32_t flags = 0;
4974         int rc;
4975
4976         if (!ptp)
4977                 return 0;
4978
4979         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4980
4981         switch (path) {
4982         case BNXT_PTP_FLAGS_PATH_TX:
4983                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4984                 break;
4985         case BNXT_PTP_FLAGS_PATH_RX:
4986                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4987                 break;
4988         case BNXT_PTP_FLAGS_CURRENT_TIME:
4989                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
4990                 break;
4991         }
4992
4993         req.flags = rte_cpu_to_le_32(flags);
4994         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
4995
4996         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4997
4998         HWRM_CHECK_RESULT();
4999
5000         if (timestamp) {
5001                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5002                 *timestamp |=
5003                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5004         }
5005         HWRM_UNLOCK();
5006
5007         return rc;
5008 }
5009
5010 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5011 {
5012         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5013                                         bp->hwrm_cmd_resp_addr;
5014         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5015         uint32_t flags = 0;
5016         int rc = 0;
5017
5018         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5019                 return rc;
5020
5021         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5022                 PMD_DRV_LOG(DEBUG,
5023                             "Not a PF or trusted VF. Command not supported\n");
5024                 return 0;
5025         }
5026
5027         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5028         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5029
5030         HWRM_CHECK_RESULT();
5031         flags = rte_le_to_cpu_32(resp->flags);
5032         HWRM_UNLOCK();
5033
5034         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5035                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5036                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5037         }
5038
5039         return rc;
5040 }