drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30 #define HWRM_VERSION_1_10_2_13          0x10a020d
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages == 0)
  68                 return;
  69
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 static struct bnxt_cp_ring_info*
  79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
  80 {
  81         struct bnxt_cp_ring_info *cp_ring = NULL;
  82         uint16_t i;
  83
  84         switch (type) {
  85         case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
  86         case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
  87                 /* FALLTHROUGH */
  88                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
  89                         struct bnxt_rx_queue *rxq = bp->rx_queues[i];
  90
  91                         if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
  92                             rte_cpu_to_le_16(rid)) {
  93                                 return rxq->cp_ring;
  94                         }
  95                 }
  96                 break;
  97         case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
  98                 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
  99                         struct bnxt_tx_queue *txq = bp->tx_queues[i];
 100
 101                         if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
 102                             rte_cpu_to_le_16(rid)) {
 103                                 return txq->cp_ring;
 104                         }
 105                 }
 106                 break;
 107         default:
 108                 return cp_ring;
 109         }
 110         return cp_ring;
 111 }
 112
 113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
 114  * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
 115  * before timeout, we force the done bit for the cleanup to proceed.
 116  * Also if cpr is null, do nothing.. The HWRM command is  not for a
 117  * Tx/Rx/AGG ring cleanup.
 118  */
 119 static int
 120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
 121                         bool tx, bool rx, bool timeout)
 122 {
 123         int done = 0;
 124
 125         if (cpr != NULL) {
 126                 if (tx)
 127                         done = bnxt_flush_tx_cmp(cpr);
 128
 129                 if (rx)
 130                         done = bnxt_flush_rx_cmp(cpr);
 131
 132                 if (done)
 133                         PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
 134                                     rx ? "Rx" : "Tx");
 135
 136                 /* We are about to timeout and still haven't seen the
 137                  * HWRM done for the Ring free. Force the cleanup.
 138                  */
 139                 if (!done && timeout) {
 140                         done = 1;
 141                         PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
 142                                     rx ? "Rx" : "Tx");
 143                 }
 144         } else {
 145                 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
 146                  * Otherwise the cpr would have been valid. So do nothing.
 147                  */
 148                 done = 1;
 149         }
 150
 151         return done;
 152 }
 153
 154 /*
 155  * HWRM Functions (sent to HWRM)
 156  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
 157  * HWRM command times out, or a negative error code if the HWRM
 158  * command was failed by the FW.
 159  */
 160
 161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
 162                                   uint32_t msg_len, bool use_kong_mb)
 163 {
 164         unsigned int i;
 165         struct input *req = msg;
 166         struct output *resp = bp->hwrm_cmd_resp_addr;
 167         uint32_t *data = msg;
 168         uint8_t *bar;
 169         uint8_t *valid;
 170         uint16_t max_req_len = bp->max_req_len;
 171         struct hwrm_short_input short_input = { 0 };
 172         uint16_t bar_offset = use_kong_mb ?
 173                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
 174         uint16_t mb_trigger_offset = use_kong_mb ?
 175                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 176         struct bnxt_cp_ring_info *cpr = NULL;
 177         bool is_rx = false;
 178         bool is_tx = false;
 179         uint32_t timeout;
 180
 181         /* Do not send HWRM commands to firmware in error state */
 182         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 183                 return 0;
 184
 185         timeout = bp->hwrm_cmd_timeout;
 186
 187         /* Update the message length for backing store config for new FW. */
 188         if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
 189             rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
 190                 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
 191
 192         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 193             msg_len > bp->max_req_len) {
 194                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 195
 196                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 197                 memcpy(short_cmd_req, req, msg_len);
 198
 199                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 200                 short_input.signature = rte_cpu_to_le_16(
 201                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 202                 short_input.size = rte_cpu_to_le_16(msg_len);
 203                 short_input.req_addr =
 204                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 205
 206                 data = (uint32_t *)&short_input;
 207                 msg_len = sizeof(short_input);
 208
 209                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 210         }
 211
 212         /* Write request msg to hwrm channel */
 213         for (i = 0; i < msg_len; i += 4) {
 214                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 215                 rte_write32(*data, bar);
 216                 data++;
 217         }
 218
 219         /* Zero the rest of the request space */
 220         for (; i < max_req_len; i += 4) {
 221                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 222                 rte_write32(0, bar);
 223         }
 224
 225         /* Ring channel doorbell */
 226         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 227         rte_write32(1, bar);
 228         /*
 229          * Make sure the channel doorbell ring command complete before
 230          * reading the response to avoid getting stale or invalid
 231          * responses.
 232          */
 233         rte_io_mb();
 234
 235         /* Check ring flush is done.
 236          * This is valid only for Tx and Rx rings (including AGG rings).
 237          * The Tx and Rx rings should be freed once the HW confirms all
 238          * the internal buffers and BDs associated with the rings are
 239          * consumed and the corresponding DMA is handled.
 240          */
 241         if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
 242                 /* Check if the TxCQ matches. If that fails check if RxCQ
 243                  * matches. And if neither match, is_rx = false, is_tx = false.
 244                  */
 245                 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 246                                                HWRM_RING_FREE_INPUT_RING_TYPE_TX);
 247                 if (cpr == NULL) {
 248                         /* Not a TxCQ. Check if the RxCQ matches. */
 249                         cpr =
 250                         bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 251                                                  HWRM_RING_FREE_INPUT_RING_TYPE_RX);
 252                         if (cpr != NULL)
 253                                 is_rx = true;
 254                 } else {
 255                         is_tx = true;
 256                 }
 257         }
 258
 259         /* Poll for the valid bit */
 260         for (i = 0; i < timeout; i++) {
 261                 int done;
 262
 263                 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
 264                                                i == timeout - 1);
 265                 /* Sanity check on the resp->resp_len */
 266                 rte_io_rmb();
 267                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 268                         /* Last byte of resp contains the valid key */
 269                         valid = (uint8_t *)resp + resp->resp_len - 1;
 270                         if (*valid == HWRM_RESP_VALID_KEY && done)
 271                                 break;
 272                 }
 273                 rte_delay_us(1);
 274         }
 275
 276         if (i >= timeout) {
 277                 /* Suppress VER_GET timeout messages during reset recovery */
 278                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 279                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 280                         return -ETIMEDOUT;
 281
 282                 PMD_DRV_LOG(ERR,
 283                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 284                             req->req_type, req->seq_id);
 285                 return -ETIMEDOUT;
 286         }
 287         return 0;
 288 }
 289
 290 /*
 291  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 292  * spinlock, and does initial processing.
 293  *
 294  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 295  * releases the spinlock only if it returns. If the regular int return codes
 296  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 297  * directly, rather it should be copied and modified to suit the function.
 298  *
 299  * HWRM_UNLOCK() must be called after all response processing is completed.
 300  */
 301 #define HWRM_PREP(req, type, kong) do { \
 302         rte_spinlock_lock(&bp->hwrm_lock); \
 303         if (bp->hwrm_cmd_resp_addr == NULL) { \
 304                 rte_spinlock_unlock(&bp->hwrm_lock); \
 305                 return -EACCES; \
 306         } \
 307         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 308         (req)->req_type = rte_cpu_to_le_16(type); \
 309         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 310         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 311                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 312         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 313         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 314 } while (0)
 315
 316 #define HWRM_CHECK_RESULT_SILENT() do {\
 317         if (rc) { \
 318                 rte_spinlock_unlock(&bp->hwrm_lock); \
 319                 return rc; \
 320         } \
 321         if (resp->error_code) { \
 322                 rc = rte_le_to_cpu_16(resp->error_code); \
 323                 rte_spinlock_unlock(&bp->hwrm_lock); \
 324                 return rc; \
 325         } \
 326 } while (0)
 327
 328 #define HWRM_CHECK_RESULT() do {\
 329         if (rc) { \
 330                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 331                 rte_spinlock_unlock(&bp->hwrm_lock); \
 332                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 333                         rc = -EACCES; \
 334                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 335                         rc = -ENOSPC; \
 336                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 337                         rc = -EINVAL; \
 338                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 339                         rc = -ENOTSUP; \
 340                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 341                         rc = -EAGAIN; \
 342                 else if (rc > 0) \
 343                         rc = -EIO; \
 344                 return rc; \
 345         } \
 346         if (resp->error_code) { \
 347                 rc = rte_le_to_cpu_16(resp->error_code); \
 348                 if (resp->resp_len >= 16) { \
 349                         struct hwrm_err_output *tmp_hwrm_err_op = \
 350                                                 (void *)resp; \
 351                         PMD_DRV_LOG(ERR, \
 352                                 "error %d:%d:%08x:%04x\n", \
 353                                 rc, tmp_hwrm_err_op->cmd_err, \
 354                                 rte_le_to_cpu_32(\
 355                                         tmp_hwrm_err_op->opaque_0), \
 356                                 rte_le_to_cpu_16(\
 357                                         tmp_hwrm_err_op->opaque_1)); \
 358                 } else { \
 359                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 360                 } \
 361                 rte_spinlock_unlock(&bp->hwrm_lock); \
 362                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 363                         rc = -EACCES; \
 364                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 365                         rc = -ENOSPC; \
 366                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 367                         rc = -EINVAL; \
 368                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 369                         rc = -ENOTSUP; \
 370                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 371                         rc = -EAGAIN; \
 372                 else if (rc > 0) \
 373                         rc = -EIO; \
 374                 return rc; \
 375         } \
 376 } while (0)
 377
 378 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 379
 380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 381                                 bool use_kong_mb,
 382                                 uint16_t msg_type,
 383                                 void *msg,
 384                                 uint32_t msg_len,
 385                                 void *resp_msg,
 386                                 uint32_t resp_len)
 387 {
 388         int rc = 0;
 389         bool mailbox = BNXT_USE_CHIMP_MB;
 390         struct input *req = msg;
 391         struct output *resp = bp->hwrm_cmd_resp_addr;
 392
 393         if (use_kong_mb)
 394                 mailbox = BNXT_USE_KONG(bp);
 395
 396         HWRM_PREP(req, msg_type, mailbox);
 397
 398         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 399
 400         HWRM_CHECK_RESULT();
 401
 402         if (resp_msg)
 403                 memcpy(resp_msg, resp, resp_len);
 404
 405         HWRM_UNLOCK();
 406
 407         return rc;
 408 }
 409
 410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 411                                   bool use_kong_mb,
 412                                   uint16_t tf_type,
 413                                   uint16_t tf_subtype,
 414                                   uint32_t *tf_response_code,
 415                                   void *msg,
 416                                   uint32_t msg_len,
 417                                   void *response,
 418                                   uint32_t response_len)
 419 {
 420         int rc = 0;
 421         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 422         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 423         bool mailbox = BNXT_USE_CHIMP_MB;
 424
 425         if (msg_len > sizeof(req.tf_req))
 426                 return -ENOMEM;
 427
 428         if (use_kong_mb)
 429                 mailbox = BNXT_USE_KONG(bp);
 430
 431         HWRM_PREP(&req, HWRM_TF, mailbox);
 432         /* Build request using the user supplied request payload.
 433          * TLV request size is checked at build time against HWRM
 434          * request max size, thus no checking required.
 435          */
 436         req.tf_type = tf_type;
 437         req.tf_subtype = tf_subtype;
 438         memcpy(req.tf_req, msg, msg_len);
 439
 440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 441         HWRM_CHECK_RESULT();
 442
 443         /* Copy the resp to user provided response buffer */
 444         if (response != NULL)
 445                 /* Post process response data. We need to copy only
 446                  * the 'payload' as the HWRM data structure really is
 447                  * HWRM header + msg header + payload and the TFLIB
 448                  * only provided a payload place holder.
 449                  */
 450                 if (response_len != 0) {
 451                         memcpy(response,
 452                                resp->tf_resp,
 453                                response_len);
 454                 }
 455
 456         /* Extract the internal tflib response code */
 457         *tf_response_code = resp->tf_resp_code;
 458         HWRM_UNLOCK();
 459
 460         return rc;
 461 }
 462
 463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 464 {
 465         int rc = 0;
 466         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 467         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 468
 469         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 470         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 471         req.mask = 0;
 472
 473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 474
 475         HWRM_CHECK_RESULT();
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 482                                  struct bnxt_vnic_info *vnic,
 483                                  uint16_t vlan_count,
 484                                  struct bnxt_vlan_table_entry *vlan_table)
 485 {
 486         int rc = 0;
 487         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 488         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 489         uint32_t mask = 0;
 490
 491         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 492                 return rc;
 493
 494         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 495         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 496
 497         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 498                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 499         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 500                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 501
 502         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 503                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 504
 505         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 506                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 507         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 508                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 509                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 510                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 511         }
 512         if (vlan_table) {
 513                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 514                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 515                 req.vlan_tag_tbl_addr =
 516                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 517                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 518         }
 519         req.mask = rte_cpu_to_le_32(mask);
 520
 521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 522
 523         HWRM_CHECK_RESULT();
 524         HWRM_UNLOCK();
 525
 526         return rc;
 527 }
 528
 529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 530                         uint16_t vlan_count,
 531                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 532 {
 533         int rc = 0;
 534         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 535         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 536                                                 bp->hwrm_cmd_resp_addr;
 537
 538         /*
 539          * Older HWRM versions did not support this command, and the set_rx_mask
 540          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 541          * removed from set_rx_mask call, and this command was added.
 542          *
 543          * This command is also present from 1.7.8.11 and higher,
 544          * as well as 1.7.8.0
 545          */
 546         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 547                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 548                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 549                                         (11)))
 550                                 return 0;
 551                 }
 552         }
 553         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 554         req.fid = rte_cpu_to_le_16(fid);
 555
 556         req.vlan_tag_mask_tbl_addr =
 557                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 558         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 559
 560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 561
 562         HWRM_CHECK_RESULT();
 563         HWRM_UNLOCK();
 564
 565         return rc;
 566 }
 567
 568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 569                              struct bnxt_filter_info *filter)
 570 {
 571         int rc = 0;
 572         struct bnxt_filter_info *l2_filter = filter;
 573         struct bnxt_vnic_info *vnic = NULL;
 574         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 575         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 576
 577         if (filter->fw_l2_filter_id == UINT64_MAX)
 578                 return 0;
 579
 580         if (filter->matching_l2_fltr_ptr)
 581                 l2_filter = filter->matching_l2_fltr_ptr;
 582
 583         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 584                     filter, l2_filter, l2_filter->l2_ref_cnt);
 585
 586         if (l2_filter->l2_ref_cnt == 0)
 587                 return 0;
 588
 589         if (l2_filter->l2_ref_cnt > 0)
 590                 l2_filter->l2_ref_cnt--;
 591
 592         if (l2_filter->l2_ref_cnt > 0)
 593                 return 0;
 594
 595         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 596
 597         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 598
 599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 600
 601         HWRM_CHECK_RESULT();
 602         HWRM_UNLOCK();
 603
 604         filter->fw_l2_filter_id = UINT64_MAX;
 605         if (l2_filter->l2_ref_cnt == 0) {
 606                 vnic = l2_filter->vnic;
 607                 if (vnic) {
 608                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 609                                       bnxt_filter_info, next);
 610                         bnxt_free_filter(bp, l2_filter);
 611                 }
 612         }
 613
 614         return 0;
 615 }
 616
 617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 618                          uint16_t dst_id,
 619                          struct bnxt_filter_info *filter)
 620 {
 621         int rc = 0;
 622         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 623         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 624         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 625         const struct rte_eth_vmdq_rx_conf *conf =
 626                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 627         uint32_t enables = 0;
 628         uint16_t j = dst_id - 1;
 629
 630         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 631         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 632             conf->pool_map[j].pools & (1UL << j)) {
 633                 PMD_DRV_LOG(DEBUG,
 634                         "Add vlan %u to vmdq pool %u\n",
 635                         conf->pool_map[j].vlan_id, j);
 636
 637                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 638                 filter->enables |=
 639                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 640                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 641         }
 642
 643         if (filter->fw_l2_filter_id != UINT64_MAX)
 644                 bnxt_hwrm_clear_l2_filter(bp, filter);
 645
 646         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 647
 648         /* PMD does not support XDP and RoCE */
 649         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 650                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 651         req.flags = rte_cpu_to_le_32(filter->flags);
 652
 653         enables = filter->enables |
 654               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 655         req.dst_id = rte_cpu_to_le_16(dst_id);
 656
 657         if (enables &
 658             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 659                 memcpy(req.l2_addr, filter->l2_addr,
 660                        RTE_ETHER_ADDR_LEN);
 661         if (enables &
 662             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 663                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 664                        RTE_ETHER_ADDR_LEN);
 665         if (enables &
 666             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 667                 req.l2_ovlan = filter->l2_ovlan;
 668         if (enables &
 669             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 670                 req.l2_ivlan = filter->l2_ivlan;
 671         if (enables &
 672             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 673                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 674         if (enables &
 675             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 676                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 677         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 678                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 679         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 680                 req.src_type = filter->src_type;
 681         if (filter->pri_hint) {
 682                 req.pri_hint = filter->pri_hint;
 683                 req.l2_filter_id_hint =
 684                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 685         }
 686
 687         req.enables = rte_cpu_to_le_32(enables);
 688
 689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 690
 691         HWRM_CHECK_RESULT();
 692
 693         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 694         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 695         HWRM_UNLOCK();
 696
 697         filter->l2_ref_cnt++;
 698
 699         return rc;
 700 }
 701
 702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 703 {
 704         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 705         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 706         uint32_t flags = 0;
 707         int rc;
 708
 709         if (!ptp)
 710                 return 0;
 711
 712         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 713
 714         if (ptp->rx_filter)
 715                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 716         else
 717                 flags |=
 718                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 719         if (ptp->tx_tstamp_en)
 720                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 721         else
 722                 flags |=
 723                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 724         req.flags = rte_cpu_to_le_32(flags);
 725         req.enables = rte_cpu_to_le_32
 726                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 727         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 728
 729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 730         HWRM_UNLOCK();
 731
 732         return rc;
 733 }
 734
 735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 736 {
 737         int rc = 0;
 738         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 739         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 740         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 741
 742         if (ptp)
 743                 return 0;
 744
 745         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 746
 747         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 748
 749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 750
 751         HWRM_CHECK_RESULT();
 752
 753         if (BNXT_CHIP_P5(bp)) {
 754                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS))
 755                         return 0;
 756         } else {
 757                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 758                         return 0;
 759         }
 760
 761         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 762                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 763
 764         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 765         if (!ptp)
 766                 return -ENOMEM;
 767
 768         if (!BNXT_CHIP_P5(bp)) {
 769                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 770                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 771                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 772                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 773                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 774                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 775                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 776                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 777                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 778                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 779                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 780                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 781                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 782                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 783                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 784                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 785                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 786                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 787         }
 788
 789         ptp->bp = bp;
 790         bp->ptp_cfg = ptp;
 791
 792         return 0;
 793 }
 794
 795 void bnxt_free_vf_info(struct bnxt *bp)
 796 {
 797         int i;
 798
 799         if (bp->pf == NULL)
 800                 return;
 801
 802         if (bp->pf->vf_info == NULL)
 803                 return;
 804
 805         for (i = 0; i < bp->pf->max_vfs; i++) {
 806                 rte_free(bp->pf->vf_info[i].vlan_table);
 807                 bp->pf->vf_info[i].vlan_table = NULL;
 808                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 809                 bp->pf->vf_info[i].vlan_as_table = NULL;
 810         }
 811         rte_free(bp->pf->vf_info);
 812         bp->pf->vf_info = NULL;
 813 }
 814
 815 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
 816 {
 817         struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
 818         int i;
 819
 820         if (vf_info)
 821                 bnxt_free_vf_info(bp);
 822
 823         vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
 824         if (vf_info == NULL) {
 825                 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
 826                 return -ENOMEM;
 827         }
 828
 829         bp->pf->max_vfs = max_vfs;
 830         for (i = 0; i < max_vfs; i++) {
 831                 vf_info[i].fid = bp->pf->first_vf_id + i;
 832                 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
 833                                                     getpagesize(), getpagesize());
 834                 if (vf_info[i].vlan_table == NULL) {
 835                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
 836                         goto err;
 837                 }
 838                 rte_mem_lock_page(vf_info[i].vlan_table);
 839
 840                 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
 841                                                        getpagesize(), getpagesize());
 842                 if (vf_info[i].vlan_as_table == NULL) {
 843                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
 844                         goto err;
 845                 }
 846                 rte_mem_lock_page(vf_info[i].vlan_as_table);
 847
 848                 STAILQ_INIT(&vf_info[i].filter);
 849         }
 850
 851         bp->pf->vf_info = vf_info;
 852
 853         return 0;
 854 err:
 855         bnxt_free_vf_info(bp);
 856         return -ENOMEM;
 857 }
 858
 859 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 860 {
 861         int rc = 0;
 862         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 863         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 864         uint16_t new_max_vfs;
 865         uint32_t flags;
 866
 867         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 868
 869         req.fid = rte_cpu_to_le_16(0xffff);
 870
 871         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 872
 873         HWRM_CHECK_RESULT();
 874
 875         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 876         flags = rte_le_to_cpu_32(resp->flags);
 877         if (BNXT_PF(bp)) {
 878                 bp->pf->port_id = resp->port_id;
 879                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 880                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 881                 new_max_vfs = bp->pdev->max_vfs;
 882                 if (new_max_vfs != bp->pf->max_vfs) {
 883                         rc = bnxt_alloc_vf_info(bp, new_max_vfs);
 884                         if (rc)
 885                                 goto unlock;
 886                 }
 887         }
 888
 889         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 890         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 891                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 892                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 893         } else {
 894                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 895         }
 896         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 897         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 898         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 899         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 900         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 901         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 902         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 903         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
 904                 bp->max_l2_ctx += bp->max_rx_em_flows;
 905         /* TODO: For now, do not support VMDq/RFS on VFs. */
 906         if (BNXT_PF(bp)) {
 907                 if (bp->pf->max_vfs)
 908                         bp->max_vnics = 1;
 909                 else
 910                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 911         } else {
 912                 bp->max_vnics = 1;
 913         }
 914         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 915                     bp->max_l2_ctx, bp->max_vnics);
 916         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 917         if (BNXT_PF(bp)) {
 918                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 919                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 920                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 921                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 922                         HWRM_UNLOCK();
 923                         bnxt_hwrm_ptp_qcfg(bp);
 924                 }
 925         }
 926
 927         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 928                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 929
 930         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 931                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 932                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 933         }
 934
 935         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 936                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 937
 938         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 939                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 940
 941         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
 942                 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
 943
 944 unlock:
 945         HWRM_UNLOCK();
 946
 947         return rc;
 948 }
 949
 950 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 951 {
 952         int rc;
 953
 954         rc = __bnxt_hwrm_func_qcaps(bp);
 955         if (rc == -ENOMEM)
 956                 return rc;
 957
 958         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 959                 rc = bnxt_alloc_ctx_mem(bp);
 960                 if (rc)
 961                         return rc;
 962
 963                 /* On older FW,
 964                  * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 965                  * But the error can be ignored. Return success.
 966                  */
 967                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 968                 if (!rc)
 969                         bp->flags |= BNXT_FLAG_NEW_RM;
 970         }
 971
 972         return 0;
 973 }
 974
 975 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 976 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 977 {
 978         int rc = 0;
 979         uint32_t flags;
 980         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 981         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 982
 983         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 984
 985         req.target_id = rte_cpu_to_le_16(0xffff);
 986
 987         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 988
 989         HWRM_CHECK_RESULT();
 990
 991         flags = rte_le_to_cpu_32(resp->flags);
 992
 993         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 994                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 995                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 996         }
 997
 998         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
 999                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
1000
1001         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
1002                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
1003
1004         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1005
1006         HWRM_UNLOCK();
1007
1008         return rc;
1009 }
1010
1011 int bnxt_hwrm_func_reset(struct bnxt *bp)
1012 {
1013         int rc = 0;
1014         struct hwrm_func_reset_input req = {.req_type = 0 };
1015         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1016
1017         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1018
1019         req.enables = rte_cpu_to_le_32(0);
1020
1021         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1022
1023         HWRM_CHECK_RESULT();
1024         HWRM_UNLOCK();
1025
1026         return rc;
1027 }
1028
1029 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1030 {
1031         int rc;
1032         uint32_t flags = 0;
1033         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1034         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1035
1036         if (bp->flags & BNXT_FLAG_REGISTERED)
1037                 return 0;
1038
1039         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1040                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1041         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1042                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1043
1044         /* PFs and trusted VFs should indicate the support of the
1045          * Master capability on non Stingray platform
1046          */
1047         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1048                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1049
1050         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1051         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1052                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1053         req.ver_maj = RTE_VER_YEAR;
1054         req.ver_min = RTE_VER_MONTH;
1055         req.ver_upd = RTE_VER_MINOR;
1056
1057         if (BNXT_PF(bp)) {
1058                 req.enables |= rte_cpu_to_le_32(
1059                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1060                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1061                        RTE_MIN(sizeof(req.vf_req_fwd),
1062                                sizeof(bp->pf->vf_req_fwd)));
1063         }
1064
1065         req.flags = rte_cpu_to_le_32(flags);
1066
1067         req.async_event_fwd[0] |=
1068                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1069                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1070                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1071                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1072                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1073         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1074                 req.async_event_fwd[0] |=
1075                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1076         req.async_event_fwd[1] |=
1077                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1078                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1079         if (BNXT_PF(bp))
1080                 req.async_event_fwd[1] |=
1081                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1082
1083         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1084                 req.async_event_fwd[1] |=
1085                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1086
1087         req.async_event_fwd[2] |=
1088                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST);
1089
1090         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1091
1092         HWRM_CHECK_RESULT();
1093
1094         flags = rte_le_to_cpu_32(resp->flags);
1095         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1096                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1097
1098         HWRM_UNLOCK();
1099
1100         bp->flags |= BNXT_FLAG_REGISTERED;
1101
1102         return rc;
1103 }
1104
1105 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1106 {
1107         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1108                 return 0;
1109
1110         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1111 }
1112
1113 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1114 {
1115         int rc;
1116         uint32_t flags = 0;
1117         uint32_t enables;
1118         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1119         struct hwrm_func_vf_cfg_input req = {0};
1120
1121         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1122
1123         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
1124                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
1125                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
1126                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1127                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1128
1129         if (BNXT_HAS_RING_GRPS(bp)) {
1130                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1131                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1132         }
1133
1134         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1135         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1136                                             AGG_RING_MULTIPLIER);
1137         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1138         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1139                                               bp->tx_nr_rings +
1140                                               BNXT_NUM_ASYNC_CPR(bp));
1141         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1142         if (bp->vf_resv_strategy ==
1143             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1144                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1145                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1146                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1147                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1148                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1149                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1150         } else if (bp->vf_resv_strategy ==
1151                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1152                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1153                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1154         }
1155
1156         if (test)
1157                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1158                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1159                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1160                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1161                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1162                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1163
1164         if (test && BNXT_HAS_RING_GRPS(bp))
1165                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1166
1167         req.flags = rte_cpu_to_le_32(flags);
1168         req.enables |= rte_cpu_to_le_32(enables);
1169
1170         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1171
1172         if (test)
1173                 HWRM_CHECK_RESULT_SILENT();
1174         else
1175                 HWRM_CHECK_RESULT();
1176
1177         HWRM_UNLOCK();
1178         return rc;
1179 }
1180
1181 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1182 {
1183         int rc;
1184         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1185         struct hwrm_func_resource_qcaps_input req = {0};
1186
1187         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1188         req.fid = rte_cpu_to_le_16(0xffff);
1189
1190         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1191
1192         HWRM_CHECK_RESULT_SILENT();
1193
1194         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1195         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1196         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1197         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1198         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1199         /* func_resource_qcaps does not return max_rx_em_flows.
1200          * So use the value provided by func_qcaps.
1201          */
1202         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1203         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1204                 bp->max_l2_ctx += bp->max_rx_em_flows;
1205         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1206         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1207         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1208         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1209         if (bp->vf_resv_strategy >
1210             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1211                 bp->vf_resv_strategy =
1212                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1213
1214         HWRM_UNLOCK();
1215         return rc;
1216 }
1217
1218 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1219 {
1220         int rc = 0;
1221         struct hwrm_ver_get_input req = {.req_type = 0 };
1222         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1223         uint32_t fw_version;
1224         uint16_t max_resp_len;
1225         char type[RTE_MEMZONE_NAMESIZE];
1226         uint32_t dev_caps_cfg;
1227
1228         bp->max_req_len = HWRM_MAX_REQ_LEN;
1229         bp->hwrm_cmd_timeout = timeout;
1230         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1231
1232         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1233         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1234         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1235
1236         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1237
1238         if (bp->flags & BNXT_FLAG_FW_RESET)
1239                 HWRM_CHECK_RESULT_SILENT();
1240         else
1241                 HWRM_CHECK_RESULT();
1242
1243         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1244                 rc = -EAGAIN;
1245                 goto error;
1246         }
1247
1248         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1249                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1250                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1251                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1252                 resp->hwrm_fw_rsvd_8b);
1253         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1254                      (resp->hwrm_fw_min_8b << 16) |
1255                      (resp->hwrm_fw_bld_8b << 8) |
1256                      resp->hwrm_fw_rsvd_8b;
1257         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1258                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1259
1260         fw_version = resp->hwrm_intf_maj_8b << 16;
1261         fw_version |= resp->hwrm_intf_min_8b << 8;
1262         fw_version |= resp->hwrm_intf_upd_8b;
1263         bp->hwrm_spec_code = fw_version;
1264
1265         /* def_req_timeout value is in milliseconds */
1266         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1267         /* convert timeout to usec */
1268         bp->hwrm_cmd_timeout *= 1000;
1269         if (!bp->hwrm_cmd_timeout)
1270                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1271
1272         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1273                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1274                 rc = -EINVAL;
1275                 goto error;
1276         }
1277
1278         if (bp->max_req_len > resp->max_req_win_len) {
1279                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1280                 rc = -EINVAL;
1281                 goto error;
1282         }
1283
1284         bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1285
1286         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1287         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1288         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1289                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1290
1291         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1292         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1293
1294         RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1295         bp->max_resp_len = max_resp_len;
1296
1297         if ((dev_caps_cfg &
1298                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1299             (dev_caps_cfg &
1300              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1301                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1302                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1303         }
1304
1305         if (((dev_caps_cfg &
1306               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1307              (dev_caps_cfg &
1308               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1309             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1310                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1311                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1312                         bp->pdev->addr.devid, bp->pdev->addr.function);
1313
1314                 rte_free(bp->hwrm_short_cmd_req_addr);
1315
1316                 bp->hwrm_short_cmd_req_addr =
1317                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1318                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1319                         rc = -ENOMEM;
1320                         goto error;
1321                 }
1322                 bp->hwrm_short_cmd_req_dma_addr =
1323                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1324                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1325                         rte_free(bp->hwrm_short_cmd_req_addr);
1326                         PMD_DRV_LOG(ERR,
1327                                 "Unable to map buffer to physical memory.\n");
1328                         rc = -ENOMEM;
1329                         goto error;
1330                 }
1331         }
1332         if (dev_caps_cfg &
1333             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1334                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1335                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1336         }
1337         if (dev_caps_cfg &
1338             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1339                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1340         if (dev_caps_cfg &
1341             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1342                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1343                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1344         }
1345
1346         if (dev_caps_cfg &
1347             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1348                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1349                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1350         }
1351
1352         if (dev_caps_cfg &
1353             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED) {
1354                 PMD_DRV_LOG(DEBUG, "Host-based truflow feature enabled.\n");
1355                 bp->fw_cap |= BNXT_FW_CAP_TRUFLOW_EN;
1356         }
1357
1358 error:
1359         HWRM_UNLOCK();
1360         return rc;
1361 }
1362
1363 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1364 {
1365         int rc;
1366         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1367         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1368
1369         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1370                 return 0;
1371
1372         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1373         req.flags = flags;
1374
1375         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1376
1377         HWRM_CHECK_RESULT();
1378         HWRM_UNLOCK();
1379
1380         PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1381                     bp->eth_dev->data->port_id);
1382
1383         return rc;
1384 }
1385
1386 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1387 {
1388         int rc = 0;
1389         struct hwrm_port_phy_cfg_input req = {0};
1390         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1391         uint32_t enables = 0;
1392
1393         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1394
1395         if (conf->link_up) {
1396                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1397                 if (bp->link_info->auto_mode && conf->link_speed) {
1398                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1399                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1400                 }
1401
1402                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1403                 /*
1404                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1405                  * any auto mode, even "none".
1406                  */
1407                 if (!conf->link_speed) {
1408                         /* No speeds specified. Enable AutoNeg - all speeds */
1409                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1410                         req.auto_mode =
1411                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1412                 } else {
1413                         if (bp->link_info->link_signal_mode) {
1414                                 enables |=
1415                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1416                                 req.force_pam4_link_speed =
1417                                         rte_cpu_to_le_16(conf->link_speed);
1418                         } else {
1419                                 req.force_link_speed =
1420                                         rte_cpu_to_le_16(conf->link_speed);
1421                         }
1422                 }
1423                 /* AutoNeg - Advertise speeds specified. */
1424                 if (conf->auto_link_speed_mask &&
1425                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1426                         req.auto_mode =
1427                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1428                         req.auto_link_speed_mask =
1429                                 conf->auto_link_speed_mask;
1430                         if (conf->auto_pam4_link_speeds) {
1431                                 enables |=
1432                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1433                                 req.auto_link_pam4_speed_mask =
1434                                         conf->auto_pam4_link_speeds;
1435                         } else {
1436                                 enables |=
1437                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1438                         }
1439                 }
1440                 if (conf->auto_link_speed &&
1441                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1442                         enables |=
1443                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1444
1445                 req.auto_duplex = conf->duplex;
1446                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1447                 req.auto_pause = conf->auto_pause;
1448                 req.force_pause = conf->force_pause;
1449                 /* Set force_pause if there is no auto or if there is a force */
1450                 if (req.auto_pause && !req.force_pause)
1451                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1452                 else
1453                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1454
1455                 req.enables = rte_cpu_to_le_32(enables);
1456         } else {
1457                 req.flags =
1458                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1459                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1460         }
1461
1462         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1463
1464         HWRM_CHECK_RESULT();
1465         HWRM_UNLOCK();
1466
1467         return rc;
1468 }
1469
1470 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1471                                    struct bnxt_link_info *link_info)
1472 {
1473         int rc = 0;
1474         struct hwrm_port_phy_qcfg_input req = {0};
1475         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1476
1477         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1478
1479         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1480
1481         HWRM_CHECK_RESULT();
1482
1483         link_info->phy_link_status = resp->link;
1484         link_info->link_up =
1485                 (link_info->phy_link_status ==
1486                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1487         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1488         link_info->duplex = resp->duplex_cfg;
1489         link_info->pause = resp->pause;
1490         link_info->auto_pause = resp->auto_pause;
1491         link_info->force_pause = resp->force_pause;
1492         link_info->auto_mode = resp->auto_mode;
1493         link_info->phy_type = resp->phy_type;
1494         link_info->media_type = resp->media_type;
1495
1496         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1497         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1498         link_info->auto_link_speed_mask = rte_le_to_cpu_16(resp->auto_link_speed_mask);
1499         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1500         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1501         link_info->phy_ver[0] = resp->phy_maj;
1502         link_info->phy_ver[1] = resp->phy_min;
1503         link_info->phy_ver[2] = resp->phy_bld;
1504         link_info->link_signal_mode =
1505                 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1506         link_info->force_pam4_link_speed =
1507                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1508         link_info->support_pam4_speeds =
1509                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1510         link_info->auto_pam4_link_speeds =
1511                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1512         link_info->module_status = resp->module_status;
1513         HWRM_UNLOCK();
1514
1515         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1516                     link_info->link_speed, link_info->auto_mode,
1517                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1518                     link_info->support_speeds, link_info->force_link_speed);
1519         PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1520                     link_info->link_signal_mode,
1521                     link_info->auto_pam4_link_speeds,
1522                     link_info->support_pam4_speeds,
1523                     link_info->force_pam4_link_speed);
1524         return rc;
1525 }
1526
1527 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1528 {
1529         int rc = 0;
1530         struct hwrm_port_phy_qcaps_input req = {0};
1531         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1532         struct bnxt_link_info *link_info = bp->link_info;
1533
1534         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1535                 return 0;
1536
1537         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1538
1539         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1540
1541         HWRM_CHECK_RESULT_SILENT();
1542
1543         bp->port_cnt = resp->port_cnt;
1544         if (resp->supported_speeds_auto_mode)
1545                 link_info->support_auto_speeds =
1546                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1547         if (resp->supported_pam4_speeds_auto_mode)
1548                 link_info->support_pam4_auto_speeds =
1549                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1550
1551         HWRM_UNLOCK();
1552
1553         /* Older firmware does not have supported_auto_speeds, so assume
1554          * that all supported speeds can be autonegotiated.
1555          */
1556         if (link_info->auto_link_speed_mask && !link_info->support_auto_speeds)
1557                 link_info->support_auto_speeds = link_info->support_speeds;
1558
1559         return 0;
1560 }
1561
1562 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1563 {
1564         int i = 0;
1565
1566         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1567                 if (bp->tx_cos_queue[i].profile ==
1568                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1569                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1570                         return true;
1571                 }
1572         }
1573         return false;
1574 }
1575
1576 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1577 {
1578         int i = 0;
1579
1580         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1581                 if (bp->tx_cos_queue[i].profile !=
1582                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1583                     bp->tx_cos_queue[i].id !=
1584                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1585                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1586                         break;
1587                 }
1588         }
1589 }
1590
1591 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1592 {
1593         int rc = 0;
1594         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1595         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1596         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1597         int i;
1598
1599 get_rx_info:
1600         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1601
1602         req.flags = rte_cpu_to_le_32(dir);
1603         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1604         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1605             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1606                 req.drv_qmap_cap =
1607                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1608         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1609
1610         HWRM_CHECK_RESULT();
1611
1612         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1613                 GET_TX_QUEUE_INFO(0);
1614                 GET_TX_QUEUE_INFO(1);
1615                 GET_TX_QUEUE_INFO(2);
1616                 GET_TX_QUEUE_INFO(3);
1617                 GET_TX_QUEUE_INFO(4);
1618                 GET_TX_QUEUE_INFO(5);
1619                 GET_TX_QUEUE_INFO(6);
1620                 GET_TX_QUEUE_INFO(7);
1621         } else  {
1622                 GET_RX_QUEUE_INFO(0);
1623                 GET_RX_QUEUE_INFO(1);
1624                 GET_RX_QUEUE_INFO(2);
1625                 GET_RX_QUEUE_INFO(3);
1626                 GET_RX_QUEUE_INFO(4);
1627                 GET_RX_QUEUE_INFO(5);
1628                 GET_RX_QUEUE_INFO(6);
1629                 GET_RX_QUEUE_INFO(7);
1630         }
1631
1632         HWRM_UNLOCK();
1633
1634         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1635                 goto done;
1636
1637         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1638                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1639         } else {
1640                 int j;
1641
1642                 /* iterate and find the COSq profile to use for Tx */
1643                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1644                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1645                                 if (bp->tx_cos_queue[i].id != 0xff)
1646                                         bp->tx_cosq_id[j++] =
1647                                                 bp->tx_cos_queue[i].id;
1648                         }
1649                 } else {
1650                         /* When CoS classification is disabled, for normal NIC
1651                          * operations, ideally we should look to use LOSSY.
1652                          * If not found, fallback to the first valid profile
1653                          */
1654                         if (!bnxt_find_lossy_profile(bp))
1655                                 bnxt_find_first_valid_profile(bp);
1656
1657                 }
1658         }
1659
1660         bp->max_tc = resp->max_configurable_queues;
1661         bp->max_lltc = resp->max_configurable_lossless_queues;
1662         if (bp->max_tc > BNXT_MAX_QUEUE)
1663                 bp->max_tc = BNXT_MAX_QUEUE;
1664         bp->max_q = bp->max_tc;
1665
1666         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1667                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1668                 goto get_rx_info;
1669         }
1670
1671 done:
1672         return rc;
1673 }
1674
1675 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1676                          struct bnxt_ring *ring,
1677                          uint32_t ring_type, uint32_t map_index,
1678                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1679                          uint16_t tx_cosq_id)
1680 {
1681         int rc = 0;
1682         uint32_t enables = 0;
1683         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1684         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1685         struct rte_mempool *mb_pool;
1686         uint16_t rx_buf_size;
1687
1688         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1689
1690         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1691         req.fbo = rte_cpu_to_le_32(0);
1692         /* Association of ring index with doorbell index */
1693         req.logical_id = rte_cpu_to_le_16(map_index);
1694         req.length = rte_cpu_to_le_32(ring->ring_size);
1695
1696         switch (ring_type) {
1697         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1698                 req.ring_type = ring_type;
1699                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1700                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1701                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1702                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1703                         enables |=
1704                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1705                 break;
1706         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1707                 req.ring_type = ring_type;
1708                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1709                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1710                 if (BNXT_CHIP_P5(bp)) {
1711                         mb_pool = bp->rx_queues[0]->mb_pool;
1712                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1713                                       RTE_PKTMBUF_HEADROOM;
1714                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1715                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1716                         enables |=
1717                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1718                 }
1719                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1720                         enables |=
1721                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1722                 break;
1723         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1724                 req.ring_type = ring_type;
1725                 if (BNXT_HAS_NQ(bp)) {
1726                         /* Association of cp ring with nq */
1727                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1728                         enables |=
1729                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1730                 }
1731                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1732                 break;
1733         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1734                 req.ring_type = ring_type;
1735                 req.page_size = BNXT_PAGE_SHFT;
1736                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1737                 break;
1738         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1739                 req.ring_type = ring_type;
1740                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1741
1742                 mb_pool = bp->rx_queues[0]->mb_pool;
1743                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1744                               RTE_PKTMBUF_HEADROOM;
1745                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1746                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1747
1748                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1749                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1750                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1751                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1752                 break;
1753         default:
1754                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1755                         ring_type);
1756                 HWRM_UNLOCK();
1757                 return -EINVAL;
1758         }
1759         req.enables = rte_cpu_to_le_32(enables);
1760
1761         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1762
1763         if (rc || resp->error_code) {
1764                 if (rc == 0 && resp->error_code)
1765                         rc = rte_le_to_cpu_16(resp->error_code);
1766                 switch (ring_type) {
1767                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1768                         PMD_DRV_LOG(ERR,
1769                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1770                         HWRM_UNLOCK();
1771                         return rc;
1772                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1773                         PMD_DRV_LOG(ERR,
1774                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1775                         HWRM_UNLOCK();
1776                         return rc;
1777                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1778                         PMD_DRV_LOG(ERR,
1779                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1780                                     rc);
1781                         HWRM_UNLOCK();
1782                         return rc;
1783                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1784                         PMD_DRV_LOG(ERR,
1785                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1786                         HWRM_UNLOCK();
1787                         return rc;
1788                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1789                         PMD_DRV_LOG(ERR,
1790                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1791                         HWRM_UNLOCK();
1792                         return rc;
1793                 default:
1794                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1795                         HWRM_UNLOCK();
1796                         return rc;
1797                 }
1798         }
1799
1800         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1801         HWRM_UNLOCK();
1802         return rc;
1803 }
1804
1805 int bnxt_hwrm_ring_free(struct bnxt *bp,
1806                         struct bnxt_ring *ring, uint32_t ring_type,
1807                         uint16_t cp_ring_id)
1808 {
1809         int rc;
1810         struct hwrm_ring_free_input req = {.req_type = 0 };
1811         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1812
1813         if (ring->fw_ring_id == INVALID_HW_RING_ID)
1814                 return -EINVAL;
1815
1816         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1817
1818         req.ring_type = ring_type;
1819         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1820         req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1821
1822         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1823         ring->fw_ring_id = INVALID_HW_RING_ID;
1824
1825         if (rc || resp->error_code) {
1826                 if (rc == 0 && resp->error_code)
1827                         rc = rte_le_to_cpu_16(resp->error_code);
1828                 HWRM_UNLOCK();
1829
1830                 switch (ring_type) {
1831                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1832                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1833                                 rc);
1834                         return rc;
1835                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1836                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1837                                 rc);
1838                         return rc;
1839                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1840                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1841                                 rc);
1842                         return rc;
1843                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1844                         PMD_DRV_LOG(ERR,
1845                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1846                         return rc;
1847                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1848                         PMD_DRV_LOG(ERR,
1849                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1850                         return rc;
1851                 default:
1852                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1853                         return rc;
1854                 }
1855         }
1856         HWRM_UNLOCK();
1857         return 0;
1858 }
1859
1860 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1861 {
1862         int rc = 0;
1863         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1864         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1865
1866         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1867
1868         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1869         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1870         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1871         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1872
1873         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1874
1875         HWRM_CHECK_RESULT();
1876
1877         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1878
1879         HWRM_UNLOCK();
1880
1881         return rc;
1882 }
1883
1884 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1885 {
1886         int rc;
1887         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1888         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1889
1890         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1891
1892         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1893
1894         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1895
1896         HWRM_CHECK_RESULT();
1897         HWRM_UNLOCK();
1898
1899         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1900         return rc;
1901 }
1902
1903 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1904 {
1905         int rc = 0;
1906         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1907         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1908
1909         if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1910                 return rc;
1911
1912         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1913
1914         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1915
1916         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1917
1918         HWRM_CHECK_RESULT();
1919         HWRM_UNLOCK();
1920
1921         return rc;
1922 }
1923
1924 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1925 {
1926         int rc;
1927         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1928         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1929
1930         if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE)
1931                 return 0;
1932
1933         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1934
1935         req.update_period_ms = rte_cpu_to_le_32(0);
1936
1937         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1938
1939         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1940
1941         HWRM_CHECK_RESULT();
1942
1943         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1944
1945         HWRM_UNLOCK();
1946
1947         return rc;
1948 }
1949
1950 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1951 {
1952         int rc;
1953         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1954         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1955
1956         if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1957                 return 0;
1958
1959         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1960
1961         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1962
1963         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1964
1965         HWRM_CHECK_RESULT();
1966         HWRM_UNLOCK();
1967
1968         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1969
1970         return rc;
1971 }
1972
1973 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1974 {
1975         int rc = 0, i, j;
1976         struct hwrm_vnic_alloc_input req = { 0 };
1977         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1978
1979         if (!BNXT_HAS_RING_GRPS(bp))
1980                 goto skip_ring_grps;
1981
1982         /* map ring groups to this vnic */
1983         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1984                 vnic->start_grp_id, vnic->end_grp_id);
1985         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1986                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1987
1988         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1989         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1990         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1991         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1992
1993 skip_ring_grps:
1994         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1995         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1996
1997         if (vnic->func_default)
1998                 req.flags =
1999                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
2000         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2001
2002         HWRM_CHECK_RESULT();
2003
2004         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
2005         HWRM_UNLOCK();
2006         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2007         return rc;
2008 }
2009
2010 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
2011                                         struct bnxt_vnic_info *vnic,
2012                                         struct bnxt_plcmodes_cfg *pmode)
2013 {
2014         int rc = 0;
2015         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
2016         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2017
2018         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
2019
2020         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2021
2022         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2023
2024         HWRM_CHECK_RESULT();
2025
2026         pmode->flags = rte_le_to_cpu_32(resp->flags);
2027         /* dflt_vnic bit doesn't exist in the _cfg command */
2028         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
2029         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2030         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2031         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2032
2033         HWRM_UNLOCK();
2034
2035         return rc;
2036 }
2037
2038 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2039                                        struct bnxt_vnic_info *vnic,
2040                                        struct bnxt_plcmodes_cfg *pmode)
2041 {
2042         int rc = 0;
2043         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2044         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2045
2046         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2047                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2048                 return rc;
2049         }
2050
2051         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2052
2053         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2054         req.flags = rte_cpu_to_le_32(pmode->flags);
2055         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2056         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2057         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2058         req.enables = rte_cpu_to_le_32(
2059             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2060             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2061             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2062         );
2063
2064         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2065
2066         HWRM_CHECK_RESULT();
2067         HWRM_UNLOCK();
2068
2069         return rc;
2070 }
2071
2072 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2073 {
2074         int rc = 0;
2075         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2076         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2077         struct bnxt_plcmodes_cfg pmodes = { 0 };
2078         uint32_t ctx_enable_flag = 0;
2079         uint32_t enables = 0;
2080
2081         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2082                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2083                 return rc;
2084         }
2085
2086         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2087         if (rc)
2088                 return rc;
2089
2090         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2091
2092         if (BNXT_CHIP_P5(bp)) {
2093                 int dflt_rxq = vnic->start_grp_id;
2094                 struct bnxt_rx_ring_info *rxr;
2095                 struct bnxt_cp_ring_info *cpr;
2096                 struct bnxt_rx_queue *rxq;
2097                 int i;
2098
2099                 /*
2100                  * The first active receive ring is used as the VNIC
2101                  * default receive ring. If there are no active receive
2102                  * rings (all corresponding receive queues are stopped),
2103                  * the first receive ring is used.
2104                  */
2105                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2106                         rxq = bp->eth_dev->data->rx_queues[i];
2107                         if (rxq->rx_started) {
2108                                 dflt_rxq = i;
2109                                 break;
2110                         }
2111                 }
2112
2113                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2114                 rxr = rxq->rx_ring;
2115                 cpr = rxq->cp_ring;
2116
2117                 req.default_rx_ring_id =
2118                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2119                 req.default_cmpl_ring_id =
2120                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2121                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2122                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2123                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2124                         enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2125                         req.rx_csum_v2_mode =
2126                                 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2127                 }
2128                 goto config_mru;
2129         }
2130
2131         /* Only RSS support for now TBD: COS & LB */
2132         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2133         if (vnic->lb_rule != 0xffff)
2134                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2135         if (vnic->cos_rule != 0xffff)
2136                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2137         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2138                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2139                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2140         }
2141         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2142                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2143                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2144         }
2145
2146         enables |= ctx_enable_flag;
2147         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2148         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2149         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2150         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2151
2152 config_mru:
2153         req.enables = rte_cpu_to_le_32(enables);
2154         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2155         req.mru = rte_cpu_to_le_16(vnic->mru);
2156         /* Configure default VNIC only once. */
2157         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2158                 req.flags |=
2159                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2160                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2161         }
2162         if (vnic->vlan_strip)
2163                 req.flags |=
2164                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2165         if (vnic->bd_stall)
2166                 req.flags |=
2167                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2168         if (vnic->rss_dflt_cr)
2169                 req.flags |= rte_cpu_to_le_32(
2170                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2171
2172         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2173
2174         HWRM_CHECK_RESULT();
2175         HWRM_UNLOCK();
2176
2177         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2178
2179         return rc;
2180 }
2181
2182 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2183                 int16_t fw_vf_id)
2184 {
2185         int rc = 0;
2186         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2187         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2188
2189         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2190                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2191                 return rc;
2192         }
2193         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2194
2195         req.enables =
2196                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2197         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2198         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2199
2200         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2201
2202         HWRM_CHECK_RESULT();
2203
2204         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2205         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2206         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2207         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2208         vnic->mru = rte_le_to_cpu_16(resp->mru);
2209         vnic->func_default = rte_le_to_cpu_32(
2210                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2211         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2212                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2213         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2214                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2215         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2216                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2217
2218         HWRM_UNLOCK();
2219
2220         return rc;
2221 }
2222
2223 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2224                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2225 {
2226         int rc = 0;
2227         uint16_t ctx_id;
2228         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2229         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2230                                                 bp->hwrm_cmd_resp_addr;
2231
2232         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2233
2234         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2235         HWRM_CHECK_RESULT();
2236
2237         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2238         if (!BNXT_HAS_RING_GRPS(bp))
2239                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2240         else if (ctx_idx == 0)
2241                 vnic->rss_rule = ctx_id;
2242
2243         HWRM_UNLOCK();
2244
2245         return rc;
2246 }
2247
2248 static
2249 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2250                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2251 {
2252         int rc = 0;
2253         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2254         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2255                                                 bp->hwrm_cmd_resp_addr;
2256
2257         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2258                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2259                 return rc;
2260         }
2261         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2262
2263         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2264
2265         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2266
2267         HWRM_CHECK_RESULT();
2268         HWRM_UNLOCK();
2269
2270         return rc;
2271 }
2272
2273 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2274 {
2275         int rc = 0;
2276
2277         if (BNXT_CHIP_P5(bp)) {
2278                 int j;
2279
2280                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2281                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2282                                                       vnic,
2283                                                       vnic->fw_grp_ids[j]);
2284                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2285                 }
2286                 vnic->num_lb_ctxts = 0;
2287         } else {
2288                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2289                 vnic->rss_rule = INVALID_HW_RING_ID;
2290         }
2291
2292         return rc;
2293 }
2294
2295 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2296 {
2297         int rc = 0;
2298         struct hwrm_vnic_free_input req = {.req_type = 0 };
2299         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2300
2301         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2302                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2303                 return rc;
2304         }
2305
2306         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2307
2308         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2309
2310         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2311
2312         HWRM_CHECK_RESULT();
2313         HWRM_UNLOCK();
2314
2315         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2316         /* Configure default VNIC again if necessary. */
2317         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2318                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2319
2320         return rc;
2321 }
2322
2323 static int
2324 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2325 {
2326         int i;
2327         int rc = 0;
2328         int nr_ctxs = vnic->num_lb_ctxts;
2329         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2330         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2331
2332         for (i = 0; i < nr_ctxs; i++) {
2333                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2334
2335                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2336                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2337                 req.hash_mode_flags = vnic->hash_mode;
2338
2339                 req.hash_key_tbl_addr =
2340                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2341
2342                 req.ring_grp_tbl_addr =
2343                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2344                                          i * HW_HASH_INDEX_SIZE);
2345                 req.ring_table_pair_index = i;
2346                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2347
2348                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2349                                             BNXT_USE_CHIMP_MB);
2350
2351                 HWRM_CHECK_RESULT();
2352                 HWRM_UNLOCK();
2353         }
2354
2355         return rc;
2356 }
2357
2358 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2359                            struct bnxt_vnic_info *vnic)
2360 {
2361         int rc = 0;
2362         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2363         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2364
2365         if (!vnic->rss_table)
2366                 return 0;
2367
2368         if (BNXT_CHIP_P5(bp))
2369                 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2370
2371         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2372
2373         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2374         req.hash_mode_flags = vnic->hash_mode;
2375
2376         req.ring_grp_tbl_addr =
2377             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2378         req.hash_key_tbl_addr =
2379             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2380         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2381         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2382
2383         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2384
2385         HWRM_CHECK_RESULT();
2386         HWRM_UNLOCK();
2387
2388         return rc;
2389 }
2390
2391 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2392                         struct bnxt_vnic_info *vnic)
2393 {
2394         int rc = 0;
2395         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2396         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2397         uint16_t size;
2398
2399         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2400                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2401                 return rc;
2402         }
2403
2404         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2405
2406         req.flags = rte_cpu_to_le_32(
2407                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2408
2409         req.enables = rte_cpu_to_le_32(
2410                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2411
2412         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2413         size -= RTE_PKTMBUF_HEADROOM;
2414         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2415
2416         req.jumbo_thresh = rte_cpu_to_le_16(size);
2417         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2418
2419         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2420
2421         HWRM_CHECK_RESULT();
2422         HWRM_UNLOCK();
2423
2424         return rc;
2425 }
2426
2427 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2428                         struct bnxt_vnic_info *vnic, bool enable)
2429 {
2430         int rc = 0;
2431         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2432         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2433
2434         if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2435                 if (enable)
2436                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2437                 return -ENOTSUP;
2438         }
2439
2440         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2441                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2442                 return 0;
2443         }
2444
2445         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2446
2447         if (enable) {
2448                 req.enables = rte_cpu_to_le_32(
2449                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2450                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2451                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2452                 req.flags = rte_cpu_to_le_32(
2453                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2454                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2455                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2456                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2457                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2458                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2459                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2460                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2461                 req.min_agg_len = rte_cpu_to_le_32(512);
2462         }
2463         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2464
2465         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2466
2467         HWRM_CHECK_RESULT();
2468         HWRM_UNLOCK();
2469
2470         return rc;
2471 }
2472
2473 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2474 {
2475         struct hwrm_func_cfg_input req = {0};
2476         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2477         int rc;
2478
2479         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2480         req.enables = rte_cpu_to_le_32(
2481                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2482         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2483         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2484
2485         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2486
2487         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2488         HWRM_CHECK_RESULT();
2489         HWRM_UNLOCK();
2490
2491         bp->pf->vf_info[vf].random_mac = false;
2492
2493         return rc;
2494 }
2495
2496 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2497                                   uint64_t *dropped)
2498 {
2499         int rc = 0;
2500         struct hwrm_func_qstats_input req = {.req_type = 0};
2501         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2502
2503         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2504
2505         req.fid = rte_cpu_to_le_16(fid);
2506
2507         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2508
2509         HWRM_CHECK_RESULT();
2510
2511         if (dropped)
2512                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2513
2514         HWRM_UNLOCK();
2515
2516         return rc;
2517 }
2518
2519 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2520                           struct rte_eth_stats *stats,
2521                           struct hwrm_func_qstats_output *func_qstats)
2522 {
2523         int rc = 0;
2524         struct hwrm_func_qstats_input req = {.req_type = 0};
2525         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2526
2527         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2528
2529         req.fid = rte_cpu_to_le_16(fid);
2530
2531         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2532
2533         HWRM_CHECK_RESULT();
2534         if (func_qstats)
2535                 memcpy(func_qstats, resp,
2536                        sizeof(struct hwrm_func_qstats_output));
2537
2538         if (!stats)
2539                 goto exit;
2540
2541         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2542         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2543         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2544         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2545         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2546         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2547
2548         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2549         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2550         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2551         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2552         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2553         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2554
2555         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2556         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2557         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2558
2559 exit:
2560         HWRM_UNLOCK();
2561
2562         return rc;
2563 }
2564
2565 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2566 {
2567         int rc = 0;
2568         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2569         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2570
2571         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2572
2573         req.fid = rte_cpu_to_le_16(fid);
2574
2575         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2576
2577         HWRM_CHECK_RESULT();
2578         HWRM_UNLOCK();
2579
2580         return rc;
2581 }
2582
2583 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2584 {
2585         unsigned int i;
2586         int rc = 0;
2587
2588         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2589                 struct bnxt_tx_queue *txq;
2590                 struct bnxt_rx_queue *rxq;
2591                 struct bnxt_cp_ring_info *cpr;
2592
2593                 if (i >= bp->rx_cp_nr_rings) {
2594                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2595                         cpr = txq->cp_ring;
2596                 } else {
2597                         rxq = bp->rx_queues[i];
2598                         cpr = rxq->cp_ring;
2599                 }
2600
2601                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2602                 if (rc)
2603                         return rc;
2604         }
2605         return 0;
2606 }
2607
2608 static int
2609 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2610 {
2611         int rc;
2612         unsigned int i;
2613         struct bnxt_cp_ring_info *cpr;
2614
2615         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2616
2617                 cpr = bp->rx_queues[i]->cp_ring;
2618                 if (BNXT_HAS_RING_GRPS(bp))
2619                         bp->grp_info[i].fw_stats_ctx = -1;
2620                 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2621                 if (rc)
2622                         return rc;
2623         }
2624
2625         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2626                 cpr = bp->tx_queues[i]->cp_ring;
2627                 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2628                 if (rc)
2629                         return rc;
2630         }
2631
2632         return 0;
2633 }
2634
2635 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2636 {
2637         struct bnxt_cp_ring_info *cpr;
2638         unsigned int i;
2639         int rc = 0;
2640
2641         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2642                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
2643
2644                 cpr = rxq->cp_ring;
2645                 if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE) {
2646                         rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2647                         if (rc)
2648                                 return rc;
2649                 }
2650         }
2651
2652         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2653                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2654
2655                 cpr = txq->cp_ring;
2656                 if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE) {
2657                         rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2658                         if (rc)
2659                                 return rc;
2660                 }
2661         }
2662
2663         return rc;
2664 }
2665
2666 static int
2667 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2668 {
2669         uint16_t idx;
2670         uint32_t rc = 0;
2671
2672         if (!BNXT_HAS_RING_GRPS(bp))
2673                 return 0;
2674
2675         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2676
2677                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2678                         continue;
2679
2680                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2681
2682                 if (rc)
2683                         return rc;
2684         }
2685         return rc;
2686 }
2687
2688 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2689 {
2690         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2691
2692         bnxt_hwrm_ring_free(bp, cp_ring,
2693                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2694                             INVALID_HW_RING_ID);
2695         memset(cpr->cp_desc_ring, 0,
2696                cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2697         cpr->cp_raw_cons = 0;
2698 }
2699
2700 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2701 {
2702         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2703
2704         bnxt_hwrm_ring_free(bp, cp_ring,
2705                             HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2706                             INVALID_HW_RING_ID);
2707         memset(cpr->cp_desc_ring, 0,
2708                cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2709         cpr->cp_raw_cons = 0;
2710 }
2711
2712 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2713 {
2714         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2715         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2716         struct bnxt_ring *ring = rxr->rx_ring_struct;
2717         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2718
2719         bnxt_hwrm_ring_free(bp, ring,
2720                             HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2721                             cpr->cp_ring_struct->fw_ring_id);
2722         if (BNXT_HAS_RING_GRPS(bp))
2723                 bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID;
2724
2725         ring = rxr->ag_ring_struct;
2726         bnxt_hwrm_ring_free(bp, ring,
2727                             BNXT_CHIP_P5(bp) ?
2728                             HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2729                             HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2730                             cpr->cp_ring_struct->fw_ring_id);
2731         if (BNXT_HAS_RING_GRPS(bp))
2732                 bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID;
2733
2734         bnxt_hwrm_stat_ctx_free(bp, cpr);
2735
2736         bnxt_free_cp_ring(bp, cpr);
2737
2738         if (BNXT_HAS_RING_GRPS(bp))
2739                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2740 }
2741
2742 int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int queue_index)
2743 {
2744         int rc;
2745         struct hwrm_ring_reset_input req = {.req_type = 0 };
2746         struct hwrm_ring_reset_output *resp = bp->hwrm_cmd_resp_addr;
2747
2748         HWRM_PREP(&req, HWRM_RING_RESET, BNXT_USE_CHIMP_MB);
2749
2750         req.ring_type = HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP;
2751         req.ring_id = rte_cpu_to_le_16(bp->grp_info[queue_index].fw_grp_id);
2752         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2753
2754         HWRM_CHECK_RESULT();
2755
2756         HWRM_UNLOCK();
2757
2758         return rc;
2759 }
2760
2761 static int
2762 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2763 {
2764         unsigned int i;
2765
2766         for (i = 0; i < bp->tx_cp_nr_rings; i++)
2767                 bnxt_free_hwrm_tx_ring(bp, i);
2768
2769         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2770                 bnxt_free_hwrm_rx_ring(bp, i);
2771
2772         return 0;
2773 }
2774
2775 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2776 {
2777         uint16_t i;
2778         uint32_t rc = 0;
2779
2780         if (!BNXT_HAS_RING_GRPS(bp))
2781                 return 0;
2782
2783         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2784                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2785                 if (rc)
2786                         return rc;
2787         }
2788         return rc;
2789 }
2790
2791 /*
2792  * HWRM utility functions
2793  */
2794
2795 void bnxt_free_hwrm_resources(struct bnxt *bp)
2796 {
2797         /* Release memzone */
2798         rte_free(bp->hwrm_cmd_resp_addr);
2799         rte_free(bp->hwrm_short_cmd_req_addr);
2800         bp->hwrm_cmd_resp_addr = NULL;
2801         bp->hwrm_short_cmd_req_addr = NULL;
2802         bp->hwrm_cmd_resp_dma_addr = 0;
2803         bp->hwrm_short_cmd_req_dma_addr = 0;
2804 }
2805
2806 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2807 {
2808         struct rte_pci_device *pdev = bp->pdev;
2809         char type[RTE_MEMZONE_NAMESIZE];
2810
2811         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2812                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2813         bp->max_resp_len = BNXT_PAGE_SIZE;
2814         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2815         if (bp->hwrm_cmd_resp_addr == NULL)
2816                 return -ENOMEM;
2817         bp->hwrm_cmd_resp_dma_addr =
2818                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2819         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2820                 PMD_DRV_LOG(ERR,
2821                         "unable to map response address to physical memory\n");
2822                 return -ENOMEM;
2823         }
2824         rte_spinlock_init(&bp->hwrm_lock);
2825
2826         return 0;
2827 }
2828
2829 int
2830 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2831 {
2832         int rc = 0;
2833
2834         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2835                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2836                 if (rc)
2837                         return rc;
2838         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2839                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2840                 if (rc)
2841                         return rc;
2842         }
2843
2844         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2845         return rc;
2846 }
2847
2848 static int
2849 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2850 {
2851         struct bnxt_filter_info *filter;
2852         int rc = 0;
2853
2854         STAILQ_FOREACH(filter, &vnic->filter, next) {
2855                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2856                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2857                 bnxt_free_filter(bp, filter);
2858         }
2859         return rc;
2860 }
2861
2862 static int
2863 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2864 {
2865         struct bnxt_filter_info *filter;
2866         struct rte_flow *flow;
2867         int rc = 0;
2868
2869         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2870                 flow = STAILQ_FIRST(&vnic->flow_list);
2871                 filter = flow->filter;
2872                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2873                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2874
2875                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2876                 rte_free(flow);
2877         }
2878         return rc;
2879 }
2880
2881 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2882 {
2883         struct bnxt_filter_info *filter;
2884         int rc = 0;
2885
2886         STAILQ_FOREACH(filter, &vnic->filter, next) {
2887                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2888                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2889                                                      filter);
2890                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2891                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2892                                                          filter);
2893                 else
2894                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2895                                                      filter);
2896                 if (rc)
2897                         break;
2898         }
2899         return rc;
2900 }
2901
2902 static void
2903 bnxt_free_tunnel_ports(struct bnxt *bp)
2904 {
2905         if (bp->vxlan_port_cnt)
2906                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2907                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2908
2909         if (bp->geneve_port_cnt)
2910                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2911                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2912 }
2913
2914 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2915 {
2916         int i;
2917
2918         if (bp->vnic_info == NULL)
2919                 return;
2920
2921         /*
2922          * Cleanup VNICs in reverse order, to make sure the L2 filter
2923          * from vnic0 is last to be cleaned up.
2924          */
2925         for (i = bp->max_vnics - 1; i >= 0; i--) {
2926                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2927
2928                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2929                         continue;
2930
2931                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2932
2933                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2934
2935                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2936
2937                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2938
2939                 bnxt_hwrm_vnic_free(bp, vnic);
2940
2941                 rte_free(vnic->fw_grp_ids);
2942         }
2943         /* Ring resources */
2944         bnxt_free_all_hwrm_rings(bp);
2945         bnxt_free_all_hwrm_ring_grps(bp);
2946         bnxt_free_all_hwrm_stat_ctxs(bp);
2947         bnxt_free_tunnel_ports(bp);
2948 }
2949
2950 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2951 {
2952         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2953
2954         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2955                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2956
2957         switch (conf_link_speed) {
2958         case ETH_LINK_SPEED_10M_HD:
2959         case ETH_LINK_SPEED_100M_HD:
2960                 /* FALLTHROUGH */
2961                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2962         }
2963         return hw_link_duplex;
2964 }
2965
2966 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2967 {
2968         return !conf_link;
2969 }
2970
2971 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2972                                           uint16_t pam4_link)
2973 {
2974         uint16_t eth_link_speed = 0;
2975
2976         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2977                 return ETH_LINK_SPEED_AUTONEG;
2978
2979         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2980         case ETH_LINK_SPEED_100M:
2981         case ETH_LINK_SPEED_100M_HD:
2982                 /* FALLTHROUGH */
2983                 eth_link_speed =
2984                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2985                 break;
2986         case ETH_LINK_SPEED_1G:
2987                 eth_link_speed =
2988                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2989                 break;
2990         case ETH_LINK_SPEED_2_5G:
2991                 eth_link_speed =
2992                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2993                 break;
2994         case ETH_LINK_SPEED_10G:
2995                 eth_link_speed =
2996                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2997                 break;
2998         case ETH_LINK_SPEED_20G:
2999                 eth_link_speed =
3000                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
3001                 break;
3002         case ETH_LINK_SPEED_25G:
3003                 eth_link_speed =
3004                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
3005                 break;
3006         case ETH_LINK_SPEED_40G:
3007                 eth_link_speed =
3008                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
3009                 break;
3010         case ETH_LINK_SPEED_50G:
3011                 eth_link_speed = pam4_link ?
3012                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
3013                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
3014                 break;
3015         case ETH_LINK_SPEED_100G:
3016                 eth_link_speed = pam4_link ?
3017                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
3018                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
3019                 break;
3020         case ETH_LINK_SPEED_200G:
3021                 eth_link_speed =
3022                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3023                 break;
3024         default:
3025                 PMD_DRV_LOG(ERR,
3026                         "Unsupported link speed %d; default to AUTO\n",
3027                         conf_link_speed);
3028                 break;
3029         }
3030         return eth_link_speed;
3031 }
3032
3033 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
3034                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
3035                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
3036                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
3037                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
3038
3039 static int bnxt_validate_link_speed(struct bnxt *bp)
3040 {
3041         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3042         uint16_t port_id = bp->eth_dev->data->port_id;
3043         uint32_t link_speed_capa;
3044         uint32_t one_speed;
3045
3046         if (link_speed == ETH_LINK_SPEED_AUTONEG)
3047                 return 0;
3048
3049         link_speed_capa = bnxt_get_speed_capabilities(bp);
3050
3051         if (link_speed & ETH_LINK_SPEED_FIXED) {
3052                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
3053
3054                 if (one_speed & (one_speed - 1)) {
3055                         PMD_DRV_LOG(ERR,
3056                                 "Invalid advertised speeds (%u) for port %u\n",
3057                                 link_speed, port_id);
3058                         return -EINVAL;
3059                 }
3060                 if ((one_speed & link_speed_capa) != one_speed) {
3061                         PMD_DRV_LOG(ERR,
3062                                 "Unsupported advertised speed (%u) for port %u\n",
3063                                 link_speed, port_id);
3064                         return -EINVAL;
3065                 }
3066         } else {
3067                 if (!(link_speed & link_speed_capa)) {
3068                         PMD_DRV_LOG(ERR,
3069                                 "Unsupported advertised speeds (%u) for port %u\n",
3070                                 link_speed, port_id);
3071                         return -EINVAL;
3072                 }
3073         }
3074         return 0;
3075 }
3076
3077 static uint16_t
3078 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3079 {
3080         uint16_t ret = 0;
3081
3082         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
3083                 if (bp->link_info->support_speeds)
3084                         return bp->link_info->support_speeds;
3085                 link_speed = BNXT_SUPPORTED_SPEEDS;
3086         }
3087
3088         if (link_speed & ETH_LINK_SPEED_100M)
3089                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3090         if (link_speed & ETH_LINK_SPEED_100M_HD)
3091                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3092         if (link_speed & ETH_LINK_SPEED_1G)
3093                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3094         if (link_speed & ETH_LINK_SPEED_2_5G)
3095                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3096         if (link_speed & ETH_LINK_SPEED_10G)
3097                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3098         if (link_speed & ETH_LINK_SPEED_20G)
3099                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3100         if (link_speed & ETH_LINK_SPEED_25G)
3101                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3102         if (link_speed & ETH_LINK_SPEED_40G)
3103                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3104         if (link_speed & ETH_LINK_SPEED_50G)
3105                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3106         if (link_speed & ETH_LINK_SPEED_100G)
3107                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3108         if (link_speed & ETH_LINK_SPEED_200G)
3109                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3110         return ret;
3111 }
3112
3113 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3114 {
3115         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
3116
3117         switch (hw_link_speed) {
3118         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3119                 eth_link_speed = ETH_SPEED_NUM_100M;
3120                 break;
3121         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3122                 eth_link_speed = ETH_SPEED_NUM_1G;
3123                 break;
3124         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3125                 eth_link_speed = ETH_SPEED_NUM_2_5G;
3126                 break;
3127         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3128                 eth_link_speed = ETH_SPEED_NUM_10G;
3129                 break;
3130         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3131                 eth_link_speed = ETH_SPEED_NUM_20G;
3132                 break;
3133         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3134                 eth_link_speed = ETH_SPEED_NUM_25G;
3135                 break;
3136         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3137                 eth_link_speed = ETH_SPEED_NUM_40G;
3138                 break;
3139         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3140                 eth_link_speed = ETH_SPEED_NUM_50G;
3141                 break;
3142         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3143                 eth_link_speed = ETH_SPEED_NUM_100G;
3144                 break;
3145         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3146                 eth_link_speed = ETH_SPEED_NUM_200G;
3147                 break;
3148         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3149         default:
3150                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3151                         hw_link_speed);
3152                 break;
3153         }
3154         return eth_link_speed;
3155 }
3156
3157 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3158 {
3159         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3160
3161         switch (hw_link_duplex) {
3162         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3163         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3164                 /* FALLTHROUGH */
3165                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3166                 break;
3167         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3168                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3169                 break;
3170         default:
3171                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3172                         hw_link_duplex);
3173                 break;
3174         }
3175         return eth_link_duplex;
3176 }
3177
3178 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3179 {
3180         int rc = 0;
3181         struct bnxt_link_info *link_info = bp->link_info;
3182
3183         rc = bnxt_hwrm_port_phy_qcaps(bp);
3184         if (rc)
3185                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3186
3187         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3188         if (rc) {
3189                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3190                 goto exit;
3191         }
3192
3193         if (link_info->link_speed)
3194                 link->link_speed =
3195                         bnxt_parse_hw_link_speed(link_info->link_speed);
3196         else
3197                 link->link_speed = ETH_SPEED_NUM_NONE;
3198         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3199         link->link_status = link_info->link_up;
3200         link->link_autoneg = link_info->auto_mode ==
3201                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3202                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3203 exit:
3204         return rc;
3205 }
3206
3207 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3208 {
3209         int rc = 0;
3210         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3211         struct bnxt_link_info link_req;
3212         uint16_t speed, autoneg;
3213
3214         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3215                 return 0;
3216
3217         rc = bnxt_validate_link_speed(bp);
3218         if (rc)
3219                 goto error;
3220
3221         memset(&link_req, 0, sizeof(link_req));
3222         link_req.link_up = link_up;
3223         if (!link_up)
3224                 goto port_phy_cfg;
3225
3226         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3227         if (BNXT_CHIP_P5(bp) &&
3228             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3229                 /* 40G is not supported as part of media auto detect.
3230                  * The speed should be forced and autoneg disabled
3231                  * to configure 40G speed.
3232                  */
3233                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3234                 autoneg = 0;
3235         }
3236
3237         /* No auto speeds and no auto_pam4_link. Disable autoneg */
3238         if (bp->link_info->auto_link_speed == 0 &&
3239             bp->link_info->link_signal_mode &&
3240             bp->link_info->auto_pam4_link_speeds == 0)
3241                 autoneg = 0;
3242
3243         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3244                                           bp->link_info->link_signal_mode);
3245         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3246         /* Autoneg can be done only when the FW allows. */
3247         if (autoneg == 1 && bp->link_info->support_auto_speeds) {
3248                 link_req.phy_flags |=
3249                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3250                 link_req.auto_link_speed_mask =
3251                         bnxt_parse_eth_link_speed_mask(bp,
3252                                                        dev_conf->link_speeds);
3253         } else {
3254                 if (bp->link_info->phy_type ==
3255                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3256                     bp->link_info->phy_type ==
3257                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3258                     bp->link_info->media_type ==
3259                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3260                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3261                         return -EINVAL;
3262                 }
3263
3264                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3265                 /* If user wants a particular speed try that first. */
3266                 if (speed)
3267                         link_req.link_speed = speed;
3268                 else if (bp->link_info->force_pam4_link_speed)
3269                         link_req.link_speed =
3270                                 bp->link_info->force_pam4_link_speed;
3271                 else if (bp->link_info->auto_pam4_link_speeds)
3272                         link_req.link_speed =
3273                                 bp->link_info->auto_pam4_link_speeds;
3274                 else if (bp->link_info->support_pam4_speeds)
3275                         link_req.link_speed =
3276                                 bp->link_info->support_pam4_speeds;
3277                 else if (bp->link_info->force_link_speed)
3278                         link_req.link_speed = bp->link_info->force_link_speed;
3279                 else
3280                         link_req.link_speed = bp->link_info->auto_link_speed;
3281                 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3282                  * zero. Use the auto_link_speed.
3283                  */
3284                 if (bp->link_info->auto_link_speed != 0 &&
3285                     bp->link_info->auto_pam4_link_speeds == 0)
3286                         link_req.link_speed = bp->link_info->auto_link_speed;
3287         }
3288         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3289         link_req.auto_pause = bp->link_info->auto_pause;
3290         link_req.force_pause = bp->link_info->force_pause;
3291
3292 port_phy_cfg:
3293         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3294         if (rc) {
3295                 PMD_DRV_LOG(ERR,
3296                         "Set link config failed with rc %d\n", rc);
3297         }
3298
3299 error:
3300         return rc;
3301 }
3302
3303 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3304 {
3305         struct hwrm_func_qcfg_input req = {0};
3306         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3307         uint16_t flags;
3308         int rc = 0;
3309         bp->func_svif = BNXT_SVIF_INVALID;
3310         uint16_t svif_info;
3311
3312         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3313         req.fid = rte_cpu_to_le_16(0xffff);
3314
3315         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3316
3317         HWRM_CHECK_RESULT();
3318
3319         bp->vlan = rte_le_to_cpu_16(resp->vlan) & ETH_VLAN_ID_MAX;
3320
3321         svif_info = rte_le_to_cpu_16(resp->svif_info);
3322         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3323                 bp->func_svif = svif_info &
3324                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3325
3326         flags = rte_le_to_cpu_16(resp->flags);
3327         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3328                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3329
3330         if (BNXT_VF(bp) &&
3331             !BNXT_VF_IS_TRUSTED(bp) &&
3332             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3333                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3334                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3335         } else if (BNXT_VF(bp) &&
3336                    BNXT_VF_IS_TRUSTED(bp) &&
3337                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3338                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3339                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3340         }
3341
3342         if (mtu)
3343                 *mtu = rte_le_to_cpu_16(resp->admin_mtu);
3344
3345         switch (resp->port_partition_type) {
3346         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3347         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3348         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3349                 /* FALLTHROUGH */
3350                 bp->flags |= BNXT_FLAG_NPAR_PF;
3351                 break;
3352         default:
3353                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3354                 break;
3355         }
3356
3357         bp->legacy_db_size =
3358                 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3359
3360         HWRM_UNLOCK();
3361
3362         return rc;
3363 }
3364
3365 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3366 {
3367         struct hwrm_func_qcfg_input req = {0};
3368         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3369         int rc;
3370
3371         if (!BNXT_VF_IS_TRUSTED(bp))
3372                 return 0;
3373
3374         if (!bp->parent)
3375                 return -EINVAL;
3376
3377         bp->parent->fid = BNXT_PF_FID_INVALID;
3378
3379         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3380
3381         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3382
3383         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3384
3385         HWRM_CHECK_RESULT_SILENT();
3386
3387         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3388         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3389         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3390         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3391
3392         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3393         if (bp->parent->vnic == 0) {
3394                 PMD_DRV_LOG(DEBUG, "parent VNIC unavailable.\n");
3395                 /* Use hard-coded values appropriate for current Wh+ fw. */
3396                 if (bp->parent->fid == 2)
3397                         bp->parent->vnic = 0x100;
3398                 else
3399                         bp->parent->vnic = 1;
3400         }
3401
3402         HWRM_UNLOCK();
3403
3404         return 0;
3405 }
3406
3407 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3408                                  uint16_t *vnic_id, uint16_t *svif)
3409 {
3410         struct hwrm_func_qcfg_input req = {0};
3411         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3412         uint16_t svif_info;
3413         int rc = 0;
3414
3415         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3416         req.fid = rte_cpu_to_le_16(fid);
3417
3418         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3419
3420         HWRM_CHECK_RESULT();
3421
3422         if (vnic_id)
3423                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3424
3425         svif_info = rte_le_to_cpu_16(resp->svif_info);
3426         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3427                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3428
3429         HWRM_UNLOCK();
3430
3431         return rc;
3432 }
3433
3434 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3435 {
3436         struct hwrm_port_mac_qcfg_input req = {0};
3437         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3438         uint16_t port_svif_info;
3439         int rc;
3440
3441         bp->port_svif = BNXT_SVIF_INVALID;
3442
3443         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3444                 return 0;
3445
3446         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3447
3448         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3449
3450         HWRM_CHECK_RESULT_SILENT();
3451
3452         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3453         if (port_svif_info &
3454             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3455                 bp->port_svif = port_svif_info &
3456                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3457
3458         HWRM_UNLOCK();
3459
3460         return 0;
3461 }
3462
3463 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3464                                  struct bnxt_pf_resource_info *pf_resc)
3465 {
3466         struct hwrm_func_cfg_input req = {0};
3467         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3468         uint32_t enables;
3469         int rc;
3470
3471         enables = HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3472                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3473                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3474                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3475                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3476                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3477                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3478                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3479                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3480
3481         if (BNXT_HAS_RING_GRPS(bp)) {
3482                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3483                 req.num_hw_ring_grps =
3484                         rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3485         } else if (BNXT_HAS_NQ(bp)) {
3486                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3487                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3488         }
3489
3490         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3491         req.admin_mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3492         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3493         req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3494         req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3495         req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3496         req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3497         req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3498         req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3499         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3500         req.fid = rte_cpu_to_le_16(0xffff);
3501         req.enables = rte_cpu_to_le_32(enables);
3502
3503         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3504
3505         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3506
3507         HWRM_CHECK_RESULT();
3508         HWRM_UNLOCK();
3509
3510         return rc;
3511 }
3512
3513 /* min values are the guaranteed resources and max values are subject
3514  * to availability. The strategy for now is to keep both min & max
3515  * values the same.
3516  */
3517 static void
3518 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3519                               struct hwrm_func_vf_resource_cfg_input *req,
3520                               int num_vfs)
3521 {
3522         req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3523                                                (num_vfs + 1));
3524         req->min_rsscos_ctx = req->max_rsscos_ctx;
3525         req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3526         req->min_stat_ctx = req->max_stat_ctx;
3527         req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3528                                                (num_vfs + 1));
3529         req->min_cmpl_rings = req->max_cmpl_rings;
3530         req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3531         req->min_tx_rings = req->max_tx_rings;
3532         req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3533         req->min_rx_rings = req->max_rx_rings;
3534         req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3535         req->min_l2_ctxs = req->max_l2_ctxs;
3536         /* TODO: For now, do not support VMDq/RFS on VFs. */
3537         req->max_vnics = rte_cpu_to_le_16(1);
3538         req->min_vnics = req->max_vnics;
3539         req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3540                                                  (num_vfs + 1));
3541         req->min_hw_ring_grps = req->max_hw_ring_grps;
3542         req->flags =
3543          rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3544 }
3545
3546 static void
3547 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3548                               struct hwrm_func_cfg_input *req,
3549                               int num_vfs)
3550 {
3551         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3552                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3553                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3554                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3555                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3556                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3557                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3558                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3559                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3560                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3561
3562         req->admin_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3563                                           RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3564                                           BNXT_NUM_VLANS);
3565         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3566         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3567                                                 (num_vfs + 1));
3568         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3569         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3570                                                (num_vfs + 1));
3571         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3572         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3573         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3574         /* TODO: For now, do not support VMDq/RFS on VFs. */
3575         req->num_vnics = rte_cpu_to_le_16(1);
3576         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3577                                                  (num_vfs + 1));
3578 }
3579
3580 /* Update the port wide resource values based on how many resources
3581  * got allocated to the VF.
3582  */
3583 static int bnxt_update_max_resources(struct bnxt *bp,
3584                                      int vf)
3585 {
3586         struct hwrm_func_qcfg_input req = {0};
3587         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3588         int rc;
3589
3590         /* Get the actual allocated values now */
3591         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3592         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3593         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3594         HWRM_CHECK_RESULT();
3595
3596         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3597         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3598         bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3599         bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3600         bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3601         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3602         bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3603
3604         HWRM_UNLOCK();
3605
3606         return 0;
3607 }
3608
3609 /* Update the PF resource values based on how many resources
3610  * got allocated to it.
3611  */
3612 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3613 {
3614         struct hwrm_func_qcfg_input req = {0};
3615         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3616         int rc;
3617
3618         /* Get the actual allocated values now */
3619         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3620         req.fid = rte_cpu_to_le_16(0xffff);
3621         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3622         HWRM_CHECK_RESULT();
3623
3624         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3625         bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3626         bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3627         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3628         bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3629         bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3630         bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3631         bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3632
3633         HWRM_UNLOCK();
3634
3635         return 0;
3636 }
3637
3638 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3639 {
3640         struct hwrm_func_qcfg_input req = {0};
3641         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3642         int rc;
3643
3644         /* Check for zero MAC address */
3645         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3646         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3647         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3648         HWRM_CHECK_RESULT();
3649         rc = rte_le_to_cpu_16(resp->vlan);
3650
3651         HWRM_UNLOCK();
3652
3653         return rc;
3654 }
3655
3656 static int bnxt_query_pf_resources(struct bnxt *bp,
3657                                    struct bnxt_pf_resource_info *pf_resc)
3658 {
3659         struct hwrm_func_qcfg_input req = {0};
3660         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3661         int rc;
3662
3663         /* And copy the allocated numbers into the pf struct */
3664         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3665         req.fid = rte_cpu_to_le_16(0xffff);
3666         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3667         HWRM_CHECK_RESULT();
3668
3669         pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3670         pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3671         pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3672         pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3673         pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3674         pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3675         pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3676         bp->pf->evb_mode = resp->evb_mode;
3677
3678         HWRM_UNLOCK();
3679
3680         return rc;
3681 }
3682
3683 static void
3684 bnxt_calculate_pf_resources(struct bnxt *bp,
3685                             struct bnxt_pf_resource_info *pf_resc,
3686                             int num_vfs)
3687 {
3688         if (!num_vfs) {
3689                 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3690                 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3691                 pf_resc->num_cp_rings = bp->max_cp_rings;
3692                 pf_resc->num_tx_rings = bp->max_tx_rings;
3693                 pf_resc->num_rx_rings = bp->max_rx_rings;
3694                 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3695                 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3696
3697                 return;
3698         }
3699
3700         pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3701                                    bp->max_rsscos_ctx % (num_vfs + 1);
3702         pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3703                                  bp->max_stat_ctx % (num_vfs + 1);
3704         pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3705                                 bp->max_cp_rings % (num_vfs + 1);
3706         pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3707                                 bp->max_tx_rings % (num_vfs + 1);
3708         pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3709                                 bp->max_rx_rings % (num_vfs + 1);
3710         pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3711                                bp->max_l2_ctx % (num_vfs + 1);
3712         pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3713                                     bp->max_ring_grps % (num_vfs + 1);
3714 }
3715
3716 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3717 {
3718         struct bnxt_pf_resource_info pf_resc = { 0 };
3719         int rc;
3720
3721         if (!BNXT_PF(bp)) {
3722                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3723                 return -EINVAL;
3724         }
3725
3726         rc = bnxt_hwrm_func_qcaps(bp);
3727         if (rc)
3728                 return rc;
3729
3730         bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3731
3732         bp->pf->func_cfg_flags &=
3733                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3734                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3735         bp->pf->func_cfg_flags |=
3736                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3737
3738         rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3739         if (rc)
3740                 return rc;
3741
3742         rc = bnxt_update_max_resources_pf_only(bp);
3743
3744         return rc;
3745 }
3746
3747 static int
3748 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3749 {
3750         size_t req_buf_sz, sz;
3751         int i, rc;
3752
3753         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3754         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3755                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3756         if (bp->pf->vf_req_buf == NULL) {
3757                 return -ENOMEM;
3758         }
3759
3760         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3761                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3762
3763         for (i = 0; i < num_vfs; i++)
3764                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3765                                              (i * HWRM_MAX_REQ_LEN);
3766
3767         rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3768         if (rc)
3769                 rte_free(bp->pf->vf_req_buf);
3770
3771         return rc;
3772 }
3773
3774 static int
3775 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3776 {
3777         struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3778         struct hwrm_func_vf_resource_cfg_input req = {0};
3779         int i, rc = 0;
3780
3781         bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3782         bp->pf->active_vfs = 0;
3783         for (i = 0; i < num_vfs; i++) {
3784                 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3785                 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3786                 rc = bnxt_hwrm_send_message(bp,
3787                                             &req,
3788                                             sizeof(req),
3789                                             BNXT_USE_CHIMP_MB);
3790                 if (rc || resp->error_code) {
3791                         PMD_DRV_LOG(ERR,
3792                                 "Failed to initialize VF %d\n", i);
3793                         PMD_DRV_LOG(ERR,
3794                                 "Not all VFs available. (%d, %d)\n",
3795                                 rc, resp->error_code);
3796                         HWRM_UNLOCK();
3797
3798                         /* If the first VF configuration itself fails,
3799                          * unregister the vf_fwd_request buffer.
3800                          */
3801                         if (i == 0)
3802                                 bnxt_hwrm_func_buf_unrgtr(bp);
3803                         break;
3804                 }
3805                 HWRM_UNLOCK();
3806
3807                 /* Update the max resource values based on the resource values
3808                  * allocated to the VF.
3809                  */
3810                 bnxt_update_max_resources(bp, i);
3811                 bp->pf->active_vfs++;
3812                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3813         }
3814
3815         return 0;
3816 }
3817
3818 static int
3819 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3820 {
3821         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3822         struct hwrm_func_cfg_input req = {0};
3823         int i, rc;
3824
3825         bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3826
3827         bp->pf->active_vfs = 0;
3828         for (i = 0; i < num_vfs; i++) {
3829                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3830                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3831                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3832                 rc = bnxt_hwrm_send_message(bp,
3833                                             &req,
3834                                             sizeof(req),
3835                                             BNXT_USE_CHIMP_MB);
3836
3837                 /* Clear enable flag for next pass */
3838                 req.enables &= ~rte_cpu_to_le_32(
3839                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3840
3841                 if (rc || resp->error_code) {
3842                         PMD_DRV_LOG(ERR,
3843                                 "Failed to initialize VF %d\n", i);
3844                         PMD_DRV_LOG(ERR,
3845                                 "Not all VFs available. (%d, %d)\n",
3846                                 rc, resp->error_code);
3847                         HWRM_UNLOCK();
3848
3849                         /* If the first VF configuration itself fails,
3850                          * unregister the vf_fwd_request buffer.
3851                          */
3852                         if (i == 0)
3853                                 bnxt_hwrm_func_buf_unrgtr(bp);
3854                         break;
3855                 }
3856
3857                 HWRM_UNLOCK();
3858
3859                 /* Update the max resource values based on the resource values
3860                  * allocated to the VF.
3861                  */
3862                 bnxt_update_max_resources(bp, i);
3863                 bp->pf->active_vfs++;
3864                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3865         }
3866
3867         return 0;
3868 }
3869
3870 static void
3871 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3872 {
3873         if (bp->flags & BNXT_FLAG_NEW_RM)
3874                 bnxt_process_vf_resc_config_new(bp, num_vfs);
3875         else
3876                 bnxt_process_vf_resc_config_old(bp, num_vfs);
3877 }
3878
3879 static void
3880 bnxt_update_pf_resources(struct bnxt *bp,
3881                          struct bnxt_pf_resource_info *pf_resc)
3882 {
3883         bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3884         bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3885         bp->max_cp_rings = pf_resc->num_cp_rings;
3886         bp->max_tx_rings = pf_resc->num_tx_rings;
3887         bp->max_rx_rings = pf_resc->num_rx_rings;
3888         bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3889 }
3890
3891 static int32_t
3892 bnxt_configure_pf_resources(struct bnxt *bp,
3893                             struct bnxt_pf_resource_info *pf_resc)
3894 {
3895         /*
3896          * We're using STD_TX_RING_MODE here which will limit the TX
3897          * rings. This will allow QoS to function properly. Not setting this
3898          * will cause PF rings to break bandwidth settings.
3899          */
3900         bp->pf->func_cfg_flags &=
3901                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3902                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3903         bp->pf->func_cfg_flags |=
3904                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3905         return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3906 }
3907
3908 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3909 {
3910         struct bnxt_pf_resource_info pf_resc = { 0 };
3911         int rc;
3912
3913         if (!BNXT_PF(bp)) {
3914                 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3915                 return -EINVAL;
3916         }
3917
3918         rc = bnxt_hwrm_func_qcaps(bp);
3919         if (rc)
3920                 return rc;
3921
3922         bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3923
3924         rc = bnxt_configure_pf_resources(bp, &pf_resc);
3925         if (rc)
3926                 return rc;
3927
3928         rc = bnxt_query_pf_resources(bp, &pf_resc);
3929         if (rc)
3930                 return rc;
3931
3932         /*
3933          * Now, create and register a buffer to hold forwarded VF requests
3934          */
3935         rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3936         if (rc)
3937                 return rc;
3938
3939         bnxt_configure_vf_resources(bp, num_vfs);
3940
3941         bnxt_update_pf_resources(bp, &pf_resc);
3942
3943         return 0;
3944 }
3945
3946 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3947 {
3948         struct hwrm_func_cfg_input req = {0};
3949         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3950         int rc;
3951
3952         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3953
3954         req.fid = rte_cpu_to_le_16(0xffff);
3955         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3956         req.evb_mode = bp->pf->evb_mode;
3957
3958         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3959         HWRM_CHECK_RESULT();
3960         HWRM_UNLOCK();
3961
3962         return rc;
3963 }
3964
3965 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3966                                 uint8_t tunnel_type)
3967 {
3968         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3969         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3970         int rc = 0;
3971
3972         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3973         req.tunnel_type = tunnel_type;
3974         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3975         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3976         HWRM_CHECK_RESULT();
3977
3978         switch (tunnel_type) {
3979         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3980                 bp->vxlan_fw_dst_port_id =
3981                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3982                 bp->vxlan_port = port;
3983                 break;
3984         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3985                 bp->geneve_fw_dst_port_id =
3986                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3987                 bp->geneve_port = port;
3988                 break;
3989         default:
3990                 break;
3991         }
3992
3993         HWRM_UNLOCK();
3994
3995         return rc;
3996 }
3997
3998 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3999                                 uint8_t tunnel_type)
4000 {
4001         struct hwrm_tunnel_dst_port_free_input req = {0};
4002         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
4003         int rc = 0;
4004
4005         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
4006
4007         req.tunnel_type = tunnel_type;
4008         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
4009         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4010
4011         HWRM_CHECK_RESULT();
4012         HWRM_UNLOCK();
4013
4014         if (tunnel_type ==
4015             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4016                 bp->vxlan_port = 0;
4017                 bp->vxlan_port_cnt = 0;
4018         }
4019
4020         if (tunnel_type ==
4021             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4022                 bp->geneve_port = 0;
4023                 bp->geneve_port_cnt = 0;
4024         }
4025
4026         return rc;
4027 }
4028
4029 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4030                                         uint32_t flags)
4031 {
4032         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4033         struct hwrm_func_cfg_input req = {0};
4034         int rc;
4035
4036         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4037
4038         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4039         req.flags = rte_cpu_to_le_32(flags);
4040         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4041
4042         HWRM_CHECK_RESULT();
4043         HWRM_UNLOCK();
4044
4045         return rc;
4046 }
4047
4048 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4049 {
4050         uint32_t *flag = flagp;
4051
4052         vnic->flags = *flag;
4053 }
4054
4055 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4056 {
4057         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4058 }
4059
4060 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4061 {
4062         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4063         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4064         int rc;
4065
4066         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4067
4068         req.req_buf_num_pages = rte_cpu_to_le_16(1);
4069         req.req_buf_page_size =
4070                 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4071         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4072         req.req_buf_page_addr0 =
4073                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4074         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4075                 PMD_DRV_LOG(ERR,
4076                         "unable to map buffer address to physical memory\n");
4077                 HWRM_UNLOCK();
4078                 return -ENOMEM;
4079         }
4080
4081         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4082
4083         HWRM_CHECK_RESULT();
4084         HWRM_UNLOCK();
4085
4086         return rc;
4087 }
4088
4089 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4090 {
4091         int rc = 0;
4092         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4093         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4094
4095         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4096                 return 0;
4097
4098         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4099
4100         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4101
4102         HWRM_CHECK_RESULT();
4103         HWRM_UNLOCK();
4104
4105         return rc;
4106 }
4107
4108 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4109 {
4110         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4111         struct hwrm_func_cfg_input req = {0};
4112         int rc;
4113
4114         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4115
4116         req.fid = rte_cpu_to_le_16(0xffff);
4117         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4118         req.enables = rte_cpu_to_le_32(
4119                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4120         req.async_event_cr = rte_cpu_to_le_16(
4121                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4122         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4123
4124         HWRM_CHECK_RESULT();
4125         HWRM_UNLOCK();
4126
4127         return rc;
4128 }
4129
4130 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4131 {
4132         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4133         struct hwrm_func_vf_cfg_input req = {0};
4134         int rc;
4135
4136         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4137
4138         req.enables = rte_cpu_to_le_32(
4139                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4140         req.async_event_cr = rte_cpu_to_le_16(
4141                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4142         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4143
4144         HWRM_CHECK_RESULT();
4145         HWRM_UNLOCK();
4146
4147         return rc;
4148 }
4149
4150 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4151 {
4152         struct hwrm_func_cfg_input req = {0};
4153         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4154         uint16_t dflt_vlan, fid;
4155         uint32_t func_cfg_flags;
4156         int rc = 0;
4157
4158         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4159
4160         if (is_vf) {
4161                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4162                 fid = bp->pf->vf_info[vf].fid;
4163                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4164         } else {
4165                 fid = rte_cpu_to_le_16(0xffff);
4166                 func_cfg_flags = bp->pf->func_cfg_flags;
4167                 dflt_vlan = bp->vlan;
4168         }
4169
4170         req.flags = rte_cpu_to_le_32(func_cfg_flags);
4171         req.fid = rte_cpu_to_le_16(fid);
4172         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4173         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4174
4175         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4176
4177         HWRM_CHECK_RESULT();
4178         HWRM_UNLOCK();
4179
4180         return rc;
4181 }
4182
4183 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4184                         uint16_t max_bw, uint16_t enables)
4185 {
4186         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4187         struct hwrm_func_cfg_input req = {0};
4188         int rc;
4189
4190         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4191
4192         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4193         req.enables |= rte_cpu_to_le_32(enables);
4194         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4195         req.max_bw = rte_cpu_to_le_32(max_bw);
4196         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4197
4198         HWRM_CHECK_RESULT();
4199         HWRM_UNLOCK();
4200
4201         return rc;
4202 }
4203
4204 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4205 {
4206         struct hwrm_func_cfg_input req = {0};
4207         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4208         int rc = 0;
4209
4210         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4211
4212         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4213         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4214         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4215         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4216
4217         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4218
4219         HWRM_CHECK_RESULT();
4220         HWRM_UNLOCK();
4221
4222         return rc;
4223 }
4224
4225 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4226 {
4227         int rc;
4228
4229         if (BNXT_PF(bp))
4230                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4231         else
4232                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4233
4234         return rc;
4235 }
4236
4237 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4238                               void *encaped, size_t ec_size)
4239 {
4240         int rc = 0;
4241         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4242         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4243
4244         if (ec_size > sizeof(req.encap_request))
4245                 return -1;
4246
4247         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4248
4249         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4250         memcpy(req.encap_request, encaped, ec_size);
4251
4252         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4253
4254         HWRM_CHECK_RESULT();
4255         HWRM_UNLOCK();
4256
4257         return rc;
4258 }
4259
4260 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4261                                        struct rte_ether_addr *mac)
4262 {
4263         struct hwrm_func_qcfg_input req = {0};
4264         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4265         int rc;
4266
4267         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4268
4269         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4271
4272         HWRM_CHECK_RESULT();
4273
4274         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4275
4276         HWRM_UNLOCK();
4277
4278         return rc;
4279 }
4280
4281 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4282                             void *encaped, size_t ec_size)
4283 {
4284         int rc = 0;
4285         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4286         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4287
4288         if (ec_size > sizeof(req.encap_request))
4289                 return -1;
4290
4291         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4292
4293         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4294         memcpy(req.encap_request, encaped, ec_size);
4295
4296         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4297
4298         HWRM_CHECK_RESULT();
4299         HWRM_UNLOCK();
4300
4301         return rc;
4302 }
4303
4304 static void bnxt_update_prev_stat(uint64_t *cntr, uint64_t *prev_cntr)
4305 {
4306         /* One of the HW stat values that make up this counter was zero as
4307          * returned by HW in this iteration, so use the previous
4308          * iteration's counter value
4309          */
4310         if (*prev_cntr && *cntr == 0)
4311                 *cntr = *prev_cntr;
4312         else
4313                 *prev_cntr = *cntr;
4314 }
4315
4316 int bnxt_hwrm_ring_stats(struct bnxt *bp, uint32_t cid, int idx,
4317                          struct bnxt_ring_stats *ring_stats, bool rx)
4318 {
4319         int rc = 0;
4320         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4321         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4322
4323         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4324
4325         req.stat_ctx_id = rte_cpu_to_le_32(cid);
4326
4327         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4328
4329         HWRM_CHECK_RESULT();
4330
4331         if (rx) {
4332                 struct bnxt_ring_stats *prev_stats = &bp->prev_rx_ring_stats[idx];
4333
4334                 ring_stats->rx_ucast_pkts = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4335                 bnxt_update_prev_stat(&ring_stats->rx_ucast_pkts,
4336                                       &prev_stats->rx_ucast_pkts);
4337
4338                 ring_stats->rx_mcast_pkts = rte_le_to_cpu_64(resp->rx_mcast_pkts);
4339                 bnxt_update_prev_stat(&ring_stats->rx_mcast_pkts,
4340                                       &prev_stats->rx_mcast_pkts);
4341
4342                 ring_stats->rx_bcast_pkts = rte_le_to_cpu_64(resp->rx_bcast_pkts);
4343                 bnxt_update_prev_stat(&ring_stats->rx_bcast_pkts,
4344                                       &prev_stats->rx_bcast_pkts);
4345
4346                 ring_stats->rx_ucast_bytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4347                 bnxt_update_prev_stat(&ring_stats->rx_ucast_bytes,
4348                                       &prev_stats->rx_ucast_bytes);
4349
4350                 ring_stats->rx_mcast_bytes = rte_le_to_cpu_64(resp->rx_mcast_bytes);
4351                 bnxt_update_prev_stat(&ring_stats->rx_mcast_bytes,
4352                                       &prev_stats->rx_mcast_bytes);
4353
4354                 ring_stats->rx_bcast_bytes = rte_le_to_cpu_64(resp->rx_bcast_bytes);
4355                 bnxt_update_prev_stat(&ring_stats->rx_bcast_bytes,
4356                                       &prev_stats->rx_bcast_bytes);
4357
4358                 ring_stats->rx_discard_pkts = rte_le_to_cpu_64(resp->rx_discard_pkts);
4359                 bnxt_update_prev_stat(&ring_stats->rx_discard_pkts,
4360                                       &prev_stats->rx_discard_pkts);
4361
4362                 ring_stats->rx_error_pkts = rte_le_to_cpu_64(resp->rx_error_pkts);
4363                 bnxt_update_prev_stat(&ring_stats->rx_error_pkts,
4364                                       &prev_stats->rx_error_pkts);
4365
4366                 ring_stats->rx_agg_pkts = rte_le_to_cpu_64(resp->rx_agg_pkts);
4367                 bnxt_update_prev_stat(&ring_stats->rx_agg_pkts,
4368                                       &prev_stats->rx_agg_pkts);
4369
4370                 ring_stats->rx_agg_bytes = rte_le_to_cpu_64(resp->rx_agg_bytes);
4371                 bnxt_update_prev_stat(&ring_stats->rx_agg_bytes,
4372                                       &prev_stats->rx_agg_bytes);
4373
4374                 ring_stats->rx_agg_events = rte_le_to_cpu_64(resp->rx_agg_events);
4375                 bnxt_update_prev_stat(&ring_stats->rx_agg_events,
4376                                       &prev_stats->rx_agg_events);
4377
4378                 ring_stats->rx_agg_aborts = rte_le_to_cpu_64(resp->rx_agg_aborts);
4379                 bnxt_update_prev_stat(&ring_stats->rx_agg_aborts,
4380                                       &prev_stats->rx_agg_aborts);
4381         } else {
4382                 struct bnxt_ring_stats *prev_stats = &bp->prev_tx_ring_stats[idx];
4383
4384                 ring_stats->tx_ucast_pkts = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4385                 bnxt_update_prev_stat(&ring_stats->tx_ucast_pkts,
4386                                       &prev_stats->tx_ucast_pkts);
4387
4388                 ring_stats->tx_mcast_pkts = rte_le_to_cpu_64(resp->tx_mcast_pkts);
4389                 bnxt_update_prev_stat(&ring_stats->tx_mcast_pkts,
4390                                       &prev_stats->tx_mcast_pkts);
4391
4392                 ring_stats->tx_bcast_pkts = rte_le_to_cpu_64(resp->tx_bcast_pkts);
4393                 bnxt_update_prev_stat(&ring_stats->tx_bcast_pkts,
4394                                       &prev_stats->tx_bcast_pkts);
4395
4396                 ring_stats->tx_ucast_bytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4397                 bnxt_update_prev_stat(&ring_stats->tx_ucast_bytes,
4398                                       &prev_stats->tx_ucast_bytes);
4399
4400                 ring_stats->tx_mcast_bytes = rte_le_to_cpu_64(resp->tx_mcast_bytes);
4401                 bnxt_update_prev_stat(&ring_stats->tx_mcast_bytes,
4402                                       &prev_stats->tx_mcast_bytes);
4403
4404                 ring_stats->tx_bcast_bytes = rte_le_to_cpu_64(resp->tx_bcast_bytes);
4405                 bnxt_update_prev_stat(&ring_stats->tx_bcast_bytes,
4406                                       &prev_stats->tx_bcast_bytes);
4407
4408                 ring_stats->tx_discard_pkts = rte_le_to_cpu_64(resp->tx_discard_pkts);
4409                 bnxt_update_prev_stat(&ring_stats->tx_discard_pkts,
4410                                       &prev_stats->tx_discard_pkts);
4411         }
4412
4413         HWRM_UNLOCK();
4414
4415         return rc;
4416 }
4417
4418 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4419 {
4420         struct hwrm_port_qstats_input req = {0};
4421         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4422         struct bnxt_pf_info *pf = bp->pf;
4423         int rc;
4424
4425         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4426
4427         req.port_id = rte_cpu_to_le_16(pf->port_id);
4428         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4429         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4430         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4431
4432         HWRM_CHECK_RESULT();
4433         HWRM_UNLOCK();
4434
4435         return rc;
4436 }
4437
4438 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4439 {
4440         struct hwrm_port_clr_stats_input req = {0};
4441         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4442         struct bnxt_pf_info *pf = bp->pf;
4443         int rc;
4444
4445         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4446         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4447             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4448                 return 0;
4449
4450         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4451
4452         req.port_id = rte_cpu_to_le_16(pf->port_id);
4453         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4454
4455         HWRM_CHECK_RESULT();
4456         HWRM_UNLOCK();
4457
4458         return rc;
4459 }
4460
4461 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4462 {
4463         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4464         struct hwrm_port_led_qcaps_input req = {0};
4465         int rc;
4466
4467         if (BNXT_VF(bp))
4468                 return 0;
4469
4470         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4471         req.port_id = bp->pf->port_id;
4472         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4473
4474         HWRM_CHECK_RESULT_SILENT();
4475
4476         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4477                 unsigned int i;
4478
4479                 bp->leds->num_leds = resp->num_leds;
4480                 memcpy(bp->leds, &resp->led0_id,
4481                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4482                 for (i = 0; i < bp->leds->num_leds; i++) {
4483                         struct bnxt_led_info *led = &bp->leds[i];
4484
4485                         uint16_t caps = led->led_state_caps;
4486
4487                         if (!led->led_group_id ||
4488                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4489                                 bp->leds->num_leds = 0;
4490                                 break;
4491                         }
4492                 }
4493         }
4494
4495         HWRM_UNLOCK();
4496
4497         return rc;
4498 }
4499
4500 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4501 {
4502         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4503         struct hwrm_port_led_cfg_input req = {0};
4504         struct bnxt_led_cfg *led_cfg;
4505         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4506         uint16_t duration = 0;
4507         int rc, i;
4508
4509         if (!bp->leds->num_leds || BNXT_VF(bp))
4510                 return -EOPNOTSUPP;
4511
4512         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4513
4514         if (led_on) {
4515                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4516                 duration = rte_cpu_to_le_16(500);
4517         }
4518         req.port_id = bp->pf->port_id;
4519         req.num_leds = bp->leds->num_leds;
4520         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4521         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4522                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4523                 led_cfg->led_id = bp->leds[i].led_id;
4524                 led_cfg->led_state = led_state;
4525                 led_cfg->led_blink_on = duration;
4526                 led_cfg->led_blink_off = duration;
4527                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4528         }
4529
4530         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4531
4532         HWRM_CHECK_RESULT();
4533         HWRM_UNLOCK();
4534
4535         return rc;
4536 }
4537
4538 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4539                                uint32_t *length)
4540 {
4541         int rc;
4542         struct hwrm_nvm_get_dir_info_input req = {0};
4543         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4544
4545         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4546
4547         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4548
4549         HWRM_CHECK_RESULT();
4550
4551         *entries = rte_le_to_cpu_32(resp->entries);
4552         *length = rte_le_to_cpu_32(resp->entry_length);
4553
4554         HWRM_UNLOCK();
4555         return rc;
4556 }
4557
4558 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4559 {
4560         int rc;
4561         uint32_t dir_entries;
4562         uint32_t entry_length;
4563         uint8_t *buf;
4564         size_t buflen;
4565         rte_iova_t dma_handle;
4566         struct hwrm_nvm_get_dir_entries_input req = {0};
4567         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4568
4569         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4570         if (rc != 0)
4571                 return rc;
4572
4573         *data++ = dir_entries;
4574         *data++ = entry_length;
4575         len -= 2;
4576         memset(data, 0xff, len);
4577
4578         buflen = dir_entries * entry_length;
4579         buf = rte_malloc("nvm_dir", buflen, 0);
4580         if (buf == NULL)
4581                 return -ENOMEM;
4582         dma_handle = rte_malloc_virt2iova(buf);
4583         if (dma_handle == RTE_BAD_IOVA) {
4584                 rte_free(buf);
4585                 PMD_DRV_LOG(ERR,
4586                         "unable to map response address to physical memory\n");
4587                 return -ENOMEM;
4588         }
4589         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4590         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4591         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4592
4593         if (rc == 0)
4594                 memcpy(data, buf, len > buflen ? buflen : len);
4595
4596         rte_free(buf);
4597         HWRM_CHECK_RESULT();
4598         HWRM_UNLOCK();
4599
4600         return rc;
4601 }
4602
4603 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4604                              uint32_t offset, uint32_t length,
4605                              uint8_t *data)
4606 {
4607         int rc;
4608         uint8_t *buf;
4609         rte_iova_t dma_handle;
4610         struct hwrm_nvm_read_input req = {0};
4611         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4612
4613         buf = rte_malloc("nvm_item", length, 0);
4614         if (!buf)
4615                 return -ENOMEM;
4616
4617         dma_handle = rte_malloc_virt2iova(buf);
4618         if (dma_handle == RTE_BAD_IOVA) {
4619                 rte_free(buf);
4620                 PMD_DRV_LOG(ERR,
4621                         "unable to map response address to physical memory\n");
4622                 return -ENOMEM;
4623         }
4624         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4625         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4626         req.dir_idx = rte_cpu_to_le_16(index);
4627         req.offset = rte_cpu_to_le_32(offset);
4628         req.len = rte_cpu_to_le_32(length);
4629         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4630         if (rc == 0)
4631                 memcpy(data, buf, length);
4632
4633         rte_free(buf);
4634         HWRM_CHECK_RESULT();
4635         HWRM_UNLOCK();
4636
4637         return rc;
4638 }
4639
4640 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4641 {
4642         int rc;
4643         struct hwrm_nvm_erase_dir_entry_input req = {0};
4644         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4645
4646         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4647         req.dir_idx = rte_cpu_to_le_16(index);
4648         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4649         HWRM_CHECK_RESULT();
4650         HWRM_UNLOCK();
4651
4652         return rc;
4653 }
4654
4655 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4656                           uint16_t dir_ordinal, uint16_t dir_ext,
4657                           uint16_t dir_attr, const uint8_t *data,
4658                           size_t data_len)
4659 {
4660         int rc;
4661         struct hwrm_nvm_write_input req = {0};
4662         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4663         rte_iova_t dma_handle;
4664         uint8_t *buf;
4665
4666         buf = rte_malloc("nvm_write", data_len, 0);
4667         if (!buf)
4668                 return -ENOMEM;
4669
4670         dma_handle = rte_malloc_virt2iova(buf);
4671         if (dma_handle == RTE_BAD_IOVA) {
4672                 rte_free(buf);
4673                 PMD_DRV_LOG(ERR,
4674                         "unable to map response address to physical memory\n");
4675                 return -ENOMEM;
4676         }
4677         memcpy(buf, data, data_len);
4678
4679         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4680
4681         req.dir_type = rte_cpu_to_le_16(dir_type);
4682         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4683         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4684         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4685         req.dir_data_length = rte_cpu_to_le_32(data_len);
4686         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4687
4688         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4689
4690         rte_free(buf);
4691         HWRM_CHECK_RESULT();
4692         HWRM_UNLOCK();
4693
4694         return rc;
4695 }
4696
4697 static void
4698 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4699 {
4700         uint32_t *count = cbdata;
4701
4702         *count = *count + 1;
4703 }
4704
4705 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4706                                      struct bnxt_vnic_info *vnic __rte_unused)
4707 {
4708         return 0;
4709 }
4710
4711 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4712 {
4713         uint32_t count = 0;
4714
4715         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4716             &count, bnxt_vnic_count_hwrm_stub);
4717
4718         return count;
4719 }
4720
4721 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4722                                         uint16_t *vnic_ids)
4723 {
4724         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4725         struct hwrm_func_vf_vnic_ids_query_output *resp =
4726                                                 bp->hwrm_cmd_resp_addr;
4727         int rc;
4728
4729         /* First query all VNIC ids */
4730         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4731
4732         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4733         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4734         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4735
4736         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4737                 HWRM_UNLOCK();
4738                 PMD_DRV_LOG(ERR,
4739                 "unable to map VNIC ID table address to physical memory\n");
4740                 return -ENOMEM;
4741         }
4742         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4743         HWRM_CHECK_RESULT();
4744         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4745
4746         HWRM_UNLOCK();
4747
4748         return rc;
4749 }
4750
4751 /*
4752  * This function queries the VNIC IDs  for a specified VF. It then calls
4753  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4754  * Then it calls the hwrm_cb function to program this new vnic configuration.
4755  */
4756 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4757         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4758         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4759 {
4760         struct bnxt_vnic_info vnic;
4761         int rc = 0;
4762         int i, num_vnic_ids;
4763         uint16_t *vnic_ids;
4764         size_t vnic_id_sz;
4765         size_t sz;
4766
4767         /* First query all VNIC ids */
4768         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4769         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4770                         RTE_CACHE_LINE_SIZE);
4771         if (vnic_ids == NULL)
4772                 return -ENOMEM;
4773
4774         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4775                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4776
4777         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4778
4779         if (num_vnic_ids < 0)
4780                 return num_vnic_ids;
4781
4782         /* Retrieve VNIC, update bd_stall then update */
4783
4784         for (i = 0; i < num_vnic_ids; i++) {
4785                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4786                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4787                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4788                 if (rc)
4789                         break;
4790                 if (vnic.mru <= 4)      /* Indicates unallocated */
4791                         continue;
4792
4793                 vnic_cb(&vnic, cbdata);
4794
4795                 rc = hwrm_cb(bp, &vnic);
4796                 if (rc)
4797                         break;
4798         }
4799
4800         rte_free(vnic_ids);
4801
4802         return rc;
4803 }
4804
4805 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4806                                               bool on)
4807 {
4808         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4809         struct hwrm_func_cfg_input req = {0};
4810         int rc;
4811
4812         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4813
4814         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4815         req.enables |= rte_cpu_to_le_32(
4816                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4817         req.vlan_antispoof_mode = on ?
4818                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4819                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4820         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4821
4822         HWRM_CHECK_RESULT();
4823         HWRM_UNLOCK();
4824
4825         return rc;
4826 }
4827
4828 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4829 {
4830         struct bnxt_vnic_info vnic;
4831         uint16_t *vnic_ids;
4832         size_t vnic_id_sz;
4833         int num_vnic_ids, i;
4834         size_t sz;
4835         int rc;
4836
4837         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4838         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4839                         RTE_CACHE_LINE_SIZE);
4840         if (vnic_ids == NULL)
4841                 return -ENOMEM;
4842
4843         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4844                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4845
4846         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4847         if (rc <= 0)
4848                 goto exit;
4849         num_vnic_ids = rc;
4850
4851         /*
4852          * Loop through to find the default VNIC ID.
4853          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4854          * by sending the hwrm_func_qcfg command to the firmware.
4855          */
4856         for (i = 0; i < num_vnic_ids; i++) {
4857                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4858                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4859                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4860                                         bp->pf->first_vf_id + vf);
4861                 if (rc)
4862                         goto exit;
4863                 if (vnic.func_default) {
4864                         rte_free(vnic_ids);
4865                         return vnic.fw_vnic_id;
4866                 }
4867         }
4868         /* Could not find a default VNIC. */
4869         PMD_DRV_LOG(ERR, "No default VNIC\n");
4870 exit:
4871         rte_free(vnic_ids);
4872         return rc;
4873 }
4874
4875 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4876                          uint16_t dst_id,
4877                          struct bnxt_filter_info *filter)
4878 {
4879         int rc = 0;
4880         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4881         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4882         uint32_t enables = 0;
4883
4884         if (filter->fw_em_filter_id != UINT64_MAX)
4885                 bnxt_hwrm_clear_em_filter(bp, filter);
4886
4887         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4888
4889         req.flags = rte_cpu_to_le_32(filter->flags);
4890
4891         enables = filter->enables |
4892               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4893         req.dst_id = rte_cpu_to_le_16(dst_id);
4894
4895         if (filter->ip_addr_type) {
4896                 req.ip_addr_type = filter->ip_addr_type;
4897                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4898         }
4899         if (enables &
4900             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4901                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4902         if (enables &
4903             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4904                 memcpy(req.src_macaddr, filter->src_macaddr,
4905                        RTE_ETHER_ADDR_LEN);
4906         if (enables &
4907             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4908                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4909                        RTE_ETHER_ADDR_LEN);
4910         if (enables &
4911             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4912                 req.ovlan_vid = filter->l2_ovlan;
4913         if (enables &
4914             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4915                 req.ivlan_vid = filter->l2_ivlan;
4916         if (enables &
4917             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4918                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4919         if (enables &
4920             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4921                 req.ip_protocol = filter->ip_protocol;
4922         if (enables &
4923             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4924                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4925         if (enables &
4926             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4927                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4928         if (enables &
4929             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4930                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4931         if (enables &
4932             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4933                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4934         if (enables &
4935             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4936                 req.mirror_vnic_id = filter->mirror_vnic_id;
4937
4938         req.enables = rte_cpu_to_le_32(enables);
4939
4940         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4941
4942         HWRM_CHECK_RESULT();
4943
4944         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4945         HWRM_UNLOCK();
4946
4947         return rc;
4948 }
4949
4950 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4951 {
4952         int rc = 0;
4953         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4954         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4955
4956         if (filter->fw_em_filter_id == UINT64_MAX)
4957                 return 0;
4958
4959         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4960
4961         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4962
4963         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4964
4965         HWRM_CHECK_RESULT();
4966         HWRM_UNLOCK();
4967
4968         filter->fw_em_filter_id = UINT64_MAX;
4969         filter->fw_l2_filter_id = UINT64_MAX;
4970
4971         return 0;
4972 }
4973
4974 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4975                          uint16_t dst_id,
4976                          struct bnxt_filter_info *filter)
4977 {
4978         int rc = 0;
4979         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4980         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4981                                                 bp->hwrm_cmd_resp_addr;
4982         uint32_t enables = 0;
4983
4984         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4985                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4986
4987         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4988
4989         req.flags = rte_cpu_to_le_32(filter->flags);
4990
4991         enables = filter->enables |
4992               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4993         req.dst_id = rte_cpu_to_le_16(dst_id);
4994
4995         if (filter->ip_addr_type) {
4996                 req.ip_addr_type = filter->ip_addr_type;
4997                 enables |=
4998                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4999         }
5000         if (enables &
5001             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
5002                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
5003         if (enables &
5004             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
5005                 memcpy(req.src_macaddr, filter->src_macaddr,
5006                        RTE_ETHER_ADDR_LEN);
5007         if (enables &
5008             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
5009                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
5010         if (enables &
5011             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
5012                 req.ip_protocol = filter->ip_protocol;
5013         if (enables &
5014             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
5015                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
5016         if (enables &
5017             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
5018                 req.src_ipaddr_mask[0] =
5019                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
5020         if (enables &
5021             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
5022                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
5023         if (enables &
5024             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
5025                 req.dst_ipaddr_mask[0] =
5026                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
5027         if (enables &
5028             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
5029                 req.src_port = rte_cpu_to_le_16(filter->src_port);
5030         if (enables &
5031             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
5032                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
5033         if (enables &
5034             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
5035                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
5036         if (enables &
5037             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
5038                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
5039         if (enables &
5040             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
5041                 req.mirror_vnic_id = filter->mirror_vnic_id;
5042
5043         req.enables = rte_cpu_to_le_32(enables);
5044
5045         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5046
5047         HWRM_CHECK_RESULT();
5048
5049         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
5050         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
5051         HWRM_UNLOCK();
5052
5053         return rc;
5054 }
5055
5056 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
5057                                 struct bnxt_filter_info *filter)
5058 {
5059         int rc = 0;
5060         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
5061         struct hwrm_cfa_ntuple_filter_free_output *resp =
5062                                                 bp->hwrm_cmd_resp_addr;
5063
5064         if (filter->fw_ntuple_filter_id == UINT64_MAX)
5065                 return 0;
5066
5067         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
5068
5069         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
5070
5071         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5072
5073         HWRM_CHECK_RESULT();
5074         HWRM_UNLOCK();
5075
5076         filter->fw_ntuple_filter_id = UINT64_MAX;
5077
5078         return 0;
5079 }
5080
5081 static int
5082 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5083 {
5084         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5085         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
5086         struct bnxt_rx_queue **rxqs = bp->rx_queues;
5087         uint16_t *ring_tbl = vnic->rss_table;
5088         int nr_ctxs = vnic->num_lb_ctxts;
5089         int max_rings = bp->rx_nr_rings;
5090         int i, j, k, cnt;
5091         int rc = 0;
5092
5093         for (i = 0, k = 0; i < nr_ctxs; i++) {
5094                 struct bnxt_rx_ring_info *rxr;
5095                 struct bnxt_cp_ring_info *cpr;
5096
5097                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5098
5099                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5100                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5101                 req.hash_mode_flags = vnic->hash_mode;
5102
5103                 req.ring_grp_tbl_addr =
5104                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5105                                      i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5106                                      2 * sizeof(*ring_tbl));
5107                 req.hash_key_tbl_addr =
5108                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5109
5110                 req.ring_table_pair_index = i;
5111                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5112
5113                 for (j = 0; j < 64; j++) {
5114                         uint16_t ring_id;
5115
5116                         /* Find next active ring. */
5117                         for (cnt = 0; cnt < max_rings; cnt++) {
5118                                 if (rxqs[k]->rx_started)
5119                                         break;
5120                                 if (++k == max_rings)
5121                                         k = 0;
5122                         }
5123
5124                         /* Return if no rings are active. */
5125                         if (cnt == max_rings) {
5126                                 HWRM_UNLOCK();
5127                                 return 0;
5128                         }
5129
5130                         /* Add rx/cp ring pair to RSS table. */
5131                         rxr = rxqs[k]->rx_ring;
5132                         cpr = rxqs[k]->cp_ring;
5133
5134                         ring_id = rxr->rx_ring_struct->fw_ring_id;
5135                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5136                         ring_id = cpr->cp_ring_struct->fw_ring_id;
5137                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5138
5139                         if (++k == max_rings)
5140                                 k = 0;
5141                 }
5142                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5143                                             BNXT_USE_CHIMP_MB);
5144
5145                 HWRM_CHECK_RESULT();
5146                 HWRM_UNLOCK();
5147         }
5148
5149         return rc;
5150 }
5151
5152 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5153 {
5154         unsigned int rss_idx, fw_idx, i;
5155
5156         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5157                 return 0;
5158
5159         if (!(vnic->rss_table && vnic->hash_type))
5160                 return 0;
5161
5162         if (BNXT_CHIP_P5(bp))
5163                 return bnxt_vnic_rss_configure_p5(bp, vnic);
5164
5165         /*
5166          * Fill the RSS hash & redirection table with
5167          * ring group ids for all VNICs
5168          */
5169         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5170              rss_idx++, fw_idx++) {
5171                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5172                         fw_idx %= bp->rx_cp_nr_rings;
5173                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5174                                 break;
5175                         fw_idx++;
5176                 }
5177
5178                 if (i == bp->rx_cp_nr_rings)
5179                         return 0;
5180
5181                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5182         }
5183
5184         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5185 }
5186
5187 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5188         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5189 {
5190         uint16_t flags;
5191
5192         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5193
5194         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5195         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5196
5197         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5198         req->num_cmpl_dma_aggr_during_int =
5199                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5200
5201         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5202
5203         /* min timer set to 1/2 of interrupt timer */
5204         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5205
5206         /* buf timer set to 1/4 of interrupt timer */
5207         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5208
5209         req->cmpl_aggr_dma_tmr_during_int =
5210                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5211
5212         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5213                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5214         req->flags = rte_cpu_to_le_16(flags);
5215 }
5216
5217 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5218                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5219 {
5220         struct hwrm_ring_aggint_qcaps_input req = {0};
5221         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5222         uint32_t enables;
5223         uint16_t flags;
5224         int rc;
5225
5226         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5227         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5228         HWRM_CHECK_RESULT();
5229
5230         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5231         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5232
5233         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5234                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5235         agg_req->flags = rte_cpu_to_le_16(flags);
5236         enables =
5237          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5238          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5239         agg_req->enables = rte_cpu_to_le_32(enables);
5240
5241         HWRM_UNLOCK();
5242         return rc;
5243 }
5244
5245 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5246                         struct bnxt_coal *coal, uint16_t ring_id)
5247 {
5248         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5249         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5250                                                 bp->hwrm_cmd_resp_addr;
5251         int rc;
5252
5253         /* Set ring coalesce parameters only for 100G NICs */
5254         if (BNXT_CHIP_P5(bp)) {
5255                 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5256                         return -1;
5257         } else if (bnxt_stratus_device(bp)) {
5258                 bnxt_hwrm_set_coal_params(coal, &req);
5259         } else {
5260                 return 0;
5261         }
5262
5263         HWRM_PREP(&req,
5264                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5265                   BNXT_USE_CHIMP_MB);
5266         req.ring_id = rte_cpu_to_le_16(ring_id);
5267         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5268         HWRM_CHECK_RESULT();
5269         HWRM_UNLOCK();
5270         return 0;
5271 }
5272
5273 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5274 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5275 {
5276         struct hwrm_func_backing_store_qcaps_input req = {0};
5277         struct hwrm_func_backing_store_qcaps_output *resp =
5278                 bp->hwrm_cmd_resp_addr;
5279         struct bnxt_ctx_pg_info *ctx_pg;
5280         struct bnxt_ctx_mem_info *ctx;
5281         int total_alloc_len;
5282         int rc, i, tqm_rings;
5283
5284         if (!BNXT_CHIP_P5(bp) ||
5285             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5286             BNXT_VF(bp) ||
5287             bp->ctx)
5288                 return 0;
5289
5290         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5291         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5292         HWRM_CHECK_RESULT_SILENT();
5293
5294         total_alloc_len = sizeof(*ctx);
5295         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5296                           RTE_CACHE_LINE_SIZE);
5297         if (!ctx) {
5298                 rc = -ENOMEM;
5299                 goto ctx_err;
5300         }
5301
5302         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5303         ctx->qp_min_qp1_entries =
5304                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5305         ctx->qp_max_l2_entries =
5306                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5307         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5308         ctx->srq_max_l2_entries =
5309                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5310         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5311         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5312         ctx->cq_max_l2_entries =
5313                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5314         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5315         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5316         ctx->vnic_max_vnic_entries =
5317                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5318         ctx->vnic_max_ring_table_entries =
5319                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5320         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5321         ctx->stat_max_entries =
5322                 rte_le_to_cpu_32(resp->stat_max_entries);
5323         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5324         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5325         ctx->tqm_min_entries_per_ring =
5326                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5327         ctx->tqm_max_entries_per_ring =
5328                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5329         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5330         if (!ctx->tqm_entries_multiple)
5331                 ctx->tqm_entries_multiple = 1;
5332         ctx->mrav_max_entries =
5333                 rte_le_to_cpu_32(resp->mrav_max_entries);
5334         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5335         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5336         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5337         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5338
5339         ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5340                                   RTE_MIN(ctx->tqm_fp_rings_count,
5341                                           BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5342                                   bp->max_q;
5343
5344         /* Check if the ext ring count needs to be counted.
5345          * Ext ring count is available only with new FW so we should not
5346          * look at the field on older FW.
5347          */
5348         if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5349             bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5350                 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5351                 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5352                                                   ctx->tqm_fp_rings_count);
5353         }
5354
5355         tqm_rings = ctx->tqm_fp_rings_count + 1;
5356
5357         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5358                             sizeof(*ctx_pg) * tqm_rings,
5359                             RTE_CACHE_LINE_SIZE);
5360         if (!ctx_pg) {
5361                 rc = -ENOMEM;
5362                 goto ctx_err;
5363         }
5364         for (i = 0; i < tqm_rings; i++, ctx_pg++)
5365                 ctx->tqm_mem[i] = ctx_pg;
5366
5367         bp->ctx = ctx;
5368 ctx_err:
5369         HWRM_UNLOCK();
5370         return rc;
5371 }
5372
5373 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5374 {
5375         struct hwrm_func_backing_store_cfg_input req = {0};
5376         struct hwrm_func_backing_store_cfg_output *resp =
5377                 bp->hwrm_cmd_resp_addr;
5378         struct bnxt_ctx_mem_info *ctx = bp->ctx;
5379         struct bnxt_ctx_pg_info *ctx_pg;
5380         uint32_t *num_entries;
5381         uint64_t *pg_dir;
5382         uint8_t *pg_attr;
5383         uint32_t ena;
5384         int i, rc;
5385
5386         if (!ctx)
5387                 return 0;
5388
5389         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5390         req.enables = rte_cpu_to_le_32(enables);
5391
5392         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5393                 ctx_pg = &ctx->qp_mem;
5394                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5395                 req.qp_num_qp1_entries =
5396                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5397                 req.qp_num_l2_entries =
5398                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5399                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5400                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5401                                       &req.qpc_pg_size_qpc_lvl,
5402                                       &req.qpc_page_dir);
5403         }
5404
5405         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5406                 ctx_pg = &ctx->srq_mem;
5407                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5408                 req.srq_num_l2_entries =
5409                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5410                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5411                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5412                                       &req.srq_pg_size_srq_lvl,
5413                                       &req.srq_page_dir);
5414         }
5415
5416         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5417                 ctx_pg = &ctx->cq_mem;
5418                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5419                 req.cq_num_l2_entries =
5420                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5421                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5422                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5423                                       &req.cq_pg_size_cq_lvl,
5424                                       &req.cq_page_dir);
5425         }
5426
5427         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5428                 ctx_pg = &ctx->vnic_mem;
5429                 req.vnic_num_vnic_entries =
5430                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5431                 req.vnic_num_ring_table_entries =
5432                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5433                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5434                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5435                                       &req.vnic_pg_size_vnic_lvl,
5436                                       &req.vnic_page_dir);
5437         }
5438
5439         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5440                 ctx_pg = &ctx->stat_mem;
5441                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5442                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5443                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5444                                       &req.stat_pg_size_stat_lvl,
5445                                       &req.stat_page_dir);
5446         }
5447
5448         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5449         num_entries = &req.tqm_sp_num_entries;
5450         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5451         pg_dir = &req.tqm_sp_page_dir;
5452         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5453         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5454                 if (!(enables & ena))
5455                         continue;
5456
5457                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5458
5459                 ctx_pg = ctx->tqm_mem[i];
5460                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5461                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5462         }
5463
5464         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5465                 /* DPDK does not need to configure MRAV and TIM type.
5466                  * So we are skipping over MRAV and TIM. Skip to configure
5467                  * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5468                  */
5469                 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5470                 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5471                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5472                                       &req.tqm_ring8_pg_size_tqm_ring_lvl,
5473                                       &req.tqm_ring8_page_dir);
5474         }
5475
5476         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5477         HWRM_CHECK_RESULT();
5478         HWRM_UNLOCK();
5479
5480         return rc;
5481 }
5482
5483 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5484 {
5485         struct hwrm_port_qstats_ext_input req = {0};
5486         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5487         struct bnxt_pf_info *pf = bp->pf;
5488         int rc;
5489
5490         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5491               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5492                 return 0;
5493
5494         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5495
5496         req.port_id = rte_cpu_to_le_16(pf->port_id);
5497         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5498                 req.tx_stat_host_addr =
5499                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5500                 req.tx_stat_size =
5501                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5502         }
5503         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5504                 req.rx_stat_host_addr =
5505                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5506                 req.rx_stat_size =
5507                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5508         }
5509         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5510
5511         if (rc) {
5512                 bp->fw_rx_port_stats_ext_size = 0;
5513                 bp->fw_tx_port_stats_ext_size = 0;
5514         } else {
5515                 bp->fw_rx_port_stats_ext_size =
5516                         rte_le_to_cpu_16(resp->rx_stat_size);
5517                 bp->fw_tx_port_stats_ext_size =
5518                         rte_le_to_cpu_16(resp->tx_stat_size);
5519         }
5520
5521         HWRM_CHECK_RESULT();
5522         HWRM_UNLOCK();
5523
5524         return rc;
5525 }
5526
5527 int
5528 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5529 {
5530         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5531         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5532                 bp->hwrm_cmd_resp_addr;
5533         int rc = 0;
5534
5535         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5536         req.tunnel_type = type;
5537         req.dest_fid = bp->fw_fid;
5538         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5539         HWRM_CHECK_RESULT();
5540
5541         HWRM_UNLOCK();
5542
5543         return rc;
5544 }
5545
5546 int
5547 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5548 {
5549         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5550         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5551                 bp->hwrm_cmd_resp_addr;
5552         int rc = 0;
5553
5554         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5555         req.tunnel_type = type;
5556         req.dest_fid = bp->fw_fid;
5557         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5558         HWRM_CHECK_RESULT();
5559
5560         HWRM_UNLOCK();
5561
5562         return rc;
5563 }
5564
5565 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5566 {
5567         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5568         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5569                 bp->hwrm_cmd_resp_addr;
5570         int rc = 0;
5571
5572         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5573         req.src_fid = bp->fw_fid;
5574         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5575         HWRM_CHECK_RESULT();
5576
5577         if (type)
5578                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5579
5580         HWRM_UNLOCK();
5581
5582         return rc;
5583 }
5584
5585 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5586                                    uint16_t *dst_fid)
5587 {
5588         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5589         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5590                 bp->hwrm_cmd_resp_addr;
5591         int rc = 0;
5592
5593         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5594         req.src_fid = bp->fw_fid;
5595         req.tunnel_type = tun_type;
5596         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5597         HWRM_CHECK_RESULT();
5598
5599         if (dst_fid)
5600                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5601
5602         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5603
5604         HWRM_UNLOCK();
5605
5606         return rc;
5607 }
5608
5609 int bnxt_hwrm_set_mac(struct bnxt *bp)
5610 {
5611         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5612         struct hwrm_func_vf_cfg_input req = {0};
5613         int rc = 0;
5614
5615         if (!BNXT_VF(bp))
5616                 return 0;
5617
5618         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5619
5620         req.enables =
5621                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5622         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5623
5624         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5625
5626         HWRM_CHECK_RESULT();
5627
5628         HWRM_UNLOCK();
5629
5630         return rc;
5631 }
5632
5633 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5634 {
5635         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5636         struct hwrm_func_drv_if_change_input req = {0};
5637         uint32_t flags;
5638         int rc;
5639
5640         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5641                 return 0;
5642
5643         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5644          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5645          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5646          */
5647         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5648                 return 0;
5649
5650         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5651
5652         if (up)
5653                 req.flags =
5654                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5655
5656         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5657
5658         HWRM_CHECK_RESULT();
5659         flags = rte_le_to_cpu_32(resp->flags);
5660         HWRM_UNLOCK();
5661
5662         if (!up)
5663                 return 0;
5664
5665         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5666                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5667                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5668         }
5669
5670         return 0;
5671 }
5672
5673 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5674 {
5675         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5676         struct bnxt_error_recovery_info *info = bp->recovery_info;
5677         struct hwrm_error_recovery_qcfg_input req = {0};
5678         uint32_t flags = 0;
5679         unsigned int i;
5680         int rc;
5681
5682         /* Older FW does not have error recovery support */
5683         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5684                 return 0;
5685
5686         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5687
5688         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5689
5690         HWRM_CHECK_RESULT();
5691
5692         flags = rte_le_to_cpu_32(resp->flags);
5693         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5694                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5695         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5696                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5697
5698         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5699             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5700                 rc = -EINVAL;
5701                 goto err;
5702         }
5703
5704         /* FW returned values are in units of 100msec */
5705         info->driver_polling_freq =
5706                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5707         info->master_func_wait_period =
5708                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5709         info->normal_func_wait_period =
5710                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5711         info->master_func_wait_period_after_reset =
5712                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5713         info->max_bailout_time_after_reset =
5714                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5715         info->status_regs[BNXT_FW_STATUS_REG] =
5716                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5717         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5718                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5719         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5720                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5721         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5722                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5723         info->reg_array_cnt =
5724                 rte_le_to_cpu_32(resp->reg_array_cnt);
5725
5726         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5727                 rc = -EINVAL;
5728                 goto err;
5729         }
5730
5731         for (i = 0; i < info->reg_array_cnt; i++) {
5732                 info->reset_reg[i] =
5733                         rte_le_to_cpu_32(resp->reset_reg[i]);
5734                 info->reset_reg_val[i] =
5735                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5736                 info->delay_after_reset[i] =
5737                         resp->delay_after_reset[i];
5738         }
5739 err:
5740         HWRM_UNLOCK();
5741
5742         /* Map the FW status registers */
5743         if (!rc)
5744                 rc = bnxt_map_fw_health_status_regs(bp);
5745
5746         if (rc) {
5747                 rte_free(bp->recovery_info);
5748                 bp->recovery_info = NULL;
5749         }
5750         return rc;
5751 }
5752
5753 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5754 {
5755         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5756         struct hwrm_fw_reset_input req = {0};
5757         int rc;
5758
5759         if (!BNXT_PF(bp))
5760                 return -EOPNOTSUPP;
5761
5762         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5763
5764         req.embedded_proc_type =
5765                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5766         req.selfrst_status =
5767                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5768         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5769
5770         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5771                                     BNXT_USE_KONG(bp));
5772
5773         HWRM_CHECK_RESULT();
5774         HWRM_UNLOCK();
5775
5776         return rc;
5777 }
5778
5779 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5780 {
5781         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5782         struct hwrm_port_ts_query_input req = {0};
5783         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5784         uint32_t flags = 0;
5785         int rc;
5786
5787         if (!ptp)
5788                 return 0;
5789
5790         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5791
5792         switch (path) {
5793         case BNXT_PTP_FLAGS_PATH_TX:
5794                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5795                 break;
5796         case BNXT_PTP_FLAGS_PATH_RX:
5797                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5798                 break;
5799         case BNXT_PTP_FLAGS_CURRENT_TIME:
5800                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5801                 break;
5802         }
5803
5804         req.flags = rte_cpu_to_le_32(flags);
5805         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5806
5807         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5808
5809         HWRM_CHECK_RESULT();
5810
5811         if (timestamp) {
5812                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5813                 *timestamp |=
5814                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5815         }
5816         HWRM_UNLOCK();
5817
5818         return rc;
5819 }
5820
5821 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5822 {
5823         int rc = 0;
5824
5825         struct hwrm_cfa_counter_qcaps_input req = {0};
5826         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5827
5828         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5829                 PMD_DRV_LOG(DEBUG,
5830                             "Not a PF or trusted VF. Command not supported\n");
5831                 return 0;
5832         }
5833
5834         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5835         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5836         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5837
5838         HWRM_CHECK_RESULT();
5839         if (max_fc)
5840                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5841         HWRM_UNLOCK();
5842
5843         return 0;
5844 }
5845
5846 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5847 {
5848         int rc = 0;
5849         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5850         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5851
5852         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5853                 PMD_DRV_LOG(DEBUG,
5854                             "Not a PF or trusted VF. Command not supported\n");
5855                 return 0;
5856         }
5857
5858         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5859
5860         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5861         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5862         req.page_dir = rte_cpu_to_le_64(dma_addr);
5863
5864         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5865
5866         HWRM_CHECK_RESULT();
5867         if (ctx_id) {
5868                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5869                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5870         }
5871         HWRM_UNLOCK();
5872
5873         return 0;
5874 }
5875
5876 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5877 {
5878         int rc = 0;
5879         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5880         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5881
5882         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5883                 PMD_DRV_LOG(DEBUG,
5884                             "Not a PF or trusted VF. Command not supported\n");
5885                 return 0;
5886         }
5887
5888         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5889
5890         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5891
5892         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5893
5894         HWRM_CHECK_RESULT();
5895         HWRM_UNLOCK();
5896
5897         return rc;
5898 }
5899
5900 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5901                               uint16_t cntr, uint16_t ctx_id,
5902                               uint32_t num_entries, bool enable)
5903 {
5904         struct hwrm_cfa_counter_cfg_input req = {0};
5905         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5906         uint16_t flags = 0;
5907         int rc;
5908
5909         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5910                 PMD_DRV_LOG(DEBUG,
5911                             "Not a PF or trusted VF. Command not supported\n");
5912                 return 0;
5913         }
5914
5915         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5916
5917         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5918         req.counter_type = rte_cpu_to_le_16(cntr);
5919         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5920                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5921         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5922         if (dir == BNXT_DIR_RX)
5923                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5924         else if (dir == BNXT_DIR_TX)
5925                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5926         req.flags = rte_cpu_to_le_16(flags);
5927         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5928         req.num_entries = rte_cpu_to_le_32(num_entries);
5929
5930         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5931         HWRM_CHECK_RESULT();
5932         HWRM_UNLOCK();
5933
5934         return 0;
5935 }
5936
5937 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5938                                  enum bnxt_flow_dir dir,
5939                                  uint16_t cntr,
5940                                  uint16_t num_entries)
5941 {
5942         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5943         struct hwrm_cfa_counter_qstats_input req = {0};
5944         uint16_t flow_ctx_id = 0;
5945         uint16_t flags = 0;
5946         int rc = 0;
5947
5948         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5949                 PMD_DRV_LOG(DEBUG,
5950                             "Not a PF or trusted VF. Command not supported\n");
5951                 return 0;
5952         }
5953
5954         if (dir == BNXT_DIR_RX) {
5955                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5956                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5957         } else if (dir == BNXT_DIR_TX) {
5958                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5959                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5960         }
5961
5962         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5963         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5964         req.counter_type = rte_cpu_to_le_16(cntr);
5965         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5966         req.num_entries = rte_cpu_to_le_16(num_entries);
5967         req.flags = rte_cpu_to_le_16(flags);
5968         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5969
5970         HWRM_CHECK_RESULT();
5971         HWRM_UNLOCK();
5972
5973         return 0;
5974 }
5975
5976 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5977                                 uint16_t *first_vf_id)
5978 {
5979         int rc = 0;
5980         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5981         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5982
5983         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5984
5985         req.fid = rte_cpu_to_le_16(fid);
5986
5987         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5988
5989         HWRM_CHECK_RESULT();
5990
5991         if (first_vf_id)
5992                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5993
5994         HWRM_UNLOCK();
5995
5996         return rc;
5997 }
5998
5999 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
6000 {
6001         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6002         struct hwrm_cfa_pair_alloc_input req = {0};
6003         int rc;
6004
6005         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6006                 PMD_DRV_LOG(DEBUG,
6007                             "Not a PF or trusted VF. Command not supported\n");
6008                 return 0;
6009         }
6010
6011         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
6012         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6013         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6014                  bp->eth_dev->data->name, rep_bp->vf_id);
6015
6016         req.pf_b_id = rep_bp->parent_pf_idx;
6017         req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6018                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6019         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
6020         req.host_b_id = 1; /* TBD - Confirm if this is OK */
6021
6022         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
6023                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
6024         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
6025                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
6026         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
6027                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
6028         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
6029                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
6030
6031         req.q_ab = rep_bp->rep_q_r2f;
6032         req.q_ba = rep_bp->rep_q_f2r;
6033         req.fc_ab = rep_bp->rep_fc_r2f;
6034         req.fc_ba = rep_bp->rep_fc_f2r;
6035
6036         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6037         HWRM_CHECK_RESULT();
6038
6039         HWRM_UNLOCK();
6040         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
6041                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
6042         return rc;
6043 }
6044
6045 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
6046 {
6047         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
6048         struct hwrm_cfa_pair_free_input req = {0};
6049         int rc;
6050
6051         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6052                 PMD_DRV_LOG(DEBUG,
6053                             "Not a PF or trusted VF. Command not supported\n");
6054                 return 0;
6055         }
6056
6057         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
6058         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6059                  bp->eth_dev->data->name, rep_bp->vf_id);
6060         req.pf_b_id = rep_bp->parent_pf_idx;
6061         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6062         req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6063                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6064         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6065         HWRM_CHECK_RESULT();
6066         HWRM_UNLOCK();
6067         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
6068                     rep_bp->vf_id);
6069         return rc;
6070 }
6071
6072 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
6073 {
6074         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
6075                                         bp->hwrm_cmd_resp_addr;
6076         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6077         uint32_t flags = 0;
6078         int rc = 0;
6079
6080         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
6081                 return 0;
6082
6083         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6084                 PMD_DRV_LOG(DEBUG,
6085                             "Not a PF or trusted VF. Command not supported\n");
6086                 return 0;
6087         }
6088
6089         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
6090         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6091
6092         HWRM_CHECK_RESULT();
6093         flags = rte_le_to_cpu_32(resp->flags);
6094         HWRM_UNLOCK();
6095
6096         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
6097                 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
6098         else
6099                 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
6100
6101         return rc;
6102 }
6103
6104 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6105                             uint32_t echo_req_data2)
6106 {
6107         struct hwrm_func_echo_response_input req = {0};
6108         struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6109         int rc;
6110
6111         HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6112         req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6113         req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6114
6115         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6116
6117         HWRM_CHECK_RESULT();
6118         HWRM_UNLOCK();
6119
6120         return rc;
6121 }
6122
6123 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6124 {
6125         struct hwrm_ver_get_input req = {.req_type = 0 };
6126         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6127         int rc = 0;
6128
6129         bp->max_req_len = HWRM_MAX_REQ_LEN;
6130         bp->max_resp_len = BNXT_PAGE_SIZE;
6131         bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6132
6133         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6134         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6135         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6136         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6137
6138         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6139
6140         HWRM_CHECK_RESULT_SILENT();
6141
6142         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)
6143                 rc = -EAGAIN;
6144
6145         HWRM_UNLOCK();
6146
6147         return rc;
6148 }
6149
6150 int bnxt_hwrm_read_sfp_module_eeprom_info(struct bnxt *bp, uint16_t i2c_addr,
6151                                           uint16_t page_number, uint16_t start_addr,
6152                                           uint16_t data_length, uint8_t *buf)
6153 {
6154         struct hwrm_port_phy_i2c_read_output *resp = bp->hwrm_cmd_resp_addr;
6155         struct hwrm_port_phy_i2c_read_input req = {0};
6156         uint32_t enables = HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET;
6157         int rc, byte_offset = 0;
6158
6159         do {
6160                 uint16_t xfer_size;
6161
6162                 HWRM_PREP(&req, HWRM_PORT_PHY_I2C_READ, BNXT_USE_CHIMP_MB);
6163                 req.i2c_slave_addr = i2c_addr;
6164                 req.page_number = rte_cpu_to_le_16(page_number);
6165                 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
6166
6167                 xfer_size = RTE_MIN(data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
6168                 req.page_offset = rte_cpu_to_le_16(start_addr + byte_offset);
6169                 req.data_length = xfer_size;
6170                 req.enables = rte_cpu_to_le_32(start_addr + byte_offset ? enables : 0);
6171                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6172                 HWRM_CHECK_RESULT();
6173
6174                 memcpy(buf + byte_offset, resp->data, xfer_size);
6175
6176                 data_length -= xfer_size;
6177                 byte_offset += xfer_size;
6178
6179                 HWRM_UNLOCK();
6180         } while (data_length > 0);
6181
6182         return rc;
6183 }
6184
6185 void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index)
6186 {
6187         struct bnxt_tx_queue *txq = bp->tx_queues[queue_index];
6188         struct bnxt_tx_ring_info *txr = txq->tx_ring;
6189         struct bnxt_ring *ring = txr->tx_ring_struct;
6190         struct bnxt_cp_ring_info *cpr = txq->cp_ring;
6191
6192         bnxt_hwrm_ring_free(bp, ring,
6193                             HWRM_RING_FREE_INPUT_RING_TYPE_TX,
6194                             cpr->cp_ring_struct->fw_ring_id);
6195         txr->tx_raw_prod = 0;
6196         txr->tx_raw_cons = 0;
6197         memset(txr->tx_desc_ring, 0,
6198                 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_desc_ring));
6199         memset(txr->tx_buf_ring, 0,
6200                 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_buf_ring));
6201
6202         bnxt_hwrm_stat_ctx_free(bp, cpr);
6203
6204         bnxt_free_cp_ring(bp, cpr);
6205 }