drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         timeout = bp->hwrm_cmd_timeout;
 104
 105         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 106             msg_len > bp->max_req_len) {
 107                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 108
 109                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 110                 memcpy(short_cmd_req, req, msg_len);
 111
 112                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 113                 short_input.signature = rte_cpu_to_le_16(
 114                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 115                 short_input.size = rte_cpu_to_le_16(msg_len);
 116                 short_input.req_addr =
 117                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 118
 119                 data = (uint32_t *)&short_input;
 120                 msg_len = sizeof(short_input);
 121
 122                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 123         }
 124
 125         /* Write request msg to hwrm channel */
 126         for (i = 0; i < msg_len; i += 4) {
 127                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 128                 rte_write32(*data, bar);
 129                 data++;
 130         }
 131
 132         /* Zero the rest of the request space */
 133         for (; i < max_req_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 135                 rte_write32(0, bar);
 136         }
 137
 138         /* Ring channel doorbell */
 139         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 140         rte_write32(1, bar);
 141         /*
 142          * Make sure the channel doorbell ring command complete before
 143          * reading the response to avoid getting stale or invalid
 144          * responses.
 145          */
 146         rte_io_mb();
 147
 148         /* Poll for the valid bit */
 149         for (i = 0; i < timeout; i++) {
 150                 /* Sanity check on the resp->resp_len */
 151                 rte_cio_rmb();
 152                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 153                         /* Last byte of resp contains the valid key */
 154                         valid = (uint8_t *)resp + resp->resp_len - 1;
 155                         if (*valid == HWRM_RESP_VALID_KEY)
 156                                 break;
 157                 }
 158                 rte_delay_us(1);
 159         }
 160
 161         if (i >= timeout) {
 162                 /* Suppress VER_GET timeout messages during reset recovery */
 163                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 164                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 165                         return -ETIMEDOUT;
 166
 167                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 168                             req->req_type);
 169                 return -ETIMEDOUT;
 170         }
 171         return 0;
 172 }
 173
 174 /*
 175  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 176  * spinlock, and does initial processing.
 177  *
 178  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 179  * releases the spinlock only if it returns. If the regular int return codes
 180  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 181  * directly, rather it should be copied and modified to suit the function.
 182  *
 183  * HWRM_UNLOCK() must be called after all response processing is completed.
 184  */
 185 #define HWRM_PREP(req, type, kong) do { \
 186         rte_spinlock_lock(&bp->hwrm_lock); \
 187         if (bp->hwrm_cmd_resp_addr == NULL) { \
 188                 rte_spinlock_unlock(&bp->hwrm_lock); \
 189                 return -EACCES; \
 190         } \
 191         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 192         (req)->req_type = rte_cpu_to_le_16(type); \
 193         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 194         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 195                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 196         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 197         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 198 } while (0)
 199
 200 #define HWRM_CHECK_RESULT_SILENT() do {\
 201         if (rc) { \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 return rc; \
 204         } \
 205         if (resp->error_code) { \
 206                 rc = rte_le_to_cpu_16(resp->error_code); \
 207                 rte_spinlock_unlock(&bp->hwrm_lock); \
 208                 return rc; \
 209         } \
 210 } while (0)
 211
 212 #define HWRM_CHECK_RESULT() do {\
 213         if (rc) { \
 214                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 215                 rte_spinlock_unlock(&bp->hwrm_lock); \
 216                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 217                         rc = -EACCES; \
 218                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 219                         rc = -ENOSPC; \
 220                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 221                         rc = -EINVAL; \
 222                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 223                         rc = -ENOTSUP; \
 224                 else if (rc > 0) \
 225                         rc = -EIO; \
 226                 return rc; \
 227         } \
 228         if (resp->error_code) { \
 229                 rc = rte_le_to_cpu_16(resp->error_code); \
 230                 if (resp->resp_len >= 16) { \
 231                         struct hwrm_err_output *tmp_hwrm_err_op = \
 232                                                 (void *)resp; \
 233                         PMD_DRV_LOG(ERR, \
 234                                 "error %d:%d:%08x:%04x\n", \
 235                                 rc, tmp_hwrm_err_op->cmd_err, \
 236                                 rte_le_to_cpu_32(\
 237                                         tmp_hwrm_err_op->opaque_0), \
 238                                 rte_le_to_cpu_16(\
 239                                         tmp_hwrm_err_op->opaque_1)); \
 240                 } else { \
 241                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 242                 } \
 243                 rte_spinlock_unlock(&bp->hwrm_lock); \
 244                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 245                         rc = -EACCES; \
 246                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 247                         rc = -ENOSPC; \
 248                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 249                         rc = -EINVAL; \
 250                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 251                         rc = -ENOTSUP; \
 252                 else if (rc > 0) \
 253                         rc = -EIO; \
 254                 return rc; \
 255         } \
 256 } while (0)
 257
 258 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 259
 260 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 261                                 bool use_kong_mb,
 262                                 uint16_t msg_type,
 263                                 void *msg,
 264                                 uint32_t msg_len,
 265                                 void *resp_msg,
 266                                 uint32_t resp_len)
 267 {
 268         int rc = 0;
 269         bool mailbox = BNXT_USE_CHIMP_MB;
 270         struct input *req = msg;
 271         struct output *resp = bp->hwrm_cmd_resp_addr;
 272
 273         if (use_kong_mb)
 274                 mailbox = BNXT_USE_KONG(bp);
 275
 276         HWRM_PREP(req, msg_type, mailbox);
 277
 278         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 279
 280         HWRM_CHECK_RESULT();
 281
 282         if (resp_msg)
 283                 memcpy(resp_msg, resp, resp_len);
 284
 285         HWRM_UNLOCK();
 286
 287         return rc;
 288 }
 289
 290 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 291                                   bool use_kong_mb,
 292                                   uint16_t tf_type,
 293                                   uint16_t tf_subtype,
 294                                   uint32_t *tf_response_code,
 295                                   void *msg,
 296                                   uint32_t msg_len,
 297                                   void *response,
 298                                   uint32_t response_len)
 299 {
 300         int rc = 0;
 301         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 302         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 303         bool mailbox = BNXT_USE_CHIMP_MB;
 304
 305         if (msg_len > sizeof(req.tf_req))
 306                 return -ENOMEM;
 307
 308         if (use_kong_mb)
 309                 mailbox = BNXT_USE_KONG(bp);
 310
 311         HWRM_PREP(&req, HWRM_TF, mailbox);
 312         /* Build request using the user supplied request payload.
 313          * TLV request size is checked at build time against HWRM
 314          * request max size, thus no checking required.
 315          */
 316         req.tf_type = tf_type;
 317         req.tf_subtype = tf_subtype;
 318         memcpy(req.tf_req, msg, msg_len);
 319
 320         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 321         HWRM_CHECK_RESULT();
 322
 323         /* Copy the resp to user provided response buffer */
 324         if (response != NULL)
 325                 /* Post process response data. We need to copy only
 326                  * the 'payload' as the HWRM data structure really is
 327                  * HWRM header + msg header + payload and the TFLIB
 328                  * only provided a payload place holder.
 329                  */
 330                 if (response_len != 0) {
 331                         memcpy(response,
 332                                resp->tf_resp,
 333                                response_len);
 334                 }
 335
 336         /* Extract the internal tflib response code */
 337         *tf_response_code = resp->tf_resp_code;
 338         HWRM_UNLOCK();
 339
 340         return rc;
 341 }
 342
 343 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 344 {
 345         int rc = 0;
 346         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 347         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 348
 349         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 350         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 351         req.mask = 0;
 352
 353         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 354
 355         HWRM_CHECK_RESULT();
 356         HWRM_UNLOCK();
 357
 358         return rc;
 359 }
 360
 361 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 362                                  struct bnxt_vnic_info *vnic,
 363                                  uint16_t vlan_count,
 364                                  struct bnxt_vlan_table_entry *vlan_table)
 365 {
 366         int rc = 0;
 367         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 368         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 369         uint32_t mask = 0;
 370
 371         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 372                 return rc;
 373
 374         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 375         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 376
 377         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 378                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 379         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 380                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 381
 382         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 383                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 384
 385         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 386                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 387         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 388                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 389                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 390                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 391         }
 392         if (vlan_table) {
 393                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 394                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 395                 req.vlan_tag_tbl_addr =
 396                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 397                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 398         }
 399         req.mask = rte_cpu_to_le_32(mask);
 400
 401         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 402
 403         HWRM_CHECK_RESULT();
 404         HWRM_UNLOCK();
 405
 406         return rc;
 407 }
 408
 409 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 410                         uint16_t vlan_count,
 411                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 412 {
 413         int rc = 0;
 414         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 415         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 416                                                 bp->hwrm_cmd_resp_addr;
 417
 418         /*
 419          * Older HWRM versions did not support this command, and the set_rx_mask
 420          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 421          * removed from set_rx_mask call, and this command was added.
 422          *
 423          * This command is also present from 1.7.8.11 and higher,
 424          * as well as 1.7.8.0
 425          */
 426         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 427                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 428                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 429                                         (11)))
 430                                 return 0;
 431                 }
 432         }
 433         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 434         req.fid = rte_cpu_to_le_16(fid);
 435
 436         req.vlan_tag_mask_tbl_addr =
 437                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 438         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 439
 440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 441
 442         HWRM_CHECK_RESULT();
 443         HWRM_UNLOCK();
 444
 445         return rc;
 446 }
 447
 448 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 449                              struct bnxt_filter_info *filter)
 450 {
 451         int rc = 0;
 452         struct bnxt_filter_info *l2_filter = filter;
 453         struct bnxt_vnic_info *vnic = NULL;
 454         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 455         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 456
 457         if (filter->fw_l2_filter_id == UINT64_MAX)
 458                 return 0;
 459
 460         if (filter->matching_l2_fltr_ptr)
 461                 l2_filter = filter->matching_l2_fltr_ptr;
 462
 463         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 464                     filter, l2_filter, l2_filter->l2_ref_cnt);
 465
 466         if (l2_filter->l2_ref_cnt == 0)
 467                 return 0;
 468
 469         if (l2_filter->l2_ref_cnt > 0)
 470                 l2_filter->l2_ref_cnt--;
 471
 472         if (l2_filter->l2_ref_cnt > 0)
 473                 return 0;
 474
 475         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 476
 477         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 478
 479         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 480
 481         HWRM_CHECK_RESULT();
 482         HWRM_UNLOCK();
 483
 484         filter->fw_l2_filter_id = UINT64_MAX;
 485         if (l2_filter->l2_ref_cnt == 0) {
 486                 vnic = l2_filter->vnic;
 487                 if (vnic) {
 488                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 489                                       bnxt_filter_info, next);
 490                         bnxt_free_filter(bp, l2_filter);
 491                 }
 492         }
 493
 494         return 0;
 495 }
 496
 497 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 498                          uint16_t dst_id,
 499                          struct bnxt_filter_info *filter)
 500 {
 501         int rc = 0;
 502         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 503         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 504         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 505         const struct rte_eth_vmdq_rx_conf *conf =
 506                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 507         uint32_t enables = 0;
 508         uint16_t j = dst_id - 1;
 509
 510         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 511         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 512             conf->pool_map[j].pools & (1UL << j)) {
 513                 PMD_DRV_LOG(DEBUG,
 514                         "Add vlan %u to vmdq pool %u\n",
 515                         conf->pool_map[j].vlan_id, j);
 516
 517                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 518                 filter->enables |=
 519                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 520                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 521         }
 522
 523         if (filter->fw_l2_filter_id != UINT64_MAX)
 524                 bnxt_hwrm_clear_l2_filter(bp, filter);
 525
 526         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 527
 528         req.flags = rte_cpu_to_le_32(filter->flags);
 529
 530         enables = filter->enables |
 531               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 532         req.dst_id = rte_cpu_to_le_16(dst_id);
 533
 534         if (enables &
 535             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 536                 memcpy(req.l2_addr, filter->l2_addr,
 537                        RTE_ETHER_ADDR_LEN);
 538         if (enables &
 539             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 540                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 541                        RTE_ETHER_ADDR_LEN);
 542         if (enables &
 543             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 544                 req.l2_ovlan = filter->l2_ovlan;
 545         if (enables &
 546             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 547                 req.l2_ivlan = filter->l2_ivlan;
 548         if (enables &
 549             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 550                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 551         if (enables &
 552             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 553                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 554         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 555                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 556         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 557                 req.src_type = filter->src_type;
 558         if (filter->pri_hint) {
 559                 req.pri_hint = filter->pri_hint;
 560                 req.l2_filter_id_hint =
 561                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 562         }
 563
 564         req.enables = rte_cpu_to_le_32(enables);
 565
 566         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 567
 568         HWRM_CHECK_RESULT();
 569
 570         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 571         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 572         HWRM_UNLOCK();
 573
 574         filter->l2_ref_cnt++;
 575
 576         return rc;
 577 }
 578
 579 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 580 {
 581         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 582         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 583         uint32_t flags = 0;
 584         int rc;
 585
 586         if (!ptp)
 587                 return 0;
 588
 589         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 590
 591         if (ptp->rx_filter)
 592                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 593         else
 594                 flags |=
 595                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 596         if (ptp->tx_tstamp_en)
 597                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 598         else
 599                 flags |=
 600                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 601         req.flags = rte_cpu_to_le_32(flags);
 602         req.enables = rte_cpu_to_le_32
 603                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 604         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 605
 606         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 607         HWRM_UNLOCK();
 608
 609         return rc;
 610 }
 611
 612 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 613 {
 614         int rc = 0;
 615         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 616         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 617         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 618
 619         if (ptp)
 620                 return 0;
 621
 622         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 623
 624         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 625
 626         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 627
 628         HWRM_CHECK_RESULT();
 629
 630         if (!BNXT_CHIP_THOR(bp) &&
 631             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 632                 return 0;
 633
 634         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 635                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 636
 637         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 638         if (!ptp)
 639                 return -ENOMEM;
 640
 641         if (!BNXT_CHIP_THOR(bp)) {
 642                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 643                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 644                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 645                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 646                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 647                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 648                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 649                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 650                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 651                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 652                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 653                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 654                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 655                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 656                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 657                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 658                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 659                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 660         }
 661
 662         ptp->bp = bp;
 663         bp->ptp_cfg = ptp;
 664
 665         return 0;
 666 }
 667
 668 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 669 {
 670         int rc = 0;
 671         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 672         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 673         uint16_t new_max_vfs;
 674         uint32_t flags;
 675         int i;
 676
 677         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 678
 679         req.fid = rte_cpu_to_le_16(0xffff);
 680
 681         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 682
 683         HWRM_CHECK_RESULT();
 684
 685         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 686         flags = rte_le_to_cpu_32(resp->flags);
 687         if (BNXT_PF(bp)) {
 688                 bp->pf.port_id = resp->port_id;
 689                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 690                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 691                 new_max_vfs = bp->pdev->max_vfs;
 692                 if (new_max_vfs != bp->pf.max_vfs) {
 693                         if (bp->pf.vf_info)
 694                                 rte_free(bp->pf.vf_info);
 695                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 696                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 697                         bp->pf.max_vfs = new_max_vfs;
 698                         for (i = 0; i < new_max_vfs; i++) {
 699                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 700                                 bp->pf.vf_info[i].vlan_table =
 701                                         rte_zmalloc("VF VLAN table",
 702                                                     getpagesize(),
 703                                                     getpagesize());
 704                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 705                                         PMD_DRV_LOG(ERR,
 706                                         "Fail to alloc VLAN table for VF %d\n",
 707                                         i);
 708                                 else
 709                                         rte_mem_lock_page(
 710                                                 bp->pf.vf_info[i].vlan_table);
 711                                 bp->pf.vf_info[i].vlan_as_table =
 712                                         rte_zmalloc("VF VLAN AS table",
 713                                                     getpagesize(),
 714                                                     getpagesize());
 715                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 716                                         PMD_DRV_LOG(ERR,
 717                                         "Alloc VLAN AS table for VF %d fail\n",
 718                                         i);
 719                                 else
 720                                         rte_mem_lock_page(
 721                                                bp->pf.vf_info[i].vlan_as_table);
 722                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 723                         }
 724                 }
 725         }
 726
 727         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 728         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 729         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 730         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 731         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 732         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 733         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 734         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 735         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 736         if (!BNXT_CHIP_THOR(bp))
 737                 bp->max_l2_ctx += bp->max_rx_em_flows;
 738         /* TODO: For now, do not support VMDq/RFS on VFs. */
 739         if (BNXT_PF(bp)) {
 740                 if (bp->pf.max_vfs)
 741                         bp->max_vnics = 1;
 742                 else
 743                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 744         } else {
 745                 bp->max_vnics = 1;
 746         }
 747         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 748         if (BNXT_PF(bp)) {
 749                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 750                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 751                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 752                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 753                         HWRM_UNLOCK();
 754                         bnxt_hwrm_ptp_qcfg(bp);
 755                 }
 756         }
 757
 758         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 759                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 760
 761         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 762                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 763                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 764         }
 765
 766         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 767                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 768
 769         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 770                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 771
 772         HWRM_UNLOCK();
 773
 774         return rc;
 775 }
 776
 777 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 778 {
 779         int rc;
 780
 781         rc = __bnxt_hwrm_func_qcaps(bp);
 782         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 783                 rc = bnxt_alloc_ctx_mem(bp);
 784                 if (rc)
 785                         return rc;
 786
 787                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 788                 if (!rc)
 789                         bp->flags |= BNXT_FLAG_NEW_RM;
 790         }
 791
 792         /* On older FW,
 793          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 794          * But the error can be ignored. Return success.
 795          */
 796
 797         return 0;
 798 }
 799
 800 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 801 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 802 {
 803         int rc = 0;
 804         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 805         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 806
 807         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 808
 809         req.target_id = rte_cpu_to_le_16(0xffff);
 810
 811         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 812
 813         HWRM_CHECK_RESULT();
 814
 815         if (rte_le_to_cpu_32(resp->flags) &
 816             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 817                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 818                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 819         }
 820
 821         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 822
 823         HWRM_UNLOCK();
 824
 825         return rc;
 826 }
 827
 828 int bnxt_hwrm_func_reset(struct bnxt *bp)
 829 {
 830         int rc = 0;
 831         struct hwrm_func_reset_input req = {.req_type = 0 };
 832         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 833
 834         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
 835
 836         req.enables = rte_cpu_to_le_32(0);
 837
 838         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 839
 840         HWRM_CHECK_RESULT();
 841         HWRM_UNLOCK();
 842
 843         return rc;
 844 }
 845
 846 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 847 {
 848         int rc;
 849         uint32_t flags = 0;
 850         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 851         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 852
 853         if (bp->flags & BNXT_FLAG_REGISTERED)
 854                 return 0;
 855
 856         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 857                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 858         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 859                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 860
 861         /* PFs and trusted VFs should indicate the support of the
 862          * Master capability on non Stingray platform
 863          */
 864         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 865                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 866
 867         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 868         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 869                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 870         req.ver_maj = RTE_VER_YEAR;
 871         req.ver_min = RTE_VER_MONTH;
 872         req.ver_upd = RTE_VER_MINOR;
 873
 874         if (BNXT_PF(bp)) {
 875                 req.enables |= rte_cpu_to_le_32(
 876                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 877                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 878                        RTE_MIN(sizeof(req.vf_req_fwd),
 879                                sizeof(bp->pf.vf_req_fwd)));
 880
 881                 /*
 882                  * PF can sniff HWRM API issued by VF. This can be set up by
 883                  * linux driver and inherited by the DPDK PF driver. Clear
 884                  * this HWRM sniffer list in FW because DPDK PF driver does
 885                  * not support this.
 886                  */
 887                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 888         }
 889
 890         req.flags = rte_cpu_to_le_32(flags);
 891
 892         req.async_event_fwd[0] |=
 893                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 894                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 895                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 896                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 897                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 898         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 899                 req.async_event_fwd[0] |=
 900                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 901         req.async_event_fwd[1] |=
 902                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 903                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 904         if (BNXT_PF(bp))
 905                 req.async_event_fwd[1] |=
 906                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 907
 908         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 909
 910         HWRM_CHECK_RESULT();
 911
 912         flags = rte_le_to_cpu_32(resp->flags);
 913         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 914                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 915
 916         HWRM_UNLOCK();
 917
 918         bp->flags |= BNXT_FLAG_REGISTERED;
 919
 920         return rc;
 921 }
 922
 923 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 924 {
 925         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 926                 return 0;
 927
 928         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 929 }
 930
 931 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 932 {
 933         int rc;
 934         uint32_t flags = 0;
 935         uint32_t enables;
 936         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 937         struct hwrm_func_vf_cfg_input req = {0};
 938
 939         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 940
 941         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 942                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 943                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 944                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 945                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 946
 947         if (BNXT_HAS_RING_GRPS(bp)) {
 948                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 949                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 950         }
 951
 952         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 953         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 954                                             AGG_RING_MULTIPLIER);
 955         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 956         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 957                                               bp->tx_nr_rings +
 958                                               BNXT_NUM_ASYNC_CPR(bp));
 959         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 960         if (bp->vf_resv_strategy ==
 961             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 962                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 963                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 964                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 965                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 966                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 967                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 968         } else if (bp->vf_resv_strategy ==
 969                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 970                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 971                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 972         }
 973
 974         if (test)
 975                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 976                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 977                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 978                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 979                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 980                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 981
 982         if (test && BNXT_HAS_RING_GRPS(bp))
 983                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 984
 985         req.flags = rte_cpu_to_le_32(flags);
 986         req.enables |= rte_cpu_to_le_32(enables);
 987
 988         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 989
 990         if (test)
 991                 HWRM_CHECK_RESULT_SILENT();
 992         else
 993                 HWRM_CHECK_RESULT();
 994
 995         HWRM_UNLOCK();
 996         return rc;
 997 }
 998
 999 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1000 {
1001         int rc;
1002         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1003         struct hwrm_func_resource_qcaps_input req = {0};
1004
1005         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1006         req.fid = rte_cpu_to_le_16(0xffff);
1007
1008         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1009
1010         HWRM_CHECK_RESULT_SILENT();
1011
1012         if (BNXT_VF(bp)) {
1013                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1014                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1015                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1016                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1017                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1018                 /* func_resource_qcaps does not return max_rx_em_flows.
1019                  * So use the value provided by func_qcaps.
1020                  */
1021                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1022                 if (!BNXT_CHIP_THOR(bp))
1023                         bp->max_l2_ctx += bp->max_rx_em_flows;
1024                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1025                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1026         }
1027         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1028         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1029         if (bp->vf_resv_strategy >
1030             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1031                 bp->vf_resv_strategy =
1032                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1033
1034         HWRM_UNLOCK();
1035         return rc;
1036 }
1037
1038 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1039 {
1040         int rc = 0;
1041         struct hwrm_ver_get_input req = {.req_type = 0 };
1042         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1043         uint32_t fw_version;
1044         uint16_t max_resp_len;
1045         char type[RTE_MEMZONE_NAMESIZE];
1046         uint32_t dev_caps_cfg;
1047
1048         bp->max_req_len = HWRM_MAX_REQ_LEN;
1049         bp->hwrm_cmd_timeout = timeout;
1050         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1051
1052         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1053         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1054         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1055
1056         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1057
1058         if (bp->flags & BNXT_FLAG_FW_RESET)
1059                 HWRM_CHECK_RESULT_SILENT();
1060         else
1061                 HWRM_CHECK_RESULT();
1062
1063         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1064                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1065                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1066                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1067         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1068                      (resp->hwrm_fw_min_8b << 16) |
1069                      (resp->hwrm_fw_bld_8b << 8) |
1070                      resp->hwrm_fw_rsvd_8b;
1071         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1072                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1073
1074         fw_version = resp->hwrm_intf_maj_8b << 16;
1075         fw_version |= resp->hwrm_intf_min_8b << 8;
1076         fw_version |= resp->hwrm_intf_upd_8b;
1077         bp->hwrm_spec_code = fw_version;
1078
1079         /* def_req_timeout value is in milliseconds */
1080         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1081         /* convert timeout to usec */
1082         bp->hwrm_cmd_timeout *= 1000;
1083         if (!bp->hwrm_cmd_timeout)
1084                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1085
1086         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1087                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1088                 rc = -EINVAL;
1089                 goto error;
1090         }
1091
1092         if (bp->max_req_len > resp->max_req_win_len) {
1093                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1094                 rc = -EINVAL;
1095         }
1096         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1097         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1098         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1099                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1100
1101         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1102         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1103
1104         if (bp->max_resp_len != max_resp_len) {
1105                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
1106                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1107                         bp->pdev->addr.devid, bp->pdev->addr.function);
1108
1109                 rte_free(bp->hwrm_cmd_resp_addr);
1110
1111                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1112                 if (bp->hwrm_cmd_resp_addr == NULL) {
1113                         rc = -ENOMEM;
1114                         goto error;
1115                 }
1116                 bp->hwrm_cmd_resp_dma_addr =
1117                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1118                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1119                         PMD_DRV_LOG(ERR,
1120                         "Unable to map response buffer to physical memory.\n");
1121                         rc = -ENOMEM;
1122                         goto error;
1123                 }
1124                 bp->max_resp_len = max_resp_len;
1125         }
1126
1127         if ((dev_caps_cfg &
1128                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1129             (dev_caps_cfg &
1130              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1131                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1132                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1133         }
1134
1135         if (((dev_caps_cfg &
1136               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1137              (dev_caps_cfg &
1138               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1139             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1140                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1141                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1142                         bp->pdev->addr.devid, bp->pdev->addr.function);
1143
1144                 rte_free(bp->hwrm_short_cmd_req_addr);
1145
1146                 bp->hwrm_short_cmd_req_addr =
1147                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1148                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1149                         rc = -ENOMEM;
1150                         goto error;
1151                 }
1152                 bp->hwrm_short_cmd_req_dma_addr =
1153                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1154                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1155                         rte_free(bp->hwrm_short_cmd_req_addr);
1156                         PMD_DRV_LOG(ERR,
1157                                 "Unable to map buffer to physical memory.\n");
1158                         rc = -ENOMEM;
1159                         goto error;
1160                 }
1161         }
1162         if (dev_caps_cfg &
1163             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1164                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1165                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1166         }
1167         if (dev_caps_cfg &
1168             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1169                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1170         if (dev_caps_cfg &
1171             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1172                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1173                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1174         }
1175
1176 error:
1177         HWRM_UNLOCK();
1178         return rc;
1179 }
1180
1181 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1182 {
1183         int rc;
1184         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1185         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1186
1187         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1188                 return 0;
1189
1190         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1191         req.flags = flags;
1192
1193         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1194
1195         HWRM_CHECK_RESULT();
1196         HWRM_UNLOCK();
1197
1198         return rc;
1199 }
1200
1201 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1202 {
1203         int rc = 0;
1204         struct hwrm_port_phy_cfg_input req = {0};
1205         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1206         uint32_t enables = 0;
1207
1208         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1209
1210         if (conf->link_up) {
1211                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1212                 if (bp->link_info.auto_mode && conf->link_speed) {
1213                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1214                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1215                 }
1216
1217                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1218                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1219                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1220                 /*
1221                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1222                  * any auto mode, even "none".
1223                  */
1224                 if (!conf->link_speed) {
1225                         /* No speeds specified. Enable AutoNeg - all speeds */
1226                         req.auto_mode =
1227                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1228                 }
1229                 /* AutoNeg - Advertise speeds specified. */
1230                 if (conf->auto_link_speed_mask &&
1231                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1232                         req.auto_mode =
1233                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1234                         req.auto_link_speed_mask =
1235                                 conf->auto_link_speed_mask;
1236                         enables |=
1237                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1238                 }
1239
1240                 req.auto_duplex = conf->duplex;
1241                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1242                 req.auto_pause = conf->auto_pause;
1243                 req.force_pause = conf->force_pause;
1244                 /* Set force_pause if there is no auto or if there is a force */
1245                 if (req.auto_pause && !req.force_pause)
1246                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1247                 else
1248                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1249
1250                 req.enables = rte_cpu_to_le_32(enables);
1251         } else {
1252                 req.flags =
1253                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1254                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1255         }
1256
1257         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1258
1259         HWRM_CHECK_RESULT();
1260         HWRM_UNLOCK();
1261
1262         return rc;
1263 }
1264
1265 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1266                                    struct bnxt_link_info *link_info)
1267 {
1268         int rc = 0;
1269         struct hwrm_port_phy_qcfg_input req = {0};
1270         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1271
1272         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1273
1274         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1275
1276         HWRM_CHECK_RESULT();
1277
1278         link_info->phy_link_status = resp->link;
1279         link_info->link_up =
1280                 (link_info->phy_link_status ==
1281                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1282         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1283         link_info->duplex = resp->duplex_cfg;
1284         link_info->pause = resp->pause;
1285         link_info->auto_pause = resp->auto_pause;
1286         link_info->force_pause = resp->force_pause;
1287         link_info->auto_mode = resp->auto_mode;
1288         link_info->phy_type = resp->phy_type;
1289         link_info->media_type = resp->media_type;
1290
1291         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1292         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1293         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1294         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1295         link_info->phy_ver[0] = resp->phy_maj;
1296         link_info->phy_ver[1] = resp->phy_min;
1297         link_info->phy_ver[2] = resp->phy_bld;
1298
1299         HWRM_UNLOCK();
1300
1301         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1302         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1303         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1304         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1305         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1306                     link_info->auto_link_speed_mask);
1307         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1308                     link_info->force_link_speed);
1309
1310         return rc;
1311 }
1312
1313 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1314 {
1315         int i = 0;
1316
1317         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1318                 if (bp->tx_cos_queue[i].profile ==
1319                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1320                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1321                         return true;
1322                 }
1323         }
1324         return false;
1325 }
1326
1327 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1328 {
1329         int i = 0;
1330
1331         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1332                 if (bp->tx_cos_queue[i].profile !=
1333                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1334                     bp->tx_cos_queue[i].id !=
1335                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1336                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1337                         break;
1338                 }
1339         }
1340 }
1341
1342 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1343 {
1344         int rc = 0;
1345         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1346         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1347         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1348         int i;
1349
1350 get_rx_info:
1351         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1352
1353         req.flags = rte_cpu_to_le_32(dir);
1354         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1355         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1356             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1357                 req.drv_qmap_cap =
1358                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1359         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1360
1361         HWRM_CHECK_RESULT();
1362
1363         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1364                 GET_TX_QUEUE_INFO(0);
1365                 GET_TX_QUEUE_INFO(1);
1366                 GET_TX_QUEUE_INFO(2);
1367                 GET_TX_QUEUE_INFO(3);
1368                 GET_TX_QUEUE_INFO(4);
1369                 GET_TX_QUEUE_INFO(5);
1370                 GET_TX_QUEUE_INFO(6);
1371                 GET_TX_QUEUE_INFO(7);
1372         } else  {
1373                 GET_RX_QUEUE_INFO(0);
1374                 GET_RX_QUEUE_INFO(1);
1375                 GET_RX_QUEUE_INFO(2);
1376                 GET_RX_QUEUE_INFO(3);
1377                 GET_RX_QUEUE_INFO(4);
1378                 GET_RX_QUEUE_INFO(5);
1379                 GET_RX_QUEUE_INFO(6);
1380                 GET_RX_QUEUE_INFO(7);
1381         }
1382
1383         HWRM_UNLOCK();
1384
1385         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1386                 goto done;
1387
1388         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1389                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1390         } else {
1391                 int j;
1392
1393                 /* iterate and find the COSq profile to use for Tx */
1394                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1395                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1396                                 if (bp->tx_cos_queue[i].id != 0xff)
1397                                         bp->tx_cosq_id[j++] =
1398                                                 bp->tx_cos_queue[i].id;
1399                         }
1400                 } else {
1401                         /* When CoS classification is disabled, for normal NIC
1402                          * operations, ideally we should look to use LOSSY.
1403                          * If not found, fallback to the first valid profile
1404                          */
1405                         if (!bnxt_find_lossy_profile(bp))
1406                                 bnxt_find_first_valid_profile(bp);
1407
1408                 }
1409         }
1410
1411         bp->max_tc = resp->max_configurable_queues;
1412         bp->max_lltc = resp->max_configurable_lossless_queues;
1413         if (bp->max_tc > BNXT_MAX_QUEUE)
1414                 bp->max_tc = BNXT_MAX_QUEUE;
1415         bp->max_q = bp->max_tc;
1416
1417         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1418                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1419                 goto get_rx_info;
1420         }
1421
1422 done:
1423         return rc;
1424 }
1425
1426 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1427                          struct bnxt_ring *ring,
1428                          uint32_t ring_type, uint32_t map_index,
1429                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1430                          uint16_t tx_cosq_id)
1431 {
1432         int rc = 0;
1433         uint32_t enables = 0;
1434         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1435         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1436         struct rte_mempool *mb_pool;
1437         uint16_t rx_buf_size;
1438
1439         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1440
1441         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1442         req.fbo = rte_cpu_to_le_32(0);
1443         /* Association of ring index with doorbell index */
1444         req.logical_id = rte_cpu_to_le_16(map_index);
1445         req.length = rte_cpu_to_le_32(ring->ring_size);
1446
1447         switch (ring_type) {
1448         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1449                 req.ring_type = ring_type;
1450                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1451                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1452                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1453                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1454                         enables |=
1455                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1456                 break;
1457         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1458                 req.ring_type = ring_type;
1459                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1460                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1461                 if (BNXT_CHIP_THOR(bp)) {
1462                         mb_pool = bp->rx_queues[0]->mb_pool;
1463                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1464                                       RTE_PKTMBUF_HEADROOM;
1465                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1466                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1467                         enables |=
1468                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1469                 }
1470                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1471                         enables |=
1472                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1473                 break;
1474         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1475                 req.ring_type = ring_type;
1476                 if (BNXT_HAS_NQ(bp)) {
1477                         /* Association of cp ring with nq */
1478                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1479                         enables |=
1480                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1481                 }
1482                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1483                 break;
1484         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1485                 req.ring_type = ring_type;
1486                 req.page_size = BNXT_PAGE_SHFT;
1487                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1488                 break;
1489         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1490                 req.ring_type = ring_type;
1491                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1492
1493                 mb_pool = bp->rx_queues[0]->mb_pool;
1494                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1495                               RTE_PKTMBUF_HEADROOM;
1496                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1497                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1498
1499                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1500                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1501                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1502                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1503                 break;
1504         default:
1505                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1506                         ring_type);
1507                 HWRM_UNLOCK();
1508                 return -EINVAL;
1509         }
1510         req.enables = rte_cpu_to_le_32(enables);
1511
1512         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1513
1514         if (rc || resp->error_code) {
1515                 if (rc == 0 && resp->error_code)
1516                         rc = rte_le_to_cpu_16(resp->error_code);
1517                 switch (ring_type) {
1518                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1519                         PMD_DRV_LOG(ERR,
1520                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1521                         HWRM_UNLOCK();
1522                         return rc;
1523                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1524                         PMD_DRV_LOG(ERR,
1525                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1526                         HWRM_UNLOCK();
1527                         return rc;
1528                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1529                         PMD_DRV_LOG(ERR,
1530                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1531                                     rc);
1532                         HWRM_UNLOCK();
1533                         return rc;
1534                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1535                         PMD_DRV_LOG(ERR,
1536                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1537                         HWRM_UNLOCK();
1538                         return rc;
1539                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1540                         PMD_DRV_LOG(ERR,
1541                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1542                         HWRM_UNLOCK();
1543                         return rc;
1544                 default:
1545                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1546                         HWRM_UNLOCK();
1547                         return rc;
1548                 }
1549         }
1550
1551         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1552         HWRM_UNLOCK();
1553         return rc;
1554 }
1555
1556 int bnxt_hwrm_ring_free(struct bnxt *bp,
1557                         struct bnxt_ring *ring, uint32_t ring_type)
1558 {
1559         int rc;
1560         struct hwrm_ring_free_input req = {.req_type = 0 };
1561         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1562
1563         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1564
1565         req.ring_type = ring_type;
1566         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1567
1568         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1569
1570         if (rc || resp->error_code) {
1571                 if (rc == 0 && resp->error_code)
1572                         rc = rte_le_to_cpu_16(resp->error_code);
1573                 HWRM_UNLOCK();
1574
1575                 switch (ring_type) {
1576                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1577                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1578                                 rc);
1579                         return rc;
1580                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1581                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1582                                 rc);
1583                         return rc;
1584                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1585                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1586                                 rc);
1587                         return rc;
1588                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1589                         PMD_DRV_LOG(ERR,
1590                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1591                         return rc;
1592                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1593                         PMD_DRV_LOG(ERR,
1594                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1595                         return rc;
1596                 default:
1597                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1598                         return rc;
1599                 }
1600         }
1601         HWRM_UNLOCK();
1602         return 0;
1603 }
1604
1605 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1606 {
1607         int rc = 0;
1608         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1609         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1610
1611         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1612
1613         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1614         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1615         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1616         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1617
1618         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1619
1620         HWRM_CHECK_RESULT();
1621
1622         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1623
1624         HWRM_UNLOCK();
1625
1626         return rc;
1627 }
1628
1629 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1630 {
1631         int rc;
1632         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1633         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1634
1635         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1636
1637         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1638
1639         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1640
1641         HWRM_CHECK_RESULT();
1642         HWRM_UNLOCK();
1643
1644         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1645         return rc;
1646 }
1647
1648 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1649 {
1650         int rc = 0;
1651         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1652         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1653
1654         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1655                 return rc;
1656
1657         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1658
1659         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1660
1661         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1662
1663         HWRM_CHECK_RESULT();
1664         HWRM_UNLOCK();
1665
1666         return rc;
1667 }
1668
1669 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1670                                 unsigned int idx __rte_unused)
1671 {
1672         int rc;
1673         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1674         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1675
1676         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1677
1678         req.update_period_ms = rte_cpu_to_le_32(0);
1679
1680         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1681
1682         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1683
1684         HWRM_CHECK_RESULT();
1685
1686         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1687
1688         HWRM_UNLOCK();
1689
1690         return rc;
1691 }
1692
1693 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1694                                 unsigned int idx __rte_unused)
1695 {
1696         int rc;
1697         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1698         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1699
1700         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1701
1702         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1703
1704         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1705
1706         HWRM_CHECK_RESULT();
1707         HWRM_UNLOCK();
1708
1709         return rc;
1710 }
1711
1712 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1713 {
1714         int rc = 0, i, j;
1715         struct hwrm_vnic_alloc_input req = { 0 };
1716         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1717
1718         if (!BNXT_HAS_RING_GRPS(bp))
1719                 goto skip_ring_grps;
1720
1721         /* map ring groups to this vnic */
1722         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1723                 vnic->start_grp_id, vnic->end_grp_id);
1724         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1725                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1726
1727         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1728         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1729         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1730         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1731
1732 skip_ring_grps:
1733         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1734         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1735
1736         if (vnic->func_default)
1737                 req.flags =
1738                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1739         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1740
1741         HWRM_CHECK_RESULT();
1742
1743         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1744         HWRM_UNLOCK();
1745         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1746         return rc;
1747 }
1748
1749 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1750                                         struct bnxt_vnic_info *vnic,
1751                                         struct bnxt_plcmodes_cfg *pmode)
1752 {
1753         int rc = 0;
1754         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1755         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1756
1757         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1758
1759         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1760
1761         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1762
1763         HWRM_CHECK_RESULT();
1764
1765         pmode->flags = rte_le_to_cpu_32(resp->flags);
1766         /* dflt_vnic bit doesn't exist in the _cfg command */
1767         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1768         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1769         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1770         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1771
1772         HWRM_UNLOCK();
1773
1774         return rc;
1775 }
1776
1777 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1778                                        struct bnxt_vnic_info *vnic,
1779                                        struct bnxt_plcmodes_cfg *pmode)
1780 {
1781         int rc = 0;
1782         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1783         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1784
1785         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1786                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1787                 return rc;
1788         }
1789
1790         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1791
1792         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1793         req.flags = rte_cpu_to_le_32(pmode->flags);
1794         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1795         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1796         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1797         req.enables = rte_cpu_to_le_32(
1798             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1799             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1800             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1801         );
1802
1803         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1804
1805         HWRM_CHECK_RESULT();
1806         HWRM_UNLOCK();
1807
1808         return rc;
1809 }
1810
1811 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1812 {
1813         int rc = 0;
1814         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1815         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1816         struct bnxt_plcmodes_cfg pmodes = { 0 };
1817         uint32_t ctx_enable_flag = 0;
1818         uint32_t enables = 0;
1819
1820         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1821                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1822                 return rc;
1823         }
1824
1825         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1826         if (rc)
1827                 return rc;
1828
1829         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1830
1831         if (BNXT_CHIP_THOR(bp)) {
1832                 int dflt_rxq = vnic->start_grp_id;
1833                 struct bnxt_rx_ring_info *rxr;
1834                 struct bnxt_cp_ring_info *cpr;
1835                 struct bnxt_rx_queue *rxq;
1836                 int i;
1837
1838                 /*
1839                  * The first active receive ring is used as the VNIC
1840                  * default receive ring. If there are no active receive
1841                  * rings (all corresponding receive queues are stopped),
1842                  * the first receive ring is used.
1843                  */
1844                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1845                         rxq = bp->eth_dev->data->rx_queues[i];
1846                         if (rxq->rx_started) {
1847                                 dflt_rxq = i;
1848                                 break;
1849                         }
1850                 }
1851
1852                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1853                 rxr = rxq->rx_ring;
1854                 cpr = rxq->cp_ring;
1855
1856                 req.default_rx_ring_id =
1857                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1858                 req.default_cmpl_ring_id =
1859                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1860                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1861                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1862                 goto config_mru;
1863         }
1864
1865         /* Only RSS support for now TBD: COS & LB */
1866         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1867         if (vnic->lb_rule != 0xffff)
1868                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1869         if (vnic->cos_rule != 0xffff)
1870                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1871         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1872                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1873                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1874         }
1875         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1876                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1877                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1878         }
1879
1880         enables |= ctx_enable_flag;
1881         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1882         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1883         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1884         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1885
1886 config_mru:
1887         req.enables = rte_cpu_to_le_32(enables);
1888         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1889         req.mru = rte_cpu_to_le_16(vnic->mru);
1890         /* Configure default VNIC only once. */
1891         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1892                 req.flags |=
1893                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1894                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1895         }
1896         if (vnic->vlan_strip)
1897                 req.flags |=
1898                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1899         if (vnic->bd_stall)
1900                 req.flags |=
1901                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1902         if (vnic->roce_dual)
1903                 req.flags |= rte_cpu_to_le_32(
1904                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1905         if (vnic->roce_only)
1906                 req.flags |= rte_cpu_to_le_32(
1907                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1908         if (vnic->rss_dflt_cr)
1909                 req.flags |= rte_cpu_to_le_32(
1910                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1911
1912         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1913
1914         HWRM_CHECK_RESULT();
1915         HWRM_UNLOCK();
1916
1917         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1918
1919         return rc;
1920 }
1921
1922 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1923                 int16_t fw_vf_id)
1924 {
1925         int rc = 0;
1926         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1927         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1928
1929         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1930                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1931                 return rc;
1932         }
1933         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
1934
1935         req.enables =
1936                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1937         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1938         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1939
1940         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1941
1942         HWRM_CHECK_RESULT();
1943
1944         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1945         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1946         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1947         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1948         vnic->mru = rte_le_to_cpu_16(resp->mru);
1949         vnic->func_default = rte_le_to_cpu_32(
1950                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1951         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1952                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1953         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1954                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1955         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1956                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1957         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1958                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1959         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1960                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1961
1962         HWRM_UNLOCK();
1963
1964         return rc;
1965 }
1966
1967 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1968                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1969 {
1970         int rc = 0;
1971         uint16_t ctx_id;
1972         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1973         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1974                                                 bp->hwrm_cmd_resp_addr;
1975
1976         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1977
1978         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1979         HWRM_CHECK_RESULT();
1980
1981         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1982         if (!BNXT_HAS_RING_GRPS(bp))
1983                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1984         else if (ctx_idx == 0)
1985                 vnic->rss_rule = ctx_id;
1986
1987         HWRM_UNLOCK();
1988
1989         return rc;
1990 }
1991
1992 static
1993 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1994                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1995 {
1996         int rc = 0;
1997         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1998         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1999                                                 bp->hwrm_cmd_resp_addr;
2000
2001         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2002                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2003                 return rc;
2004         }
2005         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2006
2007         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2008
2009         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2010
2011         HWRM_CHECK_RESULT();
2012         HWRM_UNLOCK();
2013
2014         return rc;
2015 }
2016
2017 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2018 {
2019         int rc = 0;
2020
2021         if (BNXT_CHIP_THOR(bp)) {
2022                 int j;
2023
2024                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2025                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2026                                                       vnic,
2027                                                       vnic->fw_grp_ids[j]);
2028                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2029                 }
2030                 vnic->num_lb_ctxts = 0;
2031         } else {
2032                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2033                 vnic->rss_rule = INVALID_HW_RING_ID;
2034         }
2035
2036         return rc;
2037 }
2038
2039 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2040 {
2041         int rc = 0;
2042         struct hwrm_vnic_free_input req = {.req_type = 0 };
2043         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2044
2045         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2046                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2047                 return rc;
2048         }
2049
2050         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2051
2052         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2053
2054         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2055
2056         HWRM_CHECK_RESULT();
2057         HWRM_UNLOCK();
2058
2059         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2060         /* Configure default VNIC again if necessary. */
2061         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2062                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2063
2064         return rc;
2065 }
2066
2067 static int
2068 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2069 {
2070         int i;
2071         int rc = 0;
2072         int nr_ctxs = vnic->num_lb_ctxts;
2073         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2074         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2075
2076         for (i = 0; i < nr_ctxs; i++) {
2077                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2078
2079                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2080                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2081                 req.hash_mode_flags = vnic->hash_mode;
2082
2083                 req.hash_key_tbl_addr =
2084                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2085
2086                 req.ring_grp_tbl_addr =
2087                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2088                                          i * HW_HASH_INDEX_SIZE);
2089                 req.ring_table_pair_index = i;
2090                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2091
2092                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2093                                             BNXT_USE_CHIMP_MB);
2094
2095                 HWRM_CHECK_RESULT();
2096                 HWRM_UNLOCK();
2097         }
2098
2099         return rc;
2100 }
2101
2102 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2103                            struct bnxt_vnic_info *vnic)
2104 {
2105         int rc = 0;
2106         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2107         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2108
2109         if (!vnic->rss_table)
2110                 return 0;
2111
2112         if (BNXT_CHIP_THOR(bp))
2113                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2114
2115         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2116
2117         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2118         req.hash_mode_flags = vnic->hash_mode;
2119
2120         req.ring_grp_tbl_addr =
2121             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2122         req.hash_key_tbl_addr =
2123             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2124         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2125         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2126
2127         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2128
2129         HWRM_CHECK_RESULT();
2130         HWRM_UNLOCK();
2131
2132         return rc;
2133 }
2134
2135 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2136                         struct bnxt_vnic_info *vnic)
2137 {
2138         int rc = 0;
2139         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2140         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2141         uint16_t size;
2142
2143         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2144                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2145                 return rc;
2146         }
2147
2148         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2149
2150         req.flags = rte_cpu_to_le_32(
2151                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2152
2153         req.enables = rte_cpu_to_le_32(
2154                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2155
2156         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2157         size -= RTE_PKTMBUF_HEADROOM;
2158         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2159
2160         req.jumbo_thresh = rte_cpu_to_le_16(size);
2161         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2162
2163         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2164
2165         HWRM_CHECK_RESULT();
2166         HWRM_UNLOCK();
2167
2168         return rc;
2169 }
2170
2171 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2172                         struct bnxt_vnic_info *vnic, bool enable)
2173 {
2174         int rc = 0;
2175         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2176         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2177
2178         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2179                 if (enable)
2180                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2181                 return -ENOTSUP;
2182         }
2183
2184         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2185                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2186                 return 0;
2187         }
2188
2189         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2190
2191         if (enable) {
2192                 req.enables = rte_cpu_to_le_32(
2193                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2194                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2195                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2196                 req.flags = rte_cpu_to_le_32(
2197                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2198                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2199                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2200                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2201                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2202                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2203                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2204                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2205                 req.min_agg_len = rte_cpu_to_le_32(512);
2206         }
2207         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2208
2209         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2210
2211         HWRM_CHECK_RESULT();
2212         HWRM_UNLOCK();
2213
2214         return rc;
2215 }
2216
2217 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2218 {
2219         struct hwrm_func_cfg_input req = {0};
2220         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2221         int rc;
2222
2223         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2224         req.enables = rte_cpu_to_le_32(
2225                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2226         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2227         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2228
2229         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2230
2231         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2232         HWRM_CHECK_RESULT();
2233         HWRM_UNLOCK();
2234
2235         bp->pf.vf_info[vf].random_mac = false;
2236
2237         return rc;
2238 }
2239
2240 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2241                                   uint64_t *dropped)
2242 {
2243         int rc = 0;
2244         struct hwrm_func_qstats_input req = {.req_type = 0};
2245         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2246
2247         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2248
2249         req.fid = rte_cpu_to_le_16(fid);
2250
2251         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2252
2253         HWRM_CHECK_RESULT();
2254
2255         if (dropped)
2256                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2257
2258         HWRM_UNLOCK();
2259
2260         return rc;
2261 }
2262
2263 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2264                           struct rte_eth_stats *stats)
2265 {
2266         int rc = 0;
2267         struct hwrm_func_qstats_input req = {.req_type = 0};
2268         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2269
2270         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2271
2272         req.fid = rte_cpu_to_le_16(fid);
2273
2274         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2275
2276         HWRM_CHECK_RESULT();
2277
2278         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2279         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2280         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2281         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2282         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2283         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2284
2285         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2286         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2287         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2288         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2289         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2290         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2291
2292         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2293         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2294         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2295
2296         HWRM_UNLOCK();
2297
2298         return rc;
2299 }
2300
2301 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2302 {
2303         int rc = 0;
2304         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2305         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2306
2307         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2308
2309         req.fid = rte_cpu_to_le_16(fid);
2310
2311         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2312
2313         HWRM_CHECK_RESULT();
2314         HWRM_UNLOCK();
2315
2316         return rc;
2317 }
2318
2319 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2320 {
2321         unsigned int i;
2322         int rc = 0;
2323
2324         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2325                 struct bnxt_tx_queue *txq;
2326                 struct bnxt_rx_queue *rxq;
2327                 struct bnxt_cp_ring_info *cpr;
2328
2329                 if (i >= bp->rx_cp_nr_rings) {
2330                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2331                         cpr = txq->cp_ring;
2332                 } else {
2333                         rxq = bp->rx_queues[i];
2334                         cpr = rxq->cp_ring;
2335                 }
2336
2337                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2338                 if (rc)
2339                         return rc;
2340         }
2341         return 0;
2342 }
2343
2344 static int
2345 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2346 {
2347         int rc;
2348         unsigned int i;
2349         struct bnxt_cp_ring_info *cpr;
2350
2351         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2352
2353                 if (i >= bp->rx_cp_nr_rings) {
2354                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2355                 } else {
2356                         cpr = bp->rx_queues[i]->cp_ring;
2357                         if (BNXT_HAS_RING_GRPS(bp))
2358                                 bp->grp_info[i].fw_stats_ctx = -1;
2359                 }
2360                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2361                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2362                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2363                         if (rc)
2364                                 return rc;
2365                 }
2366         }
2367         return 0;
2368 }
2369
2370 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2371 {
2372         unsigned int i;
2373         int rc = 0;
2374
2375         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2376                 struct bnxt_tx_queue *txq;
2377                 struct bnxt_rx_queue *rxq;
2378                 struct bnxt_cp_ring_info *cpr;
2379
2380                 if (i >= bp->rx_cp_nr_rings) {
2381                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2382                         cpr = txq->cp_ring;
2383                 } else {
2384                         rxq = bp->rx_queues[i];
2385                         cpr = rxq->cp_ring;
2386                 }
2387
2388                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2389
2390                 if (rc)
2391                         return rc;
2392         }
2393         return rc;
2394 }
2395
2396 static int
2397 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2398 {
2399         uint16_t idx;
2400         uint32_t rc = 0;
2401
2402         if (!BNXT_HAS_RING_GRPS(bp))
2403                 return 0;
2404
2405         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2406
2407                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2408                         continue;
2409
2410                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2411
2412                 if (rc)
2413                         return rc;
2414         }
2415         return rc;
2416 }
2417
2418 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2419 {
2420         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2421
2422         bnxt_hwrm_ring_free(bp, cp_ring,
2423                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2424         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2425         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2426                                      sizeof(*cpr->cp_desc_ring));
2427         cpr->cp_raw_cons = 0;
2428         cpr->valid = 0;
2429 }
2430
2431 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2432 {
2433         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2434
2435         bnxt_hwrm_ring_free(bp, cp_ring,
2436                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2437         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2438         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2439                         sizeof(*cpr->cp_desc_ring));
2440         cpr->cp_raw_cons = 0;
2441         cpr->valid = 0;
2442 }
2443
2444 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2445 {
2446         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2447         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2448         struct bnxt_ring *ring = rxr->rx_ring_struct;
2449         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2450
2451         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2452                 bnxt_hwrm_ring_free(bp, ring,
2453                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2454                 ring->fw_ring_id = INVALID_HW_RING_ID;
2455                 if (BNXT_HAS_RING_GRPS(bp))
2456                         bp->grp_info[queue_index].rx_fw_ring_id =
2457                                                         INVALID_HW_RING_ID;
2458                 memset(rxr->rx_desc_ring, 0,
2459                        rxr->rx_ring_struct->ring_size *
2460                        sizeof(*rxr->rx_desc_ring));
2461                 memset(rxr->rx_buf_ring, 0,
2462                        rxr->rx_ring_struct->ring_size *
2463                        sizeof(*rxr->rx_buf_ring));
2464                 rxr->rx_prod = 0;
2465         }
2466         ring = rxr->ag_ring_struct;
2467         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2468                 bnxt_hwrm_ring_free(bp, ring,
2469                                     BNXT_CHIP_THOR(bp) ?
2470                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2471                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2472                 ring->fw_ring_id = INVALID_HW_RING_ID;
2473                 memset(rxr->ag_buf_ring, 0,
2474                        rxr->ag_ring_struct->ring_size *
2475                        sizeof(*rxr->ag_buf_ring));
2476                 rxr->ag_prod = 0;
2477                 if (BNXT_HAS_RING_GRPS(bp))
2478                         bp->grp_info[queue_index].ag_fw_ring_id =
2479                                                         INVALID_HW_RING_ID;
2480         }
2481         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2482                 bnxt_free_cp_ring(bp, cpr);
2483
2484         if (BNXT_HAS_RING_GRPS(bp))
2485                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2486 }
2487
2488 static int
2489 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2490 {
2491         unsigned int i;
2492
2493         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2494                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2495                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2496                 struct bnxt_ring *ring = txr->tx_ring_struct;
2497                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2498
2499                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2500                         bnxt_hwrm_ring_free(bp, ring,
2501                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2502                         ring->fw_ring_id = INVALID_HW_RING_ID;
2503                         memset(txr->tx_desc_ring, 0,
2504                                         txr->tx_ring_struct->ring_size *
2505                                         sizeof(*txr->tx_desc_ring));
2506                         memset(txr->tx_buf_ring, 0,
2507                                         txr->tx_ring_struct->ring_size *
2508                                         sizeof(*txr->tx_buf_ring));
2509                         txr->tx_prod = 0;
2510                         txr->tx_cons = 0;
2511                 }
2512                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2513                         bnxt_free_cp_ring(bp, cpr);
2514                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2515                 }
2516         }
2517
2518         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2519                 bnxt_free_hwrm_rx_ring(bp, i);
2520
2521         return 0;
2522 }
2523
2524 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2525 {
2526         uint16_t i;
2527         uint32_t rc = 0;
2528
2529         if (!BNXT_HAS_RING_GRPS(bp))
2530                 return 0;
2531
2532         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2533                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2534                 if (rc)
2535                         return rc;
2536         }
2537         return rc;
2538 }
2539
2540 /*
2541  * HWRM utility functions
2542  */
2543
2544 void bnxt_free_hwrm_resources(struct bnxt *bp)
2545 {
2546         /* Release memzone */
2547         rte_free(bp->hwrm_cmd_resp_addr);
2548         rte_free(bp->hwrm_short_cmd_req_addr);
2549         bp->hwrm_cmd_resp_addr = NULL;
2550         bp->hwrm_short_cmd_req_addr = NULL;
2551         bp->hwrm_cmd_resp_dma_addr = 0;
2552         bp->hwrm_short_cmd_req_dma_addr = 0;
2553 }
2554
2555 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2556 {
2557         struct rte_pci_device *pdev = bp->pdev;
2558         char type[RTE_MEMZONE_NAMESIZE];
2559
2560         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2561                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2562         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2563         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2564         if (bp->hwrm_cmd_resp_addr == NULL)
2565                 return -ENOMEM;
2566         bp->hwrm_cmd_resp_dma_addr =
2567                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2568         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2569                 PMD_DRV_LOG(ERR,
2570                         "unable to map response address to physical memory\n");
2571                 return -ENOMEM;
2572         }
2573         rte_spinlock_init(&bp->hwrm_lock);
2574
2575         return 0;
2576 }
2577
2578 static int
2579 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2580 {
2581         struct bnxt_filter_info *filter;
2582         int rc = 0;
2583
2584         STAILQ_FOREACH(filter, &vnic->filter, next) {
2585                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2586                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2587                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2588                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2589                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2590                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2591                 bnxt_free_filter(bp, filter);
2592         }
2593         return rc;
2594 }
2595
2596 static int
2597 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2598 {
2599         struct bnxt_filter_info *filter;
2600         struct rte_flow *flow;
2601         int rc = 0;
2602
2603         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2604                 flow = STAILQ_FIRST(&vnic->flow_list);
2605                 filter = flow->filter;
2606                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2607                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2608                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2609                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2610                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2611                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2612
2613                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2614                 rte_free(flow);
2615         }
2616         return rc;
2617 }
2618
2619 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2620 {
2621         struct bnxt_filter_info *filter;
2622         int rc = 0;
2623
2624         STAILQ_FOREACH(filter, &vnic->filter, next) {
2625                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2626                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2627                                                      filter);
2628                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2629                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2630                                                          filter);
2631                 else
2632                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2633                                                      filter);
2634                 if (rc)
2635                         break;
2636         }
2637         return rc;
2638 }
2639
2640 static void
2641 bnxt_free_tunnel_ports(struct bnxt *bp)
2642 {
2643         if (bp->vxlan_port_cnt)
2644                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2645                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2646         bp->vxlan_port = 0;
2647         if (bp->geneve_port_cnt)
2648                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2649                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2650         bp->geneve_port = 0;
2651 }
2652
2653 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2654 {
2655         int i;
2656
2657         if (bp->vnic_info == NULL)
2658                 return;
2659
2660         /*
2661          * Cleanup VNICs in reverse order, to make sure the L2 filter
2662          * from vnic0 is last to be cleaned up.
2663          */
2664         for (i = bp->max_vnics - 1; i >= 0; i--) {
2665                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2666
2667                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2668                         continue;
2669
2670                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2671
2672                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2673
2674                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2675
2676                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2677
2678                 bnxt_hwrm_vnic_free(bp, vnic);
2679
2680                 rte_free(vnic->fw_grp_ids);
2681         }
2682         /* Ring resources */
2683         bnxt_free_all_hwrm_rings(bp);
2684         bnxt_free_all_hwrm_ring_grps(bp);
2685         bnxt_free_all_hwrm_stat_ctxs(bp);
2686         bnxt_free_tunnel_ports(bp);
2687 }
2688
2689 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2690 {
2691         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2692
2693         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2694                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2695
2696         switch (conf_link_speed) {
2697         case ETH_LINK_SPEED_10M_HD:
2698         case ETH_LINK_SPEED_100M_HD:
2699                 /* FALLTHROUGH */
2700                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2701         }
2702         return hw_link_duplex;
2703 }
2704
2705 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2706 {
2707         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2708 }
2709
2710 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2711 {
2712         uint16_t eth_link_speed = 0;
2713
2714         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2715                 return ETH_LINK_SPEED_AUTONEG;
2716
2717         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2718         case ETH_LINK_SPEED_100M:
2719         case ETH_LINK_SPEED_100M_HD:
2720                 /* FALLTHROUGH */
2721                 eth_link_speed =
2722                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2723                 break;
2724         case ETH_LINK_SPEED_1G:
2725                 eth_link_speed =
2726                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2727                 break;
2728         case ETH_LINK_SPEED_2_5G:
2729                 eth_link_speed =
2730                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2731                 break;
2732         case ETH_LINK_SPEED_10G:
2733                 eth_link_speed =
2734                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2735                 break;
2736         case ETH_LINK_SPEED_20G:
2737                 eth_link_speed =
2738                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2739                 break;
2740         case ETH_LINK_SPEED_25G:
2741                 eth_link_speed =
2742                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2743                 break;
2744         case ETH_LINK_SPEED_40G:
2745                 eth_link_speed =
2746                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2747                 break;
2748         case ETH_LINK_SPEED_50G:
2749                 eth_link_speed =
2750                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2751                 break;
2752         case ETH_LINK_SPEED_100G:
2753                 eth_link_speed =
2754                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2755                 break;
2756         default:
2757                 PMD_DRV_LOG(ERR,
2758                         "Unsupported link speed %d; default to AUTO\n",
2759                         conf_link_speed);
2760                 break;
2761         }
2762         return eth_link_speed;
2763 }
2764
2765 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2766                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2767                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2768                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2769
2770 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2771 {
2772         uint32_t one_speed;
2773
2774         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2775                 return 0;
2776
2777         if (link_speed & ETH_LINK_SPEED_FIXED) {
2778                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2779
2780                 if (one_speed & (one_speed - 1)) {
2781                         PMD_DRV_LOG(ERR,
2782                                 "Invalid advertised speeds (%u) for port %u\n",
2783                                 link_speed, port_id);
2784                         return -EINVAL;
2785                 }
2786                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2787                         PMD_DRV_LOG(ERR,
2788                                 "Unsupported advertised speed (%u) for port %u\n",
2789                                 link_speed, port_id);
2790                         return -EINVAL;
2791                 }
2792         } else {
2793                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2794                         PMD_DRV_LOG(ERR,
2795                                 "Unsupported advertised speeds (%u) for port %u\n",
2796                                 link_speed, port_id);
2797                         return -EINVAL;
2798                 }
2799         }
2800         return 0;
2801 }
2802
2803 static uint16_t
2804 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2805 {
2806         uint16_t ret = 0;
2807
2808         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2809                 if (bp->link_info.support_speeds)
2810                         return bp->link_info.support_speeds;
2811                 link_speed = BNXT_SUPPORTED_SPEEDS;
2812         }
2813
2814         if (link_speed & ETH_LINK_SPEED_100M)
2815                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2816         if (link_speed & ETH_LINK_SPEED_100M_HD)
2817                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2818         if (link_speed & ETH_LINK_SPEED_1G)
2819                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2820         if (link_speed & ETH_LINK_SPEED_2_5G)
2821                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2822         if (link_speed & ETH_LINK_SPEED_10G)
2823                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2824         if (link_speed & ETH_LINK_SPEED_20G)
2825                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2826         if (link_speed & ETH_LINK_SPEED_25G)
2827                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2828         if (link_speed & ETH_LINK_SPEED_40G)
2829                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2830         if (link_speed & ETH_LINK_SPEED_50G)
2831                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2832         if (link_speed & ETH_LINK_SPEED_100G)
2833                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2834         return ret;
2835 }
2836
2837 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2838 {
2839         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2840
2841         switch (hw_link_speed) {
2842         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2843                 eth_link_speed = ETH_SPEED_NUM_100M;
2844                 break;
2845         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2846                 eth_link_speed = ETH_SPEED_NUM_1G;
2847                 break;
2848         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2849                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2850                 break;
2851         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2852                 eth_link_speed = ETH_SPEED_NUM_10G;
2853                 break;
2854         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2855                 eth_link_speed = ETH_SPEED_NUM_20G;
2856                 break;
2857         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2858                 eth_link_speed = ETH_SPEED_NUM_25G;
2859                 break;
2860         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2861                 eth_link_speed = ETH_SPEED_NUM_40G;
2862                 break;
2863         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2864                 eth_link_speed = ETH_SPEED_NUM_50G;
2865                 break;
2866         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2867                 eth_link_speed = ETH_SPEED_NUM_100G;
2868                 break;
2869         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2870         default:
2871                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2872                         hw_link_speed);
2873                 break;
2874         }
2875         return eth_link_speed;
2876 }
2877
2878 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2879 {
2880         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2881
2882         switch (hw_link_duplex) {
2883         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2884         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2885                 /* FALLTHROUGH */
2886                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2887                 break;
2888         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2889                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2890                 break;
2891         default:
2892                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2893                         hw_link_duplex);
2894                 break;
2895         }
2896         return eth_link_duplex;
2897 }
2898
2899 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2900 {
2901         int rc = 0;
2902         struct bnxt_link_info *link_info = &bp->link_info;
2903
2904         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2905         if (rc) {
2906                 PMD_DRV_LOG(ERR,
2907                         "Get link config failed with rc %d\n", rc);
2908                 goto exit;
2909         }
2910         if (link_info->link_speed)
2911                 link->link_speed =
2912                         bnxt_parse_hw_link_speed(link_info->link_speed);
2913         else
2914                 link->link_speed = ETH_SPEED_NUM_NONE;
2915         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2916         link->link_status = link_info->link_up;
2917         link->link_autoneg = link_info->auto_mode ==
2918                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2919                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2920 exit:
2921         return rc;
2922 }
2923
2924 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2925 {
2926         int rc = 0;
2927         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2928         struct bnxt_link_info link_req;
2929         uint16_t speed, autoneg;
2930
2931         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2932                 return 0;
2933
2934         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2935                         bp->eth_dev->data->port_id);
2936         if (rc)
2937                 goto error;
2938
2939         memset(&link_req, 0, sizeof(link_req));
2940         link_req.link_up = link_up;
2941         if (!link_up)
2942                 goto port_phy_cfg;
2943
2944         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2945         if (BNXT_CHIP_THOR(bp) &&
2946             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2947                 /* 40G is not supported as part of media auto detect.
2948                  * The speed should be forced and autoneg disabled
2949                  * to configure 40G speed.
2950                  */
2951                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2952                 autoneg = 0;
2953         }
2954
2955         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2956         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2957         /* Autoneg can be done only when the FW allows.
2958          * When user configures fixed speed of 40G and later changes to
2959          * any other speed, auto_link_speed/force_link_speed is still set
2960          * to 40G until link comes up at new speed.
2961          */
2962         if (autoneg == 1 &&
2963             !(!BNXT_CHIP_THOR(bp) &&
2964               (bp->link_info.auto_link_speed ||
2965                bp->link_info.force_link_speed))) {
2966                 link_req.phy_flags |=
2967                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2968                 link_req.auto_link_speed_mask =
2969                         bnxt_parse_eth_link_speed_mask(bp,
2970                                                        dev_conf->link_speeds);
2971         } else {
2972                 if (bp->link_info.phy_type ==
2973                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2974                     bp->link_info.phy_type ==
2975                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2976                     bp->link_info.media_type ==
2977                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2978                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2979                         return -EINVAL;
2980                 }
2981
2982                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2983                 /* If user wants a particular speed try that first. */
2984                 if (speed)
2985                         link_req.link_speed = speed;
2986                 else if (bp->link_info.force_link_speed)
2987                         link_req.link_speed = bp->link_info.force_link_speed;
2988                 else
2989                         link_req.link_speed = bp->link_info.auto_link_speed;
2990         }
2991         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2992         link_req.auto_pause = bp->link_info.auto_pause;
2993         link_req.force_pause = bp->link_info.force_pause;
2994
2995 port_phy_cfg:
2996         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2997         if (rc) {
2998                 PMD_DRV_LOG(ERR,
2999                         "Set link config failed with rc %d\n", rc);
3000         }
3001
3002 error:
3003         return rc;
3004 }
3005
3006 /* JIRA 22088 */
3007 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3008 {
3009         struct hwrm_func_qcfg_input req = {0};
3010         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3011         uint16_t flags;
3012         int rc = 0;
3013         bp->func_svif = BNXT_SVIF_INVALID;
3014         uint16_t svif_info;
3015
3016         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3017         req.fid = rte_cpu_to_le_16(0xffff);
3018
3019         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3020
3021         HWRM_CHECK_RESULT();
3022
3023         /* Hard Coded.. 0xfff VLAN ID mask */
3024         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3025
3026         svif_info = rte_le_to_cpu_16(resp->svif_info);
3027         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3028                 bp->func_svif = svif_info &
3029                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3030
3031         flags = rte_le_to_cpu_16(resp->flags);
3032         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3033                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3034
3035         if (BNXT_VF(bp) &&
3036             !BNXT_VF_IS_TRUSTED(bp) &&
3037             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3038                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3039                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3040         } else if (BNXT_VF(bp) &&
3041                    BNXT_VF_IS_TRUSTED(bp) &&
3042                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3043                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3044                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3045         }
3046
3047         if (mtu)
3048                 *mtu = rte_le_to_cpu_16(resp->mtu);
3049
3050         switch (resp->port_partition_type) {
3051         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3052         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3053         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3054                 /* FALLTHROUGH */
3055                 bp->flags |= BNXT_FLAG_NPAR_PF;
3056                 break;
3057         default:
3058                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3059                 break;
3060         }
3061
3062         HWRM_UNLOCK();
3063
3064         return rc;
3065 }
3066
3067 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3068 {
3069         struct hwrm_port_mac_qcfg_input req = {0};
3070         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3071         uint16_t port_svif_info;
3072         int rc;
3073
3074         bp->port_svif = BNXT_SVIF_INVALID;
3075
3076         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3077
3078         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3079
3080         HWRM_CHECK_RESULT();
3081
3082         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3083         if (port_svif_info &
3084             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3085                 bp->port_svif = port_svif_info &
3086                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3087
3088         HWRM_UNLOCK();
3089
3090         return 0;
3091 }
3092
3093 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3094                                    struct hwrm_func_qcaps_output *qcaps)
3095 {
3096         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3097         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3098                sizeof(qcaps->mac_address));
3099         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3100         qcaps->max_rx_rings = fcfg->num_rx_rings;
3101         qcaps->max_tx_rings = fcfg->num_tx_rings;
3102         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3103         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3104         qcaps->max_vfs = 0;
3105         qcaps->first_vf_id = 0;
3106         qcaps->max_vnics = fcfg->num_vnics;
3107         qcaps->max_decap_records = 0;
3108         qcaps->max_encap_records = 0;
3109         qcaps->max_tx_wm_flows = 0;
3110         qcaps->max_tx_em_flows = 0;
3111         qcaps->max_rx_wm_flows = 0;
3112         qcaps->max_rx_em_flows = 0;
3113         qcaps->max_flow_id = 0;
3114         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3115         qcaps->max_sp_tx_rings = 0;
3116         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3117 }
3118
3119 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3120 {
3121         struct hwrm_func_cfg_input req = {0};
3122         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3123         uint32_t enables;
3124         int rc;
3125
3126         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3127                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3128                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3129                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3130                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3131                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3132                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3133                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3134                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3135
3136         if (BNXT_HAS_RING_GRPS(bp)) {
3137                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3138                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3139         } else if (BNXT_HAS_NQ(bp)) {
3140                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3141                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3142         }
3143
3144         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3145         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3146         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3147         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3148         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3149         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3150         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3151         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3152         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3153         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3154         req.fid = rte_cpu_to_le_16(0xffff);
3155         req.enables = rte_cpu_to_le_32(enables);
3156
3157         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3158
3159         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3160
3161         HWRM_CHECK_RESULT();
3162         HWRM_UNLOCK();
3163
3164         return rc;
3165 }
3166
3167 static void populate_vf_func_cfg_req(struct bnxt *bp,
3168                                      struct hwrm_func_cfg_input *req,
3169                                      int num_vfs)
3170 {
3171         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3172                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3173                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3174                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3175                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3176                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3177                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3178                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3179                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3180                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3181
3182         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3183                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3184                                     BNXT_NUM_VLANS);
3185         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3186         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3187                                                 (num_vfs + 1));
3188         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3189         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3190                                                (num_vfs + 1));
3191         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3192         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3193         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3194         /* TODO: For now, do not support VMDq/RFS on VFs. */
3195         req->num_vnics = rte_cpu_to_le_16(1);
3196         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3197                                                  (num_vfs + 1));
3198 }
3199
3200 static void add_random_mac_if_needed(struct bnxt *bp,
3201                                      struct hwrm_func_cfg_input *cfg_req,
3202                                      int vf)
3203 {
3204         struct rte_ether_addr mac;
3205
3206         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3207                 return;
3208
3209         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3210                 cfg_req->enables |=
3211                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3212                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3213                 bp->pf.vf_info[vf].random_mac = true;
3214         } else {
3215                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3216                         RTE_ETHER_ADDR_LEN);
3217         }
3218 }
3219
3220 static int reserve_resources_from_vf(struct bnxt *bp,
3221                                      struct hwrm_func_cfg_input *cfg_req,
3222                                      int vf)
3223 {
3224         struct hwrm_func_qcaps_input req = {0};
3225         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3226         int rc;
3227
3228         /* Get the actual allocated values now */
3229         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3230         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3231         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3232
3233         if (rc) {
3234                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3235                 copy_func_cfg_to_qcaps(cfg_req, resp);
3236         } else if (resp->error_code) {
3237                 rc = rte_le_to_cpu_16(resp->error_code);
3238                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3239                 copy_func_cfg_to_qcaps(cfg_req, resp);
3240         }
3241
3242         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3243         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3244         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3245         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3246         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3247         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3248         /*
3249          * TODO: While not supporting VMDq with VFs, max_vnics is always
3250          * forced to 1 in this case
3251          */
3252         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3253         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3254
3255         HWRM_UNLOCK();
3256
3257         return 0;
3258 }
3259
3260 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3261 {
3262         struct hwrm_func_qcfg_input req = {0};
3263         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3264         int rc;
3265
3266         /* Check for zero MAC address */
3267         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3268         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3269         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3270         HWRM_CHECK_RESULT();
3271         rc = rte_le_to_cpu_16(resp->vlan);
3272
3273         HWRM_UNLOCK();
3274
3275         return rc;
3276 }
3277
3278 static int update_pf_resource_max(struct bnxt *bp)
3279 {
3280         struct hwrm_func_qcfg_input req = {0};
3281         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3282         int rc;
3283
3284         /* And copy the allocated numbers into the pf struct */
3285         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3286         req.fid = rte_cpu_to_le_16(0xffff);
3287         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3288         HWRM_CHECK_RESULT();
3289
3290         /* Only TX ring value reflects actual allocation? TODO */
3291         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3292         bp->pf.evb_mode = resp->evb_mode;
3293
3294         HWRM_UNLOCK();
3295
3296         return rc;
3297 }
3298
3299 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3300 {
3301         int rc;
3302
3303         if (!BNXT_PF(bp)) {
3304                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3305                 return -EINVAL;
3306         }
3307
3308         rc = bnxt_hwrm_func_qcaps(bp);
3309         if (rc)
3310                 return rc;
3311
3312         bp->pf.func_cfg_flags &=
3313                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3314                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3315         bp->pf.func_cfg_flags |=
3316                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3317         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3318         rc = __bnxt_hwrm_func_qcaps(bp);
3319         return rc;
3320 }
3321
3322 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3323 {
3324         struct hwrm_func_cfg_input req = {0};
3325         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3326         int i;
3327         size_t sz;
3328         int rc = 0;
3329         size_t req_buf_sz;
3330
3331         if (!BNXT_PF(bp)) {
3332                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3333                 return -EINVAL;
3334         }
3335
3336         rc = bnxt_hwrm_func_qcaps(bp);
3337
3338         if (rc)
3339                 return rc;
3340
3341         bp->pf.active_vfs = num_vfs;
3342
3343         /*
3344          * First, configure the PF to only use one TX ring.  This ensures that
3345          * there are enough rings for all VFs.
3346          *
3347          * If we don't do this, when we call func_alloc() later, we will lock
3348          * extra rings to the PF that won't be available during func_cfg() of
3349          * the VFs.
3350          *
3351          * This has been fixed with firmware versions above 20.6.54
3352          */
3353         bp->pf.func_cfg_flags &=
3354                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3355                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3356         bp->pf.func_cfg_flags |=
3357                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3358         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3359         if (rc)
3360                 return rc;
3361
3362         /*
3363          * Now, create and register a buffer to hold forwarded VF requests
3364          */
3365         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3366         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3367                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3368         if (bp->pf.vf_req_buf == NULL) {
3369                 rc = -ENOMEM;
3370                 goto error_free;
3371         }
3372         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3373                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3374         for (i = 0; i < num_vfs; i++)
3375                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3376                                         (i * HWRM_MAX_REQ_LEN);
3377
3378         rc = bnxt_hwrm_func_buf_rgtr(bp);
3379         if (rc)
3380                 goto error_free;
3381
3382         populate_vf_func_cfg_req(bp, &req, num_vfs);
3383
3384         bp->pf.active_vfs = 0;
3385         for (i = 0; i < num_vfs; i++) {
3386                 add_random_mac_if_needed(bp, &req, i);
3387
3388                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3389                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3390                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3391                 rc = bnxt_hwrm_send_message(bp,
3392                                             &req,
3393                                             sizeof(req),
3394                                             BNXT_USE_CHIMP_MB);
3395
3396                 /* Clear enable flag for next pass */
3397                 req.enables &= ~rte_cpu_to_le_32(
3398                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3399
3400                 if (rc || resp->error_code) {
3401                         PMD_DRV_LOG(ERR,
3402                                 "Failed to initizlie VF %d\n", i);
3403                         PMD_DRV_LOG(ERR,
3404                                 "Not all VFs available. (%d, %d)\n",
3405                                 rc, resp->error_code);
3406                         HWRM_UNLOCK();
3407                         break;
3408                 }
3409
3410                 HWRM_UNLOCK();
3411
3412                 reserve_resources_from_vf(bp, &req, i);
3413                 bp->pf.active_vfs++;
3414                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3415         }
3416
3417         /*
3418          * Now configure the PF to use "the rest" of the resources
3419          * We're using STD_TX_RING_MODE here though which will limit the TX
3420          * rings.  This will allow QoS to function properly.  Not setting this
3421          * will cause PF rings to break bandwidth settings.
3422          */
3423         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3424         if (rc)
3425                 goto error_free;
3426
3427         rc = update_pf_resource_max(bp);
3428         if (rc)
3429                 goto error_free;
3430
3431         return rc;
3432
3433 error_free:
3434         bnxt_hwrm_func_buf_unrgtr(bp);
3435         return rc;
3436 }
3437
3438 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3439 {
3440         struct hwrm_func_cfg_input req = {0};
3441         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3442         int rc;
3443
3444         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3445
3446         req.fid = rte_cpu_to_le_16(0xffff);
3447         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3448         req.evb_mode = bp->pf.evb_mode;
3449
3450         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3451         HWRM_CHECK_RESULT();
3452         HWRM_UNLOCK();
3453
3454         return rc;
3455 }
3456
3457 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3458                                 uint8_t tunnel_type)
3459 {
3460         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3461         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3462         int rc = 0;
3463
3464         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3465         req.tunnel_type = tunnel_type;
3466         req.tunnel_dst_port_val = port;
3467         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3468         HWRM_CHECK_RESULT();
3469
3470         switch (tunnel_type) {
3471         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3472                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3473                 bp->vxlan_port = port;
3474                 break;
3475         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3476                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3477                 bp->geneve_port = port;
3478                 break;
3479         default:
3480                 break;
3481         }
3482
3483         HWRM_UNLOCK();
3484
3485         return rc;
3486 }
3487
3488 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3489                                 uint8_t tunnel_type)
3490 {
3491         struct hwrm_tunnel_dst_port_free_input req = {0};
3492         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3493         int rc = 0;
3494
3495         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3496
3497         req.tunnel_type = tunnel_type;
3498         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3499         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3500
3501         HWRM_CHECK_RESULT();
3502         HWRM_UNLOCK();
3503
3504         return rc;
3505 }
3506
3507 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3508                                         uint32_t flags)
3509 {
3510         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3511         struct hwrm_func_cfg_input req = {0};
3512         int rc;
3513
3514         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3515
3516         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3517         req.flags = rte_cpu_to_le_32(flags);
3518         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3519
3520         HWRM_CHECK_RESULT();
3521         HWRM_UNLOCK();
3522
3523         return rc;
3524 }
3525
3526 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3527 {
3528         uint32_t *flag = flagp;
3529
3530         vnic->flags = *flag;
3531 }
3532
3533 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3534 {
3535         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3536 }
3537
3538 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3539 {
3540         int rc = 0;
3541         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3542         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3543
3544         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3545
3546         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3547         req.req_buf_page_size = rte_cpu_to_le_16(
3548                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3549         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3550         req.req_buf_page_addr0 =
3551                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf.vf_req_buf));
3552         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3553                 PMD_DRV_LOG(ERR,
3554                         "unable to map buffer address to physical memory\n");
3555                 return -ENOMEM;
3556         }
3557
3558         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3559
3560         HWRM_CHECK_RESULT();
3561         HWRM_UNLOCK();
3562
3563         return rc;
3564 }
3565
3566 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3567 {
3568         int rc = 0;
3569         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3570         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3571
3572         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3573                 return 0;
3574
3575         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3576
3577         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3578
3579         HWRM_CHECK_RESULT();
3580         HWRM_UNLOCK();
3581
3582         return rc;
3583 }
3584
3585 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3586 {
3587         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3588         struct hwrm_func_cfg_input req = {0};
3589         int rc;
3590
3591         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3592
3593         req.fid = rte_cpu_to_le_16(0xffff);
3594         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3595         req.enables = rte_cpu_to_le_32(
3596                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3597         req.async_event_cr = rte_cpu_to_le_16(
3598                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3600
3601         HWRM_CHECK_RESULT();
3602         HWRM_UNLOCK();
3603
3604         return rc;
3605 }
3606
3607 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3608 {
3609         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3610         struct hwrm_func_vf_cfg_input req = {0};
3611         int rc;
3612
3613         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3614
3615         req.enables = rte_cpu_to_le_32(
3616                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3617         req.async_event_cr = rte_cpu_to_le_16(
3618                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3619         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3620
3621         HWRM_CHECK_RESULT();
3622         HWRM_UNLOCK();
3623
3624         return rc;
3625 }
3626
3627 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3628 {
3629         struct hwrm_func_cfg_input req = {0};
3630         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3631         uint16_t dflt_vlan, fid;
3632         uint32_t func_cfg_flags;
3633         int rc = 0;
3634
3635         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3636
3637         if (is_vf) {
3638                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3639                 fid = bp->pf.vf_info[vf].fid;
3640                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3641         } else {
3642                 fid = rte_cpu_to_le_16(0xffff);
3643                 func_cfg_flags = bp->pf.func_cfg_flags;
3644                 dflt_vlan = bp->vlan;
3645         }
3646
3647         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3648         req.fid = rte_cpu_to_le_16(fid);
3649         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3650         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3651
3652         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3653
3654         HWRM_CHECK_RESULT();
3655         HWRM_UNLOCK();
3656
3657         return rc;
3658 }
3659
3660 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3661                         uint16_t max_bw, uint16_t enables)
3662 {
3663         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3664         struct hwrm_func_cfg_input req = {0};
3665         int rc;
3666
3667         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3668
3669         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3670         req.enables |= rte_cpu_to_le_32(enables);
3671         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3672         req.max_bw = rte_cpu_to_le_32(max_bw);
3673         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3674
3675         HWRM_CHECK_RESULT();
3676         HWRM_UNLOCK();
3677
3678         return rc;
3679 }
3680
3681 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3682 {
3683         struct hwrm_func_cfg_input req = {0};
3684         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3685         int rc = 0;
3686
3687         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3688
3689         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3690         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3691         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3692         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3693
3694         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3695
3696         HWRM_CHECK_RESULT();
3697         HWRM_UNLOCK();
3698
3699         return rc;
3700 }
3701
3702 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3703 {
3704         int rc;
3705
3706         if (BNXT_PF(bp))
3707                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3708         else
3709                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3710
3711         return rc;
3712 }
3713
3714 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3715                               void *encaped, size_t ec_size)
3716 {
3717         int rc = 0;
3718         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3719         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3720
3721         if (ec_size > sizeof(req.encap_request))
3722                 return -1;
3723
3724         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3725
3726         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3727         memcpy(req.encap_request, encaped, ec_size);
3728
3729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3730
3731         HWRM_CHECK_RESULT();
3732         HWRM_UNLOCK();
3733
3734         return rc;
3735 }
3736
3737 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3738                                        struct rte_ether_addr *mac)
3739 {
3740         struct hwrm_func_qcfg_input req = {0};
3741         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3742         int rc;
3743
3744         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3745
3746         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3747         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3748
3749         HWRM_CHECK_RESULT();
3750
3751         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3752
3753         HWRM_UNLOCK();
3754
3755         return rc;
3756 }
3757
3758 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3759                             void *encaped, size_t ec_size)
3760 {
3761         int rc = 0;
3762         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3763         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3764
3765         if (ec_size > sizeof(req.encap_request))
3766                 return -1;
3767
3768         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3769
3770         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3771         memcpy(req.encap_request, encaped, ec_size);
3772
3773         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3774
3775         HWRM_CHECK_RESULT();
3776         HWRM_UNLOCK();
3777
3778         return rc;
3779 }
3780
3781 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3782                          struct rte_eth_stats *stats, uint8_t rx)
3783 {
3784         int rc = 0;
3785         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3786         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3787
3788         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3789
3790         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3791
3792         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3793
3794         HWRM_CHECK_RESULT();
3795
3796         if (rx) {
3797                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3798                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3799                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3800                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3801                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3802                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3803                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3804                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3805         } else {
3806                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3807                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3808                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3809                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3810                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3811                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3812         }
3813
3814         HWRM_UNLOCK();
3815
3816         return rc;
3817 }
3818
3819 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3820 {
3821         struct hwrm_port_qstats_input req = {0};
3822         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3823         struct bnxt_pf_info *pf = &bp->pf;
3824         int rc;
3825
3826         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
3827
3828         req.port_id = rte_cpu_to_le_16(pf->port_id);
3829         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3830         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3831         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3832
3833         HWRM_CHECK_RESULT();
3834         HWRM_UNLOCK();
3835
3836         return rc;
3837 }
3838
3839 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3840 {
3841         struct hwrm_port_clr_stats_input req = {0};
3842         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3843         struct bnxt_pf_info *pf = &bp->pf;
3844         int rc;
3845
3846         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3847         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3848             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3849                 return 0;
3850
3851         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3852
3853         req.port_id = rte_cpu_to_le_16(pf->port_id);
3854         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3855
3856         HWRM_CHECK_RESULT();
3857         HWRM_UNLOCK();
3858
3859         return rc;
3860 }
3861
3862 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3863 {
3864         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3865         struct hwrm_port_led_qcaps_input req = {0};
3866         int rc;
3867
3868         if (BNXT_VF(bp))
3869                 return 0;
3870
3871         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3872         req.port_id = bp->pf.port_id;
3873         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3874
3875         HWRM_CHECK_RESULT();
3876
3877         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3878                 unsigned int i;
3879
3880                 bp->num_leds = resp->num_leds;
3881                 memcpy(bp->leds, &resp->led0_id,
3882                         sizeof(bp->leds[0]) * bp->num_leds);
3883                 for (i = 0; i < bp->num_leds; i++) {
3884                         struct bnxt_led_info *led = &bp->leds[i];
3885
3886                         uint16_t caps = led->led_state_caps;
3887
3888                         if (!led->led_group_id ||
3889                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3890                                 bp->num_leds = 0;
3891                                 break;
3892                         }
3893                 }
3894         }
3895
3896         HWRM_UNLOCK();
3897
3898         return rc;
3899 }
3900
3901 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3902 {
3903         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3904         struct hwrm_port_led_cfg_input req = {0};
3905         struct bnxt_led_cfg *led_cfg;
3906         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3907         uint16_t duration = 0;
3908         int rc, i;
3909
3910         if (!bp->num_leds || BNXT_VF(bp))
3911                 return -EOPNOTSUPP;
3912
3913         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3914
3915         if (led_on) {
3916                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3917                 duration = rte_cpu_to_le_16(500);
3918         }
3919         req.port_id = bp->pf.port_id;
3920         req.num_leds = bp->num_leds;
3921         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3922         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3923                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3924                 led_cfg->led_id = bp->leds[i].led_id;
3925                 led_cfg->led_state = led_state;
3926                 led_cfg->led_blink_on = duration;
3927                 led_cfg->led_blink_off = duration;
3928                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3929         }
3930
3931         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3932
3933         HWRM_CHECK_RESULT();
3934         HWRM_UNLOCK();
3935
3936         return rc;
3937 }
3938
3939 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3940                                uint32_t *length)
3941 {
3942         int rc;
3943         struct hwrm_nvm_get_dir_info_input req = {0};
3944         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3945
3946         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3947
3948         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3949
3950         HWRM_CHECK_RESULT();
3951
3952         *entries = rte_le_to_cpu_32(resp->entries);
3953         *length = rte_le_to_cpu_32(resp->entry_length);
3954
3955         HWRM_UNLOCK();
3956         return rc;
3957 }
3958
3959 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3960 {
3961         int rc;
3962         uint32_t dir_entries;
3963         uint32_t entry_length;
3964         uint8_t *buf;
3965         size_t buflen;
3966         rte_iova_t dma_handle;
3967         struct hwrm_nvm_get_dir_entries_input req = {0};
3968         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3969
3970         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3971         if (rc != 0)
3972                 return rc;
3973
3974         *data++ = dir_entries;
3975         *data++ = entry_length;
3976         len -= 2;
3977         memset(data, 0xff, len);
3978
3979         buflen = dir_entries * entry_length;
3980         buf = rte_malloc("nvm_dir", buflen, 0);
3981         if (buf == NULL)
3982                 return -ENOMEM;
3983         dma_handle = rte_malloc_virt2iova(buf);
3984         if (dma_handle == RTE_BAD_IOVA) {
3985                 PMD_DRV_LOG(ERR,
3986                         "unable to map response address to physical memory\n");
3987                 return -ENOMEM;
3988         }
3989         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3990         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3991         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3992
3993         if (rc == 0)
3994                 memcpy(data, buf, len > buflen ? buflen : len);
3995
3996         rte_free(buf);
3997         HWRM_CHECK_RESULT();
3998         HWRM_UNLOCK();
3999
4000         return rc;
4001 }
4002
4003 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4004                              uint32_t offset, uint32_t length,
4005                              uint8_t *data)
4006 {
4007         int rc;
4008         uint8_t *buf;
4009         rte_iova_t dma_handle;
4010         struct hwrm_nvm_read_input req = {0};
4011         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4012
4013         buf = rte_malloc("nvm_item", length, 0);
4014         if (!buf)
4015                 return -ENOMEM;
4016
4017         dma_handle = rte_malloc_virt2iova(buf);
4018         if (dma_handle == RTE_BAD_IOVA) {
4019                 PMD_DRV_LOG(ERR,
4020                         "unable to map response address to physical memory\n");
4021                 return -ENOMEM;
4022         }
4023         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4024         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4025         req.dir_idx = rte_cpu_to_le_16(index);
4026         req.offset = rte_cpu_to_le_32(offset);
4027         req.len = rte_cpu_to_le_32(length);
4028         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4029         if (rc == 0)
4030                 memcpy(data, buf, length);
4031
4032         rte_free(buf);
4033         HWRM_CHECK_RESULT();
4034         HWRM_UNLOCK();
4035
4036         return rc;
4037 }
4038
4039 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4040 {
4041         int rc;
4042         struct hwrm_nvm_erase_dir_entry_input req = {0};
4043         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4044
4045         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4046         req.dir_idx = rte_cpu_to_le_16(index);
4047         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4048         HWRM_CHECK_RESULT();
4049         HWRM_UNLOCK();
4050
4051         return rc;
4052 }
4053
4054
4055 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4056                           uint16_t dir_ordinal, uint16_t dir_ext,
4057                           uint16_t dir_attr, const uint8_t *data,
4058                           size_t data_len)
4059 {
4060         int rc;
4061         struct hwrm_nvm_write_input req = {0};
4062         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4063         rte_iova_t dma_handle;
4064         uint8_t *buf;
4065
4066         buf = rte_malloc("nvm_write", data_len, 0);
4067         if (!buf)
4068                 return -ENOMEM;
4069
4070         dma_handle = rte_malloc_virt2iova(buf);
4071         if (dma_handle == RTE_BAD_IOVA) {
4072                 PMD_DRV_LOG(ERR,
4073                         "unable to map response address to physical memory\n");
4074                 return -ENOMEM;
4075         }
4076         memcpy(buf, data, data_len);
4077
4078         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4079
4080         req.dir_type = rte_cpu_to_le_16(dir_type);
4081         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4082         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4083         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4084         req.dir_data_length = rte_cpu_to_le_32(data_len);
4085         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4086
4087         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4088
4089         rte_free(buf);
4090         HWRM_CHECK_RESULT();
4091         HWRM_UNLOCK();
4092
4093         return rc;
4094 }
4095
4096 static void
4097 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4098 {
4099         uint32_t *count = cbdata;
4100
4101         *count = *count + 1;
4102 }
4103
4104 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4105                                      struct bnxt_vnic_info *vnic __rte_unused)
4106 {
4107         return 0;
4108 }
4109
4110 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4111 {
4112         uint32_t count = 0;
4113
4114         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4115             &count, bnxt_vnic_count_hwrm_stub);
4116
4117         return count;
4118 }
4119
4120 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4121                                         uint16_t *vnic_ids)
4122 {
4123         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4124         struct hwrm_func_vf_vnic_ids_query_output *resp =
4125                                                 bp->hwrm_cmd_resp_addr;
4126         int rc;
4127
4128         /* First query all VNIC ids */
4129         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4130
4131         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
4132         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
4133         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4134
4135         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4136                 HWRM_UNLOCK();
4137                 PMD_DRV_LOG(ERR,
4138                 "unable to map VNIC ID table address to physical memory\n");
4139                 return -ENOMEM;
4140         }
4141         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4142         HWRM_CHECK_RESULT();
4143         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4144
4145         HWRM_UNLOCK();
4146
4147         return rc;
4148 }
4149
4150 /*
4151  * This function queries the VNIC IDs  for a specified VF. It then calls
4152  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4153  * Then it calls the hwrm_cb function to program this new vnic configuration.
4154  */
4155 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4156         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4157         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4158 {
4159         struct bnxt_vnic_info vnic;
4160         int rc = 0;
4161         int i, num_vnic_ids;
4162         uint16_t *vnic_ids;
4163         size_t vnic_id_sz;
4164         size_t sz;
4165
4166         /* First query all VNIC ids */
4167         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4168         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4169                         RTE_CACHE_LINE_SIZE);
4170         if (vnic_ids == NULL)
4171                 return -ENOMEM;
4172
4173         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4174                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4175
4176         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4177
4178         if (num_vnic_ids < 0)
4179                 return num_vnic_ids;
4180
4181         /* Retrieve VNIC, update bd_stall then update */
4182
4183         for (i = 0; i < num_vnic_ids; i++) {
4184                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4185                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4186                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4187                 if (rc)
4188                         break;
4189                 if (vnic.mru <= 4)      /* Indicates unallocated */
4190                         continue;
4191
4192                 vnic_cb(&vnic, cbdata);
4193
4194                 rc = hwrm_cb(bp, &vnic);
4195                 if (rc)
4196                         break;
4197         }
4198
4199         rte_free(vnic_ids);
4200
4201         return rc;
4202 }
4203
4204 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4205                                               bool on)
4206 {
4207         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4208         struct hwrm_func_cfg_input req = {0};
4209         int rc;
4210
4211         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4212
4213         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4214         req.enables |= rte_cpu_to_le_32(
4215                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4216         req.vlan_antispoof_mode = on ?
4217                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4218                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4219         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4220
4221         HWRM_CHECK_RESULT();
4222         HWRM_UNLOCK();
4223
4224         return rc;
4225 }
4226
4227 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4228 {
4229         struct bnxt_vnic_info vnic;
4230         uint16_t *vnic_ids;
4231         size_t vnic_id_sz;
4232         int num_vnic_ids, i;
4233         size_t sz;
4234         int rc;
4235
4236         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4237         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4238                         RTE_CACHE_LINE_SIZE);
4239         if (vnic_ids == NULL)
4240                 return -ENOMEM;
4241
4242         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4243                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4244
4245         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4246         if (rc <= 0)
4247                 goto exit;
4248         num_vnic_ids = rc;
4249
4250         /*
4251          * Loop through to find the default VNIC ID.
4252          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4253          * by sending the hwrm_func_qcfg command to the firmware.
4254          */
4255         for (i = 0; i < num_vnic_ids; i++) {
4256                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4257                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4258                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4259                                         bp->pf.first_vf_id + vf);
4260                 if (rc)
4261                         goto exit;
4262                 if (vnic.func_default) {
4263                         rte_free(vnic_ids);
4264                         return vnic.fw_vnic_id;
4265                 }
4266         }
4267         /* Could not find a default VNIC. */
4268         PMD_DRV_LOG(ERR, "No default VNIC\n");
4269 exit:
4270         rte_free(vnic_ids);
4271         return rc;
4272 }
4273
4274 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4275                          uint16_t dst_id,
4276                          struct bnxt_filter_info *filter)
4277 {
4278         int rc = 0;
4279         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4280         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4281         uint32_t enables = 0;
4282
4283         if (filter->fw_em_filter_id != UINT64_MAX)
4284                 bnxt_hwrm_clear_em_filter(bp, filter);
4285
4286         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4287
4288         req.flags = rte_cpu_to_le_32(filter->flags);
4289
4290         enables = filter->enables |
4291               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4292         req.dst_id = rte_cpu_to_le_16(dst_id);
4293
4294         if (filter->ip_addr_type) {
4295                 req.ip_addr_type = filter->ip_addr_type;
4296                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4297         }
4298         if (enables &
4299             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4300                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4301         if (enables &
4302             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4303                 memcpy(req.src_macaddr, filter->src_macaddr,
4304                        RTE_ETHER_ADDR_LEN);
4305         if (enables &
4306             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4307                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4308                        RTE_ETHER_ADDR_LEN);
4309         if (enables &
4310             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4311                 req.ovlan_vid = filter->l2_ovlan;
4312         if (enables &
4313             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4314                 req.ivlan_vid = filter->l2_ivlan;
4315         if (enables &
4316             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4317                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4318         if (enables &
4319             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4320                 req.ip_protocol = filter->ip_protocol;
4321         if (enables &
4322             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4323                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4324         if (enables &
4325             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4326                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4327         if (enables &
4328             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4329                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4330         if (enables &
4331             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4332                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4333         if (enables &
4334             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4335                 req.mirror_vnic_id = filter->mirror_vnic_id;
4336
4337         req.enables = rte_cpu_to_le_32(enables);
4338
4339         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4340
4341         HWRM_CHECK_RESULT();
4342
4343         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4344         HWRM_UNLOCK();
4345
4346         return rc;
4347 }
4348
4349 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4350 {
4351         int rc = 0;
4352         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4353         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4354
4355         if (filter->fw_em_filter_id == UINT64_MAX)
4356                 return 0;
4357
4358         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4359
4360         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4361
4362         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4363
4364         HWRM_CHECK_RESULT();
4365         HWRM_UNLOCK();
4366
4367         filter->fw_em_filter_id = UINT64_MAX;
4368         filter->fw_l2_filter_id = UINT64_MAX;
4369
4370         return 0;
4371 }
4372
4373 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4374                          uint16_t dst_id,
4375                          struct bnxt_filter_info *filter)
4376 {
4377         int rc = 0;
4378         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4379         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4380                                                 bp->hwrm_cmd_resp_addr;
4381         uint32_t enables = 0;
4382
4383         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4384                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4385
4386         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4387
4388         req.flags = rte_cpu_to_le_32(filter->flags);
4389
4390         enables = filter->enables |
4391               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4392         req.dst_id = rte_cpu_to_le_16(dst_id);
4393
4394         if (filter->ip_addr_type) {
4395                 req.ip_addr_type = filter->ip_addr_type;
4396                 enables |=
4397                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4398         }
4399         if (enables &
4400             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4401                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4402         if (enables &
4403             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4404                 memcpy(req.src_macaddr, filter->src_macaddr,
4405                        RTE_ETHER_ADDR_LEN);
4406         if (enables &
4407             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4408                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4409         if (enables &
4410             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4411                 req.ip_protocol = filter->ip_protocol;
4412         if (enables &
4413             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4414                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4415         if (enables &
4416             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4417                 req.src_ipaddr_mask[0] =
4418                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4419         if (enables &
4420             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4421                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4422         if (enables &
4423             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4424                 req.dst_ipaddr_mask[0] =
4425                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4426         if (enables &
4427             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4428                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4429         if (enables &
4430             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4431                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4432         if (enables &
4433             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4434                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4435         if (enables &
4436             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4437                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4438         if (enables &
4439             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4440                 req.mirror_vnic_id = filter->mirror_vnic_id;
4441
4442         req.enables = rte_cpu_to_le_32(enables);
4443
4444         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4445
4446         HWRM_CHECK_RESULT();
4447
4448         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4449         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4450         HWRM_UNLOCK();
4451
4452         return rc;
4453 }
4454
4455 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4456                                 struct bnxt_filter_info *filter)
4457 {
4458         int rc = 0;
4459         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4460         struct hwrm_cfa_ntuple_filter_free_output *resp =
4461                                                 bp->hwrm_cmd_resp_addr;
4462
4463         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4464                 return 0;
4465
4466         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4467
4468         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4469
4470         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4471
4472         HWRM_CHECK_RESULT();
4473         HWRM_UNLOCK();
4474
4475         filter->fw_ntuple_filter_id = UINT64_MAX;
4476
4477         return 0;
4478 }
4479
4480 static int
4481 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4482 {
4483         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4484         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4485         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4486         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4487         uint16_t *ring_tbl = vnic->rss_table;
4488         int nr_ctxs = vnic->num_lb_ctxts;
4489         int max_rings = bp->rx_nr_rings;
4490         int i, j, k, cnt;
4491         int rc = 0;
4492
4493         for (i = 0, k = 0; i < nr_ctxs; i++) {
4494                 struct bnxt_rx_ring_info *rxr;
4495                 struct bnxt_cp_ring_info *cpr;
4496
4497                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4498
4499                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4500                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4501                 req.hash_mode_flags = vnic->hash_mode;
4502
4503                 req.ring_grp_tbl_addr =
4504                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4505                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4506                                      2 * sizeof(*ring_tbl));
4507                 req.hash_key_tbl_addr =
4508                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4509
4510                 req.ring_table_pair_index = i;
4511                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4512
4513                 for (j = 0; j < 64; j++) {
4514                         uint16_t ring_id;
4515
4516                         /* Find next active ring. */
4517                         for (cnt = 0; cnt < max_rings; cnt++) {
4518                                 if (rx_queue_state[k] !=
4519                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4520                                         break;
4521                                 if (++k == max_rings)
4522                                         k = 0;
4523                         }
4524
4525                         /* Return if no rings are active. */
4526                         if (cnt == max_rings) {
4527                                 HWRM_UNLOCK();
4528                                 return 0;
4529                         }
4530
4531                         /* Add rx/cp ring pair to RSS table. */
4532                         rxr = rxqs[k]->rx_ring;
4533                         cpr = rxqs[k]->cp_ring;
4534
4535                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4536                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4537                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4538                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4539
4540                         if (++k == max_rings)
4541                                 k = 0;
4542                 }
4543                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4544                                             BNXT_USE_CHIMP_MB);
4545
4546                 HWRM_CHECK_RESULT();
4547                 HWRM_UNLOCK();
4548         }
4549
4550         return rc;
4551 }
4552
4553 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4554 {
4555         unsigned int rss_idx, fw_idx, i;
4556
4557         if (!(vnic->rss_table && vnic->hash_type))
4558                 return 0;
4559
4560         if (BNXT_CHIP_THOR(bp))
4561                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4562
4563         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4564                 return 0;
4565
4566         if (vnic->rss_table && vnic->hash_type) {
4567                 /*
4568                  * Fill the RSS hash & redirection table with
4569                  * ring group ids for all VNICs
4570                  */
4571                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4572                         rss_idx++, fw_idx++) {
4573                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4574                                 fw_idx %= bp->rx_cp_nr_rings;
4575                                 if (vnic->fw_grp_ids[fw_idx] !=
4576                                     INVALID_HW_RING_ID)
4577                                         break;
4578                                 fw_idx++;
4579                         }
4580                         if (i == bp->rx_cp_nr_rings)
4581                                 return 0;
4582                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4583                 }
4584                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4585         }
4586
4587         return 0;
4588 }
4589
4590 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4591         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4592 {
4593         uint16_t flags;
4594
4595         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4596
4597         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4598         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4599
4600         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4601         req->num_cmpl_dma_aggr_during_int =
4602                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4603
4604         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4605
4606         /* min timer set to 1/2 of interrupt timer */
4607         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4608
4609         /* buf timer set to 1/4 of interrupt timer */
4610         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4611
4612         req->cmpl_aggr_dma_tmr_during_int =
4613                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4614
4615         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4616                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4617         req->flags = rte_cpu_to_le_16(flags);
4618 }
4619
4620 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4621                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4622 {
4623         struct hwrm_ring_aggint_qcaps_input req = {0};
4624         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4625         uint32_t enables;
4626         uint16_t flags;
4627         int rc;
4628
4629         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4630         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4631         HWRM_CHECK_RESULT();
4632
4633         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4634         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4635
4636         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4637                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4638         agg_req->flags = rte_cpu_to_le_16(flags);
4639         enables =
4640          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4641          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4642         agg_req->enables = rte_cpu_to_le_32(enables);
4643
4644         HWRM_UNLOCK();
4645         return rc;
4646 }
4647
4648 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4649                         struct bnxt_coal *coal, uint16_t ring_id)
4650 {
4651         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4652         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4653                                                 bp->hwrm_cmd_resp_addr;
4654         int rc;
4655
4656         /* Set ring coalesce parameters only for 100G NICs */
4657         if (BNXT_CHIP_THOR(bp)) {
4658                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4659                         return -1;
4660         } else if (bnxt_stratus_device(bp)) {
4661                 bnxt_hwrm_set_coal_params(coal, &req);
4662         } else {
4663                 return 0;
4664         }
4665
4666         HWRM_PREP(&req,
4667                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4668                   BNXT_USE_CHIMP_MB);
4669         req.ring_id = rte_cpu_to_le_16(ring_id);
4670         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4671         HWRM_CHECK_RESULT();
4672         HWRM_UNLOCK();
4673         return 0;
4674 }
4675
4676 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4677 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4678 {
4679         struct hwrm_func_backing_store_qcaps_input req = {0};
4680         struct hwrm_func_backing_store_qcaps_output *resp =
4681                 bp->hwrm_cmd_resp_addr;
4682         struct bnxt_ctx_pg_info *ctx_pg;
4683         struct bnxt_ctx_mem_info *ctx;
4684         int total_alloc_len;
4685         int rc, i;
4686
4687         if (!BNXT_CHIP_THOR(bp) ||
4688             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4689             BNXT_VF(bp) ||
4690             bp->ctx)
4691                 return 0;
4692
4693         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4694         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4695         HWRM_CHECK_RESULT_SILENT();
4696
4697         total_alloc_len = sizeof(*ctx);
4698         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4699                           RTE_CACHE_LINE_SIZE);
4700         if (!ctx) {
4701                 rc = -ENOMEM;
4702                 goto ctx_err;
4703         }
4704
4705         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4706                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4707                             RTE_CACHE_LINE_SIZE);
4708         if (!ctx_pg) {
4709                 rc = -ENOMEM;
4710                 goto ctx_err;
4711         }
4712         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4713                 ctx->tqm_mem[i] = ctx_pg;
4714
4715         bp->ctx = ctx;
4716         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4717         ctx->qp_min_qp1_entries =
4718                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4719         ctx->qp_max_l2_entries =
4720                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4721         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4722         ctx->srq_max_l2_entries =
4723                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4724         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4725         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4726         ctx->cq_max_l2_entries =
4727                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4728         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4729         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4730         ctx->vnic_max_vnic_entries =
4731                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4732         ctx->vnic_max_ring_table_entries =
4733                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4734         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4735         ctx->stat_max_entries =
4736                 rte_le_to_cpu_32(resp->stat_max_entries);
4737         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4738         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4739         ctx->tqm_min_entries_per_ring =
4740                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4741         ctx->tqm_max_entries_per_ring =
4742                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4743         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4744         if (!ctx->tqm_entries_multiple)
4745                 ctx->tqm_entries_multiple = 1;
4746         ctx->mrav_max_entries =
4747                 rte_le_to_cpu_32(resp->mrav_max_entries);
4748         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4749         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4750         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4751 ctx_err:
4752         HWRM_UNLOCK();
4753         return rc;
4754 }
4755
4756 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4757 {
4758         struct hwrm_func_backing_store_cfg_input req = {0};
4759         struct hwrm_func_backing_store_cfg_output *resp =
4760                 bp->hwrm_cmd_resp_addr;
4761         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4762         struct bnxt_ctx_pg_info *ctx_pg;
4763         uint32_t *num_entries;
4764         uint64_t *pg_dir;
4765         uint8_t *pg_attr;
4766         uint32_t ena;
4767         int i, rc;
4768
4769         if (!ctx)
4770                 return 0;
4771
4772         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4773         req.enables = rte_cpu_to_le_32(enables);
4774
4775         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4776                 ctx_pg = &ctx->qp_mem;
4777                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4778                 req.qp_num_qp1_entries =
4779                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4780                 req.qp_num_l2_entries =
4781                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4782                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4783                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4784                                       &req.qpc_pg_size_qpc_lvl,
4785                                       &req.qpc_page_dir);
4786         }
4787
4788         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4789                 ctx_pg = &ctx->srq_mem;
4790                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4791                 req.srq_num_l2_entries =
4792                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4793                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4794                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4795                                       &req.srq_pg_size_srq_lvl,
4796                                       &req.srq_page_dir);
4797         }
4798
4799         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4800                 ctx_pg = &ctx->cq_mem;
4801                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4802                 req.cq_num_l2_entries =
4803                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4804                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4805                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4806                                       &req.cq_pg_size_cq_lvl,
4807                                       &req.cq_page_dir);
4808         }
4809
4810         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4811                 ctx_pg = &ctx->vnic_mem;
4812                 req.vnic_num_vnic_entries =
4813                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4814                 req.vnic_num_ring_table_entries =
4815                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4816                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4817                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4818                                       &req.vnic_pg_size_vnic_lvl,
4819                                       &req.vnic_page_dir);
4820         }
4821
4822         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4823                 ctx_pg = &ctx->stat_mem;
4824                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4825                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4826                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4827                                       &req.stat_pg_size_stat_lvl,
4828                                       &req.stat_page_dir);
4829         }
4830
4831         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4832         num_entries = &req.tqm_sp_num_entries;
4833         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4834         pg_dir = &req.tqm_sp_page_dir;
4835         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4836         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4837                 if (!(enables & ena))
4838                         continue;
4839
4840                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4841
4842                 ctx_pg = ctx->tqm_mem[i];
4843                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4844                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4845         }
4846
4847         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4848         HWRM_CHECK_RESULT();
4849         HWRM_UNLOCK();
4850
4851         return rc;
4852 }
4853
4854 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4855 {
4856         struct hwrm_port_qstats_ext_input req = {0};
4857         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4858         struct bnxt_pf_info *pf = &bp->pf;
4859         int rc;
4860
4861         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4862               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4863                 return 0;
4864
4865         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4866
4867         req.port_id = rte_cpu_to_le_16(pf->port_id);
4868         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4869                 req.tx_stat_host_addr =
4870                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4871                 req.tx_stat_size =
4872                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4873         }
4874         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4875                 req.rx_stat_host_addr =
4876                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4877                 req.rx_stat_size =
4878                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4879         }
4880         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4881
4882         if (rc) {
4883                 bp->fw_rx_port_stats_ext_size = 0;
4884                 bp->fw_tx_port_stats_ext_size = 0;
4885         } else {
4886                 bp->fw_rx_port_stats_ext_size =
4887                         rte_le_to_cpu_16(resp->rx_stat_size);
4888                 bp->fw_tx_port_stats_ext_size =
4889                         rte_le_to_cpu_16(resp->tx_stat_size);
4890         }
4891
4892         HWRM_CHECK_RESULT();
4893         HWRM_UNLOCK();
4894
4895         return rc;
4896 }
4897
4898 int
4899 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4900 {
4901         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4902         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4903                 bp->hwrm_cmd_resp_addr;
4904         int rc = 0;
4905
4906         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4907         req.tunnel_type = type;
4908         req.dest_fid = bp->fw_fid;
4909         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4910         HWRM_CHECK_RESULT();
4911
4912         HWRM_UNLOCK();
4913
4914         return rc;
4915 }
4916
4917 int
4918 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4919 {
4920         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4921         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4922                 bp->hwrm_cmd_resp_addr;
4923         int rc = 0;
4924
4925         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4926         req.tunnel_type = type;
4927         req.dest_fid = bp->fw_fid;
4928         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4929         HWRM_CHECK_RESULT();
4930
4931         HWRM_UNLOCK();
4932
4933         return rc;
4934 }
4935
4936 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4937 {
4938         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4939         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4940                 bp->hwrm_cmd_resp_addr;
4941         int rc = 0;
4942
4943         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4944         req.src_fid = bp->fw_fid;
4945         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4946         HWRM_CHECK_RESULT();
4947
4948         if (type)
4949                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4950
4951         HWRM_UNLOCK();
4952
4953         return rc;
4954 }
4955
4956 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4957                                    uint16_t *dst_fid)
4958 {
4959         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4960         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4961                 bp->hwrm_cmd_resp_addr;
4962         int rc = 0;
4963
4964         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4965         req.src_fid = bp->fw_fid;
4966         req.tunnel_type = tun_type;
4967         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4968         HWRM_CHECK_RESULT();
4969
4970         if (dst_fid)
4971                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4972
4973         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4974
4975         HWRM_UNLOCK();
4976
4977         return rc;
4978 }
4979
4980 int bnxt_hwrm_set_mac(struct bnxt *bp)
4981 {
4982         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4983         struct hwrm_func_vf_cfg_input req = {0};
4984         int rc = 0;
4985
4986         if (!BNXT_VF(bp))
4987                 return 0;
4988
4989         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4990
4991         req.enables =
4992                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4993         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4994
4995         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4996
4997         HWRM_CHECK_RESULT();
4998
4999         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5000         HWRM_UNLOCK();
5001
5002         return rc;
5003 }
5004
5005 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5006 {
5007         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5008         struct hwrm_func_drv_if_change_input req = {0};
5009         uint32_t flags;
5010         int rc;
5011
5012         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5013                 return 0;
5014
5015         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5016          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5017          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5018          */
5019         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5020                 return 0;
5021
5022         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5023
5024         if (up)
5025                 req.flags =
5026                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5027
5028         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5029
5030         HWRM_CHECK_RESULT();
5031         flags = rte_le_to_cpu_32(resp->flags);
5032         HWRM_UNLOCK();
5033
5034         if (!up)
5035                 return 0;
5036
5037         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5038                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5039                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5040         }
5041
5042         return 0;
5043 }
5044
5045 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5046 {
5047         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5048         struct bnxt_error_recovery_info *info = bp->recovery_info;
5049         struct hwrm_error_recovery_qcfg_input req = {0};
5050         uint32_t flags = 0;
5051         unsigned int i;
5052         int rc;
5053
5054         /* Older FW does not have error recovery support */
5055         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5056                 return 0;
5057
5058         if (!info) {
5059                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5060                                    sizeof(*info), 0);
5061                 bp->recovery_info = info;
5062                 if (info == NULL)
5063                         return -ENOMEM;
5064         } else {
5065                 memset(info, 0, sizeof(*info));
5066         }
5067
5068         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5069
5070         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5071
5072         HWRM_CHECK_RESULT();
5073
5074         flags = rte_le_to_cpu_32(resp->flags);
5075         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5076                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5077         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5078                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5079
5080         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5081             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5082                 rc = -EINVAL;
5083                 goto err;
5084         }
5085
5086         /* FW returned values are in units of 100msec */
5087         info->driver_polling_freq =
5088                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5089         info->master_func_wait_period =
5090                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5091         info->normal_func_wait_period =
5092                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5093         info->master_func_wait_period_after_reset =
5094                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5095         info->max_bailout_time_after_reset =
5096                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5097         info->status_regs[BNXT_FW_STATUS_REG] =
5098                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5099         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5100                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5101         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5102                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5103         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5104                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5105         info->reg_array_cnt =
5106                 rte_le_to_cpu_32(resp->reg_array_cnt);
5107
5108         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5109                 rc = -EINVAL;
5110                 goto err;
5111         }
5112
5113         for (i = 0; i < info->reg_array_cnt; i++) {
5114                 info->reset_reg[i] =
5115                         rte_le_to_cpu_32(resp->reset_reg[i]);
5116                 info->reset_reg_val[i] =
5117                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5118                 info->delay_after_reset[i] =
5119                         resp->delay_after_reset[i];
5120         }
5121 err:
5122         HWRM_UNLOCK();
5123
5124         /* Map the FW status registers */
5125         if (!rc)
5126                 rc = bnxt_map_fw_health_status_regs(bp);
5127
5128         if (rc) {
5129                 rte_free(bp->recovery_info);
5130                 bp->recovery_info = NULL;
5131         }
5132         return rc;
5133 }
5134
5135 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5136 {
5137         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5138         struct hwrm_fw_reset_input req = {0};
5139         int rc;
5140
5141         if (!BNXT_PF(bp))
5142                 return -EOPNOTSUPP;
5143
5144         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5145
5146         req.embedded_proc_type =
5147                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5148         req.selfrst_status =
5149                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5150         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5151
5152         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5153                                     BNXT_USE_KONG(bp));
5154
5155         HWRM_CHECK_RESULT();
5156         HWRM_UNLOCK();
5157
5158         return rc;
5159 }
5160
5161 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5162 {
5163         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5164         struct hwrm_port_ts_query_input req = {0};
5165         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5166         uint32_t flags = 0;
5167         int rc;
5168
5169         if (!ptp)
5170                 return 0;
5171
5172         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5173
5174         switch (path) {
5175         case BNXT_PTP_FLAGS_PATH_TX:
5176                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5177                 break;
5178         case BNXT_PTP_FLAGS_PATH_RX:
5179                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5180                 break;
5181         case BNXT_PTP_FLAGS_CURRENT_TIME:
5182                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5183                 break;
5184         }
5185
5186         req.flags = rte_cpu_to_le_32(flags);
5187         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5188
5189         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5190
5191         HWRM_CHECK_RESULT();
5192
5193         if (timestamp) {
5194                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5195                 *timestamp |=
5196                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5197         }
5198         HWRM_UNLOCK();
5199
5200         return rc;
5201 }
5202
5203 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5204 {
5205         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5206                                         bp->hwrm_cmd_resp_addr;
5207         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5208         uint32_t flags = 0;
5209         int rc = 0;
5210
5211         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5212                 return rc;
5213
5214         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5215                 PMD_DRV_LOG(DEBUG,
5216                             "Not a PF or trusted VF. Command not supported\n");
5217                 return 0;
5218         }
5219
5220         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5221         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5222
5223         HWRM_CHECK_RESULT();
5224         flags = rte_le_to_cpu_32(resp->flags);
5225         HWRM_UNLOCK();
5226
5227         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5228                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5229                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5230         }
5231
5232         return rc;
5233 }