drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SPEC_CODE_1_8_3            0x10803
  31 #define HWRM_VERSION_1_9_1              0x10901
  32 #define HWRM_VERSION_1_9_2              0x10903
  33
  34 struct bnxt_plcmodes_cfg {
  35         uint32_t        flags;
  36         uint16_t        jumbo_thresh;
  37         uint16_t        hds_offset;
  38         uint16_t        hds_threshold;
  39 };
  40
  41 static int page_getenum(size_t size)
  42 {
  43         if (size <= 1 << 4)
  44                 return 4;
  45         if (size <= 1 << 12)
  46                 return 12;
  47         if (size <= 1 << 13)
  48                 return 13;
  49         if (size <= 1 << 16)
  50                 return 16;
  51         if (size <= 1 << 21)
  52                 return 21;
  53         if (size <= 1 << 22)
  54                 return 22;
  55         if (size <= 1 << 30)
  56                 return 30;
  57         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  58         return sizeof(void *) * 8 - 1;
  59 }
  60
  61 static int page_roundup(size_t size)
  62 {
  63         return 1 << page_getenum(size);
  64 }
  65
  66 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  67                                   uint8_t *pg_attr,
  68                                   uint64_t *pg_dir)
  69 {
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 /*
  79  * HWRM Functions (sent to HWRM)
  80  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  81  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  82  * command was failed by the ChiMP.
  83  */
  84
  85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  86                                   uint32_t msg_len, bool use_kong_mb)
  87 {
  88         unsigned int i;
  89         struct input *req = msg;
  90         struct output *resp = bp->hwrm_cmd_resp_addr;
  91         uint32_t *data = msg;
  92         uint8_t *bar;
  93         uint8_t *valid;
  94         uint16_t max_req_len = bp->max_req_len;
  95         struct hwrm_short_input short_input = { 0 };
  96         uint16_t bar_offset = use_kong_mb ?
  97                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  98         uint16_t mb_trigger_offset = use_kong_mb ?
  99                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 100
 101         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 102             msg_len > bp->max_req_len) {
 103                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 104
 105                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 106                 memcpy(short_cmd_req, req, msg_len);
 107
 108                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 109                 short_input.signature = rte_cpu_to_le_16(
 110                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 111                 short_input.size = rte_cpu_to_le_16(msg_len);
 112                 short_input.req_addr =
 113                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 114
 115                 data = (uint32_t *)&short_input;
 116                 msg_len = sizeof(short_input);
 117
 118                 /* Sync memory write before updating doorbell */
 119                 rte_wmb();
 120
 121                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 122         }
 123
 124         /* Write request msg to hwrm channel */
 125         for (i = 0; i < msg_len; i += 4) {
 126                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 127                 rte_write32(*data, bar);
 128                 data++;
 129         }
 130
 131         /* Zero the rest of the request space */
 132         for (; i < max_req_len; i += 4) {
 133                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 134                 rte_write32(0, bar);
 135         }
 136
 137         /* Ring channel doorbell */
 138         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 139         rte_write32(1, bar);
 140
 141         /* Poll for the valid bit */
 142         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 143                 /* Sanity check on the resp->resp_len */
 144                 rte_rmb();
 145                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 146                         /* Last byte of resp contains the valid key */
 147                         valid = (uint8_t *)resp + resp->resp_len - 1;
 148                         if (*valid == HWRM_RESP_VALID_KEY)
 149                                 break;
 150                 }
 151                 rte_delay_us(1);
 152         }
 153
 154         if (i >= HWRM_CMD_TIMEOUT) {
 155                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 156                             req->req_type);
 157                 return -ETIMEDOUT;
 158         }
 159         return 0;
 160 }
 161
 162 /*
 163  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 164  * spinlock, and does initial processing.
 165  *
 166  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 167  * releases the spinlock only if it returns.  If the regular int return codes
 168  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 169  * directly, rather it should be copied and modified to suit the function.
 170  *
 171  * HWRM_UNLOCK() must be called after all response processing is completed.
 172  */
 173 #define HWRM_PREP(req, type, kong) do { \
 174         rte_spinlock_lock(&bp->hwrm_lock); \
 175         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 176         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 177         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 178         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 179                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 180         req.target_id = rte_cpu_to_le_16(0xffff); \
 181         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 182 } while (0)
 183
 184 #define HWRM_CHECK_RESULT_SILENT() do {\
 185         if (rc) { \
 186                 rte_spinlock_unlock(&bp->hwrm_lock); \
 187                 return rc; \
 188         } \
 189         if (resp->error_code) { \
 190                 rc = rte_le_to_cpu_16(resp->error_code); \
 191                 rte_spinlock_unlock(&bp->hwrm_lock); \
 192                 return rc; \
 193         } \
 194 } while (0)
 195
 196 #define HWRM_CHECK_RESULT() do {\
 197         if (rc) { \
 198                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 199                 rte_spinlock_unlock(&bp->hwrm_lock); \
 200                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 201                         rc = -EACCES; \
 202                 else if (rc > 0) \
 203                         rc = -EINVAL; \
 204                 return rc; \
 205         } \
 206         if (resp->error_code) { \
 207                 rc = rte_le_to_cpu_16(resp->error_code); \
 208                 if (resp->resp_len >= 16) { \
 209                         struct hwrm_err_output *tmp_hwrm_err_op = \
 210                                                 (void *)resp; \
 211                         PMD_DRV_LOG(ERR, \
 212                                 "error %d:%d:%08x:%04x\n", \
 213                                 rc, tmp_hwrm_err_op->cmd_err, \
 214                                 rte_le_to_cpu_32(\
 215                                         tmp_hwrm_err_op->opaque_0), \
 216                                 rte_le_to_cpu_16(\
 217                                         tmp_hwrm_err_op->opaque_1)); \
 218                 } else { \
 219                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 220                 } \
 221                 rte_spinlock_unlock(&bp->hwrm_lock); \
 222                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 223                         rc = -EACCES; \
 224                 else if (rc > 0) \
 225                         rc = -EINVAL; \
 226                 return rc; \
 227         } \
 228 } while (0)
 229
 230 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 231
 232 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 233 {
 234         int rc = 0;
 235         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 236         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 237
 238         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 239         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 240         req.mask = 0;
 241
 242         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 243
 244         HWRM_CHECK_RESULT();
 245         HWRM_UNLOCK();
 246
 247         return rc;
 248 }
 249
 250 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 251                                  struct bnxt_vnic_info *vnic,
 252                                  uint16_t vlan_count,
 253                                  struct bnxt_vlan_table_entry *vlan_table)
 254 {
 255         int rc = 0;
 256         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 257         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 258         uint32_t mask = 0;
 259
 260         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 261                 return rc;
 262
 263         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 264         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 265
 266         /* FIXME add multicast flag, when multicast adding options is supported
 267          * by ethtool.
 268          */
 269         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 270                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 271         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 272                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 273         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 274                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 275         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 276                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 277         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 278                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 279         if (vnic->mc_addr_cnt) {
 280                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 281                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 282                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 283         }
 284         if (vlan_table) {
 285                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 286                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 287                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 288                          rte_mem_virt2iova(vlan_table));
 289                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 290         }
 291         req.mask = rte_cpu_to_le_32(mask);
 292
 293         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 294
 295         HWRM_CHECK_RESULT();
 296         HWRM_UNLOCK();
 297
 298         return rc;
 299 }
 300
 301 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 302                         uint16_t vlan_count,
 303                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 304 {
 305         int rc = 0;
 306         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 307         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 308                                                 bp->hwrm_cmd_resp_addr;
 309
 310         /*
 311          * Older HWRM versions did not support this command, and the set_rx_mask
 312          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 313          * removed from set_rx_mask call, and this command was added.
 314          *
 315          * This command is also present from 1.7.8.11 and higher,
 316          * as well as 1.7.8.0
 317          */
 318         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 319                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 320                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 321                                         (11)))
 322                                 return 0;
 323                 }
 324         }
 325         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 326         req.fid = rte_cpu_to_le_16(fid);
 327
 328         req.vlan_tag_mask_tbl_addr =
 329                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 330         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 331
 332         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 333
 334         HWRM_CHECK_RESULT();
 335         HWRM_UNLOCK();
 336
 337         return rc;
 338 }
 339
 340 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 341                            struct bnxt_filter_info *filter)
 342 {
 343         int rc = 0;
 344         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 345         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 346
 347         if (filter->fw_l2_filter_id == UINT64_MAX)
 348                 return 0;
 349
 350         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 351
 352         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 353
 354         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 355
 356         HWRM_CHECK_RESULT();
 357         HWRM_UNLOCK();
 358
 359         filter->fw_l2_filter_id = UINT64_MAX;
 360
 361         return 0;
 362 }
 363
 364 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 365                          uint16_t dst_id,
 366                          struct bnxt_filter_info *filter)
 367 {
 368         int rc = 0;
 369         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 370         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 371         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 372         const struct rte_eth_vmdq_rx_conf *conf =
 373                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 374         uint32_t enables = 0;
 375         uint16_t j = dst_id - 1;
 376
 377         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 378         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 379             conf->pool_map[j].pools & (1UL << j)) {
 380                 PMD_DRV_LOG(DEBUG,
 381                         "Add vlan %u to vmdq pool %u\n",
 382                         conf->pool_map[j].vlan_id, j);
 383
 384                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 385                 filter->enables |=
 386                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 387                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 388         }
 389
 390         if (filter->fw_l2_filter_id != UINT64_MAX)
 391                 bnxt_hwrm_clear_l2_filter(bp, filter);
 392
 393         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 394
 395         req.flags = rte_cpu_to_le_32(filter->flags);
 396         req.flags |=
 397         rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
 398
 399         enables = filter->enables |
 400               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 401         req.dst_id = rte_cpu_to_le_16(dst_id);
 402
 403         if (enables &
 404             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 405                 memcpy(req.l2_addr, filter->l2_addr,
 406                        RTE_ETHER_ADDR_LEN);
 407         if (enables &
 408             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 409                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 410                        RTE_ETHER_ADDR_LEN);
 411         if (enables &
 412             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 413                 req.l2_ovlan = filter->l2_ovlan;
 414         if (enables &
 415             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 416                 req.l2_ivlan = filter->l2_ivlan;
 417         if (enables &
 418             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 419                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 420         if (enables &
 421             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 422                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 423         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 424                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 425         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 426                 req.src_type = filter->src_type;
 427
 428         req.enables = rte_cpu_to_le_32(enables);
 429
 430         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 431
 432         HWRM_CHECK_RESULT();
 433
 434         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 435         HWRM_UNLOCK();
 436
 437         return rc;
 438 }
 439
 440 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 441 {
 442         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 443         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 444         uint32_t flags = 0;
 445         int rc;
 446
 447         if (!ptp)
 448                 return 0;
 449
 450         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 451
 452         if (ptp->rx_filter)
 453                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 454         else
 455                 flags |=
 456                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 457         if (ptp->tx_tstamp_en)
 458                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 459         else
 460                 flags |=
 461                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 462         req.flags = rte_cpu_to_le_32(flags);
 463         req.enables = rte_cpu_to_le_32
 464                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 465         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 466
 467         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 468         HWRM_UNLOCK();
 469
 470         return rc;
 471 }
 472
 473 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 474 {
 475         int rc = 0;
 476         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 477         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 478         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 479
 480 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 481         if (ptp)
 482                 return 0;
 483
 484         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 485
 486         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 487
 488         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 489
 490         HWRM_CHECK_RESULT();
 491
 492         if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 493                 return 0;
 494
 495         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 496         if (!ptp)
 497                 return -ENOMEM;
 498
 499         ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 500                 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 501         ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 502                 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 503         ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 504                 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 505         ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 506                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 507         ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 508                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 509         ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 510                 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 511         ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 512                 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 513         ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 514                 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 515         ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 516                 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 517
 518         ptp->bp = bp;
 519         bp->ptp_cfg = ptp;
 520
 521         return 0;
 522 }
 523
 524 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 525 {
 526         int rc = 0;
 527         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 528         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 529         uint16_t new_max_vfs;
 530         uint32_t flags;
 531         int i;
 532
 533         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 534
 535         req.fid = rte_cpu_to_le_16(0xffff);
 536
 537         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 538
 539         HWRM_CHECK_RESULT();
 540
 541         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 542         flags = rte_le_to_cpu_32(resp->flags);
 543         if (BNXT_PF(bp)) {
 544                 bp->pf.port_id = resp->port_id;
 545                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 546                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 547                 new_max_vfs = bp->pdev->max_vfs;
 548                 if (new_max_vfs != bp->pf.max_vfs) {
 549                         if (bp->pf.vf_info)
 550                                 rte_free(bp->pf.vf_info);
 551                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 552                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 553                         bp->pf.max_vfs = new_max_vfs;
 554                         for (i = 0; i < new_max_vfs; i++) {
 555                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 556                                 bp->pf.vf_info[i].vlan_table =
 557                                         rte_zmalloc("VF VLAN table",
 558                                                     getpagesize(),
 559                                                     getpagesize());
 560                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 561                                         PMD_DRV_LOG(ERR,
 562                                         "Fail to alloc VLAN table for VF %d\n",
 563                                         i);
 564                                 else
 565                                         rte_mem_lock_page(
 566                                                 bp->pf.vf_info[i].vlan_table);
 567                                 bp->pf.vf_info[i].vlan_as_table =
 568                                         rte_zmalloc("VF VLAN AS table",
 569                                                     getpagesize(),
 570                                                     getpagesize());
 571                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 572                                         PMD_DRV_LOG(ERR,
 573                                         "Alloc VLAN AS table for VF %d fail\n",
 574                                         i);
 575                                 else
 576                                         rte_mem_lock_page(
 577                                                bp->pf.vf_info[i].vlan_as_table);
 578                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 579                         }
 580                 }
 581         }
 582
 583         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 584         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 585         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 586         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 587         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 588         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 589         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 590         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 591         bp->max_l2_ctx =
 592                 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
 593         /* TODO: For now, do not support VMDq/RFS on VFs. */
 594         if (BNXT_PF(bp)) {
 595                 if (bp->pf.max_vfs)
 596                         bp->max_vnics = 1;
 597                 else
 598                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 599         } else {
 600                 bp->max_vnics = 1;
 601         }
 602         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 603         if (BNXT_PF(bp)) {
 604                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 605                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 606                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 607                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 608                         HWRM_UNLOCK();
 609                         bnxt_hwrm_ptp_qcfg(bp);
 610                 }
 611         }
 612
 613         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 614                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 615
 616         HWRM_UNLOCK();
 617
 618         return rc;
 619 }
 620
 621 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 622 {
 623         int rc;
 624
 625         rc = __bnxt_hwrm_func_qcaps(bp);
 626         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 627                 rc = bnxt_alloc_ctx_mem(bp);
 628                 if (rc)
 629                         return rc;
 630
 631                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 632                 if (!rc)
 633                         bp->flags |= BNXT_FLAG_NEW_RM;
 634         }
 635
 636         return rc;
 637 }
 638
 639 int bnxt_hwrm_func_reset(struct bnxt *bp)
 640 {
 641         int rc = 0;
 642         struct hwrm_func_reset_input req = {.req_type = 0 };
 643         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 644
 645         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 646
 647         req.enables = rte_cpu_to_le_32(0);
 648
 649         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 650
 651         HWRM_CHECK_RESULT();
 652         HWRM_UNLOCK();
 653
 654         return rc;
 655 }
 656
 657 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 658 {
 659         int rc;
 660         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 661         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 662
 663         if (bp->flags & BNXT_FLAG_REGISTERED)
 664                 return 0;
 665
 666         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 667         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 668                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 669         req.ver_maj = RTE_VER_YEAR;
 670         req.ver_min = RTE_VER_MONTH;
 671         req.ver_upd = RTE_VER_MINOR;
 672
 673         if (BNXT_PF(bp)) {
 674                 req.enables |= rte_cpu_to_le_32(
 675                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 676                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 677                        RTE_MIN(sizeof(req.vf_req_fwd),
 678                                sizeof(bp->pf.vf_req_fwd)));
 679
 680                 /*
 681                  * PF can sniff HWRM API issued by VF. This can be set up by
 682                  * linux driver and inherited by the DPDK PF driver. Clear
 683                  * this HWRM sniffer list in FW because DPDK PF driver does
 684                  * not support this.
 685                  */
 686                 req.flags =
 687                 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
 688         }
 689
 690         req.async_event_fwd[0] |=
 691                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 692                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 693                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
 694         req.async_event_fwd[1] |=
 695                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 696                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 697
 698         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 699
 700         HWRM_CHECK_RESULT();
 701         HWRM_UNLOCK();
 702
 703         bp->flags |= BNXT_FLAG_REGISTERED;
 704
 705         return rc;
 706 }
 707
 708 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 709 {
 710         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 711                 return 0;
 712
 713         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 714 }
 715
 716 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 717 {
 718         int rc;
 719         uint32_t flags = 0;
 720         uint32_t enables;
 721         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 722         struct hwrm_func_vf_cfg_input req = {0};
 723
 724         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 725
 726         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 727                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 728                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 729                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 730                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 731
 732         if (BNXT_HAS_RING_GRPS(bp)) {
 733                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 734                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 735         }
 736
 737         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 738         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 739                                             AGG_RING_MULTIPLIER);
 740         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
 741                                              bp->tx_nr_rings +
 742                                              BNXT_NUM_ASYNC_CPR(bp));
 743         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 744                                               bp->tx_nr_rings +
 745                                               BNXT_NUM_ASYNC_CPR(bp));
 746         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 747         if (bp->vf_resv_strategy ==
 748             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 749                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 750                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 751                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 752                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 753                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 754                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 755         }
 756
 757         if (test)
 758                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 759                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 760                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 761                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 762                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 763                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 764
 765         if (test && BNXT_HAS_RING_GRPS(bp))
 766                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 767
 768         req.flags = rte_cpu_to_le_32(flags);
 769         req.enables |= rte_cpu_to_le_32(enables);
 770
 771         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 772
 773         if (test)
 774                 HWRM_CHECK_RESULT_SILENT();
 775         else
 776                 HWRM_CHECK_RESULT();
 777
 778         HWRM_UNLOCK();
 779         return rc;
 780 }
 781
 782 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 783 {
 784         int rc;
 785         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 786         struct hwrm_func_resource_qcaps_input req = {0};
 787
 788         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 789         req.fid = rte_cpu_to_le_16(0xffff);
 790
 791         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 792
 793         HWRM_CHECK_RESULT();
 794
 795         if (BNXT_VF(bp)) {
 796                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 797                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 798                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 799                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 800                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 801                 /* func_resource_qcaps does not return max_rx_em_flows.
 802                  * So use the value provided by func_qcaps.
 803                  */
 804                 bp->max_l2_ctx =
 805                         rte_le_to_cpu_16(resp->max_l2_ctxs) +
 806                         bp->max_rx_em_flows;
 807                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 808                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 809         }
 810         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 811         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 812         if (bp->vf_resv_strategy >
 813             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 814                 bp->vf_resv_strategy =
 815                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 816
 817         HWRM_UNLOCK();
 818         return rc;
 819 }
 820
 821 int bnxt_hwrm_ver_get(struct bnxt *bp)
 822 {
 823         int rc = 0;
 824         struct hwrm_ver_get_input req = {.req_type = 0 };
 825         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 826         uint32_t fw_version;
 827         uint16_t max_resp_len;
 828         char type[RTE_MEMZONE_NAMESIZE];
 829         uint32_t dev_caps_cfg;
 830
 831         bp->max_req_len = HWRM_MAX_REQ_LEN;
 832         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 833
 834         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 835         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 836         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 837
 838         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 839
 840         HWRM_CHECK_RESULT();
 841
 842         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 843                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 844                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 845                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 846         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 847                      (resp->hwrm_fw_min_8b << 16) |
 848                      (resp->hwrm_fw_bld_8b << 8) |
 849                      resp->hwrm_fw_rsvd_8b;
 850         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 851                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 852
 853         fw_version = resp->hwrm_intf_maj_8b << 16;
 854         fw_version |= resp->hwrm_intf_min_8b << 8;
 855         fw_version |= resp->hwrm_intf_upd_8b;
 856         bp->hwrm_spec_code = fw_version;
 857
 858         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 859                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 860                 rc = -EINVAL;
 861                 goto error;
 862         }
 863
 864         if (bp->max_req_len > resp->max_req_win_len) {
 865                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 866                 rc = -EINVAL;
 867         }
 868         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 869         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 870         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 871                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 872
 873         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 874         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 875
 876         if (bp->max_resp_len != max_resp_len) {
 877                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 878                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 879                         bp->pdev->addr.devid, bp->pdev->addr.function);
 880
 881                 rte_free(bp->hwrm_cmd_resp_addr);
 882
 883                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 884                 if (bp->hwrm_cmd_resp_addr == NULL) {
 885                         rc = -ENOMEM;
 886                         goto error;
 887                 }
 888                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 889                 bp->hwrm_cmd_resp_dma_addr =
 890                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 891                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
 892                         PMD_DRV_LOG(ERR,
 893                         "Unable to map response buffer to physical memory.\n");
 894                         rc = -ENOMEM;
 895                         goto error;
 896                 }
 897                 bp->max_resp_len = max_resp_len;
 898         }
 899
 900         if ((dev_caps_cfg &
 901                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 902             (dev_caps_cfg &
 903              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 904                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 905                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 906         }
 907
 908         if (((dev_caps_cfg &
 909               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 910              (dev_caps_cfg &
 911               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
 912             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
 913                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
 914                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 915                         bp->pdev->addr.devid, bp->pdev->addr.function);
 916
 917                 rte_free(bp->hwrm_short_cmd_req_addr);
 918
 919                 bp->hwrm_short_cmd_req_addr =
 920                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
 921                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 922                         rc = -ENOMEM;
 923                         goto error;
 924                 }
 925                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 926                 bp->hwrm_short_cmd_req_dma_addr =
 927                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 928                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
 929                         rte_free(bp->hwrm_short_cmd_req_addr);
 930                         PMD_DRV_LOG(ERR,
 931                                 "Unable to map buffer to physical memory.\n");
 932                         rc = -ENOMEM;
 933                         goto error;
 934                 }
 935         }
 936         if (dev_caps_cfg &
 937             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
 938                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
 939                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
 940         }
 941         if (dev_caps_cfg &
 942             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
 943                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
 944
 945 error:
 946         HWRM_UNLOCK();
 947         return rc;
 948 }
 949
 950 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 951 {
 952         int rc;
 953         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 954         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 955
 956         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 957                 return 0;
 958
 959         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
 960         req.flags = flags;
 961
 962         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 963
 964         HWRM_CHECK_RESULT();
 965         HWRM_UNLOCK();
 966
 967         return rc;
 968 }
 969
 970 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 971 {
 972         int rc = 0;
 973         struct hwrm_port_phy_cfg_input req = {0};
 974         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 975         uint32_t enables = 0;
 976
 977         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
 978
 979         if (conf->link_up) {
 980                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
 981                 if (bp->link_info.auto_mode && conf->link_speed) {
 982                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
 983                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
 984                 }
 985
 986                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 987                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 988                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 989                 /*
 990                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 991                  * any auto mode, even "none".
 992                  */
 993                 if (!conf->link_speed) {
 994                         /* No speeds specified. Enable AutoNeg - all speeds */
 995                         req.auto_mode =
 996                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
 997                 }
 998                 /* AutoNeg - Advertise speeds specified. */
 999                 if (conf->auto_link_speed_mask &&
1000                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1001                         req.auto_mode =
1002                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1003                         req.auto_link_speed_mask =
1004                                 conf->auto_link_speed_mask;
1005                         enables |=
1006                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1007                 }
1008
1009                 req.auto_duplex = conf->duplex;
1010                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1011                 req.auto_pause = conf->auto_pause;
1012                 req.force_pause = conf->force_pause;
1013                 /* Set force_pause if there is no auto or if there is a force */
1014                 if (req.auto_pause && !req.force_pause)
1015                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1016                 else
1017                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1018
1019                 req.enables = rte_cpu_to_le_32(enables);
1020         } else {
1021                 req.flags =
1022                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1023                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1024         }
1025
1026         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1027
1028         HWRM_CHECK_RESULT();
1029         HWRM_UNLOCK();
1030
1031         return rc;
1032 }
1033
1034 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1035                                    struct bnxt_link_info *link_info)
1036 {
1037         int rc = 0;
1038         struct hwrm_port_phy_qcfg_input req = {0};
1039         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1040
1041         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1042
1043         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1044
1045         HWRM_CHECK_RESULT();
1046
1047         link_info->phy_link_status = resp->link;
1048         link_info->link_up =
1049                 (link_info->phy_link_status ==
1050                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1051         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1052         link_info->duplex = resp->duplex_cfg;
1053         link_info->pause = resp->pause;
1054         link_info->auto_pause = resp->auto_pause;
1055         link_info->force_pause = resp->force_pause;
1056         link_info->auto_mode = resp->auto_mode;
1057         link_info->phy_type = resp->phy_type;
1058         link_info->media_type = resp->media_type;
1059
1060         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1061         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1062         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1063         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1064         link_info->phy_ver[0] = resp->phy_maj;
1065         link_info->phy_ver[1] = resp->phy_min;
1066         link_info->phy_ver[2] = resp->phy_bld;
1067
1068         HWRM_UNLOCK();
1069
1070         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1071         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1072         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1073         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1074         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1075                     link_info->auto_link_speed_mask);
1076         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1077                     link_info->force_link_speed);
1078
1079         return rc;
1080 }
1081
1082 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1083 {
1084         int rc = 0;
1085         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1086         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1087         int i;
1088
1089         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1090
1091         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1092         /* HWRM Version >= 1.9.1 */
1093         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1094                 req.drv_qmap_cap =
1095                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1096         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1097
1098         HWRM_CHECK_RESULT();
1099
1100 #define GET_QUEUE_INFO(x) \
1101         bp->cos_queue[x].id = resp->queue_id##x; \
1102         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1103
1104         GET_QUEUE_INFO(0);
1105         GET_QUEUE_INFO(1);
1106         GET_QUEUE_INFO(2);
1107         GET_QUEUE_INFO(3);
1108         GET_QUEUE_INFO(4);
1109         GET_QUEUE_INFO(5);
1110         GET_QUEUE_INFO(6);
1111         GET_QUEUE_INFO(7);
1112
1113         HWRM_UNLOCK();
1114
1115         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1116                 bp->tx_cosq_id = bp->cos_queue[0].id;
1117         } else {
1118                 /* iterate and find the COSq profile to use for Tx */
1119                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1120                         if (bp->cos_queue[i].profile ==
1121                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1122                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1123                                 break;
1124                         }
1125                 }
1126         }
1127
1128         bp->max_tc = resp->max_configurable_queues;
1129         bp->max_lltc = resp->max_configurable_lossless_queues;
1130         if (bp->max_tc > BNXT_MAX_QUEUE)
1131                 bp->max_tc = BNXT_MAX_QUEUE;
1132         bp->max_q = bp->max_tc;
1133
1134         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1135
1136         return rc;
1137 }
1138
1139 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1140                          struct bnxt_ring *ring,
1141                          uint32_t ring_type, uint32_t map_index,
1142                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1143 {
1144         int rc = 0;
1145         uint32_t enables = 0;
1146         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1147         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1148         struct rte_mempool *mb_pool;
1149         uint16_t rx_buf_size;
1150
1151         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1152
1153         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1154         req.fbo = rte_cpu_to_le_32(0);
1155         /* Association of ring index with doorbell index */
1156         req.logical_id = rte_cpu_to_le_16(map_index);
1157         req.length = rte_cpu_to_le_32(ring->ring_size);
1158
1159         switch (ring_type) {
1160         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1161                 req.ring_type = ring_type;
1162                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1163                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1164                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1165                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1166                         enables |=
1167                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1168                 break;
1169         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1170                 req.ring_type = ring_type;
1171                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1172                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1173                 if (BNXT_CHIP_THOR(bp)) {
1174                         mb_pool = bp->rx_queues[0]->mb_pool;
1175                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1176                                       RTE_PKTMBUF_HEADROOM;
1177                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1178                         enables |=
1179                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1180                 }
1181                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1182                         enables |=
1183                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1184                 break;
1185         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1186                 req.ring_type = ring_type;
1187                 if (BNXT_HAS_NQ(bp)) {
1188                         /* Association of cp ring with nq */
1189                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1190                         enables |=
1191                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1192                 }
1193                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1194                 break;
1195         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1196                 req.ring_type = ring_type;
1197                 req.page_size = BNXT_PAGE_SHFT;
1198                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1199                 break;
1200         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1201                 req.ring_type = ring_type;
1202                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1203
1204                 mb_pool = bp->rx_queues[0]->mb_pool;
1205                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1206                               RTE_PKTMBUF_HEADROOM;
1207                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1208
1209                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1210                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1211                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1212                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1213                 break;
1214         default:
1215                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1216                         ring_type);
1217                 HWRM_UNLOCK();
1218                 return -EINVAL;
1219         }
1220         req.enables = rte_cpu_to_le_32(enables);
1221
1222         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1223
1224         if (rc || resp->error_code) {
1225                 if (rc == 0 && resp->error_code)
1226                         rc = rte_le_to_cpu_16(resp->error_code);
1227                 switch (ring_type) {
1228                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1229                         PMD_DRV_LOG(ERR,
1230                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1231                         HWRM_UNLOCK();
1232                         return rc;
1233                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1234                         PMD_DRV_LOG(ERR,
1235                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1236                         HWRM_UNLOCK();
1237                         return rc;
1238                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1239                         PMD_DRV_LOG(ERR,
1240                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1241                                     rc);
1242                         HWRM_UNLOCK();
1243                         return rc;
1244                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1245                         PMD_DRV_LOG(ERR,
1246                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1247                         HWRM_UNLOCK();
1248                         return rc;
1249                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1250                         PMD_DRV_LOG(ERR,
1251                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1252                         HWRM_UNLOCK();
1253                         return rc;
1254                 default:
1255                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1256                         HWRM_UNLOCK();
1257                         return rc;
1258                 }
1259         }
1260
1261         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1262         HWRM_UNLOCK();
1263         return rc;
1264 }
1265
1266 int bnxt_hwrm_ring_free(struct bnxt *bp,
1267                         struct bnxt_ring *ring, uint32_t ring_type)
1268 {
1269         int rc;
1270         struct hwrm_ring_free_input req = {.req_type = 0 };
1271         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1272
1273         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1274
1275         req.ring_type = ring_type;
1276         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1277
1278         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1279
1280         if (rc || resp->error_code) {
1281                 if (rc == 0 && resp->error_code)
1282                         rc = rte_le_to_cpu_16(resp->error_code);
1283                 HWRM_UNLOCK();
1284
1285                 switch (ring_type) {
1286                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1287                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1288                                 rc);
1289                         return rc;
1290                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1291                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1292                                 rc);
1293                         return rc;
1294                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1295                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1296                                 rc);
1297                         return rc;
1298                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1299                         PMD_DRV_LOG(ERR,
1300                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1301                         return rc;
1302                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1303                         PMD_DRV_LOG(ERR,
1304                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1305                         return rc;
1306                 default:
1307                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1308                         return rc;
1309                 }
1310         }
1311         HWRM_UNLOCK();
1312         return 0;
1313 }
1314
1315 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1316 {
1317         int rc = 0;
1318         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1319         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1320
1321         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1322
1323         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1324         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1325         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1326         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1327
1328         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1329
1330         HWRM_CHECK_RESULT();
1331
1332         bp->grp_info[idx].fw_grp_id =
1333             rte_le_to_cpu_16(resp->ring_group_id);
1334
1335         HWRM_UNLOCK();
1336
1337         return rc;
1338 }
1339
1340 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1341 {
1342         int rc;
1343         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1344         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1345
1346         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1347
1348         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1349
1350         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1351
1352         HWRM_CHECK_RESULT();
1353         HWRM_UNLOCK();
1354
1355         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1356         return rc;
1357 }
1358
1359 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1360 {
1361         int rc = 0;
1362         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1363         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1364
1365         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1366                 return rc;
1367
1368         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1369
1370         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1371
1372         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1373
1374         HWRM_CHECK_RESULT();
1375         HWRM_UNLOCK();
1376
1377         return rc;
1378 }
1379
1380 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1381                                 unsigned int idx __rte_unused)
1382 {
1383         int rc;
1384         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1385         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1386
1387         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1388
1389         req.update_period_ms = rte_cpu_to_le_32(0);
1390
1391         req.stats_dma_addr =
1392             rte_cpu_to_le_64(cpr->hw_stats_map);
1393
1394         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1395
1396         HWRM_CHECK_RESULT();
1397
1398         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1399
1400         HWRM_UNLOCK();
1401
1402         return rc;
1403 }
1404
1405 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1406                                 unsigned int idx __rte_unused)
1407 {
1408         int rc;
1409         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1410         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1411
1412         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1413
1414         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1415
1416         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1417
1418         HWRM_CHECK_RESULT();
1419         HWRM_UNLOCK();
1420
1421         return rc;
1422 }
1423
1424 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1425 {
1426         int rc = 0, i, j;
1427         struct hwrm_vnic_alloc_input req = { 0 };
1428         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1429
1430         if (!BNXT_HAS_RING_GRPS(bp))
1431                 goto skip_ring_grps;
1432
1433         /* map ring groups to this vnic */
1434         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1435                 vnic->start_grp_id, vnic->end_grp_id);
1436         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1437                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1438
1439         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1440         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1441         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1442         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1443
1444 skip_ring_grps:
1445         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1446                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1447         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1448
1449         if (vnic->func_default)
1450                 req.flags =
1451                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1452         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1453
1454         HWRM_CHECK_RESULT();
1455
1456         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1457         HWRM_UNLOCK();
1458         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1459         return rc;
1460 }
1461
1462 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1463                                         struct bnxt_vnic_info *vnic,
1464                                         struct bnxt_plcmodes_cfg *pmode)
1465 {
1466         int rc = 0;
1467         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1468         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1469
1470         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1471
1472         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1473
1474         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1475
1476         HWRM_CHECK_RESULT();
1477
1478         pmode->flags = rte_le_to_cpu_32(resp->flags);
1479         /* dflt_vnic bit doesn't exist in the _cfg command */
1480         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1481         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1482         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1483         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1484
1485         HWRM_UNLOCK();
1486
1487         return rc;
1488 }
1489
1490 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1491                                        struct bnxt_vnic_info *vnic,
1492                                        struct bnxt_plcmodes_cfg *pmode)
1493 {
1494         int rc = 0;
1495         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1496         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1497
1498         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1499                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1500                 return rc;
1501         }
1502
1503         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1504
1505         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1506         req.flags = rte_cpu_to_le_32(pmode->flags);
1507         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1508         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1509         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1510         req.enables = rte_cpu_to_le_32(
1511             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1512             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1513             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1514         );
1515
1516         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1517
1518         HWRM_CHECK_RESULT();
1519         HWRM_UNLOCK();
1520
1521         return rc;
1522 }
1523
1524 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1525 {
1526         int rc = 0;
1527         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1528         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1529         struct bnxt_plcmodes_cfg pmodes = { 0 };
1530         uint32_t ctx_enable_flag = 0;
1531         uint32_t enables = 0;
1532
1533         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1534                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1535                 return rc;
1536         }
1537
1538         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1539         if (rc)
1540                 return rc;
1541
1542         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1543
1544         if (BNXT_CHIP_THOR(bp)) {
1545                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1546                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1547                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1548
1549                 req.default_rx_ring_id =
1550                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1551                 req.default_cmpl_ring_id =
1552                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1553                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1554                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1555                 goto config_mru;
1556         }
1557
1558         /* Only RSS support for now TBD: COS & LB */
1559         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1560         if (vnic->lb_rule != 0xffff)
1561                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1562         if (vnic->cos_rule != 0xffff)
1563                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1564         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1565                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1566                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1567         }
1568         enables |= ctx_enable_flag;
1569         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1570         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1571         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1572         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1573
1574 config_mru:
1575         req.enables = rte_cpu_to_le_32(enables);
1576         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1577         req.mru = rte_cpu_to_le_16(vnic->mru);
1578         /* Configure default VNIC only once. */
1579         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1580                 req.flags |=
1581                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1582                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1583         }
1584         if (vnic->vlan_strip)
1585                 req.flags |=
1586                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1587         if (vnic->bd_stall)
1588                 req.flags |=
1589                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1590         if (vnic->roce_dual)
1591                 req.flags |= rte_cpu_to_le_32(
1592                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1593         if (vnic->roce_only)
1594                 req.flags |= rte_cpu_to_le_32(
1595                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1596         if (vnic->rss_dflt_cr)
1597                 req.flags |= rte_cpu_to_le_32(
1598                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1599
1600         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1601
1602         HWRM_CHECK_RESULT();
1603         HWRM_UNLOCK();
1604
1605         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1606
1607         return rc;
1608 }
1609
1610 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1611                 int16_t fw_vf_id)
1612 {
1613         int rc = 0;
1614         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1615         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1616
1617         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1618                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1619                 return rc;
1620         }
1621         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1622
1623         req.enables =
1624                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1625         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1626         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1627
1628         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1629
1630         HWRM_CHECK_RESULT();
1631
1632         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1633         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1634         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1635         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1636         vnic->mru = rte_le_to_cpu_16(resp->mru);
1637         vnic->func_default = rte_le_to_cpu_32(
1638                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1639         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1640                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1641         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1642                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1643         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1644                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1645         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1646                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1647         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1648                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1649
1650         HWRM_UNLOCK();
1651
1652         return rc;
1653 }
1654
1655 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1656                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1657 {
1658         int rc = 0;
1659         uint16_t ctx_id;
1660         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1661         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1662                                                 bp->hwrm_cmd_resp_addr;
1663
1664         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1665
1666         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1667         HWRM_CHECK_RESULT();
1668
1669         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1670         if (!BNXT_HAS_RING_GRPS(bp))
1671                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1672         else if (ctx_idx == 0)
1673                 vnic->rss_rule = ctx_id;
1674
1675         HWRM_UNLOCK();
1676
1677         return rc;
1678 }
1679
1680 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1681                             struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1682 {
1683         int rc = 0;
1684         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1685         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1686                                                 bp->hwrm_cmd_resp_addr;
1687
1688         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1689                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1690                 return rc;
1691         }
1692         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1693
1694         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1695
1696         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1697
1698         HWRM_CHECK_RESULT();
1699         HWRM_UNLOCK();
1700
1701         return rc;
1702 }
1703
1704 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1705 {
1706         int rc = 0;
1707         struct hwrm_vnic_free_input req = {.req_type = 0 };
1708         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1709
1710         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1711                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1712                 return rc;
1713         }
1714
1715         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1716
1717         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1718
1719         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1720
1721         HWRM_CHECK_RESULT();
1722         HWRM_UNLOCK();
1723
1724         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1725         /* Configure default VNIC again if necessary. */
1726         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1727                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1728
1729         return rc;
1730 }
1731
1732 static int
1733 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1734 {
1735         int i;
1736         int rc = 0;
1737         int nr_ctxs = vnic->num_lb_ctxts;
1738         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1739         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1740
1741         for (i = 0; i < nr_ctxs; i++) {
1742                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1743
1744                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1745                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1746                 req.hash_mode_flags = vnic->hash_mode;
1747
1748                 req.hash_key_tbl_addr =
1749                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1750
1751                 req.ring_grp_tbl_addr =
1752                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1753                                          i * HW_HASH_INDEX_SIZE);
1754                 req.ring_table_pair_index = i;
1755                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1756
1757                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1758                                             BNXT_USE_CHIMP_MB);
1759
1760                 HWRM_CHECK_RESULT();
1761                 HWRM_UNLOCK();
1762         }
1763
1764         return rc;
1765 }
1766
1767 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1768                            struct bnxt_vnic_info *vnic)
1769 {
1770         int rc = 0;
1771         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1772         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1773
1774         if (!vnic->rss_table)
1775                 return 0;
1776
1777         if (BNXT_CHIP_THOR(bp))
1778                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1779
1780         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1781
1782         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1783         req.hash_mode_flags = vnic->hash_mode;
1784
1785         req.ring_grp_tbl_addr =
1786             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1787         req.hash_key_tbl_addr =
1788             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1789         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1790         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1791
1792         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1793
1794         HWRM_CHECK_RESULT();
1795         HWRM_UNLOCK();
1796
1797         return rc;
1798 }
1799
1800 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1801                         struct bnxt_vnic_info *vnic)
1802 {
1803         int rc = 0;
1804         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1805         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1806         uint16_t size;
1807
1808         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1809                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1810                 return rc;
1811         }
1812
1813         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1814
1815         req.flags = rte_cpu_to_le_32(
1816                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1817
1818         req.enables = rte_cpu_to_le_32(
1819                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1820
1821         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1822         size -= RTE_PKTMBUF_HEADROOM;
1823
1824         req.jumbo_thresh = rte_cpu_to_le_16(size);
1825         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1826
1827         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1828
1829         HWRM_CHECK_RESULT();
1830         HWRM_UNLOCK();
1831
1832         return rc;
1833 }
1834
1835 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1836                         struct bnxt_vnic_info *vnic, bool enable)
1837 {
1838         int rc = 0;
1839         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1840         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1841
1842         if (BNXT_CHIP_THOR(bp))
1843                 return 0;
1844
1845         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1846
1847         if (enable) {
1848                 req.enables = rte_cpu_to_le_32(
1849                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1850                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1851                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1852                 req.flags = rte_cpu_to_le_32(
1853                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1854                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1855                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1856                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1857                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1858                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1859                 req.max_agg_segs = rte_cpu_to_le_16(5);
1860                 req.max_aggs =
1861                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1862                 req.min_agg_len = rte_cpu_to_le_32(512);
1863         }
1864         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1865
1866         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1867
1868         HWRM_CHECK_RESULT();
1869         HWRM_UNLOCK();
1870
1871         return rc;
1872 }
1873
1874 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1875 {
1876         struct hwrm_func_cfg_input req = {0};
1877         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1878         int rc;
1879
1880         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1881         req.enables = rte_cpu_to_le_32(
1882                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1883         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1884         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1885
1886         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1887
1888         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1889         HWRM_CHECK_RESULT();
1890         HWRM_UNLOCK();
1891
1892         bp->pf.vf_info[vf].random_mac = false;
1893
1894         return rc;
1895 }
1896
1897 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1898                                   uint64_t *dropped)
1899 {
1900         int rc = 0;
1901         struct hwrm_func_qstats_input req = {.req_type = 0};
1902         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1903
1904         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1905
1906         req.fid = rte_cpu_to_le_16(fid);
1907
1908         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1909
1910         HWRM_CHECK_RESULT();
1911
1912         if (dropped)
1913                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1914
1915         HWRM_UNLOCK();
1916
1917         return rc;
1918 }
1919
1920 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1921                           struct rte_eth_stats *stats)
1922 {
1923         int rc = 0;
1924         struct hwrm_func_qstats_input req = {.req_type = 0};
1925         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1926
1927         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1928
1929         req.fid = rte_cpu_to_le_16(fid);
1930
1931         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1932
1933         HWRM_CHECK_RESULT();
1934
1935         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1936         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1937         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1938         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1939         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1940         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1941
1942         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1943         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1944         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1945         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1946         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1947         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1948
1949         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1950         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1951         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1952
1953         HWRM_UNLOCK();
1954
1955         return rc;
1956 }
1957
1958 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1959 {
1960         int rc = 0;
1961         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1962         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1963
1964         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1965
1966         req.fid = rte_cpu_to_le_16(fid);
1967
1968         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1969
1970         HWRM_CHECK_RESULT();
1971         HWRM_UNLOCK();
1972
1973         return rc;
1974 }
1975
1976 /*
1977  * HWRM utility functions
1978  */
1979
1980 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1981 {
1982         unsigned int i;
1983         int rc = 0;
1984
1985         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1986                 struct bnxt_tx_queue *txq;
1987                 struct bnxt_rx_queue *rxq;
1988                 struct bnxt_cp_ring_info *cpr;
1989
1990                 if (i >= bp->rx_cp_nr_rings) {
1991                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1992                         cpr = txq->cp_ring;
1993                 } else {
1994                         rxq = bp->rx_queues[i];
1995                         cpr = rxq->cp_ring;
1996                 }
1997
1998                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1999                 if (rc)
2000                         return rc;
2001         }
2002         return 0;
2003 }
2004
2005 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2006 {
2007         int rc;
2008         unsigned int i;
2009         struct bnxt_cp_ring_info *cpr;
2010
2011         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2012
2013                 if (i >= bp->rx_cp_nr_rings) {
2014                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2015                 } else {
2016                         cpr = bp->rx_queues[i]->cp_ring;
2017                         if (BNXT_HAS_RING_GRPS(bp))
2018                                 bp->grp_info[i].fw_stats_ctx = -1;
2019                 }
2020                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2021                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2022                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2023                         if (rc)
2024                                 return rc;
2025                 }
2026         }
2027         return 0;
2028 }
2029
2030 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2031 {
2032         unsigned int i;
2033         int rc = 0;
2034
2035         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2036                 struct bnxt_tx_queue *txq;
2037                 struct bnxt_rx_queue *rxq;
2038                 struct bnxt_cp_ring_info *cpr;
2039
2040                 if (i >= bp->rx_cp_nr_rings) {
2041                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2042                         cpr = txq->cp_ring;
2043                 } else {
2044                         rxq = bp->rx_queues[i];
2045                         cpr = rxq->cp_ring;
2046                 }
2047
2048                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2049
2050                 if (rc)
2051                         return rc;
2052         }
2053         return rc;
2054 }
2055
2056 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2057 {
2058         uint16_t idx;
2059         uint32_t rc = 0;
2060
2061         if (!BNXT_HAS_RING_GRPS(bp))
2062                 return 0;
2063
2064         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2065
2066                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2067                         continue;
2068
2069                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2070
2071                 if (rc)
2072                         return rc;
2073         }
2074         return rc;
2075 }
2076
2077 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2078 {
2079         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2080
2081         bnxt_hwrm_ring_free(bp, cp_ring,
2082                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2083         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2084         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2085                                      sizeof(*cpr->cp_desc_ring));
2086         cpr->cp_raw_cons = 0;
2087         cpr->valid = 0;
2088 }
2089
2090 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2091 {
2092         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2093
2094         bnxt_hwrm_ring_free(bp, cp_ring,
2095                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2096         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2097         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2098                         sizeof(*cpr->cp_desc_ring));
2099         cpr->cp_raw_cons = 0;
2100         cpr->valid = 0;
2101 }
2102
2103 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2104 {
2105         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2106         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2107         struct bnxt_ring *ring = rxr->rx_ring_struct;
2108         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2109
2110         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2111                 bnxt_hwrm_ring_free(bp, ring,
2112                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2113                 ring->fw_ring_id = INVALID_HW_RING_ID;
2114                 if (BNXT_HAS_RING_GRPS(bp))
2115                         bp->grp_info[queue_index].rx_fw_ring_id =
2116                                                         INVALID_HW_RING_ID;
2117                 memset(rxr->rx_desc_ring, 0,
2118                        rxr->rx_ring_struct->ring_size *
2119                        sizeof(*rxr->rx_desc_ring));
2120                 memset(rxr->rx_buf_ring, 0,
2121                        rxr->rx_ring_struct->ring_size *
2122                        sizeof(*rxr->rx_buf_ring));
2123                 rxr->rx_prod = 0;
2124         }
2125         ring = rxr->ag_ring_struct;
2126         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2127                 bnxt_hwrm_ring_free(bp, ring,
2128                                     BNXT_CHIP_THOR(bp) ?
2129                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2130                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2131                 ring->fw_ring_id = INVALID_HW_RING_ID;
2132                 memset(rxr->ag_buf_ring, 0,
2133                        rxr->ag_ring_struct->ring_size *
2134                        sizeof(*rxr->ag_buf_ring));
2135                 rxr->ag_prod = 0;
2136                 if (BNXT_HAS_RING_GRPS(bp))
2137                         bp->grp_info[queue_index].ag_fw_ring_id =
2138                                                         INVALID_HW_RING_ID;
2139         }
2140         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2141                 bnxt_free_cp_ring(bp, cpr);
2142                 if (rxq->nq_ring)
2143                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2144         }
2145
2146         if (BNXT_HAS_RING_GRPS(bp))
2147                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2148 }
2149
2150 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2151 {
2152         unsigned int i;
2153
2154         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2155                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2156                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2157                 struct bnxt_ring *ring = txr->tx_ring_struct;
2158                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2159
2160                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2161                         bnxt_hwrm_ring_free(bp, ring,
2162                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2163                         ring->fw_ring_id = INVALID_HW_RING_ID;
2164                         memset(txr->tx_desc_ring, 0,
2165                                         txr->tx_ring_struct->ring_size *
2166                                         sizeof(*txr->tx_desc_ring));
2167                         memset(txr->tx_buf_ring, 0,
2168                                         txr->tx_ring_struct->ring_size *
2169                                         sizeof(*txr->tx_buf_ring));
2170                         txr->tx_prod = 0;
2171                         txr->tx_cons = 0;
2172                 }
2173                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2174                         bnxt_free_cp_ring(bp, cpr);
2175                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2176                         if (txq->nq_ring)
2177                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2178                 }
2179         }
2180
2181         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2182                 bnxt_free_hwrm_rx_ring(bp, i);
2183
2184         return 0;
2185 }
2186
2187 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2188 {
2189         uint16_t i;
2190         uint32_t rc = 0;
2191
2192         if (!BNXT_HAS_RING_GRPS(bp))
2193                 return 0;
2194
2195         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2196                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2197                 if (rc)
2198                         return rc;
2199         }
2200         return rc;
2201 }
2202
2203 void bnxt_free_hwrm_resources(struct bnxt *bp)
2204 {
2205         /* Release memzone */
2206         rte_free(bp->hwrm_cmd_resp_addr);
2207         rte_free(bp->hwrm_short_cmd_req_addr);
2208         bp->hwrm_cmd_resp_addr = NULL;
2209         bp->hwrm_short_cmd_req_addr = NULL;
2210         bp->hwrm_cmd_resp_dma_addr = 0;
2211         bp->hwrm_short_cmd_req_dma_addr = 0;
2212 }
2213
2214 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2215 {
2216         struct rte_pci_device *pdev = bp->pdev;
2217         char type[RTE_MEMZONE_NAMESIZE];
2218
2219         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2220                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2221         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2222         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2223         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2224         if (bp->hwrm_cmd_resp_addr == NULL)
2225                 return -ENOMEM;
2226         bp->hwrm_cmd_resp_dma_addr =
2227                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2228         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2229                 PMD_DRV_LOG(ERR,
2230                         "unable to map response address to physical memory\n");
2231                 return -ENOMEM;
2232         }
2233         rte_spinlock_init(&bp->hwrm_lock);
2234
2235         return 0;
2236 }
2237
2238 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2239 {
2240         struct bnxt_filter_info *filter;
2241         int rc = 0;
2242
2243         STAILQ_FOREACH(filter, &vnic->filter, next) {
2244                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2245                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2246                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2247                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2248                 else
2249                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2250                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2251                 //if (rc)
2252                         //break;
2253         }
2254         return rc;
2255 }
2256
2257 static int
2258 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2259 {
2260         struct bnxt_filter_info *filter;
2261         struct rte_flow *flow;
2262         int rc = 0;
2263
2264         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2265                 filter = flow->filter;
2266                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2267                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2268                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2269                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2270                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2271                 else
2272                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2273
2274                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2275                 rte_free(flow);
2276                 //if (rc)
2277                         //break;
2278         }
2279         return rc;
2280 }
2281
2282 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2283 {
2284         struct bnxt_filter_info *filter;
2285         int rc = 0;
2286
2287         STAILQ_FOREACH(filter, &vnic->filter, next) {
2288                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2289                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2290                                                      filter);
2291                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2292                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2293                                                          filter);
2294                 else
2295                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2296                                                      filter);
2297                 if (rc)
2298                         break;
2299         }
2300         return rc;
2301 }
2302
2303 void bnxt_free_tunnel_ports(struct bnxt *bp)
2304 {
2305         if (bp->vxlan_port_cnt)
2306                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2307                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2308         bp->vxlan_port = 0;
2309         if (bp->geneve_port_cnt)
2310                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2311                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2312         bp->geneve_port = 0;
2313 }
2314
2315 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2316 {
2317         int i, j;
2318
2319         if (bp->vnic_info == NULL)
2320                 return;
2321
2322         /*
2323          * Cleanup VNICs in reverse order, to make sure the L2 filter
2324          * from vnic0 is last to be cleaned up.
2325          */
2326         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2327                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2328
2329                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2330                         PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2331                         return;
2332                 }
2333
2334                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2335
2336                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2337
2338                 if (BNXT_CHIP_THOR(bp)) {
2339                         for (j = 0; j < vnic->num_lb_ctxts; j++) {
2340                                 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2341                                                         vnic->fw_grp_ids[j]);
2342                                 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2343                         }
2344                         vnic->num_lb_ctxts = 0;
2345                 } else {
2346                         bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2347                         vnic->rss_rule = INVALID_HW_RING_ID;
2348                 }
2349
2350                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2351
2352                 bnxt_hwrm_vnic_free(bp, vnic);
2353
2354                 rte_free(vnic->fw_grp_ids);
2355         }
2356         /* Ring resources */
2357         bnxt_free_all_hwrm_rings(bp);
2358         bnxt_free_all_hwrm_ring_grps(bp);
2359         bnxt_free_all_hwrm_stat_ctxs(bp);
2360         bnxt_free_tunnel_ports(bp);
2361 }
2362
2363 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2364 {
2365         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2366
2367         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2368                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2369
2370         switch (conf_link_speed) {
2371         case ETH_LINK_SPEED_10M_HD:
2372         case ETH_LINK_SPEED_100M_HD:
2373                 /* FALLTHROUGH */
2374                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2375         }
2376         return hw_link_duplex;
2377 }
2378
2379 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2380 {
2381         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2382 }
2383
2384 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2385 {
2386         uint16_t eth_link_speed = 0;
2387
2388         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2389                 return ETH_LINK_SPEED_AUTONEG;
2390
2391         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2392         case ETH_LINK_SPEED_100M:
2393         case ETH_LINK_SPEED_100M_HD:
2394                 /* FALLTHROUGH */
2395                 eth_link_speed =
2396                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2397                 break;
2398         case ETH_LINK_SPEED_1G:
2399                 eth_link_speed =
2400                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2401                 break;
2402         case ETH_LINK_SPEED_2_5G:
2403                 eth_link_speed =
2404                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2405                 break;
2406         case ETH_LINK_SPEED_10G:
2407                 eth_link_speed =
2408                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2409                 break;
2410         case ETH_LINK_SPEED_20G:
2411                 eth_link_speed =
2412                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2413                 break;
2414         case ETH_LINK_SPEED_25G:
2415                 eth_link_speed =
2416                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2417                 break;
2418         case ETH_LINK_SPEED_40G:
2419                 eth_link_speed =
2420                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2421                 break;
2422         case ETH_LINK_SPEED_50G:
2423                 eth_link_speed =
2424                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2425                 break;
2426         case ETH_LINK_SPEED_100G:
2427                 eth_link_speed =
2428                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2429                 break;
2430         default:
2431                 PMD_DRV_LOG(ERR,
2432                         "Unsupported link speed %d; default to AUTO\n",
2433                         conf_link_speed);
2434                 break;
2435         }
2436         return eth_link_speed;
2437 }
2438
2439 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2440                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2441                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2442                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2443
2444 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2445 {
2446         uint32_t one_speed;
2447
2448         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2449                 return 0;
2450
2451         if (link_speed & ETH_LINK_SPEED_FIXED) {
2452                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2453
2454                 if (one_speed & (one_speed - 1)) {
2455                         PMD_DRV_LOG(ERR,
2456                                 "Invalid advertised speeds (%u) for port %u\n",
2457                                 link_speed, port_id);
2458                         return -EINVAL;
2459                 }
2460                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2461                         PMD_DRV_LOG(ERR,
2462                                 "Unsupported advertised speed (%u) for port %u\n",
2463                                 link_speed, port_id);
2464                         return -EINVAL;
2465                 }
2466         } else {
2467                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2468                         PMD_DRV_LOG(ERR,
2469                                 "Unsupported advertised speeds (%u) for port %u\n",
2470                                 link_speed, port_id);
2471                         return -EINVAL;
2472                 }
2473         }
2474         return 0;
2475 }
2476
2477 static uint16_t
2478 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2479 {
2480         uint16_t ret = 0;
2481
2482         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2483                 if (bp->link_info.support_speeds)
2484                         return bp->link_info.support_speeds;
2485                 link_speed = BNXT_SUPPORTED_SPEEDS;
2486         }
2487
2488         if (link_speed & ETH_LINK_SPEED_100M)
2489                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2490         if (link_speed & ETH_LINK_SPEED_100M_HD)
2491                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2492         if (link_speed & ETH_LINK_SPEED_1G)
2493                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2494         if (link_speed & ETH_LINK_SPEED_2_5G)
2495                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2496         if (link_speed & ETH_LINK_SPEED_10G)
2497                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2498         if (link_speed & ETH_LINK_SPEED_20G)
2499                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2500         if (link_speed & ETH_LINK_SPEED_25G)
2501                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2502         if (link_speed & ETH_LINK_SPEED_40G)
2503                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2504         if (link_speed & ETH_LINK_SPEED_50G)
2505                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2506         if (link_speed & ETH_LINK_SPEED_100G)
2507                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2508         return ret;
2509 }
2510
2511 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2512 {
2513         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2514
2515         switch (hw_link_speed) {
2516         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2517                 eth_link_speed = ETH_SPEED_NUM_100M;
2518                 break;
2519         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2520                 eth_link_speed = ETH_SPEED_NUM_1G;
2521                 break;
2522         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2523                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2524                 break;
2525         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2526                 eth_link_speed = ETH_SPEED_NUM_10G;
2527                 break;
2528         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2529                 eth_link_speed = ETH_SPEED_NUM_20G;
2530                 break;
2531         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2532                 eth_link_speed = ETH_SPEED_NUM_25G;
2533                 break;
2534         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2535                 eth_link_speed = ETH_SPEED_NUM_40G;
2536                 break;
2537         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2538                 eth_link_speed = ETH_SPEED_NUM_50G;
2539                 break;
2540         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2541                 eth_link_speed = ETH_SPEED_NUM_100G;
2542                 break;
2543         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2544         default:
2545                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2546                         hw_link_speed);
2547                 break;
2548         }
2549         return eth_link_speed;
2550 }
2551
2552 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2553 {
2554         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2555
2556         switch (hw_link_duplex) {
2557         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2558         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2559                 /* FALLTHROUGH */
2560                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2561                 break;
2562         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2563                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2564                 break;
2565         default:
2566                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2567                         hw_link_duplex);
2568                 break;
2569         }
2570         return eth_link_duplex;
2571 }
2572
2573 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2574 {
2575         int rc = 0;
2576         struct bnxt_link_info *link_info = &bp->link_info;
2577
2578         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2579         if (rc) {
2580                 PMD_DRV_LOG(ERR,
2581                         "Get link config failed with rc %d\n", rc);
2582                 goto exit;
2583         }
2584         if (link_info->link_speed)
2585                 link->link_speed =
2586                         bnxt_parse_hw_link_speed(link_info->link_speed);
2587         else
2588                 link->link_speed = ETH_SPEED_NUM_NONE;
2589         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2590         link->link_status = link_info->link_up;
2591         link->link_autoneg = link_info->auto_mode ==
2592                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2593                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2594 exit:
2595         return rc;
2596 }
2597
2598 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2599 {
2600         int rc = 0;
2601         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2602         struct bnxt_link_info link_req;
2603         uint16_t speed, autoneg;
2604
2605         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2606                 return 0;
2607
2608         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2609                         bp->eth_dev->data->port_id);
2610         if (rc)
2611                 goto error;
2612
2613         memset(&link_req, 0, sizeof(link_req));
2614         link_req.link_up = link_up;
2615         if (!link_up)
2616                 goto port_phy_cfg;
2617
2618         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2619         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2620         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2621         /* Autoneg can be done only when the FW allows */
2622         if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2623                                 bp->link_info.force_link_speed)) {
2624                 link_req.phy_flags |=
2625                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2626                 link_req.auto_link_speed_mask =
2627                         bnxt_parse_eth_link_speed_mask(bp,
2628                                                        dev_conf->link_speeds);
2629         } else {
2630                 if (bp->link_info.phy_type ==
2631                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2632                     bp->link_info.phy_type ==
2633                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2634                     bp->link_info.media_type ==
2635                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2636                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2637                         return -EINVAL;
2638                 }
2639
2640                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2641                 /* If user wants a particular speed try that first. */
2642                 if (speed)
2643                         link_req.link_speed = speed;
2644                 else if (bp->link_info.force_link_speed)
2645                         link_req.link_speed = bp->link_info.force_link_speed;
2646                 else
2647                         link_req.link_speed = bp->link_info.auto_link_speed;
2648         }
2649         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2650         link_req.auto_pause = bp->link_info.auto_pause;
2651         link_req.force_pause = bp->link_info.force_pause;
2652
2653 port_phy_cfg:
2654         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2655         if (rc) {
2656                 PMD_DRV_LOG(ERR,
2657                         "Set link config failed with rc %d\n", rc);
2658         }
2659
2660 error:
2661         return rc;
2662 }
2663
2664 /* JIRA 22088 */
2665 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2666 {
2667         struct hwrm_func_qcfg_input req = {0};
2668         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2669         uint16_t flags;
2670         int rc = 0;
2671
2672         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2673         req.fid = rte_cpu_to_le_16(0xffff);
2674
2675         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2676
2677         HWRM_CHECK_RESULT();
2678
2679         /* Hard Coded.. 0xfff VLAN ID mask */
2680         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2681         flags = rte_le_to_cpu_16(resp->flags);
2682         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2683                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2684
2685         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2686                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2687                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2688         }
2689
2690         if (mtu)
2691                 *mtu = resp->mtu;
2692
2693         switch (resp->port_partition_type) {
2694         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2695         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2696         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2697                 /* FALLTHROUGH */
2698                 bp->port_partition_type = resp->port_partition_type;
2699                 break;
2700         default:
2701                 bp->port_partition_type = 0;
2702                 break;
2703         }
2704
2705         HWRM_UNLOCK();
2706
2707         return rc;
2708 }
2709
2710 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2711                                    struct hwrm_func_qcaps_output *qcaps)
2712 {
2713         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2714         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2715                sizeof(qcaps->mac_address));
2716         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2717         qcaps->max_rx_rings = fcfg->num_rx_rings;
2718         qcaps->max_tx_rings = fcfg->num_tx_rings;
2719         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2720         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2721         qcaps->max_vfs = 0;
2722         qcaps->first_vf_id = 0;
2723         qcaps->max_vnics = fcfg->num_vnics;
2724         qcaps->max_decap_records = 0;
2725         qcaps->max_encap_records = 0;
2726         qcaps->max_tx_wm_flows = 0;
2727         qcaps->max_tx_em_flows = 0;
2728         qcaps->max_rx_wm_flows = 0;
2729         qcaps->max_rx_em_flows = 0;
2730         qcaps->max_flow_id = 0;
2731         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2732         qcaps->max_sp_tx_rings = 0;
2733         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2734 }
2735
2736 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2737 {
2738         struct hwrm_func_cfg_input req = {0};
2739         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2740         uint32_t enables;
2741         int rc;
2742
2743         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2744                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2745                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2746                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2747                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2748                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2749                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2750                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2751                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2752
2753         if (BNXT_HAS_RING_GRPS(bp)) {
2754                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2755                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2756         } else if (BNXT_HAS_NQ(bp)) {
2757                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2758                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2759         }
2760
2761         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2762         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2763         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2764                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2765                                    BNXT_NUM_VLANS);
2766         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2767         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2768         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2769         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2770         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2771         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2772         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2773         req.fid = rte_cpu_to_le_16(0xffff);
2774         req.enables = rte_cpu_to_le_32(enables);
2775
2776         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2777
2778         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2779
2780         HWRM_CHECK_RESULT();
2781         HWRM_UNLOCK();
2782
2783         return rc;
2784 }
2785
2786 static void populate_vf_func_cfg_req(struct bnxt *bp,
2787                                      struct hwrm_func_cfg_input *req,
2788                                      int num_vfs)
2789 {
2790         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2791                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2792                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2793                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2794                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2795                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2796                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2797                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2798                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2799                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2800
2801         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2802                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2803                                     BNXT_NUM_VLANS);
2804         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2805                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2806                                     BNXT_NUM_VLANS);
2807         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2808                                                 (num_vfs + 1));
2809         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2810         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2811                                                (num_vfs + 1));
2812         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2813         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2814         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2815         /* TODO: For now, do not support VMDq/RFS on VFs. */
2816         req->num_vnics = rte_cpu_to_le_16(1);
2817         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2818                                                  (num_vfs + 1));
2819 }
2820
2821 static void add_random_mac_if_needed(struct bnxt *bp,
2822                                      struct hwrm_func_cfg_input *cfg_req,
2823                                      int vf)
2824 {
2825         struct rte_ether_addr mac;
2826
2827         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2828                 return;
2829
2830         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2831                 cfg_req->enables |=
2832                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2833                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2834                 bp->pf.vf_info[vf].random_mac = true;
2835         } else {
2836                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2837                         RTE_ETHER_ADDR_LEN);
2838         }
2839 }
2840
2841 static void reserve_resources_from_vf(struct bnxt *bp,
2842                                       struct hwrm_func_cfg_input *cfg_req,
2843                                       int vf)
2844 {
2845         struct hwrm_func_qcaps_input req = {0};
2846         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2847         int rc;
2848
2849         /* Get the actual allocated values now */
2850         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2851         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2852         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2853
2854         if (rc) {
2855                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2856                 copy_func_cfg_to_qcaps(cfg_req, resp);
2857         } else if (resp->error_code) {
2858                 rc = rte_le_to_cpu_16(resp->error_code);
2859                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2860                 copy_func_cfg_to_qcaps(cfg_req, resp);
2861         }
2862
2863         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2864         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2865         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2866         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2867         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2868         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2869         /*
2870          * TODO: While not supporting VMDq with VFs, max_vnics is always
2871          * forced to 1 in this case
2872          */
2873         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2874         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2875
2876         HWRM_UNLOCK();
2877 }
2878
2879 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2880 {
2881         struct hwrm_func_qcfg_input req = {0};
2882         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2883         int rc;
2884
2885         /* Check for zero MAC address */
2886         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2887         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2888         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2889         HWRM_CHECK_RESULT();
2890         rc = rte_le_to_cpu_16(resp->vlan);
2891
2892         HWRM_UNLOCK();
2893
2894         return rc;
2895 }
2896
2897 static int update_pf_resource_max(struct bnxt *bp)
2898 {
2899         struct hwrm_func_qcfg_input req = {0};
2900         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2901         int rc;
2902
2903         /* And copy the allocated numbers into the pf struct */
2904         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2905         req.fid = rte_cpu_to_le_16(0xffff);
2906         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2907         HWRM_CHECK_RESULT();
2908
2909         /* Only TX ring value reflects actual allocation? TODO */
2910         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2911         bp->pf.evb_mode = resp->evb_mode;
2912
2913         HWRM_UNLOCK();
2914
2915         return rc;
2916 }
2917
2918 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2919 {
2920         int rc;
2921
2922         if (!BNXT_PF(bp)) {
2923                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2924                 return -EINVAL;
2925         }
2926
2927         rc = bnxt_hwrm_func_qcaps(bp);
2928         if (rc)
2929                 return rc;
2930
2931         bp->pf.func_cfg_flags &=
2932                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2933                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2934         bp->pf.func_cfg_flags |=
2935                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2936         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2937         rc = __bnxt_hwrm_func_qcaps(bp);
2938         return rc;
2939 }
2940
2941 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2942 {
2943         struct hwrm_func_cfg_input req = {0};
2944         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2945         int i;
2946         size_t sz;
2947         int rc = 0;
2948         size_t req_buf_sz;
2949
2950         if (!BNXT_PF(bp)) {
2951                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2952                 return -EINVAL;
2953         }
2954
2955         rc = bnxt_hwrm_func_qcaps(bp);
2956
2957         if (rc)
2958                 return rc;
2959
2960         bp->pf.active_vfs = num_vfs;
2961
2962         /*
2963          * First, configure the PF to only use one TX ring.  This ensures that
2964          * there are enough rings for all VFs.
2965          *
2966          * If we don't do this, when we call func_alloc() later, we will lock
2967          * extra rings to the PF that won't be available during func_cfg() of
2968          * the VFs.
2969          *
2970          * This has been fixed with firmware versions above 20.6.54
2971          */
2972         bp->pf.func_cfg_flags &=
2973                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2974                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2975         bp->pf.func_cfg_flags |=
2976                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2977         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2978         if (rc)
2979                 return rc;
2980
2981         /*
2982          * Now, create and register a buffer to hold forwarded VF requests
2983          */
2984         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2985         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2986                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2987         if (bp->pf.vf_req_buf == NULL) {
2988                 rc = -ENOMEM;
2989                 goto error_free;
2990         }
2991         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2992                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2993         for (i = 0; i < num_vfs; i++)
2994                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2995                                         (i * HWRM_MAX_REQ_LEN);
2996
2997         rc = bnxt_hwrm_func_buf_rgtr(bp);
2998         if (rc)
2999                 goto error_free;
3000
3001         populate_vf_func_cfg_req(bp, &req, num_vfs);
3002
3003         bp->pf.active_vfs = 0;
3004         for (i = 0; i < num_vfs; i++) {
3005                 add_random_mac_if_needed(bp, &req, i);
3006
3007                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3008                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3009                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3010                 rc = bnxt_hwrm_send_message(bp,
3011                                             &req,
3012                                             sizeof(req),
3013                                             BNXT_USE_CHIMP_MB);
3014
3015                 /* Clear enable flag for next pass */
3016                 req.enables &= ~rte_cpu_to_le_32(
3017                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3018
3019                 if (rc || resp->error_code) {
3020                         PMD_DRV_LOG(ERR,
3021                                 "Failed to initizlie VF %d\n", i);
3022                         PMD_DRV_LOG(ERR,
3023                                 "Not all VFs available. (%d, %d)\n",
3024                                 rc, resp->error_code);
3025                         HWRM_UNLOCK();
3026                         break;
3027                 }
3028
3029                 HWRM_UNLOCK();
3030
3031                 reserve_resources_from_vf(bp, &req, i);
3032                 bp->pf.active_vfs++;
3033                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3034         }
3035
3036         /*
3037          * Now configure the PF to use "the rest" of the resources
3038          * We're using STD_TX_RING_MODE here though which will limit the TX
3039          * rings.  This will allow QoS to function properly.  Not setting this
3040          * will cause PF rings to break bandwidth settings.
3041          */
3042         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3043         if (rc)
3044                 goto error_free;
3045
3046         rc = update_pf_resource_max(bp);
3047         if (rc)
3048                 goto error_free;
3049
3050         return rc;
3051
3052 error_free:
3053         bnxt_hwrm_func_buf_unrgtr(bp);
3054         return rc;
3055 }
3056
3057 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3058 {
3059         struct hwrm_func_cfg_input req = {0};
3060         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3061         int rc;
3062
3063         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3064
3065         req.fid = rte_cpu_to_le_16(0xffff);
3066         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3067         req.evb_mode = bp->pf.evb_mode;
3068
3069         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3070         HWRM_CHECK_RESULT();
3071         HWRM_UNLOCK();
3072
3073         return rc;
3074 }
3075
3076 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3077                                 uint8_t tunnel_type)
3078 {
3079         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3080         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3081         int rc = 0;
3082
3083         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3084         req.tunnel_type = tunnel_type;
3085         req.tunnel_dst_port_val = port;
3086         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3087         HWRM_CHECK_RESULT();
3088
3089         switch (tunnel_type) {
3090         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3091                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3092                 bp->vxlan_port = port;
3093                 break;
3094         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3095                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3096                 bp->geneve_port = port;
3097                 break;
3098         default:
3099                 break;
3100         }
3101
3102         HWRM_UNLOCK();
3103
3104         return rc;
3105 }
3106
3107 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3108                                 uint8_t tunnel_type)
3109 {
3110         struct hwrm_tunnel_dst_port_free_input req = {0};
3111         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3112         int rc = 0;
3113
3114         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3115
3116         req.tunnel_type = tunnel_type;
3117         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3118         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3119
3120         HWRM_CHECK_RESULT();
3121         HWRM_UNLOCK();
3122
3123         return rc;
3124 }
3125
3126 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3127                                         uint32_t flags)
3128 {
3129         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3130         struct hwrm_func_cfg_input req = {0};
3131         int rc;
3132
3133         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3134
3135         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3136         req.flags = rte_cpu_to_le_32(flags);
3137         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3138
3139         HWRM_CHECK_RESULT();
3140         HWRM_UNLOCK();
3141
3142         return rc;
3143 }
3144
3145 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3146 {
3147         uint32_t *flag = flagp;
3148
3149         vnic->flags = *flag;
3150 }
3151
3152 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3153 {
3154         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3155 }
3156
3157 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3158 {
3159         int rc = 0;
3160         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3161         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3162
3163         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3164
3165         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3166         req.req_buf_page_size = rte_cpu_to_le_16(
3167                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3168         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3169         req.req_buf_page_addr0 =
3170                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3171         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3172                 PMD_DRV_LOG(ERR,
3173                         "unable to map buffer address to physical memory\n");
3174                 return -ENOMEM;
3175         }
3176
3177         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3178
3179         HWRM_CHECK_RESULT();
3180         HWRM_UNLOCK();
3181
3182         return rc;
3183 }
3184
3185 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3186 {
3187         int rc = 0;
3188         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3189         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3190
3191         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3192                 return 0;
3193
3194         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3195
3196         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3197
3198         HWRM_CHECK_RESULT();
3199         HWRM_UNLOCK();
3200
3201         return rc;
3202 }
3203
3204 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3205 {
3206         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3207         struct hwrm_func_cfg_input req = {0};
3208         int rc;
3209
3210         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3211
3212         req.fid = rte_cpu_to_le_16(0xffff);
3213         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3214         req.enables = rte_cpu_to_le_32(
3215                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3216         req.async_event_cr = rte_cpu_to_le_16(
3217                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3218         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3219
3220         HWRM_CHECK_RESULT();
3221         HWRM_UNLOCK();
3222
3223         return rc;
3224 }
3225
3226 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3227 {
3228         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3229         struct hwrm_func_vf_cfg_input req = {0};
3230         int rc;
3231
3232         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3233
3234         req.enables = rte_cpu_to_le_32(
3235                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3236         req.async_event_cr = rte_cpu_to_le_16(
3237                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3238         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3239
3240         HWRM_CHECK_RESULT();
3241         HWRM_UNLOCK();
3242
3243         return rc;
3244 }
3245
3246 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3247 {
3248         struct hwrm_func_cfg_input req = {0};
3249         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3250         uint16_t dflt_vlan, fid;
3251         uint32_t func_cfg_flags;
3252         int rc = 0;
3253
3254         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3255
3256         if (is_vf) {
3257                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3258                 fid = bp->pf.vf_info[vf].fid;
3259                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3260         } else {
3261                 fid = rte_cpu_to_le_16(0xffff);
3262                 func_cfg_flags = bp->pf.func_cfg_flags;
3263                 dflt_vlan = bp->vlan;
3264         }
3265
3266         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3267         req.fid = rte_cpu_to_le_16(fid);
3268         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3269         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3270
3271         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3272
3273         HWRM_CHECK_RESULT();
3274         HWRM_UNLOCK();
3275
3276         return rc;
3277 }
3278
3279 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3280                         uint16_t max_bw, uint16_t enables)
3281 {
3282         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3283         struct hwrm_func_cfg_input req = {0};
3284         int rc;
3285
3286         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3287
3288         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3289         req.enables |= rte_cpu_to_le_32(enables);
3290         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3291         req.max_bw = rte_cpu_to_le_32(max_bw);
3292         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3293
3294         HWRM_CHECK_RESULT();
3295         HWRM_UNLOCK();
3296
3297         return rc;
3298 }
3299
3300 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3301 {
3302         struct hwrm_func_cfg_input req = {0};
3303         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3304         int rc = 0;
3305
3306         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3307
3308         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3309         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3310         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3311         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3312
3313         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3314
3315         HWRM_CHECK_RESULT();
3316         HWRM_UNLOCK();
3317
3318         return rc;
3319 }
3320
3321 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3322 {
3323         int rc;
3324
3325         if (BNXT_PF(bp))
3326                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3327         else
3328                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3329
3330         return rc;
3331 }
3332
3333 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3334                               void *encaped, size_t ec_size)
3335 {
3336         int rc = 0;
3337         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3338         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3339
3340         if (ec_size > sizeof(req.encap_request))
3341                 return -1;
3342
3343         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3344
3345         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3346         memcpy(req.encap_request, encaped, ec_size);
3347
3348         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3349
3350         HWRM_CHECK_RESULT();
3351         HWRM_UNLOCK();
3352
3353         return rc;
3354 }
3355
3356 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3357                                        struct rte_ether_addr *mac)
3358 {
3359         struct hwrm_func_qcfg_input req = {0};
3360         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3361         int rc;
3362
3363         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3364
3365         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3366         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3367
3368         HWRM_CHECK_RESULT();
3369
3370         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3371
3372         HWRM_UNLOCK();
3373
3374         return rc;
3375 }
3376
3377 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3378                             void *encaped, size_t ec_size)
3379 {
3380         int rc = 0;
3381         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3382         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3383
3384         if (ec_size > sizeof(req.encap_request))
3385                 return -1;
3386
3387         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3388
3389         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3390         memcpy(req.encap_request, encaped, ec_size);
3391
3392         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3393
3394         HWRM_CHECK_RESULT();
3395         HWRM_UNLOCK();
3396
3397         return rc;
3398 }
3399
3400 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3401                          struct rte_eth_stats *stats, uint8_t rx)
3402 {
3403         int rc = 0;
3404         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3405         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3406
3407         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3408
3409         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3410
3411         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3412
3413         HWRM_CHECK_RESULT();
3414
3415         if (rx) {
3416                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3417                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3418                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3419                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3420                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3421                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3422                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3423                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3424         } else {
3425                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3426                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3427                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3428                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3429                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3430                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3431         }
3432
3433
3434         HWRM_UNLOCK();
3435
3436         return rc;
3437 }
3438
3439 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3440 {
3441         struct hwrm_port_qstats_input req = {0};
3442         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3443         struct bnxt_pf_info *pf = &bp->pf;
3444         int rc;
3445
3446         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3447
3448         req.port_id = rte_cpu_to_le_16(pf->port_id);
3449         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3450         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3451         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3452
3453         HWRM_CHECK_RESULT();
3454         HWRM_UNLOCK();
3455
3456         return rc;
3457 }
3458
3459 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3460 {
3461         struct hwrm_port_clr_stats_input req = {0};
3462         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3463         struct bnxt_pf_info *pf = &bp->pf;
3464         int rc;
3465
3466         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3467         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3468             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3469                 return 0;
3470
3471         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3472
3473         req.port_id = rte_cpu_to_le_16(pf->port_id);
3474         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3475
3476         HWRM_CHECK_RESULT();
3477         HWRM_UNLOCK();
3478
3479         return rc;
3480 }
3481
3482 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3483 {
3484         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3485         struct hwrm_port_led_qcaps_input req = {0};
3486         int rc;
3487
3488         if (BNXT_VF(bp))
3489                 return 0;
3490
3491         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3492         req.port_id = bp->pf.port_id;
3493         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3494
3495         HWRM_CHECK_RESULT();
3496
3497         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3498                 unsigned int i;
3499
3500                 bp->num_leds = resp->num_leds;
3501                 memcpy(bp->leds, &resp->led0_id,
3502                         sizeof(bp->leds[0]) * bp->num_leds);
3503                 for (i = 0; i < bp->num_leds; i++) {
3504                         struct bnxt_led_info *led = &bp->leds[i];
3505
3506                         uint16_t caps = led->led_state_caps;
3507
3508                         if (!led->led_group_id ||
3509                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3510                                 bp->num_leds = 0;
3511                                 break;
3512                         }
3513                 }
3514         }
3515
3516         HWRM_UNLOCK();
3517
3518         return rc;
3519 }
3520
3521 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3522 {
3523         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3524         struct hwrm_port_led_cfg_input req = {0};
3525         struct bnxt_led_cfg *led_cfg;
3526         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3527         uint16_t duration = 0;
3528         int rc, i;
3529
3530         if (!bp->num_leds || BNXT_VF(bp))
3531                 return -EOPNOTSUPP;
3532
3533         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3534
3535         if (led_on) {
3536                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3537                 duration = rte_cpu_to_le_16(500);
3538         }
3539         req.port_id = bp->pf.port_id;
3540         req.num_leds = bp->num_leds;
3541         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3542         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3543                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3544                 led_cfg->led_id = bp->leds[i].led_id;
3545                 led_cfg->led_state = led_state;
3546                 led_cfg->led_blink_on = duration;
3547                 led_cfg->led_blink_off = duration;
3548                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3549         }
3550
3551         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3552
3553         HWRM_CHECK_RESULT();
3554         HWRM_UNLOCK();
3555
3556         return rc;
3557 }
3558
3559 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3560                                uint32_t *length)
3561 {
3562         int rc;
3563         struct hwrm_nvm_get_dir_info_input req = {0};
3564         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3565
3566         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3567
3568         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3569
3570         HWRM_CHECK_RESULT();
3571
3572         *entries = rte_le_to_cpu_32(resp->entries);
3573         *length = rte_le_to_cpu_32(resp->entry_length);
3574
3575         HWRM_UNLOCK();
3576         return rc;
3577 }
3578
3579 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3580 {
3581         int rc;
3582         uint32_t dir_entries;
3583         uint32_t entry_length;
3584         uint8_t *buf;
3585         size_t buflen;
3586         rte_iova_t dma_handle;
3587         struct hwrm_nvm_get_dir_entries_input req = {0};
3588         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3589
3590         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3591         if (rc != 0)
3592                 return rc;
3593
3594         *data++ = dir_entries;
3595         *data++ = entry_length;
3596         len -= 2;
3597         memset(data, 0xff, len);
3598
3599         buflen = dir_entries * entry_length;
3600         buf = rte_malloc("nvm_dir", buflen, 0);
3601         rte_mem_lock_page(buf);
3602         if (buf == NULL)
3603                 return -ENOMEM;
3604         dma_handle = rte_mem_virt2iova(buf);
3605         if (dma_handle == RTE_BAD_IOVA) {
3606                 PMD_DRV_LOG(ERR,
3607                         "unable to map response address to physical memory\n");
3608                 return -ENOMEM;
3609         }
3610         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3611         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3612         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3613
3614         if (rc == 0)
3615                 memcpy(data, buf, len > buflen ? buflen : len);
3616
3617         rte_free(buf);
3618         HWRM_CHECK_RESULT();
3619         HWRM_UNLOCK();
3620
3621         return rc;
3622 }
3623
3624 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3625                              uint32_t offset, uint32_t length,
3626                              uint8_t *data)
3627 {
3628         int rc;
3629         uint8_t *buf;
3630         rte_iova_t dma_handle;
3631         struct hwrm_nvm_read_input req = {0};
3632         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3633
3634         buf = rte_malloc("nvm_item", length, 0);
3635         rte_mem_lock_page(buf);
3636         if (!buf)
3637                 return -ENOMEM;
3638
3639         dma_handle = rte_mem_virt2iova(buf);
3640         if (dma_handle == RTE_BAD_IOVA) {
3641                 PMD_DRV_LOG(ERR,
3642                         "unable to map response address to physical memory\n");
3643                 return -ENOMEM;
3644         }
3645         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3646         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3647         req.dir_idx = rte_cpu_to_le_16(index);
3648         req.offset = rte_cpu_to_le_32(offset);
3649         req.len = rte_cpu_to_le_32(length);
3650         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3651         if (rc == 0)
3652                 memcpy(data, buf, length);
3653
3654         rte_free(buf);
3655         HWRM_CHECK_RESULT();
3656         HWRM_UNLOCK();
3657
3658         return rc;
3659 }
3660
3661 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3662 {
3663         int rc;
3664         struct hwrm_nvm_erase_dir_entry_input req = {0};
3665         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3666
3667         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3668         req.dir_idx = rte_cpu_to_le_16(index);
3669         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3670         HWRM_CHECK_RESULT();
3671         HWRM_UNLOCK();
3672
3673         return rc;
3674 }
3675
3676
3677 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3678                           uint16_t dir_ordinal, uint16_t dir_ext,
3679                           uint16_t dir_attr, const uint8_t *data,
3680                           size_t data_len)
3681 {
3682         int rc;
3683         struct hwrm_nvm_write_input req = {0};
3684         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3685         rte_iova_t dma_handle;
3686         uint8_t *buf;
3687
3688         buf = rte_malloc("nvm_write", data_len, 0);
3689         rte_mem_lock_page(buf);
3690         if (!buf)
3691                 return -ENOMEM;
3692
3693         dma_handle = rte_mem_virt2iova(buf);
3694         if (dma_handle == RTE_BAD_IOVA) {
3695                 PMD_DRV_LOG(ERR,
3696                         "unable to map response address to physical memory\n");
3697                 return -ENOMEM;
3698         }
3699         memcpy(buf, data, data_len);
3700
3701         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3702
3703         req.dir_type = rte_cpu_to_le_16(dir_type);
3704         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3705         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3706         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3707         req.dir_data_length = rte_cpu_to_le_32(data_len);
3708         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3709
3710         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3711
3712         rte_free(buf);
3713         HWRM_CHECK_RESULT();
3714         HWRM_UNLOCK();
3715
3716         return rc;
3717 }
3718
3719 static void
3720 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3721 {
3722         uint32_t *count = cbdata;
3723
3724         *count = *count + 1;
3725 }
3726
3727 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3728                                      struct bnxt_vnic_info *vnic __rte_unused)
3729 {
3730         return 0;
3731 }
3732
3733 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3734 {
3735         uint32_t count = 0;
3736
3737         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3738             &count, bnxt_vnic_count_hwrm_stub);
3739
3740         return count;
3741 }
3742
3743 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3744                                         uint16_t *vnic_ids)
3745 {
3746         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3747         struct hwrm_func_vf_vnic_ids_query_output *resp =
3748                                                 bp->hwrm_cmd_resp_addr;
3749         int rc;
3750
3751         /* First query all VNIC ids */
3752         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3753
3754         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3755         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3756         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3757
3758         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3759                 HWRM_UNLOCK();
3760                 PMD_DRV_LOG(ERR,
3761                 "unable to map VNIC ID table address to physical memory\n");
3762                 return -ENOMEM;
3763         }
3764         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3765         HWRM_CHECK_RESULT();
3766         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3767
3768         HWRM_UNLOCK();
3769
3770         return rc;
3771 }
3772
3773 /*
3774  * This function queries the VNIC IDs  for a specified VF. It then calls
3775  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3776  * Then it calls the hwrm_cb function to program this new vnic configuration.
3777  */
3778 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3779         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3780         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3781 {
3782         struct bnxt_vnic_info vnic;
3783         int rc = 0;
3784         int i, num_vnic_ids;
3785         uint16_t *vnic_ids;
3786         size_t vnic_id_sz;
3787         size_t sz;
3788
3789         /* First query all VNIC ids */
3790         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3791         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3792                         RTE_CACHE_LINE_SIZE);
3793         if (vnic_ids == NULL)
3794                 return -ENOMEM;
3795
3796         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3797                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3798
3799         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3800
3801         if (num_vnic_ids < 0)
3802                 return num_vnic_ids;
3803
3804         /* Retrieve VNIC, update bd_stall then update */
3805
3806         for (i = 0; i < num_vnic_ids; i++) {
3807                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3808                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3809                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3810                 if (rc)
3811                         break;
3812                 if (vnic.mru <= 4)      /* Indicates unallocated */
3813                         continue;
3814
3815                 vnic_cb(&vnic, cbdata);
3816
3817                 rc = hwrm_cb(bp, &vnic);
3818                 if (rc)
3819                         break;
3820         }
3821
3822         rte_free(vnic_ids);
3823
3824         return rc;
3825 }
3826
3827 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3828                                               bool on)
3829 {
3830         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3831         struct hwrm_func_cfg_input req = {0};
3832         int rc;
3833
3834         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3835
3836         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3837         req.enables |= rte_cpu_to_le_32(
3838                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3839         req.vlan_antispoof_mode = on ?
3840                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3841                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3842         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3843
3844         HWRM_CHECK_RESULT();
3845         HWRM_UNLOCK();
3846
3847         return rc;
3848 }
3849
3850 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3851 {
3852         struct bnxt_vnic_info vnic;
3853         uint16_t *vnic_ids;
3854         size_t vnic_id_sz;
3855         int num_vnic_ids, i;
3856         size_t sz;
3857         int rc;
3858
3859         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3860         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3861                         RTE_CACHE_LINE_SIZE);
3862         if (vnic_ids == NULL)
3863                 return -ENOMEM;
3864
3865         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3866                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3867
3868         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3869         if (rc <= 0)
3870                 goto exit;
3871         num_vnic_ids = rc;
3872
3873         /*
3874          * Loop through to find the default VNIC ID.
3875          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3876          * by sending the hwrm_func_qcfg command to the firmware.
3877          */
3878         for (i = 0; i < num_vnic_ids; i++) {
3879                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3880                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3881                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3882                                         bp->pf.first_vf_id + vf);
3883                 if (rc)
3884                         goto exit;
3885                 if (vnic.func_default) {
3886                         rte_free(vnic_ids);
3887                         return vnic.fw_vnic_id;
3888                 }
3889         }
3890         /* Could not find a default VNIC. */
3891         PMD_DRV_LOG(ERR, "No default VNIC\n");
3892 exit:
3893         rte_free(vnic_ids);
3894         return rc;
3895 }
3896
3897 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3898                          uint16_t dst_id,
3899                          struct bnxt_filter_info *filter)
3900 {
3901         int rc = 0;
3902         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3903         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3904         uint32_t enables = 0;
3905
3906         if (filter->fw_em_filter_id != UINT64_MAX)
3907                 bnxt_hwrm_clear_em_filter(bp, filter);
3908
3909         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3910
3911         req.flags = rte_cpu_to_le_32(filter->flags);
3912
3913         enables = filter->enables |
3914               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3915         req.dst_id = rte_cpu_to_le_16(dst_id);
3916
3917         if (filter->ip_addr_type) {
3918                 req.ip_addr_type = filter->ip_addr_type;
3919                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3920         }
3921         if (enables &
3922             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3923                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3924         if (enables &
3925             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3926                 memcpy(req.src_macaddr, filter->src_macaddr,
3927                        RTE_ETHER_ADDR_LEN);
3928         if (enables &
3929             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3930                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3931                        RTE_ETHER_ADDR_LEN);
3932         if (enables &
3933             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3934                 req.ovlan_vid = filter->l2_ovlan;
3935         if (enables &
3936             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3937                 req.ivlan_vid = filter->l2_ivlan;
3938         if (enables &
3939             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3940                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3941         if (enables &
3942             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3943                 req.ip_protocol = filter->ip_protocol;
3944         if (enables &
3945             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3946                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3947         if (enables &
3948             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3949                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3950         if (enables &
3951             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3952                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3953         if (enables &
3954             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3955                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3956         if (enables &
3957             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3958                 req.mirror_vnic_id = filter->mirror_vnic_id;
3959
3960         req.enables = rte_cpu_to_le_32(enables);
3961
3962         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3963
3964         HWRM_CHECK_RESULT();
3965
3966         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3967         HWRM_UNLOCK();
3968
3969         return rc;
3970 }
3971
3972 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3973 {
3974         int rc = 0;
3975         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3976         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3977
3978         if (filter->fw_em_filter_id == UINT64_MAX)
3979                 return 0;
3980
3981         PMD_DRV_LOG(ERR, "Clear EM filter\n");
3982         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
3983
3984         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3985
3986         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3987
3988         HWRM_CHECK_RESULT();
3989         HWRM_UNLOCK();
3990
3991         filter->fw_em_filter_id = UINT64_MAX;
3992         filter->fw_l2_filter_id = UINT64_MAX;
3993
3994         return 0;
3995 }
3996
3997 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3998                          uint16_t dst_id,
3999                          struct bnxt_filter_info *filter)
4000 {
4001         int rc = 0;
4002         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4003         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4004                                                 bp->hwrm_cmd_resp_addr;
4005         uint32_t enables = 0;
4006
4007         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4008                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4009
4010         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4011
4012         req.flags = rte_cpu_to_le_32(filter->flags);
4013
4014         enables = filter->enables |
4015               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4016         req.dst_id = rte_cpu_to_le_16(dst_id);
4017
4018
4019         if (filter->ip_addr_type) {
4020                 req.ip_addr_type = filter->ip_addr_type;
4021                 enables |=
4022                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4023         }
4024         if (enables &
4025             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4026                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4027         if (enables &
4028             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4029                 memcpy(req.src_macaddr, filter->src_macaddr,
4030                        RTE_ETHER_ADDR_LEN);
4031         //if (enables &
4032             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4033                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4034                        //RTE_ETHER_ADDR_LEN);
4035         if (enables &
4036             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4037                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4038         if (enables &
4039             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4040                 req.ip_protocol = filter->ip_protocol;
4041         if (enables &
4042             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4043                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4044         if (enables &
4045             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4046                 req.src_ipaddr_mask[0] =
4047                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4048         if (enables &
4049             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4050                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4051         if (enables &
4052             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4053                 req.dst_ipaddr_mask[0] =
4054                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4055         if (enables &
4056             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4057                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4058         if (enables &
4059             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4060                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4061         if (enables &
4062             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4063                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4064         if (enables &
4065             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4066                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4067         if (enables &
4068             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4069                 req.mirror_vnic_id = filter->mirror_vnic_id;
4070
4071         req.enables = rte_cpu_to_le_32(enables);
4072
4073         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4074
4075         HWRM_CHECK_RESULT();
4076
4077         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4078         HWRM_UNLOCK();
4079
4080         return rc;
4081 }
4082
4083 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4084                                 struct bnxt_filter_info *filter)
4085 {
4086         int rc = 0;
4087         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4088         struct hwrm_cfa_ntuple_filter_free_output *resp =
4089                                                 bp->hwrm_cmd_resp_addr;
4090
4091         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4092                 return 0;
4093
4094         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4095
4096         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4097
4098         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4099
4100         HWRM_CHECK_RESULT();
4101         HWRM_UNLOCK();
4102
4103         filter->fw_ntuple_filter_id = UINT64_MAX;
4104
4105         return 0;
4106 }
4107
4108 static int
4109 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4110 {
4111         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4112         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4113         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4114         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4115         uint16_t *ring_tbl = vnic->rss_table;
4116         int nr_ctxs = vnic->num_lb_ctxts;
4117         int max_rings = bp->rx_nr_rings;
4118         int i, j, k, cnt;
4119         int rc = 0;
4120
4121         for (i = 0, k = 0; i < nr_ctxs; i++) {
4122                 struct bnxt_rx_ring_info *rxr;
4123                 struct bnxt_cp_ring_info *cpr;
4124
4125                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4126
4127                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4128                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4129                 req.hash_mode_flags = vnic->hash_mode;
4130
4131                 req.ring_grp_tbl_addr =
4132                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4133                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4134                                      2 * sizeof(*ring_tbl));
4135                 req.hash_key_tbl_addr =
4136                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4137
4138                 req.ring_table_pair_index = i;
4139                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4140
4141                 for (j = 0; j < 64; j++) {
4142                         uint16_t ring_id;
4143
4144                         /* Find next active ring. */
4145                         for (cnt = 0; cnt < max_rings; cnt++) {
4146                                 if (rx_queue_state[k] !=
4147                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4148                                         break;
4149                                 if (++k == max_rings)
4150                                         k = 0;
4151                         }
4152
4153                         /* Return if no rings are active. */
4154                         if (cnt == max_rings)
4155                                 return 0;
4156
4157                         /* Add rx/cp ring pair to RSS table. */
4158                         rxr = rxqs[k]->rx_ring;
4159                         cpr = rxqs[k]->cp_ring;
4160
4161                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4162                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4163                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4164                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4165
4166                         if (++k == max_rings)
4167                                 k = 0;
4168                 }
4169                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4170                                             BNXT_USE_CHIMP_MB);
4171
4172                 HWRM_CHECK_RESULT();
4173                 HWRM_UNLOCK();
4174         }
4175
4176         return rc;
4177 }
4178
4179 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4180 {
4181         unsigned int rss_idx, fw_idx, i;
4182
4183         if (!(vnic->rss_table && vnic->hash_type))
4184                 return 0;
4185
4186         if (BNXT_CHIP_THOR(bp))
4187                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4188
4189         /*
4190          * Fill the RSS hash & redirection table with
4191          * ring group ids for all VNICs
4192          */
4193         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4194                 rss_idx++, fw_idx++) {
4195                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4196                         fw_idx %= bp->rx_cp_nr_rings;
4197                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4198                                 break;
4199                         fw_idx++;
4200                 }
4201                 if (i == bp->rx_cp_nr_rings)
4202                         return 0;
4203                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4204         }
4205         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4206 }
4207
4208 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4209         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4210 {
4211         uint16_t flags;
4212
4213         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4214
4215         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4216         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4217
4218         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4219         req->num_cmpl_dma_aggr_during_int =
4220                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4221
4222         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4223
4224         /* min timer set to 1/2 of interrupt timer */
4225         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4226
4227         /* buf timer set to 1/4 of interrupt timer */
4228         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4229
4230         req->cmpl_aggr_dma_tmr_during_int =
4231                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4232
4233         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4234                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4235         req->flags = rte_cpu_to_le_16(flags);
4236 }
4237
4238 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4239                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4240 {
4241         struct hwrm_ring_aggint_qcaps_input req = {0};
4242         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4243         uint32_t enables;
4244         uint16_t flags;
4245         int rc;
4246
4247         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4248         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4249         HWRM_CHECK_RESULT();
4250
4251         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4252         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4253
4254         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4255                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4256         agg_req->flags = rte_cpu_to_le_16(flags);
4257         enables =
4258          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4259          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4260         agg_req->enables = rte_cpu_to_le_32(enables);
4261
4262         HWRM_UNLOCK();
4263         return rc;
4264 }
4265
4266 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4267                         struct bnxt_coal *coal, uint16_t ring_id)
4268 {
4269         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4270         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4271                                                 bp->hwrm_cmd_resp_addr;
4272         int rc;
4273
4274         /* Set ring coalesce parameters only for 100G NICs */
4275         if (BNXT_CHIP_THOR(bp)) {
4276                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4277                         return -1;
4278         } else if (bnxt_stratus_device(bp)) {
4279                 bnxt_hwrm_set_coal_params(coal, &req);
4280         } else {
4281                 return 0;
4282         }
4283
4284         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4285         req.ring_id = rte_cpu_to_le_16(ring_id);
4286         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4287         HWRM_CHECK_RESULT();
4288         HWRM_UNLOCK();
4289         return 0;
4290 }
4291
4292 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4293 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4294 {
4295         struct hwrm_func_backing_store_qcaps_input req = {0};
4296         struct hwrm_func_backing_store_qcaps_output *resp =
4297                 bp->hwrm_cmd_resp_addr;
4298         int rc;
4299
4300         if (!BNXT_CHIP_THOR(bp) ||
4301             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4302             BNXT_VF(bp) ||
4303             bp->ctx)
4304                 return 0;
4305
4306         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4307         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4308         HWRM_CHECK_RESULT_SILENT();
4309
4310         if (!rc) {
4311                 struct bnxt_ctx_pg_info *ctx_pg;
4312                 struct bnxt_ctx_mem_info *ctx;
4313                 int total_alloc_len;
4314                 int i;
4315
4316                 total_alloc_len = sizeof(*ctx);
4317                 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4318                                  RTE_CACHE_LINE_SIZE);
4319                 if (!ctx) {
4320                         rc = -ENOMEM;
4321                         goto ctx_err;
4322                 }
4323                 memset(ctx, 0, total_alloc_len);
4324
4325                 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4326                                     sizeof(*ctx_pg) * BNXT_MAX_Q,
4327                                     RTE_CACHE_LINE_SIZE);
4328                 if (!ctx_pg) {
4329                         rc = -ENOMEM;
4330                         goto ctx_err;
4331                 }
4332                 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4333                         ctx->tqm_mem[i] = ctx_pg;
4334
4335                 bp->ctx = ctx;
4336                 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4337                 ctx->qp_min_qp1_entries =
4338                         rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4339                 ctx->qp_max_l2_entries =
4340                         rte_le_to_cpu_16(resp->qp_max_l2_entries);
4341                 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4342                 ctx->srq_max_l2_entries =
4343                         rte_le_to_cpu_16(resp->srq_max_l2_entries);
4344                 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4345                 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4346                 ctx->cq_max_l2_entries =
4347                         rte_le_to_cpu_16(resp->cq_max_l2_entries);
4348                 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4349                 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4350                 ctx->vnic_max_vnic_entries =
4351                         rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4352                 ctx->vnic_max_ring_table_entries =
4353                         rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4354                 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4355                 ctx->stat_max_entries =
4356                         rte_le_to_cpu_32(resp->stat_max_entries);
4357                 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4358                 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4359                 ctx->tqm_min_entries_per_ring =
4360                         rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4361                 ctx->tqm_max_entries_per_ring =
4362                         rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4363                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4364                 if (!ctx->tqm_entries_multiple)
4365                         ctx->tqm_entries_multiple = 1;
4366                 ctx->mrav_max_entries =
4367                         rte_le_to_cpu_32(resp->mrav_max_entries);
4368                 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4369                 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4370                 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4371         } else {
4372                 rc = 0;
4373         }
4374 ctx_err:
4375         HWRM_UNLOCK();
4376         return rc;
4377 }
4378
4379 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4380 {
4381         struct hwrm_func_backing_store_cfg_input req = {0};
4382         struct hwrm_func_backing_store_cfg_output *resp =
4383                 bp->hwrm_cmd_resp_addr;
4384         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4385         struct bnxt_ctx_pg_info *ctx_pg;
4386         uint32_t *num_entries;
4387         uint64_t *pg_dir;
4388         uint8_t *pg_attr;
4389         uint32_t ena;
4390         int i, rc;
4391
4392         if (!ctx)
4393                 return 0;
4394
4395         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4396         req.enables = rte_cpu_to_le_32(enables);
4397
4398         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4399                 ctx_pg = &ctx->qp_mem;
4400                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4401                 req.qp_num_qp1_entries =
4402                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4403                 req.qp_num_l2_entries =
4404                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4405                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4406                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4407                                       &req.qpc_pg_size_qpc_lvl,
4408                                       &req.qpc_page_dir);
4409         }
4410
4411         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4412                 ctx_pg = &ctx->srq_mem;
4413                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4414                 req.srq_num_l2_entries =
4415                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4416                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4417                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4418                                       &req.srq_pg_size_srq_lvl,
4419                                       &req.srq_page_dir);
4420         }
4421
4422         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4423                 ctx_pg = &ctx->cq_mem;
4424                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4425                 req.cq_num_l2_entries =
4426                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4427                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4428                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4429                                       &req.cq_pg_size_cq_lvl,
4430                                       &req.cq_page_dir);
4431         }
4432
4433         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4434                 ctx_pg = &ctx->vnic_mem;
4435                 req.vnic_num_vnic_entries =
4436                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4437                 req.vnic_num_ring_table_entries =
4438                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4439                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4440                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4441                                       &req.vnic_pg_size_vnic_lvl,
4442                                       &req.vnic_page_dir);
4443         }
4444
4445         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4446                 ctx_pg = &ctx->stat_mem;
4447                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4448                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4449                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4450                                       &req.stat_pg_size_stat_lvl,
4451                                       &req.stat_page_dir);
4452         }
4453
4454         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4455         num_entries = &req.tqm_sp_num_entries;
4456         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4457         pg_dir = &req.tqm_sp_page_dir;
4458         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4459         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4460                 if (!(enables & ena))
4461                         continue;
4462
4463                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4464
4465                 ctx_pg = ctx->tqm_mem[i];
4466                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4467                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4468         }
4469
4470         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4471         HWRM_CHECK_RESULT();
4472         HWRM_UNLOCK();
4473
4474         return rc;
4475 }
4476
4477 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4478 {
4479         struct hwrm_port_qstats_ext_input req = {0};
4480         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4481         struct bnxt_pf_info *pf = &bp->pf;
4482         int rc;
4483
4484         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4485               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4486                 return 0;
4487
4488         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4489
4490         req.port_id = rte_cpu_to_le_16(pf->port_id);
4491         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4492                 req.tx_stat_host_addr =
4493                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4494                 req.tx_stat_size =
4495                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4496         }
4497         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4498                 req.rx_stat_host_addr =
4499                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4500                 req.rx_stat_size =
4501                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4502         }
4503         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4504
4505         if (rc) {
4506                 bp->fw_rx_port_stats_ext_size = 0;
4507                 bp->fw_tx_port_stats_ext_size = 0;
4508         } else {
4509                 bp->fw_rx_port_stats_ext_size =
4510                         rte_le_to_cpu_16(resp->rx_stat_size);
4511                 bp->fw_tx_port_stats_ext_size =
4512                         rte_le_to_cpu_16(resp->tx_stat_size);
4513         }
4514
4515         HWRM_CHECK_RESULT();
4516         HWRM_UNLOCK();
4517
4518         return rc;
4519 }
4520
4521 int
4522 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4523 {
4524         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4525         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4526                 bp->hwrm_cmd_resp_addr;
4527         int rc = 0;
4528
4529         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4530         req.tunnel_type = type;
4531         req.dest_fid = bp->fw_fid;
4532         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4533         HWRM_CHECK_RESULT();
4534
4535         HWRM_UNLOCK();
4536
4537         return rc;
4538 }
4539
4540 int
4541 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4542 {
4543         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4544         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4545                 bp->hwrm_cmd_resp_addr;
4546         int rc = 0;
4547
4548         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4549         req.tunnel_type = type;
4550         req.dest_fid = bp->fw_fid;
4551         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4552         HWRM_CHECK_RESULT();
4553
4554         HWRM_UNLOCK();
4555
4556         return rc;
4557 }
4558
4559 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4560 {
4561         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4562         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4563                 bp->hwrm_cmd_resp_addr;
4564         int rc = 0;
4565
4566         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4567         req.src_fid = bp->fw_fid;
4568         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4569         HWRM_CHECK_RESULT();
4570
4571         if (type)
4572                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4573
4574         HWRM_UNLOCK();
4575
4576         return rc;
4577 }
4578
4579 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4580                                    uint16_t *dst_fid)
4581 {
4582         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4583         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4584                 bp->hwrm_cmd_resp_addr;
4585         int rc = 0;
4586
4587         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4588         req.src_fid = bp->fw_fid;
4589         req.tunnel_type = tun_type;
4590         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4591         HWRM_CHECK_RESULT();
4592
4593         if (dst_fid)
4594                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4595
4596         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4597
4598         HWRM_UNLOCK();
4599
4600         return rc;
4601 }
4602
4603 int bnxt_hwrm_set_mac(struct bnxt *bp)
4604 {
4605         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4606         struct hwrm_func_vf_cfg_input req = {0};
4607         int rc = 0;
4608
4609         if (!BNXT_VF(bp))
4610                 return 0;
4611
4612         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4613
4614         req.enables =
4615                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4616         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4617
4618         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4619
4620         HWRM_CHECK_RESULT();
4621
4622         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4623         HWRM_UNLOCK();
4624
4625         return rc;
4626 }