drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         timeout = bp->hwrm_cmd_timeout;
 104
 105         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 106             msg_len > bp->max_req_len) {
 107                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 108
 109                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 110                 memcpy(short_cmd_req, req, msg_len);
 111
 112                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 113                 short_input.signature = rte_cpu_to_le_16(
 114                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 115                 short_input.size = rte_cpu_to_le_16(msg_len);
 116                 short_input.req_addr =
 117                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 118
 119                 data = (uint32_t *)&short_input;
 120                 msg_len = sizeof(short_input);
 121
 122                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 123         }
 124
 125         /* Write request msg to hwrm channel */
 126         for (i = 0; i < msg_len; i += 4) {
 127                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 128                 rte_write32(*data, bar);
 129                 data++;
 130         }
 131
 132         /* Zero the rest of the request space */
 133         for (; i < max_req_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 135                 rte_write32(0, bar);
 136         }
 137
 138         /* Ring channel doorbell */
 139         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 140         rte_write32(1, bar);
 141         /*
 142          * Make sure the channel doorbell ring command complete before
 143          * reading the response to avoid getting stale or invalid
 144          * responses.
 145          */
 146         rte_io_mb();
 147
 148         /* Poll for the valid bit */
 149         for (i = 0; i < timeout; i++) {
 150                 /* Sanity check on the resp->resp_len */
 151                 rte_cio_rmb();
 152                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 153                         /* Last byte of resp contains the valid key */
 154                         valid = (uint8_t *)resp + resp->resp_len - 1;
 155                         if (*valid == HWRM_RESP_VALID_KEY)
 156                                 break;
 157                 }
 158                 rte_delay_us(1);
 159         }
 160
 161         if (i >= timeout) {
 162                 /* Suppress VER_GET timeout messages during reset recovery */
 163                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 164                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 165                         return -ETIMEDOUT;
 166
 167                 PMD_DRV_LOG(ERR,
 168                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 169                             req->req_type, req->seq_id);
 170                 return -ETIMEDOUT;
 171         }
 172         return 0;
 173 }
 174
 175 /*
 176  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 177  * spinlock, and does initial processing.
 178  *
 179  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 180  * releases the spinlock only if it returns. If the regular int return codes
 181  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 182  * directly, rather it should be copied and modified to suit the function.
 183  *
 184  * HWRM_UNLOCK() must be called after all response processing is completed.
 185  */
 186 #define HWRM_PREP(req, type, kong) do { \
 187         rte_spinlock_lock(&bp->hwrm_lock); \
 188         if (bp->hwrm_cmd_resp_addr == NULL) { \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 return -EACCES; \
 191         } \
 192         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 193         (req)->req_type = rte_cpu_to_le_16(type); \
 194         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 195         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 196                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 197         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 198         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 199 } while (0)
 200
 201 #define HWRM_CHECK_RESULT_SILENT() do {\
 202         if (rc) { \
 203                 rte_spinlock_unlock(&bp->hwrm_lock); \
 204                 return rc; \
 205         } \
 206         if (resp->error_code) { \
 207                 rc = rte_le_to_cpu_16(resp->error_code); \
 208                 rte_spinlock_unlock(&bp->hwrm_lock); \
 209                 return rc; \
 210         } \
 211 } while (0)
 212
 213 #define HWRM_CHECK_RESULT() do {\
 214         if (rc) { \
 215                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 216                 rte_spinlock_unlock(&bp->hwrm_lock); \
 217                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 218                         rc = -EACCES; \
 219                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 220                         rc = -ENOSPC; \
 221                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 222                         rc = -EINVAL; \
 223                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 224                         rc = -ENOTSUP; \
 225                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 226                         rc = -EAGAIN; \
 227                 else if (rc > 0) \
 228                         rc = -EIO; \
 229                 return rc; \
 230         } \
 231         if (resp->error_code) { \
 232                 rc = rte_le_to_cpu_16(resp->error_code); \
 233                 if (resp->resp_len >= 16) { \
 234                         struct hwrm_err_output *tmp_hwrm_err_op = \
 235                                                 (void *)resp; \
 236                         PMD_DRV_LOG(ERR, \
 237                                 "error %d:%d:%08x:%04x\n", \
 238                                 rc, tmp_hwrm_err_op->cmd_err, \
 239                                 rte_le_to_cpu_32(\
 240                                         tmp_hwrm_err_op->opaque_0), \
 241                                 rte_le_to_cpu_16(\
 242                                         tmp_hwrm_err_op->opaque_1)); \
 243                 } else { \
 244                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 245                 } \
 246                 rte_spinlock_unlock(&bp->hwrm_lock); \
 247                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 248                         rc = -EACCES; \
 249                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 250                         rc = -ENOSPC; \
 251                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 252                         rc = -EINVAL; \
 253                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 254                         rc = -ENOTSUP; \
 255                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 256                         rc = -EAGAIN; \
 257                 else if (rc > 0) \
 258                         rc = -EIO; \
 259                 return rc; \
 260         } \
 261 } while (0)
 262
 263 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 264
 265 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 266                                 bool use_kong_mb,
 267                                 uint16_t msg_type,
 268                                 void *msg,
 269                                 uint32_t msg_len,
 270                                 void *resp_msg,
 271                                 uint32_t resp_len)
 272 {
 273         int rc = 0;
 274         bool mailbox = BNXT_USE_CHIMP_MB;
 275         struct input *req = msg;
 276         struct output *resp = bp->hwrm_cmd_resp_addr;
 277
 278         if (use_kong_mb)
 279                 mailbox = BNXT_USE_KONG(bp);
 280
 281         HWRM_PREP(req, msg_type, mailbox);
 282
 283         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 284
 285         HWRM_CHECK_RESULT();
 286
 287         if (resp_msg)
 288                 memcpy(resp_msg, resp, resp_len);
 289
 290         HWRM_UNLOCK();
 291
 292         return rc;
 293 }
 294
 295 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 296                                   bool use_kong_mb,
 297                                   uint16_t tf_type,
 298                                   uint16_t tf_subtype,
 299                                   uint32_t *tf_response_code,
 300                                   void *msg,
 301                                   uint32_t msg_len,
 302                                   void *response,
 303                                   uint32_t response_len)
 304 {
 305         int rc = 0;
 306         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 307         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 308         bool mailbox = BNXT_USE_CHIMP_MB;
 309
 310         if (msg_len > sizeof(req.tf_req))
 311                 return -ENOMEM;
 312
 313         if (use_kong_mb)
 314                 mailbox = BNXT_USE_KONG(bp);
 315
 316         HWRM_PREP(&req, HWRM_TF, mailbox);
 317         /* Build request using the user supplied request payload.
 318          * TLV request size is checked at build time against HWRM
 319          * request max size, thus no checking required.
 320          */
 321         req.tf_type = tf_type;
 322         req.tf_subtype = tf_subtype;
 323         memcpy(req.tf_req, msg, msg_len);
 324
 325         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 326         HWRM_CHECK_RESULT();
 327
 328         /* Copy the resp to user provided response buffer */
 329         if (response != NULL)
 330                 /* Post process response data. We need to copy only
 331                  * the 'payload' as the HWRM data structure really is
 332                  * HWRM header + msg header + payload and the TFLIB
 333                  * only provided a payload place holder.
 334                  */
 335                 if (response_len != 0) {
 336                         memcpy(response,
 337                                resp->tf_resp,
 338                                response_len);
 339                 }
 340
 341         /* Extract the internal tflib response code */
 342         *tf_response_code = resp->tf_resp_code;
 343         HWRM_UNLOCK();
 344
 345         return rc;
 346 }
 347
 348 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 349 {
 350         int rc = 0;
 351         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 352         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 353
 354         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 355         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 356         req.mask = 0;
 357
 358         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 359
 360         HWRM_CHECK_RESULT();
 361         HWRM_UNLOCK();
 362
 363         return rc;
 364 }
 365
 366 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 367                                  struct bnxt_vnic_info *vnic,
 368                                  uint16_t vlan_count,
 369                                  struct bnxt_vlan_table_entry *vlan_table)
 370 {
 371         int rc = 0;
 372         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 373         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 374         uint32_t mask = 0;
 375
 376         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 377                 return rc;
 378
 379         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 380         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 381
 382         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 383                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 384         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 385                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 386
 387         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 388                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 389
 390         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 391                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 392         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 393                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 394                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 395                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 396         }
 397         if (vlan_table) {
 398                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 399                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 400                 req.vlan_tag_tbl_addr =
 401                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 402                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 403         }
 404         req.mask = rte_cpu_to_le_32(mask);
 405
 406         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 407
 408         HWRM_CHECK_RESULT();
 409         HWRM_UNLOCK();
 410
 411         return rc;
 412 }
 413
 414 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 415                         uint16_t vlan_count,
 416                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 417 {
 418         int rc = 0;
 419         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 420         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 421                                                 bp->hwrm_cmd_resp_addr;
 422
 423         /*
 424          * Older HWRM versions did not support this command, and the set_rx_mask
 425          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 426          * removed from set_rx_mask call, and this command was added.
 427          *
 428          * This command is also present from 1.7.8.11 and higher,
 429          * as well as 1.7.8.0
 430          */
 431         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 432                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 433                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 434                                         (11)))
 435                                 return 0;
 436                 }
 437         }
 438         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 439         req.fid = rte_cpu_to_le_16(fid);
 440
 441         req.vlan_tag_mask_tbl_addr =
 442                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 443         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 444
 445         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 446
 447         HWRM_CHECK_RESULT();
 448         HWRM_UNLOCK();
 449
 450         return rc;
 451 }
 452
 453 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 454                              struct bnxt_filter_info *filter)
 455 {
 456         int rc = 0;
 457         struct bnxt_filter_info *l2_filter = filter;
 458         struct bnxt_vnic_info *vnic = NULL;
 459         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 460         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 461
 462         if (filter->fw_l2_filter_id == UINT64_MAX)
 463                 return 0;
 464
 465         if (filter->matching_l2_fltr_ptr)
 466                 l2_filter = filter->matching_l2_fltr_ptr;
 467
 468         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 469                     filter, l2_filter, l2_filter->l2_ref_cnt);
 470
 471         if (l2_filter->l2_ref_cnt == 0)
 472                 return 0;
 473
 474         if (l2_filter->l2_ref_cnt > 0)
 475                 l2_filter->l2_ref_cnt--;
 476
 477         if (l2_filter->l2_ref_cnt > 0)
 478                 return 0;
 479
 480         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 481
 482         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 483
 484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 485
 486         HWRM_CHECK_RESULT();
 487         HWRM_UNLOCK();
 488
 489         filter->fw_l2_filter_id = UINT64_MAX;
 490         if (l2_filter->l2_ref_cnt == 0) {
 491                 vnic = l2_filter->vnic;
 492                 if (vnic) {
 493                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 494                                       bnxt_filter_info, next);
 495                         bnxt_free_filter(bp, l2_filter);
 496                 }
 497         }
 498
 499         return 0;
 500 }
 501
 502 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 503                          uint16_t dst_id,
 504                          struct bnxt_filter_info *filter)
 505 {
 506         int rc = 0;
 507         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 508         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 509         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 510         const struct rte_eth_vmdq_rx_conf *conf =
 511                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 512         uint32_t enables = 0;
 513         uint16_t j = dst_id - 1;
 514
 515         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 516         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 517             conf->pool_map[j].pools & (1UL << j)) {
 518                 PMD_DRV_LOG(DEBUG,
 519                         "Add vlan %u to vmdq pool %u\n",
 520                         conf->pool_map[j].vlan_id, j);
 521
 522                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 523                 filter->enables |=
 524                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 525                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 526         }
 527
 528         if (filter->fw_l2_filter_id != UINT64_MAX)
 529                 bnxt_hwrm_clear_l2_filter(bp, filter);
 530
 531         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 532
 533         req.flags = rte_cpu_to_le_32(filter->flags);
 534
 535         enables = filter->enables |
 536               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 537         req.dst_id = rte_cpu_to_le_16(dst_id);
 538
 539         if (enables &
 540             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 541                 memcpy(req.l2_addr, filter->l2_addr,
 542                        RTE_ETHER_ADDR_LEN);
 543         if (enables &
 544             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 545                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 546                        RTE_ETHER_ADDR_LEN);
 547         if (enables &
 548             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 549                 req.l2_ovlan = filter->l2_ovlan;
 550         if (enables &
 551             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 552                 req.l2_ivlan = filter->l2_ivlan;
 553         if (enables &
 554             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 555                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 556         if (enables &
 557             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 558                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 559         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 560                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 561         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 562                 req.src_type = filter->src_type;
 563         if (filter->pri_hint) {
 564                 req.pri_hint = filter->pri_hint;
 565                 req.l2_filter_id_hint =
 566                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 567         }
 568
 569         req.enables = rte_cpu_to_le_32(enables);
 570
 571         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 572
 573         HWRM_CHECK_RESULT();
 574
 575         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 576         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 577         HWRM_UNLOCK();
 578
 579         filter->l2_ref_cnt++;
 580
 581         return rc;
 582 }
 583
 584 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 585 {
 586         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 587         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 588         uint32_t flags = 0;
 589         int rc;
 590
 591         if (!ptp)
 592                 return 0;
 593
 594         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 595
 596         if (ptp->rx_filter)
 597                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 598         else
 599                 flags |=
 600                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 601         if (ptp->tx_tstamp_en)
 602                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 603         else
 604                 flags |=
 605                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 606         req.flags = rte_cpu_to_le_32(flags);
 607         req.enables = rte_cpu_to_le_32
 608                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 609         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 610
 611         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 612         HWRM_UNLOCK();
 613
 614         return rc;
 615 }
 616
 617 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 618 {
 619         int rc = 0;
 620         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 621         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 622         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 623
 624         if (ptp)
 625                 return 0;
 626
 627         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 628
 629         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 630
 631         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 632
 633         HWRM_CHECK_RESULT();
 634
 635         if (!BNXT_CHIP_THOR(bp) &&
 636             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 637                 return 0;
 638
 639         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 640                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 641
 642         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 643         if (!ptp)
 644                 return -ENOMEM;
 645
 646         if (!BNXT_CHIP_THOR(bp)) {
 647                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 648                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 649                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 650                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 651                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 652                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 653                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 654                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 655                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 656                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 657                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 658                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 659                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 660                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 661                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 662                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 663                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 664                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 665         }
 666
 667         ptp->bp = bp;
 668         bp->ptp_cfg = ptp;
 669
 670         return 0;
 671 }
 672
 673 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 674 {
 675         int rc = 0;
 676         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 677         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 678         uint16_t new_max_vfs;
 679         uint32_t flags;
 680         int i;
 681
 682         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 683
 684         req.fid = rte_cpu_to_le_16(0xffff);
 685
 686         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 687
 688         HWRM_CHECK_RESULT();
 689
 690         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 691         flags = rte_le_to_cpu_32(resp->flags);
 692         if (BNXT_PF(bp)) {
 693                 bp->pf->port_id = resp->port_id;
 694                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 695                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 696                 new_max_vfs = bp->pdev->max_vfs;
 697                 if (new_max_vfs != bp->pf->max_vfs) {
 698                         if (bp->pf->vf_info)
 699                                 rte_free(bp->pf->vf_info);
 700                         bp->pf->vf_info = rte_malloc("bnxt_vf_info",
 701                             sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
 702                         bp->pf->max_vfs = new_max_vfs;
 703                         for (i = 0; i < new_max_vfs; i++) {
 704                                 bp->pf->vf_info[i].fid =
 705                                         bp->pf->first_vf_id + i;
 706                                 bp->pf->vf_info[i].vlan_table =
 707                                         rte_zmalloc("VF VLAN table",
 708                                                     getpagesize(),
 709                                                     getpagesize());
 710                                 if (bp->pf->vf_info[i].vlan_table == NULL)
 711                                         PMD_DRV_LOG(ERR,
 712                                         "Fail to alloc VLAN table for VF %d\n",
 713                                         i);
 714                                 else
 715                                         rte_mem_lock_page(
 716                                                 bp->pf->vf_info[i].vlan_table);
 717                                 bp->pf->vf_info[i].vlan_as_table =
 718                                         rte_zmalloc("VF VLAN AS table",
 719                                                     getpagesize(),
 720                                                     getpagesize());
 721                                 if (bp->pf->vf_info[i].vlan_as_table == NULL)
 722                                         PMD_DRV_LOG(ERR,
 723                                         "Alloc VLAN AS table for VF %d fail\n",
 724                                         i);
 725                                 else
 726                                         rte_mem_lock_page(
 727                                               bp->pf->vf_info[i].vlan_as_table);
 728                                 STAILQ_INIT(&bp->pf->vf_info[i].filter);
 729                         }
 730                 }
 731         }
 732
 733         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 734         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 735                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 736                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 737         } else {
 738                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 739         }
 740         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 741         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 742         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 743         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 744         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 745         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 746         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 747         if (!BNXT_CHIP_THOR(bp))
 748                 bp->max_l2_ctx += bp->max_rx_em_flows;
 749         /* TODO: For now, do not support VMDq/RFS on VFs. */
 750         if (BNXT_PF(bp)) {
 751                 if (bp->pf->max_vfs)
 752                         bp->max_vnics = 1;
 753                 else
 754                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 755         } else {
 756                 bp->max_vnics = 1;
 757         }
 758         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 759                     bp->max_l2_ctx, bp->max_vnics);
 760         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 761         if (BNXT_PF(bp)) {
 762                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 763                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 764                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 765                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 766                         HWRM_UNLOCK();
 767                         bnxt_hwrm_ptp_qcfg(bp);
 768                 }
 769         }
 770
 771         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 772                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 773
 774         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 775                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 776                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 777         }
 778
 779         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 780                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 781
 782         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 783                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 784
 785         HWRM_UNLOCK();
 786
 787         return rc;
 788 }
 789
 790 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 791 {
 792         int rc;
 793
 794         rc = __bnxt_hwrm_func_qcaps(bp);
 795         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 796                 rc = bnxt_alloc_ctx_mem(bp);
 797                 if (rc)
 798                         return rc;
 799
 800                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 801                 if (!rc)
 802                         bp->flags |= BNXT_FLAG_NEW_RM;
 803         }
 804
 805         /* On older FW,
 806          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 807          * But the error can be ignored. Return success.
 808          */
 809
 810         return 0;
 811 }
 812
 813 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 814 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 815 {
 816         int rc = 0;
 817         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 818         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 819
 820         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 821
 822         req.target_id = rte_cpu_to_le_16(0xffff);
 823
 824         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 825
 826         HWRM_CHECK_RESULT();
 827
 828         if (rte_le_to_cpu_32(resp->flags) &
 829             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 830                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 831                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 832         }
 833
 834         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 835
 836         HWRM_UNLOCK();
 837
 838         return rc;
 839 }
 840
 841 int bnxt_hwrm_func_reset(struct bnxt *bp)
 842 {
 843         int rc = 0;
 844         struct hwrm_func_reset_input req = {.req_type = 0 };
 845         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 846
 847         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
 848
 849         req.enables = rte_cpu_to_le_32(0);
 850
 851         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 852
 853         HWRM_CHECK_RESULT();
 854         HWRM_UNLOCK();
 855
 856         return rc;
 857 }
 858
 859 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 860 {
 861         int rc;
 862         uint32_t flags = 0;
 863         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 864         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 865
 866         if (bp->flags & BNXT_FLAG_REGISTERED)
 867                 return 0;
 868
 869         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 870                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 871         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 872                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 873
 874         /* PFs and trusted VFs should indicate the support of the
 875          * Master capability on non Stingray platform
 876          */
 877         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 878                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 879
 880         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 881         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 882                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 883         req.ver_maj = RTE_VER_YEAR;
 884         req.ver_min = RTE_VER_MONTH;
 885         req.ver_upd = RTE_VER_MINOR;
 886
 887         if (BNXT_PF(bp)) {
 888                 req.enables |= rte_cpu_to_le_32(
 889                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 890                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
 891                        RTE_MIN(sizeof(req.vf_req_fwd),
 892                                sizeof(bp->pf->vf_req_fwd)));
 893
 894                 /*
 895                  * PF can sniff HWRM API issued by VF. This can be set up by
 896                  * linux driver and inherited by the DPDK PF driver. Clear
 897                  * this HWRM sniffer list in FW because DPDK PF driver does
 898                  * not support this.
 899                  */
 900                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 901         }
 902
 903         req.flags = rte_cpu_to_le_32(flags);
 904
 905         req.async_event_fwd[0] |=
 906                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 907                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 908                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 909                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 910                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 911         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 912                 req.async_event_fwd[0] |=
 913                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 914         req.async_event_fwd[1] |=
 915                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 916                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 917         if (BNXT_PF(bp))
 918                 req.async_event_fwd[1] |=
 919                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 920
 921         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 922
 923         HWRM_CHECK_RESULT();
 924
 925         flags = rte_le_to_cpu_32(resp->flags);
 926         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 927                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 928
 929         HWRM_UNLOCK();
 930
 931         bp->flags |= BNXT_FLAG_REGISTERED;
 932
 933         return rc;
 934 }
 935
 936 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 937 {
 938         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 939                 return 0;
 940
 941         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 942 }
 943
 944 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 945 {
 946         int rc;
 947         uint32_t flags = 0;
 948         uint32_t enables;
 949         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 950         struct hwrm_func_vf_cfg_input req = {0};
 951
 952         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 953
 954         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 955                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 956                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 957                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 958                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 959
 960         if (BNXT_HAS_RING_GRPS(bp)) {
 961                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 962                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 963         }
 964
 965         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 966         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 967                                             AGG_RING_MULTIPLIER);
 968         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 969         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 970                                               bp->tx_nr_rings +
 971                                               BNXT_NUM_ASYNC_CPR(bp));
 972         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 973         if (bp->vf_resv_strategy ==
 974             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 975                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 976                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 977                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 978                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 979                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 980                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 981         } else if (bp->vf_resv_strategy ==
 982                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 983                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 984                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 985         }
 986
 987         if (test)
 988                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 989                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 990                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 991                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 992                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 993                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 994
 995         if (test && BNXT_HAS_RING_GRPS(bp))
 996                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 997
 998         req.flags = rte_cpu_to_le_32(flags);
 999         req.enables |= rte_cpu_to_le_32(enables);
1000
1001         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1002
1003         if (test)
1004                 HWRM_CHECK_RESULT_SILENT();
1005         else
1006                 HWRM_CHECK_RESULT();
1007
1008         HWRM_UNLOCK();
1009         return rc;
1010 }
1011
1012 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1013 {
1014         int rc;
1015         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1016         struct hwrm_func_resource_qcaps_input req = {0};
1017
1018         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1019         req.fid = rte_cpu_to_le_16(0xffff);
1020
1021         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1022
1023         HWRM_CHECK_RESULT_SILENT();
1024
1025         if (BNXT_VF(bp)) {
1026                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1027                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1028                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1029                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1030                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1031                 /* func_resource_qcaps does not return max_rx_em_flows.
1032                  * So use the value provided by func_qcaps.
1033                  */
1034                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1035                 if (!BNXT_CHIP_THOR(bp))
1036                         bp->max_l2_ctx += bp->max_rx_em_flows;
1037                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1038                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1039         }
1040         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1041         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1042         if (bp->vf_resv_strategy >
1043             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1044                 bp->vf_resv_strategy =
1045                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1046
1047         HWRM_UNLOCK();
1048         return rc;
1049 }
1050
1051 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1052 {
1053         int rc = 0;
1054         struct hwrm_ver_get_input req = {.req_type = 0 };
1055         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1056         uint32_t fw_version;
1057         uint16_t max_resp_len;
1058         char type[RTE_MEMZONE_NAMESIZE];
1059         uint32_t dev_caps_cfg;
1060
1061         bp->max_req_len = HWRM_MAX_REQ_LEN;
1062         bp->hwrm_cmd_timeout = timeout;
1063         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1064
1065         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1066         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1067         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1068
1069         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1070
1071         if (bp->flags & BNXT_FLAG_FW_RESET)
1072                 HWRM_CHECK_RESULT_SILENT();
1073         else
1074                 HWRM_CHECK_RESULT();
1075
1076         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1077                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1078                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1079                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1080         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1081                      (resp->hwrm_fw_min_8b << 16) |
1082                      (resp->hwrm_fw_bld_8b << 8) |
1083                      resp->hwrm_fw_rsvd_8b;
1084         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1085                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1086
1087         fw_version = resp->hwrm_intf_maj_8b << 16;
1088         fw_version |= resp->hwrm_intf_min_8b << 8;
1089         fw_version |= resp->hwrm_intf_upd_8b;
1090         bp->hwrm_spec_code = fw_version;
1091
1092         /* def_req_timeout value is in milliseconds */
1093         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1094         /* convert timeout to usec */
1095         bp->hwrm_cmd_timeout *= 1000;
1096         if (!bp->hwrm_cmd_timeout)
1097                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1098
1099         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1100                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1101                 rc = -EINVAL;
1102                 goto error;
1103         }
1104
1105         if (bp->max_req_len > resp->max_req_win_len) {
1106                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1107                 rc = -EINVAL;
1108         }
1109         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1110         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1111         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1112                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1113
1114         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1115         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1116
1117         if (bp->max_resp_len != max_resp_len) {
1118                 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1119                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1120                         bp->pdev->addr.devid, bp->pdev->addr.function);
1121
1122                 rte_free(bp->hwrm_cmd_resp_addr);
1123
1124                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1125                 if (bp->hwrm_cmd_resp_addr == NULL) {
1126                         rc = -ENOMEM;
1127                         goto error;
1128                 }
1129                 bp->hwrm_cmd_resp_dma_addr =
1130                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1131                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1132                         PMD_DRV_LOG(ERR,
1133                         "Unable to map response buffer to physical memory.\n");
1134                         rc = -ENOMEM;
1135                         goto error;
1136                 }
1137                 bp->max_resp_len = max_resp_len;
1138         }
1139
1140         if ((dev_caps_cfg &
1141                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1142             (dev_caps_cfg &
1143              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1144                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1145                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1146         }
1147
1148         if (((dev_caps_cfg &
1149               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1150              (dev_caps_cfg &
1151               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1152             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1153                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1154                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1155                         bp->pdev->addr.devid, bp->pdev->addr.function);
1156
1157                 rte_free(bp->hwrm_short_cmd_req_addr);
1158
1159                 bp->hwrm_short_cmd_req_addr =
1160                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1161                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1162                         rc = -ENOMEM;
1163                         goto error;
1164                 }
1165                 bp->hwrm_short_cmd_req_dma_addr =
1166                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1167                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1168                         rte_free(bp->hwrm_short_cmd_req_addr);
1169                         PMD_DRV_LOG(ERR,
1170                                 "Unable to map buffer to physical memory.\n");
1171                         rc = -ENOMEM;
1172                         goto error;
1173                 }
1174         }
1175         if (dev_caps_cfg &
1176             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1177                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1178                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1179         }
1180         if (dev_caps_cfg &
1181             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1182                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1183         if (dev_caps_cfg &
1184             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1185                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1186                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1187         }
1188
1189         if (dev_caps_cfg &
1190             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1191                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1192                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1193         }
1194
1195
1196 error:
1197         HWRM_UNLOCK();
1198         return rc;
1199 }
1200
1201 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1202 {
1203         int rc;
1204         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1205         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1206
1207         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1208                 return 0;
1209
1210         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1211         req.flags = flags;
1212
1213         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1214
1215         HWRM_CHECK_RESULT();
1216         HWRM_UNLOCK();
1217
1218         return rc;
1219 }
1220
1221 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1222 {
1223         int rc = 0;
1224         struct hwrm_port_phy_cfg_input req = {0};
1225         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1226         uint32_t enables = 0;
1227
1228         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1229
1230         if (conf->link_up) {
1231                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1232                 if (bp->link_info->auto_mode && conf->link_speed) {
1233                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1234                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1235                 }
1236
1237                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1238                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1239                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1240                 /*
1241                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1242                  * any auto mode, even "none".
1243                  */
1244                 if (!conf->link_speed) {
1245                         /* No speeds specified. Enable AutoNeg - all speeds */
1246                         req.auto_mode =
1247                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1248                 }
1249                 /* AutoNeg - Advertise speeds specified. */
1250                 if (conf->auto_link_speed_mask &&
1251                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1252                         req.auto_mode =
1253                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1254                         req.auto_link_speed_mask =
1255                                 conf->auto_link_speed_mask;
1256                         enables |=
1257                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1258                 }
1259
1260                 req.auto_duplex = conf->duplex;
1261                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1262                 req.auto_pause = conf->auto_pause;
1263                 req.force_pause = conf->force_pause;
1264                 /* Set force_pause if there is no auto or if there is a force */
1265                 if (req.auto_pause && !req.force_pause)
1266                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1267                 else
1268                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1269
1270                 req.enables = rte_cpu_to_le_32(enables);
1271         } else {
1272                 req.flags =
1273                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1274                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1275         }
1276
1277         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1278
1279         HWRM_CHECK_RESULT();
1280         HWRM_UNLOCK();
1281
1282         return rc;
1283 }
1284
1285 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1286                                    struct bnxt_link_info *link_info)
1287 {
1288         int rc = 0;
1289         struct hwrm_port_phy_qcfg_input req = {0};
1290         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1291
1292         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1293
1294         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1295
1296         HWRM_CHECK_RESULT();
1297
1298         link_info->phy_link_status = resp->link;
1299         link_info->link_up =
1300                 (link_info->phy_link_status ==
1301                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1302         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1303         link_info->duplex = resp->duplex_cfg;
1304         link_info->pause = resp->pause;
1305         link_info->auto_pause = resp->auto_pause;
1306         link_info->force_pause = resp->force_pause;
1307         link_info->auto_mode = resp->auto_mode;
1308         link_info->phy_type = resp->phy_type;
1309         link_info->media_type = resp->media_type;
1310
1311         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1312         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1313         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1314         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1315         link_info->phy_ver[0] = resp->phy_maj;
1316         link_info->phy_ver[1] = resp->phy_min;
1317         link_info->phy_ver[2] = resp->phy_bld;
1318
1319         HWRM_UNLOCK();
1320
1321         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1322         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1323         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1324         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1325         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1326                     link_info->auto_link_speed_mask);
1327         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1328                     link_info->force_link_speed);
1329
1330         return rc;
1331 }
1332
1333 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1334 {
1335         int i = 0;
1336
1337         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1338                 if (bp->tx_cos_queue[i].profile ==
1339                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1340                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1341                         return true;
1342                 }
1343         }
1344         return false;
1345 }
1346
1347 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1348 {
1349         int i = 0;
1350
1351         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1352                 if (bp->tx_cos_queue[i].profile !=
1353                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1354                     bp->tx_cos_queue[i].id !=
1355                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1356                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1357                         break;
1358                 }
1359         }
1360 }
1361
1362 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1363 {
1364         int rc = 0;
1365         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1366         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1367         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1368         int i;
1369
1370 get_rx_info:
1371         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1372
1373         req.flags = rte_cpu_to_le_32(dir);
1374         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1375         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1376             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1377                 req.drv_qmap_cap =
1378                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1379         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1380
1381         HWRM_CHECK_RESULT();
1382
1383         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1384                 GET_TX_QUEUE_INFO(0);
1385                 GET_TX_QUEUE_INFO(1);
1386                 GET_TX_QUEUE_INFO(2);
1387                 GET_TX_QUEUE_INFO(3);
1388                 GET_TX_QUEUE_INFO(4);
1389                 GET_TX_QUEUE_INFO(5);
1390                 GET_TX_QUEUE_INFO(6);
1391                 GET_TX_QUEUE_INFO(7);
1392         } else  {
1393                 GET_RX_QUEUE_INFO(0);
1394                 GET_RX_QUEUE_INFO(1);
1395                 GET_RX_QUEUE_INFO(2);
1396                 GET_RX_QUEUE_INFO(3);
1397                 GET_RX_QUEUE_INFO(4);
1398                 GET_RX_QUEUE_INFO(5);
1399                 GET_RX_QUEUE_INFO(6);
1400                 GET_RX_QUEUE_INFO(7);
1401         }
1402
1403         HWRM_UNLOCK();
1404
1405         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1406                 goto done;
1407
1408         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1409                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1410         } else {
1411                 int j;
1412
1413                 /* iterate and find the COSq profile to use for Tx */
1414                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1415                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1416                                 if (bp->tx_cos_queue[i].id != 0xff)
1417                                         bp->tx_cosq_id[j++] =
1418                                                 bp->tx_cos_queue[i].id;
1419                         }
1420                 } else {
1421                         /* When CoS classification is disabled, for normal NIC
1422                          * operations, ideally we should look to use LOSSY.
1423                          * If not found, fallback to the first valid profile
1424                          */
1425                         if (!bnxt_find_lossy_profile(bp))
1426                                 bnxt_find_first_valid_profile(bp);
1427
1428                 }
1429         }
1430
1431         bp->max_tc = resp->max_configurable_queues;
1432         bp->max_lltc = resp->max_configurable_lossless_queues;
1433         if (bp->max_tc > BNXT_MAX_QUEUE)
1434                 bp->max_tc = BNXT_MAX_QUEUE;
1435         bp->max_q = bp->max_tc;
1436
1437         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1438                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1439                 goto get_rx_info;
1440         }
1441
1442 done:
1443         return rc;
1444 }
1445
1446 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1447                          struct bnxt_ring *ring,
1448                          uint32_t ring_type, uint32_t map_index,
1449                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1450                          uint16_t tx_cosq_id)
1451 {
1452         int rc = 0;
1453         uint32_t enables = 0;
1454         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1455         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1456         struct rte_mempool *mb_pool;
1457         uint16_t rx_buf_size;
1458
1459         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1460
1461         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1462         req.fbo = rte_cpu_to_le_32(0);
1463         /* Association of ring index with doorbell index */
1464         req.logical_id = rte_cpu_to_le_16(map_index);
1465         req.length = rte_cpu_to_le_32(ring->ring_size);
1466
1467         switch (ring_type) {
1468         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1469                 req.ring_type = ring_type;
1470                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1471                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1472                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1473                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1474                         enables |=
1475                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1476                 break;
1477         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1478                 req.ring_type = ring_type;
1479                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1480                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1481                 if (BNXT_CHIP_THOR(bp)) {
1482                         mb_pool = bp->rx_queues[0]->mb_pool;
1483                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1484                                       RTE_PKTMBUF_HEADROOM;
1485                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1486                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1487                         enables |=
1488                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1489                 }
1490                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1491                         enables |=
1492                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1493                 break;
1494         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1495                 req.ring_type = ring_type;
1496                 if (BNXT_HAS_NQ(bp)) {
1497                         /* Association of cp ring with nq */
1498                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1499                         enables |=
1500                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1501                 }
1502                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1503                 break;
1504         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1505                 req.ring_type = ring_type;
1506                 req.page_size = BNXT_PAGE_SHFT;
1507                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1508                 break;
1509         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1510                 req.ring_type = ring_type;
1511                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1512
1513                 mb_pool = bp->rx_queues[0]->mb_pool;
1514                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1515                               RTE_PKTMBUF_HEADROOM;
1516                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1517                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1518
1519                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1520                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1521                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1522                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1523                 break;
1524         default:
1525                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1526                         ring_type);
1527                 HWRM_UNLOCK();
1528                 return -EINVAL;
1529         }
1530         req.enables = rte_cpu_to_le_32(enables);
1531
1532         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1533
1534         if (rc || resp->error_code) {
1535                 if (rc == 0 && resp->error_code)
1536                         rc = rte_le_to_cpu_16(resp->error_code);
1537                 switch (ring_type) {
1538                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1539                         PMD_DRV_LOG(ERR,
1540                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1541                         HWRM_UNLOCK();
1542                         return rc;
1543                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1544                         PMD_DRV_LOG(ERR,
1545                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1546                         HWRM_UNLOCK();
1547                         return rc;
1548                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1549                         PMD_DRV_LOG(ERR,
1550                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1551                                     rc);
1552                         HWRM_UNLOCK();
1553                         return rc;
1554                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1555                         PMD_DRV_LOG(ERR,
1556                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1557                         HWRM_UNLOCK();
1558                         return rc;
1559                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1560                         PMD_DRV_LOG(ERR,
1561                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1562                         HWRM_UNLOCK();
1563                         return rc;
1564                 default:
1565                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1566                         HWRM_UNLOCK();
1567                         return rc;
1568                 }
1569         }
1570
1571         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1572         HWRM_UNLOCK();
1573         return rc;
1574 }
1575
1576 int bnxt_hwrm_ring_free(struct bnxt *bp,
1577                         struct bnxt_ring *ring, uint32_t ring_type)
1578 {
1579         int rc;
1580         struct hwrm_ring_free_input req = {.req_type = 0 };
1581         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1582
1583         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1584
1585         req.ring_type = ring_type;
1586         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1587
1588         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1589
1590         if (rc || resp->error_code) {
1591                 if (rc == 0 && resp->error_code)
1592                         rc = rte_le_to_cpu_16(resp->error_code);
1593                 HWRM_UNLOCK();
1594
1595                 switch (ring_type) {
1596                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1597                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1598                                 rc);
1599                         return rc;
1600                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1601                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1602                                 rc);
1603                         return rc;
1604                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1605                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1606                                 rc);
1607                         return rc;
1608                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1609                         PMD_DRV_LOG(ERR,
1610                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1611                         return rc;
1612                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1613                         PMD_DRV_LOG(ERR,
1614                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1615                         return rc;
1616                 default:
1617                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1618                         return rc;
1619                 }
1620         }
1621         HWRM_UNLOCK();
1622         return 0;
1623 }
1624
1625 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1626 {
1627         int rc = 0;
1628         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1629         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1630
1631         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1632
1633         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1634         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1635         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1636         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1637
1638         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1639
1640         HWRM_CHECK_RESULT();
1641
1642         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1643
1644         HWRM_UNLOCK();
1645
1646         return rc;
1647 }
1648
1649 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1650 {
1651         int rc;
1652         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1653         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1654
1655         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1656
1657         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1658
1659         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1660
1661         HWRM_CHECK_RESULT();
1662         HWRM_UNLOCK();
1663
1664         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1665         return rc;
1666 }
1667
1668 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1669 {
1670         int rc = 0;
1671         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1672         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1673
1674         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1675                 return rc;
1676
1677         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1678
1679         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1680
1681         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1682
1683         HWRM_CHECK_RESULT();
1684         HWRM_UNLOCK();
1685
1686         return rc;
1687 }
1688
1689 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1690                                 unsigned int idx __rte_unused)
1691 {
1692         int rc;
1693         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1694         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1695
1696         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1697
1698         req.update_period_ms = rte_cpu_to_le_32(0);
1699
1700         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1701
1702         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1703
1704         HWRM_CHECK_RESULT();
1705
1706         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1707
1708         HWRM_UNLOCK();
1709
1710         return rc;
1711 }
1712
1713 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1714                                 unsigned int idx __rte_unused)
1715 {
1716         int rc;
1717         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1718         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1719
1720         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1721
1722         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1723
1724         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1725
1726         HWRM_CHECK_RESULT();
1727         HWRM_UNLOCK();
1728
1729         return rc;
1730 }
1731
1732 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1733 {
1734         int rc = 0, i, j;
1735         struct hwrm_vnic_alloc_input req = { 0 };
1736         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1737
1738         if (!BNXT_HAS_RING_GRPS(bp))
1739                 goto skip_ring_grps;
1740
1741         /* map ring groups to this vnic */
1742         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1743                 vnic->start_grp_id, vnic->end_grp_id);
1744         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1745                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1746
1747         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1748         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1749         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1750         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1751
1752 skip_ring_grps:
1753         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1754         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1755
1756         if (vnic->func_default)
1757                 req.flags =
1758                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1759         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1760
1761         HWRM_CHECK_RESULT();
1762
1763         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1764         HWRM_UNLOCK();
1765         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1766         return rc;
1767 }
1768
1769 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1770                                         struct bnxt_vnic_info *vnic,
1771                                         struct bnxt_plcmodes_cfg *pmode)
1772 {
1773         int rc = 0;
1774         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1775         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1776
1777         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1778
1779         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1780
1781         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1782
1783         HWRM_CHECK_RESULT();
1784
1785         pmode->flags = rte_le_to_cpu_32(resp->flags);
1786         /* dflt_vnic bit doesn't exist in the _cfg command */
1787         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1788         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1789         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1790         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1791
1792         HWRM_UNLOCK();
1793
1794         return rc;
1795 }
1796
1797 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1798                                        struct bnxt_vnic_info *vnic,
1799                                        struct bnxt_plcmodes_cfg *pmode)
1800 {
1801         int rc = 0;
1802         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1803         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1804
1805         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1806                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1807                 return rc;
1808         }
1809
1810         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1811
1812         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1813         req.flags = rte_cpu_to_le_32(pmode->flags);
1814         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1815         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1816         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1817         req.enables = rte_cpu_to_le_32(
1818             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1819             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1820             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1821         );
1822
1823         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1824
1825         HWRM_CHECK_RESULT();
1826         HWRM_UNLOCK();
1827
1828         return rc;
1829 }
1830
1831 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1832 {
1833         int rc = 0;
1834         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1835         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1836         struct bnxt_plcmodes_cfg pmodes = { 0 };
1837         uint32_t ctx_enable_flag = 0;
1838         uint32_t enables = 0;
1839
1840         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1841                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1842                 return rc;
1843         }
1844
1845         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1846         if (rc)
1847                 return rc;
1848
1849         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1850
1851         if (BNXT_CHIP_THOR(bp)) {
1852                 int dflt_rxq = vnic->start_grp_id;
1853                 struct bnxt_rx_ring_info *rxr;
1854                 struct bnxt_cp_ring_info *cpr;
1855                 struct bnxt_rx_queue *rxq;
1856                 int i;
1857
1858                 /*
1859                  * The first active receive ring is used as the VNIC
1860                  * default receive ring. If there are no active receive
1861                  * rings (all corresponding receive queues are stopped),
1862                  * the first receive ring is used.
1863                  */
1864                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1865                         rxq = bp->eth_dev->data->rx_queues[i];
1866                         if (rxq->rx_started) {
1867                                 dflt_rxq = i;
1868                                 break;
1869                         }
1870                 }
1871
1872                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1873                 rxr = rxq->rx_ring;
1874                 cpr = rxq->cp_ring;
1875
1876                 req.default_rx_ring_id =
1877                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1878                 req.default_cmpl_ring_id =
1879                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1880                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1881                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1882                 goto config_mru;
1883         }
1884
1885         /* Only RSS support for now TBD: COS & LB */
1886         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1887         if (vnic->lb_rule != 0xffff)
1888                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1889         if (vnic->cos_rule != 0xffff)
1890                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1891         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1892                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1893                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1894         }
1895         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1896                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1897                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1898         }
1899
1900         enables |= ctx_enable_flag;
1901         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1902         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1903         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1904         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1905
1906 config_mru:
1907         req.enables = rte_cpu_to_le_32(enables);
1908         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1909         req.mru = rte_cpu_to_le_16(vnic->mru);
1910         /* Configure default VNIC only once. */
1911         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1912                 req.flags |=
1913                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1914                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1915         }
1916         if (vnic->vlan_strip)
1917                 req.flags |=
1918                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1919         if (vnic->bd_stall)
1920                 req.flags |=
1921                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1922         if (vnic->roce_dual)
1923                 req.flags |= rte_cpu_to_le_32(
1924                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1925         if (vnic->roce_only)
1926                 req.flags |= rte_cpu_to_le_32(
1927                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1928         if (vnic->rss_dflt_cr)
1929                 req.flags |= rte_cpu_to_le_32(
1930                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1931
1932         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1933
1934         HWRM_CHECK_RESULT();
1935         HWRM_UNLOCK();
1936
1937         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1938
1939         return rc;
1940 }
1941
1942 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1943                 int16_t fw_vf_id)
1944 {
1945         int rc = 0;
1946         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1947         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1948
1949         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1950                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1951                 return rc;
1952         }
1953         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
1954
1955         req.enables =
1956                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1957         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1958         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1959
1960         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1961
1962         HWRM_CHECK_RESULT();
1963
1964         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1965         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1966         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1967         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1968         vnic->mru = rte_le_to_cpu_16(resp->mru);
1969         vnic->func_default = rte_le_to_cpu_32(
1970                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1971         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1972                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1973         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1974                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1975         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1976                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1977         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1978                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1979         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1980                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1981
1982         HWRM_UNLOCK();
1983
1984         return rc;
1985 }
1986
1987 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1988                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1989 {
1990         int rc = 0;
1991         uint16_t ctx_id;
1992         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1993         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1994                                                 bp->hwrm_cmd_resp_addr;
1995
1996         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1997
1998         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1999         HWRM_CHECK_RESULT();
2000
2001         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2002         if (!BNXT_HAS_RING_GRPS(bp))
2003                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2004         else if (ctx_idx == 0)
2005                 vnic->rss_rule = ctx_id;
2006
2007         HWRM_UNLOCK();
2008
2009         return rc;
2010 }
2011
2012 static
2013 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2014                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2015 {
2016         int rc = 0;
2017         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2018         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2019                                                 bp->hwrm_cmd_resp_addr;
2020
2021         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2022                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2023                 return rc;
2024         }
2025         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2026
2027         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2028
2029         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2030
2031         HWRM_CHECK_RESULT();
2032         HWRM_UNLOCK();
2033
2034         return rc;
2035 }
2036
2037 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2038 {
2039         int rc = 0;
2040
2041         if (BNXT_CHIP_THOR(bp)) {
2042                 int j;
2043
2044                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2045                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2046                                                       vnic,
2047                                                       vnic->fw_grp_ids[j]);
2048                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2049                 }
2050                 vnic->num_lb_ctxts = 0;
2051         } else {
2052                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2053                 vnic->rss_rule = INVALID_HW_RING_ID;
2054         }
2055
2056         return rc;
2057 }
2058
2059 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2060 {
2061         int rc = 0;
2062         struct hwrm_vnic_free_input req = {.req_type = 0 };
2063         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2064
2065         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2066                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2067                 return rc;
2068         }
2069
2070         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2071
2072         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2073
2074         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2075
2076         HWRM_CHECK_RESULT();
2077         HWRM_UNLOCK();
2078
2079         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2080         /* Configure default VNIC again if necessary. */
2081         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2082                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2083
2084         return rc;
2085 }
2086
2087 static int
2088 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2089 {
2090         int i;
2091         int rc = 0;
2092         int nr_ctxs = vnic->num_lb_ctxts;
2093         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2094         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2095
2096         for (i = 0; i < nr_ctxs; i++) {
2097                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2098
2099                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2100                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2101                 req.hash_mode_flags = vnic->hash_mode;
2102
2103                 req.hash_key_tbl_addr =
2104                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2105
2106                 req.ring_grp_tbl_addr =
2107                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2108                                          i * HW_HASH_INDEX_SIZE);
2109                 req.ring_table_pair_index = i;
2110                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2111
2112                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2113                                             BNXT_USE_CHIMP_MB);
2114
2115                 HWRM_CHECK_RESULT();
2116                 HWRM_UNLOCK();
2117         }
2118
2119         return rc;
2120 }
2121
2122 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2123                            struct bnxt_vnic_info *vnic)
2124 {
2125         int rc = 0;
2126         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2127         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2128
2129         if (!vnic->rss_table)
2130                 return 0;
2131
2132         if (BNXT_CHIP_THOR(bp))
2133                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2134
2135         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2136
2137         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2138         req.hash_mode_flags = vnic->hash_mode;
2139
2140         req.ring_grp_tbl_addr =
2141             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2142         req.hash_key_tbl_addr =
2143             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2144         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2145         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2146
2147         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2148
2149         HWRM_CHECK_RESULT();
2150         HWRM_UNLOCK();
2151
2152         return rc;
2153 }
2154
2155 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2156                         struct bnxt_vnic_info *vnic)
2157 {
2158         int rc = 0;
2159         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2160         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2161         uint16_t size;
2162
2163         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2164                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2165                 return rc;
2166         }
2167
2168         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2169
2170         req.flags = rte_cpu_to_le_32(
2171                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2172
2173         req.enables = rte_cpu_to_le_32(
2174                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2175
2176         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2177         size -= RTE_PKTMBUF_HEADROOM;
2178         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2179
2180         req.jumbo_thresh = rte_cpu_to_le_16(size);
2181         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2182
2183         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2184
2185         HWRM_CHECK_RESULT();
2186         HWRM_UNLOCK();
2187
2188         return rc;
2189 }
2190
2191 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2192                         struct bnxt_vnic_info *vnic, bool enable)
2193 {
2194         int rc = 0;
2195         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2196         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2197
2198         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2199                 if (enable)
2200                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2201                 return -ENOTSUP;
2202         }
2203
2204         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2205                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2206                 return 0;
2207         }
2208
2209         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2210
2211         if (enable) {
2212                 req.enables = rte_cpu_to_le_32(
2213                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2214                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2215                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2216                 req.flags = rte_cpu_to_le_32(
2217                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2218                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2219                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2220                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2221                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2222                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2223                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2224                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2225                 req.min_agg_len = rte_cpu_to_le_32(512);
2226         }
2227         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2228
2229         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2230
2231         HWRM_CHECK_RESULT();
2232         HWRM_UNLOCK();
2233
2234         return rc;
2235 }
2236
2237 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2238 {
2239         struct hwrm_func_cfg_input req = {0};
2240         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2241         int rc;
2242
2243         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2244         req.enables = rte_cpu_to_le_32(
2245                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2246         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2247         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2248
2249         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2250
2251         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2252         HWRM_CHECK_RESULT();
2253         HWRM_UNLOCK();
2254
2255         bp->pf->vf_info[vf].random_mac = false;
2256
2257         return rc;
2258 }
2259
2260 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2261                                   uint64_t *dropped)
2262 {
2263         int rc = 0;
2264         struct hwrm_func_qstats_input req = {.req_type = 0};
2265         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2266
2267         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2268
2269         req.fid = rte_cpu_to_le_16(fid);
2270
2271         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2272
2273         HWRM_CHECK_RESULT();
2274
2275         if (dropped)
2276                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2277
2278         HWRM_UNLOCK();
2279
2280         return rc;
2281 }
2282
2283 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2284                           struct rte_eth_stats *stats,
2285                           struct hwrm_func_qstats_output *func_qstats)
2286 {
2287         int rc = 0;
2288         struct hwrm_func_qstats_input req = {.req_type = 0};
2289         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2290
2291         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2292
2293         req.fid = rte_cpu_to_le_16(fid);
2294
2295         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2296
2297         HWRM_CHECK_RESULT();
2298         if (func_qstats)
2299                 memcpy(func_qstats, resp,
2300                        sizeof(struct hwrm_func_qstats_output));
2301
2302         if (!stats)
2303                 goto exit;
2304
2305         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2306         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2307         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2308         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2309         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2310         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2311
2312         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2313         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2314         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2315         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2316         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2317         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2318
2319         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2320         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2321         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2322
2323 exit:
2324         HWRM_UNLOCK();
2325
2326         return rc;
2327 }
2328
2329 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2330 {
2331         int rc = 0;
2332         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2333         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2334
2335         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2336
2337         req.fid = rte_cpu_to_le_16(fid);
2338
2339         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2340
2341         HWRM_CHECK_RESULT();
2342         HWRM_UNLOCK();
2343
2344         return rc;
2345 }
2346
2347 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2348 {
2349         unsigned int i;
2350         int rc = 0;
2351
2352         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2353                 struct bnxt_tx_queue *txq;
2354                 struct bnxt_rx_queue *rxq;
2355                 struct bnxt_cp_ring_info *cpr;
2356
2357                 if (i >= bp->rx_cp_nr_rings) {
2358                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2359                         cpr = txq->cp_ring;
2360                 } else {
2361                         rxq = bp->rx_queues[i];
2362                         cpr = rxq->cp_ring;
2363                 }
2364
2365                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2366                 if (rc)
2367                         return rc;
2368         }
2369         return 0;
2370 }
2371
2372 static int
2373 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2374 {
2375         int rc;
2376         unsigned int i;
2377         struct bnxt_cp_ring_info *cpr;
2378
2379         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2380
2381                 if (i >= bp->rx_cp_nr_rings) {
2382                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2383                 } else {
2384                         cpr = bp->rx_queues[i]->cp_ring;
2385                         if (BNXT_HAS_RING_GRPS(bp))
2386                                 bp->grp_info[i].fw_stats_ctx = -1;
2387                 }
2388                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2389                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2390                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2391                         if (rc)
2392                                 return rc;
2393                 }
2394         }
2395         return 0;
2396 }
2397
2398 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2399 {
2400         unsigned int i;
2401         int rc = 0;
2402
2403         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2404                 struct bnxt_tx_queue *txq;
2405                 struct bnxt_rx_queue *rxq;
2406                 struct bnxt_cp_ring_info *cpr;
2407
2408                 if (i >= bp->rx_cp_nr_rings) {
2409                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2410                         cpr = txq->cp_ring;
2411                 } else {
2412                         rxq = bp->rx_queues[i];
2413                         cpr = rxq->cp_ring;
2414                 }
2415
2416                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2417
2418                 if (rc)
2419                         return rc;
2420         }
2421         return rc;
2422 }
2423
2424 static int
2425 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2426 {
2427         uint16_t idx;
2428         uint32_t rc = 0;
2429
2430         if (!BNXT_HAS_RING_GRPS(bp))
2431                 return 0;
2432
2433         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2434
2435                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2436                         continue;
2437
2438                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2439
2440                 if (rc)
2441                         return rc;
2442         }
2443         return rc;
2444 }
2445
2446 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2447 {
2448         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2449
2450         bnxt_hwrm_ring_free(bp, cp_ring,
2451                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2452         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2453         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2454                                      sizeof(*cpr->cp_desc_ring));
2455         cpr->cp_raw_cons = 0;
2456         cpr->valid = 0;
2457 }
2458
2459 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2460 {
2461         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2462
2463         bnxt_hwrm_ring_free(bp, cp_ring,
2464                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2465         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2466         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2467                         sizeof(*cpr->cp_desc_ring));
2468         cpr->cp_raw_cons = 0;
2469         cpr->valid = 0;
2470 }
2471
2472 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2473 {
2474         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2475         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2476         struct bnxt_ring *ring = rxr->rx_ring_struct;
2477         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2478
2479         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2480                 bnxt_hwrm_ring_free(bp, ring,
2481                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2482                 ring->fw_ring_id = INVALID_HW_RING_ID;
2483                 if (BNXT_HAS_RING_GRPS(bp))
2484                         bp->grp_info[queue_index].rx_fw_ring_id =
2485                                                         INVALID_HW_RING_ID;
2486         }
2487         ring = rxr->ag_ring_struct;
2488         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2489                 bnxt_hwrm_ring_free(bp, ring,
2490                                     BNXT_CHIP_THOR(bp) ?
2491                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2492                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2493                 if (BNXT_HAS_RING_GRPS(bp))
2494                         bp->grp_info[queue_index].ag_fw_ring_id =
2495                                                         INVALID_HW_RING_ID;
2496         }
2497         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2498                 bnxt_free_cp_ring(bp, cpr);
2499
2500         if (BNXT_HAS_RING_GRPS(bp))
2501                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2502 }
2503
2504 static int
2505 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2506 {
2507         unsigned int i;
2508
2509         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2510                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2511                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2512                 struct bnxt_ring *ring = txr->tx_ring_struct;
2513                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2514
2515                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2516                         bnxt_hwrm_ring_free(bp, ring,
2517                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2518                         ring->fw_ring_id = INVALID_HW_RING_ID;
2519                         memset(txr->tx_desc_ring, 0,
2520                                         txr->tx_ring_struct->ring_size *
2521                                         sizeof(*txr->tx_desc_ring));
2522                         memset(txr->tx_buf_ring, 0,
2523                                         txr->tx_ring_struct->ring_size *
2524                                         sizeof(*txr->tx_buf_ring));
2525                         txr->tx_prod = 0;
2526                         txr->tx_cons = 0;
2527                 }
2528                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2529                         bnxt_free_cp_ring(bp, cpr);
2530                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2531                 }
2532         }
2533
2534         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2535                 bnxt_free_hwrm_rx_ring(bp, i);
2536
2537         return 0;
2538 }
2539
2540 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2541 {
2542         uint16_t i;
2543         uint32_t rc = 0;
2544
2545         if (!BNXT_HAS_RING_GRPS(bp))
2546                 return 0;
2547
2548         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2549                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2550                 if (rc)
2551                         return rc;
2552         }
2553         return rc;
2554 }
2555
2556 /*
2557  * HWRM utility functions
2558  */
2559
2560 void bnxt_free_hwrm_resources(struct bnxt *bp)
2561 {
2562         /* Release memzone */
2563         rte_free(bp->hwrm_cmd_resp_addr);
2564         rte_free(bp->hwrm_short_cmd_req_addr);
2565         bp->hwrm_cmd_resp_addr = NULL;
2566         bp->hwrm_short_cmd_req_addr = NULL;
2567         bp->hwrm_cmd_resp_dma_addr = 0;
2568         bp->hwrm_short_cmd_req_dma_addr = 0;
2569 }
2570
2571 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2572 {
2573         struct rte_pci_device *pdev = bp->pdev;
2574         char type[RTE_MEMZONE_NAMESIZE];
2575
2576         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2577                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2578         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2579         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2580         if (bp->hwrm_cmd_resp_addr == NULL)
2581                 return -ENOMEM;
2582         bp->hwrm_cmd_resp_dma_addr =
2583                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2584         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2585                 PMD_DRV_LOG(ERR,
2586                         "unable to map response address to physical memory\n");
2587                 return -ENOMEM;
2588         }
2589         rte_spinlock_init(&bp->hwrm_lock);
2590
2591         return 0;
2592 }
2593
2594 static int
2595 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2596 {
2597         struct bnxt_filter_info *filter;
2598         int rc = 0;
2599
2600         STAILQ_FOREACH(filter, &vnic->filter, next) {
2601                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2602                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2603                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2604                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2605                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2606                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2607                 bnxt_free_filter(bp, filter);
2608         }
2609         return rc;
2610 }
2611
2612 static int
2613 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2614 {
2615         struct bnxt_filter_info *filter;
2616         struct rte_flow *flow;
2617         int rc = 0;
2618
2619         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2620                 flow = STAILQ_FIRST(&vnic->flow_list);
2621                 filter = flow->filter;
2622                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2623                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2624                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2625                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2626                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2627                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2628
2629                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2630                 rte_free(flow);
2631         }
2632         return rc;
2633 }
2634
2635 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2636 {
2637         struct bnxt_filter_info *filter;
2638         int rc = 0;
2639
2640         STAILQ_FOREACH(filter, &vnic->filter, next) {
2641                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2642                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2643                                                      filter);
2644                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2645                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2646                                                          filter);
2647                 else
2648                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2649                                                      filter);
2650                 if (rc)
2651                         break;
2652         }
2653         return rc;
2654 }
2655
2656 static void
2657 bnxt_free_tunnel_ports(struct bnxt *bp)
2658 {
2659         if (bp->vxlan_port_cnt)
2660                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2661                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2662         bp->vxlan_port = 0;
2663         if (bp->geneve_port_cnt)
2664                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2665                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2666         bp->geneve_port = 0;
2667 }
2668
2669 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2670 {
2671         int i;
2672
2673         if (bp->vnic_info == NULL)
2674                 return;
2675
2676         /*
2677          * Cleanup VNICs in reverse order, to make sure the L2 filter
2678          * from vnic0 is last to be cleaned up.
2679          */
2680         for (i = bp->max_vnics - 1; i >= 0; i--) {
2681                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2682
2683                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2684                         continue;
2685
2686                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2687
2688                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2689
2690                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2691
2692                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2693
2694                 bnxt_hwrm_vnic_free(bp, vnic);
2695
2696                 rte_free(vnic->fw_grp_ids);
2697         }
2698         /* Ring resources */
2699         bnxt_free_all_hwrm_rings(bp);
2700         bnxt_free_all_hwrm_ring_grps(bp);
2701         bnxt_free_all_hwrm_stat_ctxs(bp);
2702         bnxt_free_tunnel_ports(bp);
2703 }
2704
2705 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2706 {
2707         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2708
2709         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2710                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2711
2712         switch (conf_link_speed) {
2713         case ETH_LINK_SPEED_10M_HD:
2714         case ETH_LINK_SPEED_100M_HD:
2715                 /* FALLTHROUGH */
2716                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2717         }
2718         return hw_link_duplex;
2719 }
2720
2721 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2722 {
2723         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2724 }
2725
2726 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2727 {
2728         uint16_t eth_link_speed = 0;
2729
2730         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2731                 return ETH_LINK_SPEED_AUTONEG;
2732
2733         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2734         case ETH_LINK_SPEED_100M:
2735         case ETH_LINK_SPEED_100M_HD:
2736                 /* FALLTHROUGH */
2737                 eth_link_speed =
2738                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2739                 break;
2740         case ETH_LINK_SPEED_1G:
2741                 eth_link_speed =
2742                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2743                 break;
2744         case ETH_LINK_SPEED_2_5G:
2745                 eth_link_speed =
2746                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2747                 break;
2748         case ETH_LINK_SPEED_10G:
2749                 eth_link_speed =
2750                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2751                 break;
2752         case ETH_LINK_SPEED_20G:
2753                 eth_link_speed =
2754                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2755                 break;
2756         case ETH_LINK_SPEED_25G:
2757                 eth_link_speed =
2758                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2759                 break;
2760         case ETH_LINK_SPEED_40G:
2761                 eth_link_speed =
2762                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2763                 break;
2764         case ETH_LINK_SPEED_50G:
2765                 eth_link_speed =
2766                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2767                 break;
2768         case ETH_LINK_SPEED_100G:
2769                 eth_link_speed =
2770                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2771                 break;
2772         case ETH_LINK_SPEED_200G:
2773                 eth_link_speed =
2774                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB;
2775                 break;
2776         default:
2777                 PMD_DRV_LOG(ERR,
2778                         "Unsupported link speed %d; default to AUTO\n",
2779                         conf_link_speed);
2780                 break;
2781         }
2782         return eth_link_speed;
2783 }
2784
2785 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2786                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2787                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2788                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2789                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2790
2791 static int bnxt_validate_link_speed(struct bnxt *bp)
2792 {
2793         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2794         uint16_t port_id = bp->eth_dev->data->port_id;
2795         uint32_t link_speed_capa;
2796         uint32_t one_speed;
2797
2798         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2799                 return 0;
2800
2801         link_speed_capa = bnxt_get_speed_capabilities(bp);
2802
2803         if (link_speed & ETH_LINK_SPEED_FIXED) {
2804                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2805
2806                 if (one_speed & (one_speed - 1)) {
2807                         PMD_DRV_LOG(ERR,
2808                                 "Invalid advertised speeds (%u) for port %u\n",
2809                                 link_speed, port_id);
2810                         return -EINVAL;
2811                 }
2812                 if ((one_speed & link_speed_capa) != one_speed) {
2813                         PMD_DRV_LOG(ERR,
2814                                 "Unsupported advertised speed (%u) for port %u\n",
2815                                 link_speed, port_id);
2816                         return -EINVAL;
2817                 }
2818         } else {
2819                 if (!(link_speed & link_speed_capa)) {
2820                         PMD_DRV_LOG(ERR,
2821                                 "Unsupported advertised speeds (%u) for port %u\n",
2822                                 link_speed, port_id);
2823                         return -EINVAL;
2824                 }
2825         }
2826         return 0;
2827 }
2828
2829 static uint16_t
2830 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2831 {
2832         uint16_t ret = 0;
2833
2834         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2835                 if (bp->link_info->support_speeds)
2836                         return bp->link_info->support_speeds;
2837                 link_speed = BNXT_SUPPORTED_SPEEDS;
2838         }
2839
2840         if (link_speed & ETH_LINK_SPEED_100M)
2841                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2842         if (link_speed & ETH_LINK_SPEED_100M_HD)
2843                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2844         if (link_speed & ETH_LINK_SPEED_1G)
2845                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2846         if (link_speed & ETH_LINK_SPEED_2_5G)
2847                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2848         if (link_speed & ETH_LINK_SPEED_10G)
2849                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2850         if (link_speed & ETH_LINK_SPEED_20G)
2851                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2852         if (link_speed & ETH_LINK_SPEED_25G)
2853                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2854         if (link_speed & ETH_LINK_SPEED_40G)
2855                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2856         if (link_speed & ETH_LINK_SPEED_50G)
2857                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2858         if (link_speed & ETH_LINK_SPEED_100G)
2859                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2860         if (link_speed & ETH_LINK_SPEED_200G)
2861                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB;
2862         return ret;
2863 }
2864
2865 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2866 {
2867         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2868
2869         switch (hw_link_speed) {
2870         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2871                 eth_link_speed = ETH_SPEED_NUM_100M;
2872                 break;
2873         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2874                 eth_link_speed = ETH_SPEED_NUM_1G;
2875                 break;
2876         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2877                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2878                 break;
2879         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2880                 eth_link_speed = ETH_SPEED_NUM_10G;
2881                 break;
2882         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2883                 eth_link_speed = ETH_SPEED_NUM_20G;
2884                 break;
2885         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2886                 eth_link_speed = ETH_SPEED_NUM_25G;
2887                 break;
2888         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2889                 eth_link_speed = ETH_SPEED_NUM_40G;
2890                 break;
2891         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2892                 eth_link_speed = ETH_SPEED_NUM_50G;
2893                 break;
2894         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2895                 eth_link_speed = ETH_SPEED_NUM_100G;
2896                 break;
2897         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
2898                 eth_link_speed = ETH_SPEED_NUM_200G;
2899                 break;
2900         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2901         default:
2902                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2903                         hw_link_speed);
2904                 break;
2905         }
2906         return eth_link_speed;
2907 }
2908
2909 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2910 {
2911         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2912
2913         switch (hw_link_duplex) {
2914         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2915         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2916                 /* FALLTHROUGH */
2917                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2918                 break;
2919         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2920                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2921                 break;
2922         default:
2923                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2924                         hw_link_duplex);
2925                 break;
2926         }
2927         return eth_link_duplex;
2928 }
2929
2930 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2931 {
2932         int rc = 0;
2933         struct bnxt_link_info *link_info = bp->link_info;
2934
2935         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2936         if (rc) {
2937                 PMD_DRV_LOG(ERR,
2938                         "Get link config failed with rc %d\n", rc);
2939                 goto exit;
2940         }
2941         if (link_info->link_speed)
2942                 link->link_speed =
2943                         bnxt_parse_hw_link_speed(link_info->link_speed);
2944         else
2945                 link->link_speed = ETH_SPEED_NUM_NONE;
2946         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2947         link->link_status = link_info->link_up;
2948         link->link_autoneg = link_info->auto_mode ==
2949                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2950                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2951 exit:
2952         return rc;
2953 }
2954
2955 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2956 {
2957         int rc = 0;
2958         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2959         struct bnxt_link_info link_req;
2960         uint16_t speed, autoneg;
2961
2962         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2963                 return 0;
2964
2965         rc = bnxt_validate_link_speed(bp);
2966         if (rc)
2967                 goto error;
2968
2969         memset(&link_req, 0, sizeof(link_req));
2970         link_req.link_up = link_up;
2971         if (!link_up)
2972                 goto port_phy_cfg;
2973
2974         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2975         if (BNXT_CHIP_THOR(bp) &&
2976             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2977                 /* 40G is not supported as part of media auto detect.
2978                  * The speed should be forced and autoneg disabled
2979                  * to configure 40G speed.
2980                  */
2981                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2982                 autoneg = 0;
2983         }
2984
2985         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2986         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2987         /* Autoneg can be done only when the FW allows.
2988          * When user configures fixed speed of 40G and later changes to
2989          * any other speed, auto_link_speed/force_link_speed is still set
2990          * to 40G until link comes up at new speed.
2991          */
2992         if (autoneg == 1 &&
2993             !(!BNXT_CHIP_THOR(bp) &&
2994               (bp->link_info->auto_link_speed ||
2995                bp->link_info->force_link_speed))) {
2996                 link_req.phy_flags |=
2997                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2998                 link_req.auto_link_speed_mask =
2999                         bnxt_parse_eth_link_speed_mask(bp,
3000                                                        dev_conf->link_speeds);
3001         } else {
3002                 if (bp->link_info->phy_type ==
3003                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3004                     bp->link_info->phy_type ==
3005                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3006                     bp->link_info->media_type ==
3007                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3008                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3009                         return -EINVAL;
3010                 }
3011
3012                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3013                 /* If user wants a particular speed try that first. */
3014                 if (speed)
3015                         link_req.link_speed = speed;
3016                 else if (bp->link_info->force_link_speed)
3017                         link_req.link_speed = bp->link_info->force_link_speed;
3018                 else
3019                         link_req.link_speed = bp->link_info->auto_link_speed;
3020         }
3021         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3022         link_req.auto_pause = bp->link_info->auto_pause;
3023         link_req.force_pause = bp->link_info->force_pause;
3024
3025 port_phy_cfg:
3026         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3027         if (rc) {
3028                 PMD_DRV_LOG(ERR,
3029                         "Set link config failed with rc %d\n", rc);
3030         }
3031
3032 error:
3033         return rc;
3034 }
3035
3036 /* JIRA 22088 */
3037 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3038 {
3039         struct hwrm_func_qcfg_input req = {0};
3040         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3041         uint16_t flags;
3042         int rc = 0;
3043         bp->func_svif = BNXT_SVIF_INVALID;
3044         uint16_t svif_info;
3045
3046         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3047         req.fid = rte_cpu_to_le_16(0xffff);
3048
3049         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3050
3051         HWRM_CHECK_RESULT();
3052
3053         /* Hard Coded.. 0xfff VLAN ID mask */
3054         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3055
3056         svif_info = rte_le_to_cpu_16(resp->svif_info);
3057         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3058                 bp->func_svif = svif_info &
3059                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3060
3061         flags = rte_le_to_cpu_16(resp->flags);
3062         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3063                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3064
3065         if (BNXT_VF(bp) &&
3066             !BNXT_VF_IS_TRUSTED(bp) &&
3067             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3068                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3069                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3070         } else if (BNXT_VF(bp) &&
3071                    BNXT_VF_IS_TRUSTED(bp) &&
3072                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3073                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3074                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3075         }
3076
3077         if (mtu)
3078                 *mtu = rte_le_to_cpu_16(resp->mtu);
3079
3080         switch (resp->port_partition_type) {
3081         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3082         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3083         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3084                 /* FALLTHROUGH */
3085                 bp->flags |= BNXT_FLAG_NPAR_PF;
3086                 break;
3087         default:
3088                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3089                 break;
3090         }
3091
3092         HWRM_UNLOCK();
3093
3094         return rc;
3095 }
3096
3097 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3098 {
3099         struct hwrm_func_qcfg_input req = {0};
3100         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3101         int rc;
3102
3103         if (!BNXT_VF_IS_TRUSTED(bp))
3104                 return 0;
3105
3106         if (!bp->parent)
3107                 return -EINVAL;
3108
3109         bp->parent->fid = BNXT_PF_FID_INVALID;
3110
3111         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3112
3113         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3114
3115         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3116
3117         HWRM_CHECK_RESULT();
3118
3119         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3120         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3121         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3122         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3123
3124         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3125         if (bp->parent->vnic == 0) {
3126                 PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
3127                 /* Use hard-coded values appropriate for current Wh+ fw. */
3128                 if (bp->parent->fid == 2)
3129                         bp->parent->vnic = 0x100;
3130                 else
3131                         bp->parent->vnic = 1;
3132         }
3133
3134         HWRM_UNLOCK();
3135
3136         return 0;
3137 }
3138
3139 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3140                                  uint16_t *vnic_id, uint16_t *svif)
3141 {
3142         struct hwrm_func_qcfg_input req = {0};
3143         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3144         uint16_t svif_info;
3145         int rc = 0;
3146
3147         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3148         req.fid = rte_cpu_to_le_16(fid);
3149
3150         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3151
3152         HWRM_CHECK_RESULT();
3153
3154         if (vnic_id)
3155                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3156
3157         svif_info = rte_le_to_cpu_16(resp->svif_info);
3158         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3159                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3160
3161         HWRM_UNLOCK();
3162
3163         return rc;
3164 }
3165
3166 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3167 {
3168         struct hwrm_port_mac_qcfg_input req = {0};
3169         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3170         uint16_t port_svif_info;
3171         int rc;
3172
3173         bp->port_svif = BNXT_SVIF_INVALID;
3174
3175         if (!BNXT_PF(bp))
3176                 return 0;
3177
3178         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3179
3180         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3181
3182         HWRM_CHECK_RESULT();
3183
3184         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3185         if (port_svif_info &
3186             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3187                 bp->port_svif = port_svif_info &
3188                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3189
3190         HWRM_UNLOCK();
3191
3192         return 0;
3193 }
3194
3195 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3196                                    struct hwrm_func_qcaps_output *qcaps)
3197 {
3198         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3199         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3200                sizeof(qcaps->mac_address));
3201         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3202         qcaps->max_rx_rings = fcfg->num_rx_rings;
3203         qcaps->max_tx_rings = fcfg->num_tx_rings;
3204         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3205         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3206         qcaps->max_vfs = 0;
3207         qcaps->first_vf_id = 0;
3208         qcaps->max_vnics = fcfg->num_vnics;
3209         qcaps->max_decap_records = 0;
3210         qcaps->max_encap_records = 0;
3211         qcaps->max_tx_wm_flows = 0;
3212         qcaps->max_tx_em_flows = 0;
3213         qcaps->max_rx_wm_flows = 0;
3214         qcaps->max_rx_em_flows = 0;
3215         qcaps->max_flow_id = 0;
3216         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3217         qcaps->max_sp_tx_rings = 0;
3218         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3219 }
3220
3221 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3222 {
3223         struct hwrm_func_cfg_input req = {0};
3224         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3225         uint32_t enables;
3226         int rc;
3227
3228         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3229                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3230                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3231                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3232                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3233                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3234                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3235                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3236                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3237
3238         if (BNXT_HAS_RING_GRPS(bp)) {
3239                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3240                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3241         } else if (BNXT_HAS_NQ(bp)) {
3242                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3243                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3244         }
3245
3246         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3247         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3248         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3249         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3250         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3251         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3252         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3253         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3254         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3255         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3256         req.fid = rte_cpu_to_le_16(0xffff);
3257         req.enables = rte_cpu_to_le_32(enables);
3258
3259         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3260
3261         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3262
3263         HWRM_CHECK_RESULT();
3264         HWRM_UNLOCK();
3265
3266         return rc;
3267 }
3268
3269 static void populate_vf_func_cfg_req(struct bnxt *bp,
3270                                      struct hwrm_func_cfg_input *req,
3271                                      int num_vfs)
3272 {
3273         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3274                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3275                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3276                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3277                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3278                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3279                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3280                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3281                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3282                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3283
3284         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3285                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3286                                     BNXT_NUM_VLANS);
3287         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3288         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3289                                                 (num_vfs + 1));
3290         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3291         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3292                                                (num_vfs + 1));
3293         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3294         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3295         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3296         /* TODO: For now, do not support VMDq/RFS on VFs. */
3297         req->num_vnics = rte_cpu_to_le_16(1);
3298         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3299                                                  (num_vfs + 1));
3300 }
3301
3302 static void add_random_mac_if_needed(struct bnxt *bp,
3303                                      struct hwrm_func_cfg_input *cfg_req,
3304                                      int vf)
3305 {
3306         struct rte_ether_addr mac;
3307
3308         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3309                 return;
3310
3311         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3312                 cfg_req->enables |=
3313                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3314                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3315                 bp->pf->vf_info[vf].random_mac = true;
3316         } else {
3317                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3318                         RTE_ETHER_ADDR_LEN);
3319         }
3320 }
3321
3322 static int reserve_resources_from_vf(struct bnxt *bp,
3323                                      struct hwrm_func_cfg_input *cfg_req,
3324                                      int vf)
3325 {
3326         struct hwrm_func_qcaps_input req = {0};
3327         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3328         int rc;
3329
3330         /* Get the actual allocated values now */
3331         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3332         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3333         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3334
3335         if (rc) {
3336                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3337                 copy_func_cfg_to_qcaps(cfg_req, resp);
3338         } else if (resp->error_code) {
3339                 rc = rte_le_to_cpu_16(resp->error_code);
3340                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3341                 copy_func_cfg_to_qcaps(cfg_req, resp);
3342         }
3343
3344         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3345         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3346         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3347         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3348         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3349         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3350         /*
3351          * TODO: While not supporting VMDq with VFs, max_vnics is always
3352          * forced to 1 in this case
3353          */
3354         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3355         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3356
3357         HWRM_UNLOCK();
3358
3359         return 0;
3360 }
3361
3362 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3363 {
3364         struct hwrm_func_qcfg_input req = {0};
3365         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3366         int rc;
3367
3368         /* Check for zero MAC address */
3369         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3370         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3371         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3372         HWRM_CHECK_RESULT();
3373         rc = rte_le_to_cpu_16(resp->vlan);
3374
3375         HWRM_UNLOCK();
3376
3377         return rc;
3378 }
3379
3380 static int update_pf_resource_max(struct bnxt *bp)
3381 {
3382         struct hwrm_func_qcfg_input req = {0};
3383         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3384         int rc;
3385
3386         /* And copy the allocated numbers into the pf struct */
3387         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3388         req.fid = rte_cpu_to_le_16(0xffff);
3389         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3390         HWRM_CHECK_RESULT();
3391
3392         /* Only TX ring value reflects actual allocation? TODO */
3393         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3394         bp->pf->evb_mode = resp->evb_mode;
3395
3396         HWRM_UNLOCK();
3397
3398         return rc;
3399 }
3400
3401 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3402 {
3403         int rc;
3404
3405         if (!BNXT_PF(bp)) {
3406                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3407                 return -EINVAL;
3408         }
3409
3410         rc = bnxt_hwrm_func_qcaps(bp);
3411         if (rc)
3412                 return rc;
3413
3414         bp->pf->func_cfg_flags &=
3415                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3416                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3417         bp->pf->func_cfg_flags |=
3418                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3419         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3420         rc = __bnxt_hwrm_func_qcaps(bp);
3421         return rc;
3422 }
3423
3424 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3425 {
3426         struct hwrm_func_cfg_input req = {0};
3427         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3428         int i;
3429         size_t sz;
3430         int rc = 0;
3431         size_t req_buf_sz;
3432
3433         if (!BNXT_PF(bp)) {
3434                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3435                 return -EINVAL;
3436         }
3437
3438         rc = bnxt_hwrm_func_qcaps(bp);
3439
3440         if (rc)
3441                 return rc;
3442
3443         bp->pf->active_vfs = num_vfs;
3444
3445         /*
3446          * First, configure the PF to only use one TX ring.  This ensures that
3447          * there are enough rings for all VFs.
3448          *
3449          * If we don't do this, when we call func_alloc() later, we will lock
3450          * extra rings to the PF that won't be available during func_cfg() of
3451          * the VFs.
3452          *
3453          * This has been fixed with firmware versions above 20.6.54
3454          */
3455         bp->pf->func_cfg_flags &=
3456                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3457                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3458         bp->pf->func_cfg_flags |=
3459                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3460         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3461         if (rc)
3462                 return rc;
3463
3464         /*
3465          * Now, create and register a buffer to hold forwarded VF requests
3466          */
3467         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3468         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3469                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3470         if (bp->pf->vf_req_buf == NULL) {
3471                 rc = -ENOMEM;
3472                 goto error_free;
3473         }
3474         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3475                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3476         for (i = 0; i < num_vfs; i++)
3477                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3478                                         (i * HWRM_MAX_REQ_LEN);
3479
3480         rc = bnxt_hwrm_func_buf_rgtr(bp);
3481         if (rc)
3482                 goto error_free;
3483
3484         populate_vf_func_cfg_req(bp, &req, num_vfs);
3485
3486         bp->pf->active_vfs = 0;
3487         for (i = 0; i < num_vfs; i++) {
3488                 add_random_mac_if_needed(bp, &req, i);
3489
3490                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3491                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3492                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3493                 rc = bnxt_hwrm_send_message(bp,
3494                                             &req,
3495                                             sizeof(req),
3496                                             BNXT_USE_CHIMP_MB);
3497
3498                 /* Clear enable flag for next pass */
3499                 req.enables &= ~rte_cpu_to_le_32(
3500                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3501
3502                 if (rc || resp->error_code) {
3503                         PMD_DRV_LOG(ERR,
3504                                 "Failed to initizlie VF %d\n", i);
3505                         PMD_DRV_LOG(ERR,
3506                                 "Not all VFs available. (%d, %d)\n",
3507                                 rc, resp->error_code);
3508                         HWRM_UNLOCK();
3509                         break;
3510                 }
3511
3512                 HWRM_UNLOCK();
3513
3514                 reserve_resources_from_vf(bp, &req, i);
3515                 bp->pf->active_vfs++;
3516                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3517         }
3518
3519         /*
3520          * Now configure the PF to use "the rest" of the resources
3521          * We're using STD_TX_RING_MODE here though which will limit the TX
3522          * rings.  This will allow QoS to function properly.  Not setting this
3523          * will cause PF rings to break bandwidth settings.
3524          */
3525         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3526         if (rc)
3527                 goto error_free;
3528
3529         rc = update_pf_resource_max(bp);
3530         if (rc)
3531                 goto error_free;
3532
3533         return rc;
3534
3535 error_free:
3536         bnxt_hwrm_func_buf_unrgtr(bp);
3537         return rc;
3538 }
3539
3540 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3541 {
3542         struct hwrm_func_cfg_input req = {0};
3543         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3544         int rc;
3545
3546         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3547
3548         req.fid = rte_cpu_to_le_16(0xffff);
3549         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3550         req.evb_mode = bp->pf->evb_mode;
3551
3552         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3553         HWRM_CHECK_RESULT();
3554         HWRM_UNLOCK();
3555
3556         return rc;
3557 }
3558
3559 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3560                                 uint8_t tunnel_type)
3561 {
3562         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3563         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3564         int rc = 0;
3565
3566         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3567         req.tunnel_type = tunnel_type;
3568         req.tunnel_dst_port_val = port;
3569         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3570         HWRM_CHECK_RESULT();
3571
3572         switch (tunnel_type) {
3573         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3574                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3575                 bp->vxlan_port = port;
3576                 break;
3577         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3578                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3579                 bp->geneve_port = port;
3580                 break;
3581         default:
3582                 break;
3583         }
3584
3585         HWRM_UNLOCK();
3586
3587         return rc;
3588 }
3589
3590 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3591                                 uint8_t tunnel_type)
3592 {
3593         struct hwrm_tunnel_dst_port_free_input req = {0};
3594         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3595         int rc = 0;
3596
3597         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3598
3599         req.tunnel_type = tunnel_type;
3600         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3601         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3602
3603         HWRM_CHECK_RESULT();
3604         HWRM_UNLOCK();
3605
3606         return rc;
3607 }
3608
3609 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3610                                         uint32_t flags)
3611 {
3612         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3613         struct hwrm_func_cfg_input req = {0};
3614         int rc;
3615
3616         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3617
3618         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3619         req.flags = rte_cpu_to_le_32(flags);
3620         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3621
3622         HWRM_CHECK_RESULT();
3623         HWRM_UNLOCK();
3624
3625         return rc;
3626 }
3627
3628 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3629 {
3630         uint32_t *flag = flagp;
3631
3632         vnic->flags = *flag;
3633 }
3634
3635 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3636 {
3637         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3638 }
3639
3640 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3641 {
3642         int rc = 0;
3643         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3644         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3645
3646         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3647
3648         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3649         req.req_buf_page_size = rte_cpu_to_le_16(
3650                          page_getenum(bp->pf->active_vfs * HWRM_MAX_REQ_LEN));
3651         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3652         req.req_buf_page_addr0 =
3653                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3654         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3655                 PMD_DRV_LOG(ERR,
3656                         "unable to map buffer address to physical memory\n");
3657                 return -ENOMEM;
3658         }
3659
3660         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3661
3662         HWRM_CHECK_RESULT();
3663         HWRM_UNLOCK();
3664
3665         return rc;
3666 }
3667
3668 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3669 {
3670         int rc = 0;
3671         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3672         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3673
3674         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3675                 return 0;
3676
3677         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3678
3679         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3680
3681         HWRM_CHECK_RESULT();
3682         HWRM_UNLOCK();
3683
3684         return rc;
3685 }
3686
3687 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3688 {
3689         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3690         struct hwrm_func_cfg_input req = {0};
3691         int rc;
3692
3693         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3694
3695         req.fid = rte_cpu_to_le_16(0xffff);
3696         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3697         req.enables = rte_cpu_to_le_32(
3698                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3699         req.async_event_cr = rte_cpu_to_le_16(
3700                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3701         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3702
3703         HWRM_CHECK_RESULT();
3704         HWRM_UNLOCK();
3705
3706         return rc;
3707 }
3708
3709 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3710 {
3711         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3712         struct hwrm_func_vf_cfg_input req = {0};
3713         int rc;
3714
3715         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3716
3717         req.enables = rte_cpu_to_le_32(
3718                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3719         req.async_event_cr = rte_cpu_to_le_16(
3720                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3721         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3722
3723         HWRM_CHECK_RESULT();
3724         HWRM_UNLOCK();
3725
3726         return rc;
3727 }
3728
3729 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3730 {
3731         struct hwrm_func_cfg_input req = {0};
3732         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3733         uint16_t dflt_vlan, fid;
3734         uint32_t func_cfg_flags;
3735         int rc = 0;
3736
3737         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3738
3739         if (is_vf) {
3740                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
3741                 fid = bp->pf->vf_info[vf].fid;
3742                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
3743         } else {
3744                 fid = rte_cpu_to_le_16(0xffff);
3745                 func_cfg_flags = bp->pf->func_cfg_flags;
3746                 dflt_vlan = bp->vlan;
3747         }
3748
3749         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3750         req.fid = rte_cpu_to_le_16(fid);
3751         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3752         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3753
3754         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3755
3756         HWRM_CHECK_RESULT();
3757         HWRM_UNLOCK();
3758
3759         return rc;
3760 }
3761
3762 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3763                         uint16_t max_bw, uint16_t enables)
3764 {
3765         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3766         struct hwrm_func_cfg_input req = {0};
3767         int rc;
3768
3769         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3770
3771         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3772         req.enables |= rte_cpu_to_le_32(enables);
3773         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3774         req.max_bw = rte_cpu_to_le_32(max_bw);
3775         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3776
3777         HWRM_CHECK_RESULT();
3778         HWRM_UNLOCK();
3779
3780         return rc;
3781 }
3782
3783 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3784 {
3785         struct hwrm_func_cfg_input req = {0};
3786         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3787         int rc = 0;
3788
3789         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3790
3791         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3792         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3793         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3794         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
3795
3796         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3797
3798         HWRM_CHECK_RESULT();
3799         HWRM_UNLOCK();
3800
3801         return rc;
3802 }
3803
3804 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3805 {
3806         int rc;
3807
3808         if (BNXT_PF(bp))
3809                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3810         else
3811                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3812
3813         return rc;
3814 }
3815
3816 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3817                               void *encaped, size_t ec_size)
3818 {
3819         int rc = 0;
3820         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3821         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3822
3823         if (ec_size > sizeof(req.encap_request))
3824                 return -1;
3825
3826         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3827
3828         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3829         memcpy(req.encap_request, encaped, ec_size);
3830
3831         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3832
3833         HWRM_CHECK_RESULT();
3834         HWRM_UNLOCK();
3835
3836         return rc;
3837 }
3838
3839 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3840                                        struct rte_ether_addr *mac)
3841 {
3842         struct hwrm_func_qcfg_input req = {0};
3843         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3844         int rc;
3845
3846         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3847
3848         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3849         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3850
3851         HWRM_CHECK_RESULT();
3852
3853         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3854
3855         HWRM_UNLOCK();
3856
3857         return rc;
3858 }
3859
3860 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3861                             void *encaped, size_t ec_size)
3862 {
3863         int rc = 0;
3864         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3865         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3866
3867         if (ec_size > sizeof(req.encap_request))
3868                 return -1;
3869
3870         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3871
3872         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3873         memcpy(req.encap_request, encaped, ec_size);
3874
3875         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3876
3877         HWRM_CHECK_RESULT();
3878         HWRM_UNLOCK();
3879
3880         return rc;
3881 }
3882
3883 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3884                          struct rte_eth_stats *stats, uint8_t rx)
3885 {
3886         int rc = 0;
3887         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3888         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3889
3890         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3891
3892         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3893
3894         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3895
3896         HWRM_CHECK_RESULT();
3897
3898         if (rx) {
3899                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3900                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3901                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3902                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3903                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3904                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3905                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3906                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3907         } else {
3908                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3909                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3910                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3911                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3912                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3913                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3914         }
3915
3916         HWRM_UNLOCK();
3917
3918         return rc;
3919 }
3920
3921 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3922 {
3923         struct hwrm_port_qstats_input req = {0};
3924         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3925         struct bnxt_pf_info *pf = bp->pf;
3926         int rc;
3927
3928         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
3929
3930         req.port_id = rte_cpu_to_le_16(pf->port_id);
3931         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3932         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3933         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3934
3935         HWRM_CHECK_RESULT();
3936         HWRM_UNLOCK();
3937
3938         return rc;
3939 }
3940
3941 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3942 {
3943         struct hwrm_port_clr_stats_input req = {0};
3944         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3945         struct bnxt_pf_info *pf = bp->pf;
3946         int rc;
3947
3948         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3949         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3950             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3951                 return 0;
3952
3953         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3954
3955         req.port_id = rte_cpu_to_le_16(pf->port_id);
3956         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3957
3958         HWRM_CHECK_RESULT();
3959         HWRM_UNLOCK();
3960
3961         return rc;
3962 }
3963
3964 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3965 {
3966         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3967         struct hwrm_port_led_qcaps_input req = {0};
3968         int rc;
3969
3970         if (BNXT_VF(bp))
3971                 return 0;
3972
3973         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3974         req.port_id = bp->pf->port_id;
3975         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3976
3977         HWRM_CHECK_RESULT();
3978
3979         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3980                 unsigned int i;
3981
3982                 bp->leds->num_leds = resp->num_leds;
3983                 memcpy(bp->leds, &resp->led0_id,
3984                         sizeof(bp->leds[0]) * bp->leds->num_leds);
3985                 for (i = 0; i < bp->leds->num_leds; i++) {
3986                         struct bnxt_led_info *led = &bp->leds[i];
3987
3988                         uint16_t caps = led->led_state_caps;
3989
3990                         if (!led->led_group_id ||
3991                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3992                                 bp->leds->num_leds = 0;
3993                                 break;
3994                         }
3995                 }
3996         }
3997
3998         HWRM_UNLOCK();
3999
4000         return rc;
4001 }
4002
4003 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4004 {
4005         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4006         struct hwrm_port_led_cfg_input req = {0};
4007         struct bnxt_led_cfg *led_cfg;
4008         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4009         uint16_t duration = 0;
4010         int rc, i;
4011
4012         if (!bp->leds->num_leds || BNXT_VF(bp))
4013                 return -EOPNOTSUPP;
4014
4015         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4016
4017         if (led_on) {
4018                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4019                 duration = rte_cpu_to_le_16(500);
4020         }
4021         req.port_id = bp->pf->port_id;
4022         req.num_leds = bp->leds->num_leds;
4023         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4024         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4025                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4026                 led_cfg->led_id = bp->leds[i].led_id;
4027                 led_cfg->led_state = led_state;
4028                 led_cfg->led_blink_on = duration;
4029                 led_cfg->led_blink_off = duration;
4030                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4031         }
4032
4033         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4034
4035         HWRM_CHECK_RESULT();
4036         HWRM_UNLOCK();
4037
4038         return rc;
4039 }
4040
4041 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4042                                uint32_t *length)
4043 {
4044         int rc;
4045         struct hwrm_nvm_get_dir_info_input req = {0};
4046         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4047
4048         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4049
4050         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4051
4052         HWRM_CHECK_RESULT();
4053
4054         *entries = rte_le_to_cpu_32(resp->entries);
4055         *length = rte_le_to_cpu_32(resp->entry_length);
4056
4057         HWRM_UNLOCK();
4058         return rc;
4059 }
4060
4061 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4062 {
4063         int rc;
4064         uint32_t dir_entries;
4065         uint32_t entry_length;
4066         uint8_t *buf;
4067         size_t buflen;
4068         rte_iova_t dma_handle;
4069         struct hwrm_nvm_get_dir_entries_input req = {0};
4070         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4071
4072         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4073         if (rc != 0)
4074                 return rc;
4075
4076         *data++ = dir_entries;
4077         *data++ = entry_length;
4078         len -= 2;
4079         memset(data, 0xff, len);
4080
4081         buflen = dir_entries * entry_length;
4082         buf = rte_malloc("nvm_dir", buflen, 0);
4083         if (buf == NULL)
4084                 return -ENOMEM;
4085         dma_handle = rte_malloc_virt2iova(buf);
4086         if (dma_handle == RTE_BAD_IOVA) {
4087                 PMD_DRV_LOG(ERR,
4088                         "unable to map response address to physical memory\n");
4089                 return -ENOMEM;
4090         }
4091         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4092         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4093         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4094
4095         if (rc == 0)
4096                 memcpy(data, buf, len > buflen ? buflen : len);
4097
4098         rte_free(buf);
4099         HWRM_CHECK_RESULT();
4100         HWRM_UNLOCK();
4101
4102         return rc;
4103 }
4104
4105 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4106                              uint32_t offset, uint32_t length,
4107                              uint8_t *data)
4108 {
4109         int rc;
4110         uint8_t *buf;
4111         rte_iova_t dma_handle;
4112         struct hwrm_nvm_read_input req = {0};
4113         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4114
4115         buf = rte_malloc("nvm_item", length, 0);
4116         if (!buf)
4117                 return -ENOMEM;
4118
4119         dma_handle = rte_malloc_virt2iova(buf);
4120         if (dma_handle == RTE_BAD_IOVA) {
4121                 PMD_DRV_LOG(ERR,
4122                         "unable to map response address to physical memory\n");
4123                 return -ENOMEM;
4124         }
4125         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4126         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4127         req.dir_idx = rte_cpu_to_le_16(index);
4128         req.offset = rte_cpu_to_le_32(offset);
4129         req.len = rte_cpu_to_le_32(length);
4130         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4131         if (rc == 0)
4132                 memcpy(data, buf, length);
4133
4134         rte_free(buf);
4135         HWRM_CHECK_RESULT();
4136         HWRM_UNLOCK();
4137
4138         return rc;
4139 }
4140
4141 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4142 {
4143         int rc;
4144         struct hwrm_nvm_erase_dir_entry_input req = {0};
4145         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4146
4147         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4148         req.dir_idx = rte_cpu_to_le_16(index);
4149         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4150         HWRM_CHECK_RESULT();
4151         HWRM_UNLOCK();
4152
4153         return rc;
4154 }
4155
4156
4157 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4158                           uint16_t dir_ordinal, uint16_t dir_ext,
4159                           uint16_t dir_attr, const uint8_t *data,
4160                           size_t data_len)
4161 {
4162         int rc;
4163         struct hwrm_nvm_write_input req = {0};
4164         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4165         rte_iova_t dma_handle;
4166         uint8_t *buf;
4167
4168         buf = rte_malloc("nvm_write", data_len, 0);
4169         if (!buf)
4170                 return -ENOMEM;
4171
4172         dma_handle = rte_malloc_virt2iova(buf);
4173         if (dma_handle == RTE_BAD_IOVA) {
4174                 PMD_DRV_LOG(ERR,
4175                         "unable to map response address to physical memory\n");
4176                 return -ENOMEM;
4177         }
4178         memcpy(buf, data, data_len);
4179
4180         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4181
4182         req.dir_type = rte_cpu_to_le_16(dir_type);
4183         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4184         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4185         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4186         req.dir_data_length = rte_cpu_to_le_32(data_len);
4187         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4188
4189         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4190
4191         rte_free(buf);
4192         HWRM_CHECK_RESULT();
4193         HWRM_UNLOCK();
4194
4195         return rc;
4196 }
4197
4198 static void
4199 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4200 {
4201         uint32_t *count = cbdata;
4202
4203         *count = *count + 1;
4204 }
4205
4206 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4207                                      struct bnxt_vnic_info *vnic __rte_unused)
4208 {
4209         return 0;
4210 }
4211
4212 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4213 {
4214         uint32_t count = 0;
4215
4216         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4217             &count, bnxt_vnic_count_hwrm_stub);
4218
4219         return count;
4220 }
4221
4222 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4223                                         uint16_t *vnic_ids)
4224 {
4225         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4226         struct hwrm_func_vf_vnic_ids_query_output *resp =
4227                                                 bp->hwrm_cmd_resp_addr;
4228         int rc;
4229
4230         /* First query all VNIC ids */
4231         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4232
4233         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4234         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4235         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4236
4237         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4238                 HWRM_UNLOCK();
4239                 PMD_DRV_LOG(ERR,
4240                 "unable to map VNIC ID table address to physical memory\n");
4241                 return -ENOMEM;
4242         }
4243         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4244         HWRM_CHECK_RESULT();
4245         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4246
4247         HWRM_UNLOCK();
4248
4249         return rc;
4250 }
4251
4252 /*
4253  * This function queries the VNIC IDs  for a specified VF. It then calls
4254  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4255  * Then it calls the hwrm_cb function to program this new vnic configuration.
4256  */
4257 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4258         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4259         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4260 {
4261         struct bnxt_vnic_info vnic;
4262         int rc = 0;
4263         int i, num_vnic_ids;
4264         uint16_t *vnic_ids;
4265         size_t vnic_id_sz;
4266         size_t sz;
4267
4268         /* First query all VNIC ids */
4269         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4270         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4271                         RTE_CACHE_LINE_SIZE);
4272         if (vnic_ids == NULL)
4273                 return -ENOMEM;
4274
4275         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4276                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4277
4278         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4279
4280         if (num_vnic_ids < 0)
4281                 return num_vnic_ids;
4282
4283         /* Retrieve VNIC, update bd_stall then update */
4284
4285         for (i = 0; i < num_vnic_ids; i++) {
4286                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4287                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4288                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4289                 if (rc)
4290                         break;
4291                 if (vnic.mru <= 4)      /* Indicates unallocated */
4292                         continue;
4293
4294                 vnic_cb(&vnic, cbdata);
4295
4296                 rc = hwrm_cb(bp, &vnic);
4297                 if (rc)
4298                         break;
4299         }
4300
4301         rte_free(vnic_ids);
4302
4303         return rc;
4304 }
4305
4306 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4307                                               bool on)
4308 {
4309         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4310         struct hwrm_func_cfg_input req = {0};
4311         int rc;
4312
4313         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4314
4315         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4316         req.enables |= rte_cpu_to_le_32(
4317                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4318         req.vlan_antispoof_mode = on ?
4319                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4320                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4321         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4322
4323         HWRM_CHECK_RESULT();
4324         HWRM_UNLOCK();
4325
4326         return rc;
4327 }
4328
4329 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4330 {
4331         struct bnxt_vnic_info vnic;
4332         uint16_t *vnic_ids;
4333         size_t vnic_id_sz;
4334         int num_vnic_ids, i;
4335         size_t sz;
4336         int rc;
4337
4338         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4339         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4340                         RTE_CACHE_LINE_SIZE);
4341         if (vnic_ids == NULL)
4342                 return -ENOMEM;
4343
4344         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4345                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4346
4347         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4348         if (rc <= 0)
4349                 goto exit;
4350         num_vnic_ids = rc;
4351
4352         /*
4353          * Loop through to find the default VNIC ID.
4354          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4355          * by sending the hwrm_func_qcfg command to the firmware.
4356          */
4357         for (i = 0; i < num_vnic_ids; i++) {
4358                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4359                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4360                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4361                                         bp->pf->first_vf_id + vf);
4362                 if (rc)
4363                         goto exit;
4364                 if (vnic.func_default) {
4365                         rte_free(vnic_ids);
4366                         return vnic.fw_vnic_id;
4367                 }
4368         }
4369         /* Could not find a default VNIC. */
4370         PMD_DRV_LOG(ERR, "No default VNIC\n");
4371 exit:
4372         rte_free(vnic_ids);
4373         return rc;
4374 }
4375
4376 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4377                          uint16_t dst_id,
4378                          struct bnxt_filter_info *filter)
4379 {
4380         int rc = 0;
4381         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4382         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4383         uint32_t enables = 0;
4384
4385         if (filter->fw_em_filter_id != UINT64_MAX)
4386                 bnxt_hwrm_clear_em_filter(bp, filter);
4387
4388         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4389
4390         req.flags = rte_cpu_to_le_32(filter->flags);
4391
4392         enables = filter->enables |
4393               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4394         req.dst_id = rte_cpu_to_le_16(dst_id);
4395
4396         if (filter->ip_addr_type) {
4397                 req.ip_addr_type = filter->ip_addr_type;
4398                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4399         }
4400         if (enables &
4401             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4402                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4403         if (enables &
4404             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4405                 memcpy(req.src_macaddr, filter->src_macaddr,
4406                        RTE_ETHER_ADDR_LEN);
4407         if (enables &
4408             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4409                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4410                        RTE_ETHER_ADDR_LEN);
4411         if (enables &
4412             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4413                 req.ovlan_vid = filter->l2_ovlan;
4414         if (enables &
4415             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4416                 req.ivlan_vid = filter->l2_ivlan;
4417         if (enables &
4418             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4419                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4420         if (enables &
4421             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4422                 req.ip_protocol = filter->ip_protocol;
4423         if (enables &
4424             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4425                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4426         if (enables &
4427             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4428                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4429         if (enables &
4430             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4431                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4432         if (enables &
4433             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4434                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4435         if (enables &
4436             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4437                 req.mirror_vnic_id = filter->mirror_vnic_id;
4438
4439         req.enables = rte_cpu_to_le_32(enables);
4440
4441         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4442
4443         HWRM_CHECK_RESULT();
4444
4445         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4446         HWRM_UNLOCK();
4447
4448         return rc;
4449 }
4450
4451 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4452 {
4453         int rc = 0;
4454         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4455         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4456
4457         if (filter->fw_em_filter_id == UINT64_MAX)
4458                 return 0;
4459
4460         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4461
4462         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4463
4464         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4465
4466         HWRM_CHECK_RESULT();
4467         HWRM_UNLOCK();
4468
4469         filter->fw_em_filter_id = UINT64_MAX;
4470         filter->fw_l2_filter_id = UINT64_MAX;
4471
4472         return 0;
4473 }
4474
4475 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4476                          uint16_t dst_id,
4477                          struct bnxt_filter_info *filter)
4478 {
4479         int rc = 0;
4480         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4481         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4482                                                 bp->hwrm_cmd_resp_addr;
4483         uint32_t enables = 0;
4484
4485         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4486                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4487
4488         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4489
4490         req.flags = rte_cpu_to_le_32(filter->flags);
4491
4492         enables = filter->enables |
4493               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4494         req.dst_id = rte_cpu_to_le_16(dst_id);
4495
4496         if (filter->ip_addr_type) {
4497                 req.ip_addr_type = filter->ip_addr_type;
4498                 enables |=
4499                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4500         }
4501         if (enables &
4502             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4503                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4504         if (enables &
4505             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4506                 memcpy(req.src_macaddr, filter->src_macaddr,
4507                        RTE_ETHER_ADDR_LEN);
4508         if (enables &
4509             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4510                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4511         if (enables &
4512             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4513                 req.ip_protocol = filter->ip_protocol;
4514         if (enables &
4515             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4516                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4517         if (enables &
4518             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4519                 req.src_ipaddr_mask[0] =
4520                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4521         if (enables &
4522             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4523                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4524         if (enables &
4525             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4526                 req.dst_ipaddr_mask[0] =
4527                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4528         if (enables &
4529             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4530                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4531         if (enables &
4532             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4533                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4534         if (enables &
4535             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4536                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4537         if (enables &
4538             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4539                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4540         if (enables &
4541             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4542                 req.mirror_vnic_id = filter->mirror_vnic_id;
4543
4544         req.enables = rte_cpu_to_le_32(enables);
4545
4546         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4547
4548         HWRM_CHECK_RESULT();
4549
4550         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4551         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4552         HWRM_UNLOCK();
4553
4554         return rc;
4555 }
4556
4557 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4558                                 struct bnxt_filter_info *filter)
4559 {
4560         int rc = 0;
4561         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4562         struct hwrm_cfa_ntuple_filter_free_output *resp =
4563                                                 bp->hwrm_cmd_resp_addr;
4564
4565         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4566                 return 0;
4567
4568         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4569
4570         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4571
4572         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4573
4574         HWRM_CHECK_RESULT();
4575         HWRM_UNLOCK();
4576
4577         filter->fw_ntuple_filter_id = UINT64_MAX;
4578
4579         return 0;
4580 }
4581
4582 static int
4583 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4584 {
4585         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4586         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4587         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4588         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4589         uint16_t *ring_tbl = vnic->rss_table;
4590         int nr_ctxs = vnic->num_lb_ctxts;
4591         int max_rings = bp->rx_nr_rings;
4592         int i, j, k, cnt;
4593         int rc = 0;
4594
4595         for (i = 0, k = 0; i < nr_ctxs; i++) {
4596                 struct bnxt_rx_ring_info *rxr;
4597                 struct bnxt_cp_ring_info *cpr;
4598
4599                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4600
4601                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4602                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4603                 req.hash_mode_flags = vnic->hash_mode;
4604
4605                 req.ring_grp_tbl_addr =
4606                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4607                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4608                                      2 * sizeof(*ring_tbl));
4609                 req.hash_key_tbl_addr =
4610                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4611
4612                 req.ring_table_pair_index = i;
4613                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4614
4615                 for (j = 0; j < 64; j++) {
4616                         uint16_t ring_id;
4617
4618                         /* Find next active ring. */
4619                         for (cnt = 0; cnt < max_rings; cnt++) {
4620                                 if (rx_queue_state[k] !=
4621                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4622                                         break;
4623                                 if (++k == max_rings)
4624                                         k = 0;
4625                         }
4626
4627                         /* Return if no rings are active. */
4628                         if (cnt == max_rings) {
4629                                 HWRM_UNLOCK();
4630                                 return 0;
4631                         }
4632
4633                         /* Add rx/cp ring pair to RSS table. */
4634                         rxr = rxqs[k]->rx_ring;
4635                         cpr = rxqs[k]->cp_ring;
4636
4637                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4638                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4639                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4640                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4641
4642                         if (++k == max_rings)
4643                                 k = 0;
4644                 }
4645                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4646                                             BNXT_USE_CHIMP_MB);
4647
4648                 HWRM_CHECK_RESULT();
4649                 HWRM_UNLOCK();
4650         }
4651
4652         return rc;
4653 }
4654
4655 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4656 {
4657         unsigned int rss_idx, fw_idx, i;
4658
4659         if (!(vnic->rss_table && vnic->hash_type))
4660                 return 0;
4661
4662         if (BNXT_CHIP_THOR(bp))
4663                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4664
4665         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4666                 return 0;
4667
4668         if (vnic->rss_table && vnic->hash_type) {
4669                 /*
4670                  * Fill the RSS hash & redirection table with
4671                  * ring group ids for all VNICs
4672                  */
4673                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4674                         rss_idx++, fw_idx++) {
4675                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4676                                 fw_idx %= bp->rx_cp_nr_rings;
4677                                 if (vnic->fw_grp_ids[fw_idx] !=
4678                                     INVALID_HW_RING_ID)
4679                                         break;
4680                                 fw_idx++;
4681                         }
4682                         if (i == bp->rx_cp_nr_rings)
4683                                 return 0;
4684                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4685                 }
4686                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4687         }
4688
4689         return 0;
4690 }
4691
4692 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4693         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4694 {
4695         uint16_t flags;
4696
4697         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4698
4699         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4700         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4701
4702         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4703         req->num_cmpl_dma_aggr_during_int =
4704                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4705
4706         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4707
4708         /* min timer set to 1/2 of interrupt timer */
4709         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4710
4711         /* buf timer set to 1/4 of interrupt timer */
4712         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4713
4714         req->cmpl_aggr_dma_tmr_during_int =
4715                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4716
4717         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4718                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4719         req->flags = rte_cpu_to_le_16(flags);
4720 }
4721
4722 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4723                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4724 {
4725         struct hwrm_ring_aggint_qcaps_input req = {0};
4726         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4727         uint32_t enables;
4728         uint16_t flags;
4729         int rc;
4730
4731         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4732         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4733         HWRM_CHECK_RESULT();
4734
4735         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4736         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4737
4738         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4739                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4740         agg_req->flags = rte_cpu_to_le_16(flags);
4741         enables =
4742          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4743          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4744         agg_req->enables = rte_cpu_to_le_32(enables);
4745
4746         HWRM_UNLOCK();
4747         return rc;
4748 }
4749
4750 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4751                         struct bnxt_coal *coal, uint16_t ring_id)
4752 {
4753         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4754         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4755                                                 bp->hwrm_cmd_resp_addr;
4756         int rc;
4757
4758         /* Set ring coalesce parameters only for 100G NICs */
4759         if (BNXT_CHIP_THOR(bp)) {
4760                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4761                         return -1;
4762         } else if (bnxt_stratus_device(bp)) {
4763                 bnxt_hwrm_set_coal_params(coal, &req);
4764         } else {
4765                 return 0;
4766         }
4767
4768         HWRM_PREP(&req,
4769                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4770                   BNXT_USE_CHIMP_MB);
4771         req.ring_id = rte_cpu_to_le_16(ring_id);
4772         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4773         HWRM_CHECK_RESULT();
4774         HWRM_UNLOCK();
4775         return 0;
4776 }
4777
4778 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4779 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4780 {
4781         struct hwrm_func_backing_store_qcaps_input req = {0};
4782         struct hwrm_func_backing_store_qcaps_output *resp =
4783                 bp->hwrm_cmd_resp_addr;
4784         struct bnxt_ctx_pg_info *ctx_pg;
4785         struct bnxt_ctx_mem_info *ctx;
4786         int total_alloc_len;
4787         int rc, i, tqm_rings;
4788
4789         if (!BNXT_CHIP_THOR(bp) ||
4790             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4791             BNXT_VF(bp) ||
4792             bp->ctx)
4793                 return 0;
4794
4795         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4796         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4797         HWRM_CHECK_RESULT_SILENT();
4798
4799         total_alloc_len = sizeof(*ctx);
4800         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4801                           RTE_CACHE_LINE_SIZE);
4802         if (!ctx) {
4803                 rc = -ENOMEM;
4804                 goto ctx_err;
4805         }
4806
4807         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4808         ctx->qp_min_qp1_entries =
4809                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4810         ctx->qp_max_l2_entries =
4811                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4812         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4813         ctx->srq_max_l2_entries =
4814                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4815         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4816         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4817         ctx->cq_max_l2_entries =
4818                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4819         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4820         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4821         ctx->vnic_max_vnic_entries =
4822                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4823         ctx->vnic_max_ring_table_entries =
4824                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4825         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4826         ctx->stat_max_entries =
4827                 rte_le_to_cpu_32(resp->stat_max_entries);
4828         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4829         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4830         ctx->tqm_min_entries_per_ring =
4831                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4832         ctx->tqm_max_entries_per_ring =
4833                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4834         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4835         if (!ctx->tqm_entries_multiple)
4836                 ctx->tqm_entries_multiple = 1;
4837         ctx->mrav_max_entries =
4838                 rte_le_to_cpu_32(resp->mrav_max_entries);
4839         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4840         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4841         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4842         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
4843
4844         if (!ctx->tqm_fp_rings_count)
4845                 ctx->tqm_fp_rings_count = bp->max_q;
4846
4847         tqm_rings = ctx->tqm_fp_rings_count + 1;
4848
4849         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4850                             sizeof(*ctx_pg) * tqm_rings,
4851                             RTE_CACHE_LINE_SIZE);
4852         if (!ctx_pg) {
4853                 rc = -ENOMEM;
4854                 goto ctx_err;
4855         }
4856         for (i = 0; i < tqm_rings; i++, ctx_pg++)
4857                 ctx->tqm_mem[i] = ctx_pg;
4858
4859         bp->ctx = ctx;
4860 ctx_err:
4861         HWRM_UNLOCK();
4862         return rc;
4863 }
4864
4865 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4866 {
4867         struct hwrm_func_backing_store_cfg_input req = {0};
4868         struct hwrm_func_backing_store_cfg_output *resp =
4869                 bp->hwrm_cmd_resp_addr;
4870         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4871         struct bnxt_ctx_pg_info *ctx_pg;
4872         uint32_t *num_entries;
4873         uint64_t *pg_dir;
4874         uint8_t *pg_attr;
4875         uint32_t ena;
4876         int i, rc;
4877
4878         if (!ctx)
4879                 return 0;
4880
4881         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4882         req.enables = rte_cpu_to_le_32(enables);
4883
4884         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4885                 ctx_pg = &ctx->qp_mem;
4886                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4887                 req.qp_num_qp1_entries =
4888                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4889                 req.qp_num_l2_entries =
4890                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4891                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4892                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4893                                       &req.qpc_pg_size_qpc_lvl,
4894                                       &req.qpc_page_dir);
4895         }
4896
4897         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4898                 ctx_pg = &ctx->srq_mem;
4899                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4900                 req.srq_num_l2_entries =
4901                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4902                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4903                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4904                                       &req.srq_pg_size_srq_lvl,
4905                                       &req.srq_page_dir);
4906         }
4907
4908         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4909                 ctx_pg = &ctx->cq_mem;
4910                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4911                 req.cq_num_l2_entries =
4912                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4913                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4914                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4915                                       &req.cq_pg_size_cq_lvl,
4916                                       &req.cq_page_dir);
4917         }
4918
4919         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4920                 ctx_pg = &ctx->vnic_mem;
4921                 req.vnic_num_vnic_entries =
4922                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4923                 req.vnic_num_ring_table_entries =
4924                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4925                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4926                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4927                                       &req.vnic_pg_size_vnic_lvl,
4928                                       &req.vnic_page_dir);
4929         }
4930
4931         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4932                 ctx_pg = &ctx->stat_mem;
4933                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4934                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4935                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4936                                       &req.stat_pg_size_stat_lvl,
4937                                       &req.stat_page_dir);
4938         }
4939
4940         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4941         num_entries = &req.tqm_sp_num_entries;
4942         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4943         pg_dir = &req.tqm_sp_page_dir;
4944         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4945         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4946                 if (!(enables & ena))
4947                         continue;
4948
4949                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4950
4951                 ctx_pg = ctx->tqm_mem[i];
4952                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4953                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4954         }
4955
4956         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4957         HWRM_CHECK_RESULT();
4958         HWRM_UNLOCK();
4959
4960         return rc;
4961 }
4962
4963 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4964 {
4965         struct hwrm_port_qstats_ext_input req = {0};
4966         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4967         struct bnxt_pf_info *pf = bp->pf;
4968         int rc;
4969
4970         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4971               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4972                 return 0;
4973
4974         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4975
4976         req.port_id = rte_cpu_to_le_16(pf->port_id);
4977         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4978                 req.tx_stat_host_addr =
4979                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4980                 req.tx_stat_size =
4981                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4982         }
4983         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4984                 req.rx_stat_host_addr =
4985                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4986                 req.rx_stat_size =
4987                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4988         }
4989         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4990
4991         if (rc) {
4992                 bp->fw_rx_port_stats_ext_size = 0;
4993                 bp->fw_tx_port_stats_ext_size = 0;
4994         } else {
4995                 bp->fw_rx_port_stats_ext_size =
4996                         rte_le_to_cpu_16(resp->rx_stat_size);
4997                 bp->fw_tx_port_stats_ext_size =
4998                         rte_le_to_cpu_16(resp->tx_stat_size);
4999         }
5000
5001         HWRM_CHECK_RESULT();
5002         HWRM_UNLOCK();
5003
5004         return rc;
5005 }
5006
5007 int
5008 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5009 {
5010         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5011         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5012                 bp->hwrm_cmd_resp_addr;
5013         int rc = 0;
5014
5015         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5016         req.tunnel_type = type;
5017         req.dest_fid = bp->fw_fid;
5018         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5019         HWRM_CHECK_RESULT();
5020
5021         HWRM_UNLOCK();
5022
5023         return rc;
5024 }
5025
5026 int
5027 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5028 {
5029         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5030         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5031                 bp->hwrm_cmd_resp_addr;
5032         int rc = 0;
5033
5034         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5035         req.tunnel_type = type;
5036         req.dest_fid = bp->fw_fid;
5037         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5038         HWRM_CHECK_RESULT();
5039
5040         HWRM_UNLOCK();
5041
5042         return rc;
5043 }
5044
5045 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5046 {
5047         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5048         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5049                 bp->hwrm_cmd_resp_addr;
5050         int rc = 0;
5051
5052         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5053         req.src_fid = bp->fw_fid;
5054         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5055         HWRM_CHECK_RESULT();
5056
5057         if (type)
5058                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5059
5060         HWRM_UNLOCK();
5061
5062         return rc;
5063 }
5064
5065 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5066                                    uint16_t *dst_fid)
5067 {
5068         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5069         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5070                 bp->hwrm_cmd_resp_addr;
5071         int rc = 0;
5072
5073         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5074         req.src_fid = bp->fw_fid;
5075         req.tunnel_type = tun_type;
5076         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5077         HWRM_CHECK_RESULT();
5078
5079         if (dst_fid)
5080                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5081
5082         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5083
5084         HWRM_UNLOCK();
5085
5086         return rc;
5087 }
5088
5089 int bnxt_hwrm_set_mac(struct bnxt *bp)
5090 {
5091         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5092         struct hwrm_func_vf_cfg_input req = {0};
5093         int rc = 0;
5094
5095         if (!BNXT_VF(bp))
5096                 return 0;
5097
5098         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5099
5100         req.enables =
5101                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5102         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5103
5104         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5105
5106         HWRM_CHECK_RESULT();
5107
5108         HWRM_UNLOCK();
5109
5110         return rc;
5111 }
5112
5113 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5114 {
5115         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5116         struct hwrm_func_drv_if_change_input req = {0};
5117         uint32_t flags;
5118         int rc;
5119
5120         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5121                 return 0;
5122
5123         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5124          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5125          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5126          */
5127         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5128                 return 0;
5129
5130         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5131
5132         if (up)
5133                 req.flags =
5134                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5135
5136         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5137
5138         HWRM_CHECK_RESULT();
5139         flags = rte_le_to_cpu_32(resp->flags);
5140         HWRM_UNLOCK();
5141
5142         if (!up)
5143                 return 0;
5144
5145         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5146                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5147                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5148         }
5149
5150         return 0;
5151 }
5152
5153 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5154 {
5155         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5156         struct bnxt_error_recovery_info *info = bp->recovery_info;
5157         struct hwrm_error_recovery_qcfg_input req = {0};
5158         uint32_t flags = 0;
5159         unsigned int i;
5160         int rc;
5161
5162         /* Older FW does not have error recovery support */
5163         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5164                 return 0;
5165
5166         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5167
5168         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5169
5170         HWRM_CHECK_RESULT();
5171
5172         flags = rte_le_to_cpu_32(resp->flags);
5173         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5174                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5175         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5176                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5177
5178         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5179             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5180                 rc = -EINVAL;
5181                 goto err;
5182         }
5183
5184         /* FW returned values are in units of 100msec */
5185         info->driver_polling_freq =
5186                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5187         info->master_func_wait_period =
5188                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5189         info->normal_func_wait_period =
5190                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5191         info->master_func_wait_period_after_reset =
5192                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5193         info->max_bailout_time_after_reset =
5194                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5195         info->status_regs[BNXT_FW_STATUS_REG] =
5196                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5197         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5198                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5199         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5200                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5201         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5202                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5203         info->reg_array_cnt =
5204                 rte_le_to_cpu_32(resp->reg_array_cnt);
5205
5206         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5207                 rc = -EINVAL;
5208                 goto err;
5209         }
5210
5211         for (i = 0; i < info->reg_array_cnt; i++) {
5212                 info->reset_reg[i] =
5213                         rte_le_to_cpu_32(resp->reset_reg[i]);
5214                 info->reset_reg_val[i] =
5215                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5216                 info->delay_after_reset[i] =
5217                         resp->delay_after_reset[i];
5218         }
5219 err:
5220         HWRM_UNLOCK();
5221
5222         /* Map the FW status registers */
5223         if (!rc)
5224                 rc = bnxt_map_fw_health_status_regs(bp);
5225
5226         if (rc) {
5227                 rte_free(bp->recovery_info);
5228                 bp->recovery_info = NULL;
5229         }
5230         return rc;
5231 }
5232
5233 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5234 {
5235         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5236         struct hwrm_fw_reset_input req = {0};
5237         int rc;
5238
5239         if (!BNXT_PF(bp))
5240                 return -EOPNOTSUPP;
5241
5242         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5243
5244         req.embedded_proc_type =
5245                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5246         req.selfrst_status =
5247                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5248         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5249
5250         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5251                                     BNXT_USE_KONG(bp));
5252
5253         HWRM_CHECK_RESULT();
5254         HWRM_UNLOCK();
5255
5256         return rc;
5257 }
5258
5259 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5260 {
5261         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5262         struct hwrm_port_ts_query_input req = {0};
5263         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5264         uint32_t flags = 0;
5265         int rc;
5266
5267         if (!ptp)
5268                 return 0;
5269
5270         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5271
5272         switch (path) {
5273         case BNXT_PTP_FLAGS_PATH_TX:
5274                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5275                 break;
5276         case BNXT_PTP_FLAGS_PATH_RX:
5277                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5278                 break;
5279         case BNXT_PTP_FLAGS_CURRENT_TIME:
5280                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5281                 break;
5282         }
5283
5284         req.flags = rte_cpu_to_le_32(flags);
5285         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5286
5287         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5288
5289         HWRM_CHECK_RESULT();
5290
5291         if (timestamp) {
5292                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5293                 *timestamp |=
5294                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5295         }
5296         HWRM_UNLOCK();
5297
5298         return rc;
5299 }
5300
5301 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5302 {
5303         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5304                                         bp->hwrm_cmd_resp_addr;
5305         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5306         uint32_t flags = 0;
5307         int rc = 0;
5308
5309         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
5310                 return rc;
5311
5312         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5313                 PMD_DRV_LOG(DEBUG,
5314                             "Not a PF or trusted VF. Command not supported\n");
5315                 return 0;
5316         }
5317
5318         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5319         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5320
5321         HWRM_CHECK_RESULT();
5322         flags = rte_le_to_cpu_32(resp->flags);
5323         HWRM_UNLOCK();
5324
5325         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5326                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5327                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5328         }
5329
5330         return rc;
5331 }
5332
5333 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5334 {
5335         int rc = 0;
5336
5337         struct hwrm_cfa_counter_qcaps_input req = {0};
5338         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5339
5340         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5341                 PMD_DRV_LOG(DEBUG,
5342                             "Not a PF or trusted VF. Command not supported\n");
5343                 return 0;
5344         }
5345
5346         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5347         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5348         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5349
5350         HWRM_CHECK_RESULT();
5351         if (max_fc)
5352                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5353         HWRM_UNLOCK();
5354
5355         return 0;
5356 }
5357
5358 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5359 {
5360         int rc = 0;
5361         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5362         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5363
5364         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5365                 PMD_DRV_LOG(DEBUG,
5366                             "Not a PF or trusted VF. Command not supported\n");
5367                 return 0;
5368         }
5369
5370         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5371
5372         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5373         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5374         req.page_dir = rte_cpu_to_le_64(dma_addr);
5375
5376         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5377
5378         HWRM_CHECK_RESULT();
5379         if (ctx_id) {
5380                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5381                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5382         }
5383         HWRM_UNLOCK();
5384
5385         return 0;
5386 }
5387
5388 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5389 {
5390         int rc = 0;
5391         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5392         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5393
5394         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5395                 PMD_DRV_LOG(DEBUG,
5396                             "Not a PF or trusted VF. Command not supported\n");
5397                 return 0;
5398         }
5399
5400         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5401
5402         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5403
5404         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5405
5406         HWRM_CHECK_RESULT();
5407         HWRM_UNLOCK();
5408
5409         return rc;
5410 }
5411
5412 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5413                               uint16_t cntr, uint16_t ctx_id,
5414                               uint32_t num_entries, bool enable)
5415 {
5416         struct hwrm_cfa_counter_cfg_input req = {0};
5417         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5418         uint16_t flags = 0;
5419         int rc;
5420
5421         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5422                 PMD_DRV_LOG(DEBUG,
5423                             "Not a PF or trusted VF. Command not supported\n");
5424                 return 0;
5425         }
5426
5427         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5428
5429         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5430         req.counter_type = rte_cpu_to_le_16(cntr);
5431         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5432                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5433         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5434         if (dir == BNXT_DIR_RX)
5435                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5436         else if (dir == BNXT_DIR_TX)
5437                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5438         req.flags = rte_cpu_to_le_16(flags);
5439         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5440         req.num_entries = rte_cpu_to_le_32(num_entries);
5441
5442         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5443         HWRM_CHECK_RESULT();
5444         HWRM_UNLOCK();
5445
5446         return 0;
5447 }
5448
5449 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5450                                  enum bnxt_flow_dir dir,
5451                                  uint16_t cntr,
5452                                  uint16_t num_entries)
5453 {
5454         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5455         struct hwrm_cfa_counter_qstats_input req = {0};
5456         uint16_t flow_ctx_id = 0;
5457         uint16_t flags = 0;
5458         int rc = 0;
5459
5460         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5461                 PMD_DRV_LOG(DEBUG,
5462                             "Not a PF or trusted VF. Command not supported\n");
5463                 return 0;
5464         }
5465
5466         if (dir == BNXT_DIR_RX) {
5467                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5468                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5469         } else if (dir == BNXT_DIR_TX) {
5470                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5471                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5472         }
5473
5474         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5475         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5476         req.counter_type = rte_cpu_to_le_16(cntr);
5477         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5478         req.num_entries = rte_cpu_to_le_16(num_entries);
5479         req.flags = rte_cpu_to_le_16(flags);
5480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5481
5482         HWRM_CHECK_RESULT();
5483         HWRM_UNLOCK();
5484
5485         return 0;
5486 }