4 * Copyright(c) Broadcom Limited.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <rte_byteorder.h>
39 #include <rte_common.h>
40 #include <rte_cycles.h>
41 #include <rte_malloc.h>
42 #include <rte_memzone.h>
43 #include <rte_version.h>
47 #include "bnxt_filter.h"
48 #include "bnxt_hwrm.h"
51 #include "bnxt_ring.h"
54 #include "bnxt_vnic.h"
55 #include "hsi_struct_def_dpdk.h"
59 #define HWRM_CMD_TIMEOUT 2000
61 struct bnxt_plcmodes_cfg {
63 uint16_t jumbo_thresh;
65 uint16_t hds_threshold;
68 static int page_getenum(size_t size)
84 RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
85 return sizeof(void *) * 8 - 1;
88 static int page_roundup(size_t size)
90 return 1 << page_getenum(size);
94 * HWRM Functions (sent to HWRM)
95 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
96 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
97 * command was failed by the ChiMP.
100 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
104 struct input *req = msg;
105 struct output *resp = bp->hwrm_cmd_resp_addr;
106 uint32_t *data = msg;
109 uint16_t max_req_len = bp->max_req_len;
110 struct hwrm_short_input short_input = { 0 };
112 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
113 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
115 memset(short_cmd_req, 0, bp->max_req_len);
116 memcpy(short_cmd_req, req, msg_len);
118 short_input.req_type = rte_cpu_to_le_16(req->req_type);
119 short_input.signature = rte_cpu_to_le_16(
120 HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
121 short_input.size = rte_cpu_to_le_16(msg_len);
122 short_input.req_addr =
123 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
125 data = (uint32_t *)&short_input;
126 msg_len = sizeof(short_input);
128 /* Sync memory write before updating doorbell */
131 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
134 /* Write request msg to hwrm channel */
135 for (i = 0; i < msg_len; i += 4) {
136 bar = (uint8_t *)bp->bar0 + i;
137 rte_write32(*data, bar);
141 /* Zero the rest of the request space */
142 for (; i < max_req_len; i += 4) {
143 bar = (uint8_t *)bp->bar0 + i;
147 /* Ring channel doorbell */
148 bar = (uint8_t *)bp->bar0 + 0x100;
151 /* Poll for the valid bit */
152 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
153 /* Sanity check on the resp->resp_len */
155 if (resp->resp_len && resp->resp_len <=
157 /* Last byte of resp contains the valid key */
158 valid = (uint8_t *)resp + resp->resp_len - 1;
159 if (*valid == HWRM_RESP_VALID_KEY)
165 if (i >= HWRM_CMD_TIMEOUT) {
166 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
176 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
180 rte_spinlock_lock(&bp->hwrm_lock);
181 rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
182 rte_spinlock_unlock(&bp->hwrm_lock);
186 #define HWRM_PREP(req, type, cr, resp) \
187 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
188 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
189 req.cmpl_ring = rte_cpu_to_le_16(cr); \
190 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
191 req.target_id = rte_cpu_to_le_16(0xffff); \
192 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
194 #define HWRM_CHECK_RESULT \
197 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
201 if (resp->error_code) { \
202 rc = rte_le_to_cpu_16(resp->error_code); \
203 if (resp->resp_len >= 16) { \
204 struct hwrm_err_output *tmp_hwrm_err_op = \
207 "%s error %d:%d:%08x:%04x\n", \
209 rc, tmp_hwrm_err_op->cmd_err, \
211 tmp_hwrm_err_op->opaque_0), \
213 tmp_hwrm_err_op->opaque_1)); \
217 "%s error %d\n", __func__, rc); \
223 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
226 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
227 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
229 HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
230 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
233 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
240 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
241 struct bnxt_vnic_info *vnic,
243 struct bnxt_vlan_table_entry *vlan_table)
246 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
247 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
250 HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
251 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
253 /* FIXME add multicast flag, when multicast adding options is supported
256 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
257 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
258 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
259 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
260 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
261 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
262 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
263 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
264 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
265 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
266 if (vnic->mc_addr_cnt) {
267 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
268 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
269 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
271 if (vlan_count && vlan_table) {
272 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
273 req.vlan_tag_tbl_addr = rte_cpu_to_le_16(
274 rte_mem_virt2phy(vlan_table));
275 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
277 req.mask = rte_cpu_to_le_32(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST |
280 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
287 int bnxt_hwrm_clear_filter(struct bnxt *bp,
288 struct bnxt_filter_info *filter)
291 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
292 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
294 HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
296 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
298 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
302 filter->fw_l2_filter_id = -1;
307 int bnxt_hwrm_set_filter(struct bnxt *bp,
309 struct bnxt_filter_info *filter)
312 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
313 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
314 uint32_t enables = 0;
316 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
318 req.flags = rte_cpu_to_le_32(filter->flags);
320 enables = filter->enables |
321 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
322 req.dst_id = rte_cpu_to_le_16(dst_id);
325 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
326 memcpy(req.l2_addr, filter->l2_addr,
329 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
330 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
333 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
334 req.l2_ovlan = filter->l2_ovlan;
336 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
337 req.l2_ovlan_mask = filter->l2_ovlan_mask;
338 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
339 req.src_id = rte_cpu_to_le_32(filter->src_id);
340 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
341 req.src_type = filter->src_type;
343 req.enables = rte_cpu_to_le_32(enables);
345 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
349 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
354 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
357 struct hwrm_func_qcaps_input req = {.req_type = 0 };
358 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
359 uint16_t new_max_vfs;
362 HWRM_PREP(req, FUNC_QCAPS, -1, resp);
364 req.fid = rte_cpu_to_le_16(0xffff);
366 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
370 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
372 bp->pf.port_id = resp->port_id;
373 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
374 new_max_vfs = bp->pdev->max_vfs;
375 if (new_max_vfs != bp->pf.max_vfs) {
377 rte_free(bp->pf.vf_info);
378 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
379 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
380 bp->pf.max_vfs = new_max_vfs;
381 for (i = 0; i < new_max_vfs; i++) {
382 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
383 bp->pf.vf_info[i].vlan_table =
384 rte_zmalloc("VF VLAN table",
387 if (bp->pf.vf_info[i].vlan_table == NULL)
389 "Fail to alloc VLAN table for VF %d\n",
393 bp->pf.vf_info[i].vlan_table);
394 STAILQ_INIT(&bp->pf.vf_info[i].filter);
399 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
400 memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
401 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
402 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
403 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
404 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
405 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
406 /* TODO: For now, do not support VMDq/RFS on VFs. */
411 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
415 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
417 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
422 int bnxt_hwrm_func_reset(struct bnxt *bp)
425 struct hwrm_func_reset_input req = {.req_type = 0 };
426 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
428 HWRM_PREP(req, FUNC_RESET, -1, resp);
430 req.enables = rte_cpu_to_le_32(0);
432 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
439 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
442 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
443 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
445 if (bp->flags & BNXT_FLAG_REGISTERED)
448 HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
449 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
450 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
451 req.ver_maj = RTE_VER_YEAR;
452 req.ver_min = RTE_VER_MONTH;
453 req.ver_upd = RTE_VER_MINOR;
456 req.enables |= rte_cpu_to_le_32(
457 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
458 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
459 RTE_MIN(sizeof(req.vf_req_fwd),
460 sizeof(bp->pf.vf_req_fwd)));
463 req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1); /* TODO: Use MACRO */
464 memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
466 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
470 bp->flags |= BNXT_FLAG_REGISTERED;
475 int bnxt_hwrm_ver_get(struct bnxt *bp)
478 struct hwrm_ver_get_input req = {.req_type = 0 };
479 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
482 uint16_t max_resp_len;
483 char type[RTE_MEMZONE_NAMESIZE];
484 uint32_t dev_caps_cfg;
486 bp->max_req_len = HWRM_MAX_REQ_LEN;
487 HWRM_PREP(req, VER_GET, -1, resp);
489 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
490 req.hwrm_intf_min = HWRM_VERSION_MINOR;
491 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
494 * Hold the lock since we may be adjusting the response pointers.
496 rte_spinlock_lock(&bp->hwrm_lock);
497 rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
501 RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
502 resp->hwrm_intf_maj, resp->hwrm_intf_min,
504 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
505 bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
506 (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
507 RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
508 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
510 my_version = HWRM_VERSION_MAJOR << 16;
511 my_version |= HWRM_VERSION_MINOR << 8;
512 my_version |= HWRM_VERSION_UPDATE;
514 fw_version = resp->hwrm_intf_maj << 16;
515 fw_version |= resp->hwrm_intf_min << 8;
516 fw_version |= resp->hwrm_intf_upd;
518 if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
519 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
524 if (my_version != fw_version) {
525 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
526 if (my_version < fw_version) {
528 "Firmware API version is newer than driver.\n");
530 "The driver may be missing features.\n");
533 "Firmware API version is older than driver.\n");
535 "Not all driver features may be functional.\n");
539 if (bp->max_req_len > resp->max_req_win_len) {
540 RTE_LOG(ERR, PMD, "Unsupported request length\n");
543 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
544 max_resp_len = resp->max_resp_len;
545 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
547 if (bp->max_resp_len != max_resp_len) {
548 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
549 bp->pdev->addr.domain, bp->pdev->addr.bus,
550 bp->pdev->addr.devid, bp->pdev->addr.function);
552 rte_free(bp->hwrm_cmd_resp_addr);
554 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
555 if (bp->hwrm_cmd_resp_addr == NULL) {
559 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
560 bp->hwrm_cmd_resp_dma_addr =
561 rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
562 if (bp->hwrm_cmd_resp_dma_addr == 0) {
564 "Unable to map response buffer to physical memory.\n");
568 bp->max_resp_len = max_resp_len;
572 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
574 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
575 RTE_LOG(DEBUG, PMD, "Short command supported\n");
577 rte_free(bp->hwrm_short_cmd_req_addr);
579 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
581 if (bp->hwrm_short_cmd_req_addr == NULL) {
585 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
586 bp->hwrm_short_cmd_req_dma_addr =
587 rte_mem_virt2phy(bp->hwrm_short_cmd_req_addr);
588 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
589 rte_free(bp->hwrm_short_cmd_req_addr);
591 "Unable to map buffer to physical memory.\n");
596 bp->flags |= BNXT_FLAG_SHORT_CMD;
600 rte_spinlock_unlock(&bp->hwrm_lock);
604 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
607 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
608 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
610 if (!(bp->flags & BNXT_FLAG_REGISTERED))
613 HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
616 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
620 bp->flags &= ~BNXT_FLAG_REGISTERED;
625 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
628 struct hwrm_port_phy_cfg_input req = {0};
629 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
630 uint32_t enables = 0;
632 HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
635 req.flags = rte_cpu_to_le_32(conf->phy_flags);
636 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
638 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
639 * any auto mode, even "none".
641 if (!conf->link_speed) {
642 req.auto_mode |= conf->auto_mode;
643 enables = HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
644 req.auto_link_speed_mask = conf->auto_link_speed_mask;
646 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
647 req.auto_link_speed = bp->link_info.auto_link_speed;
649 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
651 req.auto_duplex = conf->duplex;
652 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
653 req.auto_pause = conf->auto_pause;
654 req.force_pause = conf->force_pause;
655 /* Set force_pause if there is no auto or if there is a force */
656 if (req.auto_pause && !req.force_pause)
657 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
659 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
661 req.enables = rte_cpu_to_le_32(enables);
664 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
665 RTE_LOG(INFO, PMD, "Force Link Down\n");
668 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
675 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
676 struct bnxt_link_info *link_info)
679 struct hwrm_port_phy_qcfg_input req = {0};
680 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
682 HWRM_PREP(req, PORT_PHY_QCFG, -1, resp);
684 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
688 link_info->phy_link_status = resp->link;
690 (link_info->phy_link_status ==
691 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
692 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
693 link_info->duplex = resp->duplex;
694 link_info->pause = resp->pause;
695 link_info->auto_pause = resp->auto_pause;
696 link_info->force_pause = resp->force_pause;
697 link_info->auto_mode = resp->auto_mode;
699 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
700 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
701 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
702 link_info->phy_ver[0] = resp->phy_maj;
703 link_info->phy_ver[1] = resp->phy_min;
704 link_info->phy_ver[2] = resp->phy_bld;
709 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
712 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
713 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
715 HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
717 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
721 #define GET_QUEUE_INFO(x) \
722 bp->cos_queue[x].id = resp->queue_id##x; \
723 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
737 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
738 struct bnxt_ring *ring,
739 uint32_t ring_type, uint32_t map_index,
740 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
743 uint32_t enables = 0;
744 struct hwrm_ring_alloc_input req = {.req_type = 0 };
745 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
747 HWRM_PREP(req, RING_ALLOC, -1, resp);
749 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
750 req.fbo = rte_cpu_to_le_32(0);
751 /* Association of ring index with doorbell index */
752 req.logical_id = rte_cpu_to_le_16(map_index);
753 req.length = rte_cpu_to_le_32(ring->ring_size);
756 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
757 req.queue_id = bp->cos_queue[0].id;
759 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
760 req.ring_type = ring_type;
761 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
762 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
763 if (stats_ctx_id != INVALID_STATS_CTX_ID)
765 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
767 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
768 req.ring_type = ring_type;
770 * TODO: Some HWRM versions crash with
771 * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
773 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
776 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
780 req.enables = rte_cpu_to_le_32(enables);
782 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
784 if (rc || resp->error_code) {
785 if (rc == 0 && resp->error_code)
786 rc = rte_le_to_cpu_16(resp->error_code);
788 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
790 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
792 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
794 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
796 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
798 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
801 RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
806 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
810 int bnxt_hwrm_ring_free(struct bnxt *bp,
811 struct bnxt_ring *ring, uint32_t ring_type)
814 struct hwrm_ring_free_input req = {.req_type = 0 };
815 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
817 HWRM_PREP(req, RING_FREE, -1, resp);
819 req.ring_type = ring_type;
820 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
822 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
824 if (rc || resp->error_code) {
825 if (rc == 0 && resp->error_code)
826 rc = rte_le_to_cpu_16(resp->error_code);
829 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
830 RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
833 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
834 RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
837 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
838 RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
842 RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
849 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
852 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
853 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
855 HWRM_PREP(req, RING_GRP_ALLOC, -1, resp);
857 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
858 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
859 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
860 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
862 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
866 bp->grp_info[idx].fw_grp_id =
867 rte_le_to_cpu_16(resp->ring_group_id);
872 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
875 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
876 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
878 HWRM_PREP(req, RING_GRP_FREE, -1, resp);
880 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
882 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
886 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
890 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
893 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
894 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
896 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
899 HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
901 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
903 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
910 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
911 unsigned int idx __rte_unused)
914 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
915 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
917 HWRM_PREP(req, STAT_CTX_ALLOC, -1, resp);
919 req.update_period_ms = rte_cpu_to_le_32(0);
922 rte_cpu_to_le_64(cpr->hw_stats_map);
924 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
928 cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
933 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
934 unsigned int idx __rte_unused)
937 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
938 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
940 HWRM_PREP(req, STAT_CTX_FREE, -1, resp);
942 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
944 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
951 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
954 struct hwrm_vnic_alloc_input req = { 0 };
955 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
957 /* map ring groups to this vnic */
958 RTE_LOG(DEBUG, PMD, "Alloc VNIC. Start %x, End %x\n",
959 vnic->start_grp_id, vnic->end_grp_id);
960 for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
961 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
962 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
963 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
964 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
965 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
966 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
967 ETHER_CRC_LEN + VLAN_TAG_SIZE;
968 HWRM_PREP(req, VNIC_ALLOC, -1, resp);
970 if (vnic->func_default)
971 req.flags = HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT;
972 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
976 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
980 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
981 struct bnxt_vnic_info *vnic,
982 struct bnxt_plcmodes_cfg *pmode)
985 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
986 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
988 HWRM_PREP(req, VNIC_PLCMODES_QCFG, -1, resp);
990 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
992 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
996 pmode->flags = rte_le_to_cpu_32(resp->flags);
997 /* dflt_vnic bit doesn't exist in the _cfg command */
998 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
999 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1000 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1001 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1006 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1007 struct bnxt_vnic_info *vnic,
1008 struct bnxt_plcmodes_cfg *pmode)
1011 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1012 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1014 HWRM_PREP(req, VNIC_PLCMODES_CFG, -1, resp);
1016 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1017 req.flags = rte_cpu_to_le_32(pmode->flags);
1018 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1019 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1020 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1021 req.enables = rte_cpu_to_le_32(
1022 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1023 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1024 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1027 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1034 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1037 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1038 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1039 uint32_t ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1040 struct bnxt_plcmodes_cfg pmodes;
1042 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1046 HWRM_PREP(req, VNIC_CFG, -1, resp);
1048 /* Only RSS support for now TBD: COS & LB */
1050 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP |
1051 HWRM_VNIC_CFG_INPUT_ENABLES_MRU);
1052 if (vnic->lb_rule != 0xffff)
1053 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1054 if (vnic->cos_rule != 0xffff)
1055 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1056 if (vnic->rss_rule != 0xffff)
1057 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1058 req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1059 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1060 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1061 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1062 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1063 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1064 req.mru = rte_cpu_to_le_16(vnic->mru);
1065 if (vnic->func_default)
1067 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1068 if (vnic->vlan_strip)
1070 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1073 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1074 if (vnic->roce_dual)
1075 req.flags |= rte_cpu_to_le_32(
1076 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1077 if (vnic->roce_only)
1078 req.flags |= rte_cpu_to_le_32(
1079 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1080 if (vnic->rss_dflt_cr)
1081 req.flags |= rte_cpu_to_le_32(
1082 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1084 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1088 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1093 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1097 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1098 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1100 HWRM_PREP(req, VNIC_QCFG, -1, resp);
1103 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1104 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1105 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1107 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1111 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1112 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1113 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1114 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1115 vnic->mru = rte_le_to_cpu_16(resp->mru);
1116 vnic->func_default = rte_le_to_cpu_32(
1117 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1118 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1119 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1120 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1121 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1122 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1123 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1124 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1125 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1126 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1127 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1132 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1135 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1136 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1137 bp->hwrm_cmd_resp_addr;
1139 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, -1, resp);
1141 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1145 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1150 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1153 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1154 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1155 bp->hwrm_cmd_resp_addr;
1157 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, -1, resp);
1159 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1161 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1165 vnic->rss_rule = INVALID_HW_RING_ID;
1170 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1173 struct hwrm_vnic_free_input req = {.req_type = 0 };
1174 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1176 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
1179 HWRM_PREP(req, VNIC_FREE, -1, resp);
1181 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1183 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1187 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1191 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1192 struct bnxt_vnic_info *vnic)
1195 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1196 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1198 HWRM_PREP(req, VNIC_RSS_CFG, -1, resp);
1200 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1202 req.ring_grp_tbl_addr =
1203 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1204 req.hash_key_tbl_addr =
1205 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1206 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1208 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1215 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1216 struct bnxt_vnic_info *vnic)
1219 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1220 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1223 HWRM_PREP(req, VNIC_PLCMODES_CFG, -1, resp);
1225 req.flags = rte_cpu_to_le_32(
1226 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1228 req.enables = rte_cpu_to_le_32(
1229 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1231 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1232 size -= RTE_PKTMBUF_HEADROOM;
1234 req.jumbo_thresh = rte_cpu_to_le_16(size);
1235 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1237 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1244 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1245 struct bnxt_vnic_info *vnic, bool enable)
1248 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1249 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1251 HWRM_PREP(req, VNIC_TPA_CFG, -1, resp);
1254 req.enables = rte_cpu_to_le_32(
1255 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1256 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1257 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1258 req.flags = rte_cpu_to_le_32(
1259 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1260 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1261 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1262 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1263 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1264 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1265 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1266 req.max_agg_segs = rte_cpu_to_le_16(5);
1268 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1269 req.min_agg_len = rte_cpu_to_le_32(512);
1272 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1279 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1281 struct hwrm_func_cfg_input req = {0};
1282 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1285 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1286 req.enables = rte_cpu_to_le_32(
1287 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1288 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1289 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1291 HWRM_PREP(req, FUNC_CFG, -1, resp);
1293 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1296 bp->pf.vf_info[vf].random_mac = false;
1301 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1305 struct hwrm_func_qstats_input req = {.req_type = 0};
1306 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1308 HWRM_PREP(req, FUNC_QSTATS, -1, resp);
1310 req.fid = rte_cpu_to_le_16(fid);
1312 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1317 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1322 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1323 struct rte_eth_stats *stats)
1326 struct hwrm_func_qstats_input req = {.req_type = 0};
1327 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1329 HWRM_PREP(req, FUNC_QSTATS, -1, resp);
1331 req.fid = rte_cpu_to_le_16(fid);
1333 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1337 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1338 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1339 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1340 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1341 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1342 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1344 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1345 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1346 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1347 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1348 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1349 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1351 stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1352 stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1354 stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1359 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1362 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1363 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1365 HWRM_PREP(req, FUNC_CLR_STATS, -1, resp);
1367 req.fid = rte_cpu_to_le_16(fid);
1369 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1377 * HWRM utility functions
1380 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1385 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1386 struct bnxt_tx_queue *txq;
1387 struct bnxt_rx_queue *rxq;
1388 struct bnxt_cp_ring_info *cpr;
1390 if (i >= bp->rx_cp_nr_rings) {
1391 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1394 rxq = bp->rx_queues[i];
1398 rc = bnxt_hwrm_stat_clear(bp, cpr);
1405 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1409 struct bnxt_cp_ring_info *cpr;
1411 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1413 if (i >= bp->rx_cp_nr_rings)
1414 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1416 cpr = bp->rx_queues[i]->cp_ring;
1417 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1418 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1419 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1421 * TODO. Need a better way to reset grp_info.stats_ctx
1422 * for Rx rings only. stats_ctx is not saved for Tx
1425 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
1433 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1438 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1439 struct bnxt_tx_queue *txq;
1440 struct bnxt_rx_queue *rxq;
1441 struct bnxt_cp_ring_info *cpr;
1443 if (i >= bp->rx_cp_nr_rings) {
1444 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1447 rxq = bp->rx_queues[i];
1451 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1459 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1464 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1466 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID) {
1468 "Attempt to free invalid ring group %d\n",
1473 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1481 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1482 unsigned int idx __rte_unused)
1484 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1486 bnxt_hwrm_ring_free(bp, cp_ring,
1487 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1488 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1489 bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1490 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1491 sizeof(*cpr->cp_desc_ring));
1492 cpr->cp_raw_cons = 0;
1495 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1500 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1501 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1502 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1503 struct bnxt_ring *ring = txr->tx_ring_struct;
1504 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1505 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1507 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1508 bnxt_hwrm_ring_free(bp, ring,
1509 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1510 ring->fw_ring_id = INVALID_HW_RING_ID;
1511 memset(txr->tx_desc_ring, 0,
1512 txr->tx_ring_struct->ring_size *
1513 sizeof(*txr->tx_desc_ring));
1514 memset(txr->tx_buf_ring, 0,
1515 txr->tx_ring_struct->ring_size *
1516 sizeof(*txr->tx_buf_ring));
1520 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1521 bnxt_free_cp_ring(bp, cpr, idx);
1522 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1526 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1527 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1528 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1529 struct bnxt_ring *ring = rxr->rx_ring_struct;
1530 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1531 unsigned int idx = i + 1;
1533 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1534 bnxt_hwrm_ring_free(bp, ring,
1535 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1536 ring->fw_ring_id = INVALID_HW_RING_ID;
1537 bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1538 memset(rxr->rx_desc_ring, 0,
1539 rxr->rx_ring_struct->ring_size *
1540 sizeof(*rxr->rx_desc_ring));
1541 memset(rxr->rx_buf_ring, 0,
1542 rxr->rx_ring_struct->ring_size *
1543 sizeof(*rxr->rx_buf_ring));
1545 memset(rxr->ag_buf_ring, 0,
1546 rxr->ag_ring_struct->ring_size *
1547 sizeof(*rxr->ag_buf_ring));
1550 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1551 bnxt_free_cp_ring(bp, cpr, idx);
1552 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1553 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1557 /* Default completion ring */
1559 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1561 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1562 bnxt_free_cp_ring(bp, cpr, 0);
1563 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1570 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1575 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1576 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1583 void bnxt_free_hwrm_resources(struct bnxt *bp)
1585 /* Release memzone */
1586 rte_free(bp->hwrm_cmd_resp_addr);
1587 rte_free(bp->hwrm_short_cmd_req_addr);
1588 bp->hwrm_cmd_resp_addr = NULL;
1589 bp->hwrm_short_cmd_req_addr = NULL;
1590 bp->hwrm_cmd_resp_dma_addr = 0;
1591 bp->hwrm_short_cmd_req_dma_addr = 0;
1594 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1596 struct rte_pci_device *pdev = bp->pdev;
1597 char type[RTE_MEMZONE_NAMESIZE];
1599 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1600 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1601 bp->max_resp_len = HWRM_MAX_RESP_LEN;
1602 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1603 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1604 if (bp->hwrm_cmd_resp_addr == NULL)
1606 bp->hwrm_cmd_resp_dma_addr =
1607 rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
1608 if (bp->hwrm_cmd_resp_dma_addr == 0) {
1610 "unable to map response address to physical memory\n");
1613 rte_spinlock_init(&bp->hwrm_lock);
1618 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1620 struct bnxt_filter_info *filter;
1623 STAILQ_FOREACH(filter, &vnic->filter, next) {
1624 rc = bnxt_hwrm_clear_filter(bp, filter);
1631 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1633 struct bnxt_filter_info *filter;
1636 STAILQ_FOREACH(filter, &vnic->filter, next) {
1637 rc = bnxt_hwrm_set_filter(bp, vnic->fw_vnic_id, filter);
1644 void bnxt_free_tunnel_ports(struct bnxt *bp)
1646 if (bp->vxlan_port_cnt)
1647 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1648 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1650 if (bp->geneve_port_cnt)
1651 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1652 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1653 bp->geneve_port = 0;
1656 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1658 struct bnxt_vnic_info *vnic;
1661 if (bp->vnic_info == NULL)
1664 vnic = &bp->vnic_info[0];
1666 bnxt_hwrm_cfa_l2_clear_rx_mask(bp, vnic);
1668 /* VNIC resources */
1669 for (i = 0; i < bp->nr_vnics; i++) {
1670 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1672 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1674 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1676 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1678 bnxt_hwrm_vnic_free(bp, vnic);
1680 /* Ring resources */
1681 bnxt_free_all_hwrm_rings(bp);
1682 bnxt_free_all_hwrm_ring_grps(bp);
1683 bnxt_free_all_hwrm_stat_ctxs(bp);
1684 bnxt_free_tunnel_ports(bp);
1687 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1689 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1691 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1692 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1694 switch (conf_link_speed) {
1695 case ETH_LINK_SPEED_10M_HD:
1696 case ETH_LINK_SPEED_100M_HD:
1697 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1699 return hw_link_duplex;
1702 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1704 uint16_t eth_link_speed = 0;
1706 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1707 return ETH_LINK_SPEED_AUTONEG;
1709 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1710 case ETH_LINK_SPEED_100M:
1711 case ETH_LINK_SPEED_100M_HD:
1713 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1715 case ETH_LINK_SPEED_1G:
1717 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1719 case ETH_LINK_SPEED_2_5G:
1721 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1723 case ETH_LINK_SPEED_10G:
1725 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1727 case ETH_LINK_SPEED_20G:
1729 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1731 case ETH_LINK_SPEED_25G:
1733 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1735 case ETH_LINK_SPEED_40G:
1737 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1739 case ETH_LINK_SPEED_50G:
1741 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1745 "Unsupported link speed %d; default to AUTO\n",
1749 return eth_link_speed;
1752 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1753 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1754 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1755 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1757 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
1761 if (link_speed == ETH_LINK_SPEED_AUTONEG)
1764 if (link_speed & ETH_LINK_SPEED_FIXED) {
1765 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1767 if (one_speed & (one_speed - 1)) {
1769 "Invalid advertised speeds (%u) for port %u\n",
1770 link_speed, port_id);
1773 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1775 "Unsupported advertised speed (%u) for port %u\n",
1776 link_speed, port_id);
1780 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1782 "Unsupported advertised speeds (%u) for port %u\n",
1783 link_speed, port_id);
1791 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
1795 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
1796 if (bp->link_info.support_speeds)
1797 return bp->link_info.support_speeds;
1798 link_speed = BNXT_SUPPORTED_SPEEDS;
1801 if (link_speed & ETH_LINK_SPEED_100M)
1802 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1803 if (link_speed & ETH_LINK_SPEED_100M_HD)
1804 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1805 if (link_speed & ETH_LINK_SPEED_1G)
1806 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1807 if (link_speed & ETH_LINK_SPEED_2_5G)
1808 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1809 if (link_speed & ETH_LINK_SPEED_10G)
1810 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1811 if (link_speed & ETH_LINK_SPEED_20G)
1812 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1813 if (link_speed & ETH_LINK_SPEED_25G)
1814 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1815 if (link_speed & ETH_LINK_SPEED_40G)
1816 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1817 if (link_speed & ETH_LINK_SPEED_50G)
1818 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1822 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
1824 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
1826 switch (hw_link_speed) {
1827 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
1828 eth_link_speed = ETH_SPEED_NUM_100M;
1830 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
1831 eth_link_speed = ETH_SPEED_NUM_1G;
1833 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
1834 eth_link_speed = ETH_SPEED_NUM_2_5G;
1836 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
1837 eth_link_speed = ETH_SPEED_NUM_10G;
1839 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
1840 eth_link_speed = ETH_SPEED_NUM_20G;
1842 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
1843 eth_link_speed = ETH_SPEED_NUM_25G;
1845 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
1846 eth_link_speed = ETH_SPEED_NUM_40G;
1848 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
1849 eth_link_speed = ETH_SPEED_NUM_50G;
1851 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
1853 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
1857 return eth_link_speed;
1860 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
1862 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1864 switch (hw_link_duplex) {
1865 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
1866 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
1867 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1869 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
1870 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
1873 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
1877 return eth_link_duplex;
1880 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
1883 struct bnxt_link_info *link_info = &bp->link_info;
1885 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
1888 "Get link config failed with rc %d\n", rc);
1891 if (link_info->link_speed)
1893 bnxt_parse_hw_link_speed(link_info->link_speed);
1895 link->link_speed = ETH_SPEED_NUM_NONE;
1896 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
1897 link->link_status = link_info->link_up;
1898 link->link_autoneg = link_info->auto_mode ==
1899 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
1900 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
1905 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
1908 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1909 struct bnxt_link_info link_req;
1912 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
1915 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
1916 bp->eth_dev->data->port_id);
1920 memset(&link_req, 0, sizeof(link_req));
1921 link_req.link_up = link_up;
1925 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
1926 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
1928 link_req.phy_flags |=
1929 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
1930 link_req.auto_mode =
1931 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1932 link_req.auto_link_speed_mask =
1933 bnxt_parse_eth_link_speed_mask(bp,
1934 dev_conf->link_speeds);
1936 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
1937 link_req.link_speed = speed;
1938 RTE_LOG(INFO, PMD, "Set Link Speed %x\n", speed);
1940 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
1941 link_req.auto_pause = bp->link_info.auto_pause;
1942 link_req.force_pause = bp->link_info.force_pause;
1945 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
1948 "Set link config failed with rc %d\n", rc);
1951 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1957 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
1959 struct hwrm_func_qcfg_input req = {0};
1960 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1963 HWRM_PREP(req, FUNC_QCFG, -1, resp);
1964 req.fid = rte_cpu_to_le_16(0xffff);
1966 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1970 /* Hard Coded.. 0xfff VLAN ID mask */
1971 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
1973 switch (resp->port_partition_type) {
1974 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
1975 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
1976 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
1977 bp->port_partition_type = resp->port_partition_type;
1980 bp->port_partition_type = 0;
1987 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
1988 struct hwrm_func_qcaps_output *qcaps)
1990 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
1991 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
1992 sizeof(qcaps->mac_address));
1993 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
1994 qcaps->max_rx_rings = fcfg->num_rx_rings;
1995 qcaps->max_tx_rings = fcfg->num_tx_rings;
1996 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
1997 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
1999 qcaps->first_vf_id = 0;
2000 qcaps->max_vnics = fcfg->num_vnics;
2001 qcaps->max_decap_records = 0;
2002 qcaps->max_encap_records = 0;
2003 qcaps->max_tx_wm_flows = 0;
2004 qcaps->max_tx_em_flows = 0;
2005 qcaps->max_rx_wm_flows = 0;
2006 qcaps->max_rx_em_flows = 0;
2007 qcaps->max_flow_id = 0;
2008 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2009 qcaps->max_sp_tx_rings = 0;
2010 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2013 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2015 struct hwrm_func_cfg_input req = {0};
2016 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2019 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2020 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2021 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2022 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2023 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2024 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2025 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2026 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2027 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2028 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2029 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2030 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2031 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2032 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2033 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2034 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2035 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2036 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2037 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2038 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2039 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2040 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2041 req.fid = rte_cpu_to_le_16(0xffff);
2043 HWRM_PREP(req, FUNC_CFG, -1, resp);
2045 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2051 static void populate_vf_func_cfg_req(struct bnxt *bp,
2052 struct hwrm_func_cfg_input *req,
2055 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2056 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2057 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2058 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2059 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2060 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2061 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2062 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2063 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2064 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2066 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2067 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2068 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2069 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2070 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2072 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2073 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2075 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2076 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2077 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2078 /* TODO: For now, do not support VMDq/RFS on VFs. */
2079 req->num_vnics = rte_cpu_to_le_16(1);
2080 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2084 static void add_random_mac_if_needed(struct bnxt *bp,
2085 struct hwrm_func_cfg_input *cfg_req,
2088 struct ether_addr mac;
2090 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2093 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2095 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2096 eth_random_addr(cfg_req->dflt_mac_addr);
2097 bp->pf.vf_info[vf].random_mac = true;
2099 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2103 static void reserve_resources_from_vf(struct bnxt *bp,
2104 struct hwrm_func_cfg_input *cfg_req,
2107 struct hwrm_func_qcaps_input req = {0};
2108 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2111 /* Get the actual allocated values now */
2112 HWRM_PREP(req, FUNC_QCAPS, -1, resp);
2113 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2114 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2117 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
2118 copy_func_cfg_to_qcaps(cfg_req, resp);
2119 } else if (resp->error_code) {
2120 rc = rte_le_to_cpu_16(resp->error_code);
2121 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
2122 copy_func_cfg_to_qcaps(cfg_req, resp);
2125 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2126 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2127 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2128 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2129 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2130 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2132 * TODO: While not supporting VMDq with VFs, max_vnics is always
2133 * forced to 1 in this case
2135 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2136 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2139 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2141 struct hwrm_func_qcfg_input req = {0};
2142 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2145 /* Check for zero MAC address */
2146 HWRM_PREP(req, FUNC_QCFG, -1, resp);
2147 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2148 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2150 RTE_LOG(ERR, PMD, "hwrm_func_qcfg failed rc:%d\n", rc);
2152 } else if (resp->error_code) {
2153 rc = rte_le_to_cpu_16(resp->error_code);
2154 RTE_LOG(ERR, PMD, "hwrm_func_qcfg error %d\n", rc);
2157 return rte_le_to_cpu_16(resp->vlan);
2160 static int update_pf_resource_max(struct bnxt *bp)
2162 struct hwrm_func_qcfg_input req = {0};
2163 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2166 /* And copy the allocated numbers into the pf struct */
2167 HWRM_PREP(req, FUNC_QCFG, -1, resp);
2168 req.fid = rte_cpu_to_le_16(0xffff);
2169 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2172 /* Only TX ring value reflects actual allocation? TODO */
2173 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2174 bp->pf.evb_mode = resp->evb_mode;
2179 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2184 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2188 rc = bnxt_hwrm_func_qcaps(bp);
2192 bp->pf.func_cfg_flags &=
2193 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2194 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2195 bp->pf.func_cfg_flags |=
2196 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2197 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2201 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2203 struct hwrm_func_cfg_input req = {0};
2204 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2211 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2215 rc = bnxt_hwrm_func_qcaps(bp);
2220 bp->pf.active_vfs = num_vfs;
2223 * First, configure the PF to only use one TX ring. This ensures that
2224 * there are enough rings for all VFs.
2226 * If we don't do this, when we call func_alloc() later, we will lock
2227 * extra rings to the PF that won't be available during func_cfg() of
2230 * This has been fixed with firmware versions above 20.6.54
2232 bp->pf.func_cfg_flags &=
2233 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2234 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2235 bp->pf.func_cfg_flags |=
2236 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2237 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2242 * Now, create and register a buffer to hold forwarded VF requests
2244 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2245 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2246 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2247 if (bp->pf.vf_req_buf == NULL) {
2251 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2252 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2253 for (i = 0; i < num_vfs; i++)
2254 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2255 (i * HWRM_MAX_REQ_LEN);
2257 rc = bnxt_hwrm_func_buf_rgtr(bp);
2261 populate_vf_func_cfg_req(bp, &req, num_vfs);
2263 bp->pf.active_vfs = 0;
2264 for (i = 0; i < num_vfs; i++) {
2265 add_random_mac_if_needed(bp, &req, i);
2267 HWRM_PREP(req, FUNC_CFG, -1, resp);
2268 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2269 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2270 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2272 /* Clear enable flag for next pass */
2273 req.enables &= ~rte_cpu_to_le_32(
2274 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2276 if (rc || resp->error_code) {
2278 "Failed to initizlie VF %d\n", i);
2280 "Not all VFs available. (%d, %d)\n",
2281 rc, resp->error_code);
2285 reserve_resources_from_vf(bp, &req, i);
2286 bp->pf.active_vfs++;
2290 * Now configure the PF to use "the rest" of the resources
2291 * We're using STD_TX_RING_MODE here though which will limit the TX
2292 * rings. This will allow QoS to function properly. Not setting this
2293 * will cause PF rings to break bandwidth settings.
2295 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2299 rc = update_pf_resource_max(bp);
2306 bnxt_hwrm_func_buf_unrgtr(bp);
2310 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2312 struct hwrm_func_cfg_input req = {0};
2313 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2316 HWRM_PREP(req, FUNC_CFG, -1, resp);
2318 req.fid = rte_cpu_to_le_16(0xffff);
2319 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2320 req.evb_mode = bp->pf.evb_mode;
2322 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2328 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2329 uint8_t tunnel_type)
2331 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2332 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2335 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, -1, resp);
2336 req.tunnel_type = tunnel_type;
2337 req.tunnel_dst_port_val = port;
2338 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2341 switch (tunnel_type) {
2342 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2343 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2344 bp->vxlan_port = port;
2346 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2347 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2348 bp->geneve_port = port;
2356 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2357 uint8_t tunnel_type)
2359 struct hwrm_tunnel_dst_port_free_input req = {0};
2360 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2363 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, -1, resp);
2364 req.tunnel_type = tunnel_type;
2365 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2366 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2372 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2375 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2376 struct hwrm_func_cfg_input req = {0};
2379 HWRM_PREP(req, FUNC_CFG, -1, resp);
2380 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2381 req.flags = rte_cpu_to_le_32(flags);
2382 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2388 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2390 uint32_t *flag = flagp;
2392 vnic->flags = *flag;
2395 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2397 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2400 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2403 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2404 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2406 HWRM_PREP(req, FUNC_BUF_RGTR, -1, resp);
2408 req.req_buf_num_pages = rte_cpu_to_le_16(1);
2409 req.req_buf_page_size = rte_cpu_to_le_16(
2410 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2411 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2412 req.req_buf_page_addr[0] =
2413 rte_cpu_to_le_64(rte_mem_virt2phy(bp->pf.vf_req_buf));
2414 if (req.req_buf_page_addr[0] == 0) {
2416 "unable to map buffer address to physical memory\n");
2420 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2427 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2430 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2431 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2433 HWRM_PREP(req, FUNC_BUF_UNRGTR, -1, resp);
2435 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2442 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2444 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2445 struct hwrm_func_cfg_input req = {0};
2448 HWRM_PREP(req, FUNC_CFG, -1, resp);
2449 req.fid = rte_cpu_to_le_16(0xffff);
2450 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2451 req.enables = rte_cpu_to_le_32(
2452 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2453 req.async_event_cr = rte_cpu_to_le_16(
2454 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2455 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2461 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2463 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2464 struct hwrm_func_vf_cfg_input req = {0};
2467 HWRM_PREP(req, FUNC_VF_CFG, -1, resp);
2468 req.enables = rte_cpu_to_le_32(
2469 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2470 req.async_event_cr = rte_cpu_to_le_16(
2471 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2472 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2478 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2480 struct hwrm_func_cfg_input req = {0};
2481 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2482 uint16_t dflt_vlan, fid;
2483 uint32_t func_cfg_flags;
2486 HWRM_PREP(req, FUNC_CFG, -1, resp);
2489 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2490 fid = bp->pf.vf_info[vf].fid;
2491 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2493 fid = rte_cpu_to_le_16(0xffff);
2494 func_cfg_flags = bp->pf.func_cfg_flags;
2495 dflt_vlan = bp->vlan;
2498 req.flags = rte_cpu_to_le_32(func_cfg_flags);
2499 req.fid = rte_cpu_to_le_16(fid);
2500 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2501 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2503 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2509 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2510 uint16_t max_bw, uint16_t enables)
2512 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2513 struct hwrm_func_cfg_input req = {0};
2516 HWRM_PREP(req, FUNC_CFG, -1, resp);
2517 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2518 req.enables |= rte_cpu_to_le_32(enables);
2519 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2520 req.max_bw = rte_cpu_to_le_32(max_bw);
2521 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2527 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2529 struct hwrm_func_cfg_input req = {0};
2530 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2533 HWRM_PREP(req, FUNC_CFG, -1, resp);
2534 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2535 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2536 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2537 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2539 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2545 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2546 void *encaped, size_t ec_size)
2549 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2550 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2552 if (ec_size > sizeof(req.encap_request))
2555 HWRM_PREP(req, REJECT_FWD_RESP, -1, resp);
2557 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2558 memcpy(req.encap_request, encaped, ec_size);
2560 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2567 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2568 struct ether_addr *mac)
2570 struct hwrm_func_qcfg_input req = {0};
2571 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2574 HWRM_PREP(req, FUNC_QCFG, -1, resp);
2575 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2576 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2580 memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2584 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2585 void *encaped, size_t ec_size)
2588 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2589 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2591 if (ec_size > sizeof(req.encap_request))
2594 HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
2596 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2597 memcpy(req.encap_request, encaped, ec_size);
2599 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2606 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2607 struct rte_eth_stats *stats)
2610 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2611 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2613 HWRM_PREP(req, STAT_CTX_QUERY, -1, resp);
2615 req.stat_ctx_id = rte_cpu_to_le_32(cid);
2617 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2621 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2622 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2623 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2624 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2625 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2626 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2628 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2629 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2630 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2631 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2632 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2633 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2635 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2636 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2637 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2642 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2644 struct hwrm_port_qstats_input req = {0};
2645 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2646 struct bnxt_pf_info *pf = &bp->pf;
2649 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2652 HWRM_PREP(req, PORT_QSTATS, -1, resp);
2653 req.port_id = rte_cpu_to_le_16(pf->port_id);
2654 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
2655 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
2656 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2661 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
2663 struct hwrm_port_clr_stats_input req = {0};
2664 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2665 struct bnxt_pf_info *pf = &bp->pf;
2668 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2671 HWRM_PREP(req, PORT_CLR_STATS, -1, resp);
2672 req.port_id = rte_cpu_to_le_16(pf->port_id);
2673 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2678 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
2680 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2681 struct hwrm_port_led_qcaps_input req = {0};
2687 HWRM_PREP(req, PORT_LED_QCAPS, -1, resp);
2688 req.port_id = bp->pf.port_id;
2689 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2692 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
2695 bp->num_leds = resp->num_leds;
2696 memcpy(bp->leds, &resp->led0_id,
2697 sizeof(bp->leds[0]) * bp->num_leds);
2698 for (i = 0; i < bp->num_leds; i++) {
2699 struct bnxt_led_info *led = &bp->leds[i];
2701 uint16_t caps = led->led_state_caps;
2703 if (!led->led_group_id ||
2704 !BNXT_LED_ALT_BLINK_CAP(caps)) {
2713 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
2715 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2716 struct hwrm_port_led_cfg_input req = {0};
2717 struct bnxt_led_cfg *led_cfg;
2718 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
2719 uint16_t duration = 0;
2722 if (!bp->num_leds || BNXT_VF(bp))
2725 HWRM_PREP(req, PORT_LED_CFG, -1, resp);
2727 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
2728 duration = rte_cpu_to_le_16(500);
2730 req.port_id = bp->pf.port_id;
2731 req.num_leds = bp->num_leds;
2732 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
2733 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
2734 req.enables |= BNXT_LED_DFLT_ENABLES(i);
2735 led_cfg->led_id = bp->leds[i].led_id;
2736 led_cfg->led_state = led_state;
2737 led_cfg->led_blink_on = duration;
2738 led_cfg->led_blink_off = duration;
2739 led_cfg->led_group_id = bp->leds[i].led_group_id;
2742 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2749 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
2751 uint32_t *count = cbdata;
2753 *count = *count + 1;
2756 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
2757 struct bnxt_vnic_info *vnic __rte_unused)
2762 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
2766 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
2767 &count, bnxt_vnic_count_hwrm_stub);
2772 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
2775 struct hwrm_func_vf_vnic_ids_query_input req = {0};
2776 struct hwrm_func_vf_vnic_ids_query_output *resp =
2777 bp->hwrm_cmd_resp_addr;
2780 /* First query all VNIC ids */
2781 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, -1, resp_vf_vnic_ids);
2783 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
2784 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
2785 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2phy(vnic_ids));
2787 if (req.vnic_id_tbl_addr == 0) {
2789 "unable to map VNIC ID table address to physical memory\n");
2792 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2794 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
2796 } else if (resp->error_code) {
2797 rc = rte_le_to_cpu_16(resp->error_code);
2798 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query error %d\n", rc);
2802 return rte_le_to_cpu_32(resp->vnic_id_cnt);
2806 * This function queries the VNIC IDs for a specified VF. It then calls
2807 * the vnic_cb to update the necessary field in vnic_info with cbdata.
2808 * Then it calls the hwrm_cb function to program this new vnic configuration.
2810 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
2811 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
2812 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
2814 struct bnxt_vnic_info vnic;
2816 int i, num_vnic_ids;
2821 /* First query all VNIC ids */
2822 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
2823 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
2824 RTE_CACHE_LINE_SIZE);
2825 if (vnic_ids == NULL) {
2829 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
2830 rte_mem_lock_page(((char *)vnic_ids) + sz);
2832 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
2834 if (num_vnic_ids < 0)
2835 return num_vnic_ids;
2837 /* Retrieve VNIC, update bd_stall then update */
2839 for (i = 0; i < num_vnic_ids; i++) {
2840 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
2841 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
2842 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
2845 if (vnic.mru <= 4) /* Indicates unallocated */
2848 vnic_cb(&vnic, cbdata);
2850 rc = hwrm_cb(bp, &vnic);
2860 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
2863 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2864 struct hwrm_func_cfg_input req = {0};
2867 HWRM_PREP(req, FUNC_CFG, -1, resp);
2868 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2869 req.enables |= rte_cpu_to_le_32(
2870 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
2871 req.vlan_antispoof_mode = on ?
2872 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
2873 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
2874 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2880 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
2882 struct bnxt_vnic_info vnic;
2885 int num_vnic_ids, i;
2889 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
2890 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
2891 RTE_CACHE_LINE_SIZE);
2892 if (vnic_ids == NULL) {
2897 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
2898 rte_mem_lock_page(((char *)vnic_ids) + sz);
2900 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
2906 * Loop through to find the default VNIC ID.
2907 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
2908 * by sending the hwrm_func_qcfg command to the firmware.
2910 for (i = 0; i < num_vnic_ids; i++) {
2911 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
2912 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
2913 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
2914 bp->pf.first_vf_id + vf);
2917 if (vnic.func_default) {
2919 return vnic.fw_vnic_id;
2922 /* Could not find a default VNIC. */
2923 RTE_LOG(ERR, PMD, "No default VNIC\n");