drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         timeout = bp->hwrm_cmd_timeout;
 104
 105         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 106             msg_len > bp->max_req_len) {
 107                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 108
 109                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 110                 memcpy(short_cmd_req, req, msg_len);
 111
 112                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 113                 short_input.signature = rte_cpu_to_le_16(
 114                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 115                 short_input.size = rte_cpu_to_le_16(msg_len);
 116                 short_input.req_addr =
 117                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 118
 119                 data = (uint32_t *)&short_input;
 120                 msg_len = sizeof(short_input);
 121
 122                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 123         }
 124
 125         /* Write request msg to hwrm channel */
 126         for (i = 0; i < msg_len; i += 4) {
 127                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 128                 rte_write32(*data, bar);
 129                 data++;
 130         }
 131
 132         /* Zero the rest of the request space */
 133         for (; i < max_req_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 135                 rte_write32(0, bar);
 136         }
 137
 138         /* Ring channel doorbell */
 139         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 140         rte_write32(1, bar);
 141         /*
 142          * Make sure the channel doorbell ring command complete before
 143          * reading the response to avoid getting stale or invalid
 144          * responses.
 145          */
 146         rte_io_mb();
 147
 148         /* Poll for the valid bit */
 149         for (i = 0; i < timeout; i++) {
 150                 /* Sanity check on the resp->resp_len */
 151                 rte_io_rmb();
 152                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 153                         /* Last byte of resp contains the valid key */
 154                         valid = (uint8_t *)resp + resp->resp_len - 1;
 155                         if (*valid == HWRM_RESP_VALID_KEY)
 156                                 break;
 157                 }
 158                 rte_delay_us(1);
 159         }
 160
 161         if (i >= timeout) {
 162                 /* Suppress VER_GET timeout messages during reset recovery */
 163                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 164                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 165                         return -ETIMEDOUT;
 166
 167                 PMD_DRV_LOG(ERR,
 168                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 169                             req->req_type, req->seq_id);
 170                 return -ETIMEDOUT;
 171         }
 172         return 0;
 173 }
 174
 175 /*
 176  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 177  * spinlock, and does initial processing.
 178  *
 179  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 180  * releases the spinlock only if it returns. If the regular int return codes
 181  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 182  * directly, rather it should be copied and modified to suit the function.
 183  *
 184  * HWRM_UNLOCK() must be called after all response processing is completed.
 185  */
 186 #define HWRM_PREP(req, type, kong) do { \
 187         rte_spinlock_lock(&bp->hwrm_lock); \
 188         if (bp->hwrm_cmd_resp_addr == NULL) { \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 return -EACCES; \
 191         } \
 192         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 193         (req)->req_type = rte_cpu_to_le_16(type); \
 194         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 195         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 196                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 197         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 198         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 199 } while (0)
 200
 201 #define HWRM_CHECK_RESULT_SILENT() do {\
 202         if (rc) { \
 203                 rte_spinlock_unlock(&bp->hwrm_lock); \
 204                 return rc; \
 205         } \
 206         if (resp->error_code) { \
 207                 rc = rte_le_to_cpu_16(resp->error_code); \
 208                 rte_spinlock_unlock(&bp->hwrm_lock); \
 209                 return rc; \
 210         } \
 211 } while (0)
 212
 213 #define HWRM_CHECK_RESULT() do {\
 214         if (rc) { \
 215                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 216                 rte_spinlock_unlock(&bp->hwrm_lock); \
 217                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 218                         rc = -EACCES; \
 219                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 220                         rc = -ENOSPC; \
 221                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 222                         rc = -EINVAL; \
 223                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 224                         rc = -ENOTSUP; \
 225                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 226                         rc = -EAGAIN; \
 227                 else if (rc > 0) \
 228                         rc = -EIO; \
 229                 return rc; \
 230         } \
 231         if (resp->error_code) { \
 232                 rc = rte_le_to_cpu_16(resp->error_code); \
 233                 if (resp->resp_len >= 16) { \
 234                         struct hwrm_err_output *tmp_hwrm_err_op = \
 235                                                 (void *)resp; \
 236                         PMD_DRV_LOG(ERR, \
 237                                 "error %d:%d:%08x:%04x\n", \
 238                                 rc, tmp_hwrm_err_op->cmd_err, \
 239                                 rte_le_to_cpu_32(\
 240                                         tmp_hwrm_err_op->opaque_0), \
 241                                 rte_le_to_cpu_16(\
 242                                         tmp_hwrm_err_op->opaque_1)); \
 243                 } else { \
 244                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 245                 } \
 246                 rte_spinlock_unlock(&bp->hwrm_lock); \
 247                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 248                         rc = -EACCES; \
 249                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 250                         rc = -ENOSPC; \
 251                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 252                         rc = -EINVAL; \
 253                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 254                         rc = -ENOTSUP; \
 255                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 256                         rc = -EAGAIN; \
 257                 else if (rc > 0) \
 258                         rc = -EIO; \
 259                 return rc; \
 260         } \
 261 } while (0)
 262
 263 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 264
 265 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 266                                 bool use_kong_mb,
 267                                 uint16_t msg_type,
 268                                 void *msg,
 269                                 uint32_t msg_len,
 270                                 void *resp_msg,
 271                                 uint32_t resp_len)
 272 {
 273         int rc = 0;
 274         bool mailbox = BNXT_USE_CHIMP_MB;
 275         struct input *req = msg;
 276         struct output *resp = bp->hwrm_cmd_resp_addr;
 277
 278         if (use_kong_mb)
 279                 mailbox = BNXT_USE_KONG(bp);
 280
 281         HWRM_PREP(req, msg_type, mailbox);
 282
 283         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 284
 285         HWRM_CHECK_RESULT();
 286
 287         if (resp_msg)
 288                 memcpy(resp_msg, resp, resp_len);
 289
 290         HWRM_UNLOCK();
 291
 292         return rc;
 293 }
 294
 295 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 296                                   bool use_kong_mb,
 297                                   uint16_t tf_type,
 298                                   uint16_t tf_subtype,
 299                                   uint32_t *tf_response_code,
 300                                   void *msg,
 301                                   uint32_t msg_len,
 302                                   void *response,
 303                                   uint32_t response_len)
 304 {
 305         int rc = 0;
 306         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 307         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 308         bool mailbox = BNXT_USE_CHIMP_MB;
 309
 310         if (msg_len > sizeof(req.tf_req))
 311                 return -ENOMEM;
 312
 313         if (use_kong_mb)
 314                 mailbox = BNXT_USE_KONG(bp);
 315
 316         HWRM_PREP(&req, HWRM_TF, mailbox);
 317         /* Build request using the user supplied request payload.
 318          * TLV request size is checked at build time against HWRM
 319          * request max size, thus no checking required.
 320          */
 321         req.tf_type = tf_type;
 322         req.tf_subtype = tf_subtype;
 323         memcpy(req.tf_req, msg, msg_len);
 324
 325         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 326         HWRM_CHECK_RESULT();
 327
 328         /* Copy the resp to user provided response buffer */
 329         if (response != NULL)
 330                 /* Post process response data. We need to copy only
 331                  * the 'payload' as the HWRM data structure really is
 332                  * HWRM header + msg header + payload and the TFLIB
 333                  * only provided a payload place holder.
 334                  */
 335                 if (response_len != 0) {
 336                         memcpy(response,
 337                                resp->tf_resp,
 338                                response_len);
 339                 }
 340
 341         /* Extract the internal tflib response code */
 342         *tf_response_code = resp->tf_resp_code;
 343         HWRM_UNLOCK();
 344
 345         return rc;
 346 }
 347
 348 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 349 {
 350         int rc = 0;
 351         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 352         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 353
 354         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 355         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 356         req.mask = 0;
 357
 358         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 359
 360         HWRM_CHECK_RESULT();
 361         HWRM_UNLOCK();
 362
 363         return rc;
 364 }
 365
 366 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 367                                  struct bnxt_vnic_info *vnic,
 368                                  uint16_t vlan_count,
 369                                  struct bnxt_vlan_table_entry *vlan_table)
 370 {
 371         int rc = 0;
 372         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 373         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 374         uint32_t mask = 0;
 375
 376         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 377                 return rc;
 378
 379         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 380         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 381
 382         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 383                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 384         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 385                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 386
 387         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 388                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 389
 390         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 391                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 392         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 393                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 394                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 395                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 396         }
 397         if (vlan_table) {
 398                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 399                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 400                 req.vlan_tag_tbl_addr =
 401                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 402                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 403         }
 404         req.mask = rte_cpu_to_le_32(mask);
 405
 406         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 407
 408         HWRM_CHECK_RESULT();
 409         HWRM_UNLOCK();
 410
 411         return rc;
 412 }
 413
 414 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 415                         uint16_t vlan_count,
 416                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 417 {
 418         int rc = 0;
 419         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 420         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 421                                                 bp->hwrm_cmd_resp_addr;
 422
 423         /*
 424          * Older HWRM versions did not support this command, and the set_rx_mask
 425          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 426          * removed from set_rx_mask call, and this command was added.
 427          *
 428          * This command is also present from 1.7.8.11 and higher,
 429          * as well as 1.7.8.0
 430          */
 431         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 432                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 433                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 434                                         (11)))
 435                                 return 0;
 436                 }
 437         }
 438         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 439         req.fid = rte_cpu_to_le_16(fid);
 440
 441         req.vlan_tag_mask_tbl_addr =
 442                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 443         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 444
 445         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 446
 447         HWRM_CHECK_RESULT();
 448         HWRM_UNLOCK();
 449
 450         return rc;
 451 }
 452
 453 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 454                              struct bnxt_filter_info *filter)
 455 {
 456         int rc = 0;
 457         struct bnxt_filter_info *l2_filter = filter;
 458         struct bnxt_vnic_info *vnic = NULL;
 459         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 460         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 461
 462         if (filter->fw_l2_filter_id == UINT64_MAX)
 463                 return 0;
 464
 465         if (filter->matching_l2_fltr_ptr)
 466                 l2_filter = filter->matching_l2_fltr_ptr;
 467
 468         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 469                     filter, l2_filter, l2_filter->l2_ref_cnt);
 470
 471         if (l2_filter->l2_ref_cnt == 0)
 472                 return 0;
 473
 474         if (l2_filter->l2_ref_cnt > 0)
 475                 l2_filter->l2_ref_cnt--;
 476
 477         if (l2_filter->l2_ref_cnt > 0)
 478                 return 0;
 479
 480         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 481
 482         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 483
 484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 485
 486         HWRM_CHECK_RESULT();
 487         HWRM_UNLOCK();
 488
 489         filter->fw_l2_filter_id = UINT64_MAX;
 490         if (l2_filter->l2_ref_cnt == 0) {
 491                 vnic = l2_filter->vnic;
 492                 if (vnic) {
 493                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 494                                       bnxt_filter_info, next);
 495                         bnxt_free_filter(bp, l2_filter);
 496                 }
 497         }
 498
 499         return 0;
 500 }
 501
 502 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 503                          uint16_t dst_id,
 504                          struct bnxt_filter_info *filter)
 505 {
 506         int rc = 0;
 507         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 508         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 509         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 510         const struct rte_eth_vmdq_rx_conf *conf =
 511                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 512         uint32_t enables = 0;
 513         uint16_t j = dst_id - 1;
 514
 515         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 516         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 517             conf->pool_map[j].pools & (1UL << j)) {
 518                 PMD_DRV_LOG(DEBUG,
 519                         "Add vlan %u to vmdq pool %u\n",
 520                         conf->pool_map[j].vlan_id, j);
 521
 522                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 523                 filter->enables |=
 524                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 525                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 526         }
 527
 528         if (filter->fw_l2_filter_id != UINT64_MAX)
 529                 bnxt_hwrm_clear_l2_filter(bp, filter);
 530
 531         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 532
 533         /* PMD does not support XDP and RoCE */
 534         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 535                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 536         req.flags = rte_cpu_to_le_32(filter->flags);
 537
 538         enables = filter->enables |
 539               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 540         req.dst_id = rte_cpu_to_le_16(dst_id);
 541
 542         if (enables &
 543             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 544                 memcpy(req.l2_addr, filter->l2_addr,
 545                        RTE_ETHER_ADDR_LEN);
 546         if (enables &
 547             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 548                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 549                        RTE_ETHER_ADDR_LEN);
 550         if (enables &
 551             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 552                 req.l2_ovlan = filter->l2_ovlan;
 553         if (enables &
 554             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 555                 req.l2_ivlan = filter->l2_ivlan;
 556         if (enables &
 557             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 558                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 559         if (enables &
 560             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 561                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 562         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 563                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 564         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 565                 req.src_type = filter->src_type;
 566         if (filter->pri_hint) {
 567                 req.pri_hint = filter->pri_hint;
 568                 req.l2_filter_id_hint =
 569                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 570         }
 571
 572         req.enables = rte_cpu_to_le_32(enables);
 573
 574         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 575
 576         HWRM_CHECK_RESULT();
 577
 578         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 579         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 580         HWRM_UNLOCK();
 581
 582         filter->l2_ref_cnt++;
 583
 584         return rc;
 585 }
 586
 587 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 588 {
 589         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 590         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 591         uint32_t flags = 0;
 592         int rc;
 593
 594         if (!ptp)
 595                 return 0;
 596
 597         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 598
 599         if (ptp->rx_filter)
 600                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 601         else
 602                 flags |=
 603                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 604         if (ptp->tx_tstamp_en)
 605                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 606         else
 607                 flags |=
 608                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 609         req.flags = rte_cpu_to_le_32(flags);
 610         req.enables = rte_cpu_to_le_32
 611                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 612         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 613
 614         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 615         HWRM_UNLOCK();
 616
 617         return rc;
 618 }
 619
 620 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 621 {
 622         int rc = 0;
 623         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 624         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 625         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 626
 627         if (ptp)
 628                 return 0;
 629
 630         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 631
 632         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 633
 634         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 635
 636         HWRM_CHECK_RESULT();
 637
 638         if (!BNXT_CHIP_P5(bp) &&
 639             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 640                 return 0;
 641
 642         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 643                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 644
 645         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 646         if (!ptp)
 647                 return -ENOMEM;
 648
 649         if (!BNXT_CHIP_P5(bp)) {
 650                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 651                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 652                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 653                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 654                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 655                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 656                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 657                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 658                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 659                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 660                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 661                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 662                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 663                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 664                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 665                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 666                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 667                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 668         }
 669
 670         ptp->bp = bp;
 671         bp->ptp_cfg = ptp;
 672
 673         return 0;
 674 }
 675
 676 void bnxt_hwrm_free_vf_info(struct bnxt *bp)
 677 {
 678         int i;
 679
 680         for (i = 0; i < bp->pf->max_vfs; i++) {
 681                 rte_free(bp->pf->vf_info[i].vlan_table);
 682                 bp->pf->vf_info[i].vlan_table = NULL;
 683                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 684                 bp->pf->vf_info[i].vlan_as_table = NULL;
 685         }
 686         rte_free(bp->pf->vf_info);
 687         bp->pf->vf_info = NULL;
 688 }
 689
 690 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 691 {
 692         int rc = 0;
 693         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 694         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 695         uint16_t new_max_vfs;
 696         uint32_t flags;
 697         int i;
 698
 699         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 700
 701         req.fid = rte_cpu_to_le_16(0xffff);
 702
 703         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 704
 705         HWRM_CHECK_RESULT();
 706
 707         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 708         flags = rte_le_to_cpu_32(resp->flags);
 709         if (BNXT_PF(bp)) {
 710                 bp->pf->port_id = resp->port_id;
 711                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 712                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 713                 new_max_vfs = bp->pdev->max_vfs;
 714                 if (new_max_vfs != bp->pf->max_vfs) {
 715                         if (bp->pf->vf_info)
 716                                 bnxt_hwrm_free_vf_info(bp);
 717                         bp->pf->vf_info = rte_zmalloc("bnxt_vf_info",
 718                             sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
 719                         if (bp->pf->vf_info == NULL) {
 720                                 PMD_DRV_LOG(ERR, "Alloc vf info fail\n");
 721                                 HWRM_UNLOCK();
 722                                 return -ENOMEM;
 723                         }
 724                         bp->pf->max_vfs = new_max_vfs;
 725                         for (i = 0; i < new_max_vfs; i++) {
 726                                 bp->pf->vf_info[i].fid =
 727                                         bp->pf->first_vf_id + i;
 728                                 bp->pf->vf_info[i].vlan_table =
 729                                         rte_zmalloc("VF VLAN table",
 730                                                     getpagesize(),
 731                                                     getpagesize());
 732                                 if (bp->pf->vf_info[i].vlan_table == NULL)
 733                                         PMD_DRV_LOG(ERR,
 734                                         "Fail to alloc VLAN table for VF %d\n",
 735                                         i);
 736                                 else
 737                                         rte_mem_lock_page(
 738                                                 bp->pf->vf_info[i].vlan_table);
 739                                 bp->pf->vf_info[i].vlan_as_table =
 740                                         rte_zmalloc("VF VLAN AS table",
 741                                                     getpagesize(),
 742                                                     getpagesize());
 743                                 if (bp->pf->vf_info[i].vlan_as_table == NULL)
 744                                         PMD_DRV_LOG(ERR,
 745                                         "Alloc VLAN AS table for VF %d fail\n",
 746                                         i);
 747                                 else
 748                                         rte_mem_lock_page(
 749                                               bp->pf->vf_info[i].vlan_as_table);
 750                                 STAILQ_INIT(&bp->pf->vf_info[i].filter);
 751                         }
 752                 }
 753         }
 754
 755         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 756         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 757                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 758                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 759         } else {
 760                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 761         }
 762         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 763         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 764         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 765         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 766         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 767         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 768         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 769         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
 770                 bp->max_l2_ctx += bp->max_rx_em_flows;
 771         /* TODO: For now, do not support VMDq/RFS on VFs. */
 772         if (BNXT_PF(bp)) {
 773                 if (bp->pf->max_vfs)
 774                         bp->max_vnics = 1;
 775                 else
 776                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 777         } else {
 778                 bp->max_vnics = 1;
 779         }
 780         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 781                     bp->max_l2_ctx, bp->max_vnics);
 782         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 783         if (BNXT_PF(bp)) {
 784                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 785                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 786                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 787                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 788                         HWRM_UNLOCK();
 789                         bnxt_hwrm_ptp_qcfg(bp);
 790                 }
 791         }
 792
 793         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 794                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 795
 796         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 797                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 798                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 799         }
 800
 801         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 802                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 803
 804         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 805                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 806
 807         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
 808                 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
 809
 810         HWRM_UNLOCK();
 811
 812         return rc;
 813 }
 814
 815 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 816 {
 817         int rc;
 818
 819         rc = __bnxt_hwrm_func_qcaps(bp);
 820         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 821                 rc = bnxt_alloc_ctx_mem(bp);
 822                 if (rc)
 823                         return rc;
 824
 825                 /* On older FW,
 826                  * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 827                  * But the error can be ignored. Return success.
 828                  */
 829                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 830                 if (!rc)
 831                         bp->flags |= BNXT_FLAG_NEW_RM;
 832         }
 833
 834         return 0;
 835 }
 836
 837 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 838 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 839 {
 840         int rc = 0;
 841         uint32_t flags;
 842         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 843         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 844
 845         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 846
 847         req.target_id = rte_cpu_to_le_16(0xffff);
 848
 849         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 850
 851         HWRM_CHECK_RESULT();
 852
 853         flags = rte_le_to_cpu_32(resp->flags);
 854
 855         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 856                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 857                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 858         }
 859
 860         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
 861                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
 862
 863         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 864
 865         HWRM_UNLOCK();
 866
 867         return rc;
 868 }
 869
 870 int bnxt_hwrm_func_reset(struct bnxt *bp)
 871 {
 872         int rc = 0;
 873         struct hwrm_func_reset_input req = {.req_type = 0 };
 874         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 875
 876         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
 877
 878         req.enables = rte_cpu_to_le_32(0);
 879
 880         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 881
 882         HWRM_CHECK_RESULT();
 883         HWRM_UNLOCK();
 884
 885         return rc;
 886 }
 887
 888 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 889 {
 890         int rc;
 891         uint32_t flags = 0;
 892         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 893         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 894
 895         if (bp->flags & BNXT_FLAG_REGISTERED)
 896                 return 0;
 897
 898         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 899                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 900         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 901                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 902
 903         /* PFs and trusted VFs should indicate the support of the
 904          * Master capability on non Stingray platform
 905          */
 906         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 907                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 908
 909         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 910         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 911                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 912         req.ver_maj = RTE_VER_YEAR;
 913         req.ver_min = RTE_VER_MONTH;
 914         req.ver_upd = RTE_VER_MINOR;
 915
 916         if (BNXT_PF(bp)) {
 917                 req.enables |= rte_cpu_to_le_32(
 918                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 919                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
 920                        RTE_MIN(sizeof(req.vf_req_fwd),
 921                                sizeof(bp->pf->vf_req_fwd)));
 922         }
 923
 924         req.flags = rte_cpu_to_le_32(flags);
 925
 926         req.async_event_fwd[0] |=
 927                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 928                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 929                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 930                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 931                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 932         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 933                 req.async_event_fwd[0] |=
 934                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 935         req.async_event_fwd[1] |=
 936                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 937                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 938         if (BNXT_PF(bp))
 939                 req.async_event_fwd[1] |=
 940                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 941
 942         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
 943                 req.async_event_fwd[1] |=
 944                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
 945
 946         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 947
 948         HWRM_CHECK_RESULT();
 949
 950         flags = rte_le_to_cpu_32(resp->flags);
 951         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 952                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 953
 954         HWRM_UNLOCK();
 955
 956         bp->flags |= BNXT_FLAG_REGISTERED;
 957
 958         return rc;
 959 }
 960
 961 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 962 {
 963         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 964                 return 0;
 965
 966         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 967 }
 968
 969 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 970 {
 971         int rc;
 972         uint32_t flags = 0;
 973         uint32_t enables;
 974         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 975         struct hwrm_func_vf_cfg_input req = {0};
 976
 977         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 978
 979         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 980                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 981                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 982                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 983                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 984
 985         if (BNXT_HAS_RING_GRPS(bp)) {
 986                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 987                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 988         }
 989
 990         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 991         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 992                                             AGG_RING_MULTIPLIER);
 993         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 994         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 995                                               bp->tx_nr_rings +
 996                                               BNXT_NUM_ASYNC_CPR(bp));
 997         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 998         if (bp->vf_resv_strategy ==
 999             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1000                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1001                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1002                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1003                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1004                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1005                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1006         } else if (bp->vf_resv_strategy ==
1007                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1008                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1009                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1010         }
1011
1012         if (test)
1013                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1014                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1015                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1016                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1017                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1018                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1019
1020         if (test && BNXT_HAS_RING_GRPS(bp))
1021                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1022
1023         req.flags = rte_cpu_to_le_32(flags);
1024         req.enables |= rte_cpu_to_le_32(enables);
1025
1026         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1027
1028         if (test)
1029                 HWRM_CHECK_RESULT_SILENT();
1030         else
1031                 HWRM_CHECK_RESULT();
1032
1033         HWRM_UNLOCK();
1034         return rc;
1035 }
1036
1037 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1038 {
1039         int rc;
1040         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1041         struct hwrm_func_resource_qcaps_input req = {0};
1042
1043         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1044         req.fid = rte_cpu_to_le_16(0xffff);
1045
1046         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1047
1048         HWRM_CHECK_RESULT_SILENT();
1049
1050         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1051         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1052         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1053         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1054         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1055         /* func_resource_qcaps does not return max_rx_em_flows.
1056          * So use the value provided by func_qcaps.
1057          */
1058         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1059         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1060                 bp->max_l2_ctx += bp->max_rx_em_flows;
1061         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1062         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1063         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1064         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1065         if (bp->vf_resv_strategy >
1066             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1067                 bp->vf_resv_strategy =
1068                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1069
1070         HWRM_UNLOCK();
1071         return rc;
1072 }
1073
1074 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1075 {
1076         int rc = 0;
1077         struct hwrm_ver_get_input req = {.req_type = 0 };
1078         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1079         uint32_t fw_version;
1080         uint16_t max_resp_len;
1081         char type[RTE_MEMZONE_NAMESIZE];
1082         uint32_t dev_caps_cfg;
1083
1084         bp->max_req_len = HWRM_MAX_REQ_LEN;
1085         bp->hwrm_cmd_timeout = timeout;
1086         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1087
1088         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1089         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1090         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1091
1092         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1093
1094         if (bp->flags & BNXT_FLAG_FW_RESET)
1095                 HWRM_CHECK_RESULT_SILENT();
1096         else
1097                 HWRM_CHECK_RESULT();
1098
1099         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1100                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1101                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1102                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1103         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1104                      (resp->hwrm_fw_min_8b << 16) |
1105                      (resp->hwrm_fw_bld_8b << 8) |
1106                      resp->hwrm_fw_rsvd_8b;
1107         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1108                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1109
1110         fw_version = resp->hwrm_intf_maj_8b << 16;
1111         fw_version |= resp->hwrm_intf_min_8b << 8;
1112         fw_version |= resp->hwrm_intf_upd_8b;
1113         bp->hwrm_spec_code = fw_version;
1114
1115         /* def_req_timeout value is in milliseconds */
1116         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1117         /* convert timeout to usec */
1118         bp->hwrm_cmd_timeout *= 1000;
1119         if (!bp->hwrm_cmd_timeout)
1120                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1121
1122         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1123                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1124                 rc = -EINVAL;
1125                 goto error;
1126         }
1127
1128         if (bp->max_req_len > resp->max_req_win_len) {
1129                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1130                 rc = -EINVAL;
1131         }
1132         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1133         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1134         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1135                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1136
1137         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1138         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1139
1140         if (bp->max_resp_len != max_resp_len) {
1141                 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1142                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1143                         bp->pdev->addr.devid, bp->pdev->addr.function);
1144
1145                 rte_free(bp->hwrm_cmd_resp_addr);
1146
1147                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1148                 if (bp->hwrm_cmd_resp_addr == NULL) {
1149                         rc = -ENOMEM;
1150                         goto error;
1151                 }
1152                 bp->hwrm_cmd_resp_dma_addr =
1153                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1154                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1155                         PMD_DRV_LOG(ERR,
1156                         "Unable to map response buffer to physical memory.\n");
1157                         rc = -ENOMEM;
1158                         goto error;
1159                 }
1160                 bp->max_resp_len = max_resp_len;
1161         }
1162
1163         if ((dev_caps_cfg &
1164                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1165             (dev_caps_cfg &
1166              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1167                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1168                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1169         }
1170
1171         if (((dev_caps_cfg &
1172               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1173              (dev_caps_cfg &
1174               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1175             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1176                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1177                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1178                         bp->pdev->addr.devid, bp->pdev->addr.function);
1179
1180                 rte_free(bp->hwrm_short_cmd_req_addr);
1181
1182                 bp->hwrm_short_cmd_req_addr =
1183                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1184                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1185                         rc = -ENOMEM;
1186                         goto error;
1187                 }
1188                 bp->hwrm_short_cmd_req_dma_addr =
1189                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1190                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1191                         rte_free(bp->hwrm_short_cmd_req_addr);
1192                         PMD_DRV_LOG(ERR,
1193                                 "Unable to map buffer to physical memory.\n");
1194                         rc = -ENOMEM;
1195                         goto error;
1196                 }
1197         }
1198         if (dev_caps_cfg &
1199             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1200                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1201                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1202         }
1203         if (dev_caps_cfg &
1204             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1205                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1206         if (dev_caps_cfg &
1207             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1208                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1209                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1210         }
1211
1212         if (dev_caps_cfg &
1213             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1214                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1215                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1216         }
1217
1218
1219 error:
1220         HWRM_UNLOCK();
1221         return rc;
1222 }
1223
1224 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1225 {
1226         int rc;
1227         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1228         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1229
1230         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1231                 return 0;
1232
1233         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1234         req.flags = flags;
1235
1236         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1237
1238         HWRM_CHECK_RESULT();
1239         HWRM_UNLOCK();
1240
1241         return rc;
1242 }
1243
1244 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1245 {
1246         int rc = 0;
1247         struct hwrm_port_phy_cfg_input req = {0};
1248         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1249         uint32_t enables = 0;
1250
1251         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1252
1253         if (conf->link_up) {
1254                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1255                 if (bp->link_info->auto_mode && conf->link_speed) {
1256                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1257                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1258                 }
1259
1260                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1261                 /*
1262                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1263                  * any auto mode, even "none".
1264                  */
1265                 if (!conf->link_speed) {
1266                         /* No speeds specified. Enable AutoNeg - all speeds */
1267                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1268                         req.auto_mode =
1269                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1270                 } else {
1271                         if (bp->link_info->link_signal_mode) {
1272                                 enables |=
1273                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1274                                 req.force_pam4_link_speed =
1275                                         rte_cpu_to_le_16(conf->link_speed);
1276                         } else {
1277                                 req.force_link_speed =
1278                                         rte_cpu_to_le_16(conf->link_speed);
1279                         }
1280                 }
1281                 /* AutoNeg - Advertise speeds specified. */
1282                 if (conf->auto_link_speed_mask &&
1283                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1284                         req.auto_mode =
1285                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1286                         req.auto_link_speed_mask =
1287                                 conf->auto_link_speed_mask;
1288                         if (conf->auto_pam4_link_speeds) {
1289                                 enables |=
1290                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1291                                 req.auto_link_pam4_speed_mask =
1292                                         conf->auto_pam4_link_speeds;
1293                         } else {
1294                                 enables |=
1295                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1296                         }
1297                 }
1298                 if (conf->auto_link_speed &&
1299                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1300                         enables |=
1301                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1302
1303                 req.auto_duplex = conf->duplex;
1304                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1305                 req.auto_pause = conf->auto_pause;
1306                 req.force_pause = conf->force_pause;
1307                 /* Set force_pause if there is no auto or if there is a force */
1308                 if (req.auto_pause && !req.force_pause)
1309                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1310                 else
1311                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1312
1313                 req.enables = rte_cpu_to_le_32(enables);
1314         } else {
1315                 req.flags =
1316                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1317                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1318         }
1319
1320         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1321
1322         HWRM_CHECK_RESULT();
1323         HWRM_UNLOCK();
1324
1325         return rc;
1326 }
1327
1328 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1329                                    struct bnxt_link_info *link_info)
1330 {
1331         int rc = 0;
1332         struct hwrm_port_phy_qcfg_input req = {0};
1333         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1334
1335         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1336
1337         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1338
1339         HWRM_CHECK_RESULT();
1340
1341         link_info->phy_link_status = resp->link;
1342         link_info->link_up =
1343                 (link_info->phy_link_status ==
1344                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1345         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1346         link_info->duplex = resp->duplex_cfg;
1347         link_info->pause = resp->pause;
1348         link_info->auto_pause = resp->auto_pause;
1349         link_info->force_pause = resp->force_pause;
1350         link_info->auto_mode = resp->auto_mode;
1351         link_info->phy_type = resp->phy_type;
1352         link_info->media_type = resp->media_type;
1353
1354         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1355         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1356         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1357         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1358         link_info->phy_ver[0] = resp->phy_maj;
1359         link_info->phy_ver[1] = resp->phy_min;
1360         link_info->phy_ver[2] = resp->phy_bld;
1361         link_info->link_signal_mode =
1362                 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1363         link_info->force_pam4_link_speed =
1364                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1365         link_info->support_pam4_speeds =
1366                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1367         link_info->auto_pam4_link_speeds =
1368                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1369         HWRM_UNLOCK();
1370
1371         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1372                     link_info->link_speed, link_info->auto_mode,
1373                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1374                     link_info->support_speeds, link_info->force_link_speed);
1375         PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1376                     link_info->link_signal_mode,
1377                     link_info->auto_pam4_link_speeds,
1378                     link_info->support_pam4_speeds,
1379                     link_info->force_pam4_link_speed);
1380         return rc;
1381 }
1382
1383 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1384 {
1385         int rc = 0;
1386         struct hwrm_port_phy_qcaps_input req = {0};
1387         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1388         struct bnxt_link_info *link_info = bp->link_info;
1389
1390         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1391                 return 0;
1392
1393         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1394
1395         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1396
1397         HWRM_CHECK_RESULT();
1398
1399         bp->port_cnt = resp->port_cnt;
1400         if (resp->supported_speeds_auto_mode)
1401                 link_info->support_auto_speeds =
1402                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1403         if (resp->supported_pam4_speeds_auto_mode)
1404                 link_info->support_pam4_auto_speeds =
1405                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1406
1407         HWRM_UNLOCK();
1408
1409         return 0;
1410 }
1411
1412 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1413 {
1414         int i = 0;
1415
1416         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1417                 if (bp->tx_cos_queue[i].profile ==
1418                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1419                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1420                         return true;
1421                 }
1422         }
1423         return false;
1424 }
1425
1426 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1427 {
1428         int i = 0;
1429
1430         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1431                 if (bp->tx_cos_queue[i].profile !=
1432                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1433                     bp->tx_cos_queue[i].id !=
1434                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1435                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1436                         break;
1437                 }
1438         }
1439 }
1440
1441 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1442 {
1443         int rc = 0;
1444         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1445         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1446         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1447         int i;
1448
1449 get_rx_info:
1450         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1451
1452         req.flags = rte_cpu_to_le_32(dir);
1453         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1454         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1455             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1456                 req.drv_qmap_cap =
1457                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1458         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1459
1460         HWRM_CHECK_RESULT();
1461
1462         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1463                 GET_TX_QUEUE_INFO(0);
1464                 GET_TX_QUEUE_INFO(1);
1465                 GET_TX_QUEUE_INFO(2);
1466                 GET_TX_QUEUE_INFO(3);
1467                 GET_TX_QUEUE_INFO(4);
1468                 GET_TX_QUEUE_INFO(5);
1469                 GET_TX_QUEUE_INFO(6);
1470                 GET_TX_QUEUE_INFO(7);
1471         } else  {
1472                 GET_RX_QUEUE_INFO(0);
1473                 GET_RX_QUEUE_INFO(1);
1474                 GET_RX_QUEUE_INFO(2);
1475                 GET_RX_QUEUE_INFO(3);
1476                 GET_RX_QUEUE_INFO(4);
1477                 GET_RX_QUEUE_INFO(5);
1478                 GET_RX_QUEUE_INFO(6);
1479                 GET_RX_QUEUE_INFO(7);
1480         }
1481
1482         HWRM_UNLOCK();
1483
1484         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1485                 goto done;
1486
1487         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1488                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1489         } else {
1490                 int j;
1491
1492                 /* iterate and find the COSq profile to use for Tx */
1493                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1494                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1495                                 if (bp->tx_cos_queue[i].id != 0xff)
1496                                         bp->tx_cosq_id[j++] =
1497                                                 bp->tx_cos_queue[i].id;
1498                         }
1499                 } else {
1500                         /* When CoS classification is disabled, for normal NIC
1501                          * operations, ideally we should look to use LOSSY.
1502                          * If not found, fallback to the first valid profile
1503                          */
1504                         if (!bnxt_find_lossy_profile(bp))
1505                                 bnxt_find_first_valid_profile(bp);
1506
1507                 }
1508         }
1509
1510         bp->max_tc = resp->max_configurable_queues;
1511         bp->max_lltc = resp->max_configurable_lossless_queues;
1512         if (bp->max_tc > BNXT_MAX_QUEUE)
1513                 bp->max_tc = BNXT_MAX_QUEUE;
1514         bp->max_q = bp->max_tc;
1515
1516         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1517                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1518                 goto get_rx_info;
1519         }
1520
1521 done:
1522         return rc;
1523 }
1524
1525 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1526                          struct bnxt_ring *ring,
1527                          uint32_t ring_type, uint32_t map_index,
1528                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1529                          uint16_t tx_cosq_id)
1530 {
1531         int rc = 0;
1532         uint32_t enables = 0;
1533         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1534         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1535         struct rte_mempool *mb_pool;
1536         uint16_t rx_buf_size;
1537
1538         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1539
1540         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1541         req.fbo = rte_cpu_to_le_32(0);
1542         /* Association of ring index with doorbell index */
1543         req.logical_id = rte_cpu_to_le_16(map_index);
1544         req.length = rte_cpu_to_le_32(ring->ring_size);
1545
1546         switch (ring_type) {
1547         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1548                 req.ring_type = ring_type;
1549                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1550                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1551                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1552                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1553                         enables |=
1554                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1555                 break;
1556         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1557                 req.ring_type = ring_type;
1558                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1559                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1560                 if (BNXT_CHIP_P5(bp)) {
1561                         mb_pool = bp->rx_queues[0]->mb_pool;
1562                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1563                                       RTE_PKTMBUF_HEADROOM;
1564                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1565                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1566                         enables |=
1567                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1568                 }
1569                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1570                         enables |=
1571                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1572                 break;
1573         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1574                 req.ring_type = ring_type;
1575                 if (BNXT_HAS_NQ(bp)) {
1576                         /* Association of cp ring with nq */
1577                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1578                         enables |=
1579                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1580                 }
1581                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1582                 break;
1583         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1584                 req.ring_type = ring_type;
1585                 req.page_size = BNXT_PAGE_SHFT;
1586                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1587                 break;
1588         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1589                 req.ring_type = ring_type;
1590                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1591
1592                 mb_pool = bp->rx_queues[0]->mb_pool;
1593                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1594                               RTE_PKTMBUF_HEADROOM;
1595                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1596                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1597
1598                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1599                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1600                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1601                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1602                 break;
1603         default:
1604                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1605                         ring_type);
1606                 HWRM_UNLOCK();
1607                 return -EINVAL;
1608         }
1609         req.enables = rte_cpu_to_le_32(enables);
1610
1611         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1612
1613         if (rc || resp->error_code) {
1614                 if (rc == 0 && resp->error_code)
1615                         rc = rte_le_to_cpu_16(resp->error_code);
1616                 switch (ring_type) {
1617                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1618                         PMD_DRV_LOG(ERR,
1619                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1620                         HWRM_UNLOCK();
1621                         return rc;
1622                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1623                         PMD_DRV_LOG(ERR,
1624                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1625                         HWRM_UNLOCK();
1626                         return rc;
1627                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1628                         PMD_DRV_LOG(ERR,
1629                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1630                                     rc);
1631                         HWRM_UNLOCK();
1632                         return rc;
1633                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1634                         PMD_DRV_LOG(ERR,
1635                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1636                         HWRM_UNLOCK();
1637                         return rc;
1638                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1639                         PMD_DRV_LOG(ERR,
1640                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1641                         HWRM_UNLOCK();
1642                         return rc;
1643                 default:
1644                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1645                         HWRM_UNLOCK();
1646                         return rc;
1647                 }
1648         }
1649
1650         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1651         HWRM_UNLOCK();
1652         return rc;
1653 }
1654
1655 int bnxt_hwrm_ring_free(struct bnxt *bp,
1656                         struct bnxt_ring *ring, uint32_t ring_type)
1657 {
1658         int rc;
1659         struct hwrm_ring_free_input req = {.req_type = 0 };
1660         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1661
1662         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1663
1664         req.ring_type = ring_type;
1665         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1666
1667         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1668
1669         if (rc || resp->error_code) {
1670                 if (rc == 0 && resp->error_code)
1671                         rc = rte_le_to_cpu_16(resp->error_code);
1672                 HWRM_UNLOCK();
1673
1674                 switch (ring_type) {
1675                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1676                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1677                                 rc);
1678                         return rc;
1679                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1680                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1681                                 rc);
1682                         return rc;
1683                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1684                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1685                                 rc);
1686                         return rc;
1687                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1688                         PMD_DRV_LOG(ERR,
1689                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1690                         return rc;
1691                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1692                         PMD_DRV_LOG(ERR,
1693                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1694                         return rc;
1695                 default:
1696                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1697                         return rc;
1698                 }
1699         }
1700         HWRM_UNLOCK();
1701         return 0;
1702 }
1703
1704 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1705 {
1706         int rc = 0;
1707         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1708         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1709
1710         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1711
1712         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1713         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1714         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1715         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1716
1717         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1718
1719         HWRM_CHECK_RESULT();
1720
1721         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1722
1723         HWRM_UNLOCK();
1724
1725         return rc;
1726 }
1727
1728 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1729 {
1730         int rc;
1731         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1732         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1733
1734         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1735
1736         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1737
1738         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1739
1740         HWRM_CHECK_RESULT();
1741         HWRM_UNLOCK();
1742
1743         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1744         return rc;
1745 }
1746
1747 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1748 {
1749         int rc = 0;
1750         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1751         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1752
1753         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1754                 return rc;
1755
1756         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1757
1758         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1759
1760         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1761
1762         HWRM_CHECK_RESULT();
1763         HWRM_UNLOCK();
1764
1765         return rc;
1766 }
1767
1768 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1769                                 unsigned int idx __rte_unused)
1770 {
1771         int rc;
1772         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1773         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1774
1775         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1776
1777         req.update_period_ms = rte_cpu_to_le_32(0);
1778
1779         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1780
1781         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1782
1783         HWRM_CHECK_RESULT();
1784
1785         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1786
1787         HWRM_UNLOCK();
1788
1789         return rc;
1790 }
1791
1792 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1793                                 unsigned int idx __rte_unused)
1794 {
1795         int rc;
1796         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1797         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1798
1799         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1800
1801         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1802
1803         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1804
1805         HWRM_CHECK_RESULT();
1806         HWRM_UNLOCK();
1807
1808         return rc;
1809 }
1810
1811 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1812 {
1813         int rc = 0, i, j;
1814         struct hwrm_vnic_alloc_input req = { 0 };
1815         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1816
1817         if (!BNXT_HAS_RING_GRPS(bp))
1818                 goto skip_ring_grps;
1819
1820         /* map ring groups to this vnic */
1821         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1822                 vnic->start_grp_id, vnic->end_grp_id);
1823         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1824                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1825
1826         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1827         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1828         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1829         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1830
1831 skip_ring_grps:
1832         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1833         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1834
1835         if (vnic->func_default)
1836                 req.flags =
1837                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1838         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1839
1840         HWRM_CHECK_RESULT();
1841
1842         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1843         HWRM_UNLOCK();
1844         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1845         return rc;
1846 }
1847
1848 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1849                                         struct bnxt_vnic_info *vnic,
1850                                         struct bnxt_plcmodes_cfg *pmode)
1851 {
1852         int rc = 0;
1853         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1854         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1855
1856         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1857
1858         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1859
1860         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1861
1862         HWRM_CHECK_RESULT();
1863
1864         pmode->flags = rte_le_to_cpu_32(resp->flags);
1865         /* dflt_vnic bit doesn't exist in the _cfg command */
1866         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1867         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1868         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1869         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1870
1871         HWRM_UNLOCK();
1872
1873         return rc;
1874 }
1875
1876 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1877                                        struct bnxt_vnic_info *vnic,
1878                                        struct bnxt_plcmodes_cfg *pmode)
1879 {
1880         int rc = 0;
1881         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1882         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1883
1884         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1885                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1886                 return rc;
1887         }
1888
1889         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1890
1891         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1892         req.flags = rte_cpu_to_le_32(pmode->flags);
1893         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1894         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1895         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1896         req.enables = rte_cpu_to_le_32(
1897             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1898             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1899             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1900         );
1901
1902         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1903
1904         HWRM_CHECK_RESULT();
1905         HWRM_UNLOCK();
1906
1907         return rc;
1908 }
1909
1910 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1911 {
1912         int rc = 0;
1913         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1914         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1915         struct bnxt_plcmodes_cfg pmodes = { 0 };
1916         uint32_t ctx_enable_flag = 0;
1917         uint32_t enables = 0;
1918
1919         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1920                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1921                 return rc;
1922         }
1923
1924         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1925         if (rc)
1926                 return rc;
1927
1928         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1929
1930         if (BNXT_CHIP_P5(bp)) {
1931                 int dflt_rxq = vnic->start_grp_id;
1932                 struct bnxt_rx_ring_info *rxr;
1933                 struct bnxt_cp_ring_info *cpr;
1934                 struct bnxt_rx_queue *rxq;
1935                 int i;
1936
1937                 /*
1938                  * The first active receive ring is used as the VNIC
1939                  * default receive ring. If there are no active receive
1940                  * rings (all corresponding receive queues are stopped),
1941                  * the first receive ring is used.
1942                  */
1943                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1944                         rxq = bp->eth_dev->data->rx_queues[i];
1945                         if (rxq->rx_started) {
1946                                 dflt_rxq = i;
1947                                 break;
1948                         }
1949                 }
1950
1951                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1952                 rxr = rxq->rx_ring;
1953                 cpr = rxq->cp_ring;
1954
1955                 req.default_rx_ring_id =
1956                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1957                 req.default_cmpl_ring_id =
1958                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1959                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1960                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1961                 goto config_mru;
1962         }
1963
1964         /* Only RSS support for now TBD: COS & LB */
1965         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1966         if (vnic->lb_rule != 0xffff)
1967                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1968         if (vnic->cos_rule != 0xffff)
1969                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1970         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1971                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1972                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1973         }
1974         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1975                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1976                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1977         }
1978
1979         enables |= ctx_enable_flag;
1980         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1981         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1982         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1983         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1984
1985 config_mru:
1986         req.enables = rte_cpu_to_le_32(enables);
1987         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1988         req.mru = rte_cpu_to_le_16(vnic->mru);
1989         /* Configure default VNIC only once. */
1990         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1991                 req.flags |=
1992                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1993                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1994         }
1995         if (vnic->vlan_strip)
1996                 req.flags |=
1997                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1998         if (vnic->bd_stall)
1999                 req.flags |=
2000                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2001         if (vnic->roce_dual)
2002                 req.flags |= rte_cpu_to_le_32(
2003                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
2004         if (vnic->roce_only)
2005                 req.flags |= rte_cpu_to_le_32(
2006                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
2007         if (vnic->rss_dflt_cr)
2008                 req.flags |= rte_cpu_to_le_32(
2009                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2010
2011         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2012
2013         HWRM_CHECK_RESULT();
2014         HWRM_UNLOCK();
2015
2016         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2017
2018         return rc;
2019 }
2020
2021 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2022                 int16_t fw_vf_id)
2023 {
2024         int rc = 0;
2025         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2026         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2027
2028         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2029                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2030                 return rc;
2031         }
2032         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2033
2034         req.enables =
2035                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2036         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2037         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2038
2039         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2040
2041         HWRM_CHECK_RESULT();
2042
2043         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2044         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2045         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2046         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2047         vnic->mru = rte_le_to_cpu_16(resp->mru);
2048         vnic->func_default = rte_le_to_cpu_32(
2049                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2050         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2051                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2052         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2053                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2054         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
2055                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
2056         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
2057                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
2058         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2059                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2060
2061         HWRM_UNLOCK();
2062
2063         return rc;
2064 }
2065
2066 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2067                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2068 {
2069         int rc = 0;
2070         uint16_t ctx_id;
2071         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2072         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2073                                                 bp->hwrm_cmd_resp_addr;
2074
2075         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2076
2077         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2078         HWRM_CHECK_RESULT();
2079
2080         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2081         if (!BNXT_HAS_RING_GRPS(bp))
2082                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2083         else if (ctx_idx == 0)
2084                 vnic->rss_rule = ctx_id;
2085
2086         HWRM_UNLOCK();
2087
2088         return rc;
2089 }
2090
2091 static
2092 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2093                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2094 {
2095         int rc = 0;
2096         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2097         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2098                                                 bp->hwrm_cmd_resp_addr;
2099
2100         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2101                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2102                 return rc;
2103         }
2104         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2105
2106         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2107
2108         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2109
2110         HWRM_CHECK_RESULT();
2111         HWRM_UNLOCK();
2112
2113         return rc;
2114 }
2115
2116 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2117 {
2118         int rc = 0;
2119
2120         if (BNXT_CHIP_P5(bp)) {
2121                 int j;
2122
2123                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2124                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2125                                                       vnic,
2126                                                       vnic->fw_grp_ids[j]);
2127                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2128                 }
2129                 vnic->num_lb_ctxts = 0;
2130         } else {
2131                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2132                 vnic->rss_rule = INVALID_HW_RING_ID;
2133         }
2134
2135         return rc;
2136 }
2137
2138 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2139 {
2140         int rc = 0;
2141         struct hwrm_vnic_free_input req = {.req_type = 0 };
2142         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2143
2144         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2145                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2146                 return rc;
2147         }
2148
2149         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2150
2151         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2152
2153         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2154
2155         HWRM_CHECK_RESULT();
2156         HWRM_UNLOCK();
2157
2158         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2159         /* Configure default VNIC again if necessary. */
2160         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2161                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2162
2163         return rc;
2164 }
2165
2166 static int
2167 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2168 {
2169         int i;
2170         int rc = 0;
2171         int nr_ctxs = vnic->num_lb_ctxts;
2172         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2173         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2174
2175         for (i = 0; i < nr_ctxs; i++) {
2176                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2177
2178                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2179                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2180                 req.hash_mode_flags = vnic->hash_mode;
2181
2182                 req.hash_key_tbl_addr =
2183                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2184
2185                 req.ring_grp_tbl_addr =
2186                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2187                                          i * HW_HASH_INDEX_SIZE);
2188                 req.ring_table_pair_index = i;
2189                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2190
2191                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2192                                             BNXT_USE_CHIMP_MB);
2193
2194                 HWRM_CHECK_RESULT();
2195                 HWRM_UNLOCK();
2196         }
2197
2198         return rc;
2199 }
2200
2201 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2202                            struct bnxt_vnic_info *vnic)
2203 {
2204         int rc = 0;
2205         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2206         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2207
2208         if (!vnic->rss_table)
2209                 return 0;
2210
2211         if (BNXT_CHIP_P5(bp))
2212                 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2213
2214         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2215
2216         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2217         req.hash_mode_flags = vnic->hash_mode;
2218
2219         req.ring_grp_tbl_addr =
2220             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2221         req.hash_key_tbl_addr =
2222             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2223         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2224         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2225
2226         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2227
2228         HWRM_CHECK_RESULT();
2229         HWRM_UNLOCK();
2230
2231         return rc;
2232 }
2233
2234 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2235                         struct bnxt_vnic_info *vnic)
2236 {
2237         int rc = 0;
2238         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2239         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2240         uint16_t size;
2241
2242         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2243                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2244                 return rc;
2245         }
2246
2247         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2248
2249         req.flags = rte_cpu_to_le_32(
2250                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2251
2252         req.enables = rte_cpu_to_le_32(
2253                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2254
2255         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2256         size -= RTE_PKTMBUF_HEADROOM;
2257         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2258
2259         req.jumbo_thresh = rte_cpu_to_le_16(size);
2260         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2261
2262         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2263
2264         HWRM_CHECK_RESULT();
2265         HWRM_UNLOCK();
2266
2267         return rc;
2268 }
2269
2270 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2271                         struct bnxt_vnic_info *vnic, bool enable)
2272 {
2273         int rc = 0;
2274         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2275         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2276
2277         if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2278                 if (enable)
2279                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2280                 return -ENOTSUP;
2281         }
2282
2283         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2284                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2285                 return 0;
2286         }
2287
2288         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2289
2290         if (enable) {
2291                 req.enables = rte_cpu_to_le_32(
2292                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2293                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2294                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2295                 req.flags = rte_cpu_to_le_32(
2296                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2297                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2298                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2299                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2300                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2301                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2302                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2303                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2304                 req.min_agg_len = rte_cpu_to_le_32(512);
2305         }
2306         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2307
2308         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2309
2310         HWRM_CHECK_RESULT();
2311         HWRM_UNLOCK();
2312
2313         return rc;
2314 }
2315
2316 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2317 {
2318         struct hwrm_func_cfg_input req = {0};
2319         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2320         int rc;
2321
2322         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2323         req.enables = rte_cpu_to_le_32(
2324                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2325         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2326         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2327
2328         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2329
2330         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2331         HWRM_CHECK_RESULT();
2332         HWRM_UNLOCK();
2333
2334         bp->pf->vf_info[vf].random_mac = false;
2335
2336         return rc;
2337 }
2338
2339 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2340                                   uint64_t *dropped)
2341 {
2342         int rc = 0;
2343         struct hwrm_func_qstats_input req = {.req_type = 0};
2344         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2345
2346         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2347
2348         req.fid = rte_cpu_to_le_16(fid);
2349
2350         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2351
2352         HWRM_CHECK_RESULT();
2353
2354         if (dropped)
2355                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2356
2357         HWRM_UNLOCK();
2358
2359         return rc;
2360 }
2361
2362 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2363                           struct rte_eth_stats *stats,
2364                           struct hwrm_func_qstats_output *func_qstats)
2365 {
2366         int rc = 0;
2367         struct hwrm_func_qstats_input req = {.req_type = 0};
2368         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2369
2370         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2371
2372         req.fid = rte_cpu_to_le_16(fid);
2373
2374         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2375
2376         HWRM_CHECK_RESULT();
2377         if (func_qstats)
2378                 memcpy(func_qstats, resp,
2379                        sizeof(struct hwrm_func_qstats_output));
2380
2381         if (!stats)
2382                 goto exit;
2383
2384         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2385         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2386         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2387         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2388         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2389         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2390
2391         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2392         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2393         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2394         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2395         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2396         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2397
2398         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2399         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2400         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2401
2402 exit:
2403         HWRM_UNLOCK();
2404
2405         return rc;
2406 }
2407
2408 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2409 {
2410         int rc = 0;
2411         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2412         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2413
2414         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2415
2416         req.fid = rte_cpu_to_le_16(fid);
2417
2418         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2419
2420         HWRM_CHECK_RESULT();
2421         HWRM_UNLOCK();
2422
2423         return rc;
2424 }
2425
2426 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2427 {
2428         unsigned int i;
2429         int rc = 0;
2430
2431         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2432                 struct bnxt_tx_queue *txq;
2433                 struct bnxt_rx_queue *rxq;
2434                 struct bnxt_cp_ring_info *cpr;
2435
2436                 if (i >= bp->rx_cp_nr_rings) {
2437                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2438                         cpr = txq->cp_ring;
2439                 } else {
2440                         rxq = bp->rx_queues[i];
2441                         cpr = rxq->cp_ring;
2442                 }
2443
2444                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2445                 if (rc)
2446                         return rc;
2447         }
2448         return 0;
2449 }
2450
2451 static int
2452 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2453 {
2454         int rc;
2455         unsigned int i;
2456         struct bnxt_cp_ring_info *cpr;
2457
2458         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2459
2460                 if (i >= bp->rx_cp_nr_rings) {
2461                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2462                 } else {
2463                         cpr = bp->rx_queues[i]->cp_ring;
2464                         if (BNXT_HAS_RING_GRPS(bp))
2465                                 bp->grp_info[i].fw_stats_ctx = -1;
2466                 }
2467                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2468                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2469                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2470                         if (rc)
2471                                 return rc;
2472                 }
2473         }
2474         return 0;
2475 }
2476
2477 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2478 {
2479         unsigned int i;
2480         int rc = 0;
2481
2482         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2483                 struct bnxt_tx_queue *txq;
2484                 struct bnxt_rx_queue *rxq;
2485                 struct bnxt_cp_ring_info *cpr;
2486
2487                 if (i >= bp->rx_cp_nr_rings) {
2488                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2489                         cpr = txq->cp_ring;
2490                 } else {
2491                         rxq = bp->rx_queues[i];
2492                         cpr = rxq->cp_ring;
2493                 }
2494
2495                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2496
2497                 if (rc)
2498                         return rc;
2499         }
2500         return rc;
2501 }
2502
2503 static int
2504 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2505 {
2506         uint16_t idx;
2507         uint32_t rc = 0;
2508
2509         if (!BNXT_HAS_RING_GRPS(bp))
2510                 return 0;
2511
2512         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2513
2514                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2515                         continue;
2516
2517                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2518
2519                 if (rc)
2520                         return rc;
2521         }
2522         return rc;
2523 }
2524
2525 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2526 {
2527         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2528
2529         bnxt_hwrm_ring_free(bp, cp_ring,
2530                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2531         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2532         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2533                                      sizeof(*cpr->cp_desc_ring));
2534         cpr->cp_raw_cons = 0;
2535         cpr->valid = 0;
2536 }
2537
2538 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2539 {
2540         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2541
2542         bnxt_hwrm_ring_free(bp, cp_ring,
2543                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2544         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2545         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2546                         sizeof(*cpr->cp_desc_ring));
2547         cpr->cp_raw_cons = 0;
2548         cpr->valid = 0;
2549 }
2550
2551 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2552 {
2553         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2554         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2555         struct bnxt_ring *ring = rxr->rx_ring_struct;
2556         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2557
2558         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2559                 bnxt_hwrm_ring_free(bp, ring,
2560                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2561                 ring->fw_ring_id = INVALID_HW_RING_ID;
2562                 if (BNXT_HAS_RING_GRPS(bp))
2563                         bp->grp_info[queue_index].rx_fw_ring_id =
2564                                                         INVALID_HW_RING_ID;
2565         }
2566         ring = rxr->ag_ring_struct;
2567         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2568                 bnxt_hwrm_ring_free(bp, ring,
2569                                     BNXT_CHIP_P5(bp) ?
2570                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2571                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2572                 if (BNXT_HAS_RING_GRPS(bp))
2573                         bp->grp_info[queue_index].ag_fw_ring_id =
2574                                                         INVALID_HW_RING_ID;
2575         }
2576         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2577                 bnxt_free_cp_ring(bp, cpr);
2578
2579         if (BNXT_HAS_RING_GRPS(bp))
2580                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2581 }
2582
2583 static int
2584 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2585 {
2586         unsigned int i;
2587
2588         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2589                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2590                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2591                 struct bnxt_ring *ring = txr->tx_ring_struct;
2592                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2593
2594                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2595                         bnxt_hwrm_ring_free(bp, ring,
2596                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2597                         ring->fw_ring_id = INVALID_HW_RING_ID;
2598                         memset(txr->tx_desc_ring, 0,
2599                                         txr->tx_ring_struct->ring_size *
2600                                         sizeof(*txr->tx_desc_ring));
2601                         memset(txr->tx_buf_ring, 0,
2602                                         txr->tx_ring_struct->ring_size *
2603                                         sizeof(*txr->tx_buf_ring));
2604                         txr->tx_prod = 0;
2605                         txr->tx_cons = 0;
2606                 }
2607                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2608                         bnxt_free_cp_ring(bp, cpr);
2609                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2610                 }
2611         }
2612
2613         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2614                 bnxt_free_hwrm_rx_ring(bp, i);
2615
2616         return 0;
2617 }
2618
2619 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2620 {
2621         uint16_t i;
2622         uint32_t rc = 0;
2623
2624         if (!BNXT_HAS_RING_GRPS(bp))
2625                 return 0;
2626
2627         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2628                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2629                 if (rc)
2630                         return rc;
2631         }
2632         return rc;
2633 }
2634
2635 /*
2636  * HWRM utility functions
2637  */
2638
2639 void bnxt_free_hwrm_resources(struct bnxt *bp)
2640 {
2641         /* Release memzone */
2642         rte_free(bp->hwrm_cmd_resp_addr);
2643         rte_free(bp->hwrm_short_cmd_req_addr);
2644         bp->hwrm_cmd_resp_addr = NULL;
2645         bp->hwrm_short_cmd_req_addr = NULL;
2646         bp->hwrm_cmd_resp_dma_addr = 0;
2647         bp->hwrm_short_cmd_req_dma_addr = 0;
2648 }
2649
2650 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2651 {
2652         struct rte_pci_device *pdev = bp->pdev;
2653         char type[RTE_MEMZONE_NAMESIZE];
2654
2655         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2656                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2657         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2658         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2659         if (bp->hwrm_cmd_resp_addr == NULL)
2660                 return -ENOMEM;
2661         bp->hwrm_cmd_resp_dma_addr =
2662                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2663         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2664                 PMD_DRV_LOG(ERR,
2665                         "unable to map response address to physical memory\n");
2666                 return -ENOMEM;
2667         }
2668         rte_spinlock_init(&bp->hwrm_lock);
2669
2670         return 0;
2671 }
2672
2673 int
2674 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2675 {
2676         int rc = 0;
2677
2678         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2679                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2680                 if (rc)
2681                         return rc;
2682         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2683                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2684                 if (rc)
2685                         return rc;
2686         }
2687
2688         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2689         return rc;
2690 }
2691
2692 static int
2693 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2694 {
2695         struct bnxt_filter_info *filter;
2696         int rc = 0;
2697
2698         STAILQ_FOREACH(filter, &vnic->filter, next) {
2699                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2700                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2701                 bnxt_free_filter(bp, filter);
2702         }
2703         return rc;
2704 }
2705
2706 static int
2707 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2708 {
2709         struct bnxt_filter_info *filter;
2710         struct rte_flow *flow;
2711         int rc = 0;
2712
2713         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2714                 flow = STAILQ_FIRST(&vnic->flow_list);
2715                 filter = flow->filter;
2716                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2717                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2718
2719                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2720                 rte_free(flow);
2721         }
2722         return rc;
2723 }
2724
2725 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2726 {
2727         struct bnxt_filter_info *filter;
2728         int rc = 0;
2729
2730         STAILQ_FOREACH(filter, &vnic->filter, next) {
2731                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2732                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2733                                                      filter);
2734                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2735                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2736                                                          filter);
2737                 else
2738                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2739                                                      filter);
2740                 if (rc)
2741                         break;
2742         }
2743         return rc;
2744 }
2745
2746 static void
2747 bnxt_free_tunnel_ports(struct bnxt *bp)
2748 {
2749         if (bp->vxlan_port_cnt)
2750                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2751                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2752
2753         if (bp->geneve_port_cnt)
2754                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2755                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2756 }
2757
2758 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2759 {
2760         int i;
2761
2762         if (bp->vnic_info == NULL)
2763                 return;
2764
2765         /*
2766          * Cleanup VNICs in reverse order, to make sure the L2 filter
2767          * from vnic0 is last to be cleaned up.
2768          */
2769         for (i = bp->max_vnics - 1; i >= 0; i--) {
2770                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2771
2772                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2773                         continue;
2774
2775                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2776
2777                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2778
2779                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2780
2781                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2782
2783                 bnxt_hwrm_vnic_free(bp, vnic);
2784
2785                 rte_free(vnic->fw_grp_ids);
2786         }
2787         /* Ring resources */
2788         bnxt_free_all_hwrm_rings(bp);
2789         bnxt_free_all_hwrm_ring_grps(bp);
2790         bnxt_free_all_hwrm_stat_ctxs(bp);
2791         bnxt_free_tunnel_ports(bp);
2792 }
2793
2794 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2795 {
2796         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2797
2798         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2799                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2800
2801         switch (conf_link_speed) {
2802         case ETH_LINK_SPEED_10M_HD:
2803         case ETH_LINK_SPEED_100M_HD:
2804                 /* FALLTHROUGH */
2805                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2806         }
2807         return hw_link_duplex;
2808 }
2809
2810 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2811 {
2812         return !conf_link;
2813 }
2814
2815 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2816                                           uint16_t pam4_link)
2817 {
2818         uint16_t eth_link_speed = 0;
2819
2820         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2821                 return ETH_LINK_SPEED_AUTONEG;
2822
2823         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2824         case ETH_LINK_SPEED_100M:
2825         case ETH_LINK_SPEED_100M_HD:
2826                 /* FALLTHROUGH */
2827                 eth_link_speed =
2828                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2829                 break;
2830         case ETH_LINK_SPEED_1G:
2831                 eth_link_speed =
2832                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2833                 break;
2834         case ETH_LINK_SPEED_2_5G:
2835                 eth_link_speed =
2836                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2837                 break;
2838         case ETH_LINK_SPEED_10G:
2839                 eth_link_speed =
2840                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2841                 break;
2842         case ETH_LINK_SPEED_20G:
2843                 eth_link_speed =
2844                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2845                 break;
2846         case ETH_LINK_SPEED_25G:
2847                 eth_link_speed =
2848                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2849                 break;
2850         case ETH_LINK_SPEED_40G:
2851                 eth_link_speed =
2852                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2853                 break;
2854         case ETH_LINK_SPEED_50G:
2855                 eth_link_speed = pam4_link ?
2856                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
2857                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2858                 break;
2859         case ETH_LINK_SPEED_100G:
2860                 eth_link_speed = pam4_link ?
2861                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
2862                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2863                 break;
2864         case ETH_LINK_SPEED_200G:
2865                 eth_link_speed =
2866                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2867                 break;
2868         default:
2869                 PMD_DRV_LOG(ERR,
2870                         "Unsupported link speed %d; default to AUTO\n",
2871                         conf_link_speed);
2872                 break;
2873         }
2874         return eth_link_speed;
2875 }
2876
2877 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2878                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2879                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2880                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2881                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2882
2883 static int bnxt_validate_link_speed(struct bnxt *bp)
2884 {
2885         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2886         uint16_t port_id = bp->eth_dev->data->port_id;
2887         uint32_t link_speed_capa;
2888         uint32_t one_speed;
2889
2890         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2891                 return 0;
2892
2893         link_speed_capa = bnxt_get_speed_capabilities(bp);
2894
2895         if (link_speed & ETH_LINK_SPEED_FIXED) {
2896                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2897
2898                 if (one_speed & (one_speed - 1)) {
2899                         PMD_DRV_LOG(ERR,
2900                                 "Invalid advertised speeds (%u) for port %u\n",
2901                                 link_speed, port_id);
2902                         return -EINVAL;
2903                 }
2904                 if ((one_speed & link_speed_capa) != one_speed) {
2905                         PMD_DRV_LOG(ERR,
2906                                 "Unsupported advertised speed (%u) for port %u\n",
2907                                 link_speed, port_id);
2908                         return -EINVAL;
2909                 }
2910         } else {
2911                 if (!(link_speed & link_speed_capa)) {
2912                         PMD_DRV_LOG(ERR,
2913                                 "Unsupported advertised speeds (%u) for port %u\n",
2914                                 link_speed, port_id);
2915                         return -EINVAL;
2916                 }
2917         }
2918         return 0;
2919 }
2920
2921 static uint16_t
2922 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2923 {
2924         uint16_t ret = 0;
2925
2926         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2927                 if (bp->link_info->support_speeds)
2928                         return bp->link_info->support_speeds;
2929                 link_speed = BNXT_SUPPORTED_SPEEDS;
2930         }
2931
2932         if (link_speed & ETH_LINK_SPEED_100M)
2933                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2934         if (link_speed & ETH_LINK_SPEED_100M_HD)
2935                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2936         if (link_speed & ETH_LINK_SPEED_1G)
2937                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2938         if (link_speed & ETH_LINK_SPEED_2_5G)
2939                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2940         if (link_speed & ETH_LINK_SPEED_10G)
2941                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2942         if (link_speed & ETH_LINK_SPEED_20G)
2943                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2944         if (link_speed & ETH_LINK_SPEED_25G)
2945                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2946         if (link_speed & ETH_LINK_SPEED_40G)
2947                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2948         if (link_speed & ETH_LINK_SPEED_50G)
2949                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2950         if (link_speed & ETH_LINK_SPEED_100G)
2951                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2952         if (link_speed & ETH_LINK_SPEED_200G)
2953                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2954         return ret;
2955 }
2956
2957 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2958 {
2959         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2960
2961         switch (hw_link_speed) {
2962         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2963                 eth_link_speed = ETH_SPEED_NUM_100M;
2964                 break;
2965         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2966                 eth_link_speed = ETH_SPEED_NUM_1G;
2967                 break;
2968         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2969                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2970                 break;
2971         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2972                 eth_link_speed = ETH_SPEED_NUM_10G;
2973                 break;
2974         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2975                 eth_link_speed = ETH_SPEED_NUM_20G;
2976                 break;
2977         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2978                 eth_link_speed = ETH_SPEED_NUM_25G;
2979                 break;
2980         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2981                 eth_link_speed = ETH_SPEED_NUM_40G;
2982                 break;
2983         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2984                 eth_link_speed = ETH_SPEED_NUM_50G;
2985                 break;
2986         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2987                 eth_link_speed = ETH_SPEED_NUM_100G;
2988                 break;
2989         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
2990                 eth_link_speed = ETH_SPEED_NUM_200G;
2991                 break;
2992         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2993         default:
2994                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2995                         hw_link_speed);
2996                 break;
2997         }
2998         return eth_link_speed;
2999 }
3000
3001 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3002 {
3003         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3004
3005         switch (hw_link_duplex) {
3006         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3007         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3008                 /* FALLTHROUGH */
3009                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3010                 break;
3011         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3012                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3013                 break;
3014         default:
3015                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3016                         hw_link_duplex);
3017                 break;
3018         }
3019         return eth_link_duplex;
3020 }
3021
3022 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3023 {
3024         int rc = 0;
3025         struct bnxt_link_info *link_info = bp->link_info;
3026
3027         rc = bnxt_hwrm_port_phy_qcaps(bp);
3028         if (rc)
3029                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3030
3031         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3032         if (rc) {
3033                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3034                 goto exit;
3035         }
3036
3037         if (link_info->link_speed)
3038                 link->link_speed =
3039                         bnxt_parse_hw_link_speed(link_info->link_speed);
3040         else
3041                 link->link_speed = ETH_SPEED_NUM_NONE;
3042         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3043         link->link_status = link_info->link_up;
3044         link->link_autoneg = link_info->auto_mode ==
3045                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3046                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3047 exit:
3048         return rc;
3049 }
3050
3051 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3052 {
3053         int rc = 0;
3054         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3055         struct bnxt_link_info link_req;
3056         uint16_t speed, autoneg;
3057
3058         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3059                 return 0;
3060
3061         rc = bnxt_validate_link_speed(bp);
3062         if (rc)
3063                 goto error;
3064
3065         memset(&link_req, 0, sizeof(link_req));
3066         link_req.link_up = link_up;
3067         if (!link_up)
3068                 goto port_phy_cfg;
3069
3070         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3071         if (BNXT_CHIP_P5(bp) &&
3072             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3073                 /* 40G is not supported as part of media auto detect.
3074                  * The speed should be forced and autoneg disabled
3075                  * to configure 40G speed.
3076                  */
3077                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3078                 autoneg = 0;
3079         }
3080
3081         /* No auto speeds and no auto_pam4_link. Disable autoneg */
3082         if (bp->link_info->auto_link_speed == 0 &&
3083             bp->link_info->link_signal_mode &&
3084             bp->link_info->auto_pam4_link_speeds == 0)
3085                 autoneg = 0;
3086
3087         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3088                                           bp->link_info->link_signal_mode);
3089         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3090         /* Autoneg can be done only when the FW allows.
3091          * When user configures fixed speed of 40G and later changes to
3092          * any other speed, auto_link_speed/force_link_speed is still set
3093          * to 40G until link comes up at new speed.
3094          */
3095         if (autoneg == 1 &&
3096             !(!BNXT_CHIP_P5(bp) &&
3097               (bp->link_info->auto_link_speed ||
3098                bp->link_info->force_link_speed))) {
3099                 link_req.phy_flags |=
3100                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3101                 link_req.auto_link_speed_mask =
3102                         bnxt_parse_eth_link_speed_mask(bp,
3103                                                        dev_conf->link_speeds);
3104         } else {
3105                 if (bp->link_info->phy_type ==
3106                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3107                     bp->link_info->phy_type ==
3108                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3109                     bp->link_info->media_type ==
3110                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3111                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3112                         return -EINVAL;
3113                 }
3114
3115                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3116                 /* If user wants a particular speed try that first. */
3117                 if (speed)
3118                         link_req.link_speed = speed;
3119                 else if (bp->link_info->force_pam4_link_speed)
3120                         link_req.link_speed =
3121                                 bp->link_info->force_pam4_link_speed;
3122                 else if (bp->link_info->auto_pam4_link_speeds)
3123                         link_req.link_speed =
3124                                 bp->link_info->auto_pam4_link_speeds;
3125                 else if (bp->link_info->support_pam4_speeds)
3126                         link_req.link_speed =
3127                                 bp->link_info->support_pam4_speeds;
3128                 else if (bp->link_info->force_link_speed)
3129                         link_req.link_speed = bp->link_info->force_link_speed;
3130                 else
3131                         link_req.link_speed = bp->link_info->auto_link_speed;
3132                 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3133                  * zero. Use the auto_link_speed.
3134                  */
3135                 if (bp->link_info->auto_link_speed != 0 &&
3136                     bp->link_info->auto_pam4_link_speeds == 0)
3137                         link_req.link_speed = bp->link_info->auto_link_speed;
3138         }
3139         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3140         link_req.auto_pause = bp->link_info->auto_pause;
3141         link_req.force_pause = bp->link_info->force_pause;
3142
3143 port_phy_cfg:
3144         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3145         if (rc) {
3146                 PMD_DRV_LOG(ERR,
3147                         "Set link config failed with rc %d\n", rc);
3148         }
3149
3150 error:
3151         return rc;
3152 }
3153
3154 /* JIRA 22088 */
3155 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3156 {
3157         struct hwrm_func_qcfg_input req = {0};
3158         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3159         uint16_t flags;
3160         int rc = 0;
3161         bp->func_svif = BNXT_SVIF_INVALID;
3162         uint16_t svif_info;
3163
3164         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3165         req.fid = rte_cpu_to_le_16(0xffff);
3166
3167         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3168
3169         HWRM_CHECK_RESULT();
3170
3171         /* Hard Coded.. 0xfff VLAN ID mask */
3172         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3173
3174         svif_info = rte_le_to_cpu_16(resp->svif_info);
3175         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3176                 bp->func_svif = svif_info &
3177                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3178
3179         flags = rte_le_to_cpu_16(resp->flags);
3180         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3181                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3182
3183         if (BNXT_VF(bp) &&
3184             !BNXT_VF_IS_TRUSTED(bp) &&
3185             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3186                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3187                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3188         } else if (BNXT_VF(bp) &&
3189                    BNXT_VF_IS_TRUSTED(bp) &&
3190                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3191                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3192                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3193         }
3194
3195         if (mtu)
3196                 *mtu = rte_le_to_cpu_16(resp->mtu);
3197
3198         switch (resp->port_partition_type) {
3199         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3200         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3201         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3202                 /* FALLTHROUGH */
3203                 bp->flags |= BNXT_FLAG_NPAR_PF;
3204                 break;
3205         default:
3206                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3207                 break;
3208         }
3209
3210         HWRM_UNLOCK();
3211
3212         return rc;
3213 }
3214
3215 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3216 {
3217         struct hwrm_func_qcfg_input req = {0};
3218         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3219         int rc;
3220
3221         if (!BNXT_VF_IS_TRUSTED(bp))
3222                 return 0;
3223
3224         if (!bp->parent)
3225                 return -EINVAL;
3226
3227         bp->parent->fid = BNXT_PF_FID_INVALID;
3228
3229         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3230
3231         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3232
3233         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3234
3235         HWRM_CHECK_RESULT();
3236
3237         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3238         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3239         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3240         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3241
3242         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3243         if (bp->parent->vnic == 0) {
3244                 PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
3245                 /* Use hard-coded values appropriate for current Wh+ fw. */
3246                 if (bp->parent->fid == 2)
3247                         bp->parent->vnic = 0x100;
3248                 else
3249                         bp->parent->vnic = 1;
3250         }
3251
3252         HWRM_UNLOCK();
3253
3254         return 0;
3255 }
3256
3257 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3258                                  uint16_t *vnic_id, uint16_t *svif)
3259 {
3260         struct hwrm_func_qcfg_input req = {0};
3261         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3262         uint16_t svif_info;
3263         int rc = 0;
3264
3265         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3266         req.fid = rte_cpu_to_le_16(fid);
3267
3268         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3269
3270         HWRM_CHECK_RESULT();
3271
3272         if (vnic_id)
3273                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3274
3275         svif_info = rte_le_to_cpu_16(resp->svif_info);
3276         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3277                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3278
3279         HWRM_UNLOCK();
3280
3281         return rc;
3282 }
3283
3284 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3285 {
3286         struct hwrm_port_mac_qcfg_input req = {0};
3287         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3288         uint16_t port_svif_info;
3289         int rc;
3290
3291         bp->port_svif = BNXT_SVIF_INVALID;
3292
3293         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3294                 return 0;
3295
3296         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3297
3298         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3299
3300         HWRM_CHECK_RESULT_SILENT();
3301
3302         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3303         if (port_svif_info &
3304             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3305                 bp->port_svif = port_svif_info &
3306                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3307
3308         HWRM_UNLOCK();
3309
3310         return 0;
3311 }
3312
3313 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3314                                  struct bnxt_pf_resource_info *pf_resc)
3315 {
3316         struct hwrm_func_cfg_input req = {0};
3317         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3318         uint32_t enables;
3319         int rc;
3320
3321         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3322                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3323                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3324                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3325                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3326                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3327                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3328                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3329                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3330
3331         if (BNXT_HAS_RING_GRPS(bp)) {
3332                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3333                 req.num_hw_ring_grps =
3334                         rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3335         } else if (BNXT_HAS_NQ(bp)) {
3336                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3337                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3338         }
3339
3340         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3341         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3342         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3343         req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3344         req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3345         req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3346         req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3347         req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3348         req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3349         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3350         req.fid = rte_cpu_to_le_16(0xffff);
3351         req.enables = rte_cpu_to_le_32(enables);
3352
3353         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3354
3355         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3356
3357         HWRM_CHECK_RESULT();
3358         HWRM_UNLOCK();
3359
3360         return rc;
3361 }
3362
3363 /* min values are the guaranteed resources and max values are subject
3364  * to availability. The strategy for now is to keep both min & max
3365  * values the same.
3366  */
3367 static void
3368 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3369                               struct hwrm_func_vf_resource_cfg_input *req,
3370                               int num_vfs)
3371 {
3372         req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3373                                                (num_vfs + 1));
3374         req->min_rsscos_ctx = req->max_rsscos_ctx;
3375         req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3376         req->min_stat_ctx = req->max_stat_ctx;
3377         req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3378                                                (num_vfs + 1));
3379         req->min_cmpl_rings = req->max_cmpl_rings;
3380         req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3381         req->min_tx_rings = req->max_tx_rings;
3382         req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3383         req->min_rx_rings = req->max_rx_rings;
3384         req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3385         req->min_l2_ctxs = req->max_l2_ctxs;
3386         /* TODO: For now, do not support VMDq/RFS on VFs. */
3387         req->max_vnics = rte_cpu_to_le_16(1);
3388         req->min_vnics = req->max_vnics;
3389         req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3390                                                  (num_vfs + 1));
3391         req->min_hw_ring_grps = req->max_hw_ring_grps;
3392         req->flags =
3393          rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3394 }
3395
3396 static void
3397 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3398                               struct hwrm_func_cfg_input *req,
3399                               int num_vfs)
3400 {
3401         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3402                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3403                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3404                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3405                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3406                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3407                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3408                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3409                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3410                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3411
3412         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3413                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3414                                     BNXT_NUM_VLANS);
3415         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3416         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3417                                                 (num_vfs + 1));
3418         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3419         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3420                                                (num_vfs + 1));
3421         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3422         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3423         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3424         /* TODO: For now, do not support VMDq/RFS on VFs. */
3425         req->num_vnics = rte_cpu_to_le_16(1);
3426         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3427                                                  (num_vfs + 1));
3428 }
3429
3430 /* Update the port wide resource values based on how many resources
3431  * got allocated to the VF.
3432  */
3433 static int bnxt_update_max_resources(struct bnxt *bp,
3434                                      int vf)
3435 {
3436         struct hwrm_func_qcfg_input req = {0};
3437         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3438         int rc;
3439
3440         /* Get the actual allocated values now */
3441         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3442         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3443         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3444         HWRM_CHECK_RESULT();
3445
3446         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3447         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3448         bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3449         bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3450         bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3451         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3452         bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3453
3454         HWRM_UNLOCK();
3455
3456         return 0;
3457 }
3458
3459 /* Update the PF resource values based on how many resources
3460  * got allocated to it.
3461  */
3462 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3463 {
3464         struct hwrm_func_qcfg_input req = {0};
3465         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3466         int rc;
3467
3468         /* Get the actual allocated values now */
3469         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3470         req.fid = rte_cpu_to_le_16(0xffff);
3471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3472         HWRM_CHECK_RESULT();
3473
3474         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3475         bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3476         bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3477         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3478         bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3479         bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3480         bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3481         bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3482
3483         HWRM_UNLOCK();
3484
3485         return 0;
3486 }
3487
3488 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3489 {
3490         struct hwrm_func_qcfg_input req = {0};
3491         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3492         int rc;
3493
3494         /* Check for zero MAC address */
3495         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3496         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3497         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3498         HWRM_CHECK_RESULT();
3499         rc = rte_le_to_cpu_16(resp->vlan);
3500
3501         HWRM_UNLOCK();
3502
3503         return rc;
3504 }
3505
3506 static int bnxt_query_pf_resources(struct bnxt *bp,
3507                                    struct bnxt_pf_resource_info *pf_resc)
3508 {
3509         struct hwrm_func_qcfg_input req = {0};
3510         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3511         int rc;
3512
3513         /* And copy the allocated numbers into the pf struct */
3514         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3515         req.fid = rte_cpu_to_le_16(0xffff);
3516         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3517         HWRM_CHECK_RESULT();
3518
3519         pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3520         pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3521         pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3522         pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3523         pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3524         pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3525         pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3526         bp->pf->evb_mode = resp->evb_mode;
3527
3528         HWRM_UNLOCK();
3529
3530         return rc;
3531 }
3532
3533 static void
3534 bnxt_calculate_pf_resources(struct bnxt *bp,
3535                             struct bnxt_pf_resource_info *pf_resc,
3536                             int num_vfs)
3537 {
3538         if (!num_vfs) {
3539                 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3540                 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3541                 pf_resc->num_cp_rings = bp->max_cp_rings;
3542                 pf_resc->num_tx_rings = bp->max_tx_rings;
3543                 pf_resc->num_rx_rings = bp->max_rx_rings;
3544                 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3545                 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3546
3547                 return;
3548         }
3549
3550         pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3551                                    bp->max_rsscos_ctx % (num_vfs + 1);
3552         pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3553                                  bp->max_stat_ctx % (num_vfs + 1);
3554         pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3555                                 bp->max_cp_rings % (num_vfs + 1);
3556         pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3557                                 bp->max_tx_rings % (num_vfs + 1);
3558         pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3559                                 bp->max_rx_rings % (num_vfs + 1);
3560         pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3561                                bp->max_l2_ctx % (num_vfs + 1);
3562         pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3563                                     bp->max_ring_grps % (num_vfs + 1);
3564 }
3565
3566 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3567 {
3568         struct bnxt_pf_resource_info pf_resc = { 0 };
3569         int rc;
3570
3571         if (!BNXT_PF(bp)) {
3572                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3573                 return -EINVAL;
3574         }
3575
3576         rc = bnxt_hwrm_func_qcaps(bp);
3577         if (rc)
3578                 return rc;
3579
3580         bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3581
3582         bp->pf->func_cfg_flags &=
3583                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3584                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3585         bp->pf->func_cfg_flags |=
3586                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3587
3588         rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3589         if (rc)
3590                 return rc;
3591
3592         rc = bnxt_update_max_resources_pf_only(bp);
3593
3594         return rc;
3595 }
3596
3597 static int
3598 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3599 {
3600         size_t req_buf_sz, sz;
3601         int i, rc;
3602
3603         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3604         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3605                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3606         if (bp->pf->vf_req_buf == NULL) {
3607                 return -ENOMEM;
3608         }
3609
3610         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3611                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3612
3613         for (i = 0; i < num_vfs; i++)
3614                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3615                                              (i * HWRM_MAX_REQ_LEN);
3616
3617         rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3618         if (rc)
3619                 rte_free(bp->pf->vf_req_buf);
3620
3621         return rc;
3622 }
3623
3624 static int
3625 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3626 {
3627         struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3628         struct hwrm_func_vf_resource_cfg_input req = {0};
3629         int i, rc = 0;
3630
3631         bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3632         bp->pf->active_vfs = 0;
3633         for (i = 0; i < num_vfs; i++) {
3634                 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3635                 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3636                 rc = bnxt_hwrm_send_message(bp,
3637                                             &req,
3638                                             sizeof(req),
3639                                             BNXT_USE_CHIMP_MB);
3640                 if (rc || resp->error_code) {
3641                         PMD_DRV_LOG(ERR,
3642                                 "Failed to initialize VF %d\n", i);
3643                         PMD_DRV_LOG(ERR,
3644                                 "Not all VFs available. (%d, %d)\n",
3645                                 rc, resp->error_code);
3646                         HWRM_UNLOCK();
3647
3648                         /* If the first VF configuration itself fails,
3649                          * unregister the vf_fwd_request buffer.
3650                          */
3651                         if (i == 0)
3652                                 bnxt_hwrm_func_buf_unrgtr(bp);
3653                         break;
3654                 }
3655                 HWRM_UNLOCK();
3656
3657                 /* Update the max resource values based on the resource values
3658                  * allocated to the VF.
3659                  */
3660                 bnxt_update_max_resources(bp, i);
3661                 bp->pf->active_vfs++;
3662                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3663         }
3664
3665         return 0;
3666 }
3667
3668 static int
3669 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3670 {
3671         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3672         struct hwrm_func_cfg_input req = {0};
3673         int i, rc;
3674
3675         bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3676
3677         bp->pf->active_vfs = 0;
3678         for (i = 0; i < num_vfs; i++) {
3679                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3680                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3681                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3682                 rc = bnxt_hwrm_send_message(bp,
3683                                             &req,
3684                                             sizeof(req),
3685                                             BNXT_USE_CHIMP_MB);
3686
3687                 /* Clear enable flag for next pass */
3688                 req.enables &= ~rte_cpu_to_le_32(
3689                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3690
3691                 if (rc || resp->error_code) {
3692                         PMD_DRV_LOG(ERR,
3693                                 "Failed to initialize VF %d\n", i);
3694                         PMD_DRV_LOG(ERR,
3695                                 "Not all VFs available. (%d, %d)\n",
3696                                 rc, resp->error_code);
3697                         HWRM_UNLOCK();
3698
3699                         /* If the first VF configuration itself fails,
3700                          * unregister the vf_fwd_request buffer.
3701                          */
3702                         if (i == 0)
3703                                 bnxt_hwrm_func_buf_unrgtr(bp);
3704                         break;
3705                 }
3706
3707                 HWRM_UNLOCK();
3708
3709                 /* Update the max resource values based on the resource values
3710                  * allocated to the VF.
3711                  */
3712                 bnxt_update_max_resources(bp, i);
3713                 bp->pf->active_vfs++;
3714                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3715         }
3716
3717         return 0;
3718 }
3719
3720 static void
3721 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3722 {
3723         if (bp->flags & BNXT_FLAG_NEW_RM)
3724                 bnxt_process_vf_resc_config_new(bp, num_vfs);
3725         else
3726                 bnxt_process_vf_resc_config_old(bp, num_vfs);
3727 }
3728
3729 static void
3730 bnxt_update_pf_resources(struct bnxt *bp,
3731                          struct bnxt_pf_resource_info *pf_resc)
3732 {
3733         bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3734         bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3735         bp->max_cp_rings = pf_resc->num_cp_rings;
3736         bp->max_tx_rings = pf_resc->num_tx_rings;
3737         bp->max_rx_rings = pf_resc->num_rx_rings;
3738         bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3739 }
3740
3741 static int32_t
3742 bnxt_configure_pf_resources(struct bnxt *bp,
3743                             struct bnxt_pf_resource_info *pf_resc)
3744 {
3745         /*
3746          * We're using STD_TX_RING_MODE here which will limit the TX
3747          * rings. This will allow QoS to function properly. Not setting this
3748          * will cause PF rings to break bandwidth settings.
3749          */
3750         bp->pf->func_cfg_flags &=
3751                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3752                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3753         bp->pf->func_cfg_flags |=
3754                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3755         return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3756 }
3757
3758 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3759 {
3760         struct bnxt_pf_resource_info pf_resc = { 0 };
3761         int rc;
3762
3763         if (!BNXT_PF(bp)) {
3764                 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3765                 return -EINVAL;
3766         }
3767
3768         rc = bnxt_hwrm_func_qcaps(bp);
3769         if (rc)
3770                 return rc;
3771
3772         bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3773
3774         rc = bnxt_configure_pf_resources(bp, &pf_resc);
3775         if (rc)
3776                 return rc;
3777
3778         rc = bnxt_query_pf_resources(bp, &pf_resc);
3779         if (rc)
3780                 return rc;
3781
3782         /*
3783          * Now, create and register a buffer to hold forwarded VF requests
3784          */
3785         rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3786         if (rc)
3787                 return rc;
3788
3789         bnxt_configure_vf_resources(bp, num_vfs);
3790
3791         bnxt_update_pf_resources(bp, &pf_resc);
3792
3793         return 0;
3794 }
3795
3796 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3797 {
3798         struct hwrm_func_cfg_input req = {0};
3799         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3800         int rc;
3801
3802         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3803
3804         req.fid = rte_cpu_to_le_16(0xffff);
3805         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3806         req.evb_mode = bp->pf->evb_mode;
3807
3808         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3809         HWRM_CHECK_RESULT();
3810         HWRM_UNLOCK();
3811
3812         return rc;
3813 }
3814
3815 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3816                                 uint8_t tunnel_type)
3817 {
3818         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3819         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3820         int rc = 0;
3821
3822         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3823         req.tunnel_type = tunnel_type;
3824         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3825         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3826         HWRM_CHECK_RESULT();
3827
3828         switch (tunnel_type) {
3829         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3830                 bp->vxlan_fw_dst_port_id =
3831                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3832                 bp->vxlan_port = port;
3833                 break;
3834         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3835                 bp->geneve_fw_dst_port_id =
3836                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3837                 bp->geneve_port = port;
3838                 break;
3839         default:
3840                 break;
3841         }
3842
3843         HWRM_UNLOCK();
3844
3845         return rc;
3846 }
3847
3848 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3849                                 uint8_t tunnel_type)
3850 {
3851         struct hwrm_tunnel_dst_port_free_input req = {0};
3852         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3853         int rc = 0;
3854
3855         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3856
3857         req.tunnel_type = tunnel_type;
3858         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3859         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3860
3861         HWRM_CHECK_RESULT();
3862         HWRM_UNLOCK();
3863
3864         if (tunnel_type ==
3865             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
3866                 bp->vxlan_port = 0;
3867                 bp->vxlan_port_cnt = 0;
3868         }
3869
3870         if (tunnel_type ==
3871             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
3872                 bp->geneve_port = 0;
3873                 bp->geneve_port_cnt = 0;
3874         }
3875
3876         return rc;
3877 }
3878
3879 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3880                                         uint32_t flags)
3881 {
3882         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3883         struct hwrm_func_cfg_input req = {0};
3884         int rc;
3885
3886         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3887
3888         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3889         req.flags = rte_cpu_to_le_32(flags);
3890         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3891
3892         HWRM_CHECK_RESULT();
3893         HWRM_UNLOCK();
3894
3895         return rc;
3896 }
3897
3898 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3899 {
3900         uint32_t *flag = flagp;
3901
3902         vnic->flags = *flag;
3903 }
3904
3905 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3906 {
3907         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3908 }
3909
3910 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
3911 {
3912         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3913         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3914         int rc;
3915
3916         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3917
3918         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3919         req.req_buf_page_size =
3920                 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
3921         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3922         req.req_buf_page_addr0 =
3923                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3924         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3925                 PMD_DRV_LOG(ERR,
3926                         "unable to map buffer address to physical memory\n");
3927                 HWRM_UNLOCK();
3928                 return -ENOMEM;
3929         }
3930
3931         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3932
3933         HWRM_CHECK_RESULT();
3934         HWRM_UNLOCK();
3935
3936         return rc;
3937 }
3938
3939 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3940 {
3941         int rc = 0;
3942         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3943         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3944
3945         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3946                 return 0;
3947
3948         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3949
3950         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3951
3952         HWRM_CHECK_RESULT();
3953         HWRM_UNLOCK();
3954
3955         return rc;
3956 }
3957
3958 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3959 {
3960         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3961         struct hwrm_func_cfg_input req = {0};
3962         int rc;
3963
3964         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3965
3966         req.fid = rte_cpu_to_le_16(0xffff);
3967         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3968         req.enables = rte_cpu_to_le_32(
3969                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3970         req.async_event_cr = rte_cpu_to_le_16(
3971                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3972         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3973
3974         HWRM_CHECK_RESULT();
3975         HWRM_UNLOCK();
3976
3977         return rc;
3978 }
3979
3980 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3981 {
3982         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3983         struct hwrm_func_vf_cfg_input req = {0};
3984         int rc;
3985
3986         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3987
3988         req.enables = rte_cpu_to_le_32(
3989                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3990         req.async_event_cr = rte_cpu_to_le_16(
3991                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3992         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3993
3994         HWRM_CHECK_RESULT();
3995         HWRM_UNLOCK();
3996
3997         return rc;
3998 }
3999
4000 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4001 {
4002         struct hwrm_func_cfg_input req = {0};
4003         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4004         uint16_t dflt_vlan, fid;
4005         uint32_t func_cfg_flags;
4006         int rc = 0;
4007
4008         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4009
4010         if (is_vf) {
4011                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4012                 fid = bp->pf->vf_info[vf].fid;
4013                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4014         } else {
4015                 fid = rte_cpu_to_le_16(0xffff);
4016                 func_cfg_flags = bp->pf->func_cfg_flags;
4017                 dflt_vlan = bp->vlan;
4018         }
4019
4020         req.flags = rte_cpu_to_le_32(func_cfg_flags);
4021         req.fid = rte_cpu_to_le_16(fid);
4022         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4023         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4024
4025         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4026
4027         HWRM_CHECK_RESULT();
4028         HWRM_UNLOCK();
4029
4030         return rc;
4031 }
4032
4033 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4034                         uint16_t max_bw, uint16_t enables)
4035 {
4036         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4037         struct hwrm_func_cfg_input req = {0};
4038         int rc;
4039
4040         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4041
4042         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4043         req.enables |= rte_cpu_to_le_32(enables);
4044         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4045         req.max_bw = rte_cpu_to_le_32(max_bw);
4046         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4047
4048         HWRM_CHECK_RESULT();
4049         HWRM_UNLOCK();
4050
4051         return rc;
4052 }
4053
4054 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4055 {
4056         struct hwrm_func_cfg_input req = {0};
4057         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4058         int rc = 0;
4059
4060         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4061
4062         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4063         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4064         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4065         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4066
4067         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4068
4069         HWRM_CHECK_RESULT();
4070         HWRM_UNLOCK();
4071
4072         return rc;
4073 }
4074
4075 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4076 {
4077         int rc;
4078
4079         if (BNXT_PF(bp))
4080                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4081         else
4082                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4083
4084         return rc;
4085 }
4086
4087 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4088                               void *encaped, size_t ec_size)
4089 {
4090         int rc = 0;
4091         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4092         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4093
4094         if (ec_size > sizeof(req.encap_request))
4095                 return -1;
4096
4097         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4098
4099         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4100         memcpy(req.encap_request, encaped, ec_size);
4101
4102         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4103
4104         HWRM_CHECK_RESULT();
4105         HWRM_UNLOCK();
4106
4107         return rc;
4108 }
4109
4110 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4111                                        struct rte_ether_addr *mac)
4112 {
4113         struct hwrm_func_qcfg_input req = {0};
4114         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4115         int rc;
4116
4117         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4118
4119         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4120         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4121
4122         HWRM_CHECK_RESULT();
4123
4124         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4125
4126         HWRM_UNLOCK();
4127
4128         return rc;
4129 }
4130
4131 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4132                             void *encaped, size_t ec_size)
4133 {
4134         int rc = 0;
4135         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4136         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4137
4138         if (ec_size > sizeof(req.encap_request))
4139                 return -1;
4140
4141         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4142
4143         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4144         memcpy(req.encap_request, encaped, ec_size);
4145
4146         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4147
4148         HWRM_CHECK_RESULT();
4149         HWRM_UNLOCK();
4150
4151         return rc;
4152 }
4153
4154 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
4155                          struct rte_eth_stats *stats, uint8_t rx)
4156 {
4157         int rc = 0;
4158         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4159         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4160
4161         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4162
4163         req.stat_ctx_id = rte_cpu_to_le_32(cid);
4164
4165         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4166
4167         HWRM_CHECK_RESULT();
4168
4169         if (rx) {
4170                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4171                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
4172                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
4173                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4174                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
4175                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
4176                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_discard_pkts);
4177                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_error_pkts);
4178         } else {
4179                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4180                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
4181                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
4182                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4183                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
4184                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
4185         }
4186
4187         HWRM_UNLOCK();
4188
4189         return rc;
4190 }
4191
4192 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4193 {
4194         struct hwrm_port_qstats_input req = {0};
4195         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4196         struct bnxt_pf_info *pf = bp->pf;
4197         int rc;
4198
4199         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4200
4201         req.port_id = rte_cpu_to_le_16(pf->port_id);
4202         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4203         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4204         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4205
4206         HWRM_CHECK_RESULT();
4207         HWRM_UNLOCK();
4208
4209         return rc;
4210 }
4211
4212 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4213 {
4214         struct hwrm_port_clr_stats_input req = {0};
4215         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4216         struct bnxt_pf_info *pf = bp->pf;
4217         int rc;
4218
4219         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4220         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4221             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4222                 return 0;
4223
4224         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4225
4226         req.port_id = rte_cpu_to_le_16(pf->port_id);
4227         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4228
4229         HWRM_CHECK_RESULT();
4230         HWRM_UNLOCK();
4231
4232         return rc;
4233 }
4234
4235 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4236 {
4237         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4238         struct hwrm_port_led_qcaps_input req = {0};
4239         int rc;
4240
4241         if (BNXT_VF(bp))
4242                 return 0;
4243
4244         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4245         req.port_id = bp->pf->port_id;
4246         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4247
4248         HWRM_CHECK_RESULT();
4249
4250         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4251                 unsigned int i;
4252
4253                 bp->leds->num_leds = resp->num_leds;
4254                 memcpy(bp->leds, &resp->led0_id,
4255                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4256                 for (i = 0; i < bp->leds->num_leds; i++) {
4257                         struct bnxt_led_info *led = &bp->leds[i];
4258
4259                         uint16_t caps = led->led_state_caps;
4260
4261                         if (!led->led_group_id ||
4262                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4263                                 bp->leds->num_leds = 0;
4264                                 break;
4265                         }
4266                 }
4267         }
4268
4269         HWRM_UNLOCK();
4270
4271         return rc;
4272 }
4273
4274 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4275 {
4276         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4277         struct hwrm_port_led_cfg_input req = {0};
4278         struct bnxt_led_cfg *led_cfg;
4279         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4280         uint16_t duration = 0;
4281         int rc, i;
4282
4283         if (!bp->leds->num_leds || BNXT_VF(bp))
4284                 return -EOPNOTSUPP;
4285
4286         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4287
4288         if (led_on) {
4289                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4290                 duration = rte_cpu_to_le_16(500);
4291         }
4292         req.port_id = bp->pf->port_id;
4293         req.num_leds = bp->leds->num_leds;
4294         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4295         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4296                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4297                 led_cfg->led_id = bp->leds[i].led_id;
4298                 led_cfg->led_state = led_state;
4299                 led_cfg->led_blink_on = duration;
4300                 led_cfg->led_blink_off = duration;
4301                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4302         }
4303
4304         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4305
4306         HWRM_CHECK_RESULT();
4307         HWRM_UNLOCK();
4308
4309         return rc;
4310 }
4311
4312 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4313                                uint32_t *length)
4314 {
4315         int rc;
4316         struct hwrm_nvm_get_dir_info_input req = {0};
4317         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4318
4319         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4320
4321         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4322
4323         HWRM_CHECK_RESULT();
4324
4325         *entries = rte_le_to_cpu_32(resp->entries);
4326         *length = rte_le_to_cpu_32(resp->entry_length);
4327
4328         HWRM_UNLOCK();
4329         return rc;
4330 }
4331
4332 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4333 {
4334         int rc;
4335         uint32_t dir_entries;
4336         uint32_t entry_length;
4337         uint8_t *buf;
4338         size_t buflen;
4339         rte_iova_t dma_handle;
4340         struct hwrm_nvm_get_dir_entries_input req = {0};
4341         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4342
4343         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4344         if (rc != 0)
4345                 return rc;
4346
4347         *data++ = dir_entries;
4348         *data++ = entry_length;
4349         len -= 2;
4350         memset(data, 0xff, len);
4351
4352         buflen = dir_entries * entry_length;
4353         buf = rte_malloc("nvm_dir", buflen, 0);
4354         if (buf == NULL)
4355                 return -ENOMEM;
4356         dma_handle = rte_malloc_virt2iova(buf);
4357         if (dma_handle == RTE_BAD_IOVA) {
4358                 rte_free(buf);
4359                 PMD_DRV_LOG(ERR,
4360                         "unable to map response address to physical memory\n");
4361                 return -ENOMEM;
4362         }
4363         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4364         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4365         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4366
4367         if (rc == 0)
4368                 memcpy(data, buf, len > buflen ? buflen : len);
4369
4370         rte_free(buf);
4371         HWRM_CHECK_RESULT();
4372         HWRM_UNLOCK();
4373
4374         return rc;
4375 }
4376
4377 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4378                              uint32_t offset, uint32_t length,
4379                              uint8_t *data)
4380 {
4381         int rc;
4382         uint8_t *buf;
4383         rte_iova_t dma_handle;
4384         struct hwrm_nvm_read_input req = {0};
4385         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4386
4387         buf = rte_malloc("nvm_item", length, 0);
4388         if (!buf)
4389                 return -ENOMEM;
4390
4391         dma_handle = rte_malloc_virt2iova(buf);
4392         if (dma_handle == RTE_BAD_IOVA) {
4393                 rte_free(buf);
4394                 PMD_DRV_LOG(ERR,
4395                         "unable to map response address to physical memory\n");
4396                 return -ENOMEM;
4397         }
4398         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4399         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4400         req.dir_idx = rte_cpu_to_le_16(index);
4401         req.offset = rte_cpu_to_le_32(offset);
4402         req.len = rte_cpu_to_le_32(length);
4403         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4404         if (rc == 0)
4405                 memcpy(data, buf, length);
4406
4407         rte_free(buf);
4408         HWRM_CHECK_RESULT();
4409         HWRM_UNLOCK();
4410
4411         return rc;
4412 }
4413
4414 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4415 {
4416         int rc;
4417         struct hwrm_nvm_erase_dir_entry_input req = {0};
4418         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4419
4420         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4421         req.dir_idx = rte_cpu_to_le_16(index);
4422         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4423         HWRM_CHECK_RESULT();
4424         HWRM_UNLOCK();
4425
4426         return rc;
4427 }
4428
4429
4430 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4431                           uint16_t dir_ordinal, uint16_t dir_ext,
4432                           uint16_t dir_attr, const uint8_t *data,
4433                           size_t data_len)
4434 {
4435         int rc;
4436         struct hwrm_nvm_write_input req = {0};
4437         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4438         rte_iova_t dma_handle;
4439         uint8_t *buf;
4440
4441         buf = rte_malloc("nvm_write", data_len, 0);
4442         if (!buf)
4443                 return -ENOMEM;
4444
4445         dma_handle = rte_malloc_virt2iova(buf);
4446         if (dma_handle == RTE_BAD_IOVA) {
4447                 rte_free(buf);
4448                 PMD_DRV_LOG(ERR,
4449                         "unable to map response address to physical memory\n");
4450                 return -ENOMEM;
4451         }
4452         memcpy(buf, data, data_len);
4453
4454         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4455
4456         req.dir_type = rte_cpu_to_le_16(dir_type);
4457         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4458         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4459         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4460         req.dir_data_length = rte_cpu_to_le_32(data_len);
4461         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4462
4463         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4464
4465         rte_free(buf);
4466         HWRM_CHECK_RESULT();
4467         HWRM_UNLOCK();
4468
4469         return rc;
4470 }
4471
4472 static void
4473 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4474 {
4475         uint32_t *count = cbdata;
4476
4477         *count = *count + 1;
4478 }
4479
4480 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4481                                      struct bnxt_vnic_info *vnic __rte_unused)
4482 {
4483         return 0;
4484 }
4485
4486 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4487 {
4488         uint32_t count = 0;
4489
4490         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4491             &count, bnxt_vnic_count_hwrm_stub);
4492
4493         return count;
4494 }
4495
4496 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4497                                         uint16_t *vnic_ids)
4498 {
4499         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4500         struct hwrm_func_vf_vnic_ids_query_output *resp =
4501                                                 bp->hwrm_cmd_resp_addr;
4502         int rc;
4503
4504         /* First query all VNIC ids */
4505         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4506
4507         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4508         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4509         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4510
4511         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4512                 HWRM_UNLOCK();
4513                 PMD_DRV_LOG(ERR,
4514                 "unable to map VNIC ID table address to physical memory\n");
4515                 return -ENOMEM;
4516         }
4517         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4518         HWRM_CHECK_RESULT();
4519         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4520
4521         HWRM_UNLOCK();
4522
4523         return rc;
4524 }
4525
4526 /*
4527  * This function queries the VNIC IDs  for a specified VF. It then calls
4528  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4529  * Then it calls the hwrm_cb function to program this new vnic configuration.
4530  */
4531 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4532         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4533         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4534 {
4535         struct bnxt_vnic_info vnic;
4536         int rc = 0;
4537         int i, num_vnic_ids;
4538         uint16_t *vnic_ids;
4539         size_t vnic_id_sz;
4540         size_t sz;
4541
4542         /* First query all VNIC ids */
4543         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4544         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4545                         RTE_CACHE_LINE_SIZE);
4546         if (vnic_ids == NULL)
4547                 return -ENOMEM;
4548
4549         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4550                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4551
4552         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4553
4554         if (num_vnic_ids < 0)
4555                 return num_vnic_ids;
4556
4557         /* Retrieve VNIC, update bd_stall then update */
4558
4559         for (i = 0; i < num_vnic_ids; i++) {
4560                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4561                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4562                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4563                 if (rc)
4564                         break;
4565                 if (vnic.mru <= 4)      /* Indicates unallocated */
4566                         continue;
4567
4568                 vnic_cb(&vnic, cbdata);
4569
4570                 rc = hwrm_cb(bp, &vnic);
4571                 if (rc)
4572                         break;
4573         }
4574
4575         rte_free(vnic_ids);
4576
4577         return rc;
4578 }
4579
4580 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4581                                               bool on)
4582 {
4583         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4584         struct hwrm_func_cfg_input req = {0};
4585         int rc;
4586
4587         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4588
4589         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4590         req.enables |= rte_cpu_to_le_32(
4591                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4592         req.vlan_antispoof_mode = on ?
4593                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4594                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4595         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4596
4597         HWRM_CHECK_RESULT();
4598         HWRM_UNLOCK();
4599
4600         return rc;
4601 }
4602
4603 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4604 {
4605         struct bnxt_vnic_info vnic;
4606         uint16_t *vnic_ids;
4607         size_t vnic_id_sz;
4608         int num_vnic_ids, i;
4609         size_t sz;
4610         int rc;
4611
4612         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4613         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4614                         RTE_CACHE_LINE_SIZE);
4615         if (vnic_ids == NULL)
4616                 return -ENOMEM;
4617
4618         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4619                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4620
4621         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4622         if (rc <= 0)
4623                 goto exit;
4624         num_vnic_ids = rc;
4625
4626         /*
4627          * Loop through to find the default VNIC ID.
4628          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4629          * by sending the hwrm_func_qcfg command to the firmware.
4630          */
4631         for (i = 0; i < num_vnic_ids; i++) {
4632                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4633                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4634                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4635                                         bp->pf->first_vf_id + vf);
4636                 if (rc)
4637                         goto exit;
4638                 if (vnic.func_default) {
4639                         rte_free(vnic_ids);
4640                         return vnic.fw_vnic_id;
4641                 }
4642         }
4643         /* Could not find a default VNIC. */
4644         PMD_DRV_LOG(ERR, "No default VNIC\n");
4645 exit:
4646         rte_free(vnic_ids);
4647         return rc;
4648 }
4649
4650 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4651                          uint16_t dst_id,
4652                          struct bnxt_filter_info *filter)
4653 {
4654         int rc = 0;
4655         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4656         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4657         uint32_t enables = 0;
4658
4659         if (filter->fw_em_filter_id != UINT64_MAX)
4660                 bnxt_hwrm_clear_em_filter(bp, filter);
4661
4662         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4663
4664         req.flags = rte_cpu_to_le_32(filter->flags);
4665
4666         enables = filter->enables |
4667               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4668         req.dst_id = rte_cpu_to_le_16(dst_id);
4669
4670         if (filter->ip_addr_type) {
4671                 req.ip_addr_type = filter->ip_addr_type;
4672                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4673         }
4674         if (enables &
4675             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4676                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4677         if (enables &
4678             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4679                 memcpy(req.src_macaddr, filter->src_macaddr,
4680                        RTE_ETHER_ADDR_LEN);
4681         if (enables &
4682             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4683                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4684                        RTE_ETHER_ADDR_LEN);
4685         if (enables &
4686             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4687                 req.ovlan_vid = filter->l2_ovlan;
4688         if (enables &
4689             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4690                 req.ivlan_vid = filter->l2_ivlan;
4691         if (enables &
4692             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4693                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4694         if (enables &
4695             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4696                 req.ip_protocol = filter->ip_protocol;
4697         if (enables &
4698             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4699                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4700         if (enables &
4701             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4702                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4703         if (enables &
4704             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4705                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4706         if (enables &
4707             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4708                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4709         if (enables &
4710             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4711                 req.mirror_vnic_id = filter->mirror_vnic_id;
4712
4713         req.enables = rte_cpu_to_le_32(enables);
4714
4715         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4716
4717         HWRM_CHECK_RESULT();
4718
4719         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4720         HWRM_UNLOCK();
4721
4722         return rc;
4723 }
4724
4725 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4726 {
4727         int rc = 0;
4728         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4729         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4730
4731         if (filter->fw_em_filter_id == UINT64_MAX)
4732                 return 0;
4733
4734         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4735
4736         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4737
4738         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4739
4740         HWRM_CHECK_RESULT();
4741         HWRM_UNLOCK();
4742
4743         filter->fw_em_filter_id = UINT64_MAX;
4744         filter->fw_l2_filter_id = UINT64_MAX;
4745
4746         return 0;
4747 }
4748
4749 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4750                          uint16_t dst_id,
4751                          struct bnxt_filter_info *filter)
4752 {
4753         int rc = 0;
4754         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4755         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4756                                                 bp->hwrm_cmd_resp_addr;
4757         uint32_t enables = 0;
4758
4759         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4760                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4761
4762         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4763
4764         req.flags = rte_cpu_to_le_32(filter->flags);
4765
4766         enables = filter->enables |
4767               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4768         req.dst_id = rte_cpu_to_le_16(dst_id);
4769
4770         if (filter->ip_addr_type) {
4771                 req.ip_addr_type = filter->ip_addr_type;
4772                 enables |=
4773                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4774         }
4775         if (enables &
4776             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4777                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4778         if (enables &
4779             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4780                 memcpy(req.src_macaddr, filter->src_macaddr,
4781                        RTE_ETHER_ADDR_LEN);
4782         if (enables &
4783             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4784                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4785         if (enables &
4786             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4787                 req.ip_protocol = filter->ip_protocol;
4788         if (enables &
4789             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4790                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4791         if (enables &
4792             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4793                 req.src_ipaddr_mask[0] =
4794                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4795         if (enables &
4796             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4797                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4798         if (enables &
4799             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4800                 req.dst_ipaddr_mask[0] =
4801                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4802         if (enables &
4803             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4804                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4805         if (enables &
4806             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4807                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4808         if (enables &
4809             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4810                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4811         if (enables &
4812             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4813                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4814         if (enables &
4815             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4816                 req.mirror_vnic_id = filter->mirror_vnic_id;
4817
4818         req.enables = rte_cpu_to_le_32(enables);
4819
4820         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4821
4822         HWRM_CHECK_RESULT();
4823
4824         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4825         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4826         HWRM_UNLOCK();
4827
4828         return rc;
4829 }
4830
4831 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4832                                 struct bnxt_filter_info *filter)
4833 {
4834         int rc = 0;
4835         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4836         struct hwrm_cfa_ntuple_filter_free_output *resp =
4837                                                 bp->hwrm_cmd_resp_addr;
4838
4839         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4840                 return 0;
4841
4842         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4843
4844         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4845
4846         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4847
4848         HWRM_CHECK_RESULT();
4849         HWRM_UNLOCK();
4850
4851         filter->fw_ntuple_filter_id = UINT64_MAX;
4852
4853         return 0;
4854 }
4855
4856 static int
4857 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4858 {
4859         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4860         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4861         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4862         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4863         uint16_t *ring_tbl = vnic->rss_table;
4864         int nr_ctxs = vnic->num_lb_ctxts;
4865         int max_rings = bp->rx_nr_rings;
4866         int i, j, k, cnt;
4867         int rc = 0;
4868
4869         for (i = 0, k = 0; i < nr_ctxs; i++) {
4870                 struct bnxt_rx_ring_info *rxr;
4871                 struct bnxt_cp_ring_info *cpr;
4872
4873                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4874
4875                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4876                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4877                 req.hash_mode_flags = vnic->hash_mode;
4878
4879                 req.ring_grp_tbl_addr =
4880                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4881                                      i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
4882                                      2 * sizeof(*ring_tbl));
4883                 req.hash_key_tbl_addr =
4884                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4885
4886                 req.ring_table_pair_index = i;
4887                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4888
4889                 for (j = 0; j < 64; j++) {
4890                         uint16_t ring_id;
4891
4892                         /* Find next active ring. */
4893                         for (cnt = 0; cnt < max_rings; cnt++) {
4894                                 if (rx_queue_state[k] !=
4895                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4896                                         break;
4897                                 if (++k == max_rings)
4898                                         k = 0;
4899                         }
4900
4901                         /* Return if no rings are active. */
4902                         if (cnt == max_rings) {
4903                                 HWRM_UNLOCK();
4904                                 return 0;
4905                         }
4906
4907                         /* Add rx/cp ring pair to RSS table. */
4908                         rxr = rxqs[k]->rx_ring;
4909                         cpr = rxqs[k]->cp_ring;
4910
4911                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4912                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4913                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4914                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4915
4916                         if (++k == max_rings)
4917                                 k = 0;
4918                 }
4919                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4920                                             BNXT_USE_CHIMP_MB);
4921
4922                 HWRM_CHECK_RESULT();
4923                 HWRM_UNLOCK();
4924         }
4925
4926         return rc;
4927 }
4928
4929 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4930 {
4931         unsigned int rss_idx, fw_idx, i;
4932
4933         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4934                 return 0;
4935
4936         if (!(vnic->rss_table && vnic->hash_type))
4937                 return 0;
4938
4939         if (BNXT_CHIP_P5(bp))
4940                 return bnxt_vnic_rss_configure_p5(bp, vnic);
4941
4942         /*
4943          * Fill the RSS hash & redirection table with
4944          * ring group ids for all VNICs
4945          */
4946         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4947              rss_idx++, fw_idx++) {
4948                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4949                         fw_idx %= bp->rx_cp_nr_rings;
4950                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4951                                 break;
4952                         fw_idx++;
4953                 }
4954
4955                 if (i == bp->rx_cp_nr_rings)
4956                         return 0;
4957
4958                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4959         }
4960
4961         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4962 }
4963
4964 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4965         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4966 {
4967         uint16_t flags;
4968
4969         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4970
4971         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4972         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4973
4974         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4975         req->num_cmpl_dma_aggr_during_int =
4976                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4977
4978         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4979
4980         /* min timer set to 1/2 of interrupt timer */
4981         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4982
4983         /* buf timer set to 1/4 of interrupt timer */
4984         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4985
4986         req->cmpl_aggr_dma_tmr_during_int =
4987                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4988
4989         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4990                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4991         req->flags = rte_cpu_to_le_16(flags);
4992 }
4993
4994 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
4995                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4996 {
4997         struct hwrm_ring_aggint_qcaps_input req = {0};
4998         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4999         uint32_t enables;
5000         uint16_t flags;
5001         int rc;
5002
5003         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5004         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5005         HWRM_CHECK_RESULT();
5006
5007         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5008         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5009
5010         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5011                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5012         agg_req->flags = rte_cpu_to_le_16(flags);
5013         enables =
5014          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5015          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5016         agg_req->enables = rte_cpu_to_le_32(enables);
5017
5018         HWRM_UNLOCK();
5019         return rc;
5020 }
5021
5022 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5023                         struct bnxt_coal *coal, uint16_t ring_id)
5024 {
5025         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5026         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5027                                                 bp->hwrm_cmd_resp_addr;
5028         int rc;
5029
5030         /* Set ring coalesce parameters only for 100G NICs */
5031         if (BNXT_CHIP_P5(bp)) {
5032                 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5033                         return -1;
5034         } else if (bnxt_stratus_device(bp)) {
5035                 bnxt_hwrm_set_coal_params(coal, &req);
5036         } else {
5037                 return 0;
5038         }
5039
5040         HWRM_PREP(&req,
5041                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5042                   BNXT_USE_CHIMP_MB);
5043         req.ring_id = rte_cpu_to_le_16(ring_id);
5044         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5045         HWRM_CHECK_RESULT();
5046         HWRM_UNLOCK();
5047         return 0;
5048 }
5049
5050 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5051 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5052 {
5053         struct hwrm_func_backing_store_qcaps_input req = {0};
5054         struct hwrm_func_backing_store_qcaps_output *resp =
5055                 bp->hwrm_cmd_resp_addr;
5056         struct bnxt_ctx_pg_info *ctx_pg;
5057         struct bnxt_ctx_mem_info *ctx;
5058         int total_alloc_len;
5059         int rc, i, tqm_rings;
5060
5061         if (!BNXT_CHIP_P5(bp) ||
5062             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5063             BNXT_VF(bp) ||
5064             bp->ctx)
5065                 return 0;
5066
5067         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5068         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5069         HWRM_CHECK_RESULT_SILENT();
5070
5071         total_alloc_len = sizeof(*ctx);
5072         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5073                           RTE_CACHE_LINE_SIZE);
5074         if (!ctx) {
5075                 rc = -ENOMEM;
5076                 goto ctx_err;
5077         }
5078
5079         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5080         ctx->qp_min_qp1_entries =
5081                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5082         ctx->qp_max_l2_entries =
5083                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5084         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5085         ctx->srq_max_l2_entries =
5086                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5087         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5088         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5089         ctx->cq_max_l2_entries =
5090                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5091         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5092         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5093         ctx->vnic_max_vnic_entries =
5094                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5095         ctx->vnic_max_ring_table_entries =
5096                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5097         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5098         ctx->stat_max_entries =
5099                 rte_le_to_cpu_32(resp->stat_max_entries);
5100         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5101         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5102         ctx->tqm_min_entries_per_ring =
5103                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5104         ctx->tqm_max_entries_per_ring =
5105                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5106         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5107         if (!ctx->tqm_entries_multiple)
5108                 ctx->tqm_entries_multiple = 1;
5109         ctx->mrav_max_entries =
5110                 rte_le_to_cpu_32(resp->mrav_max_entries);
5111         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5112         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5113         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5114         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5115
5116         if (!ctx->tqm_fp_rings_count)
5117                 ctx->tqm_fp_rings_count = bp->max_q;
5118
5119         tqm_rings = ctx->tqm_fp_rings_count + 1;
5120
5121         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5122                             sizeof(*ctx_pg) * tqm_rings,
5123                             RTE_CACHE_LINE_SIZE);
5124         if (!ctx_pg) {
5125                 rc = -ENOMEM;
5126                 goto ctx_err;
5127         }
5128         for (i = 0; i < tqm_rings; i++, ctx_pg++)
5129                 ctx->tqm_mem[i] = ctx_pg;
5130
5131         bp->ctx = ctx;
5132 ctx_err:
5133         HWRM_UNLOCK();
5134         return rc;
5135 }
5136
5137 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5138 {
5139         struct hwrm_func_backing_store_cfg_input req = {0};
5140         struct hwrm_func_backing_store_cfg_output *resp =
5141                 bp->hwrm_cmd_resp_addr;
5142         struct bnxt_ctx_mem_info *ctx = bp->ctx;
5143         struct bnxt_ctx_pg_info *ctx_pg;
5144         uint32_t *num_entries;
5145         uint64_t *pg_dir;
5146         uint8_t *pg_attr;
5147         uint32_t ena;
5148         int i, rc;
5149
5150         if (!ctx)
5151                 return 0;
5152
5153         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5154         req.enables = rte_cpu_to_le_32(enables);
5155
5156         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5157                 ctx_pg = &ctx->qp_mem;
5158                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5159                 req.qp_num_qp1_entries =
5160                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5161                 req.qp_num_l2_entries =
5162                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5163                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5164                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5165                                       &req.qpc_pg_size_qpc_lvl,
5166                                       &req.qpc_page_dir);
5167         }
5168
5169         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5170                 ctx_pg = &ctx->srq_mem;
5171                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5172                 req.srq_num_l2_entries =
5173                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5174                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5175                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5176                                       &req.srq_pg_size_srq_lvl,
5177                                       &req.srq_page_dir);
5178         }
5179
5180         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5181                 ctx_pg = &ctx->cq_mem;
5182                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5183                 req.cq_num_l2_entries =
5184                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5185                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5186                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5187                                       &req.cq_pg_size_cq_lvl,
5188                                       &req.cq_page_dir);
5189         }
5190
5191         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5192                 ctx_pg = &ctx->vnic_mem;
5193                 req.vnic_num_vnic_entries =
5194                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5195                 req.vnic_num_ring_table_entries =
5196                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5197                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5198                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5199                                       &req.vnic_pg_size_vnic_lvl,
5200                                       &req.vnic_page_dir);
5201         }
5202
5203         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5204                 ctx_pg = &ctx->stat_mem;
5205                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5206                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5207                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5208                                       &req.stat_pg_size_stat_lvl,
5209                                       &req.stat_page_dir);
5210         }
5211
5212         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5213         num_entries = &req.tqm_sp_num_entries;
5214         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5215         pg_dir = &req.tqm_sp_page_dir;
5216         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5217         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5218                 if (!(enables & ena))
5219                         continue;
5220
5221                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5222
5223                 ctx_pg = ctx->tqm_mem[i];
5224                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5225                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5226         }
5227
5228         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5229         HWRM_CHECK_RESULT();
5230         HWRM_UNLOCK();
5231
5232         return rc;
5233 }
5234
5235 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5236 {
5237         struct hwrm_port_qstats_ext_input req = {0};
5238         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5239         struct bnxt_pf_info *pf = bp->pf;
5240         int rc;
5241
5242         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5243               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5244                 return 0;
5245
5246         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5247
5248         req.port_id = rte_cpu_to_le_16(pf->port_id);
5249         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5250                 req.tx_stat_host_addr =
5251                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5252                 req.tx_stat_size =
5253                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5254         }
5255         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5256                 req.rx_stat_host_addr =
5257                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5258                 req.rx_stat_size =
5259                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5260         }
5261         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5262
5263         if (rc) {
5264                 bp->fw_rx_port_stats_ext_size = 0;
5265                 bp->fw_tx_port_stats_ext_size = 0;
5266         } else {
5267                 bp->fw_rx_port_stats_ext_size =
5268                         rte_le_to_cpu_16(resp->rx_stat_size);
5269                 bp->fw_tx_port_stats_ext_size =
5270                         rte_le_to_cpu_16(resp->tx_stat_size);
5271         }
5272
5273         HWRM_CHECK_RESULT();
5274         HWRM_UNLOCK();
5275
5276         return rc;
5277 }
5278
5279 int
5280 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5281 {
5282         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5283         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5284                 bp->hwrm_cmd_resp_addr;
5285         int rc = 0;
5286
5287         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5288         req.tunnel_type = type;
5289         req.dest_fid = bp->fw_fid;
5290         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5291         HWRM_CHECK_RESULT();
5292
5293         HWRM_UNLOCK();
5294
5295         return rc;
5296 }
5297
5298 int
5299 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5300 {
5301         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5302         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5303                 bp->hwrm_cmd_resp_addr;
5304         int rc = 0;
5305
5306         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5307         req.tunnel_type = type;
5308         req.dest_fid = bp->fw_fid;
5309         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5310         HWRM_CHECK_RESULT();
5311
5312         HWRM_UNLOCK();
5313
5314         return rc;
5315 }
5316
5317 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5318 {
5319         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5320         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5321                 bp->hwrm_cmd_resp_addr;
5322         int rc = 0;
5323
5324         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5325         req.src_fid = bp->fw_fid;
5326         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5327         HWRM_CHECK_RESULT();
5328
5329         if (type)
5330                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5331
5332         HWRM_UNLOCK();
5333
5334         return rc;
5335 }
5336
5337 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5338                                    uint16_t *dst_fid)
5339 {
5340         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5341         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5342                 bp->hwrm_cmd_resp_addr;
5343         int rc = 0;
5344
5345         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5346         req.src_fid = bp->fw_fid;
5347         req.tunnel_type = tun_type;
5348         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5349         HWRM_CHECK_RESULT();
5350
5351         if (dst_fid)
5352                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5353
5354         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5355
5356         HWRM_UNLOCK();
5357
5358         return rc;
5359 }
5360
5361 int bnxt_hwrm_set_mac(struct bnxt *bp)
5362 {
5363         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5364         struct hwrm_func_vf_cfg_input req = {0};
5365         int rc = 0;
5366
5367         if (!BNXT_VF(bp))
5368                 return 0;
5369
5370         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5371
5372         req.enables =
5373                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5374         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5375
5376         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5377
5378         HWRM_CHECK_RESULT();
5379
5380         HWRM_UNLOCK();
5381
5382         return rc;
5383 }
5384
5385 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5386 {
5387         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5388         struct hwrm_func_drv_if_change_input req = {0};
5389         uint32_t flags;
5390         int rc;
5391
5392         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5393                 return 0;
5394
5395         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5396          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5397          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5398          */
5399         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5400                 return 0;
5401
5402         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5403
5404         if (up)
5405                 req.flags =
5406                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5407
5408         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5409
5410         HWRM_CHECK_RESULT();
5411         flags = rte_le_to_cpu_32(resp->flags);
5412         HWRM_UNLOCK();
5413
5414         if (!up)
5415                 return 0;
5416
5417         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5418                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5419                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5420         }
5421
5422         return 0;
5423 }
5424
5425 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5426 {
5427         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5428         struct bnxt_error_recovery_info *info = bp->recovery_info;
5429         struct hwrm_error_recovery_qcfg_input req = {0};
5430         uint32_t flags = 0;
5431         unsigned int i;
5432         int rc;
5433
5434         /* Older FW does not have error recovery support */
5435         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5436                 return 0;
5437
5438         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5439
5440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5441
5442         HWRM_CHECK_RESULT();
5443
5444         flags = rte_le_to_cpu_32(resp->flags);
5445         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5446                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5447         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5448                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5449
5450         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5451             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5452                 rc = -EINVAL;
5453                 goto err;
5454         }
5455
5456         /* FW returned values are in units of 100msec */
5457         info->driver_polling_freq =
5458                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5459         info->master_func_wait_period =
5460                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5461         info->normal_func_wait_period =
5462                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5463         info->master_func_wait_period_after_reset =
5464                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5465         info->max_bailout_time_after_reset =
5466                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5467         info->status_regs[BNXT_FW_STATUS_REG] =
5468                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5469         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5470                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5471         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5472                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5473         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5474                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5475         info->reg_array_cnt =
5476                 rte_le_to_cpu_32(resp->reg_array_cnt);
5477
5478         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5479                 rc = -EINVAL;
5480                 goto err;
5481         }
5482
5483         for (i = 0; i < info->reg_array_cnt; i++) {
5484                 info->reset_reg[i] =
5485                         rte_le_to_cpu_32(resp->reset_reg[i]);
5486                 info->reset_reg_val[i] =
5487                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5488                 info->delay_after_reset[i] =
5489                         resp->delay_after_reset[i];
5490         }
5491 err:
5492         HWRM_UNLOCK();
5493
5494         /* Map the FW status registers */
5495         if (!rc)
5496                 rc = bnxt_map_fw_health_status_regs(bp);
5497
5498         if (rc) {
5499                 rte_free(bp->recovery_info);
5500                 bp->recovery_info = NULL;
5501         }
5502         return rc;
5503 }
5504
5505 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5506 {
5507         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5508         struct hwrm_fw_reset_input req = {0};
5509         int rc;
5510
5511         if (!BNXT_PF(bp))
5512                 return -EOPNOTSUPP;
5513
5514         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5515
5516         req.embedded_proc_type =
5517                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5518         req.selfrst_status =
5519                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5520         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5521
5522         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5523                                     BNXT_USE_KONG(bp));
5524
5525         HWRM_CHECK_RESULT();
5526         HWRM_UNLOCK();
5527
5528         return rc;
5529 }
5530
5531 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5532 {
5533         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5534         struct hwrm_port_ts_query_input req = {0};
5535         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5536         uint32_t flags = 0;
5537         int rc;
5538
5539         if (!ptp)
5540                 return 0;
5541
5542         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5543
5544         switch (path) {
5545         case BNXT_PTP_FLAGS_PATH_TX:
5546                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5547                 break;
5548         case BNXT_PTP_FLAGS_PATH_RX:
5549                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5550                 break;
5551         case BNXT_PTP_FLAGS_CURRENT_TIME:
5552                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5553                 break;
5554         }
5555
5556         req.flags = rte_cpu_to_le_32(flags);
5557         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5558
5559         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5560
5561         HWRM_CHECK_RESULT();
5562
5563         if (timestamp) {
5564                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5565                 *timestamp |=
5566                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5567         }
5568         HWRM_UNLOCK();
5569
5570         return rc;
5571 }
5572
5573 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5574 {
5575         int rc = 0;
5576
5577         struct hwrm_cfa_counter_qcaps_input req = {0};
5578         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5579
5580         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5581                 PMD_DRV_LOG(DEBUG,
5582                             "Not a PF or trusted VF. Command not supported\n");
5583                 return 0;
5584         }
5585
5586         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5587         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5588         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5589
5590         HWRM_CHECK_RESULT();
5591         if (max_fc)
5592                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5593         HWRM_UNLOCK();
5594
5595         return 0;
5596 }
5597
5598 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5599 {
5600         int rc = 0;
5601         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5602         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5603
5604         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5605                 PMD_DRV_LOG(DEBUG,
5606                             "Not a PF or trusted VF. Command not supported\n");
5607                 return 0;
5608         }
5609
5610         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5611
5612         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5613         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5614         req.page_dir = rte_cpu_to_le_64(dma_addr);
5615
5616         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5617
5618         HWRM_CHECK_RESULT();
5619         if (ctx_id) {
5620                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5621                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5622         }
5623         HWRM_UNLOCK();
5624
5625         return 0;
5626 }
5627
5628 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5629 {
5630         int rc = 0;
5631         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5632         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5633
5634         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5635                 PMD_DRV_LOG(DEBUG,
5636                             "Not a PF or trusted VF. Command not supported\n");
5637                 return 0;
5638         }
5639
5640         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5641
5642         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5643
5644         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5645
5646         HWRM_CHECK_RESULT();
5647         HWRM_UNLOCK();
5648
5649         return rc;
5650 }
5651
5652 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5653                               uint16_t cntr, uint16_t ctx_id,
5654                               uint32_t num_entries, bool enable)
5655 {
5656         struct hwrm_cfa_counter_cfg_input req = {0};
5657         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5658         uint16_t flags = 0;
5659         int rc;
5660
5661         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5662                 PMD_DRV_LOG(DEBUG,
5663                             "Not a PF or trusted VF. Command not supported\n");
5664                 return 0;
5665         }
5666
5667         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5668
5669         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5670         req.counter_type = rte_cpu_to_le_16(cntr);
5671         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5672                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5673         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5674         if (dir == BNXT_DIR_RX)
5675                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5676         else if (dir == BNXT_DIR_TX)
5677                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5678         req.flags = rte_cpu_to_le_16(flags);
5679         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5680         req.num_entries = rte_cpu_to_le_32(num_entries);
5681
5682         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5683         HWRM_CHECK_RESULT();
5684         HWRM_UNLOCK();
5685
5686         return 0;
5687 }
5688
5689 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5690                                  enum bnxt_flow_dir dir,
5691                                  uint16_t cntr,
5692                                  uint16_t num_entries)
5693 {
5694         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5695         struct hwrm_cfa_counter_qstats_input req = {0};
5696         uint16_t flow_ctx_id = 0;
5697         uint16_t flags = 0;
5698         int rc = 0;
5699
5700         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5701                 PMD_DRV_LOG(DEBUG,
5702                             "Not a PF or trusted VF. Command not supported\n");
5703                 return 0;
5704         }
5705
5706         if (dir == BNXT_DIR_RX) {
5707                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5708                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5709         } else if (dir == BNXT_DIR_TX) {
5710                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5711                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5712         }
5713
5714         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5715         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5716         req.counter_type = rte_cpu_to_le_16(cntr);
5717         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5718         req.num_entries = rte_cpu_to_le_16(num_entries);
5719         req.flags = rte_cpu_to_le_16(flags);
5720         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5721
5722         HWRM_CHECK_RESULT();
5723         HWRM_UNLOCK();
5724
5725         return 0;
5726 }
5727
5728 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5729                                 uint16_t *first_vf_id)
5730 {
5731         int rc = 0;
5732         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5733         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5734
5735         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5736
5737         req.fid = rte_cpu_to_le_16(fid);
5738
5739         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5740
5741         HWRM_CHECK_RESULT();
5742
5743         if (first_vf_id)
5744                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5745
5746         HWRM_UNLOCK();
5747
5748         return rc;
5749 }
5750
5751 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
5752 {
5753         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5754         struct hwrm_cfa_pair_alloc_input req = {0};
5755         int rc;
5756
5757         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5758                 PMD_DRV_LOG(DEBUG,
5759                             "Not a PF or trusted VF. Command not supported\n");
5760                 return 0;
5761         }
5762
5763         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
5764         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5765         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5766                  bp->eth_dev->data->name, rep_bp->vf_id);
5767
5768         req.pf_b_id = rep_bp->parent_pf_idx;
5769         req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5770                                                 rte_cpu_to_le_16(rep_bp->vf_id);
5771         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
5772         req.host_b_id = 1; /* TBD - Confirm if this is OK */
5773
5774         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
5775                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
5776         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
5777                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
5778         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
5779                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
5780         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
5781                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
5782
5783         req.q_ab = rep_bp->rep_q_r2f;
5784         req.q_ba = rep_bp->rep_q_f2r;
5785         req.fc_ab = rep_bp->rep_fc_r2f;
5786         req.fc_ba = rep_bp->rep_fc_f2r;
5787
5788         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5789         HWRM_CHECK_RESULT();
5790
5791         HWRM_UNLOCK();
5792         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
5793                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
5794         return rc;
5795 }
5796
5797 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
5798 {
5799         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
5800         struct hwrm_cfa_pair_free_input req = {0};
5801         int rc;
5802
5803         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5804                 PMD_DRV_LOG(DEBUG,
5805                             "Not a PF or trusted VF. Command not supported\n");
5806                 return 0;
5807         }
5808
5809         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
5810         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5811                  bp->eth_dev->data->name, rep_bp->vf_id);
5812         req.pf_b_id = rep_bp->parent_pf_idx;
5813         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5814         req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5815                                                 rte_cpu_to_le_16(rep_bp->vf_id);
5816         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5817         HWRM_CHECK_RESULT();
5818         HWRM_UNLOCK();
5819         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
5820                     rep_bp->vf_id);
5821         return rc;
5822 }