drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30 #define HWRM_VERSION_1_10_2_13          0x10a020d
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages == 0)
  68                 return;
  69
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 static struct bnxt_cp_ring_info*
  79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
  80 {
  81         struct bnxt_cp_ring_info *cp_ring = NULL;
  82         uint16_t i;
  83
  84         switch (type) {
  85         case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
  86         case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
  87                 /* FALLTHROUGH */
  88                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
  89                         struct bnxt_rx_queue *rxq = bp->rx_queues[i];
  90
  91                         if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
  92                             rte_cpu_to_le_16(rid)) {
  93                                 return rxq->cp_ring;
  94                         }
  95                 }
  96                 break;
  97         case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
  98                 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
  99                         struct bnxt_tx_queue *txq = bp->tx_queues[i];
 100
 101                         if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
 102                             rte_cpu_to_le_16(rid)) {
 103                                 return txq->cp_ring;
 104                         }
 105                 }
 106                 break;
 107         default:
 108                 return cp_ring;
 109         }
 110         return cp_ring;
 111 }
 112
 113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
 114  * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
 115  * before timeout, we force the done bit for the cleanup to proceed.
 116  * Also if cpr is null, do nothing.. The HWRM command is  not for a
 117  * Tx/Rx/AGG ring cleanup.
 118  */
 119 static int
 120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
 121                         bool tx, bool rx, bool timeout)
 122 {
 123         int done = 0;
 124
 125         if (cpr != NULL) {
 126                 if (tx)
 127                         done = bnxt_flush_tx_cmp(cpr);
 128
 129                 if (rx)
 130                         done = bnxt_flush_rx_cmp(cpr);
 131
 132                 if (done)
 133                         PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
 134                                     rx ? "Rx" : "Tx");
 135
 136                 /* We are about to timeout and still haven't seen the
 137                  * HWRM done for the Ring free. Force the cleanup.
 138                  */
 139                 if (!done && timeout) {
 140                         done = 1;
 141                         PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
 142                                     rx ? "Rx" : "Tx");
 143                 }
 144         } else {
 145                 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
 146                  * Otherwise the cpr would have been valid. So do nothing.
 147                  */
 148                 done = 1;
 149         }
 150
 151         return done;
 152 }
 153
 154 /*
 155  * HWRM Functions (sent to HWRM)
 156  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
 157  * HWRM command times out, or a negative error code if the HWRM
 158  * command was failed by the FW.
 159  */
 160
 161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
 162                                   uint32_t msg_len, bool use_kong_mb)
 163 {
 164         unsigned int i;
 165         struct input *req = msg;
 166         struct output *resp = bp->hwrm_cmd_resp_addr;
 167         uint32_t *data = msg;
 168         uint8_t *bar;
 169         uint8_t *valid;
 170         uint16_t max_req_len = bp->max_req_len;
 171         struct hwrm_short_input short_input = { 0 };
 172         uint16_t bar_offset = use_kong_mb ?
 173                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
 174         uint16_t mb_trigger_offset = use_kong_mb ?
 175                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 176         struct bnxt_cp_ring_info *cpr = NULL;
 177         bool is_rx = false;
 178         bool is_tx = false;
 179         uint32_t timeout;
 180
 181         /* Do not send HWRM commands to firmware in error state */
 182         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 183                 return 0;
 184
 185         timeout = bp->hwrm_cmd_timeout;
 186
 187         /* Update the message length for backing store config for new FW. */
 188         if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
 189             rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
 190                 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
 191
 192         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 193             msg_len > bp->max_req_len) {
 194                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 195
 196                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 197                 memcpy(short_cmd_req, req, msg_len);
 198
 199                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 200                 short_input.signature = rte_cpu_to_le_16(
 201                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 202                 short_input.size = rte_cpu_to_le_16(msg_len);
 203                 short_input.req_addr =
 204                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 205
 206                 data = (uint32_t *)&short_input;
 207                 msg_len = sizeof(short_input);
 208
 209                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 210         }
 211
 212         /* Write request msg to hwrm channel */
 213         for (i = 0; i < msg_len; i += 4) {
 214                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 215                 rte_write32(*data, bar);
 216                 data++;
 217         }
 218
 219         /* Zero the rest of the request space */
 220         for (; i < max_req_len; i += 4) {
 221                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 222                 rte_write32(0, bar);
 223         }
 224
 225         /* Ring channel doorbell */
 226         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 227         rte_write32(1, bar);
 228         /*
 229          * Make sure the channel doorbell ring command complete before
 230          * reading the response to avoid getting stale or invalid
 231          * responses.
 232          */
 233         rte_io_mb();
 234
 235         /* Check ring flush is done.
 236          * This is valid only for Tx and Rx rings (including AGG rings).
 237          * The Tx and Rx rings should be freed once the HW confirms all
 238          * the internal buffers and BDs associated with the rings are
 239          * consumed and the corresponding DMA is handled.
 240          */
 241         if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
 242                 /* Check if the TxCQ matches. If that fails check if RxCQ
 243                  * matches. And if neither match, is_rx = false, is_tx = false.
 244                  */
 245                 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 246                                                HWRM_RING_FREE_INPUT_RING_TYPE_TX);
 247                 if (cpr == NULL) {
 248                         /* Not a TxCQ. Check if the RxCQ matches. */
 249                         cpr =
 250                         bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 251                                                  HWRM_RING_FREE_INPUT_RING_TYPE_RX);
 252                         if (cpr != NULL)
 253                                 is_rx = true;
 254                 } else {
 255                         is_tx = true;
 256                 }
 257         }
 258
 259         /* Poll for the valid bit */
 260         for (i = 0; i < timeout; i++) {
 261                 int done;
 262
 263                 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
 264                                                i == timeout - 1);
 265                 /* Sanity check on the resp->resp_len */
 266                 rte_io_rmb();
 267                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 268                         /* Last byte of resp contains the valid key */
 269                         valid = (uint8_t *)resp + resp->resp_len - 1;
 270                         if (*valid == HWRM_RESP_VALID_KEY && done)
 271                                 break;
 272                 }
 273                 rte_delay_us(1);
 274         }
 275
 276         if (i >= timeout) {
 277                 /* Suppress VER_GET timeout messages during reset recovery */
 278                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 279                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 280                         return -ETIMEDOUT;
 281
 282                 PMD_DRV_LOG(ERR,
 283                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 284                             req->req_type, req->seq_id);
 285                 return -ETIMEDOUT;
 286         }
 287         return 0;
 288 }
 289
 290 /*
 291  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 292  * spinlock, and does initial processing.
 293  *
 294  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 295  * releases the spinlock only if it returns. If the regular int return codes
 296  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 297  * directly, rather it should be copied and modified to suit the function.
 298  *
 299  * HWRM_UNLOCK() must be called after all response processing is completed.
 300  */
 301 #define HWRM_PREP(req, type, kong) do { \
 302         rte_spinlock_lock(&bp->hwrm_lock); \
 303         if (bp->hwrm_cmd_resp_addr == NULL) { \
 304                 rte_spinlock_unlock(&bp->hwrm_lock); \
 305                 return -EACCES; \
 306         } \
 307         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 308         (req)->req_type = rte_cpu_to_le_16(type); \
 309         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 310         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 311                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 312         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 313         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 314 } while (0)
 315
 316 #define HWRM_CHECK_RESULT_SILENT() do {\
 317         if (rc) { \
 318                 rte_spinlock_unlock(&bp->hwrm_lock); \
 319                 return rc; \
 320         } \
 321         if (resp->error_code) { \
 322                 rc = rte_le_to_cpu_16(resp->error_code); \
 323                 rte_spinlock_unlock(&bp->hwrm_lock); \
 324                 return rc; \
 325         } \
 326 } while (0)
 327
 328 #define HWRM_CHECK_RESULT() do {\
 329         if (rc) { \
 330                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 331                 rte_spinlock_unlock(&bp->hwrm_lock); \
 332                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 333                         rc = -EACCES; \
 334                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 335                         rc = -ENOSPC; \
 336                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 337                         rc = -EINVAL; \
 338                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 339                         rc = -ENOTSUP; \
 340                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 341                         rc = -EAGAIN; \
 342                 else if (rc > 0) \
 343                         rc = -EIO; \
 344                 return rc; \
 345         } \
 346         if (resp->error_code) { \
 347                 rc = rte_le_to_cpu_16(resp->error_code); \
 348                 if (resp->resp_len >= 16) { \
 349                         struct hwrm_err_output *tmp_hwrm_err_op = \
 350                                                 (void *)resp; \
 351                         PMD_DRV_LOG(ERR, \
 352                                 "error %d:%d:%08x:%04x\n", \
 353                                 rc, tmp_hwrm_err_op->cmd_err, \
 354                                 rte_le_to_cpu_32(\
 355                                         tmp_hwrm_err_op->opaque_0), \
 356                                 rte_le_to_cpu_16(\
 357                                         tmp_hwrm_err_op->opaque_1)); \
 358                 } else { \
 359                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 360                 } \
 361                 rte_spinlock_unlock(&bp->hwrm_lock); \
 362                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 363                         rc = -EACCES; \
 364                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 365                         rc = -ENOSPC; \
 366                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 367                         rc = -EINVAL; \
 368                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 369                         rc = -ENOTSUP; \
 370                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 371                         rc = -EAGAIN; \
 372                 else if (rc > 0) \
 373                         rc = -EIO; \
 374                 return rc; \
 375         } \
 376 } while (0)
 377
 378 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 379
 380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 381                                 bool use_kong_mb,
 382                                 uint16_t msg_type,
 383                                 void *msg,
 384                                 uint32_t msg_len,
 385                                 void *resp_msg,
 386                                 uint32_t resp_len)
 387 {
 388         int rc = 0;
 389         bool mailbox = BNXT_USE_CHIMP_MB;
 390         struct input *req = msg;
 391         struct output *resp = bp->hwrm_cmd_resp_addr;
 392
 393         if (use_kong_mb)
 394                 mailbox = BNXT_USE_KONG(bp);
 395
 396         HWRM_PREP(req, msg_type, mailbox);
 397
 398         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 399
 400         HWRM_CHECK_RESULT();
 401
 402         if (resp_msg)
 403                 memcpy(resp_msg, resp, resp_len);
 404
 405         HWRM_UNLOCK();
 406
 407         return rc;
 408 }
 409
 410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 411                                   bool use_kong_mb,
 412                                   uint16_t tf_type,
 413                                   uint16_t tf_subtype,
 414                                   uint32_t *tf_response_code,
 415                                   void *msg,
 416                                   uint32_t msg_len,
 417                                   void *response,
 418                                   uint32_t response_len)
 419 {
 420         int rc = 0;
 421         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 422         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 423         bool mailbox = BNXT_USE_CHIMP_MB;
 424
 425         if (msg_len > sizeof(req.tf_req))
 426                 return -ENOMEM;
 427
 428         if (use_kong_mb)
 429                 mailbox = BNXT_USE_KONG(bp);
 430
 431         HWRM_PREP(&req, HWRM_TF, mailbox);
 432         /* Build request using the user supplied request payload.
 433          * TLV request size is checked at build time against HWRM
 434          * request max size, thus no checking required.
 435          */
 436         req.tf_type = tf_type;
 437         req.tf_subtype = tf_subtype;
 438         memcpy(req.tf_req, msg, msg_len);
 439
 440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 441         HWRM_CHECK_RESULT();
 442
 443         /* Copy the resp to user provided response buffer */
 444         if (response != NULL)
 445                 /* Post process response data. We need to copy only
 446                  * the 'payload' as the HWRM data structure really is
 447                  * HWRM header + msg header + payload and the TFLIB
 448                  * only provided a payload place holder.
 449                  */
 450                 if (response_len != 0) {
 451                         memcpy(response,
 452                                resp->tf_resp,
 453                                response_len);
 454                 }
 455
 456         /* Extract the internal tflib response code */
 457         *tf_response_code = resp->tf_resp_code;
 458         HWRM_UNLOCK();
 459
 460         return rc;
 461 }
 462
 463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 464 {
 465         int rc = 0;
 466         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 467         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 468
 469         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 470         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 471         req.mask = 0;
 472
 473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 474
 475         HWRM_CHECK_RESULT();
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 482                                  struct bnxt_vnic_info *vnic,
 483                                  uint16_t vlan_count,
 484                                  struct bnxt_vlan_table_entry *vlan_table)
 485 {
 486         int rc = 0;
 487         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 488         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 489         uint32_t mask = 0;
 490
 491         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 492                 return rc;
 493
 494         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 495         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 496
 497         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 498                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 499         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 500                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 501
 502         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 503                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 504
 505         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 506                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 507         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 508                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 509                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 510                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 511         }
 512         if (vlan_table) {
 513                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 514                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 515                 req.vlan_tag_tbl_addr =
 516                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 517                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 518         }
 519         req.mask = rte_cpu_to_le_32(mask);
 520
 521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 522
 523         HWRM_CHECK_RESULT();
 524         HWRM_UNLOCK();
 525
 526         return rc;
 527 }
 528
 529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 530                         uint16_t vlan_count,
 531                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 532 {
 533         int rc = 0;
 534         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 535         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 536                                                 bp->hwrm_cmd_resp_addr;
 537
 538         /*
 539          * Older HWRM versions did not support this command, and the set_rx_mask
 540          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 541          * removed from set_rx_mask call, and this command was added.
 542          *
 543          * This command is also present from 1.7.8.11 and higher,
 544          * as well as 1.7.8.0
 545          */
 546         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 547                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 548                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 549                                         (11)))
 550                                 return 0;
 551                 }
 552         }
 553         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 554         req.fid = rte_cpu_to_le_16(fid);
 555
 556         req.vlan_tag_mask_tbl_addr =
 557                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 558         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 559
 560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 561
 562         HWRM_CHECK_RESULT();
 563         HWRM_UNLOCK();
 564
 565         return rc;
 566 }
 567
 568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 569                              struct bnxt_filter_info *filter)
 570 {
 571         int rc = 0;
 572         struct bnxt_filter_info *l2_filter = filter;
 573         struct bnxt_vnic_info *vnic = NULL;
 574         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 575         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 576
 577         if (filter->fw_l2_filter_id == UINT64_MAX)
 578                 return 0;
 579
 580         if (filter->matching_l2_fltr_ptr)
 581                 l2_filter = filter->matching_l2_fltr_ptr;
 582
 583         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 584                     filter, l2_filter, l2_filter->l2_ref_cnt);
 585
 586         if (l2_filter->l2_ref_cnt == 0)
 587                 return 0;
 588
 589         if (l2_filter->l2_ref_cnt > 0)
 590                 l2_filter->l2_ref_cnt--;
 591
 592         if (l2_filter->l2_ref_cnt > 0)
 593                 return 0;
 594
 595         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 596
 597         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 598
 599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 600
 601         HWRM_CHECK_RESULT();
 602         HWRM_UNLOCK();
 603
 604         filter->fw_l2_filter_id = UINT64_MAX;
 605         if (l2_filter->l2_ref_cnt == 0) {
 606                 vnic = l2_filter->vnic;
 607                 if (vnic) {
 608                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 609                                       bnxt_filter_info, next);
 610                         bnxt_free_filter(bp, l2_filter);
 611                 }
 612         }
 613
 614         return 0;
 615 }
 616
 617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 618                          uint16_t dst_id,
 619                          struct bnxt_filter_info *filter)
 620 {
 621         int rc = 0;
 622         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 623         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 624         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 625         const struct rte_eth_vmdq_rx_conf *conf =
 626                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 627         uint32_t enables = 0;
 628         uint16_t j = dst_id - 1;
 629
 630         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 631         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 632             conf->pool_map[j].pools & (1UL << j)) {
 633                 PMD_DRV_LOG(DEBUG,
 634                         "Add vlan %u to vmdq pool %u\n",
 635                         conf->pool_map[j].vlan_id, j);
 636
 637                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 638                 filter->enables |=
 639                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 640                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 641         }
 642
 643         if (filter->fw_l2_filter_id != UINT64_MAX)
 644                 bnxt_hwrm_clear_l2_filter(bp, filter);
 645
 646         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 647
 648         /* PMD does not support XDP and RoCE */
 649         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 650                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 651         req.flags = rte_cpu_to_le_32(filter->flags);
 652
 653         enables = filter->enables |
 654               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 655         req.dst_id = rte_cpu_to_le_16(dst_id);
 656
 657         if (enables &
 658             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 659                 memcpy(req.l2_addr, filter->l2_addr,
 660                        RTE_ETHER_ADDR_LEN);
 661         if (enables &
 662             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 663                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 664                        RTE_ETHER_ADDR_LEN);
 665         if (enables &
 666             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 667                 req.l2_ovlan = filter->l2_ovlan;
 668         if (enables &
 669             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 670                 req.l2_ivlan = filter->l2_ivlan;
 671         if (enables &
 672             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 673                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 674         if (enables &
 675             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 676                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 677         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 678                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 679         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 680                 req.src_type = filter->src_type;
 681         if (filter->pri_hint) {
 682                 req.pri_hint = filter->pri_hint;
 683                 req.l2_filter_id_hint =
 684                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 685         }
 686
 687         req.enables = rte_cpu_to_le_32(enables);
 688
 689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 690
 691         HWRM_CHECK_RESULT();
 692
 693         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 694         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 695         HWRM_UNLOCK();
 696
 697         filter->l2_ref_cnt++;
 698
 699         return rc;
 700 }
 701
 702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 703 {
 704         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 705         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 706         uint32_t flags = 0;
 707         int rc;
 708
 709         if (!ptp)
 710                 return 0;
 711
 712         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 713
 714         if (ptp->rx_filter)
 715                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 716         else
 717                 flags |=
 718                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 719         if (ptp->tx_tstamp_en)
 720                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 721         else
 722                 flags |=
 723                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 724         req.flags = rte_cpu_to_le_32(flags);
 725         req.enables = rte_cpu_to_le_32
 726                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 727         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 728
 729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 730         HWRM_UNLOCK();
 731
 732         return rc;
 733 }
 734
 735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 736 {
 737         int rc = 0;
 738         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 739         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 740         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 741
 742         if (ptp)
 743                 return 0;
 744
 745         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 746
 747         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 748
 749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 750
 751         HWRM_CHECK_RESULT();
 752
 753         if (!BNXT_CHIP_P5(bp) &&
 754             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 755                 return 0;
 756
 757         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 758                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 759
 760         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 761         if (!ptp)
 762                 return -ENOMEM;
 763
 764         if (!BNXT_CHIP_P5(bp)) {
 765                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 766                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 767                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 768                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 769                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 770                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 771                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 772                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 773                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 774                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 775                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 776                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 777                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 778                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 779                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 780                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 781                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 782                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 783         }
 784
 785         ptp->bp = bp;
 786         bp->ptp_cfg = ptp;
 787
 788         return 0;
 789 }
 790
 791 void bnxt_free_vf_info(struct bnxt *bp)
 792 {
 793         int i;
 794
 795         if (bp->pf->vf_info == NULL)
 796                 return;
 797
 798         for (i = 0; i < bp->pf->max_vfs; i++) {
 799                 rte_free(bp->pf->vf_info[i].vlan_table);
 800                 bp->pf->vf_info[i].vlan_table = NULL;
 801                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 802                 bp->pf->vf_info[i].vlan_as_table = NULL;
 803         }
 804         rte_free(bp->pf->vf_info);
 805         bp->pf->vf_info = NULL;
 806 }
 807
 808 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
 809 {
 810         struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
 811         int i;
 812
 813         if (vf_info)
 814                 bnxt_free_vf_info(bp);
 815
 816         vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
 817         if (vf_info == NULL) {
 818                 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
 819                 return -ENOMEM;
 820         }
 821
 822         bp->pf->max_vfs = max_vfs;
 823         for (i = 0; i < max_vfs; i++) {
 824                 vf_info[i].fid = bp->pf->first_vf_id + i;
 825                 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
 826                                                     getpagesize(), getpagesize());
 827                 if (vf_info[i].vlan_table == NULL) {
 828                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
 829                         goto err;
 830                 }
 831                 rte_mem_lock_page(vf_info[i].vlan_table);
 832
 833                 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
 834                                                        getpagesize(), getpagesize());
 835                 if (vf_info[i].vlan_as_table == NULL) {
 836                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
 837                         goto err;
 838                 }
 839                 rte_mem_lock_page(vf_info[i].vlan_as_table);
 840
 841                 STAILQ_INIT(&vf_info[i].filter);
 842         }
 843
 844         bp->pf->vf_info = vf_info;
 845
 846         return 0;
 847 err:
 848         bnxt_free_vf_info(bp);
 849         return -ENOMEM;
 850 }
 851
 852 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 853 {
 854         int rc = 0;
 855         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 856         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 857         uint16_t new_max_vfs;
 858         uint32_t flags;
 859
 860         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 861
 862         req.fid = rte_cpu_to_le_16(0xffff);
 863
 864         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 865
 866         HWRM_CHECK_RESULT();
 867
 868         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 869         flags = rte_le_to_cpu_32(resp->flags);
 870         if (BNXT_PF(bp)) {
 871                 bp->pf->port_id = resp->port_id;
 872                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 873                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 874                 new_max_vfs = bp->pdev->max_vfs;
 875                 if (new_max_vfs != bp->pf->max_vfs) {
 876                         rc = bnxt_alloc_vf_info(bp, new_max_vfs);
 877                         if (rc)
 878                                 goto unlock;
 879                 }
 880         }
 881
 882         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 883         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 884                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 885                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 886         } else {
 887                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 888         }
 889         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 890         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 891         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 892         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 893         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 894         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 895         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 896         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
 897                 bp->max_l2_ctx += bp->max_rx_em_flows;
 898         /* TODO: For now, do not support VMDq/RFS on VFs. */
 899         if (BNXT_PF(bp)) {
 900                 if (bp->pf->max_vfs)
 901                         bp->max_vnics = 1;
 902                 else
 903                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 904         } else {
 905                 bp->max_vnics = 1;
 906         }
 907         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 908                     bp->max_l2_ctx, bp->max_vnics);
 909         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 910         if (BNXT_PF(bp)) {
 911                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 912                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 913                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 914                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 915                         HWRM_UNLOCK();
 916                         bnxt_hwrm_ptp_qcfg(bp);
 917                 }
 918         }
 919
 920         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 921                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 922
 923         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 924                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 925                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 926         }
 927
 928         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 929                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 930
 931         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 932                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 933
 934         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
 935                 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
 936
 937 unlock:
 938         HWRM_UNLOCK();
 939
 940         return rc;
 941 }
 942
 943 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 944 {
 945         int rc;
 946
 947         rc = __bnxt_hwrm_func_qcaps(bp);
 948         if (rc == -ENOMEM)
 949                 return rc;
 950
 951         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 952                 rc = bnxt_alloc_ctx_mem(bp);
 953                 if (rc)
 954                         return rc;
 955
 956                 /* On older FW,
 957                  * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 958                  * But the error can be ignored. Return success.
 959                  */
 960                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 961                 if (!rc)
 962                         bp->flags |= BNXT_FLAG_NEW_RM;
 963         }
 964
 965         return 0;
 966 }
 967
 968 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 969 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 970 {
 971         int rc = 0;
 972         uint32_t flags;
 973         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 974         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 975
 976         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 977
 978         req.target_id = rte_cpu_to_le_16(0xffff);
 979
 980         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 981
 982         HWRM_CHECK_RESULT();
 983
 984         flags = rte_le_to_cpu_32(resp->flags);
 985
 986         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 987                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 988                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 989         }
 990
 991         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
 992                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
 993
 994         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
 995                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
 996
 997         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 998
 999         HWRM_UNLOCK();
1000
1001         return rc;
1002 }
1003
1004 int bnxt_hwrm_func_reset(struct bnxt *bp)
1005 {
1006         int rc = 0;
1007         struct hwrm_func_reset_input req = {.req_type = 0 };
1008         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1009
1010         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1011
1012         req.enables = rte_cpu_to_le_32(0);
1013
1014         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1015
1016         HWRM_CHECK_RESULT();
1017         HWRM_UNLOCK();
1018
1019         return rc;
1020 }
1021
1022 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1023 {
1024         int rc;
1025         uint32_t flags = 0;
1026         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1027         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1028
1029         if (bp->flags & BNXT_FLAG_REGISTERED)
1030                 return 0;
1031
1032         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1033                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1034         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1035                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1036
1037         /* PFs and trusted VFs should indicate the support of the
1038          * Master capability on non Stingray platform
1039          */
1040         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1041                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1042
1043         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1044         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1045                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1046         req.ver_maj = RTE_VER_YEAR;
1047         req.ver_min = RTE_VER_MONTH;
1048         req.ver_upd = RTE_VER_MINOR;
1049
1050         if (BNXT_PF(bp)) {
1051                 req.enables |= rte_cpu_to_le_32(
1052                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1053                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1054                        RTE_MIN(sizeof(req.vf_req_fwd),
1055                                sizeof(bp->pf->vf_req_fwd)));
1056         }
1057
1058         req.flags = rte_cpu_to_le_32(flags);
1059
1060         req.async_event_fwd[0] |=
1061                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1062                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1063                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1064                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1065                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1066         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1067                 req.async_event_fwd[0] |=
1068                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1069         req.async_event_fwd[1] |=
1070                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1071                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1072         if (BNXT_PF(bp))
1073                 req.async_event_fwd[1] |=
1074                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1075
1076         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1077                 req.async_event_fwd[1] |=
1078                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1079
1080         req.async_event_fwd[2] |=
1081                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST);
1082
1083         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1084
1085         HWRM_CHECK_RESULT();
1086
1087         flags = rte_le_to_cpu_32(resp->flags);
1088         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1089                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1090
1091         HWRM_UNLOCK();
1092
1093         bp->flags |= BNXT_FLAG_REGISTERED;
1094
1095         return rc;
1096 }
1097
1098 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1099 {
1100         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1101                 return 0;
1102
1103         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1104 }
1105
1106 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1107 {
1108         int rc;
1109         uint32_t flags = 0;
1110         uint32_t enables;
1111         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1112         struct hwrm_func_vf_cfg_input req = {0};
1113
1114         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1115
1116         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
1117                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
1118                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
1119                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1120                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1121
1122         if (BNXT_HAS_RING_GRPS(bp)) {
1123                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1124                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1125         }
1126
1127         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1128         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1129                                             AGG_RING_MULTIPLIER);
1130         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1131         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1132                                               bp->tx_nr_rings +
1133                                               BNXT_NUM_ASYNC_CPR(bp));
1134         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1135         if (bp->vf_resv_strategy ==
1136             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1137                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1138                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1139                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1140                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1141                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1142                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1143         } else if (bp->vf_resv_strategy ==
1144                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1145                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1146                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1147         }
1148
1149         if (test)
1150                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1151                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1152                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1153                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1154                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1155                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1156
1157         if (test && BNXT_HAS_RING_GRPS(bp))
1158                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1159
1160         req.flags = rte_cpu_to_le_32(flags);
1161         req.enables |= rte_cpu_to_le_32(enables);
1162
1163         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1164
1165         if (test)
1166                 HWRM_CHECK_RESULT_SILENT();
1167         else
1168                 HWRM_CHECK_RESULT();
1169
1170         HWRM_UNLOCK();
1171         return rc;
1172 }
1173
1174 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1175 {
1176         int rc;
1177         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1178         struct hwrm_func_resource_qcaps_input req = {0};
1179
1180         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1181         req.fid = rte_cpu_to_le_16(0xffff);
1182
1183         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1184
1185         HWRM_CHECK_RESULT_SILENT();
1186
1187         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1188         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1189         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1190         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1191         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1192         /* func_resource_qcaps does not return max_rx_em_flows.
1193          * So use the value provided by func_qcaps.
1194          */
1195         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1196         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1197                 bp->max_l2_ctx += bp->max_rx_em_flows;
1198         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1199         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1200         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1201         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1202         if (bp->vf_resv_strategy >
1203             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1204                 bp->vf_resv_strategy =
1205                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1206
1207         HWRM_UNLOCK();
1208         return rc;
1209 }
1210
1211 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1212 {
1213         int rc = 0;
1214         struct hwrm_ver_get_input req = {.req_type = 0 };
1215         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1216         uint32_t fw_version;
1217         uint16_t max_resp_len;
1218         char type[RTE_MEMZONE_NAMESIZE];
1219         uint32_t dev_caps_cfg;
1220
1221         bp->max_req_len = HWRM_MAX_REQ_LEN;
1222         bp->hwrm_cmd_timeout = timeout;
1223         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1224
1225         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1226         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1227         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1228
1229         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1230
1231         if (bp->flags & BNXT_FLAG_FW_RESET)
1232                 HWRM_CHECK_RESULT_SILENT();
1233         else
1234                 HWRM_CHECK_RESULT();
1235
1236         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1237                 rc = -EAGAIN;
1238                 goto error;
1239         }
1240
1241         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1242                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1243                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1244                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1245                 resp->hwrm_fw_rsvd_8b);
1246         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1247                      (resp->hwrm_fw_min_8b << 16) |
1248                      (resp->hwrm_fw_bld_8b << 8) |
1249                      resp->hwrm_fw_rsvd_8b;
1250         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1251                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1252
1253         fw_version = resp->hwrm_intf_maj_8b << 16;
1254         fw_version |= resp->hwrm_intf_min_8b << 8;
1255         fw_version |= resp->hwrm_intf_upd_8b;
1256         bp->hwrm_spec_code = fw_version;
1257
1258         /* def_req_timeout value is in milliseconds */
1259         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1260         /* convert timeout to usec */
1261         bp->hwrm_cmd_timeout *= 1000;
1262         if (!bp->hwrm_cmd_timeout)
1263                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1264
1265         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1266                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1267                 rc = -EINVAL;
1268                 goto error;
1269         }
1270
1271         if (bp->max_req_len > resp->max_req_win_len) {
1272                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1273                 rc = -EINVAL;
1274         }
1275
1276         bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1277
1278         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1279         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1280         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1281                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1282
1283         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1284         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1285
1286         if (bp->max_resp_len != max_resp_len) {
1287                 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1288                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1289                         bp->pdev->addr.devid, bp->pdev->addr.function);
1290
1291                 rte_free(bp->hwrm_cmd_resp_addr);
1292
1293                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1294                 if (bp->hwrm_cmd_resp_addr == NULL) {
1295                         rc = -ENOMEM;
1296                         goto error;
1297                 }
1298                 bp->hwrm_cmd_resp_dma_addr =
1299                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1300                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1301                         PMD_DRV_LOG(ERR,
1302                         "Unable to map response buffer to physical memory.\n");
1303                         rc = -ENOMEM;
1304                         goto error;
1305                 }
1306                 bp->max_resp_len = max_resp_len;
1307         }
1308
1309         if ((dev_caps_cfg &
1310                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1311             (dev_caps_cfg &
1312              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1313                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1314                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1315         }
1316
1317         if (((dev_caps_cfg &
1318               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1319              (dev_caps_cfg &
1320               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1321             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1322                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1323                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1324                         bp->pdev->addr.devid, bp->pdev->addr.function);
1325
1326                 rte_free(bp->hwrm_short_cmd_req_addr);
1327
1328                 bp->hwrm_short_cmd_req_addr =
1329                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1330                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1331                         rc = -ENOMEM;
1332                         goto error;
1333                 }
1334                 bp->hwrm_short_cmd_req_dma_addr =
1335                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1336                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1337                         rte_free(bp->hwrm_short_cmd_req_addr);
1338                         PMD_DRV_LOG(ERR,
1339                                 "Unable to map buffer to physical memory.\n");
1340                         rc = -ENOMEM;
1341                         goto error;
1342                 }
1343         }
1344         if (dev_caps_cfg &
1345             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1346                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1347                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1348         }
1349         if (dev_caps_cfg &
1350             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1351                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1352         if (dev_caps_cfg &
1353             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1354                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1355                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1356         }
1357
1358         if (dev_caps_cfg &
1359             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1360                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1361                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1362         }
1363
1364 error:
1365         HWRM_UNLOCK();
1366         return rc;
1367 }
1368
1369 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1370 {
1371         int rc;
1372         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1373         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1374
1375         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1376                 return 0;
1377
1378         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1379         req.flags = flags;
1380
1381         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1382
1383         HWRM_CHECK_RESULT();
1384         HWRM_UNLOCK();
1385
1386         return rc;
1387 }
1388
1389 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1390 {
1391         int rc = 0;
1392         struct hwrm_port_phy_cfg_input req = {0};
1393         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1394         uint32_t enables = 0;
1395
1396         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1397
1398         if (conf->link_up) {
1399                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1400                 if (bp->link_info->auto_mode && conf->link_speed) {
1401                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1402                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1403                 }
1404
1405                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1406                 /*
1407                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1408                  * any auto mode, even "none".
1409                  */
1410                 if (!conf->link_speed) {
1411                         /* No speeds specified. Enable AutoNeg - all speeds */
1412                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1413                         req.auto_mode =
1414                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1415                 } else {
1416                         if (bp->link_info->link_signal_mode) {
1417                                 enables |=
1418                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1419                                 req.force_pam4_link_speed =
1420                                         rte_cpu_to_le_16(conf->link_speed);
1421                         } else {
1422                                 req.force_link_speed =
1423                                         rte_cpu_to_le_16(conf->link_speed);
1424                         }
1425                 }
1426                 /* AutoNeg - Advertise speeds specified. */
1427                 if (conf->auto_link_speed_mask &&
1428                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1429                         req.auto_mode =
1430                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1431                         req.auto_link_speed_mask =
1432                                 conf->auto_link_speed_mask;
1433                         if (conf->auto_pam4_link_speeds) {
1434                                 enables |=
1435                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1436                                 req.auto_link_pam4_speed_mask =
1437                                         conf->auto_pam4_link_speeds;
1438                         } else {
1439                                 enables |=
1440                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1441                         }
1442                 }
1443                 if (conf->auto_link_speed &&
1444                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1445                         enables |=
1446                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1447
1448                 req.auto_duplex = conf->duplex;
1449                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1450                 req.auto_pause = conf->auto_pause;
1451                 req.force_pause = conf->force_pause;
1452                 /* Set force_pause if there is no auto or if there is a force */
1453                 if (req.auto_pause && !req.force_pause)
1454                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1455                 else
1456                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1457
1458                 req.enables = rte_cpu_to_le_32(enables);
1459         } else {
1460                 req.flags =
1461                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1462                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1463         }
1464
1465         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1466
1467         HWRM_CHECK_RESULT();
1468         HWRM_UNLOCK();
1469
1470         PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1471                     bp->eth_dev->data->port_id);
1472         return rc;
1473 }
1474
1475 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1476                                    struct bnxt_link_info *link_info)
1477 {
1478         int rc = 0;
1479         struct hwrm_port_phy_qcfg_input req = {0};
1480         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1481
1482         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1483
1484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1485
1486         HWRM_CHECK_RESULT();
1487
1488         link_info->phy_link_status = resp->link;
1489         link_info->link_up =
1490                 (link_info->phy_link_status ==
1491                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1492         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1493         link_info->duplex = resp->duplex_cfg;
1494         link_info->pause = resp->pause;
1495         link_info->auto_pause = resp->auto_pause;
1496         link_info->force_pause = resp->force_pause;
1497         link_info->auto_mode = resp->auto_mode;
1498         link_info->phy_type = resp->phy_type;
1499         link_info->media_type = resp->media_type;
1500
1501         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1502         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1503         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1504         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1505         link_info->phy_ver[0] = resp->phy_maj;
1506         link_info->phy_ver[1] = resp->phy_min;
1507         link_info->phy_ver[2] = resp->phy_bld;
1508         link_info->link_signal_mode =
1509                 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1510         link_info->force_pam4_link_speed =
1511                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1512         link_info->support_pam4_speeds =
1513                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1514         link_info->auto_pam4_link_speeds =
1515                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1516         HWRM_UNLOCK();
1517
1518         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1519                     link_info->link_speed, link_info->auto_mode,
1520                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1521                     link_info->support_speeds, link_info->force_link_speed);
1522         PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1523                     link_info->link_signal_mode,
1524                     link_info->auto_pam4_link_speeds,
1525                     link_info->support_pam4_speeds,
1526                     link_info->force_pam4_link_speed);
1527         return rc;
1528 }
1529
1530 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1531 {
1532         int rc = 0;
1533         struct hwrm_port_phy_qcaps_input req = {0};
1534         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1535         struct bnxt_link_info *link_info = bp->link_info;
1536
1537         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1538                 return 0;
1539
1540         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1541
1542         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1543
1544         HWRM_CHECK_RESULT();
1545
1546         bp->port_cnt = resp->port_cnt;
1547         if (resp->supported_speeds_auto_mode)
1548                 link_info->support_auto_speeds =
1549                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1550         if (resp->supported_pam4_speeds_auto_mode)
1551                 link_info->support_pam4_auto_speeds =
1552                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1553
1554         HWRM_UNLOCK();
1555
1556         return 0;
1557 }
1558
1559 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1560 {
1561         int i = 0;
1562
1563         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1564                 if (bp->tx_cos_queue[i].profile ==
1565                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1566                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1567                         return true;
1568                 }
1569         }
1570         return false;
1571 }
1572
1573 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1574 {
1575         int i = 0;
1576
1577         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1578                 if (bp->tx_cos_queue[i].profile !=
1579                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1580                     bp->tx_cos_queue[i].id !=
1581                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1582                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1583                         break;
1584                 }
1585         }
1586 }
1587
1588 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1589 {
1590         int rc = 0;
1591         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1592         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1593         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1594         int i;
1595
1596 get_rx_info:
1597         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1598
1599         req.flags = rte_cpu_to_le_32(dir);
1600         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1601         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1602             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1603                 req.drv_qmap_cap =
1604                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1605         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1606
1607         HWRM_CHECK_RESULT();
1608
1609         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1610                 GET_TX_QUEUE_INFO(0);
1611                 GET_TX_QUEUE_INFO(1);
1612                 GET_TX_QUEUE_INFO(2);
1613                 GET_TX_QUEUE_INFO(3);
1614                 GET_TX_QUEUE_INFO(4);
1615                 GET_TX_QUEUE_INFO(5);
1616                 GET_TX_QUEUE_INFO(6);
1617                 GET_TX_QUEUE_INFO(7);
1618         } else  {
1619                 GET_RX_QUEUE_INFO(0);
1620                 GET_RX_QUEUE_INFO(1);
1621                 GET_RX_QUEUE_INFO(2);
1622                 GET_RX_QUEUE_INFO(3);
1623                 GET_RX_QUEUE_INFO(4);
1624                 GET_RX_QUEUE_INFO(5);
1625                 GET_RX_QUEUE_INFO(6);
1626                 GET_RX_QUEUE_INFO(7);
1627         }
1628
1629         HWRM_UNLOCK();
1630
1631         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1632                 goto done;
1633
1634         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1635                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1636         } else {
1637                 int j;
1638
1639                 /* iterate and find the COSq profile to use for Tx */
1640                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1641                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1642                                 if (bp->tx_cos_queue[i].id != 0xff)
1643                                         bp->tx_cosq_id[j++] =
1644                                                 bp->tx_cos_queue[i].id;
1645                         }
1646                 } else {
1647                         /* When CoS classification is disabled, for normal NIC
1648                          * operations, ideally we should look to use LOSSY.
1649                          * If not found, fallback to the first valid profile
1650                          */
1651                         if (!bnxt_find_lossy_profile(bp))
1652                                 bnxt_find_first_valid_profile(bp);
1653
1654                 }
1655         }
1656
1657         bp->max_tc = resp->max_configurable_queues;
1658         bp->max_lltc = resp->max_configurable_lossless_queues;
1659         if (bp->max_tc > BNXT_MAX_QUEUE)
1660                 bp->max_tc = BNXT_MAX_QUEUE;
1661         bp->max_q = bp->max_tc;
1662
1663         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1664                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1665                 goto get_rx_info;
1666         }
1667
1668 done:
1669         return rc;
1670 }
1671
1672 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1673                          struct bnxt_ring *ring,
1674                          uint32_t ring_type, uint32_t map_index,
1675                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1676                          uint16_t tx_cosq_id)
1677 {
1678         int rc = 0;
1679         uint32_t enables = 0;
1680         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1681         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1682         struct rte_mempool *mb_pool;
1683         uint16_t rx_buf_size;
1684
1685         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1686
1687         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1688         req.fbo = rte_cpu_to_le_32(0);
1689         /* Association of ring index with doorbell index */
1690         req.logical_id = rte_cpu_to_le_16(map_index);
1691         req.length = rte_cpu_to_le_32(ring->ring_size);
1692
1693         switch (ring_type) {
1694         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1695                 req.ring_type = ring_type;
1696                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1697                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1698                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1699                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1700                         enables |=
1701                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1702                 break;
1703         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1704                 req.ring_type = ring_type;
1705                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1706                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1707                 if (BNXT_CHIP_P5(bp)) {
1708                         mb_pool = bp->rx_queues[0]->mb_pool;
1709                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1710                                       RTE_PKTMBUF_HEADROOM;
1711                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1712                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1713                         enables |=
1714                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1715                 }
1716                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1717                         enables |=
1718                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1719                 break;
1720         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1721                 req.ring_type = ring_type;
1722                 if (BNXT_HAS_NQ(bp)) {
1723                         /* Association of cp ring with nq */
1724                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1725                         enables |=
1726                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1727                 }
1728                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1729                 break;
1730         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1731                 req.ring_type = ring_type;
1732                 req.page_size = BNXT_PAGE_SHFT;
1733                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1734                 break;
1735         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1736                 req.ring_type = ring_type;
1737                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1738
1739                 mb_pool = bp->rx_queues[0]->mb_pool;
1740                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1741                               RTE_PKTMBUF_HEADROOM;
1742                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1743                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1744
1745                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1746                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1747                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1748                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1749                 break;
1750         default:
1751                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1752                         ring_type);
1753                 HWRM_UNLOCK();
1754                 return -EINVAL;
1755         }
1756         req.enables = rte_cpu_to_le_32(enables);
1757
1758         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1759
1760         if (rc || resp->error_code) {
1761                 if (rc == 0 && resp->error_code)
1762                         rc = rte_le_to_cpu_16(resp->error_code);
1763                 switch (ring_type) {
1764                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1765                         PMD_DRV_LOG(ERR,
1766                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1767                         HWRM_UNLOCK();
1768                         return rc;
1769                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1770                         PMD_DRV_LOG(ERR,
1771                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1772                         HWRM_UNLOCK();
1773                         return rc;
1774                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1775                         PMD_DRV_LOG(ERR,
1776                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1777                                     rc);
1778                         HWRM_UNLOCK();
1779                         return rc;
1780                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1781                         PMD_DRV_LOG(ERR,
1782                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1783                         HWRM_UNLOCK();
1784                         return rc;
1785                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1786                         PMD_DRV_LOG(ERR,
1787                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1788                         HWRM_UNLOCK();
1789                         return rc;
1790                 default:
1791                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1792                         HWRM_UNLOCK();
1793                         return rc;
1794                 }
1795         }
1796
1797         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1798         HWRM_UNLOCK();
1799         return rc;
1800 }
1801
1802 int bnxt_hwrm_ring_free(struct bnxt *bp,
1803                         struct bnxt_ring *ring, uint32_t ring_type,
1804                         uint16_t cp_ring_id)
1805 {
1806         int rc;
1807         struct hwrm_ring_free_input req = {.req_type = 0 };
1808         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1809
1810         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1811
1812         req.ring_type = ring_type;
1813         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1814         req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1815
1816         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1817
1818         if (rc || resp->error_code) {
1819                 if (rc == 0 && resp->error_code)
1820                         rc = rte_le_to_cpu_16(resp->error_code);
1821                 HWRM_UNLOCK();
1822
1823                 switch (ring_type) {
1824                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1825                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1826                                 rc);
1827                         return rc;
1828                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1829                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1830                                 rc);
1831                         return rc;
1832                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1833                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1834                                 rc);
1835                         return rc;
1836                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1837                         PMD_DRV_LOG(ERR,
1838                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1839                         return rc;
1840                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1841                         PMD_DRV_LOG(ERR,
1842                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1843                         return rc;
1844                 default:
1845                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1846                         return rc;
1847                 }
1848         }
1849         HWRM_UNLOCK();
1850         return 0;
1851 }
1852
1853 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1854 {
1855         int rc = 0;
1856         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1857         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1858
1859         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1860
1861         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1862         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1863         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1864         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1865
1866         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1867
1868         HWRM_CHECK_RESULT();
1869
1870         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1871
1872         HWRM_UNLOCK();
1873
1874         return rc;
1875 }
1876
1877 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1878 {
1879         int rc;
1880         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1881         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1882
1883         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1884
1885         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1886
1887         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1888
1889         HWRM_CHECK_RESULT();
1890         HWRM_UNLOCK();
1891
1892         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1893         return rc;
1894 }
1895
1896 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1897 {
1898         int rc = 0;
1899         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1900         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1901
1902         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1903                 return rc;
1904
1905         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1906
1907         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1908
1909         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1910
1911         HWRM_CHECK_RESULT();
1912         HWRM_UNLOCK();
1913
1914         return rc;
1915 }
1916
1917 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1918                                 unsigned int idx __rte_unused)
1919 {
1920         int rc;
1921         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1922         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1923
1924         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1925
1926         req.update_period_ms = rte_cpu_to_le_32(0);
1927
1928         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1929
1930         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1931
1932         HWRM_CHECK_RESULT();
1933
1934         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1935
1936         HWRM_UNLOCK();
1937
1938         return rc;
1939 }
1940
1941 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1942                                 unsigned int idx __rte_unused)
1943 {
1944         int rc;
1945         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1946         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1947
1948         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1949
1950         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1951
1952         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1953
1954         HWRM_CHECK_RESULT();
1955         HWRM_UNLOCK();
1956
1957         return rc;
1958 }
1959
1960 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1961 {
1962         int rc = 0, i, j;
1963         struct hwrm_vnic_alloc_input req = { 0 };
1964         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1965
1966         if (!BNXT_HAS_RING_GRPS(bp))
1967                 goto skip_ring_grps;
1968
1969         /* map ring groups to this vnic */
1970         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1971                 vnic->start_grp_id, vnic->end_grp_id);
1972         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1973                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1974
1975         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1976         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1977         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1978         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1979
1980 skip_ring_grps:
1981         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1982         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1983
1984         if (vnic->func_default)
1985                 req.flags =
1986                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1987         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1988
1989         HWRM_CHECK_RESULT();
1990
1991         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1992         HWRM_UNLOCK();
1993         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1994         return rc;
1995 }
1996
1997 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1998                                         struct bnxt_vnic_info *vnic,
1999                                         struct bnxt_plcmodes_cfg *pmode)
2000 {
2001         int rc = 0;
2002         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
2003         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2004
2005         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
2006
2007         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2008
2009         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2010
2011         HWRM_CHECK_RESULT();
2012
2013         pmode->flags = rte_le_to_cpu_32(resp->flags);
2014         /* dflt_vnic bit doesn't exist in the _cfg command */
2015         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
2016         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2017         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2018         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2019
2020         HWRM_UNLOCK();
2021
2022         return rc;
2023 }
2024
2025 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2026                                        struct bnxt_vnic_info *vnic,
2027                                        struct bnxt_plcmodes_cfg *pmode)
2028 {
2029         int rc = 0;
2030         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2031         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2032
2033         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2034                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2035                 return rc;
2036         }
2037
2038         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2039
2040         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2041         req.flags = rte_cpu_to_le_32(pmode->flags);
2042         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2043         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2044         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2045         req.enables = rte_cpu_to_le_32(
2046             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2047             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2048             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2049         );
2050
2051         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2052
2053         HWRM_CHECK_RESULT();
2054         HWRM_UNLOCK();
2055
2056         return rc;
2057 }
2058
2059 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2060 {
2061         int rc = 0;
2062         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2063         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2064         struct bnxt_plcmodes_cfg pmodes = { 0 };
2065         uint32_t ctx_enable_flag = 0;
2066         uint32_t enables = 0;
2067
2068         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2069                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2070                 return rc;
2071         }
2072
2073         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2074         if (rc)
2075                 return rc;
2076
2077         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2078
2079         if (BNXT_CHIP_P5(bp)) {
2080                 int dflt_rxq = vnic->start_grp_id;
2081                 struct bnxt_rx_ring_info *rxr;
2082                 struct bnxt_cp_ring_info *cpr;
2083                 struct bnxt_rx_queue *rxq;
2084                 int i;
2085
2086                 /*
2087                  * The first active receive ring is used as the VNIC
2088                  * default receive ring. If there are no active receive
2089                  * rings (all corresponding receive queues are stopped),
2090                  * the first receive ring is used.
2091                  */
2092                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2093                         rxq = bp->eth_dev->data->rx_queues[i];
2094                         if (rxq->rx_started) {
2095                                 dflt_rxq = i;
2096                                 break;
2097                         }
2098                 }
2099
2100                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2101                 rxr = rxq->rx_ring;
2102                 cpr = rxq->cp_ring;
2103
2104                 req.default_rx_ring_id =
2105                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2106                 req.default_cmpl_ring_id =
2107                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2108                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2109                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2110                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2111                         enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2112                         req.rx_csum_v2_mode =
2113                                 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2114                 }
2115                 goto config_mru;
2116         }
2117
2118         /* Only RSS support for now TBD: COS & LB */
2119         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2120         if (vnic->lb_rule != 0xffff)
2121                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2122         if (vnic->cos_rule != 0xffff)
2123                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2124         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2125                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2126                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2127         }
2128         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2129                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2130                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2131         }
2132
2133         enables |= ctx_enable_flag;
2134         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2135         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2136         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2137         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2138
2139 config_mru:
2140         req.enables = rte_cpu_to_le_32(enables);
2141         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2142         req.mru = rte_cpu_to_le_16(vnic->mru);
2143         /* Configure default VNIC only once. */
2144         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2145                 req.flags |=
2146                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2147                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2148         }
2149         if (vnic->vlan_strip)
2150                 req.flags |=
2151                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2152         if (vnic->bd_stall)
2153                 req.flags |=
2154                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2155         if (vnic->rss_dflt_cr)
2156                 req.flags |= rte_cpu_to_le_32(
2157                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2158
2159         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2160
2161         HWRM_CHECK_RESULT();
2162         HWRM_UNLOCK();
2163
2164         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2165
2166         return rc;
2167 }
2168
2169 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2170                 int16_t fw_vf_id)
2171 {
2172         int rc = 0;
2173         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2174         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2175
2176         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2177                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2178                 return rc;
2179         }
2180         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2181
2182         req.enables =
2183                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2184         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2185         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2186
2187         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2188
2189         HWRM_CHECK_RESULT();
2190
2191         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2192         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2193         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2194         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2195         vnic->mru = rte_le_to_cpu_16(resp->mru);
2196         vnic->func_default = rte_le_to_cpu_32(
2197                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2198         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2199                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2200         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2201                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2202         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2203                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2204
2205         HWRM_UNLOCK();
2206
2207         return rc;
2208 }
2209
2210 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2211                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2212 {
2213         int rc = 0;
2214         uint16_t ctx_id;
2215         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2216         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2217                                                 bp->hwrm_cmd_resp_addr;
2218
2219         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2220
2221         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2222         HWRM_CHECK_RESULT();
2223
2224         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2225         if (!BNXT_HAS_RING_GRPS(bp))
2226                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2227         else if (ctx_idx == 0)
2228                 vnic->rss_rule = ctx_id;
2229
2230         HWRM_UNLOCK();
2231
2232         return rc;
2233 }
2234
2235 static
2236 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2237                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2238 {
2239         int rc = 0;
2240         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2241         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2242                                                 bp->hwrm_cmd_resp_addr;
2243
2244         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2245                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2246                 return rc;
2247         }
2248         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2249
2250         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2251
2252         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2253
2254         HWRM_CHECK_RESULT();
2255         HWRM_UNLOCK();
2256
2257         return rc;
2258 }
2259
2260 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2261 {
2262         int rc = 0;
2263
2264         if (BNXT_CHIP_P5(bp)) {
2265                 int j;
2266
2267                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2268                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2269                                                       vnic,
2270                                                       vnic->fw_grp_ids[j]);
2271                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2272                 }
2273                 vnic->num_lb_ctxts = 0;
2274         } else {
2275                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2276                 vnic->rss_rule = INVALID_HW_RING_ID;
2277         }
2278
2279         return rc;
2280 }
2281
2282 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2283 {
2284         int rc = 0;
2285         struct hwrm_vnic_free_input req = {.req_type = 0 };
2286         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2287
2288         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2289                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2290                 return rc;
2291         }
2292
2293         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2294
2295         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2296
2297         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2298
2299         HWRM_CHECK_RESULT();
2300         HWRM_UNLOCK();
2301
2302         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2303         /* Configure default VNIC again if necessary. */
2304         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2305                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2306
2307         return rc;
2308 }
2309
2310 static int
2311 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2312 {
2313         int i;
2314         int rc = 0;
2315         int nr_ctxs = vnic->num_lb_ctxts;
2316         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2317         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2318
2319         for (i = 0; i < nr_ctxs; i++) {
2320                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2321
2322                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2323                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2324                 req.hash_mode_flags = vnic->hash_mode;
2325
2326                 req.hash_key_tbl_addr =
2327                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2328
2329                 req.ring_grp_tbl_addr =
2330                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2331                                          i * HW_HASH_INDEX_SIZE);
2332                 req.ring_table_pair_index = i;
2333                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2334
2335                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2336                                             BNXT_USE_CHIMP_MB);
2337
2338                 HWRM_CHECK_RESULT();
2339                 HWRM_UNLOCK();
2340         }
2341
2342         return rc;
2343 }
2344
2345 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2346                            struct bnxt_vnic_info *vnic)
2347 {
2348         int rc = 0;
2349         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2350         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2351
2352         if (!vnic->rss_table)
2353                 return 0;
2354
2355         if (BNXT_CHIP_P5(bp))
2356                 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2357
2358         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2359
2360         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2361         req.hash_mode_flags = vnic->hash_mode;
2362
2363         req.ring_grp_tbl_addr =
2364             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2365         req.hash_key_tbl_addr =
2366             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2367         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2368         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2369
2370         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2371
2372         HWRM_CHECK_RESULT();
2373         HWRM_UNLOCK();
2374
2375         return rc;
2376 }
2377
2378 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2379                         struct bnxt_vnic_info *vnic)
2380 {
2381         int rc = 0;
2382         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2383         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2384         uint16_t size;
2385
2386         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2387                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2388                 return rc;
2389         }
2390
2391         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2392
2393         req.flags = rte_cpu_to_le_32(
2394                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2395
2396         req.enables = rte_cpu_to_le_32(
2397                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2398
2399         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2400         size -= RTE_PKTMBUF_HEADROOM;
2401         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2402
2403         req.jumbo_thresh = rte_cpu_to_le_16(size);
2404         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2405
2406         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2407
2408         HWRM_CHECK_RESULT();
2409         HWRM_UNLOCK();
2410
2411         return rc;
2412 }
2413
2414 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2415                         struct bnxt_vnic_info *vnic, bool enable)
2416 {
2417         int rc = 0;
2418         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2419         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2420
2421         if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2422                 if (enable)
2423                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2424                 return -ENOTSUP;
2425         }
2426
2427         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2428                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2429                 return 0;
2430         }
2431
2432         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2433
2434         if (enable) {
2435                 req.enables = rte_cpu_to_le_32(
2436                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2437                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2438                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2439                 req.flags = rte_cpu_to_le_32(
2440                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2441                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2442                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2443                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2444                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2445                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2446                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2447                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2448                 req.min_agg_len = rte_cpu_to_le_32(512);
2449         }
2450         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2451
2452         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2453
2454         HWRM_CHECK_RESULT();
2455         HWRM_UNLOCK();
2456
2457         return rc;
2458 }
2459
2460 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2461 {
2462         struct hwrm_func_cfg_input req = {0};
2463         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2464         int rc;
2465
2466         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2467         req.enables = rte_cpu_to_le_32(
2468                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2469         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2470         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2471
2472         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2473
2474         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2475         HWRM_CHECK_RESULT();
2476         HWRM_UNLOCK();
2477
2478         bp->pf->vf_info[vf].random_mac = false;
2479
2480         return rc;
2481 }
2482
2483 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2484                                   uint64_t *dropped)
2485 {
2486         int rc = 0;
2487         struct hwrm_func_qstats_input req = {.req_type = 0};
2488         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2489
2490         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2491
2492         req.fid = rte_cpu_to_le_16(fid);
2493
2494         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2495
2496         HWRM_CHECK_RESULT();
2497
2498         if (dropped)
2499                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2500
2501         HWRM_UNLOCK();
2502
2503         return rc;
2504 }
2505
2506 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2507                           struct rte_eth_stats *stats,
2508                           struct hwrm_func_qstats_output *func_qstats)
2509 {
2510         int rc = 0;
2511         struct hwrm_func_qstats_input req = {.req_type = 0};
2512         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2513
2514         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2515
2516         req.fid = rte_cpu_to_le_16(fid);
2517
2518         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2519
2520         HWRM_CHECK_RESULT();
2521         if (func_qstats)
2522                 memcpy(func_qstats, resp,
2523                        sizeof(struct hwrm_func_qstats_output));
2524
2525         if (!stats)
2526                 goto exit;
2527
2528         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2529         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2530         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2531         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2532         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2533         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2534
2535         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2536         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2537         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2538         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2539         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2540         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2541
2542         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2543         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2544         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2545
2546 exit:
2547         HWRM_UNLOCK();
2548
2549         return rc;
2550 }
2551
2552 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2553 {
2554         int rc = 0;
2555         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2556         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2557
2558         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2559
2560         req.fid = rte_cpu_to_le_16(fid);
2561
2562         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2563
2564         HWRM_CHECK_RESULT();
2565         HWRM_UNLOCK();
2566
2567         return rc;
2568 }
2569
2570 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2571 {
2572         unsigned int i;
2573         int rc = 0;
2574
2575         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2576                 struct bnxt_tx_queue *txq;
2577                 struct bnxt_rx_queue *rxq;
2578                 struct bnxt_cp_ring_info *cpr;
2579
2580                 if (i >= bp->rx_cp_nr_rings) {
2581                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2582                         cpr = txq->cp_ring;
2583                 } else {
2584                         rxq = bp->rx_queues[i];
2585                         cpr = rxq->cp_ring;
2586                 }
2587
2588                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2589                 if (rc)
2590                         return rc;
2591         }
2592         return 0;
2593 }
2594
2595 static int
2596 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2597 {
2598         int rc;
2599         unsigned int i;
2600         struct bnxt_cp_ring_info *cpr;
2601
2602         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2603
2604                 if (i >= bp->rx_cp_nr_rings) {
2605                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2606                 } else {
2607                         cpr = bp->rx_queues[i]->cp_ring;
2608                         if (BNXT_HAS_RING_GRPS(bp))
2609                                 bp->grp_info[i].fw_stats_ctx = -1;
2610                 }
2611                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2612                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2613                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2614                         if (rc)
2615                                 return rc;
2616                 }
2617         }
2618         return 0;
2619 }
2620
2621 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2622 {
2623         unsigned int i;
2624         int rc = 0;
2625
2626         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2627                 struct bnxt_tx_queue *txq;
2628                 struct bnxt_rx_queue *rxq;
2629                 struct bnxt_cp_ring_info *cpr;
2630
2631                 if (i >= bp->rx_cp_nr_rings) {
2632                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2633                         cpr = txq->cp_ring;
2634                 } else {
2635                         rxq = bp->rx_queues[i];
2636                         cpr = rxq->cp_ring;
2637                 }
2638
2639                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2640
2641                 if (rc)
2642                         return rc;
2643         }
2644         return rc;
2645 }
2646
2647 static int
2648 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2649 {
2650         uint16_t idx;
2651         uint32_t rc = 0;
2652
2653         if (!BNXT_HAS_RING_GRPS(bp))
2654                 return 0;
2655
2656         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2657
2658                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2659                         continue;
2660
2661                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2662
2663                 if (rc)
2664                         return rc;
2665         }
2666         return rc;
2667 }
2668
2669 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2670 {
2671         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2672
2673         bnxt_hwrm_ring_free(bp, cp_ring,
2674                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2675                             INVALID_HW_RING_ID);
2676         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2677         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2678                                      sizeof(*cpr->cp_desc_ring));
2679         cpr->cp_raw_cons = 0;
2680         cpr->valid = 0;
2681 }
2682
2683 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2684 {
2685         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2686
2687         bnxt_hwrm_ring_free(bp, cp_ring,
2688                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2689                         INVALID_HW_RING_ID);
2690         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2691         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2692                         sizeof(*cpr->cp_desc_ring));
2693         cpr->cp_raw_cons = 0;
2694         cpr->valid = 0;
2695 }
2696
2697 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2698 {
2699         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2700         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2701         struct bnxt_ring *ring = rxr->rx_ring_struct;
2702         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2703
2704         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2705                 bnxt_hwrm_ring_free(bp, ring,
2706                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2707                                     cpr->cp_ring_struct->fw_ring_id);
2708                 ring->fw_ring_id = INVALID_HW_RING_ID;
2709                 if (BNXT_HAS_RING_GRPS(bp))
2710                         bp->grp_info[queue_index].rx_fw_ring_id =
2711                                                         INVALID_HW_RING_ID;
2712         }
2713         ring = rxr->ag_ring_struct;
2714         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2715                 bnxt_hwrm_ring_free(bp, ring,
2716                                     BNXT_CHIP_P5(bp) ?
2717                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2718                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2719                                     cpr->cp_ring_struct->fw_ring_id);
2720                 if (BNXT_HAS_RING_GRPS(bp))
2721                         bp->grp_info[queue_index].ag_fw_ring_id =
2722                                                         INVALID_HW_RING_ID;
2723         }
2724         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2725                 bnxt_free_cp_ring(bp, cpr);
2726
2727         if (BNXT_HAS_RING_GRPS(bp))
2728                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2729 }
2730
2731 static int
2732 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2733 {
2734         unsigned int i;
2735
2736         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2737                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2738                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2739                 struct bnxt_ring *ring = txr->tx_ring_struct;
2740                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2741
2742                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2743                         bnxt_hwrm_ring_free(bp, ring,
2744                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX,
2745                                         cpr->cp_ring_struct->fw_ring_id);
2746                         ring->fw_ring_id = INVALID_HW_RING_ID;
2747                         memset(txr->tx_desc_ring, 0,
2748                                         txr->tx_ring_struct->ring_size *
2749                                         sizeof(*txr->tx_desc_ring));
2750                         memset(txr->tx_buf_ring, 0,
2751                                         txr->tx_ring_struct->ring_size *
2752                                         sizeof(*txr->tx_buf_ring));
2753                         txr->tx_raw_prod = 0;
2754                         txr->tx_raw_cons = 0;
2755                 }
2756                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2757                         bnxt_free_cp_ring(bp, cpr);
2758                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2759                 }
2760         }
2761
2762         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2763                 bnxt_free_hwrm_rx_ring(bp, i);
2764
2765         return 0;
2766 }
2767
2768 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2769 {
2770         uint16_t i;
2771         uint32_t rc = 0;
2772
2773         if (!BNXT_HAS_RING_GRPS(bp))
2774                 return 0;
2775
2776         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2777                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2778                 if (rc)
2779                         return rc;
2780         }
2781         return rc;
2782 }
2783
2784 /*
2785  * HWRM utility functions
2786  */
2787
2788 void bnxt_free_hwrm_resources(struct bnxt *bp)
2789 {
2790         /* Release memzone */
2791         rte_free(bp->hwrm_cmd_resp_addr);
2792         rte_free(bp->hwrm_short_cmd_req_addr);
2793         bp->hwrm_cmd_resp_addr = NULL;
2794         bp->hwrm_short_cmd_req_addr = NULL;
2795         bp->hwrm_cmd_resp_dma_addr = 0;
2796         bp->hwrm_short_cmd_req_dma_addr = 0;
2797 }
2798
2799 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2800 {
2801         struct rte_pci_device *pdev = bp->pdev;
2802         char type[RTE_MEMZONE_NAMESIZE];
2803
2804         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2805                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2806         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2807         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2808         if (bp->hwrm_cmd_resp_addr == NULL)
2809                 return -ENOMEM;
2810         bp->hwrm_cmd_resp_dma_addr =
2811                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2812         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2813                 PMD_DRV_LOG(ERR,
2814                         "unable to map response address to physical memory\n");
2815                 return -ENOMEM;
2816         }
2817         rte_spinlock_init(&bp->hwrm_lock);
2818
2819         return 0;
2820 }
2821
2822 int
2823 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2824 {
2825         int rc = 0;
2826
2827         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2828                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2829                 if (rc)
2830                         return rc;
2831         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2832                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2833                 if (rc)
2834                         return rc;
2835         }
2836
2837         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2838         return rc;
2839 }
2840
2841 static int
2842 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2843 {
2844         struct bnxt_filter_info *filter;
2845         int rc = 0;
2846
2847         STAILQ_FOREACH(filter, &vnic->filter, next) {
2848                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2849                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2850                 bnxt_free_filter(bp, filter);
2851         }
2852         return rc;
2853 }
2854
2855 static int
2856 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2857 {
2858         struct bnxt_filter_info *filter;
2859         struct rte_flow *flow;
2860         int rc = 0;
2861
2862         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2863                 flow = STAILQ_FIRST(&vnic->flow_list);
2864                 filter = flow->filter;
2865                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2866                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2867
2868                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2869                 rte_free(flow);
2870         }
2871         return rc;
2872 }
2873
2874 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2875 {
2876         struct bnxt_filter_info *filter;
2877         int rc = 0;
2878
2879         STAILQ_FOREACH(filter, &vnic->filter, next) {
2880                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2881                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2882                                                      filter);
2883                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2884                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2885                                                          filter);
2886                 else
2887                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2888                                                      filter);
2889                 if (rc)
2890                         break;
2891         }
2892         return rc;
2893 }
2894
2895 static void
2896 bnxt_free_tunnel_ports(struct bnxt *bp)
2897 {
2898         if (bp->vxlan_port_cnt)
2899                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2900                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2901
2902         if (bp->geneve_port_cnt)
2903                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2904                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2905 }
2906
2907 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2908 {
2909         int i;
2910
2911         if (bp->vnic_info == NULL)
2912                 return;
2913
2914         /*
2915          * Cleanup VNICs in reverse order, to make sure the L2 filter
2916          * from vnic0 is last to be cleaned up.
2917          */
2918         for (i = bp->max_vnics - 1; i >= 0; i--) {
2919                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2920
2921                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2922                         continue;
2923
2924                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2925
2926                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2927
2928                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2929
2930                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2931
2932                 bnxt_hwrm_vnic_free(bp, vnic);
2933
2934                 rte_free(vnic->fw_grp_ids);
2935         }
2936         /* Ring resources */
2937         bnxt_free_all_hwrm_rings(bp);
2938         bnxt_free_all_hwrm_ring_grps(bp);
2939         bnxt_free_all_hwrm_stat_ctxs(bp);
2940         bnxt_free_tunnel_ports(bp);
2941 }
2942
2943 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2944 {
2945         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2946
2947         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2948                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2949
2950         switch (conf_link_speed) {
2951         case ETH_LINK_SPEED_10M_HD:
2952         case ETH_LINK_SPEED_100M_HD:
2953                 /* FALLTHROUGH */
2954                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2955         }
2956         return hw_link_duplex;
2957 }
2958
2959 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2960 {
2961         return !conf_link;
2962 }
2963
2964 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2965                                           uint16_t pam4_link)
2966 {
2967         uint16_t eth_link_speed = 0;
2968
2969         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2970                 return ETH_LINK_SPEED_AUTONEG;
2971
2972         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2973         case ETH_LINK_SPEED_100M:
2974         case ETH_LINK_SPEED_100M_HD:
2975                 /* FALLTHROUGH */
2976                 eth_link_speed =
2977                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2978                 break;
2979         case ETH_LINK_SPEED_1G:
2980                 eth_link_speed =
2981                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2982                 break;
2983         case ETH_LINK_SPEED_2_5G:
2984                 eth_link_speed =
2985                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2986                 break;
2987         case ETH_LINK_SPEED_10G:
2988                 eth_link_speed =
2989                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2990                 break;
2991         case ETH_LINK_SPEED_20G:
2992                 eth_link_speed =
2993                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2994                 break;
2995         case ETH_LINK_SPEED_25G:
2996                 eth_link_speed =
2997                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2998                 break;
2999         case ETH_LINK_SPEED_40G:
3000                 eth_link_speed =
3001                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
3002                 break;
3003         case ETH_LINK_SPEED_50G:
3004                 eth_link_speed = pam4_link ?
3005                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
3006                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
3007                 break;
3008         case ETH_LINK_SPEED_100G:
3009                 eth_link_speed = pam4_link ?
3010                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
3011                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
3012                 break;
3013         case ETH_LINK_SPEED_200G:
3014                 eth_link_speed =
3015                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3016                 break;
3017         default:
3018                 PMD_DRV_LOG(ERR,
3019                         "Unsupported link speed %d; default to AUTO\n",
3020                         conf_link_speed);
3021                 break;
3022         }
3023         return eth_link_speed;
3024 }
3025
3026 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
3027                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
3028                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
3029                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
3030                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
3031
3032 static int bnxt_validate_link_speed(struct bnxt *bp)
3033 {
3034         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3035         uint16_t port_id = bp->eth_dev->data->port_id;
3036         uint32_t link_speed_capa;
3037         uint32_t one_speed;
3038
3039         if (link_speed == ETH_LINK_SPEED_AUTONEG)
3040                 return 0;
3041
3042         link_speed_capa = bnxt_get_speed_capabilities(bp);
3043
3044         if (link_speed & ETH_LINK_SPEED_FIXED) {
3045                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
3046
3047                 if (one_speed & (one_speed - 1)) {
3048                         PMD_DRV_LOG(ERR,
3049                                 "Invalid advertised speeds (%u) for port %u\n",
3050                                 link_speed, port_id);
3051                         return -EINVAL;
3052                 }
3053                 if ((one_speed & link_speed_capa) != one_speed) {
3054                         PMD_DRV_LOG(ERR,
3055                                 "Unsupported advertised speed (%u) for port %u\n",
3056                                 link_speed, port_id);
3057                         return -EINVAL;
3058                 }
3059         } else {
3060                 if (!(link_speed & link_speed_capa)) {
3061                         PMD_DRV_LOG(ERR,
3062                                 "Unsupported advertised speeds (%u) for port %u\n",
3063                                 link_speed, port_id);
3064                         return -EINVAL;
3065                 }
3066         }
3067         return 0;
3068 }
3069
3070 static uint16_t
3071 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3072 {
3073         uint16_t ret = 0;
3074
3075         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
3076                 if (bp->link_info->support_speeds)
3077                         return bp->link_info->support_speeds;
3078                 link_speed = BNXT_SUPPORTED_SPEEDS;
3079         }
3080
3081         if (link_speed & ETH_LINK_SPEED_100M)
3082                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3083         if (link_speed & ETH_LINK_SPEED_100M_HD)
3084                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3085         if (link_speed & ETH_LINK_SPEED_1G)
3086                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3087         if (link_speed & ETH_LINK_SPEED_2_5G)
3088                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3089         if (link_speed & ETH_LINK_SPEED_10G)
3090                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3091         if (link_speed & ETH_LINK_SPEED_20G)
3092                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3093         if (link_speed & ETH_LINK_SPEED_25G)
3094                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3095         if (link_speed & ETH_LINK_SPEED_40G)
3096                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3097         if (link_speed & ETH_LINK_SPEED_50G)
3098                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3099         if (link_speed & ETH_LINK_SPEED_100G)
3100                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3101         if (link_speed & ETH_LINK_SPEED_200G)
3102                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3103         return ret;
3104 }
3105
3106 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3107 {
3108         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
3109
3110         switch (hw_link_speed) {
3111         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3112                 eth_link_speed = ETH_SPEED_NUM_100M;
3113                 break;
3114         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3115                 eth_link_speed = ETH_SPEED_NUM_1G;
3116                 break;
3117         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3118                 eth_link_speed = ETH_SPEED_NUM_2_5G;
3119                 break;
3120         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3121                 eth_link_speed = ETH_SPEED_NUM_10G;
3122                 break;
3123         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3124                 eth_link_speed = ETH_SPEED_NUM_20G;
3125                 break;
3126         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3127                 eth_link_speed = ETH_SPEED_NUM_25G;
3128                 break;
3129         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3130                 eth_link_speed = ETH_SPEED_NUM_40G;
3131                 break;
3132         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3133                 eth_link_speed = ETH_SPEED_NUM_50G;
3134                 break;
3135         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3136                 eth_link_speed = ETH_SPEED_NUM_100G;
3137                 break;
3138         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3139                 eth_link_speed = ETH_SPEED_NUM_200G;
3140                 break;
3141         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3142         default:
3143                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3144                         hw_link_speed);
3145                 break;
3146         }
3147         return eth_link_speed;
3148 }
3149
3150 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3151 {
3152         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3153
3154         switch (hw_link_duplex) {
3155         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3156         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3157                 /* FALLTHROUGH */
3158                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3159                 break;
3160         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3161                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3162                 break;
3163         default:
3164                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3165                         hw_link_duplex);
3166                 break;
3167         }
3168         return eth_link_duplex;
3169 }
3170
3171 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3172 {
3173         int rc = 0;
3174         struct bnxt_link_info *link_info = bp->link_info;
3175
3176         rc = bnxt_hwrm_port_phy_qcaps(bp);
3177         if (rc)
3178                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3179
3180         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3181         if (rc) {
3182                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3183                 goto exit;
3184         }
3185
3186         if (link_info->link_speed)
3187                 link->link_speed =
3188                         bnxt_parse_hw_link_speed(link_info->link_speed);
3189         else
3190                 link->link_speed = ETH_SPEED_NUM_NONE;
3191         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3192         link->link_status = link_info->link_up;
3193         link->link_autoneg = link_info->auto_mode ==
3194                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3195                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3196 exit:
3197         return rc;
3198 }
3199
3200 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3201 {
3202         int rc = 0;
3203         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3204         struct bnxt_link_info link_req;
3205         uint16_t speed, autoneg;
3206
3207         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3208                 return 0;
3209
3210         rc = bnxt_validate_link_speed(bp);
3211         if (rc)
3212                 goto error;
3213
3214         memset(&link_req, 0, sizeof(link_req));
3215         link_req.link_up = link_up;
3216         if (!link_up)
3217                 goto port_phy_cfg;
3218
3219         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3220         if (BNXT_CHIP_P5(bp) &&
3221             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3222                 /* 40G is not supported as part of media auto detect.
3223                  * The speed should be forced and autoneg disabled
3224                  * to configure 40G speed.
3225                  */
3226                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3227                 autoneg = 0;
3228         }
3229
3230         /* No auto speeds and no auto_pam4_link. Disable autoneg */
3231         if (bp->link_info->auto_link_speed == 0 &&
3232             bp->link_info->link_signal_mode &&
3233             bp->link_info->auto_pam4_link_speeds == 0)
3234                 autoneg = 0;
3235
3236         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3237                                           bp->link_info->link_signal_mode);
3238         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3239         /* Autoneg can be done only when the FW allows.
3240          * When user configures fixed speed of 40G and later changes to
3241          * any other speed, auto_link_speed/force_link_speed is still set
3242          * to 40G until link comes up at new speed.
3243          */
3244         if (autoneg == 1 &&
3245             !(!BNXT_CHIP_P5(bp) &&
3246               (bp->link_info->auto_link_speed ||
3247                bp->link_info->force_link_speed))) {
3248                 link_req.phy_flags |=
3249                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3250                 link_req.auto_link_speed_mask =
3251                         bnxt_parse_eth_link_speed_mask(bp,
3252                                                        dev_conf->link_speeds);
3253         } else {
3254                 if (bp->link_info->phy_type ==
3255                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3256                     bp->link_info->phy_type ==
3257                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3258                     bp->link_info->media_type ==
3259                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3260                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3261                         return -EINVAL;
3262                 }
3263
3264                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3265                 /* If user wants a particular speed try that first. */
3266                 if (speed)
3267                         link_req.link_speed = speed;
3268                 else if (bp->link_info->force_pam4_link_speed)
3269                         link_req.link_speed =
3270                                 bp->link_info->force_pam4_link_speed;
3271                 else if (bp->link_info->auto_pam4_link_speeds)
3272                         link_req.link_speed =
3273                                 bp->link_info->auto_pam4_link_speeds;
3274                 else if (bp->link_info->support_pam4_speeds)
3275                         link_req.link_speed =
3276                                 bp->link_info->support_pam4_speeds;
3277                 else if (bp->link_info->force_link_speed)
3278                         link_req.link_speed = bp->link_info->force_link_speed;
3279                 else
3280                         link_req.link_speed = bp->link_info->auto_link_speed;
3281                 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3282                  * zero. Use the auto_link_speed.
3283                  */
3284                 if (bp->link_info->auto_link_speed != 0 &&
3285                     bp->link_info->auto_pam4_link_speeds == 0)
3286                         link_req.link_speed = bp->link_info->auto_link_speed;
3287         }
3288         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3289         link_req.auto_pause = bp->link_info->auto_pause;
3290         link_req.force_pause = bp->link_info->force_pause;
3291
3292 port_phy_cfg:
3293         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3294         if (rc) {
3295                 PMD_DRV_LOG(ERR,
3296                         "Set link config failed with rc %d\n", rc);
3297         }
3298
3299 error:
3300         return rc;
3301 }
3302
3303 /* JIRA 22088 */
3304 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3305 {
3306         struct hwrm_func_qcfg_input req = {0};
3307         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3308         uint16_t flags;
3309         int rc = 0;
3310         bp->func_svif = BNXT_SVIF_INVALID;
3311         uint16_t svif_info;
3312
3313         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3314         req.fid = rte_cpu_to_le_16(0xffff);
3315
3316         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3317
3318         HWRM_CHECK_RESULT();
3319
3320         /* Hard Coded.. 0xfff VLAN ID mask */
3321         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3322
3323         svif_info = rte_le_to_cpu_16(resp->svif_info);
3324         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3325                 bp->func_svif = svif_info &
3326                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3327
3328         flags = rte_le_to_cpu_16(resp->flags);
3329         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3330                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3331
3332         if (BNXT_VF(bp) &&
3333             !BNXT_VF_IS_TRUSTED(bp) &&
3334             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3335                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3336                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3337         } else if (BNXT_VF(bp) &&
3338                    BNXT_VF_IS_TRUSTED(bp) &&
3339                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3340                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3341                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3342         }
3343
3344         if (mtu)
3345                 *mtu = rte_le_to_cpu_16(resp->mtu);
3346
3347         switch (resp->port_partition_type) {
3348         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3349         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3350         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3351                 /* FALLTHROUGH */
3352                 bp->flags |= BNXT_FLAG_NPAR_PF;
3353                 break;
3354         default:
3355                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3356                 break;
3357         }
3358
3359         bp->legacy_db_size =
3360                 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3361
3362         HWRM_UNLOCK();
3363
3364         return rc;
3365 }
3366
3367 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3368 {
3369         struct hwrm_func_qcfg_input req = {0};
3370         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3371         int rc;
3372
3373         if (!BNXT_VF_IS_TRUSTED(bp))
3374                 return 0;
3375
3376         if (!bp->parent)
3377                 return -EINVAL;
3378
3379         bp->parent->fid = BNXT_PF_FID_INVALID;
3380
3381         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3382
3383         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3384
3385         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3386
3387         HWRM_CHECK_RESULT();
3388
3389         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3390         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3391         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3392         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3393
3394         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3395         if (bp->parent->vnic == 0) {
3396                 PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
3397                 /* Use hard-coded values appropriate for current Wh+ fw. */
3398                 if (bp->parent->fid == 2)
3399                         bp->parent->vnic = 0x100;
3400                 else
3401                         bp->parent->vnic = 1;
3402         }
3403
3404         HWRM_UNLOCK();
3405
3406         return 0;
3407 }
3408
3409 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3410                                  uint16_t *vnic_id, uint16_t *svif)
3411 {
3412         struct hwrm_func_qcfg_input req = {0};
3413         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3414         uint16_t svif_info;
3415         int rc = 0;
3416
3417         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3418         req.fid = rte_cpu_to_le_16(fid);
3419
3420         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3421
3422         HWRM_CHECK_RESULT();
3423
3424         if (vnic_id)
3425                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3426
3427         svif_info = rte_le_to_cpu_16(resp->svif_info);
3428         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3429                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3430
3431         HWRM_UNLOCK();
3432
3433         return rc;
3434 }
3435
3436 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3437 {
3438         struct hwrm_port_mac_qcfg_input req = {0};
3439         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3440         uint16_t port_svif_info;
3441         int rc;
3442
3443         bp->port_svif = BNXT_SVIF_INVALID;
3444
3445         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3446                 return 0;
3447
3448         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3449
3450         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3451
3452         HWRM_CHECK_RESULT_SILENT();
3453
3454         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3455         if (port_svif_info &
3456             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3457                 bp->port_svif = port_svif_info &
3458                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3459
3460         HWRM_UNLOCK();
3461
3462         return 0;
3463 }
3464
3465 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3466                                  struct bnxt_pf_resource_info *pf_resc)
3467 {
3468         struct hwrm_func_cfg_input req = {0};
3469         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3470         uint32_t enables;
3471         int rc;
3472
3473         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3474                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3475                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3476                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3477                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3478                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3479                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3480                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3481                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3482
3483         if (BNXT_HAS_RING_GRPS(bp)) {
3484                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3485                 req.num_hw_ring_grps =
3486                         rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3487         } else if (BNXT_HAS_NQ(bp)) {
3488                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3489                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3490         }
3491
3492         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3493         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3494         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3495         req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3496         req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3497         req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3498         req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3499         req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3500         req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3501         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3502         req.fid = rte_cpu_to_le_16(0xffff);
3503         req.enables = rte_cpu_to_le_32(enables);
3504
3505         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3506
3507         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3508
3509         HWRM_CHECK_RESULT();
3510         HWRM_UNLOCK();
3511
3512         return rc;
3513 }
3514
3515 /* min values are the guaranteed resources and max values are subject
3516  * to availability. The strategy for now is to keep both min & max
3517  * values the same.
3518  */
3519 static void
3520 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3521                               struct hwrm_func_vf_resource_cfg_input *req,
3522                               int num_vfs)
3523 {
3524         req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3525                                                (num_vfs + 1));
3526         req->min_rsscos_ctx = req->max_rsscos_ctx;
3527         req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3528         req->min_stat_ctx = req->max_stat_ctx;
3529         req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3530                                                (num_vfs + 1));
3531         req->min_cmpl_rings = req->max_cmpl_rings;
3532         req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3533         req->min_tx_rings = req->max_tx_rings;
3534         req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3535         req->min_rx_rings = req->max_rx_rings;
3536         req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3537         req->min_l2_ctxs = req->max_l2_ctxs;
3538         /* TODO: For now, do not support VMDq/RFS on VFs. */
3539         req->max_vnics = rte_cpu_to_le_16(1);
3540         req->min_vnics = req->max_vnics;
3541         req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3542                                                  (num_vfs + 1));
3543         req->min_hw_ring_grps = req->max_hw_ring_grps;
3544         req->flags =
3545          rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3546 }
3547
3548 static void
3549 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3550                               struct hwrm_func_cfg_input *req,
3551                               int num_vfs)
3552 {
3553         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3554                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3555                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3556                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3557                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3558                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3559                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3560                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3561                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3562                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3563
3564         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3565                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3566                                     BNXT_NUM_VLANS);
3567         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3568         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3569                                                 (num_vfs + 1));
3570         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3571         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3572                                                (num_vfs + 1));
3573         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3574         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3575         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3576         /* TODO: For now, do not support VMDq/RFS on VFs. */
3577         req->num_vnics = rte_cpu_to_le_16(1);
3578         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3579                                                  (num_vfs + 1));
3580 }
3581
3582 /* Update the port wide resource values based on how many resources
3583  * got allocated to the VF.
3584  */
3585 static int bnxt_update_max_resources(struct bnxt *bp,
3586                                      int vf)
3587 {
3588         struct hwrm_func_qcfg_input req = {0};
3589         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3590         int rc;
3591
3592         /* Get the actual allocated values now */
3593         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3594         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3595         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3596         HWRM_CHECK_RESULT();
3597
3598         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3599         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3600         bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3601         bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3602         bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3603         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3604         bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3605
3606         HWRM_UNLOCK();
3607
3608         return 0;
3609 }
3610
3611 /* Update the PF resource values based on how many resources
3612  * got allocated to it.
3613  */
3614 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3615 {
3616         struct hwrm_func_qcfg_input req = {0};
3617         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3618         int rc;
3619
3620         /* Get the actual allocated values now */
3621         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3622         req.fid = rte_cpu_to_le_16(0xffff);
3623         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3624         HWRM_CHECK_RESULT();
3625
3626         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3627         bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3628         bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3629         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3630         bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3631         bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3632         bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3633         bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3634
3635         HWRM_UNLOCK();
3636
3637         return 0;
3638 }
3639
3640 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3641 {
3642         struct hwrm_func_qcfg_input req = {0};
3643         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3644         int rc;
3645
3646         /* Check for zero MAC address */
3647         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3648         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3649         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3650         HWRM_CHECK_RESULT();
3651         rc = rte_le_to_cpu_16(resp->vlan);
3652
3653         HWRM_UNLOCK();
3654
3655         return rc;
3656 }
3657
3658 static int bnxt_query_pf_resources(struct bnxt *bp,
3659                                    struct bnxt_pf_resource_info *pf_resc)
3660 {
3661         struct hwrm_func_qcfg_input req = {0};
3662         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3663         int rc;
3664
3665         /* And copy the allocated numbers into the pf struct */
3666         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3667         req.fid = rte_cpu_to_le_16(0xffff);
3668         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3669         HWRM_CHECK_RESULT();
3670
3671         pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3672         pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3673         pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3674         pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3675         pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3676         pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3677         pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3678         bp->pf->evb_mode = resp->evb_mode;
3679
3680         HWRM_UNLOCK();
3681
3682         return rc;
3683 }
3684
3685 static void
3686 bnxt_calculate_pf_resources(struct bnxt *bp,
3687                             struct bnxt_pf_resource_info *pf_resc,
3688                             int num_vfs)
3689 {
3690         if (!num_vfs) {
3691                 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3692                 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3693                 pf_resc->num_cp_rings = bp->max_cp_rings;
3694                 pf_resc->num_tx_rings = bp->max_tx_rings;
3695                 pf_resc->num_rx_rings = bp->max_rx_rings;
3696                 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3697                 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3698
3699                 return;
3700         }
3701
3702         pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3703                                    bp->max_rsscos_ctx % (num_vfs + 1);
3704         pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3705                                  bp->max_stat_ctx % (num_vfs + 1);
3706         pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3707                                 bp->max_cp_rings % (num_vfs + 1);
3708         pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3709                                 bp->max_tx_rings % (num_vfs + 1);
3710         pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3711                                 bp->max_rx_rings % (num_vfs + 1);
3712         pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3713                                bp->max_l2_ctx % (num_vfs + 1);
3714         pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3715                                     bp->max_ring_grps % (num_vfs + 1);
3716 }
3717
3718 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3719 {
3720         struct bnxt_pf_resource_info pf_resc = { 0 };
3721         int rc;
3722
3723         if (!BNXT_PF(bp)) {
3724                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3725                 return -EINVAL;
3726         }
3727
3728         rc = bnxt_hwrm_func_qcaps(bp);
3729         if (rc)
3730                 return rc;
3731
3732         bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3733
3734         bp->pf->func_cfg_flags &=
3735                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3736                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3737         bp->pf->func_cfg_flags |=
3738                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3739
3740         rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3741         if (rc)
3742                 return rc;
3743
3744         rc = bnxt_update_max_resources_pf_only(bp);
3745
3746         return rc;
3747 }
3748
3749 static int
3750 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3751 {
3752         size_t req_buf_sz, sz;
3753         int i, rc;
3754
3755         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3756         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3757                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3758         if (bp->pf->vf_req_buf == NULL) {
3759                 return -ENOMEM;
3760         }
3761
3762         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3763                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3764
3765         for (i = 0; i < num_vfs; i++)
3766                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3767                                              (i * HWRM_MAX_REQ_LEN);
3768
3769         rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3770         if (rc)
3771                 rte_free(bp->pf->vf_req_buf);
3772
3773         return rc;
3774 }
3775
3776 static int
3777 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3778 {
3779         struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3780         struct hwrm_func_vf_resource_cfg_input req = {0};
3781         int i, rc = 0;
3782
3783         bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3784         bp->pf->active_vfs = 0;
3785         for (i = 0; i < num_vfs; i++) {
3786                 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3787                 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3788                 rc = bnxt_hwrm_send_message(bp,
3789                                             &req,
3790                                             sizeof(req),
3791                                             BNXT_USE_CHIMP_MB);
3792                 if (rc || resp->error_code) {
3793                         PMD_DRV_LOG(ERR,
3794                                 "Failed to initialize VF %d\n", i);
3795                         PMD_DRV_LOG(ERR,
3796                                 "Not all VFs available. (%d, %d)\n",
3797                                 rc, resp->error_code);
3798                         HWRM_UNLOCK();
3799
3800                         /* If the first VF configuration itself fails,
3801                          * unregister the vf_fwd_request buffer.
3802                          */
3803                         if (i == 0)
3804                                 bnxt_hwrm_func_buf_unrgtr(bp);
3805                         break;
3806                 }
3807                 HWRM_UNLOCK();
3808
3809                 /* Update the max resource values based on the resource values
3810                  * allocated to the VF.
3811                  */
3812                 bnxt_update_max_resources(bp, i);
3813                 bp->pf->active_vfs++;
3814                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3815         }
3816
3817         return 0;
3818 }
3819
3820 static int
3821 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3822 {
3823         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3824         struct hwrm_func_cfg_input req = {0};
3825         int i, rc;
3826
3827         bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3828
3829         bp->pf->active_vfs = 0;
3830         for (i = 0; i < num_vfs; i++) {
3831                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3832                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3833                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3834                 rc = bnxt_hwrm_send_message(bp,
3835                                             &req,
3836                                             sizeof(req),
3837                                             BNXT_USE_CHIMP_MB);
3838
3839                 /* Clear enable flag for next pass */
3840                 req.enables &= ~rte_cpu_to_le_32(
3841                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3842
3843                 if (rc || resp->error_code) {
3844                         PMD_DRV_LOG(ERR,
3845                                 "Failed to initialize VF %d\n", i);
3846                         PMD_DRV_LOG(ERR,
3847                                 "Not all VFs available. (%d, %d)\n",
3848                                 rc, resp->error_code);
3849                         HWRM_UNLOCK();
3850
3851                         /* If the first VF configuration itself fails,
3852                          * unregister the vf_fwd_request buffer.
3853                          */
3854                         if (i == 0)
3855                                 bnxt_hwrm_func_buf_unrgtr(bp);
3856                         break;
3857                 }
3858
3859                 HWRM_UNLOCK();
3860
3861                 /* Update the max resource values based on the resource values
3862                  * allocated to the VF.
3863                  */
3864                 bnxt_update_max_resources(bp, i);
3865                 bp->pf->active_vfs++;
3866                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3867         }
3868
3869         return 0;
3870 }
3871
3872 static void
3873 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3874 {
3875         if (bp->flags & BNXT_FLAG_NEW_RM)
3876                 bnxt_process_vf_resc_config_new(bp, num_vfs);
3877         else
3878                 bnxt_process_vf_resc_config_old(bp, num_vfs);
3879 }
3880
3881 static void
3882 bnxt_update_pf_resources(struct bnxt *bp,
3883                          struct bnxt_pf_resource_info *pf_resc)
3884 {
3885         bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3886         bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3887         bp->max_cp_rings = pf_resc->num_cp_rings;
3888         bp->max_tx_rings = pf_resc->num_tx_rings;
3889         bp->max_rx_rings = pf_resc->num_rx_rings;
3890         bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3891 }
3892
3893 static int32_t
3894 bnxt_configure_pf_resources(struct bnxt *bp,
3895                             struct bnxt_pf_resource_info *pf_resc)
3896 {
3897         /*
3898          * We're using STD_TX_RING_MODE here which will limit the TX
3899          * rings. This will allow QoS to function properly. Not setting this
3900          * will cause PF rings to break bandwidth settings.
3901          */
3902         bp->pf->func_cfg_flags &=
3903                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3904                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3905         bp->pf->func_cfg_flags |=
3906                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3907         return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3908 }
3909
3910 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3911 {
3912         struct bnxt_pf_resource_info pf_resc = { 0 };
3913         int rc;
3914
3915         if (!BNXT_PF(bp)) {
3916                 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3917                 return -EINVAL;
3918         }
3919
3920         rc = bnxt_hwrm_func_qcaps(bp);
3921         if (rc)
3922                 return rc;
3923
3924         bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3925
3926         rc = bnxt_configure_pf_resources(bp, &pf_resc);
3927         if (rc)
3928                 return rc;
3929
3930         rc = bnxt_query_pf_resources(bp, &pf_resc);
3931         if (rc)
3932                 return rc;
3933
3934         /*
3935          * Now, create and register a buffer to hold forwarded VF requests
3936          */
3937         rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3938         if (rc)
3939                 return rc;
3940
3941         bnxt_configure_vf_resources(bp, num_vfs);
3942
3943         bnxt_update_pf_resources(bp, &pf_resc);
3944
3945         return 0;
3946 }
3947
3948 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3949 {
3950         struct hwrm_func_cfg_input req = {0};
3951         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3952         int rc;
3953
3954         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3955
3956         req.fid = rte_cpu_to_le_16(0xffff);
3957         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3958         req.evb_mode = bp->pf->evb_mode;
3959
3960         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3961         HWRM_CHECK_RESULT();
3962         HWRM_UNLOCK();
3963
3964         return rc;
3965 }
3966
3967 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3968                                 uint8_t tunnel_type)
3969 {
3970         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3971         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3972         int rc = 0;
3973
3974         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3975         req.tunnel_type = tunnel_type;
3976         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3977         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3978         HWRM_CHECK_RESULT();
3979
3980         switch (tunnel_type) {
3981         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3982                 bp->vxlan_fw_dst_port_id =
3983                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3984                 bp->vxlan_port = port;
3985                 break;
3986         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3987                 bp->geneve_fw_dst_port_id =
3988                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3989                 bp->geneve_port = port;
3990                 break;
3991         default:
3992                 break;
3993         }
3994
3995         HWRM_UNLOCK();
3996
3997         return rc;
3998 }
3999
4000 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
4001                                 uint8_t tunnel_type)
4002 {
4003         struct hwrm_tunnel_dst_port_free_input req = {0};
4004         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
4005         int rc = 0;
4006
4007         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
4008
4009         req.tunnel_type = tunnel_type;
4010         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
4011         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4012
4013         HWRM_CHECK_RESULT();
4014         HWRM_UNLOCK();
4015
4016         if (tunnel_type ==
4017             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4018                 bp->vxlan_port = 0;
4019                 bp->vxlan_port_cnt = 0;
4020         }
4021
4022         if (tunnel_type ==
4023             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4024                 bp->geneve_port = 0;
4025                 bp->geneve_port_cnt = 0;
4026         }
4027
4028         return rc;
4029 }
4030
4031 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4032                                         uint32_t flags)
4033 {
4034         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4035         struct hwrm_func_cfg_input req = {0};
4036         int rc;
4037
4038         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4039
4040         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4041         req.flags = rte_cpu_to_le_32(flags);
4042         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4043
4044         HWRM_CHECK_RESULT();
4045         HWRM_UNLOCK();
4046
4047         return rc;
4048 }
4049
4050 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4051 {
4052         uint32_t *flag = flagp;
4053
4054         vnic->flags = *flag;
4055 }
4056
4057 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4058 {
4059         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4060 }
4061
4062 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4063 {
4064         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4065         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4066         int rc;
4067
4068         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4069
4070         req.req_buf_num_pages = rte_cpu_to_le_16(1);
4071         req.req_buf_page_size =
4072                 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4073         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4074         req.req_buf_page_addr0 =
4075                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4076         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4077                 PMD_DRV_LOG(ERR,
4078                         "unable to map buffer address to physical memory\n");
4079                 HWRM_UNLOCK();
4080                 return -ENOMEM;
4081         }
4082
4083         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4084
4085         HWRM_CHECK_RESULT();
4086         HWRM_UNLOCK();
4087
4088         return rc;
4089 }
4090
4091 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4092 {
4093         int rc = 0;
4094         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4095         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4096
4097         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4098                 return 0;
4099
4100         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4101
4102         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4103
4104         HWRM_CHECK_RESULT();
4105         HWRM_UNLOCK();
4106
4107         return rc;
4108 }
4109
4110 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4111 {
4112         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4113         struct hwrm_func_cfg_input req = {0};
4114         int rc;
4115
4116         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4117
4118         req.fid = rte_cpu_to_le_16(0xffff);
4119         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4120         req.enables = rte_cpu_to_le_32(
4121                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4122         req.async_event_cr = rte_cpu_to_le_16(
4123                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4124         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4125
4126         HWRM_CHECK_RESULT();
4127         HWRM_UNLOCK();
4128
4129         return rc;
4130 }
4131
4132 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4133 {
4134         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4135         struct hwrm_func_vf_cfg_input req = {0};
4136         int rc;
4137
4138         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4139
4140         req.enables = rte_cpu_to_le_32(
4141                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4142         req.async_event_cr = rte_cpu_to_le_16(
4143                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4144         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4145
4146         HWRM_CHECK_RESULT();
4147         HWRM_UNLOCK();
4148
4149         return rc;
4150 }
4151
4152 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4153 {
4154         struct hwrm_func_cfg_input req = {0};
4155         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4156         uint16_t dflt_vlan, fid;
4157         uint32_t func_cfg_flags;
4158         int rc = 0;
4159
4160         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4161
4162         if (is_vf) {
4163                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4164                 fid = bp->pf->vf_info[vf].fid;
4165                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4166         } else {
4167                 fid = rte_cpu_to_le_16(0xffff);
4168                 func_cfg_flags = bp->pf->func_cfg_flags;
4169                 dflt_vlan = bp->vlan;
4170         }
4171
4172         req.flags = rte_cpu_to_le_32(func_cfg_flags);
4173         req.fid = rte_cpu_to_le_16(fid);
4174         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4175         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4176
4177         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4178
4179         HWRM_CHECK_RESULT();
4180         HWRM_UNLOCK();
4181
4182         return rc;
4183 }
4184
4185 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4186                         uint16_t max_bw, uint16_t enables)
4187 {
4188         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4189         struct hwrm_func_cfg_input req = {0};
4190         int rc;
4191
4192         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4193
4194         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4195         req.enables |= rte_cpu_to_le_32(enables);
4196         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4197         req.max_bw = rte_cpu_to_le_32(max_bw);
4198         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4199
4200         HWRM_CHECK_RESULT();
4201         HWRM_UNLOCK();
4202
4203         return rc;
4204 }
4205
4206 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4207 {
4208         struct hwrm_func_cfg_input req = {0};
4209         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4210         int rc = 0;
4211
4212         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4213
4214         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4215         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4216         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4217         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4218
4219         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4220
4221         HWRM_CHECK_RESULT();
4222         HWRM_UNLOCK();
4223
4224         return rc;
4225 }
4226
4227 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4228 {
4229         int rc;
4230
4231         if (BNXT_PF(bp))
4232                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4233         else
4234                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4235
4236         return rc;
4237 }
4238
4239 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4240                               void *encaped, size_t ec_size)
4241 {
4242         int rc = 0;
4243         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4244         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4245
4246         if (ec_size > sizeof(req.encap_request))
4247                 return -1;
4248
4249         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4250
4251         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4252         memcpy(req.encap_request, encaped, ec_size);
4253
4254         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4255
4256         HWRM_CHECK_RESULT();
4257         HWRM_UNLOCK();
4258
4259         return rc;
4260 }
4261
4262 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4263                                        struct rte_ether_addr *mac)
4264 {
4265         struct hwrm_func_qcfg_input req = {0};
4266         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4267         int rc;
4268
4269         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4270
4271         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4272         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4273
4274         HWRM_CHECK_RESULT();
4275
4276         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4277
4278         HWRM_UNLOCK();
4279
4280         return rc;
4281 }
4282
4283 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4284                             void *encaped, size_t ec_size)
4285 {
4286         int rc = 0;
4287         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4288         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4289
4290         if (ec_size > sizeof(req.encap_request))
4291                 return -1;
4292
4293         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4294
4295         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4296         memcpy(req.encap_request, encaped, ec_size);
4297
4298         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4299
4300         HWRM_CHECK_RESULT();
4301         HWRM_UNLOCK();
4302
4303         return rc;
4304 }
4305
4306 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
4307                          struct rte_eth_stats *stats, uint8_t rx)
4308 {
4309         int rc = 0;
4310         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4311         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4312
4313         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4314
4315         req.stat_ctx_id = rte_cpu_to_le_32(cid);
4316
4317         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4318
4319         HWRM_CHECK_RESULT();
4320
4321         if (rx) {
4322                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4323                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
4324                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
4325                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4326                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
4327                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
4328                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_discard_pkts);
4329                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_error_pkts);
4330         } else {
4331                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4332                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
4333                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
4334                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4335                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
4336                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
4337         }
4338
4339         HWRM_UNLOCK();
4340
4341         return rc;
4342 }
4343
4344 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4345 {
4346         struct hwrm_port_qstats_input req = {0};
4347         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4348         struct bnxt_pf_info *pf = bp->pf;
4349         int rc;
4350
4351         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4352
4353         req.port_id = rte_cpu_to_le_16(pf->port_id);
4354         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4355         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4356         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4357
4358         HWRM_CHECK_RESULT();
4359         HWRM_UNLOCK();
4360
4361         return rc;
4362 }
4363
4364 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4365 {
4366         struct hwrm_port_clr_stats_input req = {0};
4367         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4368         struct bnxt_pf_info *pf = bp->pf;
4369         int rc;
4370
4371         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4372         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4373             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4374                 return 0;
4375
4376         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4377
4378         req.port_id = rte_cpu_to_le_16(pf->port_id);
4379         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4380
4381         HWRM_CHECK_RESULT();
4382         HWRM_UNLOCK();
4383
4384         return rc;
4385 }
4386
4387 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4388 {
4389         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4390         struct hwrm_port_led_qcaps_input req = {0};
4391         int rc;
4392
4393         if (BNXT_VF(bp))
4394                 return 0;
4395
4396         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4397         req.port_id = bp->pf->port_id;
4398         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4399
4400         HWRM_CHECK_RESULT();
4401
4402         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4403                 unsigned int i;
4404
4405                 bp->leds->num_leds = resp->num_leds;
4406                 memcpy(bp->leds, &resp->led0_id,
4407                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4408                 for (i = 0; i < bp->leds->num_leds; i++) {
4409                         struct bnxt_led_info *led = &bp->leds[i];
4410
4411                         uint16_t caps = led->led_state_caps;
4412
4413                         if (!led->led_group_id ||
4414                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4415                                 bp->leds->num_leds = 0;
4416                                 break;
4417                         }
4418                 }
4419         }
4420
4421         HWRM_UNLOCK();
4422
4423         return rc;
4424 }
4425
4426 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4427 {
4428         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4429         struct hwrm_port_led_cfg_input req = {0};
4430         struct bnxt_led_cfg *led_cfg;
4431         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4432         uint16_t duration = 0;
4433         int rc, i;
4434
4435         if (!bp->leds->num_leds || BNXT_VF(bp))
4436                 return -EOPNOTSUPP;
4437
4438         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4439
4440         if (led_on) {
4441                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4442                 duration = rte_cpu_to_le_16(500);
4443         }
4444         req.port_id = bp->pf->port_id;
4445         req.num_leds = bp->leds->num_leds;
4446         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4447         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4448                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4449                 led_cfg->led_id = bp->leds[i].led_id;
4450                 led_cfg->led_state = led_state;
4451                 led_cfg->led_blink_on = duration;
4452                 led_cfg->led_blink_off = duration;
4453                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4454         }
4455
4456         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4457
4458         HWRM_CHECK_RESULT();
4459         HWRM_UNLOCK();
4460
4461         return rc;
4462 }
4463
4464 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4465                                uint32_t *length)
4466 {
4467         int rc;
4468         struct hwrm_nvm_get_dir_info_input req = {0};
4469         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4470
4471         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4472
4473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4474
4475         HWRM_CHECK_RESULT();
4476
4477         *entries = rte_le_to_cpu_32(resp->entries);
4478         *length = rte_le_to_cpu_32(resp->entry_length);
4479
4480         HWRM_UNLOCK();
4481         return rc;
4482 }
4483
4484 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4485 {
4486         int rc;
4487         uint32_t dir_entries;
4488         uint32_t entry_length;
4489         uint8_t *buf;
4490         size_t buflen;
4491         rte_iova_t dma_handle;
4492         struct hwrm_nvm_get_dir_entries_input req = {0};
4493         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4494
4495         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4496         if (rc != 0)
4497                 return rc;
4498
4499         *data++ = dir_entries;
4500         *data++ = entry_length;
4501         len -= 2;
4502         memset(data, 0xff, len);
4503
4504         buflen = dir_entries * entry_length;
4505         buf = rte_malloc("nvm_dir", buflen, 0);
4506         if (buf == NULL)
4507                 return -ENOMEM;
4508         dma_handle = rte_malloc_virt2iova(buf);
4509         if (dma_handle == RTE_BAD_IOVA) {
4510                 rte_free(buf);
4511                 PMD_DRV_LOG(ERR,
4512                         "unable to map response address to physical memory\n");
4513                 return -ENOMEM;
4514         }
4515         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4516         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4517         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4518
4519         if (rc == 0)
4520                 memcpy(data, buf, len > buflen ? buflen : len);
4521
4522         rte_free(buf);
4523         HWRM_CHECK_RESULT();
4524         HWRM_UNLOCK();
4525
4526         return rc;
4527 }
4528
4529 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4530                              uint32_t offset, uint32_t length,
4531                              uint8_t *data)
4532 {
4533         int rc;
4534         uint8_t *buf;
4535         rte_iova_t dma_handle;
4536         struct hwrm_nvm_read_input req = {0};
4537         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4538
4539         buf = rte_malloc("nvm_item", length, 0);
4540         if (!buf)
4541                 return -ENOMEM;
4542
4543         dma_handle = rte_malloc_virt2iova(buf);
4544         if (dma_handle == RTE_BAD_IOVA) {
4545                 rte_free(buf);
4546                 PMD_DRV_LOG(ERR,
4547                         "unable to map response address to physical memory\n");
4548                 return -ENOMEM;
4549         }
4550         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4551         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4552         req.dir_idx = rte_cpu_to_le_16(index);
4553         req.offset = rte_cpu_to_le_32(offset);
4554         req.len = rte_cpu_to_le_32(length);
4555         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4556         if (rc == 0)
4557                 memcpy(data, buf, length);
4558
4559         rte_free(buf);
4560         HWRM_CHECK_RESULT();
4561         HWRM_UNLOCK();
4562
4563         return rc;
4564 }
4565
4566 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4567 {
4568         int rc;
4569         struct hwrm_nvm_erase_dir_entry_input req = {0};
4570         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4571
4572         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4573         req.dir_idx = rte_cpu_to_le_16(index);
4574         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4575         HWRM_CHECK_RESULT();
4576         HWRM_UNLOCK();
4577
4578         return rc;
4579 }
4580
4581
4582 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4583                           uint16_t dir_ordinal, uint16_t dir_ext,
4584                           uint16_t dir_attr, const uint8_t *data,
4585                           size_t data_len)
4586 {
4587         int rc;
4588         struct hwrm_nvm_write_input req = {0};
4589         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4590         rte_iova_t dma_handle;
4591         uint8_t *buf;
4592
4593         buf = rte_malloc("nvm_write", data_len, 0);
4594         if (!buf)
4595                 return -ENOMEM;
4596
4597         dma_handle = rte_malloc_virt2iova(buf);
4598         if (dma_handle == RTE_BAD_IOVA) {
4599                 rte_free(buf);
4600                 PMD_DRV_LOG(ERR,
4601                         "unable to map response address to physical memory\n");
4602                 return -ENOMEM;
4603         }
4604         memcpy(buf, data, data_len);
4605
4606         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4607
4608         req.dir_type = rte_cpu_to_le_16(dir_type);
4609         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4610         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4611         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4612         req.dir_data_length = rte_cpu_to_le_32(data_len);
4613         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4614
4615         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4616
4617         rte_free(buf);
4618         HWRM_CHECK_RESULT();
4619         HWRM_UNLOCK();
4620
4621         return rc;
4622 }
4623
4624 static void
4625 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4626 {
4627         uint32_t *count = cbdata;
4628
4629         *count = *count + 1;
4630 }
4631
4632 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4633                                      struct bnxt_vnic_info *vnic __rte_unused)
4634 {
4635         return 0;
4636 }
4637
4638 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4639 {
4640         uint32_t count = 0;
4641
4642         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4643             &count, bnxt_vnic_count_hwrm_stub);
4644
4645         return count;
4646 }
4647
4648 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4649                                         uint16_t *vnic_ids)
4650 {
4651         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4652         struct hwrm_func_vf_vnic_ids_query_output *resp =
4653                                                 bp->hwrm_cmd_resp_addr;
4654         int rc;
4655
4656         /* First query all VNIC ids */
4657         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4658
4659         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4660         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4661         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4662
4663         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4664                 HWRM_UNLOCK();
4665                 PMD_DRV_LOG(ERR,
4666                 "unable to map VNIC ID table address to physical memory\n");
4667                 return -ENOMEM;
4668         }
4669         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4670         HWRM_CHECK_RESULT();
4671         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4672
4673         HWRM_UNLOCK();
4674
4675         return rc;
4676 }
4677
4678 /*
4679  * This function queries the VNIC IDs  for a specified VF. It then calls
4680  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4681  * Then it calls the hwrm_cb function to program this new vnic configuration.
4682  */
4683 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4684         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4685         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4686 {
4687         struct bnxt_vnic_info vnic;
4688         int rc = 0;
4689         int i, num_vnic_ids;
4690         uint16_t *vnic_ids;
4691         size_t vnic_id_sz;
4692         size_t sz;
4693
4694         /* First query all VNIC ids */
4695         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4696         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4697                         RTE_CACHE_LINE_SIZE);
4698         if (vnic_ids == NULL)
4699                 return -ENOMEM;
4700
4701         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4702                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4703
4704         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4705
4706         if (num_vnic_ids < 0)
4707                 return num_vnic_ids;
4708
4709         /* Retrieve VNIC, update bd_stall then update */
4710
4711         for (i = 0; i < num_vnic_ids; i++) {
4712                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4713                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4714                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4715                 if (rc)
4716                         break;
4717                 if (vnic.mru <= 4)      /* Indicates unallocated */
4718                         continue;
4719
4720                 vnic_cb(&vnic, cbdata);
4721
4722                 rc = hwrm_cb(bp, &vnic);
4723                 if (rc)
4724                         break;
4725         }
4726
4727         rte_free(vnic_ids);
4728
4729         return rc;
4730 }
4731
4732 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4733                                               bool on)
4734 {
4735         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4736         struct hwrm_func_cfg_input req = {0};
4737         int rc;
4738
4739         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4740
4741         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4742         req.enables |= rte_cpu_to_le_32(
4743                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4744         req.vlan_antispoof_mode = on ?
4745                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4746                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4747         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4748
4749         HWRM_CHECK_RESULT();
4750         HWRM_UNLOCK();
4751
4752         return rc;
4753 }
4754
4755 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4756 {
4757         struct bnxt_vnic_info vnic;
4758         uint16_t *vnic_ids;
4759         size_t vnic_id_sz;
4760         int num_vnic_ids, i;
4761         size_t sz;
4762         int rc;
4763
4764         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4765         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4766                         RTE_CACHE_LINE_SIZE);
4767         if (vnic_ids == NULL)
4768                 return -ENOMEM;
4769
4770         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4771                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4772
4773         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4774         if (rc <= 0)
4775                 goto exit;
4776         num_vnic_ids = rc;
4777
4778         /*
4779          * Loop through to find the default VNIC ID.
4780          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4781          * by sending the hwrm_func_qcfg command to the firmware.
4782          */
4783         for (i = 0; i < num_vnic_ids; i++) {
4784                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4785                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4786                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4787                                         bp->pf->first_vf_id + vf);
4788                 if (rc)
4789                         goto exit;
4790                 if (vnic.func_default) {
4791                         rte_free(vnic_ids);
4792                         return vnic.fw_vnic_id;
4793                 }
4794         }
4795         /* Could not find a default VNIC. */
4796         PMD_DRV_LOG(ERR, "No default VNIC\n");
4797 exit:
4798         rte_free(vnic_ids);
4799         return rc;
4800 }
4801
4802 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4803                          uint16_t dst_id,
4804                          struct bnxt_filter_info *filter)
4805 {
4806         int rc = 0;
4807         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4808         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4809         uint32_t enables = 0;
4810
4811         if (filter->fw_em_filter_id != UINT64_MAX)
4812                 bnxt_hwrm_clear_em_filter(bp, filter);
4813
4814         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4815
4816         req.flags = rte_cpu_to_le_32(filter->flags);
4817
4818         enables = filter->enables |
4819               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4820         req.dst_id = rte_cpu_to_le_16(dst_id);
4821
4822         if (filter->ip_addr_type) {
4823                 req.ip_addr_type = filter->ip_addr_type;
4824                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4825         }
4826         if (enables &
4827             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4828                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4829         if (enables &
4830             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4831                 memcpy(req.src_macaddr, filter->src_macaddr,
4832                        RTE_ETHER_ADDR_LEN);
4833         if (enables &
4834             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4835                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4836                        RTE_ETHER_ADDR_LEN);
4837         if (enables &
4838             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4839                 req.ovlan_vid = filter->l2_ovlan;
4840         if (enables &
4841             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4842                 req.ivlan_vid = filter->l2_ivlan;
4843         if (enables &
4844             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4845                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4846         if (enables &
4847             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4848                 req.ip_protocol = filter->ip_protocol;
4849         if (enables &
4850             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4851                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4852         if (enables &
4853             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4854                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4855         if (enables &
4856             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4857                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4858         if (enables &
4859             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4860                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4861         if (enables &
4862             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4863                 req.mirror_vnic_id = filter->mirror_vnic_id;
4864
4865         req.enables = rte_cpu_to_le_32(enables);
4866
4867         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4868
4869         HWRM_CHECK_RESULT();
4870
4871         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4872         HWRM_UNLOCK();
4873
4874         return rc;
4875 }
4876
4877 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4878 {
4879         int rc = 0;
4880         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4881         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4882
4883         if (filter->fw_em_filter_id == UINT64_MAX)
4884                 return 0;
4885
4886         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4887
4888         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4889
4890         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4891
4892         HWRM_CHECK_RESULT();
4893         HWRM_UNLOCK();
4894
4895         filter->fw_em_filter_id = UINT64_MAX;
4896         filter->fw_l2_filter_id = UINT64_MAX;
4897
4898         return 0;
4899 }
4900
4901 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4902                          uint16_t dst_id,
4903                          struct bnxt_filter_info *filter)
4904 {
4905         int rc = 0;
4906         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4907         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4908                                                 bp->hwrm_cmd_resp_addr;
4909         uint32_t enables = 0;
4910
4911         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4912                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4913
4914         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4915
4916         req.flags = rte_cpu_to_le_32(filter->flags);
4917
4918         enables = filter->enables |
4919               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4920         req.dst_id = rte_cpu_to_le_16(dst_id);
4921
4922         if (filter->ip_addr_type) {
4923                 req.ip_addr_type = filter->ip_addr_type;
4924                 enables |=
4925                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4926         }
4927         if (enables &
4928             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4929                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4930         if (enables &
4931             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4932                 memcpy(req.src_macaddr, filter->src_macaddr,
4933                        RTE_ETHER_ADDR_LEN);
4934         if (enables &
4935             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4936                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4937         if (enables &
4938             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4939                 req.ip_protocol = filter->ip_protocol;
4940         if (enables &
4941             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4942                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4943         if (enables &
4944             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4945                 req.src_ipaddr_mask[0] =
4946                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4947         if (enables &
4948             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4949                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4950         if (enables &
4951             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4952                 req.dst_ipaddr_mask[0] =
4953                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4954         if (enables &
4955             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4956                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4957         if (enables &
4958             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4959                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4960         if (enables &
4961             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4962                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4963         if (enables &
4964             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4965                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4966         if (enables &
4967             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4968                 req.mirror_vnic_id = filter->mirror_vnic_id;
4969
4970         req.enables = rte_cpu_to_le_32(enables);
4971
4972         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4973
4974         HWRM_CHECK_RESULT();
4975
4976         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4977         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4978         HWRM_UNLOCK();
4979
4980         return rc;
4981 }
4982
4983 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4984                                 struct bnxt_filter_info *filter)
4985 {
4986         int rc = 0;
4987         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4988         struct hwrm_cfa_ntuple_filter_free_output *resp =
4989                                                 bp->hwrm_cmd_resp_addr;
4990
4991         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4992                 return 0;
4993
4994         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4995
4996         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4997
4998         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4999
5000         HWRM_CHECK_RESULT();
5001         HWRM_UNLOCK();
5002
5003         filter->fw_ntuple_filter_id = UINT64_MAX;
5004
5005         return 0;
5006 }
5007
5008 static int
5009 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5010 {
5011         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5012         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
5013         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
5014         struct bnxt_rx_queue **rxqs = bp->rx_queues;
5015         uint16_t *ring_tbl = vnic->rss_table;
5016         int nr_ctxs = vnic->num_lb_ctxts;
5017         int max_rings = bp->rx_nr_rings;
5018         int i, j, k, cnt;
5019         int rc = 0;
5020
5021         for (i = 0, k = 0; i < nr_ctxs; i++) {
5022                 struct bnxt_rx_ring_info *rxr;
5023                 struct bnxt_cp_ring_info *cpr;
5024
5025                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5026
5027                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5028                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5029                 req.hash_mode_flags = vnic->hash_mode;
5030
5031                 req.ring_grp_tbl_addr =
5032                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5033                                      i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5034                                      2 * sizeof(*ring_tbl));
5035                 req.hash_key_tbl_addr =
5036                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5037
5038                 req.ring_table_pair_index = i;
5039                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5040
5041                 for (j = 0; j < 64; j++) {
5042                         uint16_t ring_id;
5043
5044                         /* Find next active ring. */
5045                         for (cnt = 0; cnt < max_rings; cnt++) {
5046                                 if (rx_queue_state[k] !=
5047                                                 RTE_ETH_QUEUE_STATE_STOPPED)
5048                                         break;
5049                                 if (++k == max_rings)
5050                                         k = 0;
5051                         }
5052
5053                         /* Return if no rings are active. */
5054                         if (cnt == max_rings) {
5055                                 HWRM_UNLOCK();
5056                                 return 0;
5057                         }
5058
5059                         /* Add rx/cp ring pair to RSS table. */
5060                         rxr = rxqs[k]->rx_ring;
5061                         cpr = rxqs[k]->cp_ring;
5062
5063                         ring_id = rxr->rx_ring_struct->fw_ring_id;
5064                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5065                         ring_id = cpr->cp_ring_struct->fw_ring_id;
5066                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5067
5068                         if (++k == max_rings)
5069                                 k = 0;
5070                 }
5071                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5072                                             BNXT_USE_CHIMP_MB);
5073
5074                 HWRM_CHECK_RESULT();
5075                 HWRM_UNLOCK();
5076         }
5077
5078         return rc;
5079 }
5080
5081 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5082 {
5083         unsigned int rss_idx, fw_idx, i;
5084
5085         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5086                 return 0;
5087
5088         if (!(vnic->rss_table && vnic->hash_type))
5089                 return 0;
5090
5091         if (BNXT_CHIP_P5(bp))
5092                 return bnxt_vnic_rss_configure_p5(bp, vnic);
5093
5094         /*
5095          * Fill the RSS hash & redirection table with
5096          * ring group ids for all VNICs
5097          */
5098         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5099              rss_idx++, fw_idx++) {
5100                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5101                         fw_idx %= bp->rx_cp_nr_rings;
5102                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5103                                 break;
5104                         fw_idx++;
5105                 }
5106
5107                 if (i == bp->rx_cp_nr_rings)
5108                         return 0;
5109
5110                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5111         }
5112
5113         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5114 }
5115
5116 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5117         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5118 {
5119         uint16_t flags;
5120
5121         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5122
5123         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5124         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5125
5126         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5127         req->num_cmpl_dma_aggr_during_int =
5128                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5129
5130         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5131
5132         /* min timer set to 1/2 of interrupt timer */
5133         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5134
5135         /* buf timer set to 1/4 of interrupt timer */
5136         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5137
5138         req->cmpl_aggr_dma_tmr_during_int =
5139                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5140
5141         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5142                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5143         req->flags = rte_cpu_to_le_16(flags);
5144 }
5145
5146 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5147                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5148 {
5149         struct hwrm_ring_aggint_qcaps_input req = {0};
5150         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5151         uint32_t enables;
5152         uint16_t flags;
5153         int rc;
5154
5155         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5156         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5157         HWRM_CHECK_RESULT();
5158
5159         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5160         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5161
5162         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5163                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5164         agg_req->flags = rte_cpu_to_le_16(flags);
5165         enables =
5166          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5167          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5168         agg_req->enables = rte_cpu_to_le_32(enables);
5169
5170         HWRM_UNLOCK();
5171         return rc;
5172 }
5173
5174 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5175                         struct bnxt_coal *coal, uint16_t ring_id)
5176 {
5177         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5178         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5179                                                 bp->hwrm_cmd_resp_addr;
5180         int rc;
5181
5182         /* Set ring coalesce parameters only for 100G NICs */
5183         if (BNXT_CHIP_P5(bp)) {
5184                 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5185                         return -1;
5186         } else if (bnxt_stratus_device(bp)) {
5187                 bnxt_hwrm_set_coal_params(coal, &req);
5188         } else {
5189                 return 0;
5190         }
5191
5192         HWRM_PREP(&req,
5193                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5194                   BNXT_USE_CHIMP_MB);
5195         req.ring_id = rte_cpu_to_le_16(ring_id);
5196         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5197         HWRM_CHECK_RESULT();
5198         HWRM_UNLOCK();
5199         return 0;
5200 }
5201
5202 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5203 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5204 {
5205         struct hwrm_func_backing_store_qcaps_input req = {0};
5206         struct hwrm_func_backing_store_qcaps_output *resp =
5207                 bp->hwrm_cmd_resp_addr;
5208         struct bnxt_ctx_pg_info *ctx_pg;
5209         struct bnxt_ctx_mem_info *ctx;
5210         int total_alloc_len;
5211         int rc, i, tqm_rings;
5212
5213         if (!BNXT_CHIP_P5(bp) ||
5214             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5215             BNXT_VF(bp) ||
5216             bp->ctx)
5217                 return 0;
5218
5219         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5220         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5221         HWRM_CHECK_RESULT_SILENT();
5222
5223         total_alloc_len = sizeof(*ctx);
5224         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5225                           RTE_CACHE_LINE_SIZE);
5226         if (!ctx) {
5227                 rc = -ENOMEM;
5228                 goto ctx_err;
5229         }
5230
5231         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5232         ctx->qp_min_qp1_entries =
5233                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5234         ctx->qp_max_l2_entries =
5235                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5236         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5237         ctx->srq_max_l2_entries =
5238                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5239         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5240         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5241         ctx->cq_max_l2_entries =
5242                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5243         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5244         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5245         ctx->vnic_max_vnic_entries =
5246                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5247         ctx->vnic_max_ring_table_entries =
5248                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5249         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5250         ctx->stat_max_entries =
5251                 rte_le_to_cpu_32(resp->stat_max_entries);
5252         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5253         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5254         ctx->tqm_min_entries_per_ring =
5255                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5256         ctx->tqm_max_entries_per_ring =
5257                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5258         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5259         if (!ctx->tqm_entries_multiple)
5260                 ctx->tqm_entries_multiple = 1;
5261         ctx->mrav_max_entries =
5262                 rte_le_to_cpu_32(resp->mrav_max_entries);
5263         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5264         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5265         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5266         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5267
5268         ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5269                                   RTE_MIN(ctx->tqm_fp_rings_count,
5270                                           BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5271                                   bp->max_q;
5272
5273         /* Check if the ext ring count needs to be counted.
5274          * Ext ring count is available only with new FW so we should not
5275          * look at the field on older FW.
5276          */
5277         if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5278             bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5279                 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5280                 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5281                                                   ctx->tqm_fp_rings_count);
5282         }
5283
5284         tqm_rings = ctx->tqm_fp_rings_count + 1;
5285
5286         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5287                             sizeof(*ctx_pg) * tqm_rings,
5288                             RTE_CACHE_LINE_SIZE);
5289         if (!ctx_pg) {
5290                 rc = -ENOMEM;
5291                 goto ctx_err;
5292         }
5293         for (i = 0; i < tqm_rings; i++, ctx_pg++)
5294                 ctx->tqm_mem[i] = ctx_pg;
5295
5296         bp->ctx = ctx;
5297 ctx_err:
5298         HWRM_UNLOCK();
5299         return rc;
5300 }
5301
5302 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5303 {
5304         struct hwrm_func_backing_store_cfg_input req = {0};
5305         struct hwrm_func_backing_store_cfg_output *resp =
5306                 bp->hwrm_cmd_resp_addr;
5307         struct bnxt_ctx_mem_info *ctx = bp->ctx;
5308         struct bnxt_ctx_pg_info *ctx_pg;
5309         uint32_t *num_entries;
5310         uint64_t *pg_dir;
5311         uint8_t *pg_attr;
5312         uint32_t ena;
5313         int i, rc;
5314
5315         if (!ctx)
5316                 return 0;
5317
5318         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5319         req.enables = rte_cpu_to_le_32(enables);
5320
5321         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5322                 ctx_pg = &ctx->qp_mem;
5323                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5324                 req.qp_num_qp1_entries =
5325                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5326                 req.qp_num_l2_entries =
5327                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5328                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5329                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5330                                       &req.qpc_pg_size_qpc_lvl,
5331                                       &req.qpc_page_dir);
5332         }
5333
5334         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5335                 ctx_pg = &ctx->srq_mem;
5336                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5337                 req.srq_num_l2_entries =
5338                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5339                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5340                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5341                                       &req.srq_pg_size_srq_lvl,
5342                                       &req.srq_page_dir);
5343         }
5344
5345         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5346                 ctx_pg = &ctx->cq_mem;
5347                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5348                 req.cq_num_l2_entries =
5349                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5350                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5351                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5352                                       &req.cq_pg_size_cq_lvl,
5353                                       &req.cq_page_dir);
5354         }
5355
5356         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5357                 ctx_pg = &ctx->vnic_mem;
5358                 req.vnic_num_vnic_entries =
5359                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5360                 req.vnic_num_ring_table_entries =
5361                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5362                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5363                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5364                                       &req.vnic_pg_size_vnic_lvl,
5365                                       &req.vnic_page_dir);
5366         }
5367
5368         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5369                 ctx_pg = &ctx->stat_mem;
5370                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5371                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5372                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5373                                       &req.stat_pg_size_stat_lvl,
5374                                       &req.stat_page_dir);
5375         }
5376
5377         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5378         num_entries = &req.tqm_sp_num_entries;
5379         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5380         pg_dir = &req.tqm_sp_page_dir;
5381         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5382         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5383                 if (!(enables & ena))
5384                         continue;
5385
5386                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5387
5388                 ctx_pg = ctx->tqm_mem[i];
5389                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5390                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5391         }
5392
5393         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5394                 /* DPDK does not need to configure MRAV and TIM type.
5395                  * So we are skipping over MRAV and TIM. Skip to configure
5396                  * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5397                  */
5398                 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5399                 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5400                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5401                                       &req.tqm_ring8_pg_size_tqm_ring_lvl,
5402                                       &req.tqm_ring8_page_dir);
5403         }
5404
5405         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5406         HWRM_CHECK_RESULT();
5407         HWRM_UNLOCK();
5408
5409         return rc;
5410 }
5411
5412 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5413 {
5414         struct hwrm_port_qstats_ext_input req = {0};
5415         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5416         struct bnxt_pf_info *pf = bp->pf;
5417         int rc;
5418
5419         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5420               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5421                 return 0;
5422
5423         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5424
5425         req.port_id = rte_cpu_to_le_16(pf->port_id);
5426         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5427                 req.tx_stat_host_addr =
5428                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5429                 req.tx_stat_size =
5430                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5431         }
5432         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5433                 req.rx_stat_host_addr =
5434                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5435                 req.rx_stat_size =
5436                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5437         }
5438         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5439
5440         if (rc) {
5441                 bp->fw_rx_port_stats_ext_size = 0;
5442                 bp->fw_tx_port_stats_ext_size = 0;
5443         } else {
5444                 bp->fw_rx_port_stats_ext_size =
5445                         rte_le_to_cpu_16(resp->rx_stat_size);
5446                 bp->fw_tx_port_stats_ext_size =
5447                         rte_le_to_cpu_16(resp->tx_stat_size);
5448         }
5449
5450         HWRM_CHECK_RESULT();
5451         HWRM_UNLOCK();
5452
5453         return rc;
5454 }
5455
5456 int
5457 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5458 {
5459         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5460         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5461                 bp->hwrm_cmd_resp_addr;
5462         int rc = 0;
5463
5464         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5465         req.tunnel_type = type;
5466         req.dest_fid = bp->fw_fid;
5467         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5468         HWRM_CHECK_RESULT();
5469
5470         HWRM_UNLOCK();
5471
5472         return rc;
5473 }
5474
5475 int
5476 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5477 {
5478         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5479         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5480                 bp->hwrm_cmd_resp_addr;
5481         int rc = 0;
5482
5483         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5484         req.tunnel_type = type;
5485         req.dest_fid = bp->fw_fid;
5486         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5487         HWRM_CHECK_RESULT();
5488
5489         HWRM_UNLOCK();
5490
5491         return rc;
5492 }
5493
5494 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5495 {
5496         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5497         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5498                 bp->hwrm_cmd_resp_addr;
5499         int rc = 0;
5500
5501         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5502         req.src_fid = bp->fw_fid;
5503         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5504         HWRM_CHECK_RESULT();
5505
5506         if (type)
5507                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5508
5509         HWRM_UNLOCK();
5510
5511         return rc;
5512 }
5513
5514 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5515                                    uint16_t *dst_fid)
5516 {
5517         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5518         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5519                 bp->hwrm_cmd_resp_addr;
5520         int rc = 0;
5521
5522         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5523         req.src_fid = bp->fw_fid;
5524         req.tunnel_type = tun_type;
5525         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5526         HWRM_CHECK_RESULT();
5527
5528         if (dst_fid)
5529                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5530
5531         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5532
5533         HWRM_UNLOCK();
5534
5535         return rc;
5536 }
5537
5538 int bnxt_hwrm_set_mac(struct bnxt *bp)
5539 {
5540         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5541         struct hwrm_func_vf_cfg_input req = {0};
5542         int rc = 0;
5543
5544         if (!BNXT_VF(bp))
5545                 return 0;
5546
5547         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5548
5549         req.enables =
5550                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5551         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5552
5553         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5554
5555         HWRM_CHECK_RESULT();
5556
5557         HWRM_UNLOCK();
5558
5559         return rc;
5560 }
5561
5562 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5563 {
5564         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5565         struct hwrm_func_drv_if_change_input req = {0};
5566         uint32_t flags;
5567         int rc;
5568
5569         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5570                 return 0;
5571
5572         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5573          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5574          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5575          */
5576         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5577                 return 0;
5578
5579         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5580
5581         if (up)
5582                 req.flags =
5583                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5584
5585         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5586
5587         HWRM_CHECK_RESULT();
5588         flags = rte_le_to_cpu_32(resp->flags);
5589         HWRM_UNLOCK();
5590
5591         if (!up)
5592                 return 0;
5593
5594         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5595                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5596                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5597         }
5598
5599         return 0;
5600 }
5601
5602 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5603 {
5604         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5605         struct bnxt_error_recovery_info *info = bp->recovery_info;
5606         struct hwrm_error_recovery_qcfg_input req = {0};
5607         uint32_t flags = 0;
5608         unsigned int i;
5609         int rc;
5610
5611         /* Older FW does not have error recovery support */
5612         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5613                 return 0;
5614
5615         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5616
5617         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5618
5619         HWRM_CHECK_RESULT();
5620
5621         flags = rte_le_to_cpu_32(resp->flags);
5622         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5623                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5624         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5625                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5626
5627         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5628             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5629                 rc = -EINVAL;
5630                 goto err;
5631         }
5632
5633         /* FW returned values are in units of 100msec */
5634         info->driver_polling_freq =
5635                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5636         info->master_func_wait_period =
5637                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5638         info->normal_func_wait_period =
5639                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5640         info->master_func_wait_period_after_reset =
5641                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5642         info->max_bailout_time_after_reset =
5643                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5644         info->status_regs[BNXT_FW_STATUS_REG] =
5645                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5646         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5647                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5648         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5649                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5650         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5651                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5652         info->reg_array_cnt =
5653                 rte_le_to_cpu_32(resp->reg_array_cnt);
5654
5655         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5656                 rc = -EINVAL;
5657                 goto err;
5658         }
5659
5660         for (i = 0; i < info->reg_array_cnt; i++) {
5661                 info->reset_reg[i] =
5662                         rte_le_to_cpu_32(resp->reset_reg[i]);
5663                 info->reset_reg_val[i] =
5664                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5665                 info->delay_after_reset[i] =
5666                         resp->delay_after_reset[i];
5667         }
5668 err:
5669         HWRM_UNLOCK();
5670
5671         /* Map the FW status registers */
5672         if (!rc)
5673                 rc = bnxt_map_fw_health_status_regs(bp);
5674
5675         if (rc) {
5676                 rte_free(bp->recovery_info);
5677                 bp->recovery_info = NULL;
5678         }
5679         return rc;
5680 }
5681
5682 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5683 {
5684         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5685         struct hwrm_fw_reset_input req = {0};
5686         int rc;
5687
5688         if (!BNXT_PF(bp))
5689                 return -EOPNOTSUPP;
5690
5691         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5692
5693         req.embedded_proc_type =
5694                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5695         req.selfrst_status =
5696                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5697         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5698
5699         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5700                                     BNXT_USE_KONG(bp));
5701
5702         HWRM_CHECK_RESULT();
5703         HWRM_UNLOCK();
5704
5705         return rc;
5706 }
5707
5708 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5709 {
5710         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5711         struct hwrm_port_ts_query_input req = {0};
5712         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5713         uint32_t flags = 0;
5714         int rc;
5715
5716         if (!ptp)
5717                 return 0;
5718
5719         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5720
5721         switch (path) {
5722         case BNXT_PTP_FLAGS_PATH_TX:
5723                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5724                 break;
5725         case BNXT_PTP_FLAGS_PATH_RX:
5726                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5727                 break;
5728         case BNXT_PTP_FLAGS_CURRENT_TIME:
5729                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5730                 break;
5731         }
5732
5733         req.flags = rte_cpu_to_le_32(flags);
5734         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5735
5736         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5737
5738         HWRM_CHECK_RESULT();
5739
5740         if (timestamp) {
5741                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5742                 *timestamp |=
5743                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5744         }
5745         HWRM_UNLOCK();
5746
5747         return rc;
5748 }
5749
5750 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5751 {
5752         int rc = 0;
5753
5754         struct hwrm_cfa_counter_qcaps_input req = {0};
5755         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5756
5757         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5758                 PMD_DRV_LOG(DEBUG,
5759                             "Not a PF or trusted VF. Command not supported\n");
5760                 return 0;
5761         }
5762
5763         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5764         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5765         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5766
5767         HWRM_CHECK_RESULT();
5768         if (max_fc)
5769                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5770         HWRM_UNLOCK();
5771
5772         return 0;
5773 }
5774
5775 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5776 {
5777         int rc = 0;
5778         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5779         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5780
5781         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5782                 PMD_DRV_LOG(DEBUG,
5783                             "Not a PF or trusted VF. Command not supported\n");
5784                 return 0;
5785         }
5786
5787         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5788
5789         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5790         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5791         req.page_dir = rte_cpu_to_le_64(dma_addr);
5792
5793         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5794
5795         HWRM_CHECK_RESULT();
5796         if (ctx_id) {
5797                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5798                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5799         }
5800         HWRM_UNLOCK();
5801
5802         return 0;
5803 }
5804
5805 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5806 {
5807         int rc = 0;
5808         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5809         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5810
5811         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5812                 PMD_DRV_LOG(DEBUG,
5813                             "Not a PF or trusted VF. Command not supported\n");
5814                 return 0;
5815         }
5816
5817         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5818
5819         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5820
5821         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5822
5823         HWRM_CHECK_RESULT();
5824         HWRM_UNLOCK();
5825
5826         return rc;
5827 }
5828
5829 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5830                               uint16_t cntr, uint16_t ctx_id,
5831                               uint32_t num_entries, bool enable)
5832 {
5833         struct hwrm_cfa_counter_cfg_input req = {0};
5834         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5835         uint16_t flags = 0;
5836         int rc;
5837
5838         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5839                 PMD_DRV_LOG(DEBUG,
5840                             "Not a PF or trusted VF. Command not supported\n");
5841                 return 0;
5842         }
5843
5844         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5845
5846         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5847         req.counter_type = rte_cpu_to_le_16(cntr);
5848         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5849                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5850         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5851         if (dir == BNXT_DIR_RX)
5852                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5853         else if (dir == BNXT_DIR_TX)
5854                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5855         req.flags = rte_cpu_to_le_16(flags);
5856         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5857         req.num_entries = rte_cpu_to_le_32(num_entries);
5858
5859         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5860         HWRM_CHECK_RESULT();
5861         HWRM_UNLOCK();
5862
5863         return 0;
5864 }
5865
5866 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5867                                  enum bnxt_flow_dir dir,
5868                                  uint16_t cntr,
5869                                  uint16_t num_entries)
5870 {
5871         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5872         struct hwrm_cfa_counter_qstats_input req = {0};
5873         uint16_t flow_ctx_id = 0;
5874         uint16_t flags = 0;
5875         int rc = 0;
5876
5877         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5878                 PMD_DRV_LOG(DEBUG,
5879                             "Not a PF or trusted VF. Command not supported\n");
5880                 return 0;
5881         }
5882
5883         if (dir == BNXT_DIR_RX) {
5884                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5885                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5886         } else if (dir == BNXT_DIR_TX) {
5887                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5888                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5889         }
5890
5891         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5892         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5893         req.counter_type = rte_cpu_to_le_16(cntr);
5894         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5895         req.num_entries = rte_cpu_to_le_16(num_entries);
5896         req.flags = rte_cpu_to_le_16(flags);
5897         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5898
5899         HWRM_CHECK_RESULT();
5900         HWRM_UNLOCK();
5901
5902         return 0;
5903 }
5904
5905 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5906                                 uint16_t *first_vf_id)
5907 {
5908         int rc = 0;
5909         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5910         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5911
5912         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5913
5914         req.fid = rte_cpu_to_le_16(fid);
5915
5916         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5917
5918         HWRM_CHECK_RESULT();
5919
5920         if (first_vf_id)
5921                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5922
5923         HWRM_UNLOCK();
5924
5925         return rc;
5926 }
5927
5928 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
5929 {
5930         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5931         struct hwrm_cfa_pair_alloc_input req = {0};
5932         int rc;
5933
5934         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5935                 PMD_DRV_LOG(DEBUG,
5936                             "Not a PF or trusted VF. Command not supported\n");
5937                 return 0;
5938         }
5939
5940         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
5941         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5942         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5943                  bp->eth_dev->data->name, rep_bp->vf_id);
5944
5945         req.pf_b_id = rep_bp->parent_pf_idx;
5946         req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5947                                                 rte_cpu_to_le_16(rep_bp->vf_id);
5948         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
5949         req.host_b_id = 1; /* TBD - Confirm if this is OK */
5950
5951         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
5952                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
5953         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
5954                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
5955         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
5956                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
5957         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
5958                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
5959
5960         req.q_ab = rep_bp->rep_q_r2f;
5961         req.q_ba = rep_bp->rep_q_f2r;
5962         req.fc_ab = rep_bp->rep_fc_r2f;
5963         req.fc_ba = rep_bp->rep_fc_f2r;
5964
5965         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5966         HWRM_CHECK_RESULT();
5967
5968         HWRM_UNLOCK();
5969         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
5970                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
5971         return rc;
5972 }
5973
5974 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
5975 {
5976         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
5977         struct hwrm_cfa_pair_free_input req = {0};
5978         int rc;
5979
5980         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5981                 PMD_DRV_LOG(DEBUG,
5982                             "Not a PF or trusted VF. Command not supported\n");
5983                 return 0;
5984         }
5985
5986         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
5987         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5988                  bp->eth_dev->data->name, rep_bp->vf_id);
5989         req.pf_b_id = rep_bp->parent_pf_idx;
5990         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5991         req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5992                                                 rte_cpu_to_le_16(rep_bp->vf_id);
5993         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5994         HWRM_CHECK_RESULT();
5995         HWRM_UNLOCK();
5996         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
5997                     rep_bp->vf_id);
5998         return rc;
5999 }
6000
6001 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
6002 {
6003         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
6004                                         bp->hwrm_cmd_resp_addr;
6005         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6006         uint32_t flags = 0;
6007         int rc = 0;
6008
6009         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
6010                 return 0;
6011
6012         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6013                 PMD_DRV_LOG(DEBUG,
6014                             "Not a PF or trusted VF. Command not supported\n");
6015                 return 0;
6016         }
6017
6018         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
6019         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6020
6021         HWRM_CHECK_RESULT();
6022         flags = rte_le_to_cpu_32(resp->flags);
6023         HWRM_UNLOCK();
6024
6025         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
6026                 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
6027         else
6028                 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
6029
6030         return rc;
6031 }
6032
6033 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6034                             uint32_t echo_req_data2)
6035 {
6036         struct hwrm_func_echo_response_input req = {0};
6037         struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6038         int rc;
6039
6040         HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6041         req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6042         req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6043
6044         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6045
6046         HWRM_CHECK_RESULT();
6047         HWRM_UNLOCK();
6048
6049         return rc;
6050 }
6051
6052 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6053 {
6054         struct hwrm_ver_get_input req = {.req_type = 0 };
6055         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6056         int rc = 0;
6057
6058         bp->max_req_len = HWRM_MAX_REQ_LEN;
6059         bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6060
6061         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6062         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6063         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6064         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6065
6066         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6067
6068         HWRM_CHECK_RESULT_SILENT();
6069
6070         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)
6071                 rc = -EAGAIN;
6072
6073         HWRM_UNLOCK();
6074
6075         return rc;
6076 }