drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         timeout = bp->hwrm_cmd_timeout;
 104
 105         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 106             msg_len > bp->max_req_len) {
 107                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 108
 109                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 110                 memcpy(short_cmd_req, req, msg_len);
 111
 112                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 113                 short_input.signature = rte_cpu_to_le_16(
 114                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 115                 short_input.size = rte_cpu_to_le_16(msg_len);
 116                 short_input.req_addr =
 117                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 118
 119                 data = (uint32_t *)&short_input;
 120                 msg_len = sizeof(short_input);
 121
 122                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 123         }
 124
 125         /* Write request msg to hwrm channel */
 126         for (i = 0; i < msg_len; i += 4) {
 127                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 128                 rte_write32(*data, bar);
 129                 data++;
 130         }
 131
 132         /* Zero the rest of the request space */
 133         for (; i < max_req_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 135                 rte_write32(0, bar);
 136         }
 137
 138         /* Ring channel doorbell */
 139         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 140         rte_write32(1, bar);
 141         /*
 142          * Make sure the channel doorbell ring command complete before
 143          * reading the response to avoid getting stale or invalid
 144          * responses.
 145          */
 146         rte_io_mb();
 147
 148         /* Poll for the valid bit */
 149         for (i = 0; i < timeout; i++) {
 150                 /* Sanity check on the resp->resp_len */
 151                 rte_io_rmb();
 152                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 153                         /* Last byte of resp contains the valid key */
 154                         valid = (uint8_t *)resp + resp->resp_len - 1;
 155                         if (*valid == HWRM_RESP_VALID_KEY)
 156                                 break;
 157                 }
 158                 rte_delay_us(1);
 159         }
 160
 161         if (i >= timeout) {
 162                 /* Suppress VER_GET timeout messages during reset recovery */
 163                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 164                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 165                         return -ETIMEDOUT;
 166
 167                 PMD_DRV_LOG(ERR,
 168                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 169                             req->req_type, req->seq_id);
 170                 return -ETIMEDOUT;
 171         }
 172         return 0;
 173 }
 174
 175 /*
 176  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 177  * spinlock, and does initial processing.
 178  *
 179  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 180  * releases the spinlock only if it returns. If the regular int return codes
 181  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 182  * directly, rather it should be copied and modified to suit the function.
 183  *
 184  * HWRM_UNLOCK() must be called after all response processing is completed.
 185  */
 186 #define HWRM_PREP(req, type, kong) do { \
 187         rte_spinlock_lock(&bp->hwrm_lock); \
 188         if (bp->hwrm_cmd_resp_addr == NULL) { \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 return -EACCES; \
 191         } \
 192         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 193         (req)->req_type = rte_cpu_to_le_16(type); \
 194         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 195         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 196                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 197         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 198         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 199 } while (0)
 200
 201 #define HWRM_CHECK_RESULT_SILENT() do {\
 202         if (rc) { \
 203                 rte_spinlock_unlock(&bp->hwrm_lock); \
 204                 return rc; \
 205         } \
 206         if (resp->error_code) { \
 207                 rc = rte_le_to_cpu_16(resp->error_code); \
 208                 rte_spinlock_unlock(&bp->hwrm_lock); \
 209                 return rc; \
 210         } \
 211 } while (0)
 212
 213 #define HWRM_CHECK_RESULT() do {\
 214         if (rc) { \
 215                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 216                 rte_spinlock_unlock(&bp->hwrm_lock); \
 217                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 218                         rc = -EACCES; \
 219                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 220                         rc = -ENOSPC; \
 221                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 222                         rc = -EINVAL; \
 223                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 224                         rc = -ENOTSUP; \
 225                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 226                         rc = -EAGAIN; \
 227                 else if (rc > 0) \
 228                         rc = -EIO; \
 229                 return rc; \
 230         } \
 231         if (resp->error_code) { \
 232                 rc = rte_le_to_cpu_16(resp->error_code); \
 233                 if (resp->resp_len >= 16) { \
 234                         struct hwrm_err_output *tmp_hwrm_err_op = \
 235                                                 (void *)resp; \
 236                         PMD_DRV_LOG(ERR, \
 237                                 "error %d:%d:%08x:%04x\n", \
 238                                 rc, tmp_hwrm_err_op->cmd_err, \
 239                                 rte_le_to_cpu_32(\
 240                                         tmp_hwrm_err_op->opaque_0), \
 241                                 rte_le_to_cpu_16(\
 242                                         tmp_hwrm_err_op->opaque_1)); \
 243                 } else { \
 244                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 245                 } \
 246                 rte_spinlock_unlock(&bp->hwrm_lock); \
 247                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 248                         rc = -EACCES; \
 249                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 250                         rc = -ENOSPC; \
 251                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 252                         rc = -EINVAL; \
 253                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 254                         rc = -ENOTSUP; \
 255                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 256                         rc = -EAGAIN; \
 257                 else if (rc > 0) \
 258                         rc = -EIO; \
 259                 return rc; \
 260         } \
 261 } while (0)
 262
 263 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 264
 265 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 266                                 bool use_kong_mb,
 267                                 uint16_t msg_type,
 268                                 void *msg,
 269                                 uint32_t msg_len,
 270                                 void *resp_msg,
 271                                 uint32_t resp_len)
 272 {
 273         int rc = 0;
 274         bool mailbox = BNXT_USE_CHIMP_MB;
 275         struct input *req = msg;
 276         struct output *resp = bp->hwrm_cmd_resp_addr;
 277
 278         if (use_kong_mb)
 279                 mailbox = BNXT_USE_KONG(bp);
 280
 281         HWRM_PREP(req, msg_type, mailbox);
 282
 283         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 284
 285         HWRM_CHECK_RESULT();
 286
 287         if (resp_msg)
 288                 memcpy(resp_msg, resp, resp_len);
 289
 290         HWRM_UNLOCK();
 291
 292         return rc;
 293 }
 294
 295 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 296                                   bool use_kong_mb,
 297                                   uint16_t tf_type,
 298                                   uint16_t tf_subtype,
 299                                   uint32_t *tf_response_code,
 300                                   void *msg,
 301                                   uint32_t msg_len,
 302                                   void *response,
 303                                   uint32_t response_len)
 304 {
 305         int rc = 0;
 306         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 307         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 308         bool mailbox = BNXT_USE_CHIMP_MB;
 309
 310         if (msg_len > sizeof(req.tf_req))
 311                 return -ENOMEM;
 312
 313         if (use_kong_mb)
 314                 mailbox = BNXT_USE_KONG(bp);
 315
 316         HWRM_PREP(&req, HWRM_TF, mailbox);
 317         /* Build request using the user supplied request payload.
 318          * TLV request size is checked at build time against HWRM
 319          * request max size, thus no checking required.
 320          */
 321         req.tf_type = tf_type;
 322         req.tf_subtype = tf_subtype;
 323         memcpy(req.tf_req, msg, msg_len);
 324
 325         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 326         HWRM_CHECK_RESULT();
 327
 328         /* Copy the resp to user provided response buffer */
 329         if (response != NULL)
 330                 /* Post process response data. We need to copy only
 331                  * the 'payload' as the HWRM data structure really is
 332                  * HWRM header + msg header + payload and the TFLIB
 333                  * only provided a payload place holder.
 334                  */
 335                 if (response_len != 0) {
 336                         memcpy(response,
 337                                resp->tf_resp,
 338                                response_len);
 339                 }
 340
 341         /* Extract the internal tflib response code */
 342         *tf_response_code = resp->tf_resp_code;
 343         HWRM_UNLOCK();
 344
 345         return rc;
 346 }
 347
 348 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 349 {
 350         int rc = 0;
 351         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 352         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 353
 354         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 355         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 356         req.mask = 0;
 357
 358         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 359
 360         HWRM_CHECK_RESULT();
 361         HWRM_UNLOCK();
 362
 363         return rc;
 364 }
 365
 366 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 367                                  struct bnxt_vnic_info *vnic,
 368                                  uint16_t vlan_count,
 369                                  struct bnxt_vlan_table_entry *vlan_table)
 370 {
 371         int rc = 0;
 372         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 373         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 374         uint32_t mask = 0;
 375
 376         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 377                 return rc;
 378
 379         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 380         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 381
 382         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 383                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 384         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 385                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 386
 387         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 388                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 389
 390         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 391                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 392         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 393                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 394                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 395                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 396         }
 397         if (vlan_table) {
 398                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 399                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 400                 req.vlan_tag_tbl_addr =
 401                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 402                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 403         }
 404         req.mask = rte_cpu_to_le_32(mask);
 405
 406         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 407
 408         HWRM_CHECK_RESULT();
 409         HWRM_UNLOCK();
 410
 411         return rc;
 412 }
 413
 414 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 415                         uint16_t vlan_count,
 416                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 417 {
 418         int rc = 0;
 419         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 420         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 421                                                 bp->hwrm_cmd_resp_addr;
 422
 423         /*
 424          * Older HWRM versions did not support this command, and the set_rx_mask
 425          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 426          * removed from set_rx_mask call, and this command was added.
 427          *
 428          * This command is also present from 1.7.8.11 and higher,
 429          * as well as 1.7.8.0
 430          */
 431         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 432                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 433                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 434                                         (11)))
 435                                 return 0;
 436                 }
 437         }
 438         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 439         req.fid = rte_cpu_to_le_16(fid);
 440
 441         req.vlan_tag_mask_tbl_addr =
 442                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 443         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 444
 445         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 446
 447         HWRM_CHECK_RESULT();
 448         HWRM_UNLOCK();
 449
 450         return rc;
 451 }
 452
 453 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 454                              struct bnxt_filter_info *filter)
 455 {
 456         int rc = 0;
 457         struct bnxt_filter_info *l2_filter = filter;
 458         struct bnxt_vnic_info *vnic = NULL;
 459         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 460         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 461
 462         if (filter->fw_l2_filter_id == UINT64_MAX)
 463                 return 0;
 464
 465         if (filter->matching_l2_fltr_ptr)
 466                 l2_filter = filter->matching_l2_fltr_ptr;
 467
 468         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 469                     filter, l2_filter, l2_filter->l2_ref_cnt);
 470
 471         if (l2_filter->l2_ref_cnt == 0)
 472                 return 0;
 473
 474         if (l2_filter->l2_ref_cnt > 0)
 475                 l2_filter->l2_ref_cnt--;
 476
 477         if (l2_filter->l2_ref_cnt > 0)
 478                 return 0;
 479
 480         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 481
 482         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 483
 484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 485
 486         HWRM_CHECK_RESULT();
 487         HWRM_UNLOCK();
 488
 489         filter->fw_l2_filter_id = UINT64_MAX;
 490         if (l2_filter->l2_ref_cnt == 0) {
 491                 vnic = l2_filter->vnic;
 492                 if (vnic) {
 493                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 494                                       bnxt_filter_info, next);
 495                         bnxt_free_filter(bp, l2_filter);
 496                 }
 497         }
 498
 499         return 0;
 500 }
 501
 502 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 503                          uint16_t dst_id,
 504                          struct bnxt_filter_info *filter)
 505 {
 506         int rc = 0;
 507         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 508         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 509         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 510         const struct rte_eth_vmdq_rx_conf *conf =
 511                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 512         uint32_t enables = 0;
 513         uint16_t j = dst_id - 1;
 514
 515         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 516         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 517             conf->pool_map[j].pools & (1UL << j)) {
 518                 PMD_DRV_LOG(DEBUG,
 519                         "Add vlan %u to vmdq pool %u\n",
 520                         conf->pool_map[j].vlan_id, j);
 521
 522                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 523                 filter->enables |=
 524                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 525                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 526         }
 527
 528         if (filter->fw_l2_filter_id != UINT64_MAX)
 529                 bnxt_hwrm_clear_l2_filter(bp, filter);
 530
 531         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 532
 533         /* PMD does not support XDP and RoCE */
 534         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 535                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 536         req.flags = rte_cpu_to_le_32(filter->flags);
 537
 538         enables = filter->enables |
 539               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 540         req.dst_id = rte_cpu_to_le_16(dst_id);
 541
 542         if (enables &
 543             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 544                 memcpy(req.l2_addr, filter->l2_addr,
 545                        RTE_ETHER_ADDR_LEN);
 546         if (enables &
 547             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 548                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 549                        RTE_ETHER_ADDR_LEN);
 550         if (enables &
 551             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 552                 req.l2_ovlan = filter->l2_ovlan;
 553         if (enables &
 554             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 555                 req.l2_ivlan = filter->l2_ivlan;
 556         if (enables &
 557             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 558                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 559         if (enables &
 560             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 561                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 562         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 563                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 564         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 565                 req.src_type = filter->src_type;
 566         if (filter->pri_hint) {
 567                 req.pri_hint = filter->pri_hint;
 568                 req.l2_filter_id_hint =
 569                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 570         }
 571
 572         req.enables = rte_cpu_to_le_32(enables);
 573
 574         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 575
 576         HWRM_CHECK_RESULT();
 577
 578         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 579         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 580         HWRM_UNLOCK();
 581
 582         filter->l2_ref_cnt++;
 583
 584         return rc;
 585 }
 586
 587 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 588 {
 589         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 590         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 591         uint32_t flags = 0;
 592         int rc;
 593
 594         if (!ptp)
 595                 return 0;
 596
 597         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 598
 599         if (ptp->rx_filter)
 600                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 601         else
 602                 flags |=
 603                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 604         if (ptp->tx_tstamp_en)
 605                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 606         else
 607                 flags |=
 608                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 609         req.flags = rte_cpu_to_le_32(flags);
 610         req.enables = rte_cpu_to_le_32
 611                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 612         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 613
 614         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 615         HWRM_UNLOCK();
 616
 617         return rc;
 618 }
 619
 620 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 621 {
 622         int rc = 0;
 623         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 624         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 625         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 626
 627         if (ptp)
 628                 return 0;
 629
 630         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 631
 632         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 633
 634         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 635
 636         HWRM_CHECK_RESULT();
 637
 638         if (!BNXT_CHIP_THOR(bp) &&
 639             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 640                 return 0;
 641
 642         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 643                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 644
 645         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 646         if (!ptp)
 647                 return -ENOMEM;
 648
 649         if (!BNXT_CHIP_THOR(bp)) {
 650                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 651                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 652                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 653                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 654                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 655                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 656                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 657                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 658                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 659                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 660                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 661                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 662                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 663                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 664                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 665                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 666                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 667                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 668         }
 669
 670         ptp->bp = bp;
 671         bp->ptp_cfg = ptp;
 672
 673         return 0;
 674 }
 675
 676 void bnxt_hwrm_free_vf_info(struct bnxt *bp)
 677 {
 678         int i;
 679
 680         for (i = 0; i < bp->pf->max_vfs; i++) {
 681                 rte_free(bp->pf->vf_info[i].vlan_table);
 682                 bp->pf->vf_info[i].vlan_table = NULL;
 683                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 684                 bp->pf->vf_info[i].vlan_as_table = NULL;
 685         }
 686         rte_free(bp->pf->vf_info);
 687         bp->pf->vf_info = NULL;
 688 }
 689
 690 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 691 {
 692         int rc = 0;
 693         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 694         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 695         uint16_t new_max_vfs;
 696         uint32_t flags;
 697         int i;
 698
 699         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 700
 701         req.fid = rte_cpu_to_le_16(0xffff);
 702
 703         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 704
 705         HWRM_CHECK_RESULT();
 706
 707         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 708         flags = rte_le_to_cpu_32(resp->flags);
 709         if (BNXT_PF(bp)) {
 710                 bp->pf->port_id = resp->port_id;
 711                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 712                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 713                 new_max_vfs = bp->pdev->max_vfs;
 714                 if (new_max_vfs != bp->pf->max_vfs) {
 715                         if (bp->pf->vf_info)
 716                                 bnxt_hwrm_free_vf_info(bp);
 717                         bp->pf->vf_info = rte_zmalloc("bnxt_vf_info",
 718                             sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
 719                         if (bp->pf->vf_info == NULL) {
 720                                 PMD_DRV_LOG(ERR, "Alloc vf info fail\n");
 721                                 return -ENOMEM;
 722                         }
 723                         bp->pf->max_vfs = new_max_vfs;
 724                         for (i = 0; i < new_max_vfs; i++) {
 725                                 bp->pf->vf_info[i].fid =
 726                                         bp->pf->first_vf_id + i;
 727                                 bp->pf->vf_info[i].vlan_table =
 728                                         rte_zmalloc("VF VLAN table",
 729                                                     getpagesize(),
 730                                                     getpagesize());
 731                                 if (bp->pf->vf_info[i].vlan_table == NULL)
 732                                         PMD_DRV_LOG(ERR,
 733                                         "Fail to alloc VLAN table for VF %d\n",
 734                                         i);
 735                                 else
 736                                         rte_mem_lock_page(
 737                                                 bp->pf->vf_info[i].vlan_table);
 738                                 bp->pf->vf_info[i].vlan_as_table =
 739                                         rte_zmalloc("VF VLAN AS table",
 740                                                     getpagesize(),
 741                                                     getpagesize());
 742                                 if (bp->pf->vf_info[i].vlan_as_table == NULL)
 743                                         PMD_DRV_LOG(ERR,
 744                                         "Alloc VLAN AS table for VF %d fail\n",
 745                                         i);
 746                                 else
 747                                         rte_mem_lock_page(
 748                                               bp->pf->vf_info[i].vlan_as_table);
 749                                 STAILQ_INIT(&bp->pf->vf_info[i].filter);
 750                         }
 751                 }
 752         }
 753
 754         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 755         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 756                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 757                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 758         } else {
 759                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 760         }
 761         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 762         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 763         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 764         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 765         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 766         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 767         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 768         if (!BNXT_CHIP_THOR(bp))
 769                 bp->max_l2_ctx += bp->max_rx_em_flows;
 770         /* TODO: For now, do not support VMDq/RFS on VFs. */
 771         if (BNXT_PF(bp)) {
 772                 if (bp->pf->max_vfs)
 773                         bp->max_vnics = 1;
 774                 else
 775                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 776         } else {
 777                 bp->max_vnics = 1;
 778         }
 779         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 780                     bp->max_l2_ctx, bp->max_vnics);
 781         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 782         if (BNXT_PF(bp)) {
 783                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 784                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 785                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 786                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 787                         HWRM_UNLOCK();
 788                         bnxt_hwrm_ptp_qcfg(bp);
 789                 }
 790         }
 791
 792         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 793                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 794
 795         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 796                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 797                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 798         }
 799
 800         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 801                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 802
 803         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 804                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 805
 806         HWRM_UNLOCK();
 807
 808         return rc;
 809 }
 810
 811 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 812 {
 813         int rc;
 814
 815         rc = __bnxt_hwrm_func_qcaps(bp);
 816         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 817                 rc = bnxt_alloc_ctx_mem(bp);
 818                 if (rc)
 819                         return rc;
 820
 821                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 822                 if (!rc)
 823                         bp->flags |= BNXT_FLAG_NEW_RM;
 824         }
 825
 826         /* On older FW,
 827          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 828          * But the error can be ignored. Return success.
 829          */
 830
 831         return 0;
 832 }
 833
 834 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 835 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 836 {
 837         int rc = 0;
 838         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 839         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 840
 841         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 842
 843         req.target_id = rte_cpu_to_le_16(0xffff);
 844
 845         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 846
 847         HWRM_CHECK_RESULT();
 848
 849         if (rte_le_to_cpu_32(resp->flags) &
 850             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 851                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 852                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 853         }
 854
 855         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 856
 857         HWRM_UNLOCK();
 858
 859         return rc;
 860 }
 861
 862 int bnxt_hwrm_func_reset(struct bnxt *bp)
 863 {
 864         int rc = 0;
 865         struct hwrm_func_reset_input req = {.req_type = 0 };
 866         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 867
 868         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
 869
 870         req.enables = rte_cpu_to_le_32(0);
 871
 872         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 873
 874         HWRM_CHECK_RESULT();
 875         HWRM_UNLOCK();
 876
 877         return rc;
 878 }
 879
 880 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 881 {
 882         int rc;
 883         uint32_t flags = 0;
 884         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 885         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 886
 887         if (bp->flags & BNXT_FLAG_REGISTERED)
 888                 return 0;
 889
 890         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 891                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 892         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 893                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 894
 895         /* PFs and trusted VFs should indicate the support of the
 896          * Master capability on non Stingray platform
 897          */
 898         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 899                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 900
 901         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 902         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 903                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 904         req.ver_maj = RTE_VER_YEAR;
 905         req.ver_min = RTE_VER_MONTH;
 906         req.ver_upd = RTE_VER_MINOR;
 907
 908         if (BNXT_PF(bp)) {
 909                 req.enables |= rte_cpu_to_le_32(
 910                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 911                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
 912                        RTE_MIN(sizeof(req.vf_req_fwd),
 913                                sizeof(bp->pf->vf_req_fwd)));
 914
 915                 /*
 916                  * PF can sniff HWRM API issued by VF. This can be set up by
 917                  * linux driver and inherited by the DPDK PF driver. Clear
 918                  * this HWRM sniffer list in FW because DPDK PF driver does
 919                  * not support this.
 920                  */
 921                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 922         }
 923
 924         req.flags = rte_cpu_to_le_32(flags);
 925
 926         req.async_event_fwd[0] |=
 927                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 928                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 929                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 930                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 931                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 932         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 933                 req.async_event_fwd[0] |=
 934                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 935         req.async_event_fwd[1] |=
 936                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 937                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 938         if (BNXT_PF(bp))
 939                 req.async_event_fwd[1] |=
 940                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 941
 942         if (BNXT_VF_IS_TRUSTED(bp))
 943                 req.async_event_fwd[1] |=
 944                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
 945
 946         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 947
 948         HWRM_CHECK_RESULT();
 949
 950         flags = rte_le_to_cpu_32(resp->flags);
 951         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 952                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 953
 954         HWRM_UNLOCK();
 955
 956         bp->flags |= BNXT_FLAG_REGISTERED;
 957
 958         return rc;
 959 }
 960
 961 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 962 {
 963         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 964                 return 0;
 965
 966         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 967 }
 968
 969 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 970 {
 971         int rc;
 972         uint32_t flags = 0;
 973         uint32_t enables;
 974         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 975         struct hwrm_func_vf_cfg_input req = {0};
 976
 977         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 978
 979         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 980                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 981                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 982                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 983                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 984
 985         if (BNXT_HAS_RING_GRPS(bp)) {
 986                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 987                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 988         }
 989
 990         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 991         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 992                                             AGG_RING_MULTIPLIER);
 993         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 994         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 995                                               bp->tx_nr_rings +
 996                                               BNXT_NUM_ASYNC_CPR(bp));
 997         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 998         if (bp->vf_resv_strategy ==
 999             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1000                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1001                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1002                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1003                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1004                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1005                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1006         } else if (bp->vf_resv_strategy ==
1007                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1008                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1009                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1010         }
1011
1012         if (test)
1013                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1014                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1015                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1016                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1017                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1018                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1019
1020         if (test && BNXT_HAS_RING_GRPS(bp))
1021                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1022
1023         req.flags = rte_cpu_to_le_32(flags);
1024         req.enables |= rte_cpu_to_le_32(enables);
1025
1026         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1027
1028         if (test)
1029                 HWRM_CHECK_RESULT_SILENT();
1030         else
1031                 HWRM_CHECK_RESULT();
1032
1033         HWRM_UNLOCK();
1034         return rc;
1035 }
1036
1037 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1038 {
1039         int rc;
1040         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1041         struct hwrm_func_resource_qcaps_input req = {0};
1042
1043         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1044         req.fid = rte_cpu_to_le_16(0xffff);
1045
1046         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1047
1048         HWRM_CHECK_RESULT_SILENT();
1049
1050         if (BNXT_VF(bp)) {
1051                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1052                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1053                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1054                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1055                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1056                 /* func_resource_qcaps does not return max_rx_em_flows.
1057                  * So use the value provided by func_qcaps.
1058                  */
1059                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1060                 if (!BNXT_CHIP_THOR(bp))
1061                         bp->max_l2_ctx += bp->max_rx_em_flows;
1062                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1063                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1064         }
1065         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1066         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1067         if (bp->vf_resv_strategy >
1068             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1069                 bp->vf_resv_strategy =
1070                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1071
1072         HWRM_UNLOCK();
1073         return rc;
1074 }
1075
1076 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1077 {
1078         int rc = 0;
1079         struct hwrm_ver_get_input req = {.req_type = 0 };
1080         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1081         uint32_t fw_version;
1082         uint16_t max_resp_len;
1083         char type[RTE_MEMZONE_NAMESIZE];
1084         uint32_t dev_caps_cfg;
1085
1086         bp->max_req_len = HWRM_MAX_REQ_LEN;
1087         bp->hwrm_cmd_timeout = timeout;
1088         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1089
1090         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1091         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1092         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1093
1094         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1095
1096         if (bp->flags & BNXT_FLAG_FW_RESET)
1097                 HWRM_CHECK_RESULT_SILENT();
1098         else
1099                 HWRM_CHECK_RESULT();
1100
1101         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1102                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1103                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1104                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1105         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1106                      (resp->hwrm_fw_min_8b << 16) |
1107                      (resp->hwrm_fw_bld_8b << 8) |
1108                      resp->hwrm_fw_rsvd_8b;
1109         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1110                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1111
1112         fw_version = resp->hwrm_intf_maj_8b << 16;
1113         fw_version |= resp->hwrm_intf_min_8b << 8;
1114         fw_version |= resp->hwrm_intf_upd_8b;
1115         bp->hwrm_spec_code = fw_version;
1116
1117         /* def_req_timeout value is in milliseconds */
1118         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1119         /* convert timeout to usec */
1120         bp->hwrm_cmd_timeout *= 1000;
1121         if (!bp->hwrm_cmd_timeout)
1122                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1123
1124         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1125                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1126                 rc = -EINVAL;
1127                 goto error;
1128         }
1129
1130         if (bp->max_req_len > resp->max_req_win_len) {
1131                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1132                 rc = -EINVAL;
1133         }
1134         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1135         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1136         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1137                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1138
1139         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1140         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1141
1142         if (bp->max_resp_len != max_resp_len) {
1143                 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1144                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1145                         bp->pdev->addr.devid, bp->pdev->addr.function);
1146
1147                 rte_free(bp->hwrm_cmd_resp_addr);
1148
1149                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1150                 if (bp->hwrm_cmd_resp_addr == NULL) {
1151                         rc = -ENOMEM;
1152                         goto error;
1153                 }
1154                 bp->hwrm_cmd_resp_dma_addr =
1155                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1156                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1157                         PMD_DRV_LOG(ERR,
1158                         "Unable to map response buffer to physical memory.\n");
1159                         rc = -ENOMEM;
1160                         goto error;
1161                 }
1162                 bp->max_resp_len = max_resp_len;
1163         }
1164
1165         if ((dev_caps_cfg &
1166                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1167             (dev_caps_cfg &
1168              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1169                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1170                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1171         }
1172
1173         if (((dev_caps_cfg &
1174               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1175              (dev_caps_cfg &
1176               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1177             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1178                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1179                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1180                         bp->pdev->addr.devid, bp->pdev->addr.function);
1181
1182                 rte_free(bp->hwrm_short_cmd_req_addr);
1183
1184                 bp->hwrm_short_cmd_req_addr =
1185                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1186                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1187                         rc = -ENOMEM;
1188                         goto error;
1189                 }
1190                 bp->hwrm_short_cmd_req_dma_addr =
1191                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1192                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1193                         rte_free(bp->hwrm_short_cmd_req_addr);
1194                         PMD_DRV_LOG(ERR,
1195                                 "Unable to map buffer to physical memory.\n");
1196                         rc = -ENOMEM;
1197                         goto error;
1198                 }
1199         }
1200         if (dev_caps_cfg &
1201             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1202                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1203                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1204         }
1205         if (dev_caps_cfg &
1206             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1207                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1208         if (dev_caps_cfg &
1209             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1210                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1211                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1212         }
1213
1214         if (dev_caps_cfg &
1215             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1216                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1217                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1218         }
1219
1220
1221 error:
1222         HWRM_UNLOCK();
1223         return rc;
1224 }
1225
1226 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1227 {
1228         int rc;
1229         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1230         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1231
1232         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1233                 return 0;
1234
1235         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1236         req.flags = flags;
1237
1238         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1239
1240         HWRM_CHECK_RESULT();
1241         HWRM_UNLOCK();
1242
1243         return rc;
1244 }
1245
1246 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1247 {
1248         int rc = 0;
1249         struct hwrm_port_phy_cfg_input req = {0};
1250         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1251         uint32_t enables = 0;
1252
1253         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1254
1255         if (conf->link_up) {
1256                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1257                 if (bp->link_info->auto_mode && conf->link_speed) {
1258                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1259                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1260                 }
1261
1262                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1263                 /*
1264                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1265                  * any auto mode, even "none".
1266                  */
1267                 if (!conf->link_speed) {
1268                         /* No speeds specified. Enable AutoNeg - all speeds */
1269                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1270                         req.auto_mode =
1271                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1272                 } else {
1273                         if (bp->link_info->link_signal_mode) {
1274                                 enables |=
1275                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1276                                 req.force_pam4_link_speed =
1277                                         rte_cpu_to_le_16(conf->link_speed);
1278                         }
1279                         req.force_link_speed =
1280                                         rte_cpu_to_le_16(conf->link_speed);
1281                 }
1282                 /* AutoNeg - Advertise speeds specified. */
1283                 if (conf->auto_link_speed_mask &&
1284                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1285                         req.auto_mode =
1286                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1287                         req.auto_link_speed_mask =
1288                                 conf->auto_link_speed_mask;
1289                         if (conf->auto_pam4_link_speeds) {
1290                                 enables |=
1291                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1292                                 req.auto_link_pam4_speed_mask =
1293                                         conf->auto_pam4_link_speeds;
1294                         } else {
1295                                 enables |=
1296                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1297                         }
1298                 }
1299                 if (conf->auto_link_speed &&
1300                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1301                         enables |=
1302                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1303
1304                 req.auto_duplex = conf->duplex;
1305                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1306                 req.auto_pause = conf->auto_pause;
1307                 req.force_pause = conf->force_pause;
1308                 /* Set force_pause if there is no auto or if there is a force */
1309                 if (req.auto_pause && !req.force_pause)
1310                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1311                 else
1312                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1313
1314                 req.enables = rte_cpu_to_le_32(enables);
1315         } else {
1316                 req.flags =
1317                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1318                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1319         }
1320
1321         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1322
1323         HWRM_CHECK_RESULT();
1324         HWRM_UNLOCK();
1325
1326         return rc;
1327 }
1328
1329 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1330                                    struct bnxt_link_info *link_info)
1331 {
1332         int rc = 0;
1333         struct hwrm_port_phy_qcfg_input req = {0};
1334         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1335
1336         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1337
1338         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1339
1340         HWRM_CHECK_RESULT();
1341
1342         link_info->phy_link_status = resp->link;
1343         link_info->link_up =
1344                 (link_info->phy_link_status ==
1345                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1346         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1347         link_info->duplex = resp->duplex_cfg;
1348         link_info->pause = resp->pause;
1349         link_info->auto_pause = resp->auto_pause;
1350         link_info->force_pause = resp->force_pause;
1351         link_info->auto_mode = resp->auto_mode;
1352         link_info->phy_type = resp->phy_type;
1353         link_info->media_type = resp->media_type;
1354
1355         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1356         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1357         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1358         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1359         link_info->phy_ver[0] = resp->phy_maj;
1360         link_info->phy_ver[1] = resp->phy_min;
1361         link_info->phy_ver[2] = resp->phy_bld;
1362         link_info->link_signal_mode = rte_le_to_cpu_16(resp->link_signal_mode);
1363         link_info->force_pam4_link_speed =
1364                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1365         link_info->support_pam4_speeds =
1366                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1367         link_info->auto_pam4_link_speeds =
1368                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1369         HWRM_UNLOCK();
1370
1371         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1372                     link_info->link_speed, link_info->auto_mode,
1373                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1374                     link_info->support_speeds, link_info->force_link_speed);
1375         return rc;
1376 }
1377
1378 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1379 {
1380         int rc = 0;
1381         struct hwrm_port_phy_qcaps_input req = {0};
1382         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1383         struct bnxt_link_info *link_info = bp->link_info;
1384
1385         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1386                 return 0;
1387
1388         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1389
1390         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1391
1392         HWRM_CHECK_RESULT();
1393
1394         bp->port_cnt = resp->port_cnt;
1395         if (resp->supported_speeds_auto_mode)
1396                 link_info->support_auto_speeds =
1397                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1398         if (resp->supported_pam4_speeds_auto_mode)
1399                 link_info->support_pam4_auto_speeds =
1400                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1401
1402         HWRM_UNLOCK();
1403
1404         return 0;
1405 }
1406
1407 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1408 {
1409         int i = 0;
1410
1411         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1412                 if (bp->tx_cos_queue[i].profile ==
1413                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1414                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1415                         return true;
1416                 }
1417         }
1418         return false;
1419 }
1420
1421 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1422 {
1423         int i = 0;
1424
1425         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1426                 if (bp->tx_cos_queue[i].profile !=
1427                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1428                     bp->tx_cos_queue[i].id !=
1429                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1430                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1431                         break;
1432                 }
1433         }
1434 }
1435
1436 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1437 {
1438         int rc = 0;
1439         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1440         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1441         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1442         int i;
1443
1444 get_rx_info:
1445         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1446
1447         req.flags = rte_cpu_to_le_32(dir);
1448         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1449         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1450             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1451                 req.drv_qmap_cap =
1452                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1453         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1454
1455         HWRM_CHECK_RESULT();
1456
1457         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1458                 GET_TX_QUEUE_INFO(0);
1459                 GET_TX_QUEUE_INFO(1);
1460                 GET_TX_QUEUE_INFO(2);
1461                 GET_TX_QUEUE_INFO(3);
1462                 GET_TX_QUEUE_INFO(4);
1463                 GET_TX_QUEUE_INFO(5);
1464                 GET_TX_QUEUE_INFO(6);
1465                 GET_TX_QUEUE_INFO(7);
1466         } else  {
1467                 GET_RX_QUEUE_INFO(0);
1468                 GET_RX_QUEUE_INFO(1);
1469                 GET_RX_QUEUE_INFO(2);
1470                 GET_RX_QUEUE_INFO(3);
1471                 GET_RX_QUEUE_INFO(4);
1472                 GET_RX_QUEUE_INFO(5);
1473                 GET_RX_QUEUE_INFO(6);
1474                 GET_RX_QUEUE_INFO(7);
1475         }
1476
1477         HWRM_UNLOCK();
1478
1479         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1480                 goto done;
1481
1482         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1483                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1484         } else {
1485                 int j;
1486
1487                 /* iterate and find the COSq profile to use for Tx */
1488                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1489                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1490                                 if (bp->tx_cos_queue[i].id != 0xff)
1491                                         bp->tx_cosq_id[j++] =
1492                                                 bp->tx_cos_queue[i].id;
1493                         }
1494                 } else {
1495                         /* When CoS classification is disabled, for normal NIC
1496                          * operations, ideally we should look to use LOSSY.
1497                          * If not found, fallback to the first valid profile
1498                          */
1499                         if (!bnxt_find_lossy_profile(bp))
1500                                 bnxt_find_first_valid_profile(bp);
1501
1502                 }
1503         }
1504
1505         bp->max_tc = resp->max_configurable_queues;
1506         bp->max_lltc = resp->max_configurable_lossless_queues;
1507         if (bp->max_tc > BNXT_MAX_QUEUE)
1508                 bp->max_tc = BNXT_MAX_QUEUE;
1509         bp->max_q = bp->max_tc;
1510
1511         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1512                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1513                 goto get_rx_info;
1514         }
1515
1516 done:
1517         return rc;
1518 }
1519
1520 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1521                          struct bnxt_ring *ring,
1522                          uint32_t ring_type, uint32_t map_index,
1523                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1524                          uint16_t tx_cosq_id)
1525 {
1526         int rc = 0;
1527         uint32_t enables = 0;
1528         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1529         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1530         struct rte_mempool *mb_pool;
1531         uint16_t rx_buf_size;
1532
1533         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1534
1535         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1536         req.fbo = rte_cpu_to_le_32(0);
1537         /* Association of ring index with doorbell index */
1538         req.logical_id = rte_cpu_to_le_16(map_index);
1539         req.length = rte_cpu_to_le_32(ring->ring_size);
1540
1541         switch (ring_type) {
1542         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1543                 req.ring_type = ring_type;
1544                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1545                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1546                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1547                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1548                         enables |=
1549                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1550                 break;
1551         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1552                 req.ring_type = ring_type;
1553                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1554                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1555                 if (BNXT_CHIP_THOR(bp)) {
1556                         mb_pool = bp->rx_queues[0]->mb_pool;
1557                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1558                                       RTE_PKTMBUF_HEADROOM;
1559                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1560                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1561                         enables |=
1562                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1563                 }
1564                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1565                         enables |=
1566                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1567                 break;
1568         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1569                 req.ring_type = ring_type;
1570                 if (BNXT_HAS_NQ(bp)) {
1571                         /* Association of cp ring with nq */
1572                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1573                         enables |=
1574                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1575                 }
1576                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1577                 break;
1578         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1579                 req.ring_type = ring_type;
1580                 req.page_size = BNXT_PAGE_SHFT;
1581                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1582                 break;
1583         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1584                 req.ring_type = ring_type;
1585                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1586
1587                 mb_pool = bp->rx_queues[0]->mb_pool;
1588                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1589                               RTE_PKTMBUF_HEADROOM;
1590                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1591                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1592
1593                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1594                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1595                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1596                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1597                 break;
1598         default:
1599                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1600                         ring_type);
1601                 HWRM_UNLOCK();
1602                 return -EINVAL;
1603         }
1604         req.enables = rte_cpu_to_le_32(enables);
1605
1606         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1607
1608         if (rc || resp->error_code) {
1609                 if (rc == 0 && resp->error_code)
1610                         rc = rte_le_to_cpu_16(resp->error_code);
1611                 switch (ring_type) {
1612                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1613                         PMD_DRV_LOG(ERR,
1614                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1615                         HWRM_UNLOCK();
1616                         return rc;
1617                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1618                         PMD_DRV_LOG(ERR,
1619                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1620                         HWRM_UNLOCK();
1621                         return rc;
1622                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1623                         PMD_DRV_LOG(ERR,
1624                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1625                                     rc);
1626                         HWRM_UNLOCK();
1627                         return rc;
1628                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1629                         PMD_DRV_LOG(ERR,
1630                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1631                         HWRM_UNLOCK();
1632                         return rc;
1633                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1634                         PMD_DRV_LOG(ERR,
1635                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1636                         HWRM_UNLOCK();
1637                         return rc;
1638                 default:
1639                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1640                         HWRM_UNLOCK();
1641                         return rc;
1642                 }
1643         }
1644
1645         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1646         HWRM_UNLOCK();
1647         return rc;
1648 }
1649
1650 int bnxt_hwrm_ring_free(struct bnxt *bp,
1651                         struct bnxt_ring *ring, uint32_t ring_type)
1652 {
1653         int rc;
1654         struct hwrm_ring_free_input req = {.req_type = 0 };
1655         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1656
1657         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1658
1659         req.ring_type = ring_type;
1660         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1661
1662         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1663
1664         if (rc || resp->error_code) {
1665                 if (rc == 0 && resp->error_code)
1666                         rc = rte_le_to_cpu_16(resp->error_code);
1667                 HWRM_UNLOCK();
1668
1669                 switch (ring_type) {
1670                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1671                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1672                                 rc);
1673                         return rc;
1674                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1675                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1676                                 rc);
1677                         return rc;
1678                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1679                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1680                                 rc);
1681                         return rc;
1682                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1683                         PMD_DRV_LOG(ERR,
1684                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1685                         return rc;
1686                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1687                         PMD_DRV_LOG(ERR,
1688                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1689                         return rc;
1690                 default:
1691                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1692                         return rc;
1693                 }
1694         }
1695         HWRM_UNLOCK();
1696         return 0;
1697 }
1698
1699 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1700 {
1701         int rc = 0;
1702         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1703         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1704
1705         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1706
1707         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1708         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1709         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1710         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1711
1712         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1713
1714         HWRM_CHECK_RESULT();
1715
1716         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1717
1718         HWRM_UNLOCK();
1719
1720         return rc;
1721 }
1722
1723 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1724 {
1725         int rc;
1726         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1727         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1728
1729         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1730
1731         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1732
1733         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1734
1735         HWRM_CHECK_RESULT();
1736         HWRM_UNLOCK();
1737
1738         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1739         return rc;
1740 }
1741
1742 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1743 {
1744         int rc = 0;
1745         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1746         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1747
1748         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1749                 return rc;
1750
1751         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1752
1753         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1754
1755         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1756
1757         HWRM_CHECK_RESULT();
1758         HWRM_UNLOCK();
1759
1760         return rc;
1761 }
1762
1763 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1764                                 unsigned int idx __rte_unused)
1765 {
1766         int rc;
1767         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1768         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1769
1770         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1771
1772         req.update_period_ms = rte_cpu_to_le_32(0);
1773
1774         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1775
1776         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1777
1778         HWRM_CHECK_RESULT();
1779
1780         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1781
1782         HWRM_UNLOCK();
1783
1784         return rc;
1785 }
1786
1787 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1788                                 unsigned int idx __rte_unused)
1789 {
1790         int rc;
1791         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1792         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1793
1794         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1795
1796         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1797
1798         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1799
1800         HWRM_CHECK_RESULT();
1801         HWRM_UNLOCK();
1802
1803         return rc;
1804 }
1805
1806 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1807 {
1808         int rc = 0, i, j;
1809         struct hwrm_vnic_alloc_input req = { 0 };
1810         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1811
1812         if (!BNXT_HAS_RING_GRPS(bp))
1813                 goto skip_ring_grps;
1814
1815         /* map ring groups to this vnic */
1816         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1817                 vnic->start_grp_id, vnic->end_grp_id);
1818         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1819                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1820
1821         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1822         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1823         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1824         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1825
1826 skip_ring_grps:
1827         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1828         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1829
1830         if (vnic->func_default)
1831                 req.flags =
1832                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1833         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1834
1835         HWRM_CHECK_RESULT();
1836
1837         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1838         HWRM_UNLOCK();
1839         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1840         return rc;
1841 }
1842
1843 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1844                                         struct bnxt_vnic_info *vnic,
1845                                         struct bnxt_plcmodes_cfg *pmode)
1846 {
1847         int rc = 0;
1848         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1849         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1850
1851         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1852
1853         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1854
1855         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1856
1857         HWRM_CHECK_RESULT();
1858
1859         pmode->flags = rte_le_to_cpu_32(resp->flags);
1860         /* dflt_vnic bit doesn't exist in the _cfg command */
1861         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1862         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1863         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1864         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1865
1866         HWRM_UNLOCK();
1867
1868         return rc;
1869 }
1870
1871 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1872                                        struct bnxt_vnic_info *vnic,
1873                                        struct bnxt_plcmodes_cfg *pmode)
1874 {
1875         int rc = 0;
1876         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1877         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1878
1879         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1880                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1881                 return rc;
1882         }
1883
1884         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1885
1886         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1887         req.flags = rte_cpu_to_le_32(pmode->flags);
1888         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1889         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1890         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1891         req.enables = rte_cpu_to_le_32(
1892             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1893             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1894             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1895         );
1896
1897         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1898
1899         HWRM_CHECK_RESULT();
1900         HWRM_UNLOCK();
1901
1902         return rc;
1903 }
1904
1905 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1906 {
1907         int rc = 0;
1908         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1909         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1910         struct bnxt_plcmodes_cfg pmodes = { 0 };
1911         uint32_t ctx_enable_flag = 0;
1912         uint32_t enables = 0;
1913
1914         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1915                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1916                 return rc;
1917         }
1918
1919         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1920         if (rc)
1921                 return rc;
1922
1923         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1924
1925         if (BNXT_CHIP_THOR(bp)) {
1926                 int dflt_rxq = vnic->start_grp_id;
1927                 struct bnxt_rx_ring_info *rxr;
1928                 struct bnxt_cp_ring_info *cpr;
1929                 struct bnxt_rx_queue *rxq;
1930                 int i;
1931
1932                 /*
1933                  * The first active receive ring is used as the VNIC
1934                  * default receive ring. If there are no active receive
1935                  * rings (all corresponding receive queues are stopped),
1936                  * the first receive ring is used.
1937                  */
1938                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1939                         rxq = bp->eth_dev->data->rx_queues[i];
1940                         if (rxq->rx_started) {
1941                                 dflt_rxq = i;
1942                                 break;
1943                         }
1944                 }
1945
1946                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1947                 rxr = rxq->rx_ring;
1948                 cpr = rxq->cp_ring;
1949
1950                 req.default_rx_ring_id =
1951                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1952                 req.default_cmpl_ring_id =
1953                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1954                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1955                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1956                 goto config_mru;
1957         }
1958
1959         /* Only RSS support for now TBD: COS & LB */
1960         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1961         if (vnic->lb_rule != 0xffff)
1962                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1963         if (vnic->cos_rule != 0xffff)
1964                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1965         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1966                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1967                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1968         }
1969         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1970                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1971                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1972         }
1973
1974         enables |= ctx_enable_flag;
1975         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1976         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1977         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1978         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1979
1980 config_mru:
1981         req.enables = rte_cpu_to_le_32(enables);
1982         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1983         req.mru = rte_cpu_to_le_16(vnic->mru);
1984         /* Configure default VNIC only once. */
1985         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1986                 req.flags |=
1987                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1988                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1989         }
1990         if (vnic->vlan_strip)
1991                 req.flags |=
1992                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1993         if (vnic->bd_stall)
1994                 req.flags |=
1995                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1996         if (vnic->roce_dual)
1997                 req.flags |= rte_cpu_to_le_32(
1998                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1999         if (vnic->roce_only)
2000                 req.flags |= rte_cpu_to_le_32(
2001                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
2002         if (vnic->rss_dflt_cr)
2003                 req.flags |= rte_cpu_to_le_32(
2004                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2005
2006         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2007
2008         HWRM_CHECK_RESULT();
2009         HWRM_UNLOCK();
2010
2011         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2012
2013         return rc;
2014 }
2015
2016 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2017                 int16_t fw_vf_id)
2018 {
2019         int rc = 0;
2020         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2021         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2022
2023         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2024                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2025                 return rc;
2026         }
2027         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2028
2029         req.enables =
2030                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2031         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2032         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2033
2034         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2035
2036         HWRM_CHECK_RESULT();
2037
2038         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2039         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2040         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2041         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2042         vnic->mru = rte_le_to_cpu_16(resp->mru);
2043         vnic->func_default = rte_le_to_cpu_32(
2044                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2045         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2046                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2047         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2048                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2049         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
2050                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
2051         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
2052                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
2053         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2054                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2055
2056         HWRM_UNLOCK();
2057
2058         return rc;
2059 }
2060
2061 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2062                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2063 {
2064         int rc = 0;
2065         uint16_t ctx_id;
2066         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2067         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2068                                                 bp->hwrm_cmd_resp_addr;
2069
2070         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2071
2072         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2073         HWRM_CHECK_RESULT();
2074
2075         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2076         if (!BNXT_HAS_RING_GRPS(bp))
2077                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2078         else if (ctx_idx == 0)
2079                 vnic->rss_rule = ctx_id;
2080
2081         HWRM_UNLOCK();
2082
2083         return rc;
2084 }
2085
2086 static
2087 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2088                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2089 {
2090         int rc = 0;
2091         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2092         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2093                                                 bp->hwrm_cmd_resp_addr;
2094
2095         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2096                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2097                 return rc;
2098         }
2099         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2100
2101         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2102
2103         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2104
2105         HWRM_CHECK_RESULT();
2106         HWRM_UNLOCK();
2107
2108         return rc;
2109 }
2110
2111 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2112 {
2113         int rc = 0;
2114
2115         if (BNXT_CHIP_THOR(bp)) {
2116                 int j;
2117
2118                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2119                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2120                                                       vnic,
2121                                                       vnic->fw_grp_ids[j]);
2122                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2123                 }
2124                 vnic->num_lb_ctxts = 0;
2125         } else {
2126                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2127                 vnic->rss_rule = INVALID_HW_RING_ID;
2128         }
2129
2130         return rc;
2131 }
2132
2133 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2134 {
2135         int rc = 0;
2136         struct hwrm_vnic_free_input req = {.req_type = 0 };
2137         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2138
2139         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2140                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2141                 return rc;
2142         }
2143
2144         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2145
2146         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2147
2148         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2149
2150         HWRM_CHECK_RESULT();
2151         HWRM_UNLOCK();
2152
2153         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2154         /* Configure default VNIC again if necessary. */
2155         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2156                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2157
2158         return rc;
2159 }
2160
2161 static int
2162 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2163 {
2164         int i;
2165         int rc = 0;
2166         int nr_ctxs = vnic->num_lb_ctxts;
2167         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2168         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2169
2170         for (i = 0; i < nr_ctxs; i++) {
2171                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2172
2173                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2174                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2175                 req.hash_mode_flags = vnic->hash_mode;
2176
2177                 req.hash_key_tbl_addr =
2178                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2179
2180                 req.ring_grp_tbl_addr =
2181                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2182                                          i * HW_HASH_INDEX_SIZE);
2183                 req.ring_table_pair_index = i;
2184                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2185
2186                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2187                                             BNXT_USE_CHIMP_MB);
2188
2189                 HWRM_CHECK_RESULT();
2190                 HWRM_UNLOCK();
2191         }
2192
2193         return rc;
2194 }
2195
2196 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2197                            struct bnxt_vnic_info *vnic)
2198 {
2199         int rc = 0;
2200         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2201         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2202
2203         if (!vnic->rss_table)
2204                 return 0;
2205
2206         if (BNXT_CHIP_THOR(bp))
2207                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2208
2209         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2210
2211         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2212         req.hash_mode_flags = vnic->hash_mode;
2213
2214         req.ring_grp_tbl_addr =
2215             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2216         req.hash_key_tbl_addr =
2217             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2218         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2219         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2220
2221         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2222
2223         HWRM_CHECK_RESULT();
2224         HWRM_UNLOCK();
2225
2226         return rc;
2227 }
2228
2229 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2230                         struct bnxt_vnic_info *vnic)
2231 {
2232         int rc = 0;
2233         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2234         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2235         uint16_t size;
2236
2237         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2238                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2239                 return rc;
2240         }
2241
2242         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2243
2244         req.flags = rte_cpu_to_le_32(
2245                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2246
2247         req.enables = rte_cpu_to_le_32(
2248                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2249
2250         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2251         size -= RTE_PKTMBUF_HEADROOM;
2252         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2253
2254         req.jumbo_thresh = rte_cpu_to_le_16(size);
2255         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2256
2257         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2258
2259         HWRM_CHECK_RESULT();
2260         HWRM_UNLOCK();
2261
2262         return rc;
2263 }
2264
2265 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2266                         struct bnxt_vnic_info *vnic, bool enable)
2267 {
2268         int rc = 0;
2269         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2270         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2271
2272         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2273                 if (enable)
2274                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2275                 return -ENOTSUP;
2276         }
2277
2278         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2279                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2280                 return 0;
2281         }
2282
2283         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2284
2285         if (enable) {
2286                 req.enables = rte_cpu_to_le_32(
2287                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2288                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2289                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2290                 req.flags = rte_cpu_to_le_32(
2291                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2292                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2293                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2294                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2295                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2296                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2297                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2298                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2299                 req.min_agg_len = rte_cpu_to_le_32(512);
2300         }
2301         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2302
2303         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2304
2305         HWRM_CHECK_RESULT();
2306         HWRM_UNLOCK();
2307
2308         return rc;
2309 }
2310
2311 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2312 {
2313         struct hwrm_func_cfg_input req = {0};
2314         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2315         int rc;
2316
2317         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2318         req.enables = rte_cpu_to_le_32(
2319                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2320         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2321         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2322
2323         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2324
2325         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2326         HWRM_CHECK_RESULT();
2327         HWRM_UNLOCK();
2328
2329         bp->pf->vf_info[vf].random_mac = false;
2330
2331         return rc;
2332 }
2333
2334 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2335                                   uint64_t *dropped)
2336 {
2337         int rc = 0;
2338         struct hwrm_func_qstats_input req = {.req_type = 0};
2339         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2340
2341         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2342
2343         req.fid = rte_cpu_to_le_16(fid);
2344
2345         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2346
2347         HWRM_CHECK_RESULT();
2348
2349         if (dropped)
2350                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2351
2352         HWRM_UNLOCK();
2353
2354         return rc;
2355 }
2356
2357 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2358                           struct rte_eth_stats *stats,
2359                           struct hwrm_func_qstats_output *func_qstats)
2360 {
2361         int rc = 0;
2362         struct hwrm_func_qstats_input req = {.req_type = 0};
2363         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2364
2365         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2366
2367         req.fid = rte_cpu_to_le_16(fid);
2368
2369         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2370
2371         HWRM_CHECK_RESULT();
2372         if (func_qstats)
2373                 memcpy(func_qstats, resp,
2374                        sizeof(struct hwrm_func_qstats_output));
2375
2376         if (!stats)
2377                 goto exit;
2378
2379         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2380         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2381         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2382         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2383         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2384         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2385
2386         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2387         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2388         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2389         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2390         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2391         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2392
2393         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2394         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2395         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2396
2397 exit:
2398         HWRM_UNLOCK();
2399
2400         return rc;
2401 }
2402
2403 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2404 {
2405         int rc = 0;
2406         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2407         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2408
2409         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2410
2411         req.fid = rte_cpu_to_le_16(fid);
2412
2413         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2414
2415         HWRM_CHECK_RESULT();
2416         HWRM_UNLOCK();
2417
2418         return rc;
2419 }
2420
2421 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2422 {
2423         unsigned int i;
2424         int rc = 0;
2425
2426         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2427                 struct bnxt_tx_queue *txq;
2428                 struct bnxt_rx_queue *rxq;
2429                 struct bnxt_cp_ring_info *cpr;
2430
2431                 if (i >= bp->rx_cp_nr_rings) {
2432                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2433                         cpr = txq->cp_ring;
2434                 } else {
2435                         rxq = bp->rx_queues[i];
2436                         cpr = rxq->cp_ring;
2437                 }
2438
2439                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2440                 if (rc)
2441                         return rc;
2442         }
2443         return 0;
2444 }
2445
2446 static int
2447 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2448 {
2449         int rc;
2450         unsigned int i;
2451         struct bnxt_cp_ring_info *cpr;
2452
2453         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2454
2455                 if (i >= bp->rx_cp_nr_rings) {
2456                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2457                 } else {
2458                         cpr = bp->rx_queues[i]->cp_ring;
2459                         if (BNXT_HAS_RING_GRPS(bp))
2460                                 bp->grp_info[i].fw_stats_ctx = -1;
2461                 }
2462                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2463                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2464                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2465                         if (rc)
2466                                 return rc;
2467                 }
2468         }
2469         return 0;
2470 }
2471
2472 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2473 {
2474         unsigned int i;
2475         int rc = 0;
2476
2477         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2478                 struct bnxt_tx_queue *txq;
2479                 struct bnxt_rx_queue *rxq;
2480                 struct bnxt_cp_ring_info *cpr;
2481
2482                 if (i >= bp->rx_cp_nr_rings) {
2483                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2484                         cpr = txq->cp_ring;
2485                 } else {
2486                         rxq = bp->rx_queues[i];
2487                         cpr = rxq->cp_ring;
2488                 }
2489
2490                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2491
2492                 if (rc)
2493                         return rc;
2494         }
2495         return rc;
2496 }
2497
2498 static int
2499 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2500 {
2501         uint16_t idx;
2502         uint32_t rc = 0;
2503
2504         if (!BNXT_HAS_RING_GRPS(bp))
2505                 return 0;
2506
2507         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2508
2509                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2510                         continue;
2511
2512                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2513
2514                 if (rc)
2515                         return rc;
2516         }
2517         return rc;
2518 }
2519
2520 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2521 {
2522         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2523
2524         bnxt_hwrm_ring_free(bp, cp_ring,
2525                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2526         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2527         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2528                                      sizeof(*cpr->cp_desc_ring));
2529         cpr->cp_raw_cons = 0;
2530         cpr->valid = 0;
2531 }
2532
2533 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2534 {
2535         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2536
2537         bnxt_hwrm_ring_free(bp, cp_ring,
2538                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2539         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2540         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2541                         sizeof(*cpr->cp_desc_ring));
2542         cpr->cp_raw_cons = 0;
2543         cpr->valid = 0;
2544 }
2545
2546 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2547 {
2548         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2549         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2550         struct bnxt_ring *ring = rxr->rx_ring_struct;
2551         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2552
2553         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2554                 bnxt_hwrm_ring_free(bp, ring,
2555                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2556                 ring->fw_ring_id = INVALID_HW_RING_ID;
2557                 if (BNXT_HAS_RING_GRPS(bp))
2558                         bp->grp_info[queue_index].rx_fw_ring_id =
2559                                                         INVALID_HW_RING_ID;
2560         }
2561         ring = rxr->ag_ring_struct;
2562         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2563                 bnxt_hwrm_ring_free(bp, ring,
2564                                     BNXT_CHIP_THOR(bp) ?
2565                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2566                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2567                 if (BNXT_HAS_RING_GRPS(bp))
2568                         bp->grp_info[queue_index].ag_fw_ring_id =
2569                                                         INVALID_HW_RING_ID;
2570         }
2571         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2572                 bnxt_free_cp_ring(bp, cpr);
2573
2574         if (BNXT_HAS_RING_GRPS(bp))
2575                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2576 }
2577
2578 static int
2579 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2580 {
2581         unsigned int i;
2582
2583         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2584                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2585                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2586                 struct bnxt_ring *ring = txr->tx_ring_struct;
2587                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2588
2589                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2590                         bnxt_hwrm_ring_free(bp, ring,
2591                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2592                         ring->fw_ring_id = INVALID_HW_RING_ID;
2593                         memset(txr->tx_desc_ring, 0,
2594                                         txr->tx_ring_struct->ring_size *
2595                                         sizeof(*txr->tx_desc_ring));
2596                         memset(txr->tx_buf_ring, 0,
2597                                         txr->tx_ring_struct->ring_size *
2598                                         sizeof(*txr->tx_buf_ring));
2599                         txr->tx_prod = 0;
2600                         txr->tx_cons = 0;
2601                 }
2602                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2603                         bnxt_free_cp_ring(bp, cpr);
2604                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2605                 }
2606         }
2607
2608         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2609                 bnxt_free_hwrm_rx_ring(bp, i);
2610
2611         return 0;
2612 }
2613
2614 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2615 {
2616         uint16_t i;
2617         uint32_t rc = 0;
2618
2619         if (!BNXT_HAS_RING_GRPS(bp))
2620                 return 0;
2621
2622         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2623                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2624                 if (rc)
2625                         return rc;
2626         }
2627         return rc;
2628 }
2629
2630 /*
2631  * HWRM utility functions
2632  */
2633
2634 void bnxt_free_hwrm_resources(struct bnxt *bp)
2635 {
2636         /* Release memzone */
2637         rte_free(bp->hwrm_cmd_resp_addr);
2638         rte_free(bp->hwrm_short_cmd_req_addr);
2639         bp->hwrm_cmd_resp_addr = NULL;
2640         bp->hwrm_short_cmd_req_addr = NULL;
2641         bp->hwrm_cmd_resp_dma_addr = 0;
2642         bp->hwrm_short_cmd_req_dma_addr = 0;
2643 }
2644
2645 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2646 {
2647         struct rte_pci_device *pdev = bp->pdev;
2648         char type[RTE_MEMZONE_NAMESIZE];
2649
2650         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2651                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2652         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2653         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2654         if (bp->hwrm_cmd_resp_addr == NULL)
2655                 return -ENOMEM;
2656         bp->hwrm_cmd_resp_dma_addr =
2657                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2658         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2659                 PMD_DRV_LOG(ERR,
2660                         "unable to map response address to physical memory\n");
2661                 return -ENOMEM;
2662         }
2663         rte_spinlock_init(&bp->hwrm_lock);
2664
2665         return 0;
2666 }
2667
2668 int
2669 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2670 {
2671         int rc = 0;
2672
2673         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2674                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2675                 if (rc)
2676                         return rc;
2677         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2678                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2679                 if (rc)
2680                         return rc;
2681         }
2682
2683         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2684         return rc;
2685 }
2686
2687 static int
2688 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2689 {
2690         struct bnxt_filter_info *filter;
2691         int rc = 0;
2692
2693         STAILQ_FOREACH(filter, &vnic->filter, next) {
2694                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2695                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2696                 bnxt_free_filter(bp, filter);
2697         }
2698         return rc;
2699 }
2700
2701 static int
2702 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2703 {
2704         struct bnxt_filter_info *filter;
2705         struct rte_flow *flow;
2706         int rc = 0;
2707
2708         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2709                 flow = STAILQ_FIRST(&vnic->flow_list);
2710                 filter = flow->filter;
2711                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2712                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2713
2714                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2715                 rte_free(flow);
2716         }
2717         return rc;
2718 }
2719
2720 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2721 {
2722         struct bnxt_filter_info *filter;
2723         int rc = 0;
2724
2725         STAILQ_FOREACH(filter, &vnic->filter, next) {
2726                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2727                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2728                                                      filter);
2729                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2730                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2731                                                          filter);
2732                 else
2733                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2734                                                      filter);
2735                 if (rc)
2736                         break;
2737         }
2738         return rc;
2739 }
2740
2741 static void
2742 bnxt_free_tunnel_ports(struct bnxt *bp)
2743 {
2744         if (bp->vxlan_port_cnt)
2745                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2746                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2747         bp->vxlan_port = 0;
2748         if (bp->geneve_port_cnt)
2749                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2750                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2751         bp->geneve_port = 0;
2752 }
2753
2754 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2755 {
2756         int i;
2757
2758         if (bp->vnic_info == NULL)
2759                 return;
2760
2761         /*
2762          * Cleanup VNICs in reverse order, to make sure the L2 filter
2763          * from vnic0 is last to be cleaned up.
2764          */
2765         for (i = bp->max_vnics - 1; i >= 0; i--) {
2766                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2767
2768                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2769                         continue;
2770
2771                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2772
2773                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2774
2775                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2776
2777                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2778
2779                 bnxt_hwrm_vnic_free(bp, vnic);
2780
2781                 rte_free(vnic->fw_grp_ids);
2782         }
2783         /* Ring resources */
2784         bnxt_free_all_hwrm_rings(bp);
2785         bnxt_free_all_hwrm_ring_grps(bp);
2786         bnxt_free_all_hwrm_stat_ctxs(bp);
2787         bnxt_free_tunnel_ports(bp);
2788 }
2789
2790 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2791 {
2792         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2793
2794         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2795                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2796
2797         switch (conf_link_speed) {
2798         case ETH_LINK_SPEED_10M_HD:
2799         case ETH_LINK_SPEED_100M_HD:
2800                 /* FALLTHROUGH */
2801                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2802         }
2803         return hw_link_duplex;
2804 }
2805
2806 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2807 {
2808         return !conf_link;
2809 }
2810
2811 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2812                                           uint16_t pam4_link)
2813 {
2814         uint16_t eth_link_speed = 0;
2815
2816         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2817                 return ETH_LINK_SPEED_AUTONEG;
2818
2819         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2820         case ETH_LINK_SPEED_100M:
2821         case ETH_LINK_SPEED_100M_HD:
2822                 /* FALLTHROUGH */
2823                 eth_link_speed =
2824                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2825                 break;
2826         case ETH_LINK_SPEED_1G:
2827                 eth_link_speed =
2828                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2829                 break;
2830         case ETH_LINK_SPEED_2_5G:
2831                 eth_link_speed =
2832                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2833                 break;
2834         case ETH_LINK_SPEED_10G:
2835                 eth_link_speed =
2836                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2837                 break;
2838         case ETH_LINK_SPEED_20G:
2839                 eth_link_speed =
2840                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2841                 break;
2842         case ETH_LINK_SPEED_25G:
2843                 eth_link_speed =
2844                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2845                 break;
2846         case ETH_LINK_SPEED_40G:
2847                 eth_link_speed =
2848                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2849                 break;
2850         case ETH_LINK_SPEED_50G:
2851                 eth_link_speed = pam4_link ?
2852                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
2853                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2854                 break;
2855         case ETH_LINK_SPEED_100G:
2856                 eth_link_speed = pam4_link ?
2857                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
2858                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2859                 break;
2860         case ETH_LINK_SPEED_200G:
2861                 eth_link_speed =
2862                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2863                 break;
2864         default:
2865                 PMD_DRV_LOG(ERR,
2866                         "Unsupported link speed %d; default to AUTO\n",
2867                         conf_link_speed);
2868                 break;
2869         }
2870         return eth_link_speed;
2871 }
2872
2873 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2874                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2875                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2876                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2877                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2878
2879 static int bnxt_validate_link_speed(struct bnxt *bp)
2880 {
2881         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2882         uint16_t port_id = bp->eth_dev->data->port_id;
2883         uint32_t link_speed_capa;
2884         uint32_t one_speed;
2885
2886         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2887                 return 0;
2888
2889         link_speed_capa = bnxt_get_speed_capabilities(bp);
2890
2891         if (link_speed & ETH_LINK_SPEED_FIXED) {
2892                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2893
2894                 if (one_speed & (one_speed - 1)) {
2895                         PMD_DRV_LOG(ERR,
2896                                 "Invalid advertised speeds (%u) for port %u\n",
2897                                 link_speed, port_id);
2898                         return -EINVAL;
2899                 }
2900                 if ((one_speed & link_speed_capa) != one_speed) {
2901                         PMD_DRV_LOG(ERR,
2902                                 "Unsupported advertised speed (%u) for port %u\n",
2903                                 link_speed, port_id);
2904                         return -EINVAL;
2905                 }
2906         } else {
2907                 if (!(link_speed & link_speed_capa)) {
2908                         PMD_DRV_LOG(ERR,
2909                                 "Unsupported advertised speeds (%u) for port %u\n",
2910                                 link_speed, port_id);
2911                         return -EINVAL;
2912                 }
2913         }
2914         return 0;
2915 }
2916
2917 static uint16_t
2918 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2919 {
2920         uint16_t ret = 0;
2921
2922         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2923                 if (bp->link_info->support_speeds)
2924                         return bp->link_info->support_speeds;
2925                 link_speed = BNXT_SUPPORTED_SPEEDS;
2926         }
2927
2928         if (link_speed & ETH_LINK_SPEED_100M)
2929                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2930         if (link_speed & ETH_LINK_SPEED_100M_HD)
2931                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2932         if (link_speed & ETH_LINK_SPEED_1G)
2933                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2934         if (link_speed & ETH_LINK_SPEED_2_5G)
2935                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2936         if (link_speed & ETH_LINK_SPEED_10G)
2937                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2938         if (link_speed & ETH_LINK_SPEED_20G)
2939                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2940         if (link_speed & ETH_LINK_SPEED_25G)
2941                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2942         if (link_speed & ETH_LINK_SPEED_40G)
2943                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2944         if (link_speed & ETH_LINK_SPEED_50G)
2945                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2946         if (link_speed & ETH_LINK_SPEED_100G)
2947                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2948         if (link_speed & ETH_LINK_SPEED_200G)
2949                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2950         return ret;
2951 }
2952
2953 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2954 {
2955         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2956
2957         switch (hw_link_speed) {
2958         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2959                 eth_link_speed = ETH_SPEED_NUM_100M;
2960                 break;
2961         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2962                 eth_link_speed = ETH_SPEED_NUM_1G;
2963                 break;
2964         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2965                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2966                 break;
2967         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2968                 eth_link_speed = ETH_SPEED_NUM_10G;
2969                 break;
2970         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2971                 eth_link_speed = ETH_SPEED_NUM_20G;
2972                 break;
2973         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2974                 eth_link_speed = ETH_SPEED_NUM_25G;
2975                 break;
2976         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2977                 eth_link_speed = ETH_SPEED_NUM_40G;
2978                 break;
2979         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2980                 eth_link_speed = ETH_SPEED_NUM_50G;
2981                 break;
2982         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2983                 eth_link_speed = ETH_SPEED_NUM_100G;
2984                 break;
2985         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
2986                 eth_link_speed = ETH_SPEED_NUM_200G;
2987                 break;
2988         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2989         default:
2990                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2991                         hw_link_speed);
2992                 break;
2993         }
2994         return eth_link_speed;
2995 }
2996
2997 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2998 {
2999         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3000
3001         switch (hw_link_duplex) {
3002         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3003         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3004                 /* FALLTHROUGH */
3005                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3006                 break;
3007         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3008                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3009                 break;
3010         default:
3011                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3012                         hw_link_duplex);
3013                 break;
3014         }
3015         return eth_link_duplex;
3016 }
3017
3018 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3019 {
3020         int rc = 0;
3021         struct bnxt_link_info *link_info = bp->link_info;
3022
3023         rc = bnxt_hwrm_port_phy_qcaps(bp);
3024         if (rc)
3025                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3026
3027         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3028         if (rc) {
3029                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3030                 goto exit;
3031         }
3032
3033         if (link_info->link_speed)
3034                 link->link_speed =
3035                         bnxt_parse_hw_link_speed(link_info->link_speed);
3036         else
3037                 link->link_speed = ETH_SPEED_NUM_NONE;
3038         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3039         link->link_status = link_info->link_up;
3040         link->link_autoneg = link_info->auto_mode ==
3041                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3042                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3043 exit:
3044         return rc;
3045 }
3046
3047 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3048 {
3049         int rc = 0;
3050         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3051         struct bnxt_link_info link_req;
3052         uint16_t speed, autoneg;
3053
3054         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3055                 return 0;
3056
3057         rc = bnxt_validate_link_speed(bp);
3058         if (rc)
3059                 goto error;
3060
3061         memset(&link_req, 0, sizeof(link_req));
3062         link_req.link_up = link_up;
3063         if (!link_up)
3064                 goto port_phy_cfg;
3065
3066         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3067         if (BNXT_CHIP_THOR(bp) &&
3068             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3069                 /* 40G is not supported as part of media auto detect.
3070                  * The speed should be forced and autoneg disabled
3071                  * to configure 40G speed.
3072                  */
3073                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3074                 autoneg = 0;
3075         }
3076
3077         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3078                                           bp->link_info->link_signal_mode);
3079         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3080         /* Autoneg can be done only when the FW allows.
3081          * When user configures fixed speed of 40G and later changes to
3082          * any other speed, auto_link_speed/force_link_speed is still set
3083          * to 40G until link comes up at new speed.
3084          */
3085         if (autoneg == 1 &&
3086             !(!BNXT_CHIP_THOR(bp) &&
3087               (bp->link_info->auto_link_speed ||
3088                bp->link_info->force_link_speed))) {
3089                 link_req.phy_flags |=
3090                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3091                 link_req.auto_link_speed_mask =
3092                         bnxt_parse_eth_link_speed_mask(bp,
3093                                                        dev_conf->link_speeds);
3094         } else {
3095                 if (bp->link_info->phy_type ==
3096                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3097                     bp->link_info->phy_type ==
3098                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3099                     bp->link_info->media_type ==
3100                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3101                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3102                         return -EINVAL;
3103                 }
3104
3105                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3106                 /* If user wants a particular speed try that first. */
3107                 if (speed)
3108                         link_req.link_speed = speed;
3109                 else if (bp->link_info->force_pam4_link_speed)
3110                         link_req.link_speed =
3111                                 bp->link_info->force_pam4_link_speed;
3112                 else if (bp->link_info->auto_pam4_link_speeds)
3113                         link_req.link_speed =
3114                                 bp->link_info->auto_pam4_link_speeds;
3115                 else if (bp->link_info->support_pam4_speeds)
3116                         link_req.link_speed =
3117                                 bp->link_info->support_pam4_speeds;
3118                 else if (bp->link_info->force_link_speed)
3119                         link_req.link_speed = bp->link_info->force_link_speed;
3120                 else
3121                         link_req.link_speed = bp->link_info->auto_link_speed;
3122         }
3123         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3124         link_req.auto_pause = bp->link_info->auto_pause;
3125         link_req.force_pause = bp->link_info->force_pause;
3126
3127 port_phy_cfg:
3128         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3129         if (rc) {
3130                 PMD_DRV_LOG(ERR,
3131                         "Set link config failed with rc %d\n", rc);
3132         }
3133
3134 error:
3135         return rc;
3136 }
3137
3138 /* JIRA 22088 */
3139 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3140 {
3141         struct hwrm_func_qcfg_input req = {0};
3142         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3143         uint16_t flags;
3144         int rc = 0;
3145         bp->func_svif = BNXT_SVIF_INVALID;
3146         uint16_t svif_info;
3147
3148         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3149         req.fid = rte_cpu_to_le_16(0xffff);
3150
3151         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3152
3153         HWRM_CHECK_RESULT();
3154
3155         /* Hard Coded.. 0xfff VLAN ID mask */
3156         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3157
3158         svif_info = rte_le_to_cpu_16(resp->svif_info);
3159         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3160                 bp->func_svif = svif_info &
3161                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3162
3163         flags = rte_le_to_cpu_16(resp->flags);
3164         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3165                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3166
3167         if (BNXT_VF(bp) &&
3168             !BNXT_VF_IS_TRUSTED(bp) &&
3169             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3170                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3171                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3172         } else if (BNXT_VF(bp) &&
3173                    BNXT_VF_IS_TRUSTED(bp) &&
3174                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3175                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3176                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3177         }
3178
3179         if (mtu)
3180                 *mtu = rte_le_to_cpu_16(resp->mtu);
3181
3182         switch (resp->port_partition_type) {
3183         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3184         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3185         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3186                 /* FALLTHROUGH */
3187                 bp->flags |= BNXT_FLAG_NPAR_PF;
3188                 break;
3189         default:
3190                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3191                 break;
3192         }
3193
3194         HWRM_UNLOCK();
3195
3196         return rc;
3197 }
3198
3199 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3200 {
3201         struct hwrm_func_qcfg_input req = {0};
3202         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3203         int rc;
3204
3205         if (!BNXT_VF_IS_TRUSTED(bp))
3206                 return 0;
3207
3208         if (!bp->parent)
3209                 return -EINVAL;
3210
3211         bp->parent->fid = BNXT_PF_FID_INVALID;
3212
3213         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3214
3215         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3216
3217         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3218
3219         HWRM_CHECK_RESULT();
3220
3221         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3222         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3223         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3224         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3225
3226         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3227         if (bp->parent->vnic == 0) {
3228                 PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
3229                 /* Use hard-coded values appropriate for current Wh+ fw. */
3230                 if (bp->parent->fid == 2)
3231                         bp->parent->vnic = 0x100;
3232                 else
3233                         bp->parent->vnic = 1;
3234         }
3235
3236         HWRM_UNLOCK();
3237
3238         return 0;
3239 }
3240
3241 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3242                                  uint16_t *vnic_id, uint16_t *svif)
3243 {
3244         struct hwrm_func_qcfg_input req = {0};
3245         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3246         uint16_t svif_info;
3247         int rc = 0;
3248
3249         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3250         req.fid = rte_cpu_to_le_16(fid);
3251
3252         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3253
3254         HWRM_CHECK_RESULT();
3255
3256         if (vnic_id)
3257                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3258
3259         svif_info = rte_le_to_cpu_16(resp->svif_info);
3260         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3261                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3262
3263         HWRM_UNLOCK();
3264
3265         return rc;
3266 }
3267
3268 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3269 {
3270         struct hwrm_port_mac_qcfg_input req = {0};
3271         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3272         uint16_t port_svif_info;
3273         int rc;
3274
3275         bp->port_svif = BNXT_SVIF_INVALID;
3276
3277         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3278                 return 0;
3279
3280         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3281
3282         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3283
3284         HWRM_CHECK_RESULT_SILENT();
3285
3286         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3287         if (port_svif_info &
3288             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3289                 bp->port_svif = port_svif_info &
3290                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3291
3292         HWRM_UNLOCK();
3293
3294         return 0;
3295 }
3296
3297 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3298                                    struct hwrm_func_qcaps_output *qcaps)
3299 {
3300         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3301         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3302                sizeof(qcaps->mac_address));
3303         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3304         qcaps->max_rx_rings = fcfg->num_rx_rings;
3305         qcaps->max_tx_rings = fcfg->num_tx_rings;
3306         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3307         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3308         qcaps->max_vfs = 0;
3309         qcaps->first_vf_id = 0;
3310         qcaps->max_vnics = fcfg->num_vnics;
3311         qcaps->max_decap_records = 0;
3312         qcaps->max_encap_records = 0;
3313         qcaps->max_tx_wm_flows = 0;
3314         qcaps->max_tx_em_flows = 0;
3315         qcaps->max_rx_wm_flows = 0;
3316         qcaps->max_rx_em_flows = 0;
3317         qcaps->max_flow_id = 0;
3318         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3319         qcaps->max_sp_tx_rings = 0;
3320         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3321 }
3322
3323 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3324 {
3325         struct hwrm_func_cfg_input req = {0};
3326         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3327         uint32_t enables;
3328         int rc;
3329
3330         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3331                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3332                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3333                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3334                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3335                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3336                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3337                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3338                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3339
3340         if (BNXT_HAS_RING_GRPS(bp)) {
3341                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3342                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3343         } else if (BNXT_HAS_NQ(bp)) {
3344                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3345                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3346         }
3347
3348         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3349         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3350         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3351         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3352         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3353         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3354         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3355         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3356         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3357         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3358         req.fid = rte_cpu_to_le_16(0xffff);
3359         req.enables = rte_cpu_to_le_32(enables);
3360
3361         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3362
3363         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3364
3365         HWRM_CHECK_RESULT();
3366         HWRM_UNLOCK();
3367
3368         return rc;
3369 }
3370
3371 static void populate_vf_func_cfg_req(struct bnxt *bp,
3372                                      struct hwrm_func_cfg_input *req,
3373                                      int num_vfs)
3374 {
3375         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3376                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3377                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3378                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3379                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3380                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3381                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3382                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3383                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3384                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3385
3386         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3387                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3388                                     BNXT_NUM_VLANS);
3389         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3390         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3391                                                 (num_vfs + 1));
3392         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3393         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3394                                                (num_vfs + 1));
3395         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3396         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3397         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3398         /* TODO: For now, do not support VMDq/RFS on VFs. */
3399         req->num_vnics = rte_cpu_to_le_16(1);
3400         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3401                                                  (num_vfs + 1));
3402 }
3403
3404 static void add_random_mac_if_needed(struct bnxt *bp,
3405                                      struct hwrm_func_cfg_input *cfg_req,
3406                                      int vf)
3407 {
3408         struct rte_ether_addr mac;
3409
3410         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3411                 return;
3412
3413         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3414                 cfg_req->enables |=
3415                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3416                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3417                 bp->pf->vf_info[vf].random_mac = true;
3418         } else {
3419                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3420                         RTE_ETHER_ADDR_LEN);
3421         }
3422 }
3423
3424 static int reserve_resources_from_vf(struct bnxt *bp,
3425                                      struct hwrm_func_cfg_input *cfg_req,
3426                                      int vf)
3427 {
3428         struct hwrm_func_qcaps_input req = {0};
3429         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3430         int rc;
3431
3432         /* Get the actual allocated values now */
3433         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3434         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3435         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3436
3437         if (rc) {
3438                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3439                 copy_func_cfg_to_qcaps(cfg_req, resp);
3440         } else if (resp->error_code) {
3441                 rc = rte_le_to_cpu_16(resp->error_code);
3442                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3443                 copy_func_cfg_to_qcaps(cfg_req, resp);
3444         }
3445
3446         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3447         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3448         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3449         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3450         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3451         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3452         /*
3453          * TODO: While not supporting VMDq with VFs, max_vnics is always
3454          * forced to 1 in this case
3455          */
3456         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3457         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3458
3459         HWRM_UNLOCK();
3460
3461         return 0;
3462 }
3463
3464 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3465 {
3466         struct hwrm_func_qcfg_input req = {0};
3467         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3468         int rc;
3469
3470         /* Check for zero MAC address */
3471         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3472         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3474         HWRM_CHECK_RESULT();
3475         rc = rte_le_to_cpu_16(resp->vlan);
3476
3477         HWRM_UNLOCK();
3478
3479         return rc;
3480 }
3481
3482 static int update_pf_resource_max(struct bnxt *bp)
3483 {
3484         struct hwrm_func_qcfg_input req = {0};
3485         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3486         int rc;
3487
3488         /* And copy the allocated numbers into the pf struct */
3489         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3490         req.fid = rte_cpu_to_le_16(0xffff);
3491         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3492         HWRM_CHECK_RESULT();
3493
3494         /* Only TX ring value reflects actual allocation? TODO */
3495         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3496         bp->pf->evb_mode = resp->evb_mode;
3497
3498         HWRM_UNLOCK();
3499
3500         return rc;
3501 }
3502
3503 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3504 {
3505         int rc;
3506
3507         if (!BNXT_PF(bp)) {
3508                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3509                 return -EINVAL;
3510         }
3511
3512         rc = bnxt_hwrm_func_qcaps(bp);
3513         if (rc)
3514                 return rc;
3515
3516         bp->pf->func_cfg_flags &=
3517                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3518                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3519         bp->pf->func_cfg_flags |=
3520                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3521         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3522         rc = __bnxt_hwrm_func_qcaps(bp);
3523         return rc;
3524 }
3525
3526 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3527 {
3528         struct hwrm_func_cfg_input req = {0};
3529         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3530         int i;
3531         size_t sz;
3532         int rc = 0;
3533         size_t req_buf_sz;
3534
3535         if (!BNXT_PF(bp)) {
3536                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3537                 return -EINVAL;
3538         }
3539
3540         rc = bnxt_hwrm_func_qcaps(bp);
3541
3542         if (rc)
3543                 return rc;
3544
3545         bp->pf->active_vfs = num_vfs;
3546
3547         /*
3548          * First, configure the PF to only use one TX ring.  This ensures that
3549          * there are enough rings for all VFs.
3550          *
3551          * If we don't do this, when we call func_alloc() later, we will lock
3552          * extra rings to the PF that won't be available during func_cfg() of
3553          * the VFs.
3554          *
3555          * This has been fixed with firmware versions above 20.6.54
3556          */
3557         bp->pf->func_cfg_flags &=
3558                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3559                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3560         bp->pf->func_cfg_flags |=
3561                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3562         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3563         if (rc)
3564                 return rc;
3565
3566         /*
3567          * Now, create and register a buffer to hold forwarded VF requests
3568          */
3569         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3570         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3571                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3572         if (bp->pf->vf_req_buf == NULL) {
3573                 rc = -ENOMEM;
3574                 goto error_free;
3575         }
3576         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3577                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3578         for (i = 0; i < num_vfs; i++)
3579                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3580                                         (i * HWRM_MAX_REQ_LEN);
3581
3582         rc = bnxt_hwrm_func_buf_rgtr(bp);
3583         if (rc)
3584                 goto error_free;
3585
3586         populate_vf_func_cfg_req(bp, &req, num_vfs);
3587
3588         bp->pf->active_vfs = 0;
3589         for (i = 0; i < num_vfs; i++) {
3590                 add_random_mac_if_needed(bp, &req, i);
3591
3592                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3593                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3594                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3595                 rc = bnxt_hwrm_send_message(bp,
3596                                             &req,
3597                                             sizeof(req),
3598                                             BNXT_USE_CHIMP_MB);
3599
3600                 /* Clear enable flag for next pass */
3601                 req.enables &= ~rte_cpu_to_le_32(
3602                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3603
3604                 if (rc || resp->error_code) {
3605                         PMD_DRV_LOG(ERR,
3606                                 "Failed to initizlie VF %d\n", i);
3607                         PMD_DRV_LOG(ERR,
3608                                 "Not all VFs available. (%d, %d)\n",
3609                                 rc, resp->error_code);
3610                         HWRM_UNLOCK();
3611                         break;
3612                 }
3613
3614                 HWRM_UNLOCK();
3615
3616                 reserve_resources_from_vf(bp, &req, i);
3617                 bp->pf->active_vfs++;
3618                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3619         }
3620
3621         /*
3622          * Now configure the PF to use "the rest" of the resources
3623          * We're using STD_TX_RING_MODE here though which will limit the TX
3624          * rings.  This will allow QoS to function properly.  Not setting this
3625          * will cause PF rings to break bandwidth settings.
3626          */
3627         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3628         if (rc)
3629                 goto error_free;
3630
3631         rc = update_pf_resource_max(bp);
3632         if (rc)
3633                 goto error_free;
3634
3635         return rc;
3636
3637 error_free:
3638         bnxt_hwrm_func_buf_unrgtr(bp);
3639         return rc;
3640 }
3641
3642 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3643 {
3644         struct hwrm_func_cfg_input req = {0};
3645         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3646         int rc;
3647
3648         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3649
3650         req.fid = rte_cpu_to_le_16(0xffff);
3651         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3652         req.evb_mode = bp->pf->evb_mode;
3653
3654         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3655         HWRM_CHECK_RESULT();
3656         HWRM_UNLOCK();
3657
3658         return rc;
3659 }
3660
3661 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3662                                 uint8_t tunnel_type)
3663 {
3664         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3665         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3666         int rc = 0;
3667
3668         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3669         req.tunnel_type = tunnel_type;
3670         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3671         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3672         HWRM_CHECK_RESULT();
3673
3674         switch (tunnel_type) {
3675         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3676                 bp->vxlan_fw_dst_port_id =
3677                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3678                 bp->vxlan_port = port;
3679                 break;
3680         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3681                 bp->geneve_fw_dst_port_id =
3682                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3683                 bp->geneve_port = port;
3684                 break;
3685         default:
3686                 break;
3687         }
3688
3689         HWRM_UNLOCK();
3690
3691         return rc;
3692 }
3693
3694 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3695                                 uint8_t tunnel_type)
3696 {
3697         struct hwrm_tunnel_dst_port_free_input req = {0};
3698         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3699         int rc = 0;
3700
3701         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3702
3703         req.tunnel_type = tunnel_type;
3704         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3705         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3706
3707         HWRM_CHECK_RESULT();
3708         HWRM_UNLOCK();
3709
3710         return rc;
3711 }
3712
3713 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3714                                         uint32_t flags)
3715 {
3716         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3717         struct hwrm_func_cfg_input req = {0};
3718         int rc;
3719
3720         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3721
3722         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3723         req.flags = rte_cpu_to_le_32(flags);
3724         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3725
3726         HWRM_CHECK_RESULT();
3727         HWRM_UNLOCK();
3728
3729         return rc;
3730 }
3731
3732 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3733 {
3734         uint32_t *flag = flagp;
3735
3736         vnic->flags = *flag;
3737 }
3738
3739 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3740 {
3741         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3742 }
3743
3744 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3745 {
3746         int rc = 0;
3747         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3748         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3749
3750         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3751
3752         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3753         req.req_buf_page_size = rte_cpu_to_le_16(
3754                          page_getenum(bp->pf->active_vfs * HWRM_MAX_REQ_LEN));
3755         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3756         req.req_buf_page_addr0 =
3757                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3758         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3759                 PMD_DRV_LOG(ERR,
3760                         "unable to map buffer address to physical memory\n");
3761                 return -ENOMEM;
3762         }
3763
3764         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3765
3766         HWRM_CHECK_RESULT();
3767         HWRM_UNLOCK();
3768
3769         return rc;
3770 }
3771
3772 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3773 {
3774         int rc = 0;
3775         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3776         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3777
3778         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3779                 return 0;
3780
3781         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3782
3783         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3784
3785         HWRM_CHECK_RESULT();
3786         HWRM_UNLOCK();
3787
3788         return rc;
3789 }
3790
3791 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3792 {
3793         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3794         struct hwrm_func_cfg_input req = {0};
3795         int rc;
3796
3797         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3798
3799         req.fid = rte_cpu_to_le_16(0xffff);
3800         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3801         req.enables = rte_cpu_to_le_32(
3802                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3803         req.async_event_cr = rte_cpu_to_le_16(
3804                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3805         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3806
3807         HWRM_CHECK_RESULT();
3808         HWRM_UNLOCK();
3809
3810         return rc;
3811 }
3812
3813 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3814 {
3815         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3816         struct hwrm_func_vf_cfg_input req = {0};
3817         int rc;
3818
3819         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3820
3821         req.enables = rte_cpu_to_le_32(
3822                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3823         req.async_event_cr = rte_cpu_to_le_16(
3824                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3825         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3826
3827         HWRM_CHECK_RESULT();
3828         HWRM_UNLOCK();
3829
3830         return rc;
3831 }
3832
3833 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3834 {
3835         struct hwrm_func_cfg_input req = {0};
3836         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3837         uint16_t dflt_vlan, fid;
3838         uint32_t func_cfg_flags;
3839         int rc = 0;
3840
3841         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3842
3843         if (is_vf) {
3844                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
3845                 fid = bp->pf->vf_info[vf].fid;
3846                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
3847         } else {
3848                 fid = rte_cpu_to_le_16(0xffff);
3849                 func_cfg_flags = bp->pf->func_cfg_flags;
3850                 dflt_vlan = bp->vlan;
3851         }
3852
3853         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3854         req.fid = rte_cpu_to_le_16(fid);
3855         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3856         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3857
3858         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3859
3860         HWRM_CHECK_RESULT();
3861         HWRM_UNLOCK();
3862
3863         return rc;
3864 }
3865
3866 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3867                         uint16_t max_bw, uint16_t enables)
3868 {
3869         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3870         struct hwrm_func_cfg_input req = {0};
3871         int rc;
3872
3873         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3874
3875         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3876         req.enables |= rte_cpu_to_le_32(enables);
3877         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3878         req.max_bw = rte_cpu_to_le_32(max_bw);
3879         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3880
3881         HWRM_CHECK_RESULT();
3882         HWRM_UNLOCK();
3883
3884         return rc;
3885 }
3886
3887 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3888 {
3889         struct hwrm_func_cfg_input req = {0};
3890         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3891         int rc = 0;
3892
3893         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3894
3895         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3896         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3897         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3898         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
3899
3900         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3901
3902         HWRM_CHECK_RESULT();
3903         HWRM_UNLOCK();
3904
3905         return rc;
3906 }
3907
3908 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3909 {
3910         int rc;
3911
3912         if (BNXT_PF(bp))
3913                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3914         else
3915                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3916
3917         return rc;
3918 }
3919
3920 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3921                               void *encaped, size_t ec_size)
3922 {
3923         int rc = 0;
3924         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3925         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3926
3927         if (ec_size > sizeof(req.encap_request))
3928                 return -1;
3929
3930         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3931
3932         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3933         memcpy(req.encap_request, encaped, ec_size);
3934
3935         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3936
3937         HWRM_CHECK_RESULT();
3938         HWRM_UNLOCK();
3939
3940         return rc;
3941 }
3942
3943 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3944                                        struct rte_ether_addr *mac)
3945 {
3946         struct hwrm_func_qcfg_input req = {0};
3947         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3948         int rc;
3949
3950         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3951
3952         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3953         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3954
3955         HWRM_CHECK_RESULT();
3956
3957         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3958
3959         HWRM_UNLOCK();
3960
3961         return rc;
3962 }
3963
3964 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3965                             void *encaped, size_t ec_size)
3966 {
3967         int rc = 0;
3968         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3969         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3970
3971         if (ec_size > sizeof(req.encap_request))
3972                 return -1;
3973
3974         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3975
3976         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3977         memcpy(req.encap_request, encaped, ec_size);
3978
3979         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3980
3981         HWRM_CHECK_RESULT();
3982         HWRM_UNLOCK();
3983
3984         return rc;
3985 }
3986
3987 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3988                          struct rte_eth_stats *stats, uint8_t rx)
3989 {
3990         int rc = 0;
3991         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3992         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3993
3994         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3995
3996         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3997
3998         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3999
4000         HWRM_CHECK_RESULT();
4001
4002         if (rx) {
4003                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4004                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
4005                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
4006                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4007                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
4008                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
4009                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
4010                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
4011         } else {
4012                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4013                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
4014                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
4015                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4016                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
4017                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
4018         }
4019
4020         HWRM_UNLOCK();
4021
4022         return rc;
4023 }
4024
4025 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4026 {
4027         struct hwrm_port_qstats_input req = {0};
4028         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4029         struct bnxt_pf_info *pf = bp->pf;
4030         int rc;
4031
4032         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4033
4034         req.port_id = rte_cpu_to_le_16(pf->port_id);
4035         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4036         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4037         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4038
4039         HWRM_CHECK_RESULT();
4040         HWRM_UNLOCK();
4041
4042         return rc;
4043 }
4044
4045 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4046 {
4047         struct hwrm_port_clr_stats_input req = {0};
4048         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4049         struct bnxt_pf_info *pf = bp->pf;
4050         int rc;
4051
4052         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4053         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4054             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4055                 return 0;
4056
4057         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4058
4059         req.port_id = rte_cpu_to_le_16(pf->port_id);
4060         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4061
4062         HWRM_CHECK_RESULT();
4063         HWRM_UNLOCK();
4064
4065         return rc;
4066 }
4067
4068 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4069 {
4070         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4071         struct hwrm_port_led_qcaps_input req = {0};
4072         int rc;
4073
4074         if (BNXT_VF(bp))
4075                 return 0;
4076
4077         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4078         req.port_id = bp->pf->port_id;
4079         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4080
4081         HWRM_CHECK_RESULT();
4082
4083         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4084                 unsigned int i;
4085
4086                 bp->leds->num_leds = resp->num_leds;
4087                 memcpy(bp->leds, &resp->led0_id,
4088                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4089                 for (i = 0; i < bp->leds->num_leds; i++) {
4090                         struct bnxt_led_info *led = &bp->leds[i];
4091
4092                         uint16_t caps = led->led_state_caps;
4093
4094                         if (!led->led_group_id ||
4095                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4096                                 bp->leds->num_leds = 0;
4097                                 break;
4098                         }
4099                 }
4100         }
4101
4102         HWRM_UNLOCK();
4103
4104         return rc;
4105 }
4106
4107 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4108 {
4109         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4110         struct hwrm_port_led_cfg_input req = {0};
4111         struct bnxt_led_cfg *led_cfg;
4112         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4113         uint16_t duration = 0;
4114         int rc, i;
4115
4116         if (!bp->leds->num_leds || BNXT_VF(bp))
4117                 return -EOPNOTSUPP;
4118
4119         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4120
4121         if (led_on) {
4122                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4123                 duration = rte_cpu_to_le_16(500);
4124         }
4125         req.port_id = bp->pf->port_id;
4126         req.num_leds = bp->leds->num_leds;
4127         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4128         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4129                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4130                 led_cfg->led_id = bp->leds[i].led_id;
4131                 led_cfg->led_state = led_state;
4132                 led_cfg->led_blink_on = duration;
4133                 led_cfg->led_blink_off = duration;
4134                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4135         }
4136
4137         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4138
4139         HWRM_CHECK_RESULT();
4140         HWRM_UNLOCK();
4141
4142         return rc;
4143 }
4144
4145 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4146                                uint32_t *length)
4147 {
4148         int rc;
4149         struct hwrm_nvm_get_dir_info_input req = {0};
4150         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4151
4152         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4153
4154         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4155
4156         HWRM_CHECK_RESULT();
4157
4158         *entries = rte_le_to_cpu_32(resp->entries);
4159         *length = rte_le_to_cpu_32(resp->entry_length);
4160
4161         HWRM_UNLOCK();
4162         return rc;
4163 }
4164
4165 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4166 {
4167         int rc;
4168         uint32_t dir_entries;
4169         uint32_t entry_length;
4170         uint8_t *buf;
4171         size_t buflen;
4172         rte_iova_t dma_handle;
4173         struct hwrm_nvm_get_dir_entries_input req = {0};
4174         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4175
4176         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4177         if (rc != 0)
4178                 return rc;
4179
4180         *data++ = dir_entries;
4181         *data++ = entry_length;
4182         len -= 2;
4183         memset(data, 0xff, len);
4184
4185         buflen = dir_entries * entry_length;
4186         buf = rte_malloc("nvm_dir", buflen, 0);
4187         if (buf == NULL)
4188                 return -ENOMEM;
4189         dma_handle = rte_malloc_virt2iova(buf);
4190         if (dma_handle == RTE_BAD_IOVA) {
4191                 PMD_DRV_LOG(ERR,
4192                         "unable to map response address to physical memory\n");
4193                 return -ENOMEM;
4194         }
4195         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4196         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4197         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4198
4199         if (rc == 0)
4200                 memcpy(data, buf, len > buflen ? buflen : len);
4201
4202         rte_free(buf);
4203         HWRM_CHECK_RESULT();
4204         HWRM_UNLOCK();
4205
4206         return rc;
4207 }
4208
4209 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4210                              uint32_t offset, uint32_t length,
4211                              uint8_t *data)
4212 {
4213         int rc;
4214         uint8_t *buf;
4215         rte_iova_t dma_handle;
4216         struct hwrm_nvm_read_input req = {0};
4217         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4218
4219         buf = rte_malloc("nvm_item", length, 0);
4220         if (!buf)
4221                 return -ENOMEM;
4222
4223         dma_handle = rte_malloc_virt2iova(buf);
4224         if (dma_handle == RTE_BAD_IOVA) {
4225                 PMD_DRV_LOG(ERR,
4226                         "unable to map response address to physical memory\n");
4227                 return -ENOMEM;
4228         }
4229         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4230         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4231         req.dir_idx = rte_cpu_to_le_16(index);
4232         req.offset = rte_cpu_to_le_32(offset);
4233         req.len = rte_cpu_to_le_32(length);
4234         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4235         if (rc == 0)
4236                 memcpy(data, buf, length);
4237
4238         rte_free(buf);
4239         HWRM_CHECK_RESULT();
4240         HWRM_UNLOCK();
4241
4242         return rc;
4243 }
4244
4245 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4246 {
4247         int rc;
4248         struct hwrm_nvm_erase_dir_entry_input req = {0};
4249         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4250
4251         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4252         req.dir_idx = rte_cpu_to_le_16(index);
4253         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4254         HWRM_CHECK_RESULT();
4255         HWRM_UNLOCK();
4256
4257         return rc;
4258 }
4259
4260
4261 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4262                           uint16_t dir_ordinal, uint16_t dir_ext,
4263                           uint16_t dir_attr, const uint8_t *data,
4264                           size_t data_len)
4265 {
4266         int rc;
4267         struct hwrm_nvm_write_input req = {0};
4268         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4269         rte_iova_t dma_handle;
4270         uint8_t *buf;
4271
4272         buf = rte_malloc("nvm_write", data_len, 0);
4273         if (!buf)
4274                 return -ENOMEM;
4275
4276         dma_handle = rte_malloc_virt2iova(buf);
4277         if (dma_handle == RTE_BAD_IOVA) {
4278                 PMD_DRV_LOG(ERR,
4279                         "unable to map response address to physical memory\n");
4280                 return -ENOMEM;
4281         }
4282         memcpy(buf, data, data_len);
4283
4284         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4285
4286         req.dir_type = rte_cpu_to_le_16(dir_type);
4287         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4288         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4289         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4290         req.dir_data_length = rte_cpu_to_le_32(data_len);
4291         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4292
4293         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4294
4295         rte_free(buf);
4296         HWRM_CHECK_RESULT();
4297         HWRM_UNLOCK();
4298
4299         return rc;
4300 }
4301
4302 static void
4303 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4304 {
4305         uint32_t *count = cbdata;
4306
4307         *count = *count + 1;
4308 }
4309
4310 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4311                                      struct bnxt_vnic_info *vnic __rte_unused)
4312 {
4313         return 0;
4314 }
4315
4316 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4317 {
4318         uint32_t count = 0;
4319
4320         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4321             &count, bnxt_vnic_count_hwrm_stub);
4322
4323         return count;
4324 }
4325
4326 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4327                                         uint16_t *vnic_ids)
4328 {
4329         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4330         struct hwrm_func_vf_vnic_ids_query_output *resp =
4331                                                 bp->hwrm_cmd_resp_addr;
4332         int rc;
4333
4334         /* First query all VNIC ids */
4335         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4336
4337         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4338         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4339         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4340
4341         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4342                 HWRM_UNLOCK();
4343                 PMD_DRV_LOG(ERR,
4344                 "unable to map VNIC ID table address to physical memory\n");
4345                 return -ENOMEM;
4346         }
4347         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4348         HWRM_CHECK_RESULT();
4349         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4350
4351         HWRM_UNLOCK();
4352
4353         return rc;
4354 }
4355
4356 /*
4357  * This function queries the VNIC IDs  for a specified VF. It then calls
4358  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4359  * Then it calls the hwrm_cb function to program this new vnic configuration.
4360  */
4361 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4362         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4363         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4364 {
4365         struct bnxt_vnic_info vnic;
4366         int rc = 0;
4367         int i, num_vnic_ids;
4368         uint16_t *vnic_ids;
4369         size_t vnic_id_sz;
4370         size_t sz;
4371
4372         /* First query all VNIC ids */
4373         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4374         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4375                         RTE_CACHE_LINE_SIZE);
4376         if (vnic_ids == NULL)
4377                 return -ENOMEM;
4378
4379         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4380                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4381
4382         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4383
4384         if (num_vnic_ids < 0)
4385                 return num_vnic_ids;
4386
4387         /* Retrieve VNIC, update bd_stall then update */
4388
4389         for (i = 0; i < num_vnic_ids; i++) {
4390                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4391                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4392                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4393                 if (rc)
4394                         break;
4395                 if (vnic.mru <= 4)      /* Indicates unallocated */
4396                         continue;
4397
4398                 vnic_cb(&vnic, cbdata);
4399
4400                 rc = hwrm_cb(bp, &vnic);
4401                 if (rc)
4402                         break;
4403         }
4404
4405         rte_free(vnic_ids);
4406
4407         return rc;
4408 }
4409
4410 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4411                                               bool on)
4412 {
4413         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4414         struct hwrm_func_cfg_input req = {0};
4415         int rc;
4416
4417         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4418
4419         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4420         req.enables |= rte_cpu_to_le_32(
4421                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4422         req.vlan_antispoof_mode = on ?
4423                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4424                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4425         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4426
4427         HWRM_CHECK_RESULT();
4428         HWRM_UNLOCK();
4429
4430         return rc;
4431 }
4432
4433 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4434 {
4435         struct bnxt_vnic_info vnic;
4436         uint16_t *vnic_ids;
4437         size_t vnic_id_sz;
4438         int num_vnic_ids, i;
4439         size_t sz;
4440         int rc;
4441
4442         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4443         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4444                         RTE_CACHE_LINE_SIZE);
4445         if (vnic_ids == NULL)
4446                 return -ENOMEM;
4447
4448         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4449                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4450
4451         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4452         if (rc <= 0)
4453                 goto exit;
4454         num_vnic_ids = rc;
4455
4456         /*
4457          * Loop through to find the default VNIC ID.
4458          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4459          * by sending the hwrm_func_qcfg command to the firmware.
4460          */
4461         for (i = 0; i < num_vnic_ids; i++) {
4462                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4463                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4464                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4465                                         bp->pf->first_vf_id + vf);
4466                 if (rc)
4467                         goto exit;
4468                 if (vnic.func_default) {
4469                         rte_free(vnic_ids);
4470                         return vnic.fw_vnic_id;
4471                 }
4472         }
4473         /* Could not find a default VNIC. */
4474         PMD_DRV_LOG(ERR, "No default VNIC\n");
4475 exit:
4476         rte_free(vnic_ids);
4477         return rc;
4478 }
4479
4480 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4481                          uint16_t dst_id,
4482                          struct bnxt_filter_info *filter)
4483 {
4484         int rc = 0;
4485         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4486         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4487         uint32_t enables = 0;
4488
4489         if (filter->fw_em_filter_id != UINT64_MAX)
4490                 bnxt_hwrm_clear_em_filter(bp, filter);
4491
4492         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4493
4494         req.flags = rte_cpu_to_le_32(filter->flags);
4495
4496         enables = filter->enables |
4497               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4498         req.dst_id = rte_cpu_to_le_16(dst_id);
4499
4500         if (filter->ip_addr_type) {
4501                 req.ip_addr_type = filter->ip_addr_type;
4502                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4503         }
4504         if (enables &
4505             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4506                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4507         if (enables &
4508             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4509                 memcpy(req.src_macaddr, filter->src_macaddr,
4510                        RTE_ETHER_ADDR_LEN);
4511         if (enables &
4512             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4513                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4514                        RTE_ETHER_ADDR_LEN);
4515         if (enables &
4516             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4517                 req.ovlan_vid = filter->l2_ovlan;
4518         if (enables &
4519             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4520                 req.ivlan_vid = filter->l2_ivlan;
4521         if (enables &
4522             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4523                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4524         if (enables &
4525             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4526                 req.ip_protocol = filter->ip_protocol;
4527         if (enables &
4528             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4529                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4530         if (enables &
4531             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4532                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4533         if (enables &
4534             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4535                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4536         if (enables &
4537             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4538                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4539         if (enables &
4540             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4541                 req.mirror_vnic_id = filter->mirror_vnic_id;
4542
4543         req.enables = rte_cpu_to_le_32(enables);
4544
4545         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4546
4547         HWRM_CHECK_RESULT();
4548
4549         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4550         HWRM_UNLOCK();
4551
4552         return rc;
4553 }
4554
4555 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4556 {
4557         int rc = 0;
4558         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4559         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4560
4561         if (filter->fw_em_filter_id == UINT64_MAX)
4562                 return 0;
4563
4564         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4565
4566         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4567
4568         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4569
4570         HWRM_CHECK_RESULT();
4571         HWRM_UNLOCK();
4572
4573         filter->fw_em_filter_id = UINT64_MAX;
4574         filter->fw_l2_filter_id = UINT64_MAX;
4575
4576         return 0;
4577 }
4578
4579 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4580                          uint16_t dst_id,
4581                          struct bnxt_filter_info *filter)
4582 {
4583         int rc = 0;
4584         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4585         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4586                                                 bp->hwrm_cmd_resp_addr;
4587         uint32_t enables = 0;
4588
4589         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4590                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4591
4592         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4593
4594         req.flags = rte_cpu_to_le_32(filter->flags);
4595
4596         enables = filter->enables |
4597               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4598         req.dst_id = rte_cpu_to_le_16(dst_id);
4599
4600         if (filter->ip_addr_type) {
4601                 req.ip_addr_type = filter->ip_addr_type;
4602                 enables |=
4603                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4604         }
4605         if (enables &
4606             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4607                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4608         if (enables &
4609             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4610                 memcpy(req.src_macaddr, filter->src_macaddr,
4611                        RTE_ETHER_ADDR_LEN);
4612         if (enables &
4613             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4614                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4615         if (enables &
4616             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4617                 req.ip_protocol = filter->ip_protocol;
4618         if (enables &
4619             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4620                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4621         if (enables &
4622             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4623                 req.src_ipaddr_mask[0] =
4624                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4625         if (enables &
4626             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4627                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4628         if (enables &
4629             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4630                 req.dst_ipaddr_mask[0] =
4631                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4632         if (enables &
4633             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4634                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4635         if (enables &
4636             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4637                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4638         if (enables &
4639             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4640                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4641         if (enables &
4642             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4643                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4644         if (enables &
4645             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4646                 req.mirror_vnic_id = filter->mirror_vnic_id;
4647
4648         req.enables = rte_cpu_to_le_32(enables);
4649
4650         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4651
4652         HWRM_CHECK_RESULT();
4653
4654         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4655         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4656         HWRM_UNLOCK();
4657
4658         return rc;
4659 }
4660
4661 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4662                                 struct bnxt_filter_info *filter)
4663 {
4664         int rc = 0;
4665         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4666         struct hwrm_cfa_ntuple_filter_free_output *resp =
4667                                                 bp->hwrm_cmd_resp_addr;
4668
4669         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4670                 return 0;
4671
4672         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4673
4674         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4675
4676         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4677
4678         HWRM_CHECK_RESULT();
4679         HWRM_UNLOCK();
4680
4681         filter->fw_ntuple_filter_id = UINT64_MAX;
4682
4683         return 0;
4684 }
4685
4686 static int
4687 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4688 {
4689         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4690         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4691         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4692         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4693         uint16_t *ring_tbl = vnic->rss_table;
4694         int nr_ctxs = vnic->num_lb_ctxts;
4695         int max_rings = bp->rx_nr_rings;
4696         int i, j, k, cnt;
4697         int rc = 0;
4698
4699         for (i = 0, k = 0; i < nr_ctxs; i++) {
4700                 struct bnxt_rx_ring_info *rxr;
4701                 struct bnxt_cp_ring_info *cpr;
4702
4703                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4704
4705                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4706                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4707                 req.hash_mode_flags = vnic->hash_mode;
4708
4709                 req.ring_grp_tbl_addr =
4710                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4711                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4712                                      2 * sizeof(*ring_tbl));
4713                 req.hash_key_tbl_addr =
4714                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4715
4716                 req.ring_table_pair_index = i;
4717                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4718
4719                 for (j = 0; j < 64; j++) {
4720                         uint16_t ring_id;
4721
4722                         /* Find next active ring. */
4723                         for (cnt = 0; cnt < max_rings; cnt++) {
4724                                 if (rx_queue_state[k] !=
4725                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4726                                         break;
4727                                 if (++k == max_rings)
4728                                         k = 0;
4729                         }
4730
4731                         /* Return if no rings are active. */
4732                         if (cnt == max_rings) {
4733                                 HWRM_UNLOCK();
4734                                 return 0;
4735                         }
4736
4737                         /* Add rx/cp ring pair to RSS table. */
4738                         rxr = rxqs[k]->rx_ring;
4739                         cpr = rxqs[k]->cp_ring;
4740
4741                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4742                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4743                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4744                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4745
4746                         if (++k == max_rings)
4747                                 k = 0;
4748                 }
4749                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4750                                             BNXT_USE_CHIMP_MB);
4751
4752                 HWRM_CHECK_RESULT();
4753                 HWRM_UNLOCK();
4754         }
4755
4756         return rc;
4757 }
4758
4759 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4760 {
4761         unsigned int rss_idx, fw_idx, i;
4762
4763         if (!(vnic->rss_table && vnic->hash_type))
4764                 return 0;
4765
4766         if (BNXT_CHIP_THOR(bp))
4767                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4768
4769         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4770                 return 0;
4771
4772         if (vnic->rss_table && vnic->hash_type) {
4773                 /*
4774                  * Fill the RSS hash & redirection table with
4775                  * ring group ids for all VNICs
4776                  */
4777                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4778                         rss_idx++, fw_idx++) {
4779                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4780                                 fw_idx %= bp->rx_cp_nr_rings;
4781                                 if (vnic->fw_grp_ids[fw_idx] !=
4782                                     INVALID_HW_RING_ID)
4783                                         break;
4784                                 fw_idx++;
4785                         }
4786                         if (i == bp->rx_cp_nr_rings)
4787                                 return 0;
4788                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4789                 }
4790                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4791         }
4792
4793         return 0;
4794 }
4795
4796 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4797         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4798 {
4799         uint16_t flags;
4800
4801         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4802
4803         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4804         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4805
4806         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4807         req->num_cmpl_dma_aggr_during_int =
4808                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4809
4810         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4811
4812         /* min timer set to 1/2 of interrupt timer */
4813         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4814
4815         /* buf timer set to 1/4 of interrupt timer */
4816         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4817
4818         req->cmpl_aggr_dma_tmr_during_int =
4819                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4820
4821         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4822                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4823         req->flags = rte_cpu_to_le_16(flags);
4824 }
4825
4826 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4827                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4828 {
4829         struct hwrm_ring_aggint_qcaps_input req = {0};
4830         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4831         uint32_t enables;
4832         uint16_t flags;
4833         int rc;
4834
4835         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4836         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4837         HWRM_CHECK_RESULT();
4838
4839         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4840         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4841
4842         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4843                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4844         agg_req->flags = rte_cpu_to_le_16(flags);
4845         enables =
4846          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4847          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4848         agg_req->enables = rte_cpu_to_le_32(enables);
4849
4850         HWRM_UNLOCK();
4851         return rc;
4852 }
4853
4854 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4855                         struct bnxt_coal *coal, uint16_t ring_id)
4856 {
4857         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4858         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4859                                                 bp->hwrm_cmd_resp_addr;
4860         int rc;
4861
4862         /* Set ring coalesce parameters only for 100G NICs */
4863         if (BNXT_CHIP_THOR(bp)) {
4864                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4865                         return -1;
4866         } else if (bnxt_stratus_device(bp)) {
4867                 bnxt_hwrm_set_coal_params(coal, &req);
4868         } else {
4869                 return 0;
4870         }
4871
4872         HWRM_PREP(&req,
4873                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4874                   BNXT_USE_CHIMP_MB);
4875         req.ring_id = rte_cpu_to_le_16(ring_id);
4876         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4877         HWRM_CHECK_RESULT();
4878         HWRM_UNLOCK();
4879         return 0;
4880 }
4881
4882 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4883 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4884 {
4885         struct hwrm_func_backing_store_qcaps_input req = {0};
4886         struct hwrm_func_backing_store_qcaps_output *resp =
4887                 bp->hwrm_cmd_resp_addr;
4888         struct bnxt_ctx_pg_info *ctx_pg;
4889         struct bnxt_ctx_mem_info *ctx;
4890         int total_alloc_len;
4891         int rc, i, tqm_rings;
4892
4893         if (!BNXT_CHIP_THOR(bp) ||
4894             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4895             BNXT_VF(bp) ||
4896             bp->ctx)
4897                 return 0;
4898
4899         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4900         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4901         HWRM_CHECK_RESULT_SILENT();
4902
4903         total_alloc_len = sizeof(*ctx);
4904         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4905                           RTE_CACHE_LINE_SIZE);
4906         if (!ctx) {
4907                 rc = -ENOMEM;
4908                 goto ctx_err;
4909         }
4910
4911         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4912         ctx->qp_min_qp1_entries =
4913                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4914         ctx->qp_max_l2_entries =
4915                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4916         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4917         ctx->srq_max_l2_entries =
4918                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4919         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4920         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4921         ctx->cq_max_l2_entries =
4922                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4923         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4924         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4925         ctx->vnic_max_vnic_entries =
4926                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4927         ctx->vnic_max_ring_table_entries =
4928                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4929         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4930         ctx->stat_max_entries =
4931                 rte_le_to_cpu_32(resp->stat_max_entries);
4932         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4933         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4934         ctx->tqm_min_entries_per_ring =
4935                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4936         ctx->tqm_max_entries_per_ring =
4937                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4938         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4939         if (!ctx->tqm_entries_multiple)
4940                 ctx->tqm_entries_multiple = 1;
4941         ctx->mrav_max_entries =
4942                 rte_le_to_cpu_32(resp->mrav_max_entries);
4943         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4944         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4945         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4946         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
4947
4948         if (!ctx->tqm_fp_rings_count)
4949                 ctx->tqm_fp_rings_count = bp->max_q;
4950
4951         tqm_rings = ctx->tqm_fp_rings_count + 1;
4952
4953         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4954                             sizeof(*ctx_pg) * tqm_rings,
4955                             RTE_CACHE_LINE_SIZE);
4956         if (!ctx_pg) {
4957                 rc = -ENOMEM;
4958                 goto ctx_err;
4959         }
4960         for (i = 0; i < tqm_rings; i++, ctx_pg++)
4961                 ctx->tqm_mem[i] = ctx_pg;
4962
4963         bp->ctx = ctx;
4964 ctx_err:
4965         HWRM_UNLOCK();
4966         return rc;
4967 }
4968
4969 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4970 {
4971         struct hwrm_func_backing_store_cfg_input req = {0};
4972         struct hwrm_func_backing_store_cfg_output *resp =
4973                 bp->hwrm_cmd_resp_addr;
4974         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4975         struct bnxt_ctx_pg_info *ctx_pg;
4976         uint32_t *num_entries;
4977         uint64_t *pg_dir;
4978         uint8_t *pg_attr;
4979         uint32_t ena;
4980         int i, rc;
4981
4982         if (!ctx)
4983                 return 0;
4984
4985         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4986         req.enables = rte_cpu_to_le_32(enables);
4987
4988         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4989                 ctx_pg = &ctx->qp_mem;
4990                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4991                 req.qp_num_qp1_entries =
4992                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4993                 req.qp_num_l2_entries =
4994                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4995                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4996                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4997                                       &req.qpc_pg_size_qpc_lvl,
4998                                       &req.qpc_page_dir);
4999         }
5000
5001         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5002                 ctx_pg = &ctx->srq_mem;
5003                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5004                 req.srq_num_l2_entries =
5005                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5006                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5007                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5008                                       &req.srq_pg_size_srq_lvl,
5009                                       &req.srq_page_dir);
5010         }
5011
5012         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5013                 ctx_pg = &ctx->cq_mem;
5014                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5015                 req.cq_num_l2_entries =
5016                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5017                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5018                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5019                                       &req.cq_pg_size_cq_lvl,
5020                                       &req.cq_page_dir);
5021         }
5022
5023         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5024                 ctx_pg = &ctx->vnic_mem;
5025                 req.vnic_num_vnic_entries =
5026                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5027                 req.vnic_num_ring_table_entries =
5028                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5029                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5030                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5031                                       &req.vnic_pg_size_vnic_lvl,
5032                                       &req.vnic_page_dir);
5033         }
5034
5035         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5036                 ctx_pg = &ctx->stat_mem;
5037                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5038                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5039                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5040                                       &req.stat_pg_size_stat_lvl,
5041                                       &req.stat_page_dir);
5042         }
5043
5044         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5045         num_entries = &req.tqm_sp_num_entries;
5046         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5047         pg_dir = &req.tqm_sp_page_dir;
5048         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5049         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5050                 if (!(enables & ena))
5051                         continue;
5052
5053                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5054
5055                 ctx_pg = ctx->tqm_mem[i];
5056                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5057                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5058         }
5059
5060         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5061         HWRM_CHECK_RESULT();
5062         HWRM_UNLOCK();
5063
5064         return rc;
5065 }
5066
5067 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5068 {
5069         struct hwrm_port_qstats_ext_input req = {0};
5070         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5071         struct bnxt_pf_info *pf = bp->pf;
5072         int rc;
5073
5074         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5075               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5076                 return 0;
5077
5078         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5079
5080         req.port_id = rte_cpu_to_le_16(pf->port_id);
5081         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5082                 req.tx_stat_host_addr =
5083                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5084                 req.tx_stat_size =
5085                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5086         }
5087         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5088                 req.rx_stat_host_addr =
5089                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5090                 req.rx_stat_size =
5091                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5092         }
5093         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5094
5095         if (rc) {
5096                 bp->fw_rx_port_stats_ext_size = 0;
5097                 bp->fw_tx_port_stats_ext_size = 0;
5098         } else {
5099                 bp->fw_rx_port_stats_ext_size =
5100                         rte_le_to_cpu_16(resp->rx_stat_size);
5101                 bp->fw_tx_port_stats_ext_size =
5102                         rte_le_to_cpu_16(resp->tx_stat_size);
5103         }
5104
5105         HWRM_CHECK_RESULT();
5106         HWRM_UNLOCK();
5107
5108         return rc;
5109 }
5110
5111 int
5112 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5113 {
5114         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5115         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5116                 bp->hwrm_cmd_resp_addr;
5117         int rc = 0;
5118
5119         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5120         req.tunnel_type = type;
5121         req.dest_fid = bp->fw_fid;
5122         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5123         HWRM_CHECK_RESULT();
5124
5125         HWRM_UNLOCK();
5126
5127         return rc;
5128 }
5129
5130 int
5131 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5132 {
5133         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5134         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5135                 bp->hwrm_cmd_resp_addr;
5136         int rc = 0;
5137
5138         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5139         req.tunnel_type = type;
5140         req.dest_fid = bp->fw_fid;
5141         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5142         HWRM_CHECK_RESULT();
5143
5144         HWRM_UNLOCK();
5145
5146         return rc;
5147 }
5148
5149 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5150 {
5151         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5152         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5153                 bp->hwrm_cmd_resp_addr;
5154         int rc = 0;
5155
5156         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5157         req.src_fid = bp->fw_fid;
5158         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5159         HWRM_CHECK_RESULT();
5160
5161         if (type)
5162                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5163
5164         HWRM_UNLOCK();
5165
5166         return rc;
5167 }
5168
5169 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5170                                    uint16_t *dst_fid)
5171 {
5172         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5173         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5174                 bp->hwrm_cmd_resp_addr;
5175         int rc = 0;
5176
5177         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5178         req.src_fid = bp->fw_fid;
5179         req.tunnel_type = tun_type;
5180         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5181         HWRM_CHECK_RESULT();
5182
5183         if (dst_fid)
5184                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5185
5186         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5187
5188         HWRM_UNLOCK();
5189
5190         return rc;
5191 }
5192
5193 int bnxt_hwrm_set_mac(struct bnxt *bp)
5194 {
5195         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5196         struct hwrm_func_vf_cfg_input req = {0};
5197         int rc = 0;
5198
5199         if (!BNXT_VF(bp))
5200                 return 0;
5201
5202         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5203
5204         req.enables =
5205                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5206         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5207
5208         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5209
5210         HWRM_CHECK_RESULT();
5211
5212         HWRM_UNLOCK();
5213
5214         return rc;
5215 }
5216
5217 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5218 {
5219         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5220         struct hwrm_func_drv_if_change_input req = {0};
5221         uint32_t flags;
5222         int rc;
5223
5224         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5225                 return 0;
5226
5227         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5228          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5229          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5230          */
5231         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5232                 return 0;
5233
5234         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5235
5236         if (up)
5237                 req.flags =
5238                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5239
5240         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5241
5242         HWRM_CHECK_RESULT();
5243         flags = rte_le_to_cpu_32(resp->flags);
5244         HWRM_UNLOCK();
5245
5246         if (!up)
5247                 return 0;
5248
5249         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5250                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5251                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5252         }
5253
5254         return 0;
5255 }
5256
5257 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5258 {
5259         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5260         struct bnxt_error_recovery_info *info = bp->recovery_info;
5261         struct hwrm_error_recovery_qcfg_input req = {0};
5262         uint32_t flags = 0;
5263         unsigned int i;
5264         int rc;
5265
5266         /* Older FW does not have error recovery support */
5267         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5268                 return 0;
5269
5270         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5271
5272         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5273
5274         HWRM_CHECK_RESULT();
5275
5276         flags = rte_le_to_cpu_32(resp->flags);
5277         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5278                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5279         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5280                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5281
5282         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5283             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5284                 rc = -EINVAL;
5285                 goto err;
5286         }
5287
5288         /* FW returned values are in units of 100msec */
5289         info->driver_polling_freq =
5290                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5291         info->master_func_wait_period =
5292                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5293         info->normal_func_wait_period =
5294                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5295         info->master_func_wait_period_after_reset =
5296                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5297         info->max_bailout_time_after_reset =
5298                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5299         info->status_regs[BNXT_FW_STATUS_REG] =
5300                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5301         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5302                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5303         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5304                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5305         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5306                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5307         info->reg_array_cnt =
5308                 rte_le_to_cpu_32(resp->reg_array_cnt);
5309
5310         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5311                 rc = -EINVAL;
5312                 goto err;
5313         }
5314
5315         for (i = 0; i < info->reg_array_cnt; i++) {
5316                 info->reset_reg[i] =
5317                         rte_le_to_cpu_32(resp->reset_reg[i]);
5318                 info->reset_reg_val[i] =
5319                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5320                 info->delay_after_reset[i] =
5321                         resp->delay_after_reset[i];
5322         }
5323 err:
5324         HWRM_UNLOCK();
5325
5326         /* Map the FW status registers */
5327         if (!rc)
5328                 rc = bnxt_map_fw_health_status_regs(bp);
5329
5330         if (rc) {
5331                 rte_free(bp->recovery_info);
5332                 bp->recovery_info = NULL;
5333         }
5334         return rc;
5335 }
5336
5337 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5338 {
5339         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5340         struct hwrm_fw_reset_input req = {0};
5341         int rc;
5342
5343         if (!BNXT_PF(bp))
5344                 return -EOPNOTSUPP;
5345
5346         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5347
5348         req.embedded_proc_type =
5349                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5350         req.selfrst_status =
5351                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5352         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5353
5354         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5355                                     BNXT_USE_KONG(bp));
5356
5357         HWRM_CHECK_RESULT();
5358         HWRM_UNLOCK();
5359
5360         return rc;
5361 }
5362
5363 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5364 {
5365         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5366         struct hwrm_port_ts_query_input req = {0};
5367         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5368         uint32_t flags = 0;
5369         int rc;
5370
5371         if (!ptp)
5372                 return 0;
5373
5374         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5375
5376         switch (path) {
5377         case BNXT_PTP_FLAGS_PATH_TX:
5378                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5379                 break;
5380         case BNXT_PTP_FLAGS_PATH_RX:
5381                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5382                 break;
5383         case BNXT_PTP_FLAGS_CURRENT_TIME:
5384                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5385                 break;
5386         }
5387
5388         req.flags = rte_cpu_to_le_32(flags);
5389         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5390
5391         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5392
5393         HWRM_CHECK_RESULT();
5394
5395         if (timestamp) {
5396                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5397                 *timestamp |=
5398                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5399         }
5400         HWRM_UNLOCK();
5401
5402         return rc;
5403 }
5404
5405 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5406 {
5407         int rc = 0;
5408
5409         struct hwrm_cfa_counter_qcaps_input req = {0};
5410         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5411
5412         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5413                 PMD_DRV_LOG(DEBUG,
5414                             "Not a PF or trusted VF. Command not supported\n");
5415                 return 0;
5416         }
5417
5418         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5419         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5420         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5421
5422         HWRM_CHECK_RESULT();
5423         if (max_fc)
5424                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5425         HWRM_UNLOCK();
5426
5427         return 0;
5428 }
5429
5430 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5431 {
5432         int rc = 0;
5433         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5434         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5435
5436         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5437                 PMD_DRV_LOG(DEBUG,
5438                             "Not a PF or trusted VF. Command not supported\n");
5439                 return 0;
5440         }
5441
5442         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5443
5444         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5445         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5446         req.page_dir = rte_cpu_to_le_64(dma_addr);
5447
5448         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5449
5450         HWRM_CHECK_RESULT();
5451         if (ctx_id) {
5452                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5453                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5454         }
5455         HWRM_UNLOCK();
5456
5457         return 0;
5458 }
5459
5460 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5461 {
5462         int rc = 0;
5463         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5464         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5465
5466         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5467                 PMD_DRV_LOG(DEBUG,
5468                             "Not a PF or trusted VF. Command not supported\n");
5469                 return 0;
5470         }
5471
5472         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5473
5474         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5475
5476         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5477
5478         HWRM_CHECK_RESULT();
5479         HWRM_UNLOCK();
5480
5481         return rc;
5482 }
5483
5484 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5485                               uint16_t cntr, uint16_t ctx_id,
5486                               uint32_t num_entries, bool enable)
5487 {
5488         struct hwrm_cfa_counter_cfg_input req = {0};
5489         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5490         uint16_t flags = 0;
5491         int rc;
5492
5493         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5494                 PMD_DRV_LOG(DEBUG,
5495                             "Not a PF or trusted VF. Command not supported\n");
5496                 return 0;
5497         }
5498
5499         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5500
5501         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5502         req.counter_type = rte_cpu_to_le_16(cntr);
5503         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5504                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5505         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5506         if (dir == BNXT_DIR_RX)
5507                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5508         else if (dir == BNXT_DIR_TX)
5509                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5510         req.flags = rte_cpu_to_le_16(flags);
5511         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5512         req.num_entries = rte_cpu_to_le_32(num_entries);
5513
5514         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5515         HWRM_CHECK_RESULT();
5516         HWRM_UNLOCK();
5517
5518         return 0;
5519 }
5520
5521 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5522                                  enum bnxt_flow_dir dir,
5523                                  uint16_t cntr,
5524                                  uint16_t num_entries)
5525 {
5526         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5527         struct hwrm_cfa_counter_qstats_input req = {0};
5528         uint16_t flow_ctx_id = 0;
5529         uint16_t flags = 0;
5530         int rc = 0;
5531
5532         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5533                 PMD_DRV_LOG(DEBUG,
5534                             "Not a PF or trusted VF. Command not supported\n");
5535                 return 0;
5536         }
5537
5538         if (dir == BNXT_DIR_RX) {
5539                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5540                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5541         } else if (dir == BNXT_DIR_TX) {
5542                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5543                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5544         }
5545
5546         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5547         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5548         req.counter_type = rte_cpu_to_le_16(cntr);
5549         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5550         req.num_entries = rte_cpu_to_le_16(num_entries);
5551         req.flags = rte_cpu_to_le_16(flags);
5552         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5553
5554         HWRM_CHECK_RESULT();
5555         HWRM_UNLOCK();
5556
5557         return 0;
5558 }
5559
5560 int bnxt_hwrm_cfa_vfr_alloc(struct bnxt *bp, uint16_t vf_idx)
5561 {
5562         struct hwrm_cfa_vfr_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5563         struct hwrm_cfa_vfr_alloc_input req = {0};
5564         int rc;
5565
5566         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5567                 PMD_DRV_LOG(DEBUG,
5568                             "Not a PF or trusted VF. Command not supported\n");
5569                 return 0;
5570         }
5571
5572         HWRM_PREP(&req, HWRM_CFA_VFR_ALLOC, BNXT_USE_CHIMP_MB);
5573         req.vf_id = rte_cpu_to_le_16(vf_idx);
5574         snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5575                  bp->eth_dev->data->name, vf_idx);
5576
5577         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5578         HWRM_CHECK_RESULT();
5579
5580         HWRM_UNLOCK();
5581         PMD_DRV_LOG(DEBUG, "VFR %d allocated\n", vf_idx);
5582         return rc;
5583 }
5584
5585 int bnxt_hwrm_cfa_vfr_free(struct bnxt *bp, uint16_t vf_idx)
5586 {
5587         struct hwrm_cfa_vfr_free_output *resp = bp->hwrm_cmd_resp_addr;
5588         struct hwrm_cfa_vfr_free_input req = {0};
5589         int rc;
5590
5591         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5592                 PMD_DRV_LOG(DEBUG,
5593                             "Not a PF or trusted VF. Command not supported\n");
5594                 return 0;
5595         }
5596
5597         HWRM_PREP(&req, HWRM_CFA_VFR_FREE, BNXT_USE_CHIMP_MB);
5598         req.vf_id = rte_cpu_to_le_16(vf_idx);
5599         snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5600                  bp->eth_dev->data->name, vf_idx);
5601
5602         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5603         HWRM_CHECK_RESULT();
5604         HWRM_UNLOCK();
5605         PMD_DRV_LOG(DEBUG, "VFR %d freed\n", vf_idx);
5606         return rc;
5607 }
5608
5609 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5610                                 uint16_t *first_vf_id)
5611 {
5612         int rc = 0;
5613         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5614         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5615
5616         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5617
5618         req.fid = rte_cpu_to_le_16(fid);
5619
5620         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5621
5622         HWRM_CHECK_RESULT();
5623
5624         if (first_vf_id)
5625                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5626
5627         HWRM_UNLOCK();
5628
5629         return rc;
5630 }
5631
5632 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
5633 {
5634         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5635         struct hwrm_cfa_pair_alloc_input req = {0};
5636         int rc;
5637
5638         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5639                 PMD_DRV_LOG(DEBUG,
5640                             "Not a PF or trusted VF. Command not supported\n");
5641                 return 0;
5642         }
5643
5644         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
5645         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5646         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5647                  bp->eth_dev->data->name, rep_bp->vf_id);
5648
5649         req.pf_b_id = rte_cpu_to_le_32(rep_bp->rep_based_pf);
5650         req.vf_b_id = rte_cpu_to_le_16(rep_bp->vf_id);
5651         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
5652         req.host_b_id = 1; /* TBD - Confirm if this is OK */
5653
5654         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
5655                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
5656         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
5657                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
5658         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
5659                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
5660         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
5661                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
5662
5663         req.q_ab = rep_bp->rep_q_r2f;
5664         req.q_ba = rep_bp->rep_q_f2r;
5665         req.fc_ab = rep_bp->rep_fc_r2f;
5666         req.fc_ba = rep_bp->rep_fc_f2r;
5667
5668         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5669         HWRM_CHECK_RESULT();
5670
5671         HWRM_UNLOCK();
5672         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
5673                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
5674         return rc;
5675 }
5676
5677 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
5678 {
5679         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
5680         struct hwrm_cfa_pair_free_input req = {0};
5681         int rc;
5682
5683         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5684                 PMD_DRV_LOG(DEBUG,
5685                             "Not a PF or trusted VF. Command not supported\n");
5686                 return 0;
5687         }
5688
5689         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
5690         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5691                  bp->eth_dev->data->name, rep_bp->vf_id);
5692         req.pf_b_id = rte_cpu_to_le_32(rep_bp->rep_based_pf);
5693         req.vf_id = rte_cpu_to_le_16(rep_bp->vf_id);
5694         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5695
5696         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5697         HWRM_CHECK_RESULT();
5698         HWRM_UNLOCK();
5699         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
5700                     rep_bp->vf_id);
5701         return rc;
5702 }