drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         timeout = bp->hwrm_cmd_timeout;
 104
 105         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 106             msg_len > bp->max_req_len) {
 107                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 108
 109                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 110                 memcpy(short_cmd_req, req, msg_len);
 111
 112                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 113                 short_input.signature = rte_cpu_to_le_16(
 114                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 115                 short_input.size = rte_cpu_to_le_16(msg_len);
 116                 short_input.req_addr =
 117                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 118
 119                 data = (uint32_t *)&short_input;
 120                 msg_len = sizeof(short_input);
 121
 122                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 123         }
 124
 125         /* Write request msg to hwrm channel */
 126         for (i = 0; i < msg_len; i += 4) {
 127                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 128                 rte_write32(*data, bar);
 129                 data++;
 130         }
 131
 132         /* Zero the rest of the request space */
 133         for (; i < max_req_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 135                 rte_write32(0, bar);
 136         }
 137
 138         /* Ring channel doorbell */
 139         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 140         rte_write32(1, bar);
 141         /*
 142          * Make sure the channel doorbell ring command complete before
 143          * reading the response to avoid getting stale or invalid
 144          * responses.
 145          */
 146         rte_io_mb();
 147
 148         /* Poll for the valid bit */
 149         for (i = 0; i < timeout; i++) {
 150                 /* Sanity check on the resp->resp_len */
 151                 rte_cio_rmb();
 152                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 153                         /* Last byte of resp contains the valid key */
 154                         valid = (uint8_t *)resp + resp->resp_len - 1;
 155                         if (*valid == HWRM_RESP_VALID_KEY)
 156                                 break;
 157                 }
 158                 rte_delay_us(1);
 159         }
 160
 161         if (i >= timeout) {
 162                 /* Suppress VER_GET timeout messages during reset recovery */
 163                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 164                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 165                         return -ETIMEDOUT;
 166
 167                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 168                             req->req_type);
 169                 return -ETIMEDOUT;
 170         }
 171         return 0;
 172 }
 173
 174 /*
 175  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 176  * spinlock, and does initial processing.
 177  *
 178  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 179  * releases the spinlock only if it returns. If the regular int return codes
 180  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 181  * directly, rather it should be copied and modified to suit the function.
 182  *
 183  * HWRM_UNLOCK() must be called after all response processing is completed.
 184  */
 185 #define HWRM_PREP(req, type, kong) do { \
 186         rte_spinlock_lock(&bp->hwrm_lock); \
 187         if (bp->hwrm_cmd_resp_addr == NULL) { \
 188                 rte_spinlock_unlock(&bp->hwrm_lock); \
 189                 return -EACCES; \
 190         } \
 191         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 192         (req)->req_type = rte_cpu_to_le_16(type); \
 193         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 194         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 195                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 196         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 197         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 198 } while (0)
 199
 200 #define HWRM_CHECK_RESULT_SILENT() do {\
 201         if (rc) { \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 return rc; \
 204         } \
 205         if (resp->error_code) { \
 206                 rc = rte_le_to_cpu_16(resp->error_code); \
 207                 rte_spinlock_unlock(&bp->hwrm_lock); \
 208                 return rc; \
 209         } \
 210 } while (0)
 211
 212 #define HWRM_CHECK_RESULT() do {\
 213         if (rc) { \
 214                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 215                 rte_spinlock_unlock(&bp->hwrm_lock); \
 216                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 217                         rc = -EACCES; \
 218                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 219                         rc = -ENOSPC; \
 220                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 221                         rc = -EINVAL; \
 222                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 223                         rc = -ENOTSUP; \
 224                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 225                         rc = -EAGAIN; \
 226                 else if (rc > 0) \
 227                         rc = -EIO; \
 228                 return rc; \
 229         } \
 230         if (resp->error_code) { \
 231                 rc = rte_le_to_cpu_16(resp->error_code); \
 232                 if (resp->resp_len >= 16) { \
 233                         struct hwrm_err_output *tmp_hwrm_err_op = \
 234                                                 (void *)resp; \
 235                         PMD_DRV_LOG(ERR, \
 236                                 "error %d:%d:%08x:%04x\n", \
 237                                 rc, tmp_hwrm_err_op->cmd_err, \
 238                                 rte_le_to_cpu_32(\
 239                                         tmp_hwrm_err_op->opaque_0), \
 240                                 rte_le_to_cpu_16(\
 241                                         tmp_hwrm_err_op->opaque_1)); \
 242                 } else { \
 243                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 244                 } \
 245                 rte_spinlock_unlock(&bp->hwrm_lock); \
 246                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 247                         rc = -EACCES; \
 248                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 249                         rc = -ENOSPC; \
 250                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 251                         rc = -EINVAL; \
 252                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 253                         rc = -ENOTSUP; \
 254                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 255                         rc = -EAGAIN; \
 256                 else if (rc > 0) \
 257                         rc = -EIO; \
 258                 return rc; \
 259         } \
 260 } while (0)
 261
 262 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 263
 264 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 265                                 bool use_kong_mb,
 266                                 uint16_t msg_type,
 267                                 void *msg,
 268                                 uint32_t msg_len,
 269                                 void *resp_msg,
 270                                 uint32_t resp_len)
 271 {
 272         int rc = 0;
 273         bool mailbox = BNXT_USE_CHIMP_MB;
 274         struct input *req = msg;
 275         struct output *resp = bp->hwrm_cmd_resp_addr;
 276
 277         if (use_kong_mb)
 278                 mailbox = BNXT_USE_KONG(bp);
 279
 280         HWRM_PREP(req, msg_type, mailbox);
 281
 282         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 283
 284         HWRM_CHECK_RESULT();
 285
 286         if (resp_msg)
 287                 memcpy(resp_msg, resp, resp_len);
 288
 289         HWRM_UNLOCK();
 290
 291         return rc;
 292 }
 293
 294 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 295                                   bool use_kong_mb,
 296                                   uint16_t tf_type,
 297                                   uint16_t tf_subtype,
 298                                   uint32_t *tf_response_code,
 299                                   void *msg,
 300                                   uint32_t msg_len,
 301                                   void *response,
 302                                   uint32_t response_len)
 303 {
 304         int rc = 0;
 305         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 306         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 307         bool mailbox = BNXT_USE_CHIMP_MB;
 308
 309         if (msg_len > sizeof(req.tf_req))
 310                 return -ENOMEM;
 311
 312         if (use_kong_mb)
 313                 mailbox = BNXT_USE_KONG(bp);
 314
 315         HWRM_PREP(&req, HWRM_TF, mailbox);
 316         /* Build request using the user supplied request payload.
 317          * TLV request size is checked at build time against HWRM
 318          * request max size, thus no checking required.
 319          */
 320         req.tf_type = tf_type;
 321         req.tf_subtype = tf_subtype;
 322         memcpy(req.tf_req, msg, msg_len);
 323
 324         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 325         HWRM_CHECK_RESULT();
 326
 327         /* Copy the resp to user provided response buffer */
 328         if (response != NULL)
 329                 /* Post process response data. We need to copy only
 330                  * the 'payload' as the HWRM data structure really is
 331                  * HWRM header + msg header + payload and the TFLIB
 332                  * only provided a payload place holder.
 333                  */
 334                 if (response_len != 0) {
 335                         memcpy(response,
 336                                resp->tf_resp,
 337                                response_len);
 338                 }
 339
 340         /* Extract the internal tflib response code */
 341         *tf_response_code = resp->tf_resp_code;
 342         HWRM_UNLOCK();
 343
 344         return rc;
 345 }
 346
 347 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 348 {
 349         int rc = 0;
 350         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 351         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 352
 353         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 354         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 355         req.mask = 0;
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         return rc;
 363 }
 364
 365 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 366                                  struct bnxt_vnic_info *vnic,
 367                                  uint16_t vlan_count,
 368                                  struct bnxt_vlan_table_entry *vlan_table)
 369 {
 370         int rc = 0;
 371         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 372         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 373         uint32_t mask = 0;
 374
 375         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 376                 return rc;
 377
 378         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 379         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 380
 381         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 382                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 383         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 384                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 385
 386         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 387                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 388
 389         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 390                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 391         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 392                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 393                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 394                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 395         }
 396         if (vlan_table) {
 397                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 398                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 399                 req.vlan_tag_tbl_addr =
 400                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 401                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 402         }
 403         req.mask = rte_cpu_to_le_32(mask);
 404
 405         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 406
 407         HWRM_CHECK_RESULT();
 408         HWRM_UNLOCK();
 409
 410         return rc;
 411 }
 412
 413 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 414                         uint16_t vlan_count,
 415                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 416 {
 417         int rc = 0;
 418         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 419         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 420                                                 bp->hwrm_cmd_resp_addr;
 421
 422         /*
 423          * Older HWRM versions did not support this command, and the set_rx_mask
 424          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 425          * removed from set_rx_mask call, and this command was added.
 426          *
 427          * This command is also present from 1.7.8.11 and higher,
 428          * as well as 1.7.8.0
 429          */
 430         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 431                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 432                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 433                                         (11)))
 434                                 return 0;
 435                 }
 436         }
 437         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 438         req.fid = rte_cpu_to_le_16(fid);
 439
 440         req.vlan_tag_mask_tbl_addr =
 441                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 442         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 443
 444         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 445
 446         HWRM_CHECK_RESULT();
 447         HWRM_UNLOCK();
 448
 449         return rc;
 450 }
 451
 452 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 453                              struct bnxt_filter_info *filter)
 454 {
 455         int rc = 0;
 456         struct bnxt_filter_info *l2_filter = filter;
 457         struct bnxt_vnic_info *vnic = NULL;
 458         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 459         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 460
 461         if (filter->fw_l2_filter_id == UINT64_MAX)
 462                 return 0;
 463
 464         if (filter->matching_l2_fltr_ptr)
 465                 l2_filter = filter->matching_l2_fltr_ptr;
 466
 467         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 468                     filter, l2_filter, l2_filter->l2_ref_cnt);
 469
 470         if (l2_filter->l2_ref_cnt == 0)
 471                 return 0;
 472
 473         if (l2_filter->l2_ref_cnt > 0)
 474                 l2_filter->l2_ref_cnt--;
 475
 476         if (l2_filter->l2_ref_cnt > 0)
 477                 return 0;
 478
 479         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 480
 481         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 482
 483         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 484
 485         HWRM_CHECK_RESULT();
 486         HWRM_UNLOCK();
 487
 488         filter->fw_l2_filter_id = UINT64_MAX;
 489         if (l2_filter->l2_ref_cnt == 0) {
 490                 vnic = l2_filter->vnic;
 491                 if (vnic) {
 492                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 493                                       bnxt_filter_info, next);
 494                         bnxt_free_filter(bp, l2_filter);
 495                 }
 496         }
 497
 498         return 0;
 499 }
 500
 501 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 502                          uint16_t dst_id,
 503                          struct bnxt_filter_info *filter)
 504 {
 505         int rc = 0;
 506         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 507         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 508         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 509         const struct rte_eth_vmdq_rx_conf *conf =
 510                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 511         uint32_t enables = 0;
 512         uint16_t j = dst_id - 1;
 513
 514         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 515         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 516             conf->pool_map[j].pools & (1UL << j)) {
 517                 PMD_DRV_LOG(DEBUG,
 518                         "Add vlan %u to vmdq pool %u\n",
 519                         conf->pool_map[j].vlan_id, j);
 520
 521                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 522                 filter->enables |=
 523                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 524                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 525         }
 526
 527         if (filter->fw_l2_filter_id != UINT64_MAX)
 528                 bnxt_hwrm_clear_l2_filter(bp, filter);
 529
 530         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 531
 532         req.flags = rte_cpu_to_le_32(filter->flags);
 533
 534         enables = filter->enables |
 535               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 536         req.dst_id = rte_cpu_to_le_16(dst_id);
 537
 538         if (enables &
 539             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 540                 memcpy(req.l2_addr, filter->l2_addr,
 541                        RTE_ETHER_ADDR_LEN);
 542         if (enables &
 543             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 544                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 545                        RTE_ETHER_ADDR_LEN);
 546         if (enables &
 547             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 548                 req.l2_ovlan = filter->l2_ovlan;
 549         if (enables &
 550             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 551                 req.l2_ivlan = filter->l2_ivlan;
 552         if (enables &
 553             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 554                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 555         if (enables &
 556             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 557                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 558         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 559                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 560         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 561                 req.src_type = filter->src_type;
 562         if (filter->pri_hint) {
 563                 req.pri_hint = filter->pri_hint;
 564                 req.l2_filter_id_hint =
 565                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 566         }
 567
 568         req.enables = rte_cpu_to_le_32(enables);
 569
 570         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 571
 572         HWRM_CHECK_RESULT();
 573
 574         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 575         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 576         HWRM_UNLOCK();
 577
 578         filter->l2_ref_cnt++;
 579
 580         return rc;
 581 }
 582
 583 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 584 {
 585         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 586         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 587         uint32_t flags = 0;
 588         int rc;
 589
 590         if (!ptp)
 591                 return 0;
 592
 593         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 594
 595         if (ptp->rx_filter)
 596                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 597         else
 598                 flags |=
 599                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 600         if (ptp->tx_tstamp_en)
 601                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 602         else
 603                 flags |=
 604                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 605         req.flags = rte_cpu_to_le_32(flags);
 606         req.enables = rte_cpu_to_le_32
 607                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 608         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 609
 610         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 611         HWRM_UNLOCK();
 612
 613         return rc;
 614 }
 615
 616 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 617 {
 618         int rc = 0;
 619         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 620         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 621         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 622
 623         if (ptp)
 624                 return 0;
 625
 626         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 627
 628         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 629
 630         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 631
 632         HWRM_CHECK_RESULT();
 633
 634         if (!BNXT_CHIP_THOR(bp) &&
 635             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 636                 return 0;
 637
 638         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 639                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 640
 641         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 642         if (!ptp)
 643                 return -ENOMEM;
 644
 645         if (!BNXT_CHIP_THOR(bp)) {
 646                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 647                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 648                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 649                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 650                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 651                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 652                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 653                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 654                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 655                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 656                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 657                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 658                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 659                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 660                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 661                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 662                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 663                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 664         }
 665
 666         ptp->bp = bp;
 667         bp->ptp_cfg = ptp;
 668
 669         return 0;
 670 }
 671
 672 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 673 {
 674         int rc = 0;
 675         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 676         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 677         uint16_t new_max_vfs;
 678         uint32_t flags;
 679         int i;
 680
 681         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 682
 683         req.fid = rte_cpu_to_le_16(0xffff);
 684
 685         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 686
 687         HWRM_CHECK_RESULT();
 688
 689         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 690         flags = rte_le_to_cpu_32(resp->flags);
 691         if (BNXT_PF(bp)) {
 692                 bp->pf.port_id = resp->port_id;
 693                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 694                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 695                 new_max_vfs = bp->pdev->max_vfs;
 696                 if (new_max_vfs != bp->pf.max_vfs) {
 697                         if (bp->pf.vf_info)
 698                                 rte_free(bp->pf.vf_info);
 699                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 700                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 701                         bp->pf.max_vfs = new_max_vfs;
 702                         for (i = 0; i < new_max_vfs; i++) {
 703                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 704                                 bp->pf.vf_info[i].vlan_table =
 705                                         rte_zmalloc("VF VLAN table",
 706                                                     getpagesize(),
 707                                                     getpagesize());
 708                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 709                                         PMD_DRV_LOG(ERR,
 710                                         "Fail to alloc VLAN table for VF %d\n",
 711                                         i);
 712                                 else
 713                                         rte_mem_lock_page(
 714                                                 bp->pf.vf_info[i].vlan_table);
 715                                 bp->pf.vf_info[i].vlan_as_table =
 716                                         rte_zmalloc("VF VLAN AS table",
 717                                                     getpagesize(),
 718                                                     getpagesize());
 719                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 720                                         PMD_DRV_LOG(ERR,
 721                                         "Alloc VLAN AS table for VF %d fail\n",
 722                                         i);
 723                                 else
 724                                         rte_mem_lock_page(
 725                                                bp->pf.vf_info[i].vlan_as_table);
 726                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 727                         }
 728                 }
 729         }
 730
 731         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 732         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 733         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 734         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 735         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 736         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 737         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 738         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 739         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 740         if (!BNXT_CHIP_THOR(bp))
 741                 bp->max_l2_ctx += bp->max_rx_em_flows;
 742         /* TODO: For now, do not support VMDq/RFS on VFs. */
 743         if (BNXT_PF(bp)) {
 744                 if (bp->pf.max_vfs)
 745                         bp->max_vnics = 1;
 746                 else
 747                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 748         } else {
 749                 bp->max_vnics = 1;
 750         }
 751         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 752                     bp->max_l2_ctx, bp->max_vnics);
 753         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 754         if (BNXT_PF(bp)) {
 755                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 756                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 757                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 758                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 759                         HWRM_UNLOCK();
 760                         bnxt_hwrm_ptp_qcfg(bp);
 761                 }
 762         }
 763
 764         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 765                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 766
 767         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 768                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 769                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 770         }
 771
 772         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 773                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 774
 775         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 776                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 777
 778         HWRM_UNLOCK();
 779
 780         return rc;
 781 }
 782
 783 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 784 {
 785         int rc;
 786
 787         rc = __bnxt_hwrm_func_qcaps(bp);
 788         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 789                 rc = bnxt_alloc_ctx_mem(bp);
 790                 if (rc)
 791                         return rc;
 792
 793                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 794                 if (!rc)
 795                         bp->flags |= BNXT_FLAG_NEW_RM;
 796         }
 797
 798         /* On older FW,
 799          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 800          * But the error can be ignored. Return success.
 801          */
 802
 803         return 0;
 804 }
 805
 806 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 807 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 808 {
 809         int rc = 0;
 810         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 811         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 812
 813         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 814
 815         req.target_id = rte_cpu_to_le_16(0xffff);
 816
 817         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 818
 819         HWRM_CHECK_RESULT();
 820
 821         if (rte_le_to_cpu_32(resp->flags) &
 822             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 823                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 824                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 825         }
 826
 827         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 828
 829         HWRM_UNLOCK();
 830
 831         return rc;
 832 }
 833
 834 int bnxt_hwrm_func_reset(struct bnxt *bp)
 835 {
 836         int rc = 0;
 837         struct hwrm_func_reset_input req = {.req_type = 0 };
 838         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 839
 840         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
 841
 842         req.enables = rte_cpu_to_le_32(0);
 843
 844         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 845
 846         HWRM_CHECK_RESULT();
 847         HWRM_UNLOCK();
 848
 849         return rc;
 850 }
 851
 852 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 853 {
 854         int rc;
 855         uint32_t flags = 0;
 856         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 857         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 858
 859         if (bp->flags & BNXT_FLAG_REGISTERED)
 860                 return 0;
 861
 862         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 863                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 864         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 865                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 866
 867         /* PFs and trusted VFs should indicate the support of the
 868          * Master capability on non Stingray platform
 869          */
 870         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 871                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 872
 873         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 874         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 875                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 876         req.ver_maj = RTE_VER_YEAR;
 877         req.ver_min = RTE_VER_MONTH;
 878         req.ver_upd = RTE_VER_MINOR;
 879
 880         if (BNXT_PF(bp)) {
 881                 req.enables |= rte_cpu_to_le_32(
 882                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 883                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 884                        RTE_MIN(sizeof(req.vf_req_fwd),
 885                                sizeof(bp->pf.vf_req_fwd)));
 886
 887                 /*
 888                  * PF can sniff HWRM API issued by VF. This can be set up by
 889                  * linux driver and inherited by the DPDK PF driver. Clear
 890                  * this HWRM sniffer list in FW because DPDK PF driver does
 891                  * not support this.
 892                  */
 893                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 894         }
 895
 896         req.flags = rte_cpu_to_le_32(flags);
 897
 898         req.async_event_fwd[0] |=
 899                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 900                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 901                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 902                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 903                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 904         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 905                 req.async_event_fwd[0] |=
 906                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 907         req.async_event_fwd[1] |=
 908                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 909                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 910         if (BNXT_PF(bp))
 911                 req.async_event_fwd[1] |=
 912                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 913
 914         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 915
 916         HWRM_CHECK_RESULT();
 917
 918         flags = rte_le_to_cpu_32(resp->flags);
 919         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 920                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 921
 922         HWRM_UNLOCK();
 923
 924         bp->flags |= BNXT_FLAG_REGISTERED;
 925
 926         return rc;
 927 }
 928
 929 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 930 {
 931         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 932                 return 0;
 933
 934         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 935 }
 936
 937 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 938 {
 939         int rc;
 940         uint32_t flags = 0;
 941         uint32_t enables;
 942         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 943         struct hwrm_func_vf_cfg_input req = {0};
 944
 945         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 946
 947         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 948                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 949                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 950                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 951                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 952
 953         if (BNXT_HAS_RING_GRPS(bp)) {
 954                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 955                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 956         }
 957
 958         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 959         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 960                                             AGG_RING_MULTIPLIER);
 961         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 962         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 963                                               bp->tx_nr_rings +
 964                                               BNXT_NUM_ASYNC_CPR(bp));
 965         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 966         if (bp->vf_resv_strategy ==
 967             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 968                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 969                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 970                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 971                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 972                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 973                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 974         } else if (bp->vf_resv_strategy ==
 975                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 976                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 977                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 978         }
 979
 980         if (test)
 981                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 982                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 983                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 984                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 985                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 986                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 987
 988         if (test && BNXT_HAS_RING_GRPS(bp))
 989                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 990
 991         req.flags = rte_cpu_to_le_32(flags);
 992         req.enables |= rte_cpu_to_le_32(enables);
 993
 994         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 995
 996         if (test)
 997                 HWRM_CHECK_RESULT_SILENT();
 998         else
 999                 HWRM_CHECK_RESULT();
1000
1001         HWRM_UNLOCK();
1002         return rc;
1003 }
1004
1005 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1006 {
1007         int rc;
1008         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1009         struct hwrm_func_resource_qcaps_input req = {0};
1010
1011         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1012         req.fid = rte_cpu_to_le_16(0xffff);
1013
1014         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1015
1016         HWRM_CHECK_RESULT_SILENT();
1017
1018         if (BNXT_VF(bp)) {
1019                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1020                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1021                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1022                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1023                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1024                 /* func_resource_qcaps does not return max_rx_em_flows.
1025                  * So use the value provided by func_qcaps.
1026                  */
1027                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1028                 if (!BNXT_CHIP_THOR(bp))
1029                         bp->max_l2_ctx += bp->max_rx_em_flows;
1030                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1031                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1032         }
1033         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1034         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1035         if (bp->vf_resv_strategy >
1036             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1037                 bp->vf_resv_strategy =
1038                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1039
1040         HWRM_UNLOCK();
1041         return rc;
1042 }
1043
1044 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1045 {
1046         int rc = 0;
1047         struct hwrm_ver_get_input req = {.req_type = 0 };
1048         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1049         uint32_t fw_version;
1050         uint16_t max_resp_len;
1051         char type[RTE_MEMZONE_NAMESIZE];
1052         uint32_t dev_caps_cfg;
1053
1054         bp->max_req_len = HWRM_MAX_REQ_LEN;
1055         bp->hwrm_cmd_timeout = timeout;
1056         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1057
1058         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1059         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1060         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1061
1062         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1063
1064         if (bp->flags & BNXT_FLAG_FW_RESET)
1065                 HWRM_CHECK_RESULT_SILENT();
1066         else
1067                 HWRM_CHECK_RESULT();
1068
1069         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1070                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1071                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1072                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1073         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1074                      (resp->hwrm_fw_min_8b << 16) |
1075                      (resp->hwrm_fw_bld_8b << 8) |
1076                      resp->hwrm_fw_rsvd_8b;
1077         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1078                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1079
1080         fw_version = resp->hwrm_intf_maj_8b << 16;
1081         fw_version |= resp->hwrm_intf_min_8b << 8;
1082         fw_version |= resp->hwrm_intf_upd_8b;
1083         bp->hwrm_spec_code = fw_version;
1084
1085         /* def_req_timeout value is in milliseconds */
1086         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1087         /* convert timeout to usec */
1088         bp->hwrm_cmd_timeout *= 1000;
1089         if (!bp->hwrm_cmd_timeout)
1090                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1091
1092         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1093                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1094                 rc = -EINVAL;
1095                 goto error;
1096         }
1097
1098         if (bp->max_req_len > resp->max_req_win_len) {
1099                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1100                 rc = -EINVAL;
1101         }
1102         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1103         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1104         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1105                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1106
1107         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1108         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1109
1110         if (bp->max_resp_len != max_resp_len) {
1111                 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1112                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1113                         bp->pdev->addr.devid, bp->pdev->addr.function);
1114
1115                 rte_free(bp->hwrm_cmd_resp_addr);
1116
1117                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1118                 if (bp->hwrm_cmd_resp_addr == NULL) {
1119                         rc = -ENOMEM;
1120                         goto error;
1121                 }
1122                 bp->hwrm_cmd_resp_dma_addr =
1123                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1124                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1125                         PMD_DRV_LOG(ERR,
1126                         "Unable to map response buffer to physical memory.\n");
1127                         rc = -ENOMEM;
1128                         goto error;
1129                 }
1130                 bp->max_resp_len = max_resp_len;
1131         }
1132
1133         if ((dev_caps_cfg &
1134                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1135             (dev_caps_cfg &
1136              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1137                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1138                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1139         }
1140
1141         if (((dev_caps_cfg &
1142               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1143              (dev_caps_cfg &
1144               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1145             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1146                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1147                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1148                         bp->pdev->addr.devid, bp->pdev->addr.function);
1149
1150                 rte_free(bp->hwrm_short_cmd_req_addr);
1151
1152                 bp->hwrm_short_cmd_req_addr =
1153                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1154                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1155                         rc = -ENOMEM;
1156                         goto error;
1157                 }
1158                 bp->hwrm_short_cmd_req_dma_addr =
1159                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1160                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1161                         rte_free(bp->hwrm_short_cmd_req_addr);
1162                         PMD_DRV_LOG(ERR,
1163                                 "Unable to map buffer to physical memory.\n");
1164                         rc = -ENOMEM;
1165                         goto error;
1166                 }
1167         }
1168         if (dev_caps_cfg &
1169             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1170                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1171                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1172         }
1173         if (dev_caps_cfg &
1174             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1175                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1176         if (dev_caps_cfg &
1177             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1178                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1179                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1180         }
1181
1182         if (dev_caps_cfg &
1183             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1184                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1185                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1186         }
1187
1188
1189 error:
1190         HWRM_UNLOCK();
1191         return rc;
1192 }
1193
1194 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1195 {
1196         int rc;
1197         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1198         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1199
1200         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1201                 return 0;
1202
1203         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1204         req.flags = flags;
1205
1206         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1207
1208         HWRM_CHECK_RESULT();
1209         HWRM_UNLOCK();
1210
1211         return rc;
1212 }
1213
1214 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1215 {
1216         int rc = 0;
1217         struct hwrm_port_phy_cfg_input req = {0};
1218         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1219         uint32_t enables = 0;
1220
1221         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1222
1223         if (conf->link_up) {
1224                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1225                 if (bp->link_info.auto_mode && conf->link_speed) {
1226                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1227                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1228                 }
1229
1230                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1231                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1232                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1233                 /*
1234                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1235                  * any auto mode, even "none".
1236                  */
1237                 if (!conf->link_speed) {
1238                         /* No speeds specified. Enable AutoNeg - all speeds */
1239                         req.auto_mode =
1240                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1241                 }
1242                 /* AutoNeg - Advertise speeds specified. */
1243                 if (conf->auto_link_speed_mask &&
1244                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1245                         req.auto_mode =
1246                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1247                         req.auto_link_speed_mask =
1248                                 conf->auto_link_speed_mask;
1249                         enables |=
1250                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1251                 }
1252
1253                 req.auto_duplex = conf->duplex;
1254                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1255                 req.auto_pause = conf->auto_pause;
1256                 req.force_pause = conf->force_pause;
1257                 /* Set force_pause if there is no auto or if there is a force */
1258                 if (req.auto_pause && !req.force_pause)
1259                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1260                 else
1261                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1262
1263                 req.enables = rte_cpu_to_le_32(enables);
1264         } else {
1265                 req.flags =
1266                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1267                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1268         }
1269
1270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1271
1272         HWRM_CHECK_RESULT();
1273         HWRM_UNLOCK();
1274
1275         return rc;
1276 }
1277
1278 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1279                                    struct bnxt_link_info *link_info)
1280 {
1281         int rc = 0;
1282         struct hwrm_port_phy_qcfg_input req = {0};
1283         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1284
1285         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1286
1287         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1288
1289         HWRM_CHECK_RESULT();
1290
1291         link_info->phy_link_status = resp->link;
1292         link_info->link_up =
1293                 (link_info->phy_link_status ==
1294                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1295         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1296         link_info->duplex = resp->duplex_cfg;
1297         link_info->pause = resp->pause;
1298         link_info->auto_pause = resp->auto_pause;
1299         link_info->force_pause = resp->force_pause;
1300         link_info->auto_mode = resp->auto_mode;
1301         link_info->phy_type = resp->phy_type;
1302         link_info->media_type = resp->media_type;
1303
1304         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1305         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1306         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1307         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1308         link_info->phy_ver[0] = resp->phy_maj;
1309         link_info->phy_ver[1] = resp->phy_min;
1310         link_info->phy_ver[2] = resp->phy_bld;
1311
1312         HWRM_UNLOCK();
1313
1314         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1315         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1316         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1317         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1318         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1319                     link_info->auto_link_speed_mask);
1320         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1321                     link_info->force_link_speed);
1322
1323         return rc;
1324 }
1325
1326 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1327 {
1328         int i = 0;
1329
1330         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1331                 if (bp->tx_cos_queue[i].profile ==
1332                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1333                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1334                         return true;
1335                 }
1336         }
1337         return false;
1338 }
1339
1340 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1341 {
1342         int i = 0;
1343
1344         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1345                 if (bp->tx_cos_queue[i].profile !=
1346                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1347                     bp->tx_cos_queue[i].id !=
1348                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1349                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1350                         break;
1351                 }
1352         }
1353 }
1354
1355 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1356 {
1357         int rc = 0;
1358         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1359         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1360         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1361         int i;
1362
1363 get_rx_info:
1364         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1365
1366         req.flags = rte_cpu_to_le_32(dir);
1367         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1368         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1369             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1370                 req.drv_qmap_cap =
1371                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1372         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1373
1374         HWRM_CHECK_RESULT();
1375
1376         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1377                 GET_TX_QUEUE_INFO(0);
1378                 GET_TX_QUEUE_INFO(1);
1379                 GET_TX_QUEUE_INFO(2);
1380                 GET_TX_QUEUE_INFO(3);
1381                 GET_TX_QUEUE_INFO(4);
1382                 GET_TX_QUEUE_INFO(5);
1383                 GET_TX_QUEUE_INFO(6);
1384                 GET_TX_QUEUE_INFO(7);
1385         } else  {
1386                 GET_RX_QUEUE_INFO(0);
1387                 GET_RX_QUEUE_INFO(1);
1388                 GET_RX_QUEUE_INFO(2);
1389                 GET_RX_QUEUE_INFO(3);
1390                 GET_RX_QUEUE_INFO(4);
1391                 GET_RX_QUEUE_INFO(5);
1392                 GET_RX_QUEUE_INFO(6);
1393                 GET_RX_QUEUE_INFO(7);
1394         }
1395
1396         HWRM_UNLOCK();
1397
1398         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1399                 goto done;
1400
1401         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1402                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1403         } else {
1404                 int j;
1405
1406                 /* iterate and find the COSq profile to use for Tx */
1407                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1408                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1409                                 if (bp->tx_cos_queue[i].id != 0xff)
1410                                         bp->tx_cosq_id[j++] =
1411                                                 bp->tx_cos_queue[i].id;
1412                         }
1413                 } else {
1414                         /* When CoS classification is disabled, for normal NIC
1415                          * operations, ideally we should look to use LOSSY.
1416                          * If not found, fallback to the first valid profile
1417                          */
1418                         if (!bnxt_find_lossy_profile(bp))
1419                                 bnxt_find_first_valid_profile(bp);
1420
1421                 }
1422         }
1423
1424         bp->max_tc = resp->max_configurable_queues;
1425         bp->max_lltc = resp->max_configurable_lossless_queues;
1426         if (bp->max_tc > BNXT_MAX_QUEUE)
1427                 bp->max_tc = BNXT_MAX_QUEUE;
1428         bp->max_q = bp->max_tc;
1429
1430         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1431                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1432                 goto get_rx_info;
1433         }
1434
1435 done:
1436         return rc;
1437 }
1438
1439 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1440                          struct bnxt_ring *ring,
1441                          uint32_t ring_type, uint32_t map_index,
1442                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1443                          uint16_t tx_cosq_id)
1444 {
1445         int rc = 0;
1446         uint32_t enables = 0;
1447         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1448         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1449         struct rte_mempool *mb_pool;
1450         uint16_t rx_buf_size;
1451
1452         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1453
1454         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1455         req.fbo = rte_cpu_to_le_32(0);
1456         /* Association of ring index with doorbell index */
1457         req.logical_id = rte_cpu_to_le_16(map_index);
1458         req.length = rte_cpu_to_le_32(ring->ring_size);
1459
1460         switch (ring_type) {
1461         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1462                 req.ring_type = ring_type;
1463                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1464                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1465                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1466                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1467                         enables |=
1468                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1469                 break;
1470         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1471                 req.ring_type = ring_type;
1472                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1473                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1474                 if (BNXT_CHIP_THOR(bp)) {
1475                         mb_pool = bp->rx_queues[0]->mb_pool;
1476                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1477                                       RTE_PKTMBUF_HEADROOM;
1478                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1479                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1480                         enables |=
1481                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1482                 }
1483                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1484                         enables |=
1485                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1486                 break;
1487         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1488                 req.ring_type = ring_type;
1489                 if (BNXT_HAS_NQ(bp)) {
1490                         /* Association of cp ring with nq */
1491                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1492                         enables |=
1493                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1494                 }
1495                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1496                 break;
1497         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1498                 req.ring_type = ring_type;
1499                 req.page_size = BNXT_PAGE_SHFT;
1500                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1501                 break;
1502         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1503                 req.ring_type = ring_type;
1504                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1505
1506                 mb_pool = bp->rx_queues[0]->mb_pool;
1507                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1508                               RTE_PKTMBUF_HEADROOM;
1509                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1510                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1511
1512                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1513                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1514                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1515                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1516                 break;
1517         default:
1518                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1519                         ring_type);
1520                 HWRM_UNLOCK();
1521                 return -EINVAL;
1522         }
1523         req.enables = rte_cpu_to_le_32(enables);
1524
1525         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1526
1527         if (rc || resp->error_code) {
1528                 if (rc == 0 && resp->error_code)
1529                         rc = rte_le_to_cpu_16(resp->error_code);
1530                 switch (ring_type) {
1531                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1532                         PMD_DRV_LOG(ERR,
1533                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1534                         HWRM_UNLOCK();
1535                         return rc;
1536                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1537                         PMD_DRV_LOG(ERR,
1538                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1539                         HWRM_UNLOCK();
1540                         return rc;
1541                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1542                         PMD_DRV_LOG(ERR,
1543                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1544                                     rc);
1545                         HWRM_UNLOCK();
1546                         return rc;
1547                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1548                         PMD_DRV_LOG(ERR,
1549                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1550                         HWRM_UNLOCK();
1551                         return rc;
1552                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1553                         PMD_DRV_LOG(ERR,
1554                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1555                         HWRM_UNLOCK();
1556                         return rc;
1557                 default:
1558                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1559                         HWRM_UNLOCK();
1560                         return rc;
1561                 }
1562         }
1563
1564         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1565         HWRM_UNLOCK();
1566         return rc;
1567 }
1568
1569 int bnxt_hwrm_ring_free(struct bnxt *bp,
1570                         struct bnxt_ring *ring, uint32_t ring_type)
1571 {
1572         int rc;
1573         struct hwrm_ring_free_input req = {.req_type = 0 };
1574         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1575
1576         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1577
1578         req.ring_type = ring_type;
1579         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1580
1581         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1582
1583         if (rc || resp->error_code) {
1584                 if (rc == 0 && resp->error_code)
1585                         rc = rte_le_to_cpu_16(resp->error_code);
1586                 HWRM_UNLOCK();
1587
1588                 switch (ring_type) {
1589                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1590                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1591                                 rc);
1592                         return rc;
1593                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1594                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1595                                 rc);
1596                         return rc;
1597                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1598                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1599                                 rc);
1600                         return rc;
1601                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1602                         PMD_DRV_LOG(ERR,
1603                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1604                         return rc;
1605                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1606                         PMD_DRV_LOG(ERR,
1607                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1608                         return rc;
1609                 default:
1610                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1611                         return rc;
1612                 }
1613         }
1614         HWRM_UNLOCK();
1615         return 0;
1616 }
1617
1618 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1619 {
1620         int rc = 0;
1621         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1622         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1623
1624         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1625
1626         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1627         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1628         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1629         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1630
1631         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1632
1633         HWRM_CHECK_RESULT();
1634
1635         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1636
1637         HWRM_UNLOCK();
1638
1639         return rc;
1640 }
1641
1642 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1643 {
1644         int rc;
1645         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1646         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1647
1648         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1649
1650         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1651
1652         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1653
1654         HWRM_CHECK_RESULT();
1655         HWRM_UNLOCK();
1656
1657         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1658         return rc;
1659 }
1660
1661 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1662 {
1663         int rc = 0;
1664         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1665         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1666
1667         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1668                 return rc;
1669
1670         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1671
1672         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1673
1674         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1675
1676         HWRM_CHECK_RESULT();
1677         HWRM_UNLOCK();
1678
1679         return rc;
1680 }
1681
1682 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1683                                 unsigned int idx __rte_unused)
1684 {
1685         int rc;
1686         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1687         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1688
1689         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1690
1691         req.update_period_ms = rte_cpu_to_le_32(0);
1692
1693         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1694
1695         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1696
1697         HWRM_CHECK_RESULT();
1698
1699         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1700
1701         HWRM_UNLOCK();
1702
1703         return rc;
1704 }
1705
1706 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1707                                 unsigned int idx __rte_unused)
1708 {
1709         int rc;
1710         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1711         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1712
1713         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1714
1715         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1716
1717         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1718
1719         HWRM_CHECK_RESULT();
1720         HWRM_UNLOCK();
1721
1722         return rc;
1723 }
1724
1725 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1726 {
1727         int rc = 0, i, j;
1728         struct hwrm_vnic_alloc_input req = { 0 };
1729         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1730
1731         if (!BNXT_HAS_RING_GRPS(bp))
1732                 goto skip_ring_grps;
1733
1734         /* map ring groups to this vnic */
1735         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1736                 vnic->start_grp_id, vnic->end_grp_id);
1737         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1738                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1739
1740         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1741         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1742         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1743         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1744
1745 skip_ring_grps:
1746         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1747         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1748
1749         if (vnic->func_default)
1750                 req.flags =
1751                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1752         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1753
1754         HWRM_CHECK_RESULT();
1755
1756         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1757         HWRM_UNLOCK();
1758         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1759         return rc;
1760 }
1761
1762 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1763                                         struct bnxt_vnic_info *vnic,
1764                                         struct bnxt_plcmodes_cfg *pmode)
1765 {
1766         int rc = 0;
1767         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1768         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1769
1770         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1771
1772         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1773
1774         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1775
1776         HWRM_CHECK_RESULT();
1777
1778         pmode->flags = rte_le_to_cpu_32(resp->flags);
1779         /* dflt_vnic bit doesn't exist in the _cfg command */
1780         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1781         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1782         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1783         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1784
1785         HWRM_UNLOCK();
1786
1787         return rc;
1788 }
1789
1790 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1791                                        struct bnxt_vnic_info *vnic,
1792                                        struct bnxt_plcmodes_cfg *pmode)
1793 {
1794         int rc = 0;
1795         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1796         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1797
1798         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1799                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1800                 return rc;
1801         }
1802
1803         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1804
1805         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1806         req.flags = rte_cpu_to_le_32(pmode->flags);
1807         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1808         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1809         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1810         req.enables = rte_cpu_to_le_32(
1811             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1812             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1813             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1814         );
1815
1816         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1817
1818         HWRM_CHECK_RESULT();
1819         HWRM_UNLOCK();
1820
1821         return rc;
1822 }
1823
1824 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1825 {
1826         int rc = 0;
1827         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1828         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1829         struct bnxt_plcmodes_cfg pmodes = { 0 };
1830         uint32_t ctx_enable_flag = 0;
1831         uint32_t enables = 0;
1832
1833         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1834                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1835                 return rc;
1836         }
1837
1838         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1839         if (rc)
1840                 return rc;
1841
1842         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1843
1844         if (BNXT_CHIP_THOR(bp)) {
1845                 int dflt_rxq = vnic->start_grp_id;
1846                 struct bnxt_rx_ring_info *rxr;
1847                 struct bnxt_cp_ring_info *cpr;
1848                 struct bnxt_rx_queue *rxq;
1849                 int i;
1850
1851                 /*
1852                  * The first active receive ring is used as the VNIC
1853                  * default receive ring. If there are no active receive
1854                  * rings (all corresponding receive queues are stopped),
1855                  * the first receive ring is used.
1856                  */
1857                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1858                         rxq = bp->eth_dev->data->rx_queues[i];
1859                         if (rxq->rx_started) {
1860                                 dflt_rxq = i;
1861                                 break;
1862                         }
1863                 }
1864
1865                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1866                 rxr = rxq->rx_ring;
1867                 cpr = rxq->cp_ring;
1868
1869                 req.default_rx_ring_id =
1870                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1871                 req.default_cmpl_ring_id =
1872                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1873                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1874                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1875                 goto config_mru;
1876         }
1877
1878         /* Only RSS support for now TBD: COS & LB */
1879         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1880         if (vnic->lb_rule != 0xffff)
1881                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1882         if (vnic->cos_rule != 0xffff)
1883                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1884         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1885                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1886                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1887         }
1888         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1889                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1890                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1891         }
1892
1893         enables |= ctx_enable_flag;
1894         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1895         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1896         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1897         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1898
1899 config_mru:
1900         req.enables = rte_cpu_to_le_32(enables);
1901         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1902         req.mru = rte_cpu_to_le_16(vnic->mru);
1903         /* Configure default VNIC only once. */
1904         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1905                 req.flags |=
1906                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1907                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1908         }
1909         if (vnic->vlan_strip)
1910                 req.flags |=
1911                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1912         if (vnic->bd_stall)
1913                 req.flags |=
1914                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1915         if (vnic->roce_dual)
1916                 req.flags |= rte_cpu_to_le_32(
1917                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1918         if (vnic->roce_only)
1919                 req.flags |= rte_cpu_to_le_32(
1920                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1921         if (vnic->rss_dflt_cr)
1922                 req.flags |= rte_cpu_to_le_32(
1923                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1924
1925         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1926
1927         HWRM_CHECK_RESULT();
1928         HWRM_UNLOCK();
1929
1930         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1931
1932         return rc;
1933 }
1934
1935 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1936                 int16_t fw_vf_id)
1937 {
1938         int rc = 0;
1939         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1940         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1941
1942         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1943                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1944                 return rc;
1945         }
1946         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
1947
1948         req.enables =
1949                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1950         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1951         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1952
1953         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1954
1955         HWRM_CHECK_RESULT();
1956
1957         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1958         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1959         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1960         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1961         vnic->mru = rte_le_to_cpu_16(resp->mru);
1962         vnic->func_default = rte_le_to_cpu_32(
1963                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1964         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1965                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1966         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1967                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1968         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1969                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1970         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1971                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1972         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1973                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1974
1975         HWRM_UNLOCK();
1976
1977         return rc;
1978 }
1979
1980 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1981                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1982 {
1983         int rc = 0;
1984         uint16_t ctx_id;
1985         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1986         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1987                                                 bp->hwrm_cmd_resp_addr;
1988
1989         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1990
1991         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1992         HWRM_CHECK_RESULT();
1993
1994         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1995         if (!BNXT_HAS_RING_GRPS(bp))
1996                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1997         else if (ctx_idx == 0)
1998                 vnic->rss_rule = ctx_id;
1999
2000         HWRM_UNLOCK();
2001
2002         return rc;
2003 }
2004
2005 static
2006 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2007                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2008 {
2009         int rc = 0;
2010         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2011         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2012                                                 bp->hwrm_cmd_resp_addr;
2013
2014         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2015                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2016                 return rc;
2017         }
2018         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2019
2020         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2021
2022         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2023
2024         HWRM_CHECK_RESULT();
2025         HWRM_UNLOCK();
2026
2027         return rc;
2028 }
2029
2030 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2031 {
2032         int rc = 0;
2033
2034         if (BNXT_CHIP_THOR(bp)) {
2035                 int j;
2036
2037                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2038                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2039                                                       vnic,
2040                                                       vnic->fw_grp_ids[j]);
2041                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2042                 }
2043                 vnic->num_lb_ctxts = 0;
2044         } else {
2045                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2046                 vnic->rss_rule = INVALID_HW_RING_ID;
2047         }
2048
2049         return rc;
2050 }
2051
2052 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2053 {
2054         int rc = 0;
2055         struct hwrm_vnic_free_input req = {.req_type = 0 };
2056         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2057
2058         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2059                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2060                 return rc;
2061         }
2062
2063         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2064
2065         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2066
2067         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2068
2069         HWRM_CHECK_RESULT();
2070         HWRM_UNLOCK();
2071
2072         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2073         /* Configure default VNIC again if necessary. */
2074         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2075                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2076
2077         return rc;
2078 }
2079
2080 static int
2081 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2082 {
2083         int i;
2084         int rc = 0;
2085         int nr_ctxs = vnic->num_lb_ctxts;
2086         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2087         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2088
2089         for (i = 0; i < nr_ctxs; i++) {
2090                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2091
2092                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2093                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2094                 req.hash_mode_flags = vnic->hash_mode;
2095
2096                 req.hash_key_tbl_addr =
2097                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2098
2099                 req.ring_grp_tbl_addr =
2100                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2101                                          i * HW_HASH_INDEX_SIZE);
2102                 req.ring_table_pair_index = i;
2103                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2104
2105                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2106                                             BNXT_USE_CHIMP_MB);
2107
2108                 HWRM_CHECK_RESULT();
2109                 HWRM_UNLOCK();
2110         }
2111
2112         return rc;
2113 }
2114
2115 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2116                            struct bnxt_vnic_info *vnic)
2117 {
2118         int rc = 0;
2119         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2120         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2121
2122         if (!vnic->rss_table)
2123                 return 0;
2124
2125         if (BNXT_CHIP_THOR(bp))
2126                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2127
2128         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2129
2130         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2131         req.hash_mode_flags = vnic->hash_mode;
2132
2133         req.ring_grp_tbl_addr =
2134             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2135         req.hash_key_tbl_addr =
2136             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2137         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2138         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2139
2140         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2141
2142         HWRM_CHECK_RESULT();
2143         HWRM_UNLOCK();
2144
2145         return rc;
2146 }
2147
2148 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2149                         struct bnxt_vnic_info *vnic)
2150 {
2151         int rc = 0;
2152         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2153         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2154         uint16_t size;
2155
2156         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2157                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2158                 return rc;
2159         }
2160
2161         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2162
2163         req.flags = rte_cpu_to_le_32(
2164                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2165
2166         req.enables = rte_cpu_to_le_32(
2167                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2168
2169         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2170         size -= RTE_PKTMBUF_HEADROOM;
2171         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2172
2173         req.jumbo_thresh = rte_cpu_to_le_16(size);
2174         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2175
2176         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2177
2178         HWRM_CHECK_RESULT();
2179         HWRM_UNLOCK();
2180
2181         return rc;
2182 }
2183
2184 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2185                         struct bnxt_vnic_info *vnic, bool enable)
2186 {
2187         int rc = 0;
2188         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2189         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2190
2191         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2192                 if (enable)
2193                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2194                 return -ENOTSUP;
2195         }
2196
2197         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2198                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2199                 return 0;
2200         }
2201
2202         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2203
2204         if (enable) {
2205                 req.enables = rte_cpu_to_le_32(
2206                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2207                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2208                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2209                 req.flags = rte_cpu_to_le_32(
2210                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2211                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2212                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2213                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2214                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2215                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2216                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2217                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2218                 req.min_agg_len = rte_cpu_to_le_32(512);
2219         }
2220         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2221
2222         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2223
2224         HWRM_CHECK_RESULT();
2225         HWRM_UNLOCK();
2226
2227         return rc;
2228 }
2229
2230 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2231 {
2232         struct hwrm_func_cfg_input req = {0};
2233         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2234         int rc;
2235
2236         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2237         req.enables = rte_cpu_to_le_32(
2238                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2239         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2240         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2241
2242         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2243
2244         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2245         HWRM_CHECK_RESULT();
2246         HWRM_UNLOCK();
2247
2248         bp->pf.vf_info[vf].random_mac = false;
2249
2250         return rc;
2251 }
2252
2253 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2254                                   uint64_t *dropped)
2255 {
2256         int rc = 0;
2257         struct hwrm_func_qstats_input req = {.req_type = 0};
2258         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2259
2260         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2261
2262         req.fid = rte_cpu_to_le_16(fid);
2263
2264         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2265
2266         HWRM_CHECK_RESULT();
2267
2268         if (dropped)
2269                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2270
2271         HWRM_UNLOCK();
2272
2273         return rc;
2274 }
2275
2276 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2277                           struct rte_eth_stats *stats,
2278                           struct hwrm_func_qstats_output *func_qstats)
2279 {
2280         int rc = 0;
2281         struct hwrm_func_qstats_input req = {.req_type = 0};
2282         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2283
2284         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2285
2286         req.fid = rte_cpu_to_le_16(fid);
2287
2288         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2289
2290         HWRM_CHECK_RESULT();
2291         if (func_qstats)
2292                 memcpy(func_qstats, resp,
2293                        sizeof(struct hwrm_func_qstats_output));
2294
2295         if (!stats)
2296                 goto exit;
2297
2298         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2299         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2300         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2301         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2302         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2303         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2304
2305         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2306         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2307         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2308         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2309         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2310         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2311
2312         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2313         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2314         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2315
2316 exit:
2317         HWRM_UNLOCK();
2318
2319         return rc;
2320 }
2321
2322 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2323 {
2324         int rc = 0;
2325         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2326         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2327
2328         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2329
2330         req.fid = rte_cpu_to_le_16(fid);
2331
2332         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2333
2334         HWRM_CHECK_RESULT();
2335         HWRM_UNLOCK();
2336
2337         return rc;
2338 }
2339
2340 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2341 {
2342         unsigned int i;
2343         int rc = 0;
2344
2345         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2346                 struct bnxt_tx_queue *txq;
2347                 struct bnxt_rx_queue *rxq;
2348                 struct bnxt_cp_ring_info *cpr;
2349
2350                 if (i >= bp->rx_cp_nr_rings) {
2351                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2352                         cpr = txq->cp_ring;
2353                 } else {
2354                         rxq = bp->rx_queues[i];
2355                         cpr = rxq->cp_ring;
2356                 }
2357
2358                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2359                 if (rc)
2360                         return rc;
2361         }
2362         return 0;
2363 }
2364
2365 static int
2366 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2367 {
2368         int rc;
2369         unsigned int i;
2370         struct bnxt_cp_ring_info *cpr;
2371
2372         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2373
2374                 if (i >= bp->rx_cp_nr_rings) {
2375                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2376                 } else {
2377                         cpr = bp->rx_queues[i]->cp_ring;
2378                         if (BNXT_HAS_RING_GRPS(bp))
2379                                 bp->grp_info[i].fw_stats_ctx = -1;
2380                 }
2381                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2382                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2383                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2384                         if (rc)
2385                                 return rc;
2386                 }
2387         }
2388         return 0;
2389 }
2390
2391 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2392 {
2393         unsigned int i;
2394         int rc = 0;
2395
2396         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2397                 struct bnxt_tx_queue *txq;
2398                 struct bnxt_rx_queue *rxq;
2399                 struct bnxt_cp_ring_info *cpr;
2400
2401                 if (i >= bp->rx_cp_nr_rings) {
2402                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2403                         cpr = txq->cp_ring;
2404                 } else {
2405                         rxq = bp->rx_queues[i];
2406                         cpr = rxq->cp_ring;
2407                 }
2408
2409                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2410
2411                 if (rc)
2412                         return rc;
2413         }
2414         return rc;
2415 }
2416
2417 static int
2418 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2419 {
2420         uint16_t idx;
2421         uint32_t rc = 0;
2422
2423         if (!BNXT_HAS_RING_GRPS(bp))
2424                 return 0;
2425
2426         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2427
2428                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2429                         continue;
2430
2431                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2432
2433                 if (rc)
2434                         return rc;
2435         }
2436         return rc;
2437 }
2438
2439 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2440 {
2441         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2442
2443         bnxt_hwrm_ring_free(bp, cp_ring,
2444                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2445         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2446         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2447                                      sizeof(*cpr->cp_desc_ring));
2448         cpr->cp_raw_cons = 0;
2449         cpr->valid = 0;
2450 }
2451
2452 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2453 {
2454         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2455
2456         bnxt_hwrm_ring_free(bp, cp_ring,
2457                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2458         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2459         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2460                         sizeof(*cpr->cp_desc_ring));
2461         cpr->cp_raw_cons = 0;
2462         cpr->valid = 0;
2463 }
2464
2465 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2466 {
2467         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2468         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2469         struct bnxt_ring *ring = rxr->rx_ring_struct;
2470         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2471
2472         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2473                 bnxt_hwrm_ring_free(bp, ring,
2474                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2475                 ring->fw_ring_id = INVALID_HW_RING_ID;
2476                 if (BNXT_HAS_RING_GRPS(bp))
2477                         bp->grp_info[queue_index].rx_fw_ring_id =
2478                                                         INVALID_HW_RING_ID;
2479                 memset(rxr->rx_desc_ring, 0,
2480                        rxr->rx_ring_struct->ring_size *
2481                        sizeof(*rxr->rx_desc_ring));
2482                 memset(rxr->rx_buf_ring, 0,
2483                        rxr->rx_ring_struct->ring_size *
2484                        sizeof(*rxr->rx_buf_ring));
2485                 rxr->rx_prod = 0;
2486         }
2487         ring = rxr->ag_ring_struct;
2488         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2489                 bnxt_hwrm_ring_free(bp, ring,
2490                                     BNXT_CHIP_THOR(bp) ?
2491                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2492                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2493                 ring->fw_ring_id = INVALID_HW_RING_ID;
2494                 memset(rxr->ag_buf_ring, 0,
2495                        rxr->ag_ring_struct->ring_size *
2496                        sizeof(*rxr->ag_buf_ring));
2497                 rxr->ag_prod = 0;
2498                 if (BNXT_HAS_RING_GRPS(bp))
2499                         bp->grp_info[queue_index].ag_fw_ring_id =
2500                                                         INVALID_HW_RING_ID;
2501         }
2502         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2503                 bnxt_free_cp_ring(bp, cpr);
2504
2505         if (BNXT_HAS_RING_GRPS(bp))
2506                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2507 }
2508
2509 static int
2510 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2511 {
2512         unsigned int i;
2513
2514         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2515                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2516                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2517                 struct bnxt_ring *ring = txr->tx_ring_struct;
2518                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2519
2520                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2521                         bnxt_hwrm_ring_free(bp, ring,
2522                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2523                         ring->fw_ring_id = INVALID_HW_RING_ID;
2524                         memset(txr->tx_desc_ring, 0,
2525                                         txr->tx_ring_struct->ring_size *
2526                                         sizeof(*txr->tx_desc_ring));
2527                         memset(txr->tx_buf_ring, 0,
2528                                         txr->tx_ring_struct->ring_size *
2529                                         sizeof(*txr->tx_buf_ring));
2530                         txr->tx_prod = 0;
2531                         txr->tx_cons = 0;
2532                 }
2533                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2534                         bnxt_free_cp_ring(bp, cpr);
2535                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2536                 }
2537         }
2538
2539         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2540                 bnxt_free_hwrm_rx_ring(bp, i);
2541
2542         return 0;
2543 }
2544
2545 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2546 {
2547         uint16_t i;
2548         uint32_t rc = 0;
2549
2550         if (!BNXT_HAS_RING_GRPS(bp))
2551                 return 0;
2552
2553         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2554                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2555                 if (rc)
2556                         return rc;
2557         }
2558         return rc;
2559 }
2560
2561 /*
2562  * HWRM utility functions
2563  */
2564
2565 void bnxt_free_hwrm_resources(struct bnxt *bp)
2566 {
2567         /* Release memzone */
2568         rte_free(bp->hwrm_cmd_resp_addr);
2569         rte_free(bp->hwrm_short_cmd_req_addr);
2570         bp->hwrm_cmd_resp_addr = NULL;
2571         bp->hwrm_short_cmd_req_addr = NULL;
2572         bp->hwrm_cmd_resp_dma_addr = 0;
2573         bp->hwrm_short_cmd_req_dma_addr = 0;
2574 }
2575
2576 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2577 {
2578         struct rte_pci_device *pdev = bp->pdev;
2579         char type[RTE_MEMZONE_NAMESIZE];
2580
2581         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2582                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2583         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2584         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2585         if (bp->hwrm_cmd_resp_addr == NULL)
2586                 return -ENOMEM;
2587         bp->hwrm_cmd_resp_dma_addr =
2588                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2589         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2590                 PMD_DRV_LOG(ERR,
2591                         "unable to map response address to physical memory\n");
2592                 return -ENOMEM;
2593         }
2594         rte_spinlock_init(&bp->hwrm_lock);
2595
2596         return 0;
2597 }
2598
2599 static int
2600 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2601 {
2602         struct bnxt_filter_info *filter;
2603         int rc = 0;
2604
2605         STAILQ_FOREACH(filter, &vnic->filter, next) {
2606                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2607                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2608                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2609                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2610                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2611                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2612                 bnxt_free_filter(bp, filter);
2613         }
2614         return rc;
2615 }
2616
2617 static int
2618 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2619 {
2620         struct bnxt_filter_info *filter;
2621         struct rte_flow *flow;
2622         int rc = 0;
2623
2624         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2625                 flow = STAILQ_FIRST(&vnic->flow_list);
2626                 filter = flow->filter;
2627                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2628                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2629                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2630                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2631                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2632                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2633
2634                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2635                 rte_free(flow);
2636         }
2637         return rc;
2638 }
2639
2640 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2641 {
2642         struct bnxt_filter_info *filter;
2643         int rc = 0;
2644
2645         STAILQ_FOREACH(filter, &vnic->filter, next) {
2646                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2647                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2648                                                      filter);
2649                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2650                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2651                                                          filter);
2652                 else
2653                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2654                                                      filter);
2655                 if (rc)
2656                         break;
2657         }
2658         return rc;
2659 }
2660
2661 static void
2662 bnxt_free_tunnel_ports(struct bnxt *bp)
2663 {
2664         if (bp->vxlan_port_cnt)
2665                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2666                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2667         bp->vxlan_port = 0;
2668         if (bp->geneve_port_cnt)
2669                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2670                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2671         bp->geneve_port = 0;
2672 }
2673
2674 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2675 {
2676         int i;
2677
2678         if (bp->vnic_info == NULL)
2679                 return;
2680
2681         /*
2682          * Cleanup VNICs in reverse order, to make sure the L2 filter
2683          * from vnic0 is last to be cleaned up.
2684          */
2685         for (i = bp->max_vnics - 1; i >= 0; i--) {
2686                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2687
2688                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2689                         continue;
2690
2691                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2692
2693                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2694
2695                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2696
2697                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2698
2699                 bnxt_hwrm_vnic_free(bp, vnic);
2700
2701                 rte_free(vnic->fw_grp_ids);
2702         }
2703         /* Ring resources */
2704         bnxt_free_all_hwrm_rings(bp);
2705         bnxt_free_all_hwrm_ring_grps(bp);
2706         bnxt_free_all_hwrm_stat_ctxs(bp);
2707         bnxt_free_tunnel_ports(bp);
2708 }
2709
2710 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2711 {
2712         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2713
2714         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2715                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2716
2717         switch (conf_link_speed) {
2718         case ETH_LINK_SPEED_10M_HD:
2719         case ETH_LINK_SPEED_100M_HD:
2720                 /* FALLTHROUGH */
2721                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2722         }
2723         return hw_link_duplex;
2724 }
2725
2726 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2727 {
2728         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2729 }
2730
2731 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2732 {
2733         uint16_t eth_link_speed = 0;
2734
2735         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2736                 return ETH_LINK_SPEED_AUTONEG;
2737
2738         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2739         case ETH_LINK_SPEED_100M:
2740         case ETH_LINK_SPEED_100M_HD:
2741                 /* FALLTHROUGH */
2742                 eth_link_speed =
2743                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2744                 break;
2745         case ETH_LINK_SPEED_1G:
2746                 eth_link_speed =
2747                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2748                 break;
2749         case ETH_LINK_SPEED_2_5G:
2750                 eth_link_speed =
2751                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2752                 break;
2753         case ETH_LINK_SPEED_10G:
2754                 eth_link_speed =
2755                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2756                 break;
2757         case ETH_LINK_SPEED_20G:
2758                 eth_link_speed =
2759                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2760                 break;
2761         case ETH_LINK_SPEED_25G:
2762                 eth_link_speed =
2763                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2764                 break;
2765         case ETH_LINK_SPEED_40G:
2766                 eth_link_speed =
2767                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2768                 break;
2769         case ETH_LINK_SPEED_50G:
2770                 eth_link_speed =
2771                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2772                 break;
2773         case ETH_LINK_SPEED_100G:
2774                 eth_link_speed =
2775                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2776                 break;
2777         default:
2778                 PMD_DRV_LOG(ERR,
2779                         "Unsupported link speed %d; default to AUTO\n",
2780                         conf_link_speed);
2781                 break;
2782         }
2783         return eth_link_speed;
2784 }
2785
2786 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2787                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2788                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2789                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2790
2791 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2792 {
2793         uint32_t one_speed;
2794
2795         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2796                 return 0;
2797
2798         if (link_speed & ETH_LINK_SPEED_FIXED) {
2799                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2800
2801                 if (one_speed & (one_speed - 1)) {
2802                         PMD_DRV_LOG(ERR,
2803                                 "Invalid advertised speeds (%u) for port %u\n",
2804                                 link_speed, port_id);
2805                         return -EINVAL;
2806                 }
2807                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2808                         PMD_DRV_LOG(ERR,
2809                                 "Unsupported advertised speed (%u) for port %u\n",
2810                                 link_speed, port_id);
2811                         return -EINVAL;
2812                 }
2813         } else {
2814                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2815                         PMD_DRV_LOG(ERR,
2816                                 "Unsupported advertised speeds (%u) for port %u\n",
2817                                 link_speed, port_id);
2818                         return -EINVAL;
2819                 }
2820         }
2821         return 0;
2822 }
2823
2824 static uint16_t
2825 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2826 {
2827         uint16_t ret = 0;
2828
2829         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2830                 if (bp->link_info.support_speeds)
2831                         return bp->link_info.support_speeds;
2832                 link_speed = BNXT_SUPPORTED_SPEEDS;
2833         }
2834
2835         if (link_speed & ETH_LINK_SPEED_100M)
2836                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2837         if (link_speed & ETH_LINK_SPEED_100M_HD)
2838                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2839         if (link_speed & ETH_LINK_SPEED_1G)
2840                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2841         if (link_speed & ETH_LINK_SPEED_2_5G)
2842                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2843         if (link_speed & ETH_LINK_SPEED_10G)
2844                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2845         if (link_speed & ETH_LINK_SPEED_20G)
2846                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2847         if (link_speed & ETH_LINK_SPEED_25G)
2848                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2849         if (link_speed & ETH_LINK_SPEED_40G)
2850                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2851         if (link_speed & ETH_LINK_SPEED_50G)
2852                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2853         if (link_speed & ETH_LINK_SPEED_100G)
2854                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2855         return ret;
2856 }
2857
2858 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2859 {
2860         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2861
2862         switch (hw_link_speed) {
2863         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2864                 eth_link_speed = ETH_SPEED_NUM_100M;
2865                 break;
2866         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2867                 eth_link_speed = ETH_SPEED_NUM_1G;
2868                 break;
2869         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2870                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2871                 break;
2872         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2873                 eth_link_speed = ETH_SPEED_NUM_10G;
2874                 break;
2875         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2876                 eth_link_speed = ETH_SPEED_NUM_20G;
2877                 break;
2878         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2879                 eth_link_speed = ETH_SPEED_NUM_25G;
2880                 break;
2881         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2882                 eth_link_speed = ETH_SPEED_NUM_40G;
2883                 break;
2884         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2885                 eth_link_speed = ETH_SPEED_NUM_50G;
2886                 break;
2887         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2888                 eth_link_speed = ETH_SPEED_NUM_100G;
2889                 break;
2890         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2891         default:
2892                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2893                         hw_link_speed);
2894                 break;
2895         }
2896         return eth_link_speed;
2897 }
2898
2899 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2900 {
2901         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2902
2903         switch (hw_link_duplex) {
2904         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2905         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2906                 /* FALLTHROUGH */
2907                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2908                 break;
2909         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2910                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2911                 break;
2912         default:
2913                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2914                         hw_link_duplex);
2915                 break;
2916         }
2917         return eth_link_duplex;
2918 }
2919
2920 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2921 {
2922         int rc = 0;
2923         struct bnxt_link_info *link_info = &bp->link_info;
2924
2925         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2926         if (rc) {
2927                 PMD_DRV_LOG(ERR,
2928                         "Get link config failed with rc %d\n", rc);
2929                 goto exit;
2930         }
2931         if (link_info->link_speed)
2932                 link->link_speed =
2933                         bnxt_parse_hw_link_speed(link_info->link_speed);
2934         else
2935                 link->link_speed = ETH_SPEED_NUM_NONE;
2936         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2937         link->link_status = link_info->link_up;
2938         link->link_autoneg = link_info->auto_mode ==
2939                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2940                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2941 exit:
2942         return rc;
2943 }
2944
2945 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2946 {
2947         int rc = 0;
2948         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2949         struct bnxt_link_info link_req;
2950         uint16_t speed, autoneg;
2951
2952         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2953                 return 0;
2954
2955         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2956                         bp->eth_dev->data->port_id);
2957         if (rc)
2958                 goto error;
2959
2960         memset(&link_req, 0, sizeof(link_req));
2961         link_req.link_up = link_up;
2962         if (!link_up)
2963                 goto port_phy_cfg;
2964
2965         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2966         if (BNXT_CHIP_THOR(bp) &&
2967             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2968                 /* 40G is not supported as part of media auto detect.
2969                  * The speed should be forced and autoneg disabled
2970                  * to configure 40G speed.
2971                  */
2972                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2973                 autoneg = 0;
2974         }
2975
2976         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2977         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2978         /* Autoneg can be done only when the FW allows.
2979          * When user configures fixed speed of 40G and later changes to
2980          * any other speed, auto_link_speed/force_link_speed is still set
2981          * to 40G until link comes up at new speed.
2982          */
2983         if (autoneg == 1 &&
2984             !(!BNXT_CHIP_THOR(bp) &&
2985               (bp->link_info.auto_link_speed ||
2986                bp->link_info.force_link_speed))) {
2987                 link_req.phy_flags |=
2988                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2989                 link_req.auto_link_speed_mask =
2990                         bnxt_parse_eth_link_speed_mask(bp,
2991                                                        dev_conf->link_speeds);
2992         } else {
2993                 if (bp->link_info.phy_type ==
2994                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2995                     bp->link_info.phy_type ==
2996                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2997                     bp->link_info.media_type ==
2998                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2999                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3000                         return -EINVAL;
3001                 }
3002
3003                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3004                 /* If user wants a particular speed try that first. */
3005                 if (speed)
3006                         link_req.link_speed = speed;
3007                 else if (bp->link_info.force_link_speed)
3008                         link_req.link_speed = bp->link_info.force_link_speed;
3009                 else
3010                         link_req.link_speed = bp->link_info.auto_link_speed;
3011         }
3012         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3013         link_req.auto_pause = bp->link_info.auto_pause;
3014         link_req.force_pause = bp->link_info.force_pause;
3015
3016 port_phy_cfg:
3017         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3018         if (rc) {
3019                 PMD_DRV_LOG(ERR,
3020                         "Set link config failed with rc %d\n", rc);
3021         }
3022
3023 error:
3024         return rc;
3025 }
3026
3027 /* JIRA 22088 */
3028 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3029 {
3030         struct hwrm_func_qcfg_input req = {0};
3031         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3032         uint16_t flags;
3033         int rc = 0;
3034         bp->func_svif = BNXT_SVIF_INVALID;
3035         uint16_t svif_info;
3036
3037         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3038         req.fid = rte_cpu_to_le_16(0xffff);
3039
3040         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3041
3042         HWRM_CHECK_RESULT();
3043
3044         /* Hard Coded.. 0xfff VLAN ID mask */
3045         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3046
3047         svif_info = rte_le_to_cpu_16(resp->svif_info);
3048         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3049                 bp->func_svif = svif_info &
3050                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3051
3052         flags = rte_le_to_cpu_16(resp->flags);
3053         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3054                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3055
3056         if (BNXT_VF(bp) &&
3057             !BNXT_VF_IS_TRUSTED(bp) &&
3058             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3059                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3060                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3061         } else if (BNXT_VF(bp) &&
3062                    BNXT_VF_IS_TRUSTED(bp) &&
3063                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3064                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3065                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3066         }
3067
3068         if (mtu)
3069                 *mtu = rte_le_to_cpu_16(resp->mtu);
3070
3071         switch (resp->port_partition_type) {
3072         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3073         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3074         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3075                 /* FALLTHROUGH */
3076                 bp->flags |= BNXT_FLAG_NPAR_PF;
3077                 break;
3078         default:
3079                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3080                 break;
3081         }
3082
3083         HWRM_UNLOCK();
3084
3085         return rc;
3086 }
3087
3088 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3089 {
3090         struct hwrm_port_mac_qcfg_input req = {0};
3091         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3092         uint16_t port_svif_info;
3093         int rc;
3094
3095         bp->port_svif = BNXT_SVIF_INVALID;
3096
3097         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3098
3099         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3100
3101         HWRM_CHECK_RESULT();
3102
3103         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3104         if (port_svif_info &
3105             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3106                 bp->port_svif = port_svif_info &
3107                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3108
3109         HWRM_UNLOCK();
3110
3111         return 0;
3112 }
3113
3114 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3115                                    struct hwrm_func_qcaps_output *qcaps)
3116 {
3117         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3118         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3119                sizeof(qcaps->mac_address));
3120         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3121         qcaps->max_rx_rings = fcfg->num_rx_rings;
3122         qcaps->max_tx_rings = fcfg->num_tx_rings;
3123         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3124         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3125         qcaps->max_vfs = 0;
3126         qcaps->first_vf_id = 0;
3127         qcaps->max_vnics = fcfg->num_vnics;
3128         qcaps->max_decap_records = 0;
3129         qcaps->max_encap_records = 0;
3130         qcaps->max_tx_wm_flows = 0;
3131         qcaps->max_tx_em_flows = 0;
3132         qcaps->max_rx_wm_flows = 0;
3133         qcaps->max_rx_em_flows = 0;
3134         qcaps->max_flow_id = 0;
3135         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3136         qcaps->max_sp_tx_rings = 0;
3137         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3138 }
3139
3140 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3141 {
3142         struct hwrm_func_cfg_input req = {0};
3143         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3144         uint32_t enables;
3145         int rc;
3146
3147         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3148                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3149                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3150                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3151                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3152                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3153                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3154                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3155                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3156
3157         if (BNXT_HAS_RING_GRPS(bp)) {
3158                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3159                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3160         } else if (BNXT_HAS_NQ(bp)) {
3161                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3162                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3163         }
3164
3165         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3166         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3167         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3168         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3169         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3170         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3171         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3172         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3173         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3174         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3175         req.fid = rte_cpu_to_le_16(0xffff);
3176         req.enables = rte_cpu_to_le_32(enables);
3177
3178         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3179
3180         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3181
3182         HWRM_CHECK_RESULT();
3183         HWRM_UNLOCK();
3184
3185         return rc;
3186 }
3187
3188 static void populate_vf_func_cfg_req(struct bnxt *bp,
3189                                      struct hwrm_func_cfg_input *req,
3190                                      int num_vfs)
3191 {
3192         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3193                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3194                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3195                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3196                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3197                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3198                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3199                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3200                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3201                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3202
3203         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3204                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3205                                     BNXT_NUM_VLANS);
3206         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3207         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3208                                                 (num_vfs + 1));
3209         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3210         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3211                                                (num_vfs + 1));
3212         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3213         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3214         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3215         /* TODO: For now, do not support VMDq/RFS on VFs. */
3216         req->num_vnics = rte_cpu_to_le_16(1);
3217         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3218                                                  (num_vfs + 1));
3219 }
3220
3221 static void add_random_mac_if_needed(struct bnxt *bp,
3222                                      struct hwrm_func_cfg_input *cfg_req,
3223                                      int vf)
3224 {
3225         struct rte_ether_addr mac;
3226
3227         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3228                 return;
3229
3230         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3231                 cfg_req->enables |=
3232                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3233                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3234                 bp->pf.vf_info[vf].random_mac = true;
3235         } else {
3236                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3237                         RTE_ETHER_ADDR_LEN);
3238         }
3239 }
3240
3241 static int reserve_resources_from_vf(struct bnxt *bp,
3242                                      struct hwrm_func_cfg_input *cfg_req,
3243                                      int vf)
3244 {
3245         struct hwrm_func_qcaps_input req = {0};
3246         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3247         int rc;
3248
3249         /* Get the actual allocated values now */
3250         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3251         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3252         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3253
3254         if (rc) {
3255                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3256                 copy_func_cfg_to_qcaps(cfg_req, resp);
3257         } else if (resp->error_code) {
3258                 rc = rte_le_to_cpu_16(resp->error_code);
3259                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3260                 copy_func_cfg_to_qcaps(cfg_req, resp);
3261         }
3262
3263         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3264         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3265         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3266         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3267         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3268         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3269         /*
3270          * TODO: While not supporting VMDq with VFs, max_vnics is always
3271          * forced to 1 in this case
3272          */
3273         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3274         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3275
3276         HWRM_UNLOCK();
3277
3278         return 0;
3279 }
3280
3281 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3282 {
3283         struct hwrm_func_qcfg_input req = {0};
3284         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3285         int rc;
3286
3287         /* Check for zero MAC address */
3288         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3289         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3290         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3291         HWRM_CHECK_RESULT();
3292         rc = rte_le_to_cpu_16(resp->vlan);
3293
3294         HWRM_UNLOCK();
3295
3296         return rc;
3297 }
3298
3299 static int update_pf_resource_max(struct bnxt *bp)
3300 {
3301         struct hwrm_func_qcfg_input req = {0};
3302         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3303         int rc;
3304
3305         /* And copy the allocated numbers into the pf struct */
3306         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3307         req.fid = rte_cpu_to_le_16(0xffff);
3308         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3309         HWRM_CHECK_RESULT();
3310
3311         /* Only TX ring value reflects actual allocation? TODO */
3312         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3313         bp->pf.evb_mode = resp->evb_mode;
3314
3315         HWRM_UNLOCK();
3316
3317         return rc;
3318 }
3319
3320 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3321 {
3322         int rc;
3323
3324         if (!BNXT_PF(bp)) {
3325                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3326                 return -EINVAL;
3327         }
3328
3329         rc = bnxt_hwrm_func_qcaps(bp);
3330         if (rc)
3331                 return rc;
3332
3333         bp->pf.func_cfg_flags &=
3334                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3335                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3336         bp->pf.func_cfg_flags |=
3337                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3338         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3339         rc = __bnxt_hwrm_func_qcaps(bp);
3340         return rc;
3341 }
3342
3343 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3344 {
3345         struct hwrm_func_cfg_input req = {0};
3346         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3347         int i;
3348         size_t sz;
3349         int rc = 0;
3350         size_t req_buf_sz;
3351
3352         if (!BNXT_PF(bp)) {
3353                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3354                 return -EINVAL;
3355         }
3356
3357         rc = bnxt_hwrm_func_qcaps(bp);
3358
3359         if (rc)
3360                 return rc;
3361
3362         bp->pf.active_vfs = num_vfs;
3363
3364         /*
3365          * First, configure the PF to only use one TX ring.  This ensures that
3366          * there are enough rings for all VFs.
3367          *
3368          * If we don't do this, when we call func_alloc() later, we will lock
3369          * extra rings to the PF that won't be available during func_cfg() of
3370          * the VFs.
3371          *
3372          * This has been fixed with firmware versions above 20.6.54
3373          */
3374         bp->pf.func_cfg_flags &=
3375                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3376                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3377         bp->pf.func_cfg_flags |=
3378                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3379         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3380         if (rc)
3381                 return rc;
3382
3383         /*
3384          * Now, create and register a buffer to hold forwarded VF requests
3385          */
3386         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3387         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3388                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3389         if (bp->pf.vf_req_buf == NULL) {
3390                 rc = -ENOMEM;
3391                 goto error_free;
3392         }
3393         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3394                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3395         for (i = 0; i < num_vfs; i++)
3396                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3397                                         (i * HWRM_MAX_REQ_LEN);
3398
3399         rc = bnxt_hwrm_func_buf_rgtr(bp);
3400         if (rc)
3401                 goto error_free;
3402
3403         populate_vf_func_cfg_req(bp, &req, num_vfs);
3404
3405         bp->pf.active_vfs = 0;
3406         for (i = 0; i < num_vfs; i++) {
3407                 add_random_mac_if_needed(bp, &req, i);
3408
3409                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3410                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3411                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3412                 rc = bnxt_hwrm_send_message(bp,
3413                                             &req,
3414                                             sizeof(req),
3415                                             BNXT_USE_CHIMP_MB);
3416
3417                 /* Clear enable flag for next pass */
3418                 req.enables &= ~rte_cpu_to_le_32(
3419                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3420
3421                 if (rc || resp->error_code) {
3422                         PMD_DRV_LOG(ERR,
3423                                 "Failed to initizlie VF %d\n", i);
3424                         PMD_DRV_LOG(ERR,
3425                                 "Not all VFs available. (%d, %d)\n",
3426                                 rc, resp->error_code);
3427                         HWRM_UNLOCK();
3428                         break;
3429                 }
3430
3431                 HWRM_UNLOCK();
3432
3433                 reserve_resources_from_vf(bp, &req, i);
3434                 bp->pf.active_vfs++;
3435                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3436         }
3437
3438         /*
3439          * Now configure the PF to use "the rest" of the resources
3440          * We're using STD_TX_RING_MODE here though which will limit the TX
3441          * rings.  This will allow QoS to function properly.  Not setting this
3442          * will cause PF rings to break bandwidth settings.
3443          */
3444         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3445         if (rc)
3446                 goto error_free;
3447
3448         rc = update_pf_resource_max(bp);
3449         if (rc)
3450                 goto error_free;
3451
3452         return rc;
3453
3454 error_free:
3455         bnxt_hwrm_func_buf_unrgtr(bp);
3456         return rc;
3457 }
3458
3459 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3460 {
3461         struct hwrm_func_cfg_input req = {0};
3462         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3463         int rc;
3464
3465         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3466
3467         req.fid = rte_cpu_to_le_16(0xffff);
3468         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3469         req.evb_mode = bp->pf.evb_mode;
3470
3471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3472         HWRM_CHECK_RESULT();
3473         HWRM_UNLOCK();
3474
3475         return rc;
3476 }
3477
3478 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3479                                 uint8_t tunnel_type)
3480 {
3481         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3482         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3483         int rc = 0;
3484
3485         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3486         req.tunnel_type = tunnel_type;
3487         req.tunnel_dst_port_val = port;
3488         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3489         HWRM_CHECK_RESULT();
3490
3491         switch (tunnel_type) {
3492         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3493                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3494                 bp->vxlan_port = port;
3495                 break;
3496         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3497                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3498                 bp->geneve_port = port;
3499                 break;
3500         default:
3501                 break;
3502         }
3503
3504         HWRM_UNLOCK();
3505
3506         return rc;
3507 }
3508
3509 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3510                                 uint8_t tunnel_type)
3511 {
3512         struct hwrm_tunnel_dst_port_free_input req = {0};
3513         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3514         int rc = 0;
3515
3516         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3517
3518         req.tunnel_type = tunnel_type;
3519         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3520         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3521
3522         HWRM_CHECK_RESULT();
3523         HWRM_UNLOCK();
3524
3525         return rc;
3526 }
3527
3528 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3529                                         uint32_t flags)
3530 {
3531         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3532         struct hwrm_func_cfg_input req = {0};
3533         int rc;
3534
3535         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3536
3537         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3538         req.flags = rte_cpu_to_le_32(flags);
3539         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3540
3541         HWRM_CHECK_RESULT();
3542         HWRM_UNLOCK();
3543
3544         return rc;
3545 }
3546
3547 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3548 {
3549         uint32_t *flag = flagp;
3550
3551         vnic->flags = *flag;
3552 }
3553
3554 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3555 {
3556         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3557 }
3558
3559 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3560 {
3561         int rc = 0;
3562         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3563         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3564
3565         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3566
3567         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3568         req.req_buf_page_size = rte_cpu_to_le_16(
3569                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3570         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3571         req.req_buf_page_addr0 =
3572                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf.vf_req_buf));
3573         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3574                 PMD_DRV_LOG(ERR,
3575                         "unable to map buffer address to physical memory\n");
3576                 return -ENOMEM;
3577         }
3578
3579         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3580
3581         HWRM_CHECK_RESULT();
3582         HWRM_UNLOCK();
3583
3584         return rc;
3585 }
3586
3587 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3588 {
3589         int rc = 0;
3590         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3591         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3592
3593         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3594                 return 0;
3595
3596         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3597
3598         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3599
3600         HWRM_CHECK_RESULT();
3601         HWRM_UNLOCK();
3602
3603         return rc;
3604 }
3605
3606 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3607 {
3608         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3609         struct hwrm_func_cfg_input req = {0};
3610         int rc;
3611
3612         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3613
3614         req.fid = rte_cpu_to_le_16(0xffff);
3615         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3616         req.enables = rte_cpu_to_le_32(
3617                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3618         req.async_event_cr = rte_cpu_to_le_16(
3619                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3620         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3621
3622         HWRM_CHECK_RESULT();
3623         HWRM_UNLOCK();
3624
3625         return rc;
3626 }
3627
3628 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3629 {
3630         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3631         struct hwrm_func_vf_cfg_input req = {0};
3632         int rc;
3633
3634         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3635
3636         req.enables = rte_cpu_to_le_32(
3637                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3638         req.async_event_cr = rte_cpu_to_le_16(
3639                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3640         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3641
3642         HWRM_CHECK_RESULT();
3643         HWRM_UNLOCK();
3644
3645         return rc;
3646 }
3647
3648 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3649 {
3650         struct hwrm_func_cfg_input req = {0};
3651         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3652         uint16_t dflt_vlan, fid;
3653         uint32_t func_cfg_flags;
3654         int rc = 0;
3655
3656         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3657
3658         if (is_vf) {
3659                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3660                 fid = bp->pf.vf_info[vf].fid;
3661                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3662         } else {
3663                 fid = rte_cpu_to_le_16(0xffff);
3664                 func_cfg_flags = bp->pf.func_cfg_flags;
3665                 dflt_vlan = bp->vlan;
3666         }
3667
3668         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3669         req.fid = rte_cpu_to_le_16(fid);
3670         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3671         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3672
3673         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3674
3675         HWRM_CHECK_RESULT();
3676         HWRM_UNLOCK();
3677
3678         return rc;
3679 }
3680
3681 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3682                         uint16_t max_bw, uint16_t enables)
3683 {
3684         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3685         struct hwrm_func_cfg_input req = {0};
3686         int rc;
3687
3688         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3689
3690         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3691         req.enables |= rte_cpu_to_le_32(enables);
3692         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3693         req.max_bw = rte_cpu_to_le_32(max_bw);
3694         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3695
3696         HWRM_CHECK_RESULT();
3697         HWRM_UNLOCK();
3698
3699         return rc;
3700 }
3701
3702 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3703 {
3704         struct hwrm_func_cfg_input req = {0};
3705         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3706         int rc = 0;
3707
3708         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3709
3710         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3711         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3712         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3713         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3714
3715         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3716
3717         HWRM_CHECK_RESULT();
3718         HWRM_UNLOCK();
3719
3720         return rc;
3721 }
3722
3723 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3724 {
3725         int rc;
3726
3727         if (BNXT_PF(bp))
3728                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3729         else
3730                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3731
3732         return rc;
3733 }
3734
3735 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3736                               void *encaped, size_t ec_size)
3737 {
3738         int rc = 0;
3739         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3740         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3741
3742         if (ec_size > sizeof(req.encap_request))
3743                 return -1;
3744
3745         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3746
3747         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3748         memcpy(req.encap_request, encaped, ec_size);
3749
3750         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3751
3752         HWRM_CHECK_RESULT();
3753         HWRM_UNLOCK();
3754
3755         return rc;
3756 }
3757
3758 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3759                                        struct rte_ether_addr *mac)
3760 {
3761         struct hwrm_func_qcfg_input req = {0};
3762         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3763         int rc;
3764
3765         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3766
3767         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3768         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3769
3770         HWRM_CHECK_RESULT();
3771
3772         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3773
3774         HWRM_UNLOCK();
3775
3776         return rc;
3777 }
3778
3779 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3780                             void *encaped, size_t ec_size)
3781 {
3782         int rc = 0;
3783         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3784         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3785
3786         if (ec_size > sizeof(req.encap_request))
3787                 return -1;
3788
3789         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3790
3791         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3792         memcpy(req.encap_request, encaped, ec_size);
3793
3794         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3795
3796         HWRM_CHECK_RESULT();
3797         HWRM_UNLOCK();
3798
3799         return rc;
3800 }
3801
3802 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3803                          struct rte_eth_stats *stats, uint8_t rx)
3804 {
3805         int rc = 0;
3806         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3807         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3808
3809         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3810
3811         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3812
3813         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3814
3815         HWRM_CHECK_RESULT();
3816
3817         if (rx) {
3818                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3819                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3820                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3821                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3822                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3823                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3824                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3825                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3826         } else {
3827                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3828                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3829                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3830                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3831                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3832                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3833         }
3834
3835         HWRM_UNLOCK();
3836
3837         return rc;
3838 }
3839
3840 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3841 {
3842         struct hwrm_port_qstats_input req = {0};
3843         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3844         struct bnxt_pf_info *pf = &bp->pf;
3845         int rc;
3846
3847         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
3848
3849         req.port_id = rte_cpu_to_le_16(pf->port_id);
3850         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3851         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3852         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3853
3854         HWRM_CHECK_RESULT();
3855         HWRM_UNLOCK();
3856
3857         return rc;
3858 }
3859
3860 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3861 {
3862         struct hwrm_port_clr_stats_input req = {0};
3863         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3864         struct bnxt_pf_info *pf = &bp->pf;
3865         int rc;
3866
3867         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3868         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3869             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3870                 return 0;
3871
3872         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3873
3874         req.port_id = rte_cpu_to_le_16(pf->port_id);
3875         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3876
3877         HWRM_CHECK_RESULT();
3878         HWRM_UNLOCK();
3879
3880         return rc;
3881 }
3882
3883 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3884 {
3885         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3886         struct hwrm_port_led_qcaps_input req = {0};
3887         int rc;
3888
3889         if (BNXT_VF(bp))
3890                 return 0;
3891
3892         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3893         req.port_id = bp->pf.port_id;
3894         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3895
3896         HWRM_CHECK_RESULT();
3897
3898         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3899                 unsigned int i;
3900
3901                 bp->num_leds = resp->num_leds;
3902                 memcpy(bp->leds, &resp->led0_id,
3903                         sizeof(bp->leds[0]) * bp->num_leds);
3904                 for (i = 0; i < bp->num_leds; i++) {
3905                         struct bnxt_led_info *led = &bp->leds[i];
3906
3907                         uint16_t caps = led->led_state_caps;
3908
3909                         if (!led->led_group_id ||
3910                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3911                                 bp->num_leds = 0;
3912                                 break;
3913                         }
3914                 }
3915         }
3916
3917         HWRM_UNLOCK();
3918
3919         return rc;
3920 }
3921
3922 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3923 {
3924         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3925         struct hwrm_port_led_cfg_input req = {0};
3926         struct bnxt_led_cfg *led_cfg;
3927         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3928         uint16_t duration = 0;
3929         int rc, i;
3930
3931         if (!bp->num_leds || BNXT_VF(bp))
3932                 return -EOPNOTSUPP;
3933
3934         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3935
3936         if (led_on) {
3937                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3938                 duration = rte_cpu_to_le_16(500);
3939         }
3940         req.port_id = bp->pf.port_id;
3941         req.num_leds = bp->num_leds;
3942         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3943         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3944                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3945                 led_cfg->led_id = bp->leds[i].led_id;
3946                 led_cfg->led_state = led_state;
3947                 led_cfg->led_blink_on = duration;
3948                 led_cfg->led_blink_off = duration;
3949                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3950         }
3951
3952         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3953
3954         HWRM_CHECK_RESULT();
3955         HWRM_UNLOCK();
3956
3957         return rc;
3958 }
3959
3960 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3961                                uint32_t *length)
3962 {
3963         int rc;
3964         struct hwrm_nvm_get_dir_info_input req = {0};
3965         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3966
3967         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3968
3969         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3970
3971         HWRM_CHECK_RESULT();
3972
3973         *entries = rte_le_to_cpu_32(resp->entries);
3974         *length = rte_le_to_cpu_32(resp->entry_length);
3975
3976         HWRM_UNLOCK();
3977         return rc;
3978 }
3979
3980 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3981 {
3982         int rc;
3983         uint32_t dir_entries;
3984         uint32_t entry_length;
3985         uint8_t *buf;
3986         size_t buflen;
3987         rte_iova_t dma_handle;
3988         struct hwrm_nvm_get_dir_entries_input req = {0};
3989         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3990
3991         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3992         if (rc != 0)
3993                 return rc;
3994
3995         *data++ = dir_entries;
3996         *data++ = entry_length;
3997         len -= 2;
3998         memset(data, 0xff, len);
3999
4000         buflen = dir_entries * entry_length;
4001         buf = rte_malloc("nvm_dir", buflen, 0);
4002         if (buf == NULL)
4003                 return -ENOMEM;
4004         dma_handle = rte_malloc_virt2iova(buf);
4005         if (dma_handle == RTE_BAD_IOVA) {
4006                 PMD_DRV_LOG(ERR,
4007                         "unable to map response address to physical memory\n");
4008                 return -ENOMEM;
4009         }
4010         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4011         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4012         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4013
4014         if (rc == 0)
4015                 memcpy(data, buf, len > buflen ? buflen : len);
4016
4017         rte_free(buf);
4018         HWRM_CHECK_RESULT();
4019         HWRM_UNLOCK();
4020
4021         return rc;
4022 }
4023
4024 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4025                              uint32_t offset, uint32_t length,
4026                              uint8_t *data)
4027 {
4028         int rc;
4029         uint8_t *buf;
4030         rte_iova_t dma_handle;
4031         struct hwrm_nvm_read_input req = {0};
4032         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4033
4034         buf = rte_malloc("nvm_item", length, 0);
4035         if (!buf)
4036                 return -ENOMEM;
4037
4038         dma_handle = rte_malloc_virt2iova(buf);
4039         if (dma_handle == RTE_BAD_IOVA) {
4040                 PMD_DRV_LOG(ERR,
4041                         "unable to map response address to physical memory\n");
4042                 return -ENOMEM;
4043         }
4044         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4045         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4046         req.dir_idx = rte_cpu_to_le_16(index);
4047         req.offset = rte_cpu_to_le_32(offset);
4048         req.len = rte_cpu_to_le_32(length);
4049         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4050         if (rc == 0)
4051                 memcpy(data, buf, length);
4052
4053         rte_free(buf);
4054         HWRM_CHECK_RESULT();
4055         HWRM_UNLOCK();
4056
4057         return rc;
4058 }
4059
4060 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4061 {
4062         int rc;
4063         struct hwrm_nvm_erase_dir_entry_input req = {0};
4064         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4065
4066         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4067         req.dir_idx = rte_cpu_to_le_16(index);
4068         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4069         HWRM_CHECK_RESULT();
4070         HWRM_UNLOCK();
4071
4072         return rc;
4073 }
4074
4075
4076 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4077                           uint16_t dir_ordinal, uint16_t dir_ext,
4078                           uint16_t dir_attr, const uint8_t *data,
4079                           size_t data_len)
4080 {
4081         int rc;
4082         struct hwrm_nvm_write_input req = {0};
4083         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4084         rte_iova_t dma_handle;
4085         uint8_t *buf;
4086
4087         buf = rte_malloc("nvm_write", data_len, 0);
4088         if (!buf)
4089                 return -ENOMEM;
4090
4091         dma_handle = rte_malloc_virt2iova(buf);
4092         if (dma_handle == RTE_BAD_IOVA) {
4093                 PMD_DRV_LOG(ERR,
4094                         "unable to map response address to physical memory\n");
4095                 return -ENOMEM;
4096         }
4097         memcpy(buf, data, data_len);
4098
4099         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4100
4101         req.dir_type = rte_cpu_to_le_16(dir_type);
4102         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4103         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4104         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4105         req.dir_data_length = rte_cpu_to_le_32(data_len);
4106         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4107
4108         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4109
4110         rte_free(buf);
4111         HWRM_CHECK_RESULT();
4112         HWRM_UNLOCK();
4113
4114         return rc;
4115 }
4116
4117 static void
4118 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4119 {
4120         uint32_t *count = cbdata;
4121
4122         *count = *count + 1;
4123 }
4124
4125 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4126                                      struct bnxt_vnic_info *vnic __rte_unused)
4127 {
4128         return 0;
4129 }
4130
4131 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4132 {
4133         uint32_t count = 0;
4134
4135         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4136             &count, bnxt_vnic_count_hwrm_stub);
4137
4138         return count;
4139 }
4140
4141 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4142                                         uint16_t *vnic_ids)
4143 {
4144         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4145         struct hwrm_func_vf_vnic_ids_query_output *resp =
4146                                                 bp->hwrm_cmd_resp_addr;
4147         int rc;
4148
4149         /* First query all VNIC ids */
4150         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4151
4152         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
4153         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
4154         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4155
4156         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4157                 HWRM_UNLOCK();
4158                 PMD_DRV_LOG(ERR,
4159                 "unable to map VNIC ID table address to physical memory\n");
4160                 return -ENOMEM;
4161         }
4162         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4163         HWRM_CHECK_RESULT();
4164         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4165
4166         HWRM_UNLOCK();
4167
4168         return rc;
4169 }
4170
4171 /*
4172  * This function queries the VNIC IDs  for a specified VF. It then calls
4173  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4174  * Then it calls the hwrm_cb function to program this new vnic configuration.
4175  */
4176 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4177         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4178         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4179 {
4180         struct bnxt_vnic_info vnic;
4181         int rc = 0;
4182         int i, num_vnic_ids;
4183         uint16_t *vnic_ids;
4184         size_t vnic_id_sz;
4185         size_t sz;
4186
4187         /* First query all VNIC ids */
4188         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4189         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4190                         RTE_CACHE_LINE_SIZE);
4191         if (vnic_ids == NULL)
4192                 return -ENOMEM;
4193
4194         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4195                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4196
4197         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4198
4199         if (num_vnic_ids < 0)
4200                 return num_vnic_ids;
4201
4202         /* Retrieve VNIC, update bd_stall then update */
4203
4204         for (i = 0; i < num_vnic_ids; i++) {
4205                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4206                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4207                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4208                 if (rc)
4209                         break;
4210                 if (vnic.mru <= 4)      /* Indicates unallocated */
4211                         continue;
4212
4213                 vnic_cb(&vnic, cbdata);
4214
4215                 rc = hwrm_cb(bp, &vnic);
4216                 if (rc)
4217                         break;
4218         }
4219
4220         rte_free(vnic_ids);
4221
4222         return rc;
4223 }
4224
4225 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4226                                               bool on)
4227 {
4228         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4229         struct hwrm_func_cfg_input req = {0};
4230         int rc;
4231
4232         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4233
4234         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4235         req.enables |= rte_cpu_to_le_32(
4236                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4237         req.vlan_antispoof_mode = on ?
4238                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4239                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4240         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4241
4242         HWRM_CHECK_RESULT();
4243         HWRM_UNLOCK();
4244
4245         return rc;
4246 }
4247
4248 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4249 {
4250         struct bnxt_vnic_info vnic;
4251         uint16_t *vnic_ids;
4252         size_t vnic_id_sz;
4253         int num_vnic_ids, i;
4254         size_t sz;
4255         int rc;
4256
4257         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4258         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4259                         RTE_CACHE_LINE_SIZE);
4260         if (vnic_ids == NULL)
4261                 return -ENOMEM;
4262
4263         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4264                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4265
4266         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4267         if (rc <= 0)
4268                 goto exit;
4269         num_vnic_ids = rc;
4270
4271         /*
4272          * Loop through to find the default VNIC ID.
4273          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4274          * by sending the hwrm_func_qcfg command to the firmware.
4275          */
4276         for (i = 0; i < num_vnic_ids; i++) {
4277                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4278                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4279                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4280                                         bp->pf.first_vf_id + vf);
4281                 if (rc)
4282                         goto exit;
4283                 if (vnic.func_default) {
4284                         rte_free(vnic_ids);
4285                         return vnic.fw_vnic_id;
4286                 }
4287         }
4288         /* Could not find a default VNIC. */
4289         PMD_DRV_LOG(ERR, "No default VNIC\n");
4290 exit:
4291         rte_free(vnic_ids);
4292         return rc;
4293 }
4294
4295 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4296                          uint16_t dst_id,
4297                          struct bnxt_filter_info *filter)
4298 {
4299         int rc = 0;
4300         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4301         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4302         uint32_t enables = 0;
4303
4304         if (filter->fw_em_filter_id != UINT64_MAX)
4305                 bnxt_hwrm_clear_em_filter(bp, filter);
4306
4307         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4308
4309         req.flags = rte_cpu_to_le_32(filter->flags);
4310
4311         enables = filter->enables |
4312               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4313         req.dst_id = rte_cpu_to_le_16(dst_id);
4314
4315         if (filter->ip_addr_type) {
4316                 req.ip_addr_type = filter->ip_addr_type;
4317                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4318         }
4319         if (enables &
4320             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4321                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4322         if (enables &
4323             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4324                 memcpy(req.src_macaddr, filter->src_macaddr,
4325                        RTE_ETHER_ADDR_LEN);
4326         if (enables &
4327             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4328                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4329                        RTE_ETHER_ADDR_LEN);
4330         if (enables &
4331             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4332                 req.ovlan_vid = filter->l2_ovlan;
4333         if (enables &
4334             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4335                 req.ivlan_vid = filter->l2_ivlan;
4336         if (enables &
4337             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4338                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4339         if (enables &
4340             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4341                 req.ip_protocol = filter->ip_protocol;
4342         if (enables &
4343             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4344                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4345         if (enables &
4346             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4347                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4348         if (enables &
4349             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4350                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4351         if (enables &
4352             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4353                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4354         if (enables &
4355             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4356                 req.mirror_vnic_id = filter->mirror_vnic_id;
4357
4358         req.enables = rte_cpu_to_le_32(enables);
4359
4360         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4361
4362         HWRM_CHECK_RESULT();
4363
4364         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4365         HWRM_UNLOCK();
4366
4367         return rc;
4368 }
4369
4370 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4371 {
4372         int rc = 0;
4373         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4374         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4375
4376         if (filter->fw_em_filter_id == UINT64_MAX)
4377                 return 0;
4378
4379         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4380
4381         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4382
4383         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4384
4385         HWRM_CHECK_RESULT();
4386         HWRM_UNLOCK();
4387
4388         filter->fw_em_filter_id = UINT64_MAX;
4389         filter->fw_l2_filter_id = UINT64_MAX;
4390
4391         return 0;
4392 }
4393
4394 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4395                          uint16_t dst_id,
4396                          struct bnxt_filter_info *filter)
4397 {
4398         int rc = 0;
4399         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4400         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4401                                                 bp->hwrm_cmd_resp_addr;
4402         uint32_t enables = 0;
4403
4404         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4405                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4406
4407         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4408
4409         req.flags = rte_cpu_to_le_32(filter->flags);
4410
4411         enables = filter->enables |
4412               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4413         req.dst_id = rte_cpu_to_le_16(dst_id);
4414
4415         if (filter->ip_addr_type) {
4416                 req.ip_addr_type = filter->ip_addr_type;
4417                 enables |=
4418                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4419         }
4420         if (enables &
4421             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4422                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4423         if (enables &
4424             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4425                 memcpy(req.src_macaddr, filter->src_macaddr,
4426                        RTE_ETHER_ADDR_LEN);
4427         if (enables &
4428             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4429                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4430         if (enables &
4431             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4432                 req.ip_protocol = filter->ip_protocol;
4433         if (enables &
4434             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4435                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4436         if (enables &
4437             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4438                 req.src_ipaddr_mask[0] =
4439                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4440         if (enables &
4441             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4442                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4443         if (enables &
4444             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4445                 req.dst_ipaddr_mask[0] =
4446                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4447         if (enables &
4448             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4449                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4450         if (enables &
4451             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4452                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4453         if (enables &
4454             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4455                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4456         if (enables &
4457             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4458                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4459         if (enables &
4460             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4461                 req.mirror_vnic_id = filter->mirror_vnic_id;
4462
4463         req.enables = rte_cpu_to_le_32(enables);
4464
4465         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4466
4467         HWRM_CHECK_RESULT();
4468
4469         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4470         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4471         HWRM_UNLOCK();
4472
4473         return rc;
4474 }
4475
4476 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4477                                 struct bnxt_filter_info *filter)
4478 {
4479         int rc = 0;
4480         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4481         struct hwrm_cfa_ntuple_filter_free_output *resp =
4482                                                 bp->hwrm_cmd_resp_addr;
4483
4484         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4485                 return 0;
4486
4487         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4488
4489         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4490
4491         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4492
4493         HWRM_CHECK_RESULT();
4494         HWRM_UNLOCK();
4495
4496         filter->fw_ntuple_filter_id = UINT64_MAX;
4497
4498         return 0;
4499 }
4500
4501 static int
4502 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4503 {
4504         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4505         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4506         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4507         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4508         uint16_t *ring_tbl = vnic->rss_table;
4509         int nr_ctxs = vnic->num_lb_ctxts;
4510         int max_rings = bp->rx_nr_rings;
4511         int i, j, k, cnt;
4512         int rc = 0;
4513
4514         for (i = 0, k = 0; i < nr_ctxs; i++) {
4515                 struct bnxt_rx_ring_info *rxr;
4516                 struct bnxt_cp_ring_info *cpr;
4517
4518                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4519
4520                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4521                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4522                 req.hash_mode_flags = vnic->hash_mode;
4523
4524                 req.ring_grp_tbl_addr =
4525                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4526                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4527                                      2 * sizeof(*ring_tbl));
4528                 req.hash_key_tbl_addr =
4529                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4530
4531                 req.ring_table_pair_index = i;
4532                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4533
4534                 for (j = 0; j < 64; j++) {
4535                         uint16_t ring_id;
4536
4537                         /* Find next active ring. */
4538                         for (cnt = 0; cnt < max_rings; cnt++) {
4539                                 if (rx_queue_state[k] !=
4540                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4541                                         break;
4542                                 if (++k == max_rings)
4543                                         k = 0;
4544                         }
4545
4546                         /* Return if no rings are active. */
4547                         if (cnt == max_rings) {
4548                                 HWRM_UNLOCK();
4549                                 return 0;
4550                         }
4551
4552                         /* Add rx/cp ring pair to RSS table. */
4553                         rxr = rxqs[k]->rx_ring;
4554                         cpr = rxqs[k]->cp_ring;
4555
4556                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4557                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4558                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4559                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4560
4561                         if (++k == max_rings)
4562                                 k = 0;
4563                 }
4564                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4565                                             BNXT_USE_CHIMP_MB);
4566
4567                 HWRM_CHECK_RESULT();
4568                 HWRM_UNLOCK();
4569         }
4570
4571         return rc;
4572 }
4573
4574 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4575 {
4576         unsigned int rss_idx, fw_idx, i;
4577
4578         if (!(vnic->rss_table && vnic->hash_type))
4579                 return 0;
4580
4581         if (BNXT_CHIP_THOR(bp))
4582                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4583
4584         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4585                 return 0;
4586
4587         if (vnic->rss_table && vnic->hash_type) {
4588                 /*
4589                  * Fill the RSS hash & redirection table with
4590                  * ring group ids for all VNICs
4591                  */
4592                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4593                         rss_idx++, fw_idx++) {
4594                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4595                                 fw_idx %= bp->rx_cp_nr_rings;
4596                                 if (vnic->fw_grp_ids[fw_idx] !=
4597                                     INVALID_HW_RING_ID)
4598                                         break;
4599                                 fw_idx++;
4600                         }
4601                         if (i == bp->rx_cp_nr_rings)
4602                                 return 0;
4603                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4604                 }
4605                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4606         }
4607
4608         return 0;
4609 }
4610
4611 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4612         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4613 {
4614         uint16_t flags;
4615
4616         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4617
4618         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4619         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4620
4621         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4622         req->num_cmpl_dma_aggr_during_int =
4623                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4624
4625         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4626
4627         /* min timer set to 1/2 of interrupt timer */
4628         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4629
4630         /* buf timer set to 1/4 of interrupt timer */
4631         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4632
4633         req->cmpl_aggr_dma_tmr_during_int =
4634                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4635
4636         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4637                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4638         req->flags = rte_cpu_to_le_16(flags);
4639 }
4640
4641 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4642                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4643 {
4644         struct hwrm_ring_aggint_qcaps_input req = {0};
4645         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4646         uint32_t enables;
4647         uint16_t flags;
4648         int rc;
4649
4650         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4651         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4652         HWRM_CHECK_RESULT();
4653
4654         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4655         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4656
4657         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4658                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4659         agg_req->flags = rte_cpu_to_le_16(flags);
4660         enables =
4661          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4662          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4663         agg_req->enables = rte_cpu_to_le_32(enables);
4664
4665         HWRM_UNLOCK();
4666         return rc;
4667 }
4668
4669 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4670                         struct bnxt_coal *coal, uint16_t ring_id)
4671 {
4672         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4673         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4674                                                 bp->hwrm_cmd_resp_addr;
4675         int rc;
4676
4677         /* Set ring coalesce parameters only for 100G NICs */
4678         if (BNXT_CHIP_THOR(bp)) {
4679                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4680                         return -1;
4681         } else if (bnxt_stratus_device(bp)) {
4682                 bnxt_hwrm_set_coal_params(coal, &req);
4683         } else {
4684                 return 0;
4685         }
4686
4687         HWRM_PREP(&req,
4688                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4689                   BNXT_USE_CHIMP_MB);
4690         req.ring_id = rte_cpu_to_le_16(ring_id);
4691         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4692         HWRM_CHECK_RESULT();
4693         HWRM_UNLOCK();
4694         return 0;
4695 }
4696
4697 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4698 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4699 {
4700         struct hwrm_func_backing_store_qcaps_input req = {0};
4701         struct hwrm_func_backing_store_qcaps_output *resp =
4702                 bp->hwrm_cmd_resp_addr;
4703         struct bnxt_ctx_pg_info *ctx_pg;
4704         struct bnxt_ctx_mem_info *ctx;
4705         int total_alloc_len;
4706         int rc, i;
4707
4708         if (!BNXT_CHIP_THOR(bp) ||
4709             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4710             BNXT_VF(bp) ||
4711             bp->ctx)
4712                 return 0;
4713
4714         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4715         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4716         HWRM_CHECK_RESULT_SILENT();
4717
4718         total_alloc_len = sizeof(*ctx);
4719         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4720                           RTE_CACHE_LINE_SIZE);
4721         if (!ctx) {
4722                 rc = -ENOMEM;
4723                 goto ctx_err;
4724         }
4725
4726         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4727                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4728                             RTE_CACHE_LINE_SIZE);
4729         if (!ctx_pg) {
4730                 rc = -ENOMEM;
4731                 goto ctx_err;
4732         }
4733         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4734                 ctx->tqm_mem[i] = ctx_pg;
4735
4736         bp->ctx = ctx;
4737         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4738         ctx->qp_min_qp1_entries =
4739                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4740         ctx->qp_max_l2_entries =
4741                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4742         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4743         ctx->srq_max_l2_entries =
4744                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4745         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4746         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4747         ctx->cq_max_l2_entries =
4748                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4749         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4750         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4751         ctx->vnic_max_vnic_entries =
4752                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4753         ctx->vnic_max_ring_table_entries =
4754                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4755         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4756         ctx->stat_max_entries =
4757                 rte_le_to_cpu_32(resp->stat_max_entries);
4758         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4759         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4760         ctx->tqm_min_entries_per_ring =
4761                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4762         ctx->tqm_max_entries_per_ring =
4763                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4764         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4765         if (!ctx->tqm_entries_multiple)
4766                 ctx->tqm_entries_multiple = 1;
4767         ctx->mrav_max_entries =
4768                 rte_le_to_cpu_32(resp->mrav_max_entries);
4769         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4770         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4771         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4772 ctx_err:
4773         HWRM_UNLOCK();
4774         return rc;
4775 }
4776
4777 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4778 {
4779         struct hwrm_func_backing_store_cfg_input req = {0};
4780         struct hwrm_func_backing_store_cfg_output *resp =
4781                 bp->hwrm_cmd_resp_addr;
4782         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4783         struct bnxt_ctx_pg_info *ctx_pg;
4784         uint32_t *num_entries;
4785         uint64_t *pg_dir;
4786         uint8_t *pg_attr;
4787         uint32_t ena;
4788         int i, rc;
4789
4790         if (!ctx)
4791                 return 0;
4792
4793         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4794         req.enables = rte_cpu_to_le_32(enables);
4795
4796         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4797                 ctx_pg = &ctx->qp_mem;
4798                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4799                 req.qp_num_qp1_entries =
4800                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4801                 req.qp_num_l2_entries =
4802                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4803                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4804                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4805                                       &req.qpc_pg_size_qpc_lvl,
4806                                       &req.qpc_page_dir);
4807         }
4808
4809         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4810                 ctx_pg = &ctx->srq_mem;
4811                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4812                 req.srq_num_l2_entries =
4813                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4814                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4815                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4816                                       &req.srq_pg_size_srq_lvl,
4817                                       &req.srq_page_dir);
4818         }
4819
4820         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4821                 ctx_pg = &ctx->cq_mem;
4822                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4823                 req.cq_num_l2_entries =
4824                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4825                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4826                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4827                                       &req.cq_pg_size_cq_lvl,
4828                                       &req.cq_page_dir);
4829         }
4830
4831         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4832                 ctx_pg = &ctx->vnic_mem;
4833                 req.vnic_num_vnic_entries =
4834                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4835                 req.vnic_num_ring_table_entries =
4836                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4837                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4838                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4839                                       &req.vnic_pg_size_vnic_lvl,
4840                                       &req.vnic_page_dir);
4841         }
4842
4843         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4844                 ctx_pg = &ctx->stat_mem;
4845                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4846                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4847                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4848                                       &req.stat_pg_size_stat_lvl,
4849                                       &req.stat_page_dir);
4850         }
4851
4852         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4853         num_entries = &req.tqm_sp_num_entries;
4854         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4855         pg_dir = &req.tqm_sp_page_dir;
4856         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4857         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4858                 if (!(enables & ena))
4859                         continue;
4860
4861                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4862
4863                 ctx_pg = ctx->tqm_mem[i];
4864                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4865                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4866         }
4867
4868         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4869         HWRM_CHECK_RESULT();
4870         HWRM_UNLOCK();
4871
4872         return rc;
4873 }
4874
4875 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4876 {
4877         struct hwrm_port_qstats_ext_input req = {0};
4878         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4879         struct bnxt_pf_info *pf = &bp->pf;
4880         int rc;
4881
4882         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4883               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4884                 return 0;
4885
4886         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4887
4888         req.port_id = rte_cpu_to_le_16(pf->port_id);
4889         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4890                 req.tx_stat_host_addr =
4891                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4892                 req.tx_stat_size =
4893                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4894         }
4895         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4896                 req.rx_stat_host_addr =
4897                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4898                 req.rx_stat_size =
4899                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4900         }
4901         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4902
4903         if (rc) {
4904                 bp->fw_rx_port_stats_ext_size = 0;
4905                 bp->fw_tx_port_stats_ext_size = 0;
4906         } else {
4907                 bp->fw_rx_port_stats_ext_size =
4908                         rte_le_to_cpu_16(resp->rx_stat_size);
4909                 bp->fw_tx_port_stats_ext_size =
4910                         rte_le_to_cpu_16(resp->tx_stat_size);
4911         }
4912
4913         HWRM_CHECK_RESULT();
4914         HWRM_UNLOCK();
4915
4916         return rc;
4917 }
4918
4919 int
4920 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4921 {
4922         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4923         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4924                 bp->hwrm_cmd_resp_addr;
4925         int rc = 0;
4926
4927         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4928         req.tunnel_type = type;
4929         req.dest_fid = bp->fw_fid;
4930         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4931         HWRM_CHECK_RESULT();
4932
4933         HWRM_UNLOCK();
4934
4935         return rc;
4936 }
4937
4938 int
4939 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4940 {
4941         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4942         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4943                 bp->hwrm_cmd_resp_addr;
4944         int rc = 0;
4945
4946         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4947         req.tunnel_type = type;
4948         req.dest_fid = bp->fw_fid;
4949         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4950         HWRM_CHECK_RESULT();
4951
4952         HWRM_UNLOCK();
4953
4954         return rc;
4955 }
4956
4957 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4958 {
4959         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4960         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4961                 bp->hwrm_cmd_resp_addr;
4962         int rc = 0;
4963
4964         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4965         req.src_fid = bp->fw_fid;
4966         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4967         HWRM_CHECK_RESULT();
4968
4969         if (type)
4970                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4971
4972         HWRM_UNLOCK();
4973
4974         return rc;
4975 }
4976
4977 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4978                                    uint16_t *dst_fid)
4979 {
4980         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4981         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4982                 bp->hwrm_cmd_resp_addr;
4983         int rc = 0;
4984
4985         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4986         req.src_fid = bp->fw_fid;
4987         req.tunnel_type = tun_type;
4988         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4989         HWRM_CHECK_RESULT();
4990
4991         if (dst_fid)
4992                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4993
4994         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4995
4996         HWRM_UNLOCK();
4997
4998         return rc;
4999 }
5000
5001 int bnxt_hwrm_set_mac(struct bnxt *bp)
5002 {
5003         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5004         struct hwrm_func_vf_cfg_input req = {0};
5005         int rc = 0;
5006
5007         if (!BNXT_VF(bp))
5008                 return 0;
5009
5010         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5011
5012         req.enables =
5013                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5014         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5015
5016         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5017
5018         HWRM_CHECK_RESULT();
5019
5020         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5021         HWRM_UNLOCK();
5022
5023         return rc;
5024 }
5025
5026 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5027 {
5028         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5029         struct hwrm_func_drv_if_change_input req = {0};
5030         uint32_t flags;
5031         int rc;
5032
5033         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5034                 return 0;
5035
5036         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5037          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5038          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5039          */
5040         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5041                 return 0;
5042
5043         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5044
5045         if (up)
5046                 req.flags =
5047                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5048
5049         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5050
5051         HWRM_CHECK_RESULT();
5052         flags = rte_le_to_cpu_32(resp->flags);
5053         HWRM_UNLOCK();
5054
5055         if (!up)
5056                 return 0;
5057
5058         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5059                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5060                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5061         }
5062
5063         return 0;
5064 }
5065
5066 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5067 {
5068         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5069         struct bnxt_error_recovery_info *info = bp->recovery_info;
5070         struct hwrm_error_recovery_qcfg_input req = {0};
5071         uint32_t flags = 0;
5072         unsigned int i;
5073         int rc;
5074
5075         /* Older FW does not have error recovery support */
5076         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5077                 return 0;
5078
5079         if (!info) {
5080                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5081                                    sizeof(*info), 0);
5082                 bp->recovery_info = info;
5083                 if (info == NULL)
5084                         return -ENOMEM;
5085         } else {
5086                 memset(info, 0, sizeof(*info));
5087         }
5088
5089         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5090
5091         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5092
5093         HWRM_CHECK_RESULT();
5094
5095         flags = rte_le_to_cpu_32(resp->flags);
5096         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5097                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5098         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5099                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5100
5101         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5102             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5103                 rc = -EINVAL;
5104                 goto err;
5105         }
5106
5107         /* FW returned values are in units of 100msec */
5108         info->driver_polling_freq =
5109                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5110         info->master_func_wait_period =
5111                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5112         info->normal_func_wait_period =
5113                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5114         info->master_func_wait_period_after_reset =
5115                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5116         info->max_bailout_time_after_reset =
5117                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5118         info->status_regs[BNXT_FW_STATUS_REG] =
5119                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5120         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5121                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5122         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5123                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5124         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5125                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5126         info->reg_array_cnt =
5127                 rte_le_to_cpu_32(resp->reg_array_cnt);
5128
5129         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5130                 rc = -EINVAL;
5131                 goto err;
5132         }
5133
5134         for (i = 0; i < info->reg_array_cnt; i++) {
5135                 info->reset_reg[i] =
5136                         rte_le_to_cpu_32(resp->reset_reg[i]);
5137                 info->reset_reg_val[i] =
5138                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5139                 info->delay_after_reset[i] =
5140                         resp->delay_after_reset[i];
5141         }
5142 err:
5143         HWRM_UNLOCK();
5144
5145         /* Map the FW status registers */
5146         if (!rc)
5147                 rc = bnxt_map_fw_health_status_regs(bp);
5148
5149         if (rc) {
5150                 rte_free(bp->recovery_info);
5151                 bp->recovery_info = NULL;
5152         }
5153         return rc;
5154 }
5155
5156 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5157 {
5158         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5159         struct hwrm_fw_reset_input req = {0};
5160         int rc;
5161
5162         if (!BNXT_PF(bp))
5163                 return -EOPNOTSUPP;
5164
5165         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5166
5167         req.embedded_proc_type =
5168                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5169         req.selfrst_status =
5170                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5171         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5172
5173         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5174                                     BNXT_USE_KONG(bp));
5175
5176         HWRM_CHECK_RESULT();
5177         HWRM_UNLOCK();
5178
5179         return rc;
5180 }
5181
5182 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5183 {
5184         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5185         struct hwrm_port_ts_query_input req = {0};
5186         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5187         uint32_t flags = 0;
5188         int rc;
5189
5190         if (!ptp)
5191                 return 0;
5192
5193         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5194
5195         switch (path) {
5196         case BNXT_PTP_FLAGS_PATH_TX:
5197                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5198                 break;
5199         case BNXT_PTP_FLAGS_PATH_RX:
5200                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5201                 break;
5202         case BNXT_PTP_FLAGS_CURRENT_TIME:
5203                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5204                 break;
5205         }
5206
5207         req.flags = rte_cpu_to_le_32(flags);
5208         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5209
5210         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5211
5212         HWRM_CHECK_RESULT();
5213
5214         if (timestamp) {
5215                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5216                 *timestamp |=
5217                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5218         }
5219         HWRM_UNLOCK();
5220
5221         return rc;
5222 }
5223
5224 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5225 {
5226         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5227                                         bp->hwrm_cmd_resp_addr;
5228         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5229         uint32_t flags = 0;
5230         int rc = 0;
5231
5232         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
5233                 return rc;
5234
5235         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5236                 PMD_DRV_LOG(DEBUG,
5237                             "Not a PF or trusted VF. Command not supported\n");
5238                 return 0;
5239         }
5240
5241         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5242         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5243
5244         HWRM_CHECK_RESULT();
5245         flags = rte_le_to_cpu_32(resp->flags);
5246         HWRM_UNLOCK();
5247
5248         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5249                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5250                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5251         }
5252
5253         return rc;
5254 }
5255
5256 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5257 {
5258         int rc = 0;
5259
5260         struct hwrm_cfa_counter_qcaps_input req = {0};
5261         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5262
5263         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5264                 PMD_DRV_LOG(DEBUG,
5265                             "Not a PF or trusted VF. Command not supported\n");
5266                 return 0;
5267         }
5268
5269         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5270         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5271         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5272
5273         HWRM_CHECK_RESULT();
5274         if (max_fc)
5275                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5276         HWRM_UNLOCK();
5277
5278         PMD_DRV_LOG(DEBUG, "max_fc = %d\n", *max_fc);
5279         return 0;
5280 }
5281
5282 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5283 {
5284         int rc = 0;
5285         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5286         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5287
5288         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5289                 PMD_DRV_LOG(DEBUG,
5290                             "Not a PF or trusted VF. Command not supported\n");
5291                 return 0;
5292         }
5293
5294         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5295
5296         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5297         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5298         req.page_dir = rte_cpu_to_le_64(dma_addr);
5299
5300         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5301
5302         HWRM_CHECK_RESULT();
5303         if (ctx_id) {
5304                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5305                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5306         }
5307         HWRM_UNLOCK();
5308
5309         return 0;
5310 }
5311
5312 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5313 {
5314         int rc = 0;
5315         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5316         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5317
5318         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5319                 PMD_DRV_LOG(DEBUG,
5320                             "Not a PF or trusted VF. Command not supported\n");
5321                 return 0;
5322         }
5323
5324         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5325
5326         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5327
5328         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5329
5330         HWRM_CHECK_RESULT();
5331         HWRM_UNLOCK();
5332
5333         return rc;
5334 }
5335
5336 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5337                               uint16_t cntr, uint16_t ctx_id,
5338                               uint32_t num_entries, bool enable)
5339 {
5340         struct hwrm_cfa_counter_cfg_input req = {0};
5341         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5342         uint16_t flags = 0;
5343         int rc;
5344
5345         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5346                 PMD_DRV_LOG(DEBUG,
5347                             "Not a PF or trusted VF. Command not supported\n");
5348                 return 0;
5349         }
5350
5351         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5352
5353         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5354         req.counter_type = rte_cpu_to_le_16(cntr);
5355         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5356                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5357         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5358         if (dir == BNXT_DIR_RX)
5359                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5360         else if (dir == BNXT_DIR_TX)
5361                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5362         req.flags = rte_cpu_to_le_16(flags);
5363         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5364         req.num_entries = rte_cpu_to_le_32(num_entries);
5365
5366         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5367         HWRM_CHECK_RESULT();
5368         HWRM_UNLOCK();
5369
5370         return 0;
5371 }
5372
5373 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5374                                  enum bnxt_flow_dir dir,
5375                                  uint16_t cntr,
5376                                  uint16_t num_entries)
5377 {
5378         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5379         struct hwrm_cfa_counter_qstats_input req = {0};
5380         uint16_t flow_ctx_id = 0;
5381         uint16_t flags = 0;
5382         int rc = 0;
5383
5384         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5385                 PMD_DRV_LOG(DEBUG,
5386                             "Not a PF or trusted VF. Command not supported\n");
5387                 return 0;
5388         }
5389
5390         if (dir == BNXT_DIR_RX) {
5391                 flow_ctx_id = bp->rx_fc_in_tbl.ctx_id;
5392                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5393         } else if (dir == BNXT_DIR_TX) {
5394                 flow_ctx_id = bp->tx_fc_in_tbl.ctx_id;
5395                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5396         }
5397
5398         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5399         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5400         req.counter_type = rte_cpu_to_le_16(cntr);
5401         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5402         req.num_entries = rte_cpu_to_le_16(num_entries);
5403         req.flags = rte_cpu_to_le_16(flags);
5404         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5405
5406         HWRM_CHECK_RESULT();
5407         HWRM_UNLOCK();
5408
5409         return 0;
5410 }