drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SHORT_CMD_TIMEOUT          50000
  31 #define HWRM_SPEC_CODE_1_8_3            0x10803
  32 #define HWRM_VERSION_1_9_1              0x10901
  33 #define HWRM_VERSION_1_9_2              0x10903
  34
  35 struct bnxt_plcmodes_cfg {
  36         uint32_t        flags;
  37         uint16_t        jumbo_thresh;
  38         uint16_t        hds_offset;
  39         uint16_t        hds_threshold;
  40 };
  41
  42 static int page_getenum(size_t size)
  43 {
  44         if (size <= 1 << 4)
  45                 return 4;
  46         if (size <= 1 << 12)
  47                 return 12;
  48         if (size <= 1 << 13)
  49                 return 13;
  50         if (size <= 1 << 16)
  51                 return 16;
  52         if (size <= 1 << 21)
  53                 return 21;
  54         if (size <= 1 << 22)
  55                 return 22;
  56         if (size <= 1 << 30)
  57                 return 30;
  58         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  59         return sizeof(void *) * 8 - 1;
  60 }
  61
  62 static int page_roundup(size_t size)
  63 {
  64         return 1 << page_getenum(size);
  65 }
  66
  67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  68                                   uint8_t *pg_attr,
  69                                   uint64_t *pg_dir)
  70 {
  71         if (rmem->nr_pages > 1) {
  72                 *pg_attr = 1;
  73                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  74         } else {
  75                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  76         }
  77 }
  78
  79 /*
  80  * HWRM Functions (sent to HWRM)
  81  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  82  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  83  * command was failed by the ChiMP.
  84  */
  85
  86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  87                                   uint32_t msg_len, bool use_kong_mb)
  88 {
  89         unsigned int i;
  90         struct input *req = msg;
  91         struct output *resp = bp->hwrm_cmd_resp_addr;
  92         uint32_t *data = msg;
  93         uint8_t *bar;
  94         uint8_t *valid;
  95         uint16_t max_req_len = bp->max_req_len;
  96         struct hwrm_short_input short_input = { 0 };
  97         uint16_t bar_offset = use_kong_mb ?
  98                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  99         uint16_t mb_trigger_offset = use_kong_mb ?
 100                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 101         uint32_t timeout;
 102
 103         /* Do not send HWRM commands to firmware in error state */
 104         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 105                 return 0;
 106
 107         /* For VER_GET command, set timeout as 50ms */
 108         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 109                 timeout = HWRM_SHORT_CMD_TIMEOUT;
 110         else
 111                 timeout = HWRM_CMD_TIMEOUT;
 112
 113         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 114             msg_len > bp->max_req_len) {
 115                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 116
 117                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 118                 memcpy(short_cmd_req, req, msg_len);
 119
 120                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 121                 short_input.signature = rte_cpu_to_le_16(
 122                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 123                 short_input.size = rte_cpu_to_le_16(msg_len);
 124                 short_input.req_addr =
 125                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 126
 127                 data = (uint32_t *)&short_input;
 128                 msg_len = sizeof(short_input);
 129
 130                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 131         }
 132
 133         /* Write request msg to hwrm channel */
 134         for (i = 0; i < msg_len; i += 4) {
 135                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 136                 rte_write32(*data, bar);
 137                 data++;
 138         }
 139
 140         /* Zero the rest of the request space */
 141         for (; i < max_req_len; i += 4) {
 142                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 143                 rte_write32(0, bar);
 144         }
 145
 146         /* Ring channel doorbell */
 147         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 148         rte_write32(1, bar);
 149
 150         /* Poll for the valid bit */
 151         for (i = 0; i < timeout; i++) {
 152                 /* Sanity check on the resp->resp_len */
 153                 rte_cio_rmb();
 154                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 155                         /* Last byte of resp contains the valid key */
 156                         valid = (uint8_t *)resp + resp->resp_len - 1;
 157                         if (*valid == HWRM_RESP_VALID_KEY)
 158                                 break;
 159                 }
 160                 rte_delay_us(1);
 161         }
 162
 163         if (i >= timeout) {
 164                 /* Suppress VER_GET timeout messages during reset recovery */
 165                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 166                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 167                         return -ETIMEDOUT;
 168
 169                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 170                             req->req_type);
 171                 return -ETIMEDOUT;
 172         }
 173         return 0;
 174 }
 175
 176 /*
 177  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 178  * spinlock, and does initial processing.
 179  *
 180  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 181  * releases the spinlock only if it returns.  If the regular int return codes
 182  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 183  * directly, rather it should be copied and modified to suit the function.
 184  *
 185  * HWRM_UNLOCK() must be called after all response processing is completed.
 186  */
 187 #define HWRM_PREP(req, type, kong) do { \
 188         rte_spinlock_lock(&bp->hwrm_lock); \
 189         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 190         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 191         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 192         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 193                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 194         req.target_id = rte_cpu_to_le_16(0xffff); \
 195         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 196 } while (0)
 197
 198 #define HWRM_CHECK_RESULT_SILENT() do {\
 199         if (rc) { \
 200                 rte_spinlock_unlock(&bp->hwrm_lock); \
 201                 return rc; \
 202         } \
 203         if (resp->error_code) { \
 204                 rc = rte_le_to_cpu_16(resp->error_code); \
 205                 rte_spinlock_unlock(&bp->hwrm_lock); \
 206                 return rc; \
 207         } \
 208 } while (0)
 209
 210 #define HWRM_CHECK_RESULT() do {\
 211         if (rc) { \
 212                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 213                 rte_spinlock_unlock(&bp->hwrm_lock); \
 214                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 215                         rc = -EACCES; \
 216                 else if (rc > 0) \
 217                         rc = -EINVAL; \
 218                 return rc; \
 219         } \
 220         if (resp->error_code) { \
 221                 rc = rte_le_to_cpu_16(resp->error_code); \
 222                 if (resp->resp_len >= 16) { \
 223                         struct hwrm_err_output *tmp_hwrm_err_op = \
 224                                                 (void *)resp; \
 225                         PMD_DRV_LOG(ERR, \
 226                                 "error %d:%d:%08x:%04x\n", \
 227                                 rc, tmp_hwrm_err_op->cmd_err, \
 228                                 rte_le_to_cpu_32(\
 229                                         tmp_hwrm_err_op->opaque_0), \
 230                                 rte_le_to_cpu_16(\
 231                                         tmp_hwrm_err_op->opaque_1)); \
 232                 } else { \
 233                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 234                 } \
 235                 rte_spinlock_unlock(&bp->hwrm_lock); \
 236                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 237                         rc = -EACCES; \
 238                 else if (rc > 0) \
 239                         rc = -EINVAL; \
 240                 return rc; \
 241         } \
 242 } while (0)
 243
 244 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 245
 246 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 247 {
 248         int rc = 0;
 249         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 250         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 251
 252         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 253         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 254         req.mask = 0;
 255
 256         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 257
 258         HWRM_CHECK_RESULT();
 259         HWRM_UNLOCK();
 260
 261         return rc;
 262 }
 263
 264 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 265                                  struct bnxt_vnic_info *vnic,
 266                                  uint16_t vlan_count,
 267                                  struct bnxt_vlan_table_entry *vlan_table)
 268 {
 269         int rc = 0;
 270         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 271         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 272         uint32_t mask = 0;
 273
 274         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 275                 return rc;
 276
 277         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 278         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 279
 280         /* FIXME add multicast flag, when multicast adding options is supported
 281          * by ethtool.
 282          */
 283         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 284                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 285         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 286                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 287         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 288                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 289         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 290                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 291         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 292                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 293         if (vnic->mc_addr_cnt) {
 294                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 295                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 296                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 297         }
 298         if (vlan_table) {
 299                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 300                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 301                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 302                          rte_mem_virt2iova(vlan_table));
 303                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 304         }
 305         req.mask = rte_cpu_to_le_32(mask);
 306
 307         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 308
 309         HWRM_CHECK_RESULT();
 310         HWRM_UNLOCK();
 311
 312         return rc;
 313 }
 314
 315 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 316                         uint16_t vlan_count,
 317                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 318 {
 319         int rc = 0;
 320         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 321         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 322                                                 bp->hwrm_cmd_resp_addr;
 323
 324         /*
 325          * Older HWRM versions did not support this command, and the set_rx_mask
 326          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 327          * removed from set_rx_mask call, and this command was added.
 328          *
 329          * This command is also present from 1.7.8.11 and higher,
 330          * as well as 1.7.8.0
 331          */
 332         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 333                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 334                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 335                                         (11)))
 336                                 return 0;
 337                 }
 338         }
 339         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 340         req.fid = rte_cpu_to_le_16(fid);
 341
 342         req.vlan_tag_mask_tbl_addr =
 343                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 344         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 345
 346         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 347
 348         HWRM_CHECK_RESULT();
 349         HWRM_UNLOCK();
 350
 351         return rc;
 352 }
 353
 354 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 355                            struct bnxt_filter_info *filter)
 356 {
 357         int rc = 0;
 358         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 359         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 360
 361         if (filter->fw_l2_filter_id == UINT64_MAX)
 362                 return 0;
 363
 364         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 365
 366         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 367
 368         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 369
 370         HWRM_CHECK_RESULT();
 371         HWRM_UNLOCK();
 372
 373         filter->fw_l2_filter_id = UINT64_MAX;
 374
 375         return 0;
 376 }
 377
 378 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 379                          uint16_t dst_id,
 380                          struct bnxt_filter_info *filter)
 381 {
 382         int rc = 0;
 383         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 384         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 385         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 386         const struct rte_eth_vmdq_rx_conf *conf =
 387                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 388         uint32_t enables = 0;
 389         uint16_t j = dst_id - 1;
 390
 391         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 392         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 393             conf->pool_map[j].pools & (1UL << j)) {
 394                 PMD_DRV_LOG(DEBUG,
 395                         "Add vlan %u to vmdq pool %u\n",
 396                         conf->pool_map[j].vlan_id, j);
 397
 398                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 399                 filter->enables |=
 400                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 401                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 402         }
 403
 404         if (filter->fw_l2_filter_id != UINT64_MAX)
 405                 bnxt_hwrm_clear_l2_filter(bp, filter);
 406
 407         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 408
 409         req.flags = rte_cpu_to_le_32(filter->flags);
 410         req.flags |=
 411         rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
 412
 413         enables = filter->enables |
 414               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 415         req.dst_id = rte_cpu_to_le_16(dst_id);
 416
 417         if (enables &
 418             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 419                 memcpy(req.l2_addr, filter->l2_addr,
 420                        RTE_ETHER_ADDR_LEN);
 421         if (enables &
 422             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 423                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 424                        RTE_ETHER_ADDR_LEN);
 425         if (enables &
 426             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 427                 req.l2_ovlan = filter->l2_ovlan;
 428         if (enables &
 429             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 430                 req.l2_ivlan = filter->l2_ivlan;
 431         if (enables &
 432             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 433                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 434         if (enables &
 435             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 436                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 437         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 438                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 439         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 440                 req.src_type = filter->src_type;
 441
 442         req.enables = rte_cpu_to_le_32(enables);
 443
 444         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 445
 446         HWRM_CHECK_RESULT();
 447
 448         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 449         HWRM_UNLOCK();
 450
 451         return rc;
 452 }
 453
 454 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 455 {
 456         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 457         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 458         uint32_t flags = 0;
 459         int rc;
 460
 461         if (!ptp)
 462                 return 0;
 463
 464         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 465
 466         if (ptp->rx_filter)
 467                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 468         else
 469                 flags |=
 470                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 471         if (ptp->tx_tstamp_en)
 472                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 473         else
 474                 flags |=
 475                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 476         req.flags = rte_cpu_to_le_32(flags);
 477         req.enables = rte_cpu_to_le_32
 478                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 479         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 480
 481         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 482         HWRM_UNLOCK();
 483
 484         return rc;
 485 }
 486
 487 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 488 {
 489         int rc = 0;
 490         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 491         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 492         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 493
 494 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 495         if (ptp)
 496                 return 0;
 497
 498         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 499
 500         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 501
 502         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 503
 504         HWRM_CHECK_RESULT();
 505
 506         if (!BNXT_CHIP_THOR(bp) &&
 507             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 508                 return 0;
 509
 510         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 511                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 512
 513         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 514         if (!ptp)
 515                 return -ENOMEM;
 516
 517         if (!BNXT_CHIP_THOR(bp)) {
 518                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 519                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 520                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 521                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 522                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 523                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 524                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 525                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 526                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 527                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 528                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 529                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 530                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 531                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 532                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 533                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 534                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 535                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 536         }
 537
 538         ptp->bp = bp;
 539         bp->ptp_cfg = ptp;
 540
 541         return 0;
 542 }
 543
 544 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 545 {
 546         int rc = 0;
 547         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 548         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 549         uint16_t new_max_vfs;
 550         uint32_t flags;
 551         int i;
 552
 553         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 554
 555         req.fid = rte_cpu_to_le_16(0xffff);
 556
 557         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 558
 559         HWRM_CHECK_RESULT();
 560
 561         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 562         flags = rte_le_to_cpu_32(resp->flags);
 563         if (BNXT_PF(bp)) {
 564                 bp->pf.port_id = resp->port_id;
 565                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 566                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 567                 new_max_vfs = bp->pdev->max_vfs;
 568                 if (new_max_vfs != bp->pf.max_vfs) {
 569                         if (bp->pf.vf_info)
 570                                 rte_free(bp->pf.vf_info);
 571                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 572                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 573                         bp->pf.max_vfs = new_max_vfs;
 574                         for (i = 0; i < new_max_vfs; i++) {
 575                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 576                                 bp->pf.vf_info[i].vlan_table =
 577                                         rte_zmalloc("VF VLAN table",
 578                                                     getpagesize(),
 579                                                     getpagesize());
 580                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 581                                         PMD_DRV_LOG(ERR,
 582                                         "Fail to alloc VLAN table for VF %d\n",
 583                                         i);
 584                                 else
 585                                         rte_mem_lock_page(
 586                                                 bp->pf.vf_info[i].vlan_table);
 587                                 bp->pf.vf_info[i].vlan_as_table =
 588                                         rte_zmalloc("VF VLAN AS table",
 589                                                     getpagesize(),
 590                                                     getpagesize());
 591                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 592                                         PMD_DRV_LOG(ERR,
 593                                         "Alloc VLAN AS table for VF %d fail\n",
 594                                         i);
 595                                 else
 596                                         rte_mem_lock_page(
 597                                                bp->pf.vf_info[i].vlan_as_table);
 598                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 599                         }
 600                 }
 601         }
 602
 603         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 604         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 605         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 606         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 607         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 608         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 609         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 610         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 611         bp->max_l2_ctx =
 612                 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
 613         /* TODO: For now, do not support VMDq/RFS on VFs. */
 614         if (BNXT_PF(bp)) {
 615                 if (bp->pf.max_vfs)
 616                         bp->max_vnics = 1;
 617                 else
 618                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 619         } else {
 620                 bp->max_vnics = 1;
 621         }
 622         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 623         if (BNXT_PF(bp)) {
 624                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 625                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 626                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 627                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 628                         HWRM_UNLOCK();
 629                         bnxt_hwrm_ptp_qcfg(bp);
 630                 }
 631         }
 632
 633         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 634                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 635
 636         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 637                 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 638                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 639         } else {
 640                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 641         }
 642
 643         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 644                 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 645         else
 646                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 647
 648         HWRM_UNLOCK();
 649
 650         return rc;
 651 }
 652
 653 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 654 {
 655         int rc;
 656
 657         rc = __bnxt_hwrm_func_qcaps(bp);
 658         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 659                 rc = bnxt_alloc_ctx_mem(bp);
 660                 if (rc)
 661                         return rc;
 662
 663                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 664                 if (!rc)
 665                         bp->flags |= BNXT_FLAG_NEW_RM;
 666         }
 667
 668         return rc;
 669 }
 670
 671 int bnxt_hwrm_func_reset(struct bnxt *bp)
 672 {
 673         int rc = 0;
 674         struct hwrm_func_reset_input req = {.req_type = 0 };
 675         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 676
 677         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 678
 679         req.enables = rte_cpu_to_le_32(0);
 680
 681         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 682
 683         HWRM_CHECK_RESULT();
 684         HWRM_UNLOCK();
 685
 686         return rc;
 687 }
 688
 689 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 690 {
 691         int rc;
 692         uint32_t flags = 0;
 693         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 694         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 695
 696         if (bp->flags & BNXT_FLAG_REGISTERED)
 697                 return 0;
 698
 699         flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 700         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 701                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 702
 703         /* PFs and trusted VFs should indicate the support of the
 704          * Master capability on non Stingray platform
 705          */
 706         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 707                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 708
 709         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 710         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 711                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 712         req.ver_maj = RTE_VER_YEAR;
 713         req.ver_min = RTE_VER_MONTH;
 714         req.ver_upd = RTE_VER_MINOR;
 715
 716         if (BNXT_PF(bp)) {
 717                 req.enables |= rte_cpu_to_le_32(
 718                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 719                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 720                        RTE_MIN(sizeof(req.vf_req_fwd),
 721                                sizeof(bp->pf.vf_req_fwd)));
 722
 723                 /*
 724                  * PF can sniff HWRM API issued by VF. This can be set up by
 725                  * linux driver and inherited by the DPDK PF driver. Clear
 726                  * this HWRM sniffer list in FW because DPDK PF driver does
 727                  * not support this.
 728                  */
 729                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 730         }
 731
 732         req.flags = rte_cpu_to_le_32(flags);
 733
 734         req.async_event_fwd[0] |=
 735                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 736                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 737                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 738                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 739         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 740                 req.async_event_fwd[0] |=
 741                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 742         req.async_event_fwd[1] |=
 743                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 744                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 745
 746         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 747
 748         HWRM_CHECK_RESULT();
 749
 750         flags = rte_le_to_cpu_32(resp->flags);
 751         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 752                 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
 753
 754         HWRM_UNLOCK();
 755
 756         bp->flags |= BNXT_FLAG_REGISTERED;
 757
 758         return rc;
 759 }
 760
 761 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 762 {
 763         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 764                 return 0;
 765
 766         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 767 }
 768
 769 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 770 {
 771         int rc;
 772         uint32_t flags = 0;
 773         uint32_t enables;
 774         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 775         struct hwrm_func_vf_cfg_input req = {0};
 776
 777         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 778
 779         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 780                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 781                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 782                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 783                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 784
 785         if (BNXT_HAS_RING_GRPS(bp)) {
 786                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 787                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 788         }
 789
 790         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 791         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 792                                             AGG_RING_MULTIPLIER);
 793         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
 794                                              bp->tx_nr_rings +
 795                                              BNXT_NUM_ASYNC_CPR(bp));
 796         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 797                                               bp->tx_nr_rings +
 798                                               BNXT_NUM_ASYNC_CPR(bp));
 799         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 800         if (bp->vf_resv_strategy ==
 801             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 802                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 803                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 804                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 805                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 806                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 807                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 808         }
 809
 810         if (test)
 811                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 812                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 813                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 814                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 815                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 816                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 817
 818         if (test && BNXT_HAS_RING_GRPS(bp))
 819                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 820
 821         req.flags = rte_cpu_to_le_32(flags);
 822         req.enables |= rte_cpu_to_le_32(enables);
 823
 824         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 825
 826         if (test)
 827                 HWRM_CHECK_RESULT_SILENT();
 828         else
 829                 HWRM_CHECK_RESULT();
 830
 831         HWRM_UNLOCK();
 832         return rc;
 833 }
 834
 835 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 836 {
 837         int rc;
 838         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 839         struct hwrm_func_resource_qcaps_input req = {0};
 840
 841         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 842         req.fid = rte_cpu_to_le_16(0xffff);
 843
 844         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 845
 846         HWRM_CHECK_RESULT();
 847
 848         if (BNXT_VF(bp)) {
 849                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 850                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 851                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 852                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 853                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 854                 /* func_resource_qcaps does not return max_rx_em_flows.
 855                  * So use the value provided by func_qcaps.
 856                  */
 857                 bp->max_l2_ctx =
 858                         rte_le_to_cpu_16(resp->max_l2_ctxs) +
 859                         bp->max_rx_em_flows;
 860                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 861                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 862         }
 863         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 864         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 865         if (bp->vf_resv_strategy >
 866             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 867                 bp->vf_resv_strategy =
 868                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 869
 870         HWRM_UNLOCK();
 871         return rc;
 872 }
 873
 874 int bnxt_hwrm_ver_get(struct bnxt *bp)
 875 {
 876         int rc = 0;
 877         struct hwrm_ver_get_input req = {.req_type = 0 };
 878         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 879         uint32_t fw_version;
 880         uint16_t max_resp_len;
 881         char type[RTE_MEMZONE_NAMESIZE];
 882         uint32_t dev_caps_cfg;
 883
 884         bp->max_req_len = HWRM_MAX_REQ_LEN;
 885         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 886
 887         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 888         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 889         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 890
 891         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 892
 893         if (bp->flags & BNXT_FLAG_FW_RESET)
 894                 HWRM_CHECK_RESULT_SILENT();
 895         else
 896                 HWRM_CHECK_RESULT();
 897
 898         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 899                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 900                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 901                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 902         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 903                      (resp->hwrm_fw_min_8b << 16) |
 904                      (resp->hwrm_fw_bld_8b << 8) |
 905                      resp->hwrm_fw_rsvd_8b;
 906         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 907                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 908
 909         fw_version = resp->hwrm_intf_maj_8b << 16;
 910         fw_version |= resp->hwrm_intf_min_8b << 8;
 911         fw_version |= resp->hwrm_intf_upd_8b;
 912         bp->hwrm_spec_code = fw_version;
 913
 914         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 915                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 916                 rc = -EINVAL;
 917                 goto error;
 918         }
 919
 920         if (bp->max_req_len > resp->max_req_win_len) {
 921                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 922                 rc = -EINVAL;
 923         }
 924         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 925         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 926         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 927                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 928
 929         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 930         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 931
 932         if (bp->max_resp_len != max_resp_len) {
 933                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 934                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 935                         bp->pdev->addr.devid, bp->pdev->addr.function);
 936
 937                 rte_free(bp->hwrm_cmd_resp_addr);
 938
 939                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 940                 if (bp->hwrm_cmd_resp_addr == NULL) {
 941                         rc = -ENOMEM;
 942                         goto error;
 943                 }
 944                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 945                 bp->hwrm_cmd_resp_dma_addr =
 946                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 947                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
 948                         PMD_DRV_LOG(ERR,
 949                         "Unable to map response buffer to physical memory.\n");
 950                         rc = -ENOMEM;
 951                         goto error;
 952                 }
 953                 bp->max_resp_len = max_resp_len;
 954         }
 955
 956         if ((dev_caps_cfg &
 957                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 958             (dev_caps_cfg &
 959              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 960                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 961                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 962         }
 963
 964         if (((dev_caps_cfg &
 965               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 966              (dev_caps_cfg &
 967               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
 968             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
 969                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
 970                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 971                         bp->pdev->addr.devid, bp->pdev->addr.function);
 972
 973                 rte_free(bp->hwrm_short_cmd_req_addr);
 974
 975                 bp->hwrm_short_cmd_req_addr =
 976                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
 977                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 978                         rc = -ENOMEM;
 979                         goto error;
 980                 }
 981                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 982                 bp->hwrm_short_cmd_req_dma_addr =
 983                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 984                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
 985                         rte_free(bp->hwrm_short_cmd_req_addr);
 986                         PMD_DRV_LOG(ERR,
 987                                 "Unable to map buffer to physical memory.\n");
 988                         rc = -ENOMEM;
 989                         goto error;
 990                 }
 991         }
 992         if (dev_caps_cfg &
 993             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
 994                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
 995                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
 996         }
 997         if (dev_caps_cfg &
 998             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
 999                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1000
1001 error:
1002         HWRM_UNLOCK();
1003         return rc;
1004 }
1005
1006 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1007 {
1008         int rc;
1009         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1010         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1011
1012         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1013                 return 0;
1014
1015         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1016         req.flags = flags;
1017
1018         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1019
1020         HWRM_CHECK_RESULT();
1021         HWRM_UNLOCK();
1022
1023         return rc;
1024 }
1025
1026 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1027 {
1028         int rc = 0;
1029         struct hwrm_port_phy_cfg_input req = {0};
1030         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1031         uint32_t enables = 0;
1032
1033         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1034
1035         if (conf->link_up) {
1036                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1037                 if (bp->link_info.auto_mode && conf->link_speed) {
1038                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1039                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1040                 }
1041
1042                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1043                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1044                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1045                 /*
1046                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1047                  * any auto mode, even "none".
1048                  */
1049                 if (!conf->link_speed) {
1050                         /* No speeds specified. Enable AutoNeg - all speeds */
1051                         req.auto_mode =
1052                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1053                 }
1054                 /* AutoNeg - Advertise speeds specified. */
1055                 if (conf->auto_link_speed_mask &&
1056                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1057                         req.auto_mode =
1058                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1059                         req.auto_link_speed_mask =
1060                                 conf->auto_link_speed_mask;
1061                         enables |=
1062                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1063                 }
1064
1065                 req.auto_duplex = conf->duplex;
1066                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1067                 req.auto_pause = conf->auto_pause;
1068                 req.force_pause = conf->force_pause;
1069                 /* Set force_pause if there is no auto or if there is a force */
1070                 if (req.auto_pause && !req.force_pause)
1071                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1072                 else
1073                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1074
1075                 req.enables = rte_cpu_to_le_32(enables);
1076         } else {
1077                 req.flags =
1078                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1079                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1080         }
1081
1082         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1083
1084         HWRM_CHECK_RESULT();
1085         HWRM_UNLOCK();
1086
1087         return rc;
1088 }
1089
1090 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1091                                    struct bnxt_link_info *link_info)
1092 {
1093         int rc = 0;
1094         struct hwrm_port_phy_qcfg_input req = {0};
1095         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1096
1097         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1098
1099         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1100
1101         HWRM_CHECK_RESULT();
1102
1103         link_info->phy_link_status = resp->link;
1104         link_info->link_up =
1105                 (link_info->phy_link_status ==
1106                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1107         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1108         link_info->duplex = resp->duplex_cfg;
1109         link_info->pause = resp->pause;
1110         link_info->auto_pause = resp->auto_pause;
1111         link_info->force_pause = resp->force_pause;
1112         link_info->auto_mode = resp->auto_mode;
1113         link_info->phy_type = resp->phy_type;
1114         link_info->media_type = resp->media_type;
1115
1116         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1117         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1118         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1119         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1120         link_info->phy_ver[0] = resp->phy_maj;
1121         link_info->phy_ver[1] = resp->phy_min;
1122         link_info->phy_ver[2] = resp->phy_bld;
1123
1124         HWRM_UNLOCK();
1125
1126         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1127         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1128         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1129         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1130         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1131                     link_info->auto_link_speed_mask);
1132         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1133                     link_info->force_link_speed);
1134
1135         return rc;
1136 }
1137
1138 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1139 {
1140         int rc = 0;
1141         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1142         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1143         int i;
1144
1145         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1146
1147         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1148         /* HWRM Version >= 1.9.1 */
1149         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1150                 req.drv_qmap_cap =
1151                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1152         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1153
1154         HWRM_CHECK_RESULT();
1155
1156 #define GET_QUEUE_INFO(x) \
1157         bp->cos_queue[x].id = resp->queue_id##x; \
1158         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1159
1160         GET_QUEUE_INFO(0);
1161         GET_QUEUE_INFO(1);
1162         GET_QUEUE_INFO(2);
1163         GET_QUEUE_INFO(3);
1164         GET_QUEUE_INFO(4);
1165         GET_QUEUE_INFO(5);
1166         GET_QUEUE_INFO(6);
1167         GET_QUEUE_INFO(7);
1168
1169         HWRM_UNLOCK();
1170
1171         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1172                 bp->tx_cosq_id = bp->cos_queue[0].id;
1173         } else {
1174                 /* iterate and find the COSq profile to use for Tx */
1175                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1176                         if (bp->cos_queue[i].profile ==
1177                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1178                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1179                                 break;
1180                         }
1181                 }
1182         }
1183
1184         bp->max_tc = resp->max_configurable_queues;
1185         bp->max_lltc = resp->max_configurable_lossless_queues;
1186         if (bp->max_tc > BNXT_MAX_QUEUE)
1187                 bp->max_tc = BNXT_MAX_QUEUE;
1188         bp->max_q = bp->max_tc;
1189
1190         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1191
1192         return rc;
1193 }
1194
1195 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1196                          struct bnxt_ring *ring,
1197                          uint32_t ring_type, uint32_t map_index,
1198                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1199 {
1200         int rc = 0;
1201         uint32_t enables = 0;
1202         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1203         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1204         struct rte_mempool *mb_pool;
1205         uint16_t rx_buf_size;
1206
1207         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1208
1209         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1210         req.fbo = rte_cpu_to_le_32(0);
1211         /* Association of ring index with doorbell index */
1212         req.logical_id = rte_cpu_to_le_16(map_index);
1213         req.length = rte_cpu_to_le_32(ring->ring_size);
1214
1215         switch (ring_type) {
1216         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1217                 req.ring_type = ring_type;
1218                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1219                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1220                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1221                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1222                         enables |=
1223                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1224                 break;
1225         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1226                 req.ring_type = ring_type;
1227                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1228                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1229                 if (BNXT_CHIP_THOR(bp)) {
1230                         mb_pool = bp->rx_queues[0]->mb_pool;
1231                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1232                                       RTE_PKTMBUF_HEADROOM;
1233                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1234                         enables |=
1235                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1236                 }
1237                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1238                         enables |=
1239                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1240                 break;
1241         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1242                 req.ring_type = ring_type;
1243                 if (BNXT_HAS_NQ(bp)) {
1244                         /* Association of cp ring with nq */
1245                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1246                         enables |=
1247                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1248                 }
1249                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1250                 break;
1251         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1252                 req.ring_type = ring_type;
1253                 req.page_size = BNXT_PAGE_SHFT;
1254                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1255                 break;
1256         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1257                 req.ring_type = ring_type;
1258                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1259
1260                 mb_pool = bp->rx_queues[0]->mb_pool;
1261                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1262                               RTE_PKTMBUF_HEADROOM;
1263                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1264
1265                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1266                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1267                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1268                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1269                 break;
1270         default:
1271                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1272                         ring_type);
1273                 HWRM_UNLOCK();
1274                 return -EINVAL;
1275         }
1276         req.enables = rte_cpu_to_le_32(enables);
1277
1278         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1279
1280         if (rc || resp->error_code) {
1281                 if (rc == 0 && resp->error_code)
1282                         rc = rte_le_to_cpu_16(resp->error_code);
1283                 switch (ring_type) {
1284                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1285                         PMD_DRV_LOG(ERR,
1286                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1287                         HWRM_UNLOCK();
1288                         return rc;
1289                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1290                         PMD_DRV_LOG(ERR,
1291                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1292                         HWRM_UNLOCK();
1293                         return rc;
1294                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1295                         PMD_DRV_LOG(ERR,
1296                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1297                                     rc);
1298                         HWRM_UNLOCK();
1299                         return rc;
1300                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1301                         PMD_DRV_LOG(ERR,
1302                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1303                         HWRM_UNLOCK();
1304                         return rc;
1305                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1306                         PMD_DRV_LOG(ERR,
1307                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1308                         HWRM_UNLOCK();
1309                         return rc;
1310                 default:
1311                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1312                         HWRM_UNLOCK();
1313                         return rc;
1314                 }
1315         }
1316
1317         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1318         HWRM_UNLOCK();
1319         return rc;
1320 }
1321
1322 int bnxt_hwrm_ring_free(struct bnxt *bp,
1323                         struct bnxt_ring *ring, uint32_t ring_type)
1324 {
1325         int rc;
1326         struct hwrm_ring_free_input req = {.req_type = 0 };
1327         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1328
1329         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1330
1331         req.ring_type = ring_type;
1332         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1333
1334         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1335
1336         if (rc || resp->error_code) {
1337                 if (rc == 0 && resp->error_code)
1338                         rc = rte_le_to_cpu_16(resp->error_code);
1339                 HWRM_UNLOCK();
1340
1341                 switch (ring_type) {
1342                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1343                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1344                                 rc);
1345                         return rc;
1346                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1347                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1348                                 rc);
1349                         return rc;
1350                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1351                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1352                                 rc);
1353                         return rc;
1354                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1355                         PMD_DRV_LOG(ERR,
1356                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1357                         return rc;
1358                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1359                         PMD_DRV_LOG(ERR,
1360                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1361                         return rc;
1362                 default:
1363                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1364                         return rc;
1365                 }
1366         }
1367         HWRM_UNLOCK();
1368         return 0;
1369 }
1370
1371 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1372 {
1373         int rc = 0;
1374         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1375         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1376
1377         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1378
1379         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1380         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1381         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1382         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1383
1384         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1385
1386         HWRM_CHECK_RESULT();
1387
1388         bp->grp_info[idx].fw_grp_id =
1389             rte_le_to_cpu_16(resp->ring_group_id);
1390
1391         HWRM_UNLOCK();
1392
1393         return rc;
1394 }
1395
1396 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1397 {
1398         int rc;
1399         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1400         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1401
1402         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1403
1404         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1405
1406         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1407
1408         HWRM_CHECK_RESULT();
1409         HWRM_UNLOCK();
1410
1411         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1412         return rc;
1413 }
1414
1415 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1416 {
1417         int rc = 0;
1418         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1419         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1420
1421         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1422                 return rc;
1423
1424         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1425
1426         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1427
1428         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1429
1430         HWRM_CHECK_RESULT();
1431         HWRM_UNLOCK();
1432
1433         return rc;
1434 }
1435
1436 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1437                                 unsigned int idx __rte_unused)
1438 {
1439         int rc;
1440         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1441         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1442
1443         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1444
1445         req.update_period_ms = rte_cpu_to_le_32(0);
1446
1447         req.stats_dma_addr =
1448             rte_cpu_to_le_64(cpr->hw_stats_map);
1449
1450         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1451
1452         HWRM_CHECK_RESULT();
1453
1454         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1455
1456         HWRM_UNLOCK();
1457
1458         return rc;
1459 }
1460
1461 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1462                                 unsigned int idx __rte_unused)
1463 {
1464         int rc;
1465         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1466         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1467
1468         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1469
1470         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1471
1472         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1473
1474         HWRM_CHECK_RESULT();
1475         HWRM_UNLOCK();
1476
1477         return rc;
1478 }
1479
1480 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1481 {
1482         int rc = 0, i, j;
1483         struct hwrm_vnic_alloc_input req = { 0 };
1484         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1485
1486         if (!BNXT_HAS_RING_GRPS(bp))
1487                 goto skip_ring_grps;
1488
1489         /* map ring groups to this vnic */
1490         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1491                 vnic->start_grp_id, vnic->end_grp_id);
1492         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1493                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1494
1495         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1496         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1497         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1498         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1499
1500 skip_ring_grps:
1501         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1502                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1503         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1504
1505         if (vnic->func_default)
1506                 req.flags =
1507                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1508         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1509
1510         HWRM_CHECK_RESULT();
1511
1512         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1513         HWRM_UNLOCK();
1514         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1515         return rc;
1516 }
1517
1518 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1519                                         struct bnxt_vnic_info *vnic,
1520                                         struct bnxt_plcmodes_cfg *pmode)
1521 {
1522         int rc = 0;
1523         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1524         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1525
1526         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1527
1528         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1529
1530         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1531
1532         HWRM_CHECK_RESULT();
1533
1534         pmode->flags = rte_le_to_cpu_32(resp->flags);
1535         /* dflt_vnic bit doesn't exist in the _cfg command */
1536         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1537         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1538         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1539         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1540
1541         HWRM_UNLOCK();
1542
1543         return rc;
1544 }
1545
1546 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1547                                        struct bnxt_vnic_info *vnic,
1548                                        struct bnxt_plcmodes_cfg *pmode)
1549 {
1550         int rc = 0;
1551         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1552         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1553
1554         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1555                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1556                 return rc;
1557         }
1558
1559         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1560
1561         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1562         req.flags = rte_cpu_to_le_32(pmode->flags);
1563         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1564         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1565         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1566         req.enables = rte_cpu_to_le_32(
1567             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1568             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1569             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1570         );
1571
1572         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1573
1574         HWRM_CHECK_RESULT();
1575         HWRM_UNLOCK();
1576
1577         return rc;
1578 }
1579
1580 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1581 {
1582         int rc = 0;
1583         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1584         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1585         struct bnxt_plcmodes_cfg pmodes = { 0 };
1586         uint32_t ctx_enable_flag = 0;
1587         uint32_t enables = 0;
1588
1589         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1590                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1591                 return rc;
1592         }
1593
1594         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1595         if (rc)
1596                 return rc;
1597
1598         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1599
1600         if (BNXT_CHIP_THOR(bp)) {
1601                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1602                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1603                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1604
1605                 req.default_rx_ring_id =
1606                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1607                 req.default_cmpl_ring_id =
1608                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1609                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1610                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1611                 goto config_mru;
1612         }
1613
1614         /* Only RSS support for now TBD: COS & LB */
1615         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1616         if (vnic->lb_rule != 0xffff)
1617                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1618         if (vnic->cos_rule != 0xffff)
1619                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1620         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1621                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1622                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1623         }
1624         enables |= ctx_enable_flag;
1625         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1626         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1627         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1628         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1629
1630 config_mru:
1631         req.enables = rte_cpu_to_le_32(enables);
1632         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1633         req.mru = rte_cpu_to_le_16(vnic->mru);
1634         /* Configure default VNIC only once. */
1635         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1636                 req.flags |=
1637                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1638                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1639         }
1640         if (vnic->vlan_strip)
1641                 req.flags |=
1642                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1643         if (vnic->bd_stall)
1644                 req.flags |=
1645                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1646         if (vnic->roce_dual)
1647                 req.flags |= rte_cpu_to_le_32(
1648                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1649         if (vnic->roce_only)
1650                 req.flags |= rte_cpu_to_le_32(
1651                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1652         if (vnic->rss_dflt_cr)
1653                 req.flags |= rte_cpu_to_le_32(
1654                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1655
1656         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1657
1658         HWRM_CHECK_RESULT();
1659         HWRM_UNLOCK();
1660
1661         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1662
1663         return rc;
1664 }
1665
1666 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1667                 int16_t fw_vf_id)
1668 {
1669         int rc = 0;
1670         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1671         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1672
1673         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1674                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1675                 return rc;
1676         }
1677         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1678
1679         req.enables =
1680                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1681         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1682         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1683
1684         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1685
1686         HWRM_CHECK_RESULT();
1687
1688         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1689         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1690         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1691         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1692         vnic->mru = rte_le_to_cpu_16(resp->mru);
1693         vnic->func_default = rte_le_to_cpu_32(
1694                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1695         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1696                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1697         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1698                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1699         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1700                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1701         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1702                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1703         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1704                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1705
1706         HWRM_UNLOCK();
1707
1708         return rc;
1709 }
1710
1711 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1712                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1713 {
1714         int rc = 0;
1715         uint16_t ctx_id;
1716         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1717         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1718                                                 bp->hwrm_cmd_resp_addr;
1719
1720         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1721
1722         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1723         HWRM_CHECK_RESULT();
1724
1725         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1726         if (!BNXT_HAS_RING_GRPS(bp))
1727                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1728         else if (ctx_idx == 0)
1729                 vnic->rss_rule = ctx_id;
1730
1731         HWRM_UNLOCK();
1732
1733         return rc;
1734 }
1735
1736 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1737                             struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1738 {
1739         int rc = 0;
1740         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1741         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1742                                                 bp->hwrm_cmd_resp_addr;
1743
1744         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1745                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1746                 return rc;
1747         }
1748         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1749
1750         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1751
1752         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1753
1754         HWRM_CHECK_RESULT();
1755         HWRM_UNLOCK();
1756
1757         return rc;
1758 }
1759
1760 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1761 {
1762         int rc = 0;
1763         struct hwrm_vnic_free_input req = {.req_type = 0 };
1764         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1765
1766         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1767                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1768                 return rc;
1769         }
1770
1771         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1772
1773         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1774
1775         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1776
1777         HWRM_CHECK_RESULT();
1778         HWRM_UNLOCK();
1779
1780         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1781         /* Configure default VNIC again if necessary. */
1782         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1783                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1784
1785         return rc;
1786 }
1787
1788 static int
1789 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1790 {
1791         int i;
1792         int rc = 0;
1793         int nr_ctxs = vnic->num_lb_ctxts;
1794         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1795         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1796
1797         for (i = 0; i < nr_ctxs; i++) {
1798                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1799
1800                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1801                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1802                 req.hash_mode_flags = vnic->hash_mode;
1803
1804                 req.hash_key_tbl_addr =
1805                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1806
1807                 req.ring_grp_tbl_addr =
1808                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1809                                          i * HW_HASH_INDEX_SIZE);
1810                 req.ring_table_pair_index = i;
1811                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1812
1813                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1814                                             BNXT_USE_CHIMP_MB);
1815
1816                 HWRM_CHECK_RESULT();
1817                 HWRM_UNLOCK();
1818         }
1819
1820         return rc;
1821 }
1822
1823 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1824                            struct bnxt_vnic_info *vnic)
1825 {
1826         int rc = 0;
1827         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1828         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1829
1830         if (!vnic->rss_table)
1831                 return 0;
1832
1833         if (BNXT_CHIP_THOR(bp))
1834                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1835
1836         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1837
1838         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1839         req.hash_mode_flags = vnic->hash_mode;
1840
1841         req.ring_grp_tbl_addr =
1842             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1843         req.hash_key_tbl_addr =
1844             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1845         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1846         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1847
1848         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1849
1850         HWRM_CHECK_RESULT();
1851         HWRM_UNLOCK();
1852
1853         return rc;
1854 }
1855
1856 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1857                         struct bnxt_vnic_info *vnic)
1858 {
1859         int rc = 0;
1860         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1861         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1862         uint16_t size;
1863
1864         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1865                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1866                 return rc;
1867         }
1868
1869         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1870
1871         req.flags = rte_cpu_to_le_32(
1872                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1873
1874         req.enables = rte_cpu_to_le_32(
1875                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1876
1877         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1878         size -= RTE_PKTMBUF_HEADROOM;
1879
1880         req.jumbo_thresh = rte_cpu_to_le_16(size);
1881         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1882
1883         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1884
1885         HWRM_CHECK_RESULT();
1886         HWRM_UNLOCK();
1887
1888         return rc;
1889 }
1890
1891 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1892                         struct bnxt_vnic_info *vnic, bool enable)
1893 {
1894         int rc = 0;
1895         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1896         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1897
1898         if (BNXT_CHIP_THOR(bp))
1899                 return 0;
1900
1901         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1902
1903         if (enable) {
1904                 req.enables = rte_cpu_to_le_32(
1905                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1906                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1907                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1908                 req.flags = rte_cpu_to_le_32(
1909                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1910                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1911                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1912                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1913                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1914                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1915                 req.max_agg_segs = rte_cpu_to_le_16(5);
1916                 req.max_aggs =
1917                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1918                 req.min_agg_len = rte_cpu_to_le_32(512);
1919         }
1920         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1921
1922         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1923
1924         HWRM_CHECK_RESULT();
1925         HWRM_UNLOCK();
1926
1927         return rc;
1928 }
1929
1930 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1931 {
1932         struct hwrm_func_cfg_input req = {0};
1933         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1934         int rc;
1935
1936         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1937         req.enables = rte_cpu_to_le_32(
1938                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1939         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1940         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1941
1942         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1943
1944         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1945         HWRM_CHECK_RESULT();
1946         HWRM_UNLOCK();
1947
1948         bp->pf.vf_info[vf].random_mac = false;
1949
1950         return rc;
1951 }
1952
1953 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1954                                   uint64_t *dropped)
1955 {
1956         int rc = 0;
1957         struct hwrm_func_qstats_input req = {.req_type = 0};
1958         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1959
1960         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1961
1962         req.fid = rte_cpu_to_le_16(fid);
1963
1964         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1965
1966         HWRM_CHECK_RESULT();
1967
1968         if (dropped)
1969                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1970
1971         HWRM_UNLOCK();
1972
1973         return rc;
1974 }
1975
1976 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1977                           struct rte_eth_stats *stats)
1978 {
1979         int rc = 0;
1980         struct hwrm_func_qstats_input req = {.req_type = 0};
1981         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1982
1983         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1984
1985         req.fid = rte_cpu_to_le_16(fid);
1986
1987         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1988
1989         HWRM_CHECK_RESULT();
1990
1991         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1992         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1993         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1994         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1995         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1996         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1997
1998         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1999         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2000         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2001         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2002         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2003         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2004
2005         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2006         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2007         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2008
2009         HWRM_UNLOCK();
2010
2011         return rc;
2012 }
2013
2014 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2015 {
2016         int rc = 0;
2017         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2018         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2019
2020         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2021
2022         req.fid = rte_cpu_to_le_16(fid);
2023
2024         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2025
2026         HWRM_CHECK_RESULT();
2027         HWRM_UNLOCK();
2028
2029         return rc;
2030 }
2031
2032 /*
2033  * HWRM utility functions
2034  */
2035
2036 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2037 {
2038         unsigned int i;
2039         int rc = 0;
2040
2041         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2042                 struct bnxt_tx_queue *txq;
2043                 struct bnxt_rx_queue *rxq;
2044                 struct bnxt_cp_ring_info *cpr;
2045
2046                 if (i >= bp->rx_cp_nr_rings) {
2047                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2048                         cpr = txq->cp_ring;
2049                 } else {
2050                         rxq = bp->rx_queues[i];
2051                         cpr = rxq->cp_ring;
2052                 }
2053
2054                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2055                 if (rc)
2056                         return rc;
2057         }
2058         return 0;
2059 }
2060
2061 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2062 {
2063         int rc;
2064         unsigned int i;
2065         struct bnxt_cp_ring_info *cpr;
2066
2067         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2068
2069                 if (i >= bp->rx_cp_nr_rings) {
2070                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2071                 } else {
2072                         cpr = bp->rx_queues[i]->cp_ring;
2073                         if (BNXT_HAS_RING_GRPS(bp))
2074                                 bp->grp_info[i].fw_stats_ctx = -1;
2075                 }
2076                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2077                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2078                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2079                         if (rc)
2080                                 return rc;
2081                 }
2082         }
2083         return 0;
2084 }
2085
2086 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2087 {
2088         unsigned int i;
2089         int rc = 0;
2090
2091         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2092                 struct bnxt_tx_queue *txq;
2093                 struct bnxt_rx_queue *rxq;
2094                 struct bnxt_cp_ring_info *cpr;
2095
2096                 if (i >= bp->rx_cp_nr_rings) {
2097                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2098                         cpr = txq->cp_ring;
2099                 } else {
2100                         rxq = bp->rx_queues[i];
2101                         cpr = rxq->cp_ring;
2102                 }
2103
2104                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2105
2106                 if (rc)
2107                         return rc;
2108         }
2109         return rc;
2110 }
2111
2112 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2113 {
2114         uint16_t idx;
2115         uint32_t rc = 0;
2116
2117         if (!BNXT_HAS_RING_GRPS(bp))
2118                 return 0;
2119
2120         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2121
2122                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2123                         continue;
2124
2125                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2126
2127                 if (rc)
2128                         return rc;
2129         }
2130         return rc;
2131 }
2132
2133 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2134 {
2135         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2136
2137         bnxt_hwrm_ring_free(bp, cp_ring,
2138                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2139         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2140         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2141                                      sizeof(*cpr->cp_desc_ring));
2142         cpr->cp_raw_cons = 0;
2143         cpr->valid = 0;
2144 }
2145
2146 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2147 {
2148         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2149
2150         bnxt_hwrm_ring_free(bp, cp_ring,
2151                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2152         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2153         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2154                         sizeof(*cpr->cp_desc_ring));
2155         cpr->cp_raw_cons = 0;
2156         cpr->valid = 0;
2157 }
2158
2159 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2160 {
2161         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2162         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2163         struct bnxt_ring *ring = rxr->rx_ring_struct;
2164         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2165
2166         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2167                 bnxt_hwrm_ring_free(bp, ring,
2168                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2169                 ring->fw_ring_id = INVALID_HW_RING_ID;
2170                 if (BNXT_HAS_RING_GRPS(bp))
2171                         bp->grp_info[queue_index].rx_fw_ring_id =
2172                                                         INVALID_HW_RING_ID;
2173                 memset(rxr->rx_desc_ring, 0,
2174                        rxr->rx_ring_struct->ring_size *
2175                        sizeof(*rxr->rx_desc_ring));
2176                 memset(rxr->rx_buf_ring, 0,
2177                        rxr->rx_ring_struct->ring_size *
2178                        sizeof(*rxr->rx_buf_ring));
2179                 rxr->rx_prod = 0;
2180         }
2181         ring = rxr->ag_ring_struct;
2182         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2183                 bnxt_hwrm_ring_free(bp, ring,
2184                                     BNXT_CHIP_THOR(bp) ?
2185                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2186                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2187                 ring->fw_ring_id = INVALID_HW_RING_ID;
2188                 memset(rxr->ag_buf_ring, 0,
2189                        rxr->ag_ring_struct->ring_size *
2190                        sizeof(*rxr->ag_buf_ring));
2191                 rxr->ag_prod = 0;
2192                 if (BNXT_HAS_RING_GRPS(bp))
2193                         bp->grp_info[queue_index].ag_fw_ring_id =
2194                                                         INVALID_HW_RING_ID;
2195         }
2196         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2197                 bnxt_free_cp_ring(bp, cpr);
2198                 if (rxq->nq_ring)
2199                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2200         }
2201
2202         if (BNXT_HAS_RING_GRPS(bp))
2203                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2204 }
2205
2206 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2207 {
2208         unsigned int i;
2209
2210         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2211                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2212                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2213                 struct bnxt_ring *ring = txr->tx_ring_struct;
2214                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2215
2216                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2217                         bnxt_hwrm_ring_free(bp, ring,
2218                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2219                         ring->fw_ring_id = INVALID_HW_RING_ID;
2220                         memset(txr->tx_desc_ring, 0,
2221                                         txr->tx_ring_struct->ring_size *
2222                                         sizeof(*txr->tx_desc_ring));
2223                         memset(txr->tx_buf_ring, 0,
2224                                         txr->tx_ring_struct->ring_size *
2225                                         sizeof(*txr->tx_buf_ring));
2226                         txr->tx_prod = 0;
2227                         txr->tx_cons = 0;
2228                 }
2229                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2230                         bnxt_free_cp_ring(bp, cpr);
2231                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2232                         if (txq->nq_ring)
2233                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2234                 }
2235         }
2236
2237         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2238                 bnxt_free_hwrm_rx_ring(bp, i);
2239
2240         return 0;
2241 }
2242
2243 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2244 {
2245         uint16_t i;
2246         uint32_t rc = 0;
2247
2248         if (!BNXT_HAS_RING_GRPS(bp))
2249                 return 0;
2250
2251         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2252                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2253                 if (rc)
2254                         return rc;
2255         }
2256         return rc;
2257 }
2258
2259 void bnxt_free_hwrm_resources(struct bnxt *bp)
2260 {
2261         /* Release memzone */
2262         rte_free(bp->hwrm_cmd_resp_addr);
2263         rte_free(bp->hwrm_short_cmd_req_addr);
2264         bp->hwrm_cmd_resp_addr = NULL;
2265         bp->hwrm_short_cmd_req_addr = NULL;
2266         bp->hwrm_cmd_resp_dma_addr = 0;
2267         bp->hwrm_short_cmd_req_dma_addr = 0;
2268 }
2269
2270 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2271 {
2272         struct rte_pci_device *pdev = bp->pdev;
2273         char type[RTE_MEMZONE_NAMESIZE];
2274
2275         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2276                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2277         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2278         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2279         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2280         if (bp->hwrm_cmd_resp_addr == NULL)
2281                 return -ENOMEM;
2282         bp->hwrm_cmd_resp_dma_addr =
2283                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2284         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2285                 PMD_DRV_LOG(ERR,
2286                         "unable to map response address to physical memory\n");
2287                 return -ENOMEM;
2288         }
2289         rte_spinlock_init(&bp->hwrm_lock);
2290
2291         return 0;
2292 }
2293
2294 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2295 {
2296         struct bnxt_filter_info *filter;
2297         int rc = 0;
2298
2299         STAILQ_FOREACH(filter, &vnic->filter, next) {
2300                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2301                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2302                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2303                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2304                 else
2305                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2306                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2307                 //if (rc)
2308                         //break;
2309         }
2310         return rc;
2311 }
2312
2313 static int
2314 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2315 {
2316         struct bnxt_filter_info *filter;
2317         struct rte_flow *flow;
2318         int rc = 0;
2319
2320         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2321                 filter = flow->filter;
2322                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2323                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2324                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2325                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2326                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2327                 else
2328                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2329
2330                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2331                 rte_free(flow);
2332                 //if (rc)
2333                         //break;
2334         }
2335         return rc;
2336 }
2337
2338 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2339 {
2340         struct bnxt_filter_info *filter;
2341         int rc = 0;
2342
2343         STAILQ_FOREACH(filter, &vnic->filter, next) {
2344                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2345                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2346                                                      filter);
2347                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2348                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2349                                                          filter);
2350                 else
2351                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2352                                                      filter);
2353                 if (rc)
2354                         break;
2355         }
2356         return rc;
2357 }
2358
2359 void bnxt_free_tunnel_ports(struct bnxt *bp)
2360 {
2361         if (bp->vxlan_port_cnt)
2362                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2363                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2364         bp->vxlan_port = 0;
2365         if (bp->geneve_port_cnt)
2366                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2367                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2368         bp->geneve_port = 0;
2369 }
2370
2371 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2372 {
2373         int i, j;
2374
2375         if (bp->vnic_info == NULL)
2376                 return;
2377
2378         /*
2379          * Cleanup VNICs in reverse order, to make sure the L2 filter
2380          * from vnic0 is last to be cleaned up.
2381          */
2382         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2383                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2384
2385                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2386                         PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2387                         return;
2388                 }
2389
2390                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2391
2392                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2393
2394                 if (BNXT_CHIP_THOR(bp)) {
2395                         for (j = 0; j < vnic->num_lb_ctxts; j++) {
2396                                 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2397                                                         vnic->fw_grp_ids[j]);
2398                                 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2399                         }
2400                         vnic->num_lb_ctxts = 0;
2401                 } else {
2402                         bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2403                         vnic->rss_rule = INVALID_HW_RING_ID;
2404                 }
2405
2406                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2407
2408                 bnxt_hwrm_vnic_free(bp, vnic);
2409
2410                 rte_free(vnic->fw_grp_ids);
2411         }
2412         /* Ring resources */
2413         bnxt_free_all_hwrm_rings(bp);
2414         bnxt_free_all_hwrm_ring_grps(bp);
2415         bnxt_free_all_hwrm_stat_ctxs(bp);
2416         bnxt_free_tunnel_ports(bp);
2417 }
2418
2419 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2420 {
2421         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2422
2423         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2424                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2425
2426         switch (conf_link_speed) {
2427         case ETH_LINK_SPEED_10M_HD:
2428         case ETH_LINK_SPEED_100M_HD:
2429                 /* FALLTHROUGH */
2430                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2431         }
2432         return hw_link_duplex;
2433 }
2434
2435 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2436 {
2437         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2438 }
2439
2440 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2441 {
2442         uint16_t eth_link_speed = 0;
2443
2444         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2445                 return ETH_LINK_SPEED_AUTONEG;
2446
2447         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2448         case ETH_LINK_SPEED_100M:
2449         case ETH_LINK_SPEED_100M_HD:
2450                 /* FALLTHROUGH */
2451                 eth_link_speed =
2452                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2453                 break;
2454         case ETH_LINK_SPEED_1G:
2455                 eth_link_speed =
2456                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2457                 break;
2458         case ETH_LINK_SPEED_2_5G:
2459                 eth_link_speed =
2460                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2461                 break;
2462         case ETH_LINK_SPEED_10G:
2463                 eth_link_speed =
2464                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2465                 break;
2466         case ETH_LINK_SPEED_20G:
2467                 eth_link_speed =
2468                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2469                 break;
2470         case ETH_LINK_SPEED_25G:
2471                 eth_link_speed =
2472                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2473                 break;
2474         case ETH_LINK_SPEED_40G:
2475                 eth_link_speed =
2476                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2477                 break;
2478         case ETH_LINK_SPEED_50G:
2479                 eth_link_speed =
2480                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2481                 break;
2482         case ETH_LINK_SPEED_100G:
2483                 eth_link_speed =
2484                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2485                 break;
2486         default:
2487                 PMD_DRV_LOG(ERR,
2488                         "Unsupported link speed %d; default to AUTO\n",
2489                         conf_link_speed);
2490                 break;
2491         }
2492         return eth_link_speed;
2493 }
2494
2495 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2496                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2497                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2498                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2499
2500 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2501 {
2502         uint32_t one_speed;
2503
2504         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2505                 return 0;
2506
2507         if (link_speed & ETH_LINK_SPEED_FIXED) {
2508                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2509
2510                 if (one_speed & (one_speed - 1)) {
2511                         PMD_DRV_LOG(ERR,
2512                                 "Invalid advertised speeds (%u) for port %u\n",
2513                                 link_speed, port_id);
2514                         return -EINVAL;
2515                 }
2516                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2517                         PMD_DRV_LOG(ERR,
2518                                 "Unsupported advertised speed (%u) for port %u\n",
2519                                 link_speed, port_id);
2520                         return -EINVAL;
2521                 }
2522         } else {
2523                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2524                         PMD_DRV_LOG(ERR,
2525                                 "Unsupported advertised speeds (%u) for port %u\n",
2526                                 link_speed, port_id);
2527                         return -EINVAL;
2528                 }
2529         }
2530         return 0;
2531 }
2532
2533 static uint16_t
2534 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2535 {
2536         uint16_t ret = 0;
2537
2538         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2539                 if (bp->link_info.support_speeds)
2540                         return bp->link_info.support_speeds;
2541                 link_speed = BNXT_SUPPORTED_SPEEDS;
2542         }
2543
2544         if (link_speed & ETH_LINK_SPEED_100M)
2545                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2546         if (link_speed & ETH_LINK_SPEED_100M_HD)
2547                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2548         if (link_speed & ETH_LINK_SPEED_1G)
2549                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2550         if (link_speed & ETH_LINK_SPEED_2_5G)
2551                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2552         if (link_speed & ETH_LINK_SPEED_10G)
2553                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2554         if (link_speed & ETH_LINK_SPEED_20G)
2555                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2556         if (link_speed & ETH_LINK_SPEED_25G)
2557                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2558         if (link_speed & ETH_LINK_SPEED_40G)
2559                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2560         if (link_speed & ETH_LINK_SPEED_50G)
2561                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2562         if (link_speed & ETH_LINK_SPEED_100G)
2563                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2564         return ret;
2565 }
2566
2567 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2568 {
2569         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2570
2571         switch (hw_link_speed) {
2572         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2573                 eth_link_speed = ETH_SPEED_NUM_100M;
2574                 break;
2575         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2576                 eth_link_speed = ETH_SPEED_NUM_1G;
2577                 break;
2578         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2579                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2580                 break;
2581         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2582                 eth_link_speed = ETH_SPEED_NUM_10G;
2583                 break;
2584         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2585                 eth_link_speed = ETH_SPEED_NUM_20G;
2586                 break;
2587         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2588                 eth_link_speed = ETH_SPEED_NUM_25G;
2589                 break;
2590         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2591                 eth_link_speed = ETH_SPEED_NUM_40G;
2592                 break;
2593         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2594                 eth_link_speed = ETH_SPEED_NUM_50G;
2595                 break;
2596         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2597                 eth_link_speed = ETH_SPEED_NUM_100G;
2598                 break;
2599         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2600         default:
2601                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2602                         hw_link_speed);
2603                 break;
2604         }
2605         return eth_link_speed;
2606 }
2607
2608 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2609 {
2610         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2611
2612         switch (hw_link_duplex) {
2613         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2614         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2615                 /* FALLTHROUGH */
2616                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2617                 break;
2618         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2619                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2620                 break;
2621         default:
2622                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2623                         hw_link_duplex);
2624                 break;
2625         }
2626         return eth_link_duplex;
2627 }
2628
2629 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2630 {
2631         int rc = 0;
2632         struct bnxt_link_info *link_info = &bp->link_info;
2633
2634         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2635         if (rc) {
2636                 PMD_DRV_LOG(ERR,
2637                         "Get link config failed with rc %d\n", rc);
2638                 goto exit;
2639         }
2640         if (link_info->link_speed)
2641                 link->link_speed =
2642                         bnxt_parse_hw_link_speed(link_info->link_speed);
2643         else
2644                 link->link_speed = ETH_SPEED_NUM_NONE;
2645         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2646         link->link_status = link_info->link_up;
2647         link->link_autoneg = link_info->auto_mode ==
2648                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2649                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2650 exit:
2651         return rc;
2652 }
2653
2654 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2655 {
2656         int rc = 0;
2657         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2658         struct bnxt_link_info link_req;
2659         uint16_t speed, autoneg;
2660
2661         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2662                 return 0;
2663
2664         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2665                         bp->eth_dev->data->port_id);
2666         if (rc)
2667                 goto error;
2668
2669         memset(&link_req, 0, sizeof(link_req));
2670         link_req.link_up = link_up;
2671         if (!link_up)
2672                 goto port_phy_cfg;
2673
2674         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2675         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2676         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2677         /* Autoneg can be done only when the FW allows */
2678         if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2679                                 bp->link_info.force_link_speed)) {
2680                 link_req.phy_flags |=
2681                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2682                 link_req.auto_link_speed_mask =
2683                         bnxt_parse_eth_link_speed_mask(bp,
2684                                                        dev_conf->link_speeds);
2685         } else {
2686                 if (bp->link_info.phy_type ==
2687                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2688                     bp->link_info.phy_type ==
2689                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2690                     bp->link_info.media_type ==
2691                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2692                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2693                         return -EINVAL;
2694                 }
2695
2696                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2697                 /* If user wants a particular speed try that first. */
2698                 if (speed)
2699                         link_req.link_speed = speed;
2700                 else if (bp->link_info.force_link_speed)
2701                         link_req.link_speed = bp->link_info.force_link_speed;
2702                 else
2703                         link_req.link_speed = bp->link_info.auto_link_speed;
2704         }
2705         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2706         link_req.auto_pause = bp->link_info.auto_pause;
2707         link_req.force_pause = bp->link_info.force_pause;
2708
2709 port_phy_cfg:
2710         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2711         if (rc) {
2712                 PMD_DRV_LOG(ERR,
2713                         "Set link config failed with rc %d\n", rc);
2714         }
2715
2716 error:
2717         return rc;
2718 }
2719
2720 /* JIRA 22088 */
2721 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2722 {
2723         struct hwrm_func_qcfg_input req = {0};
2724         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2725         uint16_t flags;
2726         int rc = 0;
2727
2728         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2729         req.fid = rte_cpu_to_le_16(0xffff);
2730
2731         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2732
2733         HWRM_CHECK_RESULT();
2734
2735         /* Hard Coded.. 0xfff VLAN ID mask */
2736         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2737         flags = rte_le_to_cpu_16(resp->flags);
2738         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2739                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2740
2741         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2742                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2743                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2744         } else if (BNXT_VF(bp) &&
2745                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2746                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2747                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2748         }
2749
2750         if (mtu)
2751                 *mtu = resp->mtu;
2752
2753         switch (resp->port_partition_type) {
2754         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2755         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2756         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2757                 /* FALLTHROUGH */
2758                 bp->port_partition_type = resp->port_partition_type;
2759                 break;
2760         default:
2761                 bp->port_partition_type = 0;
2762                 break;
2763         }
2764
2765         HWRM_UNLOCK();
2766
2767         return rc;
2768 }
2769
2770 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2771                                    struct hwrm_func_qcaps_output *qcaps)
2772 {
2773         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2774         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2775                sizeof(qcaps->mac_address));
2776         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2777         qcaps->max_rx_rings = fcfg->num_rx_rings;
2778         qcaps->max_tx_rings = fcfg->num_tx_rings;
2779         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2780         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2781         qcaps->max_vfs = 0;
2782         qcaps->first_vf_id = 0;
2783         qcaps->max_vnics = fcfg->num_vnics;
2784         qcaps->max_decap_records = 0;
2785         qcaps->max_encap_records = 0;
2786         qcaps->max_tx_wm_flows = 0;
2787         qcaps->max_tx_em_flows = 0;
2788         qcaps->max_rx_wm_flows = 0;
2789         qcaps->max_rx_em_flows = 0;
2790         qcaps->max_flow_id = 0;
2791         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2792         qcaps->max_sp_tx_rings = 0;
2793         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2794 }
2795
2796 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2797 {
2798         struct hwrm_func_cfg_input req = {0};
2799         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2800         uint32_t enables;
2801         int rc;
2802
2803         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2804                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2805                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2806                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2807                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2808                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2809                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2810                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2811                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2812
2813         if (BNXT_HAS_RING_GRPS(bp)) {
2814                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2815                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2816         } else if (BNXT_HAS_NQ(bp)) {
2817                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2818                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2819         }
2820
2821         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2822         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2823         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2824                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2825                                    BNXT_NUM_VLANS);
2826         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2827         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2828         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2829         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2830         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2831         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2832         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2833         req.fid = rte_cpu_to_le_16(0xffff);
2834         req.enables = rte_cpu_to_le_32(enables);
2835
2836         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2837
2838         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2839
2840         HWRM_CHECK_RESULT();
2841         HWRM_UNLOCK();
2842
2843         return rc;
2844 }
2845
2846 static void populate_vf_func_cfg_req(struct bnxt *bp,
2847                                      struct hwrm_func_cfg_input *req,
2848                                      int num_vfs)
2849 {
2850         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2851                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2852                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2853                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2854                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2855                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2856                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2857                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2858                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2859                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2860
2861         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2862                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2863                                     BNXT_NUM_VLANS);
2864         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2865                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2866                                     BNXT_NUM_VLANS);
2867         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2868                                                 (num_vfs + 1));
2869         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2870         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2871                                                (num_vfs + 1));
2872         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2873         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2874         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2875         /* TODO: For now, do not support VMDq/RFS on VFs. */
2876         req->num_vnics = rte_cpu_to_le_16(1);
2877         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2878                                                  (num_vfs + 1));
2879 }
2880
2881 static void add_random_mac_if_needed(struct bnxt *bp,
2882                                      struct hwrm_func_cfg_input *cfg_req,
2883                                      int vf)
2884 {
2885         struct rte_ether_addr mac;
2886
2887         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2888                 return;
2889
2890         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2891                 cfg_req->enables |=
2892                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2893                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2894                 bp->pf.vf_info[vf].random_mac = true;
2895         } else {
2896                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2897                         RTE_ETHER_ADDR_LEN);
2898         }
2899 }
2900
2901 static void reserve_resources_from_vf(struct bnxt *bp,
2902                                       struct hwrm_func_cfg_input *cfg_req,
2903                                       int vf)
2904 {
2905         struct hwrm_func_qcaps_input req = {0};
2906         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2907         int rc;
2908
2909         /* Get the actual allocated values now */
2910         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2911         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2912         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2913
2914         if (rc) {
2915                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2916                 copy_func_cfg_to_qcaps(cfg_req, resp);
2917         } else if (resp->error_code) {
2918                 rc = rte_le_to_cpu_16(resp->error_code);
2919                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2920                 copy_func_cfg_to_qcaps(cfg_req, resp);
2921         }
2922
2923         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2924         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2925         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2926         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2927         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2928         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2929         /*
2930          * TODO: While not supporting VMDq with VFs, max_vnics is always
2931          * forced to 1 in this case
2932          */
2933         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2934         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2935
2936         HWRM_UNLOCK();
2937 }
2938
2939 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2940 {
2941         struct hwrm_func_qcfg_input req = {0};
2942         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2943         int rc;
2944
2945         /* Check for zero MAC address */
2946         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2947         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2948         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2949         HWRM_CHECK_RESULT();
2950         rc = rte_le_to_cpu_16(resp->vlan);
2951
2952         HWRM_UNLOCK();
2953
2954         return rc;
2955 }
2956
2957 static int update_pf_resource_max(struct bnxt *bp)
2958 {
2959         struct hwrm_func_qcfg_input req = {0};
2960         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2961         int rc;
2962
2963         /* And copy the allocated numbers into the pf struct */
2964         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2965         req.fid = rte_cpu_to_le_16(0xffff);
2966         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2967         HWRM_CHECK_RESULT();
2968
2969         /* Only TX ring value reflects actual allocation? TODO */
2970         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2971         bp->pf.evb_mode = resp->evb_mode;
2972
2973         HWRM_UNLOCK();
2974
2975         return rc;
2976 }
2977
2978 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2979 {
2980         int rc;
2981
2982         if (!BNXT_PF(bp)) {
2983                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2984                 return -EINVAL;
2985         }
2986
2987         rc = bnxt_hwrm_func_qcaps(bp);
2988         if (rc)
2989                 return rc;
2990
2991         bp->pf.func_cfg_flags &=
2992                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2993                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2994         bp->pf.func_cfg_flags |=
2995                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2996         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2997         rc = __bnxt_hwrm_func_qcaps(bp);
2998         return rc;
2999 }
3000
3001 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3002 {
3003         struct hwrm_func_cfg_input req = {0};
3004         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3005         int i;
3006         size_t sz;
3007         int rc = 0;
3008         size_t req_buf_sz;
3009
3010         if (!BNXT_PF(bp)) {
3011                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3012                 return -EINVAL;
3013         }
3014
3015         rc = bnxt_hwrm_func_qcaps(bp);
3016
3017         if (rc)
3018                 return rc;
3019
3020         bp->pf.active_vfs = num_vfs;
3021
3022         /*
3023          * First, configure the PF to only use one TX ring.  This ensures that
3024          * there are enough rings for all VFs.
3025          *
3026          * If we don't do this, when we call func_alloc() later, we will lock
3027          * extra rings to the PF that won't be available during func_cfg() of
3028          * the VFs.
3029          *
3030          * This has been fixed with firmware versions above 20.6.54
3031          */
3032         bp->pf.func_cfg_flags &=
3033                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3034                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3035         bp->pf.func_cfg_flags |=
3036                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3037         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3038         if (rc)
3039                 return rc;
3040
3041         /*
3042          * Now, create and register a buffer to hold forwarded VF requests
3043          */
3044         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3045         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3046                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3047         if (bp->pf.vf_req_buf == NULL) {
3048                 rc = -ENOMEM;
3049                 goto error_free;
3050         }
3051         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3052                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3053         for (i = 0; i < num_vfs; i++)
3054                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3055                                         (i * HWRM_MAX_REQ_LEN);
3056
3057         rc = bnxt_hwrm_func_buf_rgtr(bp);
3058         if (rc)
3059                 goto error_free;
3060
3061         populate_vf_func_cfg_req(bp, &req, num_vfs);
3062
3063         bp->pf.active_vfs = 0;
3064         for (i = 0; i < num_vfs; i++) {
3065                 add_random_mac_if_needed(bp, &req, i);
3066
3067                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3068                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3069                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3070                 rc = bnxt_hwrm_send_message(bp,
3071                                             &req,
3072                                             sizeof(req),
3073                                             BNXT_USE_CHIMP_MB);
3074
3075                 /* Clear enable flag for next pass */
3076                 req.enables &= ~rte_cpu_to_le_32(
3077                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3078
3079                 if (rc || resp->error_code) {
3080                         PMD_DRV_LOG(ERR,
3081                                 "Failed to initizlie VF %d\n", i);
3082                         PMD_DRV_LOG(ERR,
3083                                 "Not all VFs available. (%d, %d)\n",
3084                                 rc, resp->error_code);
3085                         HWRM_UNLOCK();
3086                         break;
3087                 }
3088
3089                 HWRM_UNLOCK();
3090
3091                 reserve_resources_from_vf(bp, &req, i);
3092                 bp->pf.active_vfs++;
3093                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3094         }
3095
3096         /*
3097          * Now configure the PF to use "the rest" of the resources
3098          * We're using STD_TX_RING_MODE here though which will limit the TX
3099          * rings.  This will allow QoS to function properly.  Not setting this
3100          * will cause PF rings to break bandwidth settings.
3101          */
3102         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3103         if (rc)
3104                 goto error_free;
3105
3106         rc = update_pf_resource_max(bp);
3107         if (rc)
3108                 goto error_free;
3109
3110         return rc;
3111
3112 error_free:
3113         bnxt_hwrm_func_buf_unrgtr(bp);
3114         return rc;
3115 }
3116
3117 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3118 {
3119         struct hwrm_func_cfg_input req = {0};
3120         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3121         int rc;
3122
3123         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3124
3125         req.fid = rte_cpu_to_le_16(0xffff);
3126         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3127         req.evb_mode = bp->pf.evb_mode;
3128
3129         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3130         HWRM_CHECK_RESULT();
3131         HWRM_UNLOCK();
3132
3133         return rc;
3134 }
3135
3136 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3137                                 uint8_t tunnel_type)
3138 {
3139         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3140         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3141         int rc = 0;
3142
3143         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3144         req.tunnel_type = tunnel_type;
3145         req.tunnel_dst_port_val = port;
3146         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3147         HWRM_CHECK_RESULT();
3148
3149         switch (tunnel_type) {
3150         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3151                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3152                 bp->vxlan_port = port;
3153                 break;
3154         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3155                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3156                 bp->geneve_port = port;
3157                 break;
3158         default:
3159                 break;
3160         }
3161
3162         HWRM_UNLOCK();
3163
3164         return rc;
3165 }
3166
3167 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3168                                 uint8_t tunnel_type)
3169 {
3170         struct hwrm_tunnel_dst_port_free_input req = {0};
3171         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3172         int rc = 0;
3173
3174         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3175
3176         req.tunnel_type = tunnel_type;
3177         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3178         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3179
3180         HWRM_CHECK_RESULT();
3181         HWRM_UNLOCK();
3182
3183         return rc;
3184 }
3185
3186 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3187                                         uint32_t flags)
3188 {
3189         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3190         struct hwrm_func_cfg_input req = {0};
3191         int rc;
3192
3193         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3194
3195         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3196         req.flags = rte_cpu_to_le_32(flags);
3197         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3198
3199         HWRM_CHECK_RESULT();
3200         HWRM_UNLOCK();
3201
3202         return rc;
3203 }
3204
3205 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3206 {
3207         uint32_t *flag = flagp;
3208
3209         vnic->flags = *flag;
3210 }
3211
3212 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3213 {
3214         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3215 }
3216
3217 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3218 {
3219         int rc = 0;
3220         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3221         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3222
3223         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3224
3225         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3226         req.req_buf_page_size = rte_cpu_to_le_16(
3227                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3228         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3229         req.req_buf_page_addr0 =
3230                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3231         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3232                 PMD_DRV_LOG(ERR,
3233                         "unable to map buffer address to physical memory\n");
3234                 return -ENOMEM;
3235         }
3236
3237         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3238
3239         HWRM_CHECK_RESULT();
3240         HWRM_UNLOCK();
3241
3242         return rc;
3243 }
3244
3245 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3246 {
3247         int rc = 0;
3248         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3249         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3250
3251         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3252                 return 0;
3253
3254         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3255
3256         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3257
3258         HWRM_CHECK_RESULT();
3259         HWRM_UNLOCK();
3260
3261         return rc;
3262 }
3263
3264 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3265 {
3266         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3267         struct hwrm_func_cfg_input req = {0};
3268         int rc;
3269
3270         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3271
3272         req.fid = rte_cpu_to_le_16(0xffff);
3273         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3274         req.enables = rte_cpu_to_le_32(
3275                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3276         req.async_event_cr = rte_cpu_to_le_16(
3277                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3278         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3279
3280         HWRM_CHECK_RESULT();
3281         HWRM_UNLOCK();
3282
3283         return rc;
3284 }
3285
3286 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3287 {
3288         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3289         struct hwrm_func_vf_cfg_input req = {0};
3290         int rc;
3291
3292         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3293
3294         req.enables = rte_cpu_to_le_32(
3295                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3296         req.async_event_cr = rte_cpu_to_le_16(
3297                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3298         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3299
3300         HWRM_CHECK_RESULT();
3301         HWRM_UNLOCK();
3302
3303         return rc;
3304 }
3305
3306 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3307 {
3308         struct hwrm_func_cfg_input req = {0};
3309         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3310         uint16_t dflt_vlan, fid;
3311         uint32_t func_cfg_flags;
3312         int rc = 0;
3313
3314         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3315
3316         if (is_vf) {
3317                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3318                 fid = bp->pf.vf_info[vf].fid;
3319                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3320         } else {
3321                 fid = rte_cpu_to_le_16(0xffff);
3322                 func_cfg_flags = bp->pf.func_cfg_flags;
3323                 dflt_vlan = bp->vlan;
3324         }
3325
3326         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3327         req.fid = rte_cpu_to_le_16(fid);
3328         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3329         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3330
3331         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3332
3333         HWRM_CHECK_RESULT();
3334         HWRM_UNLOCK();
3335
3336         return rc;
3337 }
3338
3339 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3340                         uint16_t max_bw, uint16_t enables)
3341 {
3342         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3343         struct hwrm_func_cfg_input req = {0};
3344         int rc;
3345
3346         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3347
3348         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3349         req.enables |= rte_cpu_to_le_32(enables);
3350         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3351         req.max_bw = rte_cpu_to_le_32(max_bw);
3352         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3353
3354         HWRM_CHECK_RESULT();
3355         HWRM_UNLOCK();
3356
3357         return rc;
3358 }
3359
3360 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3361 {
3362         struct hwrm_func_cfg_input req = {0};
3363         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3364         int rc = 0;
3365
3366         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3367
3368         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3369         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3370         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3371         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3372
3373         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3374
3375         HWRM_CHECK_RESULT();
3376         HWRM_UNLOCK();
3377
3378         return rc;
3379 }
3380
3381 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3382 {
3383         int rc;
3384
3385         if (BNXT_PF(bp))
3386                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3387         else
3388                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3389
3390         return rc;
3391 }
3392
3393 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3394                               void *encaped, size_t ec_size)
3395 {
3396         int rc = 0;
3397         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3398         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3399
3400         if (ec_size > sizeof(req.encap_request))
3401                 return -1;
3402
3403         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3404
3405         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3406         memcpy(req.encap_request, encaped, ec_size);
3407
3408         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3409
3410         HWRM_CHECK_RESULT();
3411         HWRM_UNLOCK();
3412
3413         return rc;
3414 }
3415
3416 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3417                                        struct rte_ether_addr *mac)
3418 {
3419         struct hwrm_func_qcfg_input req = {0};
3420         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3421         int rc;
3422
3423         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3424
3425         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3426         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3427
3428         HWRM_CHECK_RESULT();
3429
3430         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3431
3432         HWRM_UNLOCK();
3433
3434         return rc;
3435 }
3436
3437 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3438                             void *encaped, size_t ec_size)
3439 {
3440         int rc = 0;
3441         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3442         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3443
3444         if (ec_size > sizeof(req.encap_request))
3445                 return -1;
3446
3447         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3448
3449         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3450         memcpy(req.encap_request, encaped, ec_size);
3451
3452         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3453
3454         HWRM_CHECK_RESULT();
3455         HWRM_UNLOCK();
3456
3457         return rc;
3458 }
3459
3460 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3461                          struct rte_eth_stats *stats, uint8_t rx)
3462 {
3463         int rc = 0;
3464         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3465         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3466
3467         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3468
3469         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3470
3471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3472
3473         HWRM_CHECK_RESULT();
3474
3475         if (rx) {
3476                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3477                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3478                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3479                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3480                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3481                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3482                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3483                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3484         } else {
3485                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3486                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3487                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3488                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3489                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3490                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3491         }
3492
3493
3494         HWRM_UNLOCK();
3495
3496         return rc;
3497 }
3498
3499 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3500 {
3501         struct hwrm_port_qstats_input req = {0};
3502         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3503         struct bnxt_pf_info *pf = &bp->pf;
3504         int rc;
3505
3506         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3507
3508         req.port_id = rte_cpu_to_le_16(pf->port_id);
3509         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3510         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3511         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3512
3513         HWRM_CHECK_RESULT();
3514         HWRM_UNLOCK();
3515
3516         return rc;
3517 }
3518
3519 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3520 {
3521         struct hwrm_port_clr_stats_input req = {0};
3522         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3523         struct bnxt_pf_info *pf = &bp->pf;
3524         int rc;
3525
3526         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3527         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3528             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3529                 return 0;
3530
3531         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3532
3533         req.port_id = rte_cpu_to_le_16(pf->port_id);
3534         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3535
3536         HWRM_CHECK_RESULT();
3537         HWRM_UNLOCK();
3538
3539         return rc;
3540 }
3541
3542 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3543 {
3544         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3545         struct hwrm_port_led_qcaps_input req = {0};
3546         int rc;
3547
3548         if (BNXT_VF(bp))
3549                 return 0;
3550
3551         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3552         req.port_id = bp->pf.port_id;
3553         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3554
3555         HWRM_CHECK_RESULT();
3556
3557         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3558                 unsigned int i;
3559
3560                 bp->num_leds = resp->num_leds;
3561                 memcpy(bp->leds, &resp->led0_id,
3562                         sizeof(bp->leds[0]) * bp->num_leds);
3563                 for (i = 0; i < bp->num_leds; i++) {
3564                         struct bnxt_led_info *led = &bp->leds[i];
3565
3566                         uint16_t caps = led->led_state_caps;
3567
3568                         if (!led->led_group_id ||
3569                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3570                                 bp->num_leds = 0;
3571                                 break;
3572                         }
3573                 }
3574         }
3575
3576         HWRM_UNLOCK();
3577
3578         return rc;
3579 }
3580
3581 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3582 {
3583         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3584         struct hwrm_port_led_cfg_input req = {0};
3585         struct bnxt_led_cfg *led_cfg;
3586         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3587         uint16_t duration = 0;
3588         int rc, i;
3589
3590         if (!bp->num_leds || BNXT_VF(bp))
3591                 return -EOPNOTSUPP;
3592
3593         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3594
3595         if (led_on) {
3596                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3597                 duration = rte_cpu_to_le_16(500);
3598         }
3599         req.port_id = bp->pf.port_id;
3600         req.num_leds = bp->num_leds;
3601         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3602         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3603                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3604                 led_cfg->led_id = bp->leds[i].led_id;
3605                 led_cfg->led_state = led_state;
3606                 led_cfg->led_blink_on = duration;
3607                 led_cfg->led_blink_off = duration;
3608                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3609         }
3610
3611         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3612
3613         HWRM_CHECK_RESULT();
3614         HWRM_UNLOCK();
3615
3616         return rc;
3617 }
3618
3619 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3620                                uint32_t *length)
3621 {
3622         int rc;
3623         struct hwrm_nvm_get_dir_info_input req = {0};
3624         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3625
3626         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3627
3628         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3629
3630         HWRM_CHECK_RESULT();
3631
3632         *entries = rte_le_to_cpu_32(resp->entries);
3633         *length = rte_le_to_cpu_32(resp->entry_length);
3634
3635         HWRM_UNLOCK();
3636         return rc;
3637 }
3638
3639 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3640 {
3641         int rc;
3642         uint32_t dir_entries;
3643         uint32_t entry_length;
3644         uint8_t *buf;
3645         size_t buflen;
3646         rte_iova_t dma_handle;
3647         struct hwrm_nvm_get_dir_entries_input req = {0};
3648         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3649
3650         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3651         if (rc != 0)
3652                 return rc;
3653
3654         *data++ = dir_entries;
3655         *data++ = entry_length;
3656         len -= 2;
3657         memset(data, 0xff, len);
3658
3659         buflen = dir_entries * entry_length;
3660         buf = rte_malloc("nvm_dir", buflen, 0);
3661         rte_mem_lock_page(buf);
3662         if (buf == NULL)
3663                 return -ENOMEM;
3664         dma_handle = rte_mem_virt2iova(buf);
3665         if (dma_handle == RTE_BAD_IOVA) {
3666                 PMD_DRV_LOG(ERR,
3667                         "unable to map response address to physical memory\n");
3668                 return -ENOMEM;
3669         }
3670         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3671         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3672         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3673
3674         if (rc == 0)
3675                 memcpy(data, buf, len > buflen ? buflen : len);
3676
3677         rte_free(buf);
3678         HWRM_CHECK_RESULT();
3679         HWRM_UNLOCK();
3680
3681         return rc;
3682 }
3683
3684 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3685                              uint32_t offset, uint32_t length,
3686                              uint8_t *data)
3687 {
3688         int rc;
3689         uint8_t *buf;
3690         rte_iova_t dma_handle;
3691         struct hwrm_nvm_read_input req = {0};
3692         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3693
3694         buf = rte_malloc("nvm_item", length, 0);
3695         rte_mem_lock_page(buf);
3696         if (!buf)
3697                 return -ENOMEM;
3698
3699         dma_handle = rte_mem_virt2iova(buf);
3700         if (dma_handle == RTE_BAD_IOVA) {
3701                 PMD_DRV_LOG(ERR,
3702                         "unable to map response address to physical memory\n");
3703                 return -ENOMEM;
3704         }
3705         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3706         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3707         req.dir_idx = rte_cpu_to_le_16(index);
3708         req.offset = rte_cpu_to_le_32(offset);
3709         req.len = rte_cpu_to_le_32(length);
3710         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3711         if (rc == 0)
3712                 memcpy(data, buf, length);
3713
3714         rte_free(buf);
3715         HWRM_CHECK_RESULT();
3716         HWRM_UNLOCK();
3717
3718         return rc;
3719 }
3720
3721 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3722 {
3723         int rc;
3724         struct hwrm_nvm_erase_dir_entry_input req = {0};
3725         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3726
3727         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3728         req.dir_idx = rte_cpu_to_le_16(index);
3729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3730         HWRM_CHECK_RESULT();
3731         HWRM_UNLOCK();
3732
3733         return rc;
3734 }
3735
3736
3737 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3738                           uint16_t dir_ordinal, uint16_t dir_ext,
3739                           uint16_t dir_attr, const uint8_t *data,
3740                           size_t data_len)
3741 {
3742         int rc;
3743         struct hwrm_nvm_write_input req = {0};
3744         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3745         rte_iova_t dma_handle;
3746         uint8_t *buf;
3747
3748         buf = rte_malloc("nvm_write", data_len, 0);
3749         rte_mem_lock_page(buf);
3750         if (!buf)
3751                 return -ENOMEM;
3752
3753         dma_handle = rte_mem_virt2iova(buf);
3754         if (dma_handle == RTE_BAD_IOVA) {
3755                 PMD_DRV_LOG(ERR,
3756                         "unable to map response address to physical memory\n");
3757                 return -ENOMEM;
3758         }
3759         memcpy(buf, data, data_len);
3760
3761         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3762
3763         req.dir_type = rte_cpu_to_le_16(dir_type);
3764         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3765         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3766         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3767         req.dir_data_length = rte_cpu_to_le_32(data_len);
3768         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3769
3770         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3771
3772         rte_free(buf);
3773         HWRM_CHECK_RESULT();
3774         HWRM_UNLOCK();
3775
3776         return rc;
3777 }
3778
3779 static void
3780 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3781 {
3782         uint32_t *count = cbdata;
3783
3784         *count = *count + 1;
3785 }
3786
3787 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3788                                      struct bnxt_vnic_info *vnic __rte_unused)
3789 {
3790         return 0;
3791 }
3792
3793 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3794 {
3795         uint32_t count = 0;
3796
3797         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3798             &count, bnxt_vnic_count_hwrm_stub);
3799
3800         return count;
3801 }
3802
3803 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3804                                         uint16_t *vnic_ids)
3805 {
3806         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3807         struct hwrm_func_vf_vnic_ids_query_output *resp =
3808                                                 bp->hwrm_cmd_resp_addr;
3809         int rc;
3810
3811         /* First query all VNIC ids */
3812         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3813
3814         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3815         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3816         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3817
3818         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3819                 HWRM_UNLOCK();
3820                 PMD_DRV_LOG(ERR,
3821                 "unable to map VNIC ID table address to physical memory\n");
3822                 return -ENOMEM;
3823         }
3824         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3825         HWRM_CHECK_RESULT();
3826         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3827
3828         HWRM_UNLOCK();
3829
3830         return rc;
3831 }
3832
3833 /*
3834  * This function queries the VNIC IDs  for a specified VF. It then calls
3835  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3836  * Then it calls the hwrm_cb function to program this new vnic configuration.
3837  */
3838 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3839         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3840         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3841 {
3842         struct bnxt_vnic_info vnic;
3843         int rc = 0;
3844         int i, num_vnic_ids;
3845         uint16_t *vnic_ids;
3846         size_t vnic_id_sz;
3847         size_t sz;
3848
3849         /* First query all VNIC ids */
3850         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3851         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3852                         RTE_CACHE_LINE_SIZE);
3853         if (vnic_ids == NULL)
3854                 return -ENOMEM;
3855
3856         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3857                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3858
3859         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3860
3861         if (num_vnic_ids < 0)
3862                 return num_vnic_ids;
3863
3864         /* Retrieve VNIC, update bd_stall then update */
3865
3866         for (i = 0; i < num_vnic_ids; i++) {
3867                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3868                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3869                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3870                 if (rc)
3871                         break;
3872                 if (vnic.mru <= 4)      /* Indicates unallocated */
3873                         continue;
3874
3875                 vnic_cb(&vnic, cbdata);
3876
3877                 rc = hwrm_cb(bp, &vnic);
3878                 if (rc)
3879                         break;
3880         }
3881
3882         rte_free(vnic_ids);
3883
3884         return rc;
3885 }
3886
3887 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3888                                               bool on)
3889 {
3890         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3891         struct hwrm_func_cfg_input req = {0};
3892         int rc;
3893
3894         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3895
3896         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3897         req.enables |= rte_cpu_to_le_32(
3898                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3899         req.vlan_antispoof_mode = on ?
3900                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3901                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3902         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3903
3904         HWRM_CHECK_RESULT();
3905         HWRM_UNLOCK();
3906
3907         return rc;
3908 }
3909
3910 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3911 {
3912         struct bnxt_vnic_info vnic;
3913         uint16_t *vnic_ids;
3914         size_t vnic_id_sz;
3915         int num_vnic_ids, i;
3916         size_t sz;
3917         int rc;
3918
3919         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3920         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3921                         RTE_CACHE_LINE_SIZE);
3922         if (vnic_ids == NULL)
3923                 return -ENOMEM;
3924
3925         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3926                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3927
3928         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3929         if (rc <= 0)
3930                 goto exit;
3931         num_vnic_ids = rc;
3932
3933         /*
3934          * Loop through to find the default VNIC ID.
3935          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3936          * by sending the hwrm_func_qcfg command to the firmware.
3937          */
3938         for (i = 0; i < num_vnic_ids; i++) {
3939                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3940                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3941                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3942                                         bp->pf.first_vf_id + vf);
3943                 if (rc)
3944                         goto exit;
3945                 if (vnic.func_default) {
3946                         rte_free(vnic_ids);
3947                         return vnic.fw_vnic_id;
3948                 }
3949         }
3950         /* Could not find a default VNIC. */
3951         PMD_DRV_LOG(ERR, "No default VNIC\n");
3952 exit:
3953         rte_free(vnic_ids);
3954         return rc;
3955 }
3956
3957 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3958                          uint16_t dst_id,
3959                          struct bnxt_filter_info *filter)
3960 {
3961         int rc = 0;
3962         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3963         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3964         uint32_t enables = 0;
3965
3966         if (filter->fw_em_filter_id != UINT64_MAX)
3967                 bnxt_hwrm_clear_em_filter(bp, filter);
3968
3969         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3970
3971         req.flags = rte_cpu_to_le_32(filter->flags);
3972
3973         enables = filter->enables |
3974               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3975         req.dst_id = rte_cpu_to_le_16(dst_id);
3976
3977         if (filter->ip_addr_type) {
3978                 req.ip_addr_type = filter->ip_addr_type;
3979                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3980         }
3981         if (enables &
3982             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3983                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3984         if (enables &
3985             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3986                 memcpy(req.src_macaddr, filter->src_macaddr,
3987                        RTE_ETHER_ADDR_LEN);
3988         if (enables &
3989             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3990                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3991                        RTE_ETHER_ADDR_LEN);
3992         if (enables &
3993             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3994                 req.ovlan_vid = filter->l2_ovlan;
3995         if (enables &
3996             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3997                 req.ivlan_vid = filter->l2_ivlan;
3998         if (enables &
3999             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4000                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4001         if (enables &
4002             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4003                 req.ip_protocol = filter->ip_protocol;
4004         if (enables &
4005             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4006                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4007         if (enables &
4008             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4009                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4010         if (enables &
4011             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4012                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4013         if (enables &
4014             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4015                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4016         if (enables &
4017             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4018                 req.mirror_vnic_id = filter->mirror_vnic_id;
4019
4020         req.enables = rte_cpu_to_le_32(enables);
4021
4022         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4023
4024         HWRM_CHECK_RESULT();
4025
4026         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4027         HWRM_UNLOCK();
4028
4029         return rc;
4030 }
4031
4032 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4033 {
4034         int rc = 0;
4035         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4036         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4037
4038         if (filter->fw_em_filter_id == UINT64_MAX)
4039                 return 0;
4040
4041         PMD_DRV_LOG(ERR, "Clear EM filter\n");
4042         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4043
4044         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4045
4046         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4047
4048         HWRM_CHECK_RESULT();
4049         HWRM_UNLOCK();
4050
4051         filter->fw_em_filter_id = UINT64_MAX;
4052         filter->fw_l2_filter_id = UINT64_MAX;
4053
4054         return 0;
4055 }
4056
4057 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4058                          uint16_t dst_id,
4059                          struct bnxt_filter_info *filter)
4060 {
4061         int rc = 0;
4062         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4063         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4064                                                 bp->hwrm_cmd_resp_addr;
4065         uint32_t enables = 0;
4066
4067         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4068                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4069
4070         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4071
4072         req.flags = rte_cpu_to_le_32(filter->flags);
4073
4074         enables = filter->enables |
4075               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4076         req.dst_id = rte_cpu_to_le_16(dst_id);
4077
4078
4079         if (filter->ip_addr_type) {
4080                 req.ip_addr_type = filter->ip_addr_type;
4081                 enables |=
4082                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4083         }
4084         if (enables &
4085             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4086                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4087         if (enables &
4088             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4089                 memcpy(req.src_macaddr, filter->src_macaddr,
4090                        RTE_ETHER_ADDR_LEN);
4091         //if (enables &
4092             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4093                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4094                        //RTE_ETHER_ADDR_LEN);
4095         if (enables &
4096             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4097                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4098         if (enables &
4099             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4100                 req.ip_protocol = filter->ip_protocol;
4101         if (enables &
4102             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4103                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4104         if (enables &
4105             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4106                 req.src_ipaddr_mask[0] =
4107                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4108         if (enables &
4109             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4110                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4111         if (enables &
4112             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4113                 req.dst_ipaddr_mask[0] =
4114                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4115         if (enables &
4116             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4117                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4118         if (enables &
4119             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4120                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4121         if (enables &
4122             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4123                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4124         if (enables &
4125             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4126                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4127         if (enables &
4128             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4129                 req.mirror_vnic_id = filter->mirror_vnic_id;
4130
4131         req.enables = rte_cpu_to_le_32(enables);
4132
4133         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4134
4135         HWRM_CHECK_RESULT();
4136
4137         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4138         HWRM_UNLOCK();
4139
4140         return rc;
4141 }
4142
4143 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4144                                 struct bnxt_filter_info *filter)
4145 {
4146         int rc = 0;
4147         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4148         struct hwrm_cfa_ntuple_filter_free_output *resp =
4149                                                 bp->hwrm_cmd_resp_addr;
4150
4151         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4152                 return 0;
4153
4154         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4155
4156         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4157
4158         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4159
4160         HWRM_CHECK_RESULT();
4161         HWRM_UNLOCK();
4162
4163         filter->fw_ntuple_filter_id = UINT64_MAX;
4164
4165         return 0;
4166 }
4167
4168 static int
4169 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4170 {
4171         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4172         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4173         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4174         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4175         uint16_t *ring_tbl = vnic->rss_table;
4176         int nr_ctxs = vnic->num_lb_ctxts;
4177         int max_rings = bp->rx_nr_rings;
4178         int i, j, k, cnt;
4179         int rc = 0;
4180
4181         for (i = 0, k = 0; i < nr_ctxs; i++) {
4182                 struct bnxt_rx_ring_info *rxr;
4183                 struct bnxt_cp_ring_info *cpr;
4184
4185                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4186
4187                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4188                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4189                 req.hash_mode_flags = vnic->hash_mode;
4190
4191                 req.ring_grp_tbl_addr =
4192                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4193                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4194                                      2 * sizeof(*ring_tbl));
4195                 req.hash_key_tbl_addr =
4196                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4197
4198                 req.ring_table_pair_index = i;
4199                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4200
4201                 for (j = 0; j < 64; j++) {
4202                         uint16_t ring_id;
4203
4204                         /* Find next active ring. */
4205                         for (cnt = 0; cnt < max_rings; cnt++) {
4206                                 if (rx_queue_state[k] !=
4207                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4208                                         break;
4209                                 if (++k == max_rings)
4210                                         k = 0;
4211                         }
4212
4213                         /* Return if no rings are active. */
4214                         if (cnt == max_rings)
4215                                 return 0;
4216
4217                         /* Add rx/cp ring pair to RSS table. */
4218                         rxr = rxqs[k]->rx_ring;
4219                         cpr = rxqs[k]->cp_ring;
4220
4221                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4222                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4223                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4224                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4225
4226                         if (++k == max_rings)
4227                                 k = 0;
4228                 }
4229                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4230                                             BNXT_USE_CHIMP_MB);
4231
4232                 HWRM_CHECK_RESULT();
4233                 HWRM_UNLOCK();
4234         }
4235
4236         return rc;
4237 }
4238
4239 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4240 {
4241         unsigned int rss_idx, fw_idx, i;
4242
4243         if (!(vnic->rss_table && vnic->hash_type))
4244                 return 0;
4245
4246         if (BNXT_CHIP_THOR(bp))
4247                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4248
4249         /*
4250          * Fill the RSS hash & redirection table with
4251          * ring group ids for all VNICs
4252          */
4253         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4254                 rss_idx++, fw_idx++) {
4255                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4256                         fw_idx %= bp->rx_cp_nr_rings;
4257                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4258                                 break;
4259                         fw_idx++;
4260                 }
4261                 if (i == bp->rx_cp_nr_rings)
4262                         return 0;
4263                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4264         }
4265         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4266 }
4267
4268 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4269         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4270 {
4271         uint16_t flags;
4272
4273         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4274
4275         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4276         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4277
4278         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4279         req->num_cmpl_dma_aggr_during_int =
4280                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4281
4282         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4283
4284         /* min timer set to 1/2 of interrupt timer */
4285         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4286
4287         /* buf timer set to 1/4 of interrupt timer */
4288         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4289
4290         req->cmpl_aggr_dma_tmr_during_int =
4291                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4292
4293         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4294                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4295         req->flags = rte_cpu_to_le_16(flags);
4296 }
4297
4298 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4299                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4300 {
4301         struct hwrm_ring_aggint_qcaps_input req = {0};
4302         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4303         uint32_t enables;
4304         uint16_t flags;
4305         int rc;
4306
4307         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4308         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4309         HWRM_CHECK_RESULT();
4310
4311         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4312         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4313
4314         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4315                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4316         agg_req->flags = rte_cpu_to_le_16(flags);
4317         enables =
4318          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4319          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4320         agg_req->enables = rte_cpu_to_le_32(enables);
4321
4322         HWRM_UNLOCK();
4323         return rc;
4324 }
4325
4326 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4327                         struct bnxt_coal *coal, uint16_t ring_id)
4328 {
4329         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4330         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4331                                                 bp->hwrm_cmd_resp_addr;
4332         int rc;
4333
4334         /* Set ring coalesce parameters only for 100G NICs */
4335         if (BNXT_CHIP_THOR(bp)) {
4336                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4337                         return -1;
4338         } else if (bnxt_stratus_device(bp)) {
4339                 bnxt_hwrm_set_coal_params(coal, &req);
4340         } else {
4341                 return 0;
4342         }
4343
4344         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4345         req.ring_id = rte_cpu_to_le_16(ring_id);
4346         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4347         HWRM_CHECK_RESULT();
4348         HWRM_UNLOCK();
4349         return 0;
4350 }
4351
4352 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4353 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4354 {
4355         struct hwrm_func_backing_store_qcaps_input req = {0};
4356         struct hwrm_func_backing_store_qcaps_output *resp =
4357                 bp->hwrm_cmd_resp_addr;
4358         int rc;
4359
4360         if (!BNXT_CHIP_THOR(bp) ||
4361             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4362             BNXT_VF(bp) ||
4363             bp->ctx)
4364                 return 0;
4365
4366         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4367         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4368         HWRM_CHECK_RESULT_SILENT();
4369
4370         if (!rc) {
4371                 struct bnxt_ctx_pg_info *ctx_pg;
4372                 struct bnxt_ctx_mem_info *ctx;
4373                 int total_alloc_len;
4374                 int i;
4375
4376                 total_alloc_len = sizeof(*ctx);
4377                 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4378                                  RTE_CACHE_LINE_SIZE);
4379                 if (!ctx) {
4380                         rc = -ENOMEM;
4381                         goto ctx_err;
4382                 }
4383                 memset(ctx, 0, total_alloc_len);
4384
4385                 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4386                                     sizeof(*ctx_pg) * BNXT_MAX_Q,
4387                                     RTE_CACHE_LINE_SIZE);
4388                 if (!ctx_pg) {
4389                         rc = -ENOMEM;
4390                         goto ctx_err;
4391                 }
4392                 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4393                         ctx->tqm_mem[i] = ctx_pg;
4394
4395                 bp->ctx = ctx;
4396                 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4397                 ctx->qp_min_qp1_entries =
4398                         rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4399                 ctx->qp_max_l2_entries =
4400                         rte_le_to_cpu_16(resp->qp_max_l2_entries);
4401                 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4402                 ctx->srq_max_l2_entries =
4403                         rte_le_to_cpu_16(resp->srq_max_l2_entries);
4404                 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4405                 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4406                 ctx->cq_max_l2_entries =
4407                         rte_le_to_cpu_16(resp->cq_max_l2_entries);
4408                 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4409                 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4410                 ctx->vnic_max_vnic_entries =
4411                         rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4412                 ctx->vnic_max_ring_table_entries =
4413                         rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4414                 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4415                 ctx->stat_max_entries =
4416                         rte_le_to_cpu_32(resp->stat_max_entries);
4417                 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4418                 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4419                 ctx->tqm_min_entries_per_ring =
4420                         rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4421                 ctx->tqm_max_entries_per_ring =
4422                         rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4423                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4424                 if (!ctx->tqm_entries_multiple)
4425                         ctx->tqm_entries_multiple = 1;
4426                 ctx->mrav_max_entries =
4427                         rte_le_to_cpu_32(resp->mrav_max_entries);
4428                 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4429                 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4430                 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4431         } else {
4432                 rc = 0;
4433         }
4434 ctx_err:
4435         HWRM_UNLOCK();
4436         return rc;
4437 }
4438
4439 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4440 {
4441         struct hwrm_func_backing_store_cfg_input req = {0};
4442         struct hwrm_func_backing_store_cfg_output *resp =
4443                 bp->hwrm_cmd_resp_addr;
4444         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4445         struct bnxt_ctx_pg_info *ctx_pg;
4446         uint32_t *num_entries;
4447         uint64_t *pg_dir;
4448         uint8_t *pg_attr;
4449         uint32_t ena;
4450         int i, rc;
4451
4452         if (!ctx)
4453                 return 0;
4454
4455         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4456         req.enables = rte_cpu_to_le_32(enables);
4457
4458         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4459                 ctx_pg = &ctx->qp_mem;
4460                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4461                 req.qp_num_qp1_entries =
4462                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4463                 req.qp_num_l2_entries =
4464                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4465                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4466                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4467                                       &req.qpc_pg_size_qpc_lvl,
4468                                       &req.qpc_page_dir);
4469         }
4470
4471         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4472                 ctx_pg = &ctx->srq_mem;
4473                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4474                 req.srq_num_l2_entries =
4475                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4476                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4477                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4478                                       &req.srq_pg_size_srq_lvl,
4479                                       &req.srq_page_dir);
4480         }
4481
4482         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4483                 ctx_pg = &ctx->cq_mem;
4484                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4485                 req.cq_num_l2_entries =
4486                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4487                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4488                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4489                                       &req.cq_pg_size_cq_lvl,
4490                                       &req.cq_page_dir);
4491         }
4492
4493         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4494                 ctx_pg = &ctx->vnic_mem;
4495                 req.vnic_num_vnic_entries =
4496                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4497                 req.vnic_num_ring_table_entries =
4498                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4499                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4500                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4501                                       &req.vnic_pg_size_vnic_lvl,
4502                                       &req.vnic_page_dir);
4503         }
4504
4505         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4506                 ctx_pg = &ctx->stat_mem;
4507                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4508                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4509                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4510                                       &req.stat_pg_size_stat_lvl,
4511                                       &req.stat_page_dir);
4512         }
4513
4514         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4515         num_entries = &req.tqm_sp_num_entries;
4516         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4517         pg_dir = &req.tqm_sp_page_dir;
4518         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4519         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4520                 if (!(enables & ena))
4521                         continue;
4522
4523                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4524
4525                 ctx_pg = ctx->tqm_mem[i];
4526                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4527                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4528         }
4529
4530         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4531         HWRM_CHECK_RESULT();
4532         HWRM_UNLOCK();
4533
4534         return rc;
4535 }
4536
4537 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4538 {
4539         struct hwrm_port_qstats_ext_input req = {0};
4540         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4541         struct bnxt_pf_info *pf = &bp->pf;
4542         int rc;
4543
4544         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4545               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4546                 return 0;
4547
4548         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4549
4550         req.port_id = rte_cpu_to_le_16(pf->port_id);
4551         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4552                 req.tx_stat_host_addr =
4553                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4554                 req.tx_stat_size =
4555                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4556         }
4557         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4558                 req.rx_stat_host_addr =
4559                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4560                 req.rx_stat_size =
4561                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4562         }
4563         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4564
4565         if (rc) {
4566                 bp->fw_rx_port_stats_ext_size = 0;
4567                 bp->fw_tx_port_stats_ext_size = 0;
4568         } else {
4569                 bp->fw_rx_port_stats_ext_size =
4570                         rte_le_to_cpu_16(resp->rx_stat_size);
4571                 bp->fw_tx_port_stats_ext_size =
4572                         rte_le_to_cpu_16(resp->tx_stat_size);
4573         }
4574
4575         HWRM_CHECK_RESULT();
4576         HWRM_UNLOCK();
4577
4578         return rc;
4579 }
4580
4581 int
4582 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4583 {
4584         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4585         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4586                 bp->hwrm_cmd_resp_addr;
4587         int rc = 0;
4588
4589         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4590         req.tunnel_type = type;
4591         req.dest_fid = bp->fw_fid;
4592         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4593         HWRM_CHECK_RESULT();
4594
4595         HWRM_UNLOCK();
4596
4597         return rc;
4598 }
4599
4600 int
4601 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4602 {
4603         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4604         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4605                 bp->hwrm_cmd_resp_addr;
4606         int rc = 0;
4607
4608         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4609         req.tunnel_type = type;
4610         req.dest_fid = bp->fw_fid;
4611         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4612         HWRM_CHECK_RESULT();
4613
4614         HWRM_UNLOCK();
4615
4616         return rc;
4617 }
4618
4619 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4620 {
4621         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4622         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4623                 bp->hwrm_cmd_resp_addr;
4624         int rc = 0;
4625
4626         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4627         req.src_fid = bp->fw_fid;
4628         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4629         HWRM_CHECK_RESULT();
4630
4631         if (type)
4632                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4633
4634         HWRM_UNLOCK();
4635
4636         return rc;
4637 }
4638
4639 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4640                                    uint16_t *dst_fid)
4641 {
4642         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4643         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4644                 bp->hwrm_cmd_resp_addr;
4645         int rc = 0;
4646
4647         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4648         req.src_fid = bp->fw_fid;
4649         req.tunnel_type = tun_type;
4650         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4651         HWRM_CHECK_RESULT();
4652
4653         if (dst_fid)
4654                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4655
4656         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4657
4658         HWRM_UNLOCK();
4659
4660         return rc;
4661 }
4662
4663 int bnxt_hwrm_set_mac(struct bnxt *bp)
4664 {
4665         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4666         struct hwrm_func_vf_cfg_input req = {0};
4667         int rc = 0;
4668
4669         if (!BNXT_VF(bp))
4670                 return 0;
4671
4672         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4673
4674         req.enables =
4675                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4676         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4677
4678         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4679
4680         HWRM_CHECK_RESULT();
4681
4682         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4683         HWRM_UNLOCK();
4684
4685         return rc;
4686 }
4687
4688 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4689 {
4690         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4691         struct hwrm_func_drv_if_change_input req = {0};
4692         uint32_t flags;
4693         int rc;
4694
4695         if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4696                 return 0;
4697
4698         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4699          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4700          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4701          */
4702         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4703                 return 0;
4704
4705         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4706
4707         if (up)
4708                 req.flags =
4709                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4710
4711         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4712
4713         HWRM_CHECK_RESULT();
4714         flags = rte_le_to_cpu_32(resp->flags);
4715         HWRM_UNLOCK();
4716
4717         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4718                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4719                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4720         }
4721
4722         return 0;
4723 }
4724
4725 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4726 {
4727         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4728         struct bnxt_error_recovery_info *info = bp->recovery_info;
4729         struct hwrm_error_recovery_qcfg_input req = {0};
4730         uint32_t flags = 0;
4731         unsigned int i;
4732         int rc;
4733
4734         /* Older FW does not have error recovery support */
4735         if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4736                 return 0;
4737
4738         if (!info) {
4739                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4740                                    sizeof(*info), 0);
4741                 bp->recovery_info = info;
4742                 if (info == NULL)
4743                         return -ENOMEM;
4744         } else {
4745                 memset(info, 0, sizeof(*info));
4746         }
4747
4748         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4749
4750         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4751
4752         HWRM_CHECK_RESULT();
4753
4754         flags = rte_le_to_cpu_32(resp->flags);
4755         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4756                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4757         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4758                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4759
4760         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4761             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4762                 rc = -EINVAL;
4763                 goto err;
4764         }
4765
4766         /* FW returned values are in units of 100msec */
4767         info->driver_polling_freq =
4768                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4769         info->master_func_wait_period =
4770                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4771         info->normal_func_wait_period =
4772                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4773         info->master_func_wait_period_after_reset =
4774                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4775         info->max_bailout_time_after_reset =
4776                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4777         info->status_regs[BNXT_FW_STATUS_REG] =
4778                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4779         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4780                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4781         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4782                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4783         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4784                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4785         info->reg_array_cnt =
4786                 rte_le_to_cpu_32(resp->reg_array_cnt);
4787
4788         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4789                 rc = -EINVAL;
4790                 goto err;
4791         }
4792
4793         for (i = 0; i < info->reg_array_cnt; i++) {
4794                 info->reset_reg[i] =
4795                         rte_le_to_cpu_32(resp->reset_reg[i]);
4796                 info->reset_reg_val[i] =
4797                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4798                 info->delay_after_reset[i] =
4799                         resp->delay_after_reset[i];
4800         }
4801 err:
4802         HWRM_UNLOCK();
4803
4804         /* Map the FW status registers */
4805         if (!rc)
4806                 rc = bnxt_map_fw_health_status_regs(bp);
4807
4808         if (rc) {
4809                 rte_free(bp->recovery_info);
4810                 bp->recovery_info = NULL;
4811         }
4812         return rc;
4813 }
4814
4815 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4816 {
4817         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4818         struct hwrm_fw_reset_input req = {0};
4819         int rc;
4820
4821         if (!BNXT_PF(bp))
4822                 return -EOPNOTSUPP;
4823
4824         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4825
4826         req.embedded_proc_type =
4827                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4828         req.selfrst_status =
4829                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4830         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4831
4832         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4833                                     BNXT_USE_KONG(bp));
4834
4835         HWRM_CHECK_RESULT();
4836         HWRM_UNLOCK();
4837
4838         return rc;
4839 }
4840
4841 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4842 {
4843         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4844         struct hwrm_port_ts_query_input req = {0};
4845         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4846         uint32_t flags = 0;
4847         int rc;
4848
4849         if (!ptp)
4850                 return 0;
4851
4852         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4853
4854         switch (path) {
4855         case BNXT_PTP_FLAGS_PATH_TX:
4856                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4857                 break;
4858         case BNXT_PTP_FLAGS_PATH_RX:
4859                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4860                 break;
4861         case BNXT_PTP_FLAGS_CURRENT_TIME:
4862                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
4863                 break;
4864         }
4865
4866         req.flags = rte_cpu_to_le_32(flags);
4867         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
4868
4869         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4870
4871         HWRM_CHECK_RESULT();
4872
4873         if (timestamp) {
4874                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
4875                 *timestamp |=
4876                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
4877         }
4878         HWRM_UNLOCK();
4879
4880         return rc;
4881 }