drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SPEC_CODE_1_8_3            0x10803
  31 #define HWRM_VERSION_1_9_1              0x10901
  32 #define HWRM_VERSION_1_9_2              0x10903
  33
  34 struct bnxt_plcmodes_cfg {
  35         uint32_t        flags;
  36         uint16_t        jumbo_thresh;
  37         uint16_t        hds_offset;
  38         uint16_t        hds_threshold;
  39 };
  40
  41 static int page_getenum(size_t size)
  42 {
  43         if (size <= 1 << 4)
  44                 return 4;
  45         if (size <= 1 << 12)
  46                 return 12;
  47         if (size <= 1 << 13)
  48                 return 13;
  49         if (size <= 1 << 16)
  50                 return 16;
  51         if (size <= 1 << 21)
  52                 return 21;
  53         if (size <= 1 << 22)
  54                 return 22;
  55         if (size <= 1 << 30)
  56                 return 30;
  57         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  58         return sizeof(void *) * 8 - 1;
  59 }
  60
  61 static int page_roundup(size_t size)
  62 {
  63         return 1 << page_getenum(size);
  64 }
  65
  66 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  67                                   uint8_t *pg_attr,
  68                                   uint64_t *pg_dir)
  69 {
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 /*
  79  * HWRM Functions (sent to HWRM)
  80  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  81  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  82  * command was failed by the ChiMP.
  83  */
  84
  85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  86                                   uint32_t msg_len, bool use_kong_mb)
  87 {
  88         unsigned int i;
  89         struct input *req = msg;
  90         struct output *resp = bp->hwrm_cmd_resp_addr;
  91         uint32_t *data = msg;
  92         uint8_t *bar;
  93         uint8_t *valid;
  94         uint16_t max_req_len = bp->max_req_len;
  95         struct hwrm_short_input short_input = { 0 };
  96         uint16_t bar_offset = use_kong_mb ?
  97                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  98         uint16_t mb_trigger_offset = use_kong_mb ?
  99                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 100
 101         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 102             msg_len > bp->max_req_len) {
 103                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 104
 105                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 106                 memcpy(short_cmd_req, req, msg_len);
 107
 108                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 109                 short_input.signature = rte_cpu_to_le_16(
 110                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 111                 short_input.size = rte_cpu_to_le_16(msg_len);
 112                 short_input.req_addr =
 113                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 114
 115                 data = (uint32_t *)&short_input;
 116                 msg_len = sizeof(short_input);
 117
 118                 /* Sync memory write before updating doorbell */
 119                 rte_wmb();
 120
 121                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 122         }
 123
 124         /* Write request msg to hwrm channel */
 125         for (i = 0; i < msg_len; i += 4) {
 126                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 127                 rte_write32(*data, bar);
 128                 data++;
 129         }
 130
 131         /* Zero the rest of the request space */
 132         for (; i < max_req_len; i += 4) {
 133                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 134                 rte_write32(0, bar);
 135         }
 136
 137         /* Ring channel doorbell */
 138         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 139         rte_write32(1, bar);
 140
 141         /* Poll for the valid bit */
 142         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 143                 /* Sanity check on the resp->resp_len */
 144                 rte_rmb();
 145                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 146                         /* Last byte of resp contains the valid key */
 147                         valid = (uint8_t *)resp + resp->resp_len - 1;
 148                         if (*valid == HWRM_RESP_VALID_KEY)
 149                                 break;
 150                 }
 151                 rte_delay_us(1);
 152         }
 153
 154         if (i >= HWRM_CMD_TIMEOUT) {
 155                 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
 156                         req->req_type);
 157                 goto err_ret;
 158         }
 159         return 0;
 160
 161 err_ret:
 162         return -1;
 163 }
 164
 165 /*
 166  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 167  * spinlock, and does initial processing.
 168  *
 169  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 170  * releases the spinlock only if it returns.  If the regular int return codes
 171  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 172  * directly, rather it should be copied and modified to suit the function.
 173  *
 174  * HWRM_UNLOCK() must be called after all response processing is completed.
 175  */
 176 #define HWRM_PREP(req, type, kong) do { \
 177         rte_spinlock_lock(&bp->hwrm_lock); \
 178         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 179         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 180         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 181         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 182                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 183         req.target_id = rte_cpu_to_le_16(0xffff); \
 184         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 185 } while (0)
 186
 187 #define HWRM_CHECK_RESULT_SILENT() do {\
 188         if (rc) { \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 return rc; \
 191         } \
 192         if (resp->error_code) { \
 193                 rc = rte_le_to_cpu_16(resp->error_code); \
 194                 rte_spinlock_unlock(&bp->hwrm_lock); \
 195                 return rc; \
 196         } \
 197 } while (0)
 198
 199 #define HWRM_CHECK_RESULT() do {\
 200         if (rc) { \
 201                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 204                         rc = -EACCES; \
 205                 else if (rc > 0) \
 206                         rc = -EINVAL; \
 207                 return rc; \
 208         } \
 209         if (resp->error_code) { \
 210                 rc = rte_le_to_cpu_16(resp->error_code); \
 211                 if (resp->resp_len >= 16) { \
 212                         struct hwrm_err_output *tmp_hwrm_err_op = \
 213                                                 (void *)resp; \
 214                         PMD_DRV_LOG(ERR, \
 215                                 "error %d:%d:%08x:%04x\n", \
 216                                 rc, tmp_hwrm_err_op->cmd_err, \
 217                                 rte_le_to_cpu_32(\
 218                                         tmp_hwrm_err_op->opaque_0), \
 219                                 rte_le_to_cpu_16(\
 220                                         tmp_hwrm_err_op->opaque_1)); \
 221                 } else { \
 222                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 223                 } \
 224                 rte_spinlock_unlock(&bp->hwrm_lock); \
 225                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 226                         rc = -EACCES; \
 227                 else if (rc > 0) \
 228                         rc = -EINVAL; \
 229                 return rc; \
 230         } \
 231 } while (0)
 232
 233 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 234
 235 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 236 {
 237         int rc = 0;
 238         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 239         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 240
 241         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 242         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 243         req.mask = 0;
 244
 245         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 246
 247         HWRM_CHECK_RESULT();
 248         HWRM_UNLOCK();
 249
 250         return rc;
 251 }
 252
 253 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 254                                  struct bnxt_vnic_info *vnic,
 255                                  uint16_t vlan_count,
 256                                  struct bnxt_vlan_table_entry *vlan_table)
 257 {
 258         int rc = 0;
 259         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 260         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 261         uint32_t mask = 0;
 262
 263         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 264                 return rc;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268
 269         /* FIXME add multicast flag, when multicast adding options is supported
 270          * by ethtool.
 271          */
 272         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 273                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 274         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 275                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 276         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 277                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 278         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 279                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 280         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 281                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 282         if (vnic->mc_addr_cnt) {
 283                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 284                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 285                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 286         }
 287         if (vlan_table) {
 288                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 289                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 290                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 291                          rte_mem_virt2iova(vlan_table));
 292                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 293         }
 294         req.mask = rte_cpu_to_le_32(mask);
 295
 296         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 297
 298         HWRM_CHECK_RESULT();
 299         HWRM_UNLOCK();
 300
 301         return rc;
 302 }
 303
 304 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 305                         uint16_t vlan_count,
 306                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 307 {
 308         int rc = 0;
 309         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 310         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 311                                                 bp->hwrm_cmd_resp_addr;
 312
 313         /*
 314          * Older HWRM versions did not support this command, and the set_rx_mask
 315          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 316          * removed from set_rx_mask call, and this command was added.
 317          *
 318          * This command is also present from 1.7.8.11 and higher,
 319          * as well as 1.7.8.0
 320          */
 321         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 322                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 323                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 324                                         (11)))
 325                                 return 0;
 326                 }
 327         }
 328         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 329         req.fid = rte_cpu_to_le_16(fid);
 330
 331         req.vlan_tag_mask_tbl_addr =
 332                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 333         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 334
 335         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 336
 337         HWRM_CHECK_RESULT();
 338         HWRM_UNLOCK();
 339
 340         return rc;
 341 }
 342
 343 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 344                            struct bnxt_filter_info *filter)
 345 {
 346         int rc = 0;
 347         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 348         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 349
 350         if (filter->fw_l2_filter_id == UINT64_MAX)
 351                 return 0;
 352
 353         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 354
 355         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         filter->fw_l2_filter_id = UINT64_MAX;
 363
 364         return 0;
 365 }
 366
 367 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 368                          uint16_t dst_id,
 369                          struct bnxt_filter_info *filter)
 370 {
 371         int rc = 0;
 372         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 373         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 374         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 375         const struct rte_eth_vmdq_rx_conf *conf =
 376                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 377         uint32_t enables = 0;
 378         uint16_t j = dst_id - 1;
 379
 380         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 381         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 382             conf->pool_map[j].pools & (1UL << j)) {
 383                 PMD_DRV_LOG(DEBUG,
 384                         "Add vlan %u to vmdq pool %u\n",
 385                         conf->pool_map[j].vlan_id, j);
 386
 387                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 388                 filter->enables |=
 389                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 390                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 391         }
 392
 393         if (filter->fw_l2_filter_id != UINT64_MAX)
 394                 bnxt_hwrm_clear_l2_filter(bp, filter);
 395
 396         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 397
 398         req.flags = rte_cpu_to_le_32(filter->flags);
 399         req.flags |=
 400         rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
 401
 402         enables = filter->enables |
 403               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 404         req.dst_id = rte_cpu_to_le_16(dst_id);
 405
 406         if (enables &
 407             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 408                 memcpy(req.l2_addr, filter->l2_addr,
 409                        RTE_ETHER_ADDR_LEN);
 410         if (enables &
 411             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 412                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 413                        RTE_ETHER_ADDR_LEN);
 414         if (enables &
 415             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 416                 req.l2_ovlan = filter->l2_ovlan;
 417         if (enables &
 418             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 419                 req.l2_ivlan = filter->l2_ivlan;
 420         if (enables &
 421             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 422                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 423         if (enables &
 424             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 425                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 426         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 427                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 428         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 429                 req.src_type = filter->src_type;
 430
 431         req.enables = rte_cpu_to_le_32(enables);
 432
 433         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 434
 435         HWRM_CHECK_RESULT();
 436
 437         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 438         HWRM_UNLOCK();
 439
 440         return rc;
 441 }
 442
 443 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 444 {
 445         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 446         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 447         uint32_t flags = 0;
 448         int rc;
 449
 450         if (!ptp)
 451                 return 0;
 452
 453         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 454
 455         if (ptp->rx_filter)
 456                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 457         else
 458                 flags |=
 459                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 460         if (ptp->tx_tstamp_en)
 461                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 462         else
 463                 flags |=
 464                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 465         req.flags = rte_cpu_to_le_32(flags);
 466         req.enables = rte_cpu_to_le_32
 467                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 468         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 469
 470         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 471         HWRM_UNLOCK();
 472
 473         return rc;
 474 }
 475
 476 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 477 {
 478         int rc = 0;
 479         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 480         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 481         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 482
 483 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 484         if (ptp)
 485                 return 0;
 486
 487         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 488
 489         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 490
 491         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 492
 493         HWRM_CHECK_RESULT();
 494
 495         if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 496                 return 0;
 497
 498         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 499         if (!ptp)
 500                 return -ENOMEM;
 501
 502         ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 503                 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 504         ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 505                 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 506         ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 507                 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 508         ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 509                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 510         ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 511                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 512         ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 513                 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 514         ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 515                 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 516         ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 517                 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 518         ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 519                 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 520
 521         ptp->bp = bp;
 522         bp->ptp_cfg = ptp;
 523
 524         return 0;
 525 }
 526
 527 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 528 {
 529         int rc = 0;
 530         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 531         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 532         uint16_t new_max_vfs;
 533         uint32_t flags;
 534         int i;
 535
 536         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 537
 538         req.fid = rte_cpu_to_le_16(0xffff);
 539
 540         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 541
 542         HWRM_CHECK_RESULT();
 543
 544         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 545         flags = rte_le_to_cpu_32(resp->flags);
 546         if (BNXT_PF(bp)) {
 547                 bp->pf.port_id = resp->port_id;
 548                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 549                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 550                 new_max_vfs = bp->pdev->max_vfs;
 551                 if (new_max_vfs != bp->pf.max_vfs) {
 552                         if (bp->pf.vf_info)
 553                                 rte_free(bp->pf.vf_info);
 554                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 555                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 556                         bp->pf.max_vfs = new_max_vfs;
 557                         for (i = 0; i < new_max_vfs; i++) {
 558                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 559                                 bp->pf.vf_info[i].vlan_table =
 560                                         rte_zmalloc("VF VLAN table",
 561                                                     getpagesize(),
 562                                                     getpagesize());
 563                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 564                                         PMD_DRV_LOG(ERR,
 565                                         "Fail to alloc VLAN table for VF %d\n",
 566                                         i);
 567                                 else
 568                                         rte_mem_lock_page(
 569                                                 bp->pf.vf_info[i].vlan_table);
 570                                 bp->pf.vf_info[i].vlan_as_table =
 571                                         rte_zmalloc("VF VLAN AS table",
 572                                                     getpagesize(),
 573                                                     getpagesize());
 574                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 575                                         PMD_DRV_LOG(ERR,
 576                                         "Alloc VLAN AS table for VF %d fail\n",
 577                                         i);
 578                                 else
 579                                         rte_mem_lock_page(
 580                                                bp->pf.vf_info[i].vlan_as_table);
 581                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 582                         }
 583                 }
 584         }
 585
 586         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 587         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 588         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 589         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 590         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 591         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 592         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 593         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 594         bp->max_l2_ctx =
 595                 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
 596         /* TODO: For now, do not support VMDq/RFS on VFs. */
 597         if (BNXT_PF(bp)) {
 598                 if (bp->pf.max_vfs)
 599                         bp->max_vnics = 1;
 600                 else
 601                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 602         } else {
 603                 bp->max_vnics = 1;
 604         }
 605         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 606         if (BNXT_PF(bp)) {
 607                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 608                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 609                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 610                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 611                         HWRM_UNLOCK();
 612                         bnxt_hwrm_ptp_qcfg(bp);
 613                 }
 614         }
 615
 616         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 617                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 618
 619         HWRM_UNLOCK();
 620
 621         return rc;
 622 }
 623
 624 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 625 {
 626         int rc;
 627
 628         rc = __bnxt_hwrm_func_qcaps(bp);
 629         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 630                 rc = bnxt_alloc_ctx_mem(bp);
 631                 if (rc)
 632                         return rc;
 633
 634                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 635                 if (!rc)
 636                         bp->flags |= BNXT_FLAG_NEW_RM;
 637         }
 638
 639         return rc;
 640 }
 641
 642 int bnxt_hwrm_func_reset(struct bnxt *bp)
 643 {
 644         int rc = 0;
 645         struct hwrm_func_reset_input req = {.req_type = 0 };
 646         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 647
 648         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 649
 650         req.enables = rte_cpu_to_le_32(0);
 651
 652         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 653
 654         HWRM_CHECK_RESULT();
 655         HWRM_UNLOCK();
 656
 657         return rc;
 658 }
 659
 660 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 661 {
 662         int rc;
 663         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 664         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 665
 666         if (bp->flags & BNXT_FLAG_REGISTERED)
 667                 return 0;
 668
 669         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 670         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 671                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 672         req.ver_maj = RTE_VER_YEAR;
 673         req.ver_min = RTE_VER_MONTH;
 674         req.ver_upd = RTE_VER_MINOR;
 675
 676         if (BNXT_PF(bp)) {
 677                 req.enables |= rte_cpu_to_le_32(
 678                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 679                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 680                        RTE_MIN(sizeof(req.vf_req_fwd),
 681                                sizeof(bp->pf.vf_req_fwd)));
 682
 683                 /*
 684                  * PF can sniff HWRM API issued by VF. This can be set up by
 685                  * linux driver and inherited by the DPDK PF driver. Clear
 686                  * this HWRM sniffer list in FW because DPDK PF driver does
 687                  * not support this.
 688                  */
 689                 req.flags =
 690                 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
 691         }
 692
 693         req.async_event_fwd[0] |=
 694                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 695                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 696                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
 697         req.async_event_fwd[1] |=
 698                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 699                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 700
 701         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 702
 703         HWRM_CHECK_RESULT();
 704         HWRM_UNLOCK();
 705
 706         bp->flags |= BNXT_FLAG_REGISTERED;
 707
 708         return rc;
 709 }
 710
 711 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 712 {
 713         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 714                 return 0;
 715
 716         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 717 }
 718
 719 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 720 {
 721         int rc;
 722         uint32_t flags = 0;
 723         uint32_t enables;
 724         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 725         struct hwrm_func_vf_cfg_input req = {0};
 726
 727         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 728
 729         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 730                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 731                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 732                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 733                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 734
 735         if (BNXT_HAS_RING_GRPS(bp)) {
 736                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 737                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 738         }
 739
 740         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 741         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 742                                             AGG_RING_MULTIPLIER);
 743         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 744         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 745                                               bp->tx_nr_rings);
 746         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 747         if (bp->vf_resv_strategy ==
 748             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 749                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 750                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 751                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 752                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 753                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 754                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 755         }
 756
 757         if (test)
 758                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 759                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 760                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 761                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 762                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 763                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 764
 765         if (test && BNXT_HAS_RING_GRPS(bp))
 766                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 767
 768         req.flags = rte_cpu_to_le_32(flags);
 769         req.enables |= rte_cpu_to_le_32(enables);
 770
 771         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 772
 773         if (test)
 774                 HWRM_CHECK_RESULT_SILENT();
 775         else
 776                 HWRM_CHECK_RESULT();
 777
 778         HWRM_UNLOCK();
 779         return rc;
 780 }
 781
 782 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 783 {
 784         int rc;
 785         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 786         struct hwrm_func_resource_qcaps_input req = {0};
 787
 788         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 789         req.fid = rte_cpu_to_le_16(0xffff);
 790
 791         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 792
 793         HWRM_CHECK_RESULT();
 794
 795         if (BNXT_VF(bp)) {
 796                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 797                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 798                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 799                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 800                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 801                 /* func_resource_qcaps does not return max_rx_em_flows.
 802                  * So use the value provided by func_qcaps.
 803                  */
 804                 bp->max_l2_ctx =
 805                         rte_le_to_cpu_16(resp->max_l2_ctxs) +
 806                         bp->max_rx_em_flows;
 807                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 808                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 809         }
 810         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 811         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 812         if (bp->vf_resv_strategy >
 813             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 814                 bp->vf_resv_strategy =
 815                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 816
 817         HWRM_UNLOCK();
 818         return rc;
 819 }
 820
 821 int bnxt_hwrm_ver_get(struct bnxt *bp)
 822 {
 823         int rc = 0;
 824         struct hwrm_ver_get_input req = {.req_type = 0 };
 825         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 826         uint32_t fw_version;
 827         uint16_t max_resp_len;
 828         char type[RTE_MEMZONE_NAMESIZE];
 829         uint32_t dev_caps_cfg;
 830
 831         bp->max_req_len = HWRM_MAX_REQ_LEN;
 832         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 833
 834         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 835         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 836         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 837
 838         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 839
 840         HWRM_CHECK_RESULT();
 841
 842         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 843                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 844                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 845                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 846         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 847                      (resp->hwrm_fw_min_8b << 16) |
 848                      (resp->hwrm_fw_bld_8b << 8) |
 849                      resp->hwrm_fw_rsvd_8b;
 850         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 851                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 852
 853         fw_version = resp->hwrm_intf_maj_8b << 16;
 854         fw_version |= resp->hwrm_intf_min_8b << 8;
 855         fw_version |= resp->hwrm_intf_upd_8b;
 856         bp->hwrm_spec_code = fw_version;
 857
 858         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 859                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 860                 rc = -EINVAL;
 861                 goto error;
 862         }
 863
 864         if (bp->max_req_len > resp->max_req_win_len) {
 865                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 866                 rc = -EINVAL;
 867         }
 868         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 869         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 870         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 871                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 872
 873         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 874         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 875
 876         if (bp->max_resp_len != max_resp_len) {
 877                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 878                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 879                         bp->pdev->addr.devid, bp->pdev->addr.function);
 880
 881                 rte_free(bp->hwrm_cmd_resp_addr);
 882
 883                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 884                 if (bp->hwrm_cmd_resp_addr == NULL) {
 885                         rc = -ENOMEM;
 886                         goto error;
 887                 }
 888                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 889                 bp->hwrm_cmd_resp_dma_addr =
 890                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 891                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
 892                         PMD_DRV_LOG(ERR,
 893                         "Unable to map response buffer to physical memory.\n");
 894                         rc = -ENOMEM;
 895                         goto error;
 896                 }
 897                 bp->max_resp_len = max_resp_len;
 898         }
 899
 900         if ((dev_caps_cfg &
 901                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 902             (dev_caps_cfg &
 903              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 904                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 905                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 906         }
 907
 908         if (((dev_caps_cfg &
 909               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 910              (dev_caps_cfg &
 911               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
 912             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
 913                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
 914                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 915                         bp->pdev->addr.devid, bp->pdev->addr.function);
 916
 917                 rte_free(bp->hwrm_short_cmd_req_addr);
 918
 919                 bp->hwrm_short_cmd_req_addr =
 920                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
 921                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 922                         rc = -ENOMEM;
 923                         goto error;
 924                 }
 925                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 926                 bp->hwrm_short_cmd_req_dma_addr =
 927                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 928                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
 929                         rte_free(bp->hwrm_short_cmd_req_addr);
 930                         PMD_DRV_LOG(ERR,
 931                                 "Unable to map buffer to physical memory.\n");
 932                         rc = -ENOMEM;
 933                         goto error;
 934                 }
 935         }
 936         if (dev_caps_cfg &
 937             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
 938                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
 939                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
 940         }
 941         if (dev_caps_cfg &
 942             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
 943                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
 944
 945 error:
 946         HWRM_UNLOCK();
 947         return rc;
 948 }
 949
 950 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 951 {
 952         int rc;
 953         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 954         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 955
 956         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 957                 return 0;
 958
 959         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
 960         req.flags = flags;
 961
 962         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 963
 964         HWRM_CHECK_RESULT();
 965         HWRM_UNLOCK();
 966
 967         bp->flags &= ~BNXT_FLAG_REGISTERED;
 968
 969         return rc;
 970 }
 971
 972 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 973 {
 974         int rc = 0;
 975         struct hwrm_port_phy_cfg_input req = {0};
 976         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 977         uint32_t enables = 0;
 978
 979         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
 980
 981         if (conf->link_up) {
 982                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
 983                 if (bp->link_info.auto_mode && conf->link_speed) {
 984                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
 985                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
 986                 }
 987
 988                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 989                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 990                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 991                 /*
 992                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 993                  * any auto mode, even "none".
 994                  */
 995                 if (!conf->link_speed) {
 996                         /* No speeds specified. Enable AutoNeg - all speeds */
 997                         req.auto_mode =
 998                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
 999                 }
1000                 /* AutoNeg - Advertise speeds specified. */
1001                 if (conf->auto_link_speed_mask &&
1002                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1003                         req.auto_mode =
1004                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1005                         req.auto_link_speed_mask =
1006                                 conf->auto_link_speed_mask;
1007                         enables |=
1008                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1009                 }
1010
1011                 req.auto_duplex = conf->duplex;
1012                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1013                 req.auto_pause = conf->auto_pause;
1014                 req.force_pause = conf->force_pause;
1015                 /* Set force_pause if there is no auto or if there is a force */
1016                 if (req.auto_pause && !req.force_pause)
1017                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1018                 else
1019                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1020
1021                 req.enables = rte_cpu_to_le_32(enables);
1022         } else {
1023                 req.flags =
1024                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1025                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1026         }
1027
1028         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1029
1030         HWRM_CHECK_RESULT();
1031         HWRM_UNLOCK();
1032
1033         return rc;
1034 }
1035
1036 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1037                                    struct bnxt_link_info *link_info)
1038 {
1039         int rc = 0;
1040         struct hwrm_port_phy_qcfg_input req = {0};
1041         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1042
1043         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1044
1045         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1046
1047         HWRM_CHECK_RESULT();
1048
1049         link_info->phy_link_status = resp->link;
1050         link_info->link_up =
1051                 (link_info->phy_link_status ==
1052                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1053         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1054         link_info->duplex = resp->duplex_cfg;
1055         link_info->pause = resp->pause;
1056         link_info->auto_pause = resp->auto_pause;
1057         link_info->force_pause = resp->force_pause;
1058         link_info->auto_mode = resp->auto_mode;
1059         link_info->phy_type = resp->phy_type;
1060         link_info->media_type = resp->media_type;
1061
1062         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1063         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1064         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1065         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1066         link_info->phy_ver[0] = resp->phy_maj;
1067         link_info->phy_ver[1] = resp->phy_min;
1068         link_info->phy_ver[2] = resp->phy_bld;
1069
1070         HWRM_UNLOCK();
1071
1072         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1073         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1074         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1075         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1076         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1077                     link_info->auto_link_speed_mask);
1078         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1079                     link_info->force_link_speed);
1080
1081         return rc;
1082 }
1083
1084 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1085 {
1086         int rc = 0;
1087         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1088         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1089         int i;
1090
1091         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1092
1093         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1094         /* HWRM Version >= 1.9.1 */
1095         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1096                 req.drv_qmap_cap =
1097                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1098         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1099
1100         HWRM_CHECK_RESULT();
1101
1102 #define GET_QUEUE_INFO(x) \
1103         bp->cos_queue[x].id = resp->queue_id##x; \
1104         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1105
1106         GET_QUEUE_INFO(0);
1107         GET_QUEUE_INFO(1);
1108         GET_QUEUE_INFO(2);
1109         GET_QUEUE_INFO(3);
1110         GET_QUEUE_INFO(4);
1111         GET_QUEUE_INFO(5);
1112         GET_QUEUE_INFO(6);
1113         GET_QUEUE_INFO(7);
1114
1115         HWRM_UNLOCK();
1116
1117         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1118                 bp->tx_cosq_id = bp->cos_queue[0].id;
1119         } else {
1120                 /* iterate and find the COSq profile to use for Tx */
1121                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1122                         if (bp->cos_queue[i].profile ==
1123                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1124                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1125                                 break;
1126                         }
1127                 }
1128         }
1129
1130         bp->max_tc = resp->max_configurable_queues;
1131         bp->max_lltc = resp->max_configurable_lossless_queues;
1132         if (bp->max_tc > BNXT_MAX_QUEUE)
1133                 bp->max_tc = BNXT_MAX_QUEUE;
1134         bp->max_q = bp->max_tc;
1135
1136         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1137
1138         return rc;
1139 }
1140
1141 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1142                          struct bnxt_ring *ring,
1143                          uint32_t ring_type, uint32_t map_index,
1144                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1145 {
1146         int rc = 0;
1147         uint32_t enables = 0;
1148         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1149         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1150         struct rte_mempool *mb_pool;
1151         uint16_t rx_buf_size;
1152
1153         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1154
1155         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1156         req.fbo = rte_cpu_to_le_32(0);
1157         /* Association of ring index with doorbell index */
1158         req.logical_id = rte_cpu_to_le_16(map_index);
1159         req.length = rte_cpu_to_le_32(ring->ring_size);
1160
1161         switch (ring_type) {
1162         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1163                 req.ring_type = ring_type;
1164                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1165                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1166                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1167                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1168                         enables |=
1169                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1170                 break;
1171         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1172                 req.ring_type = ring_type;
1173                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1174                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1175                 if (BNXT_CHIP_THOR(bp)) {
1176                         mb_pool = bp->rx_queues[0]->mb_pool;
1177                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1178                                       RTE_PKTMBUF_HEADROOM;
1179                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1180                         enables |=
1181                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1182                 }
1183                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1184                         enables |=
1185                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1186                 break;
1187         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1188                 req.ring_type = ring_type;
1189                 if (BNXT_HAS_NQ(bp)) {
1190                         /* Association of cp ring with nq */
1191                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1192                         enables |=
1193                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1194                 }
1195                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1196                 break;
1197         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1198                 req.ring_type = ring_type;
1199                 req.page_size = BNXT_PAGE_SHFT;
1200                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1201                 break;
1202         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1203                 req.ring_type = ring_type;
1204                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1205
1206                 mb_pool = bp->rx_queues[0]->mb_pool;
1207                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1208                               RTE_PKTMBUF_HEADROOM;
1209                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1210
1211                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1212                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1213                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1214                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1215                 break;
1216         default:
1217                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1218                         ring_type);
1219                 HWRM_UNLOCK();
1220                 return -1;
1221         }
1222         req.enables = rte_cpu_to_le_32(enables);
1223
1224         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1225
1226         if (rc || resp->error_code) {
1227                 if (rc == 0 && resp->error_code)
1228                         rc = rte_le_to_cpu_16(resp->error_code);
1229                 switch (ring_type) {
1230                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1231                         PMD_DRV_LOG(ERR,
1232                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1233                         HWRM_UNLOCK();
1234                         return rc;
1235                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1236                         PMD_DRV_LOG(ERR,
1237                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1238                         HWRM_UNLOCK();
1239                         return rc;
1240                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1241                         PMD_DRV_LOG(ERR,
1242                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1243                                     rc);
1244                         HWRM_UNLOCK();
1245                         return rc;
1246                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1247                         PMD_DRV_LOG(ERR,
1248                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1249                         HWRM_UNLOCK();
1250                         return rc;
1251                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1252                         PMD_DRV_LOG(ERR,
1253                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1254                         HWRM_UNLOCK();
1255                         return rc;
1256                 default:
1257                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1258                         HWRM_UNLOCK();
1259                         return rc;
1260                 }
1261         }
1262
1263         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1264         HWRM_UNLOCK();
1265         return rc;
1266 }
1267
1268 int bnxt_hwrm_ring_free(struct bnxt *bp,
1269                         struct bnxt_ring *ring, uint32_t ring_type)
1270 {
1271         int rc;
1272         struct hwrm_ring_free_input req = {.req_type = 0 };
1273         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1274
1275         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1276
1277         req.ring_type = ring_type;
1278         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1279
1280         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1281
1282         if (rc || resp->error_code) {
1283                 if (rc == 0 && resp->error_code)
1284                         rc = rte_le_to_cpu_16(resp->error_code);
1285                 HWRM_UNLOCK();
1286
1287                 switch (ring_type) {
1288                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1289                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1290                                 rc);
1291                         return rc;
1292                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1293                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1294                                 rc);
1295                         return rc;
1296                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1297                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1298                                 rc);
1299                         return rc;
1300                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1301                         PMD_DRV_LOG(ERR,
1302                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1303                         return rc;
1304                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1305                         PMD_DRV_LOG(ERR,
1306                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1307                         return rc;
1308                 default:
1309                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1310                         return rc;
1311                 }
1312         }
1313         HWRM_UNLOCK();
1314         return 0;
1315 }
1316
1317 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1318 {
1319         int rc = 0;
1320         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1321         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1322
1323         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1324
1325         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1326         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1327         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1328         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1329
1330         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1331
1332         HWRM_CHECK_RESULT();
1333
1334         bp->grp_info[idx].fw_grp_id =
1335             rte_le_to_cpu_16(resp->ring_group_id);
1336
1337         HWRM_UNLOCK();
1338
1339         return rc;
1340 }
1341
1342 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1343 {
1344         int rc;
1345         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1346         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1347
1348         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1349
1350         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1351
1352         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1353
1354         HWRM_CHECK_RESULT();
1355         HWRM_UNLOCK();
1356
1357         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1358         return rc;
1359 }
1360
1361 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1362 {
1363         int rc = 0;
1364         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1365         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1366
1367         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1368                 return rc;
1369
1370         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1371
1372         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1373
1374         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1375
1376         HWRM_CHECK_RESULT();
1377         HWRM_UNLOCK();
1378
1379         return rc;
1380 }
1381
1382 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1383                                 unsigned int idx __rte_unused)
1384 {
1385         int rc;
1386         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1387         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1388
1389         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1390
1391         req.update_period_ms = rte_cpu_to_le_32(0);
1392
1393         req.stats_dma_addr =
1394             rte_cpu_to_le_64(cpr->hw_stats_map);
1395
1396         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1397
1398         HWRM_CHECK_RESULT();
1399
1400         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1401
1402         HWRM_UNLOCK();
1403
1404         return rc;
1405 }
1406
1407 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1408                                 unsigned int idx __rte_unused)
1409 {
1410         int rc;
1411         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1412         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1413
1414         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1415
1416         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1417
1418         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1419
1420         HWRM_CHECK_RESULT();
1421         HWRM_UNLOCK();
1422
1423         return rc;
1424 }
1425
1426 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1427 {
1428         int rc = 0, i, j;
1429         struct hwrm_vnic_alloc_input req = { 0 };
1430         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1431
1432         if (!BNXT_HAS_RING_GRPS(bp))
1433                 goto skip_ring_grps;
1434
1435         /* map ring groups to this vnic */
1436         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1437                 vnic->start_grp_id, vnic->end_grp_id);
1438         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1439                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1440
1441         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1442         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1443         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1444         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1445
1446 skip_ring_grps:
1447         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1448                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1449         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1450
1451         if (vnic->func_default)
1452                 req.flags =
1453                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1454         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1455
1456         HWRM_CHECK_RESULT();
1457
1458         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1459         HWRM_UNLOCK();
1460         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1461         return rc;
1462 }
1463
1464 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1465                                         struct bnxt_vnic_info *vnic,
1466                                         struct bnxt_plcmodes_cfg *pmode)
1467 {
1468         int rc = 0;
1469         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1470         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1471
1472         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1473
1474         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1475
1476         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1477
1478         HWRM_CHECK_RESULT();
1479
1480         pmode->flags = rte_le_to_cpu_32(resp->flags);
1481         /* dflt_vnic bit doesn't exist in the _cfg command */
1482         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1483         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1484         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1485         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1486
1487         HWRM_UNLOCK();
1488
1489         return rc;
1490 }
1491
1492 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1493                                        struct bnxt_vnic_info *vnic,
1494                                        struct bnxt_plcmodes_cfg *pmode)
1495 {
1496         int rc = 0;
1497         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1498         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1499
1500         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1501                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1502                 return rc;
1503         }
1504
1505         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1506
1507         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1508         req.flags = rte_cpu_to_le_32(pmode->flags);
1509         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1510         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1511         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1512         req.enables = rte_cpu_to_le_32(
1513             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1514             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1515             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1516         );
1517
1518         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1519
1520         HWRM_CHECK_RESULT();
1521         HWRM_UNLOCK();
1522
1523         return rc;
1524 }
1525
1526 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1527 {
1528         int rc = 0;
1529         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1530         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1531         struct bnxt_plcmodes_cfg pmodes = { 0 };
1532         uint32_t ctx_enable_flag = 0;
1533         uint32_t enables = 0;
1534
1535         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1536                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1537                 return rc;
1538         }
1539
1540         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1541         if (rc)
1542                 return rc;
1543
1544         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1545
1546         if (BNXT_CHIP_THOR(bp)) {
1547                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1548                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1549                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1550
1551                 req.default_rx_ring_id =
1552                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1553                 req.default_cmpl_ring_id =
1554                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1555                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1556                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1557                 goto config_mru;
1558         }
1559
1560         /* Only RSS support for now TBD: COS & LB */
1561         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1562         if (vnic->lb_rule != 0xffff)
1563                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1564         if (vnic->cos_rule != 0xffff)
1565                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1566         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1567                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1568                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1569         }
1570         enables |= ctx_enable_flag;
1571         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1572         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1573         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1574         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1575
1576 config_mru:
1577         req.enables = rte_cpu_to_le_32(enables);
1578         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1579         req.mru = rte_cpu_to_le_16(vnic->mru);
1580         /* Configure default VNIC only once. */
1581         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1582                 req.flags |=
1583                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1584                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1585         }
1586         if (vnic->vlan_strip)
1587                 req.flags |=
1588                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1589         if (vnic->bd_stall)
1590                 req.flags |=
1591                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1592         if (vnic->roce_dual)
1593                 req.flags |= rte_cpu_to_le_32(
1594                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1595         if (vnic->roce_only)
1596                 req.flags |= rte_cpu_to_le_32(
1597                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1598         if (vnic->rss_dflt_cr)
1599                 req.flags |= rte_cpu_to_le_32(
1600                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1601
1602         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1603
1604         HWRM_CHECK_RESULT();
1605         HWRM_UNLOCK();
1606
1607         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1608
1609         return rc;
1610 }
1611
1612 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1613                 int16_t fw_vf_id)
1614 {
1615         int rc = 0;
1616         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1617         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1618
1619         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1620                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1621                 return rc;
1622         }
1623         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1624
1625         req.enables =
1626                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1627         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1628         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1629
1630         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1631
1632         HWRM_CHECK_RESULT();
1633
1634         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1635         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1636         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1637         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1638         vnic->mru = rte_le_to_cpu_16(resp->mru);
1639         vnic->func_default = rte_le_to_cpu_32(
1640                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1641         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1642                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1643         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1644                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1645         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1646                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1647         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1648                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1649         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1650                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1651
1652         HWRM_UNLOCK();
1653
1654         return rc;
1655 }
1656
1657 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1658                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1659 {
1660         int rc = 0;
1661         uint16_t ctx_id;
1662         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1663         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1664                                                 bp->hwrm_cmd_resp_addr;
1665
1666         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1667
1668         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1669         HWRM_CHECK_RESULT();
1670
1671         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1672         if (!BNXT_HAS_RING_GRPS(bp))
1673                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1674         else if (ctx_idx == 0)
1675                 vnic->rss_rule = ctx_id;
1676
1677         HWRM_UNLOCK();
1678
1679         return rc;
1680 }
1681
1682 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1683                             struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1684 {
1685         int rc = 0;
1686         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1687         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1688                                                 bp->hwrm_cmd_resp_addr;
1689
1690         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1691                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1692                 return rc;
1693         }
1694         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1695
1696         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1697
1698         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1699
1700         HWRM_CHECK_RESULT();
1701         HWRM_UNLOCK();
1702
1703         return rc;
1704 }
1705
1706 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1707 {
1708         int rc = 0;
1709         struct hwrm_vnic_free_input req = {.req_type = 0 };
1710         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1711
1712         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1713                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1714                 return rc;
1715         }
1716
1717         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1718
1719         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1720
1721         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1722
1723         HWRM_CHECK_RESULT();
1724         HWRM_UNLOCK();
1725
1726         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1727         /* Configure default VNIC again if necessary. */
1728         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1729                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1730
1731         return rc;
1732 }
1733
1734 static int
1735 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1736 {
1737         int i;
1738         int rc = 0;
1739         int nr_ctxs = bp->max_ring_grps;
1740         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1741         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1742
1743         if (!(vnic->rss_table && vnic->hash_type))
1744                 return 0;
1745
1746         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1747
1748         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1749         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1750         req.hash_mode_flags = vnic->hash_mode;
1751
1752         req.hash_key_tbl_addr =
1753             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1754
1755         for (i = 0; i < nr_ctxs; i++) {
1756                 req.ring_grp_tbl_addr =
1757                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1758                                          i * HW_HASH_INDEX_SIZE);
1759                 req.ring_table_pair_index = i;
1760                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1761
1762                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1763                                             BNXT_USE_CHIMP_MB);
1764
1765                 HWRM_CHECK_RESULT();
1766         }
1767
1768         HWRM_UNLOCK();
1769
1770         return rc;
1771 }
1772
1773 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1774                            struct bnxt_vnic_info *vnic)
1775 {
1776         int rc = 0;
1777         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1778         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1779
1780         if (BNXT_CHIP_THOR(bp))
1781                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1782
1783         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1784
1785         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1786         req.hash_mode_flags = vnic->hash_mode;
1787
1788         req.ring_grp_tbl_addr =
1789             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1790         req.hash_key_tbl_addr =
1791             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1792         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1793         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1794
1795         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1796
1797         HWRM_CHECK_RESULT();
1798         HWRM_UNLOCK();
1799
1800         return rc;
1801 }
1802
1803 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1804                         struct bnxt_vnic_info *vnic)
1805 {
1806         int rc = 0;
1807         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1808         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1809         uint16_t size;
1810
1811         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1812                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1813                 return rc;
1814         }
1815
1816         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1817
1818         req.flags = rte_cpu_to_le_32(
1819                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1820
1821         req.enables = rte_cpu_to_le_32(
1822                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1823
1824         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1825         size -= RTE_PKTMBUF_HEADROOM;
1826
1827         req.jumbo_thresh = rte_cpu_to_le_16(size);
1828         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1829
1830         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1831
1832         HWRM_CHECK_RESULT();
1833         HWRM_UNLOCK();
1834
1835         return rc;
1836 }
1837
1838 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1839                         struct bnxt_vnic_info *vnic, bool enable)
1840 {
1841         int rc = 0;
1842         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1843         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1844
1845         if (BNXT_CHIP_THOR(bp))
1846                 return 0;
1847
1848         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1849
1850         if (enable) {
1851                 req.enables = rte_cpu_to_le_32(
1852                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1853                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1854                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1855                 req.flags = rte_cpu_to_le_32(
1856                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1857                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1858                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1859                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1860                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1861                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1862                 req.max_agg_segs = rte_cpu_to_le_16(5);
1863                 req.max_aggs =
1864                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1865                 req.min_agg_len = rte_cpu_to_le_32(512);
1866         }
1867         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1868
1869         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1870
1871         HWRM_CHECK_RESULT();
1872         HWRM_UNLOCK();
1873
1874         return rc;
1875 }
1876
1877 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1878 {
1879         struct hwrm_func_cfg_input req = {0};
1880         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1881         int rc;
1882
1883         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1884         req.enables = rte_cpu_to_le_32(
1885                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1886         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1887         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1888
1889         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1890
1891         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1892         HWRM_CHECK_RESULT();
1893         HWRM_UNLOCK();
1894
1895         bp->pf.vf_info[vf].random_mac = false;
1896
1897         return rc;
1898 }
1899
1900 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1901                                   uint64_t *dropped)
1902 {
1903         int rc = 0;
1904         struct hwrm_func_qstats_input req = {.req_type = 0};
1905         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1906
1907         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1908
1909         req.fid = rte_cpu_to_le_16(fid);
1910
1911         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1912
1913         HWRM_CHECK_RESULT();
1914
1915         if (dropped)
1916                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1917
1918         HWRM_UNLOCK();
1919
1920         return rc;
1921 }
1922
1923 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1924                           struct rte_eth_stats *stats)
1925 {
1926         int rc = 0;
1927         struct hwrm_func_qstats_input req = {.req_type = 0};
1928         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1929
1930         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1931
1932         req.fid = rte_cpu_to_le_16(fid);
1933
1934         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1935
1936         HWRM_CHECK_RESULT();
1937
1938         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1939         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1940         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1941         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1942         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1943         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1944
1945         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1946         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1947         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1948         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1949         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1950         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1951
1952         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1953         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1954         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1955
1956         HWRM_UNLOCK();
1957
1958         return rc;
1959 }
1960
1961 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1962 {
1963         int rc = 0;
1964         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1965         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1966
1967         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1968
1969         req.fid = rte_cpu_to_le_16(fid);
1970
1971         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1972
1973         HWRM_CHECK_RESULT();
1974         HWRM_UNLOCK();
1975
1976         return rc;
1977 }
1978
1979 /*
1980  * HWRM utility functions
1981  */
1982
1983 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1984 {
1985         unsigned int i;
1986         int rc = 0;
1987
1988         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1989                 struct bnxt_tx_queue *txq;
1990                 struct bnxt_rx_queue *rxq;
1991                 struct bnxt_cp_ring_info *cpr;
1992
1993                 if (i >= bp->rx_cp_nr_rings) {
1994                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1995                         cpr = txq->cp_ring;
1996                 } else {
1997                         rxq = bp->rx_queues[i];
1998                         cpr = rxq->cp_ring;
1999                 }
2000
2001                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2002                 if (rc)
2003                         return rc;
2004         }
2005         return 0;
2006 }
2007
2008 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2009 {
2010         int rc;
2011         unsigned int i;
2012         struct bnxt_cp_ring_info *cpr;
2013
2014         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2015
2016                 if (i >= bp->rx_cp_nr_rings) {
2017                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2018                 } else {
2019                         cpr = bp->rx_queues[i]->cp_ring;
2020                         if (BNXT_HAS_RING_GRPS(bp))
2021                                 bp->grp_info[i].fw_stats_ctx = -1;
2022                 }
2023                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2024                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2025                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2026                         if (rc)
2027                                 return rc;
2028                 }
2029         }
2030         return 0;
2031 }
2032
2033 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2034 {
2035         unsigned int i;
2036         int rc = 0;
2037
2038         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2039                 struct bnxt_tx_queue *txq;
2040                 struct bnxt_rx_queue *rxq;
2041                 struct bnxt_cp_ring_info *cpr;
2042
2043                 if (i >= bp->rx_cp_nr_rings) {
2044                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2045                         cpr = txq->cp_ring;
2046                 } else {
2047                         rxq = bp->rx_queues[i];
2048                         cpr = rxq->cp_ring;
2049                 }
2050
2051                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2052
2053                 if (rc)
2054                         return rc;
2055         }
2056         return rc;
2057 }
2058
2059 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2060 {
2061         uint16_t idx;
2062         uint32_t rc = 0;
2063
2064         if (!BNXT_HAS_RING_GRPS(bp))
2065                 return 0;
2066
2067         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2068
2069                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2070                         continue;
2071
2072                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2073
2074                 if (rc)
2075                         return rc;
2076         }
2077         return rc;
2078 }
2079
2080 static void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2081 {
2082         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2083
2084         bnxt_hwrm_ring_free(bp, cp_ring,
2085                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2086         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2087         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2088                                      sizeof(*cpr->cp_desc_ring));
2089         cpr->cp_raw_cons = 0;
2090 }
2091
2092 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2093 {
2094         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2095
2096         bnxt_hwrm_ring_free(bp, cp_ring,
2097                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2098         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2099         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2100                         sizeof(*cpr->cp_desc_ring));
2101         cpr->cp_raw_cons = 0;
2102         cpr->valid = 0;
2103 }
2104
2105 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2106 {
2107         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2108         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2109         struct bnxt_ring *ring = rxr->rx_ring_struct;
2110         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2111
2112         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2113                 bnxt_hwrm_ring_free(bp, ring,
2114                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2115                 ring->fw_ring_id = INVALID_HW_RING_ID;
2116                 if (BNXT_HAS_RING_GRPS(bp))
2117                         bp->grp_info[queue_index].rx_fw_ring_id =
2118                                                         INVALID_HW_RING_ID;
2119                 memset(rxr->rx_desc_ring, 0,
2120                        rxr->rx_ring_struct->ring_size *
2121                        sizeof(*rxr->rx_desc_ring));
2122                 memset(rxr->rx_buf_ring, 0,
2123                        rxr->rx_ring_struct->ring_size *
2124                        sizeof(*rxr->rx_buf_ring));
2125                 rxr->rx_prod = 0;
2126         }
2127         ring = rxr->ag_ring_struct;
2128         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2129                 bnxt_hwrm_ring_free(bp, ring,
2130                                     BNXT_CHIP_THOR(bp) ?
2131                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2132                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2133                 ring->fw_ring_id = INVALID_HW_RING_ID;
2134                 memset(rxr->ag_buf_ring, 0,
2135                        rxr->ag_ring_struct->ring_size *
2136                        sizeof(*rxr->ag_buf_ring));
2137                 rxr->ag_prod = 0;
2138                 if (BNXT_HAS_RING_GRPS(bp))
2139                         bp->grp_info[queue_index].ag_fw_ring_id =
2140                                                         INVALID_HW_RING_ID;
2141         }
2142         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2143                 bnxt_free_cp_ring(bp, cpr);
2144                 if (rxq->nq_ring)
2145                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2146         }
2147
2148         if (BNXT_HAS_RING_GRPS(bp))
2149                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2150 }
2151
2152 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2153 {
2154         unsigned int i;
2155
2156         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2157                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2158                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2159                 struct bnxt_ring *ring = txr->tx_ring_struct;
2160                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2161
2162                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2163                         bnxt_hwrm_ring_free(bp, ring,
2164                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2165                         ring->fw_ring_id = INVALID_HW_RING_ID;
2166                         memset(txr->tx_desc_ring, 0,
2167                                         txr->tx_ring_struct->ring_size *
2168                                         sizeof(*txr->tx_desc_ring));
2169                         memset(txr->tx_buf_ring, 0,
2170                                         txr->tx_ring_struct->ring_size *
2171                                         sizeof(*txr->tx_buf_ring));
2172                         txr->tx_prod = 0;
2173                         txr->tx_cons = 0;
2174                 }
2175                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2176                         bnxt_free_cp_ring(bp, cpr);
2177                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2178                         if (txq->nq_ring)
2179                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2180                 }
2181         }
2182
2183         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2184                 bnxt_free_hwrm_rx_ring(bp, i);
2185
2186         return 0;
2187 }
2188
2189 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2190 {
2191         uint16_t i;
2192         uint32_t rc = 0;
2193
2194         if (!BNXT_HAS_RING_GRPS(bp))
2195                 return 0;
2196
2197         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2198                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2199                 if (rc)
2200                         return rc;
2201         }
2202         return rc;
2203 }
2204
2205 void bnxt_free_hwrm_resources(struct bnxt *bp)
2206 {
2207         /* Release memzone */
2208         rte_free(bp->hwrm_cmd_resp_addr);
2209         rte_free(bp->hwrm_short_cmd_req_addr);
2210         bp->hwrm_cmd_resp_addr = NULL;
2211         bp->hwrm_short_cmd_req_addr = NULL;
2212         bp->hwrm_cmd_resp_dma_addr = 0;
2213         bp->hwrm_short_cmd_req_dma_addr = 0;
2214 }
2215
2216 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2217 {
2218         struct rte_pci_device *pdev = bp->pdev;
2219         char type[RTE_MEMZONE_NAMESIZE];
2220
2221         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2222                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2223         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2224         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2225         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2226         if (bp->hwrm_cmd_resp_addr == NULL)
2227                 return -ENOMEM;
2228         bp->hwrm_cmd_resp_dma_addr =
2229                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2230         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2231                 PMD_DRV_LOG(ERR,
2232                         "unable to map response address to physical memory\n");
2233                 return -ENOMEM;
2234         }
2235         rte_spinlock_init(&bp->hwrm_lock);
2236
2237         return 0;
2238 }
2239
2240 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2241 {
2242         struct bnxt_filter_info *filter;
2243         int rc = 0;
2244
2245         STAILQ_FOREACH(filter, &vnic->filter, next) {
2246                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2247                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2248                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2249                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2250                 else
2251                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2252                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2253                 //if (rc)
2254                         //break;
2255         }
2256         return rc;
2257 }
2258
2259 static int
2260 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2261 {
2262         struct bnxt_filter_info *filter;
2263         struct rte_flow *flow;
2264         int rc = 0;
2265
2266         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2267                 filter = flow->filter;
2268                 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
2269                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2270                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2271                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2272                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2273                 else
2274                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2275
2276                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2277                 rte_free(flow);
2278                 //if (rc)
2279                         //break;
2280         }
2281         return rc;
2282 }
2283
2284 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2285 {
2286         struct bnxt_filter_info *filter;
2287         int rc = 0;
2288
2289         STAILQ_FOREACH(filter, &vnic->filter, next) {
2290                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2291                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2292                                                      filter);
2293                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2294                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2295                                                          filter);
2296                 else
2297                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2298                                                      filter);
2299                 if (rc)
2300                         break;
2301         }
2302         return rc;
2303 }
2304
2305 void bnxt_free_tunnel_ports(struct bnxt *bp)
2306 {
2307         if (bp->vxlan_port_cnt)
2308                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2309                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2310         bp->vxlan_port = 0;
2311         if (bp->geneve_port_cnt)
2312                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2313                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2314         bp->geneve_port = 0;
2315 }
2316
2317 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2318 {
2319         int i, j;
2320
2321         if (bp->vnic_info == NULL)
2322                 return;
2323
2324         /*
2325          * Cleanup VNICs in reverse order, to make sure the L2 filter
2326          * from vnic0 is last to be cleaned up.
2327          */
2328         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2329                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2330
2331                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2332                         PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2333                         return;
2334                 }
2335
2336                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2337
2338                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2339
2340                 if (BNXT_CHIP_THOR(bp)) {
2341                         for (j = 0; j < vnic->num_lb_ctxts; j++) {
2342                                 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2343                                                         vnic->fw_grp_ids[j]);
2344                                 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2345                         }
2346                         vnic->num_lb_ctxts = 0;
2347                 } else {
2348                         bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2349                         vnic->rss_rule = INVALID_HW_RING_ID;
2350                 }
2351
2352                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2353
2354                 bnxt_hwrm_vnic_free(bp, vnic);
2355
2356                 rte_free(vnic->fw_grp_ids);
2357         }
2358         /* Ring resources */
2359         bnxt_free_all_hwrm_rings(bp);
2360         bnxt_free_all_hwrm_ring_grps(bp);
2361         bnxt_free_all_hwrm_stat_ctxs(bp);
2362         bnxt_free_tunnel_ports(bp);
2363 }
2364
2365 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2366 {
2367         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2368
2369         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2370                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2371
2372         switch (conf_link_speed) {
2373         case ETH_LINK_SPEED_10M_HD:
2374         case ETH_LINK_SPEED_100M_HD:
2375                 /* FALLTHROUGH */
2376                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2377         }
2378         return hw_link_duplex;
2379 }
2380
2381 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2382 {
2383         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2384 }
2385
2386 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2387 {
2388         uint16_t eth_link_speed = 0;
2389
2390         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2391                 return ETH_LINK_SPEED_AUTONEG;
2392
2393         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2394         case ETH_LINK_SPEED_100M:
2395         case ETH_LINK_SPEED_100M_HD:
2396                 /* FALLTHROUGH */
2397                 eth_link_speed =
2398                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2399                 break;
2400         case ETH_LINK_SPEED_1G:
2401                 eth_link_speed =
2402                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2403                 break;
2404         case ETH_LINK_SPEED_2_5G:
2405                 eth_link_speed =
2406                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2407                 break;
2408         case ETH_LINK_SPEED_10G:
2409                 eth_link_speed =
2410                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2411                 break;
2412         case ETH_LINK_SPEED_20G:
2413                 eth_link_speed =
2414                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2415                 break;
2416         case ETH_LINK_SPEED_25G:
2417                 eth_link_speed =
2418                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2419                 break;
2420         case ETH_LINK_SPEED_40G:
2421                 eth_link_speed =
2422                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2423                 break;
2424         case ETH_LINK_SPEED_50G:
2425                 eth_link_speed =
2426                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2427                 break;
2428         case ETH_LINK_SPEED_100G:
2429                 eth_link_speed =
2430                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2431                 break;
2432         default:
2433                 PMD_DRV_LOG(ERR,
2434                         "Unsupported link speed %d; default to AUTO\n",
2435                         conf_link_speed);
2436                 break;
2437         }
2438         return eth_link_speed;
2439 }
2440
2441 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2442                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2443                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2444                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2445
2446 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2447 {
2448         uint32_t one_speed;
2449
2450         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2451                 return 0;
2452
2453         if (link_speed & ETH_LINK_SPEED_FIXED) {
2454                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2455
2456                 if (one_speed & (one_speed - 1)) {
2457                         PMD_DRV_LOG(ERR,
2458                                 "Invalid advertised speeds (%u) for port %u\n",
2459                                 link_speed, port_id);
2460                         return -EINVAL;
2461                 }
2462                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2463                         PMD_DRV_LOG(ERR,
2464                                 "Unsupported advertised speed (%u) for port %u\n",
2465                                 link_speed, port_id);
2466                         return -EINVAL;
2467                 }
2468         } else {
2469                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2470                         PMD_DRV_LOG(ERR,
2471                                 "Unsupported advertised speeds (%u) for port %u\n",
2472                                 link_speed, port_id);
2473                         return -EINVAL;
2474                 }
2475         }
2476         return 0;
2477 }
2478
2479 static uint16_t
2480 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2481 {
2482         uint16_t ret = 0;
2483
2484         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2485                 if (bp->link_info.support_speeds)
2486                         return bp->link_info.support_speeds;
2487                 link_speed = BNXT_SUPPORTED_SPEEDS;
2488         }
2489
2490         if (link_speed & ETH_LINK_SPEED_100M)
2491                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2492         if (link_speed & ETH_LINK_SPEED_100M_HD)
2493                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2494         if (link_speed & ETH_LINK_SPEED_1G)
2495                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2496         if (link_speed & ETH_LINK_SPEED_2_5G)
2497                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2498         if (link_speed & ETH_LINK_SPEED_10G)
2499                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2500         if (link_speed & ETH_LINK_SPEED_20G)
2501                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2502         if (link_speed & ETH_LINK_SPEED_25G)
2503                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2504         if (link_speed & ETH_LINK_SPEED_40G)
2505                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2506         if (link_speed & ETH_LINK_SPEED_50G)
2507                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2508         if (link_speed & ETH_LINK_SPEED_100G)
2509                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2510         return ret;
2511 }
2512
2513 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2514 {
2515         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2516
2517         switch (hw_link_speed) {
2518         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2519                 eth_link_speed = ETH_SPEED_NUM_100M;
2520                 break;
2521         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2522                 eth_link_speed = ETH_SPEED_NUM_1G;
2523                 break;
2524         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2525                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2526                 break;
2527         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2528                 eth_link_speed = ETH_SPEED_NUM_10G;
2529                 break;
2530         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2531                 eth_link_speed = ETH_SPEED_NUM_20G;
2532                 break;
2533         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2534                 eth_link_speed = ETH_SPEED_NUM_25G;
2535                 break;
2536         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2537                 eth_link_speed = ETH_SPEED_NUM_40G;
2538                 break;
2539         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2540                 eth_link_speed = ETH_SPEED_NUM_50G;
2541                 break;
2542         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2543                 eth_link_speed = ETH_SPEED_NUM_100G;
2544                 break;
2545         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2546         default:
2547                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2548                         hw_link_speed);
2549                 break;
2550         }
2551         return eth_link_speed;
2552 }
2553
2554 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2555 {
2556         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2557
2558         switch (hw_link_duplex) {
2559         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2560         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2561                 /* FALLTHROUGH */
2562                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2563                 break;
2564         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2565                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2566                 break;
2567         default:
2568                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2569                         hw_link_duplex);
2570                 break;
2571         }
2572         return eth_link_duplex;
2573 }
2574
2575 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2576 {
2577         int rc = 0;
2578         struct bnxt_link_info *link_info = &bp->link_info;
2579
2580         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2581         if (rc) {
2582                 PMD_DRV_LOG(ERR,
2583                         "Get link config failed with rc %d\n", rc);
2584                 goto exit;
2585         }
2586         if (link_info->link_speed)
2587                 link->link_speed =
2588                         bnxt_parse_hw_link_speed(link_info->link_speed);
2589         else
2590                 link->link_speed = ETH_SPEED_NUM_NONE;
2591         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2592         link->link_status = link_info->link_up;
2593         link->link_autoneg = link_info->auto_mode ==
2594                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2595                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2596 exit:
2597         return rc;
2598 }
2599
2600 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2601 {
2602         int rc = 0;
2603         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2604         struct bnxt_link_info link_req;
2605         uint16_t speed, autoneg;
2606
2607         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2608                 return 0;
2609
2610         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2611                         bp->eth_dev->data->port_id);
2612         if (rc)
2613                 goto error;
2614
2615         memset(&link_req, 0, sizeof(link_req));
2616         link_req.link_up = link_up;
2617         if (!link_up)
2618                 goto port_phy_cfg;
2619
2620         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2621         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2622         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2623         /* Autoneg can be done only when the FW allows */
2624         if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2625                                 bp->link_info.force_link_speed)) {
2626                 link_req.phy_flags |=
2627                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2628                 link_req.auto_link_speed_mask =
2629                         bnxt_parse_eth_link_speed_mask(bp,
2630                                                        dev_conf->link_speeds);
2631         } else {
2632                 if (bp->link_info.phy_type ==
2633                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2634                     bp->link_info.phy_type ==
2635                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2636                     bp->link_info.media_type ==
2637                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2638                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2639                         return -EINVAL;
2640                 }
2641
2642                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2643                 /* If user wants a particular speed try that first. */
2644                 if (speed)
2645                         link_req.link_speed = speed;
2646                 else if (bp->link_info.force_link_speed)
2647                         link_req.link_speed = bp->link_info.force_link_speed;
2648                 else
2649                         link_req.link_speed = bp->link_info.auto_link_speed;
2650         }
2651         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2652         link_req.auto_pause = bp->link_info.auto_pause;
2653         link_req.force_pause = bp->link_info.force_pause;
2654
2655 port_phy_cfg:
2656         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2657         if (rc) {
2658                 PMD_DRV_LOG(ERR,
2659                         "Set link config failed with rc %d\n", rc);
2660         }
2661
2662 error:
2663         return rc;
2664 }
2665
2666 /* JIRA 22088 */
2667 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2668 {
2669         struct hwrm_func_qcfg_input req = {0};
2670         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2671         uint16_t flags;
2672         int rc = 0;
2673
2674         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2675         req.fid = rte_cpu_to_le_16(0xffff);
2676
2677         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2678
2679         HWRM_CHECK_RESULT();
2680
2681         /* Hard Coded.. 0xfff VLAN ID mask */
2682         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2683         flags = rte_le_to_cpu_16(resp->flags);
2684         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2685                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2686
2687         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2688                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2689                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2690         }
2691
2692         if (mtu)
2693                 *mtu = resp->mtu;
2694
2695         switch (resp->port_partition_type) {
2696         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2697         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2698         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2699                 /* FALLTHROUGH */
2700                 bp->port_partition_type = resp->port_partition_type;
2701                 break;
2702         default:
2703                 bp->port_partition_type = 0;
2704                 break;
2705         }
2706
2707         HWRM_UNLOCK();
2708
2709         return rc;
2710 }
2711
2712 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2713                                    struct hwrm_func_qcaps_output *qcaps)
2714 {
2715         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2716         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2717                sizeof(qcaps->mac_address));
2718         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2719         qcaps->max_rx_rings = fcfg->num_rx_rings;
2720         qcaps->max_tx_rings = fcfg->num_tx_rings;
2721         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2722         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2723         qcaps->max_vfs = 0;
2724         qcaps->first_vf_id = 0;
2725         qcaps->max_vnics = fcfg->num_vnics;
2726         qcaps->max_decap_records = 0;
2727         qcaps->max_encap_records = 0;
2728         qcaps->max_tx_wm_flows = 0;
2729         qcaps->max_tx_em_flows = 0;
2730         qcaps->max_rx_wm_flows = 0;
2731         qcaps->max_rx_em_flows = 0;
2732         qcaps->max_flow_id = 0;
2733         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2734         qcaps->max_sp_tx_rings = 0;
2735         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2736 }
2737
2738 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2739 {
2740         struct hwrm_func_cfg_input req = {0};
2741         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2742         uint32_t enables;
2743         int rc;
2744
2745         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2746                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2747                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2748                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2749                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2750                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2751                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2752                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2753                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2754
2755         if (BNXT_HAS_RING_GRPS(bp)) {
2756                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2757                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2758         } else if (BNXT_HAS_NQ(bp)) {
2759                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2760                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2761         }
2762
2763         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2764         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2765         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2766                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2767                                    BNXT_NUM_VLANS);
2768         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2769         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2770         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2771         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2772         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2773         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2774         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2775         req.fid = rte_cpu_to_le_16(0xffff);
2776         req.enables = rte_cpu_to_le_32(enables);
2777
2778         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2779
2780         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2781
2782         HWRM_CHECK_RESULT();
2783         HWRM_UNLOCK();
2784
2785         return rc;
2786 }
2787
2788 static void populate_vf_func_cfg_req(struct bnxt *bp,
2789                                      struct hwrm_func_cfg_input *req,
2790                                      int num_vfs)
2791 {
2792         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2793                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2794                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2795                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2796                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2797                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2798                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2799                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2800                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2801                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2802
2803         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2804                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2805                                     BNXT_NUM_VLANS);
2806         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2807                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2808                                     BNXT_NUM_VLANS);
2809         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2810                                                 (num_vfs + 1));
2811         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2812         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2813                                                (num_vfs + 1));
2814         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2815         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2816         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2817         /* TODO: For now, do not support VMDq/RFS on VFs. */
2818         req->num_vnics = rte_cpu_to_le_16(1);
2819         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2820                                                  (num_vfs + 1));
2821 }
2822
2823 static void add_random_mac_if_needed(struct bnxt *bp,
2824                                      struct hwrm_func_cfg_input *cfg_req,
2825                                      int vf)
2826 {
2827         struct rte_ether_addr mac;
2828
2829         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2830                 return;
2831
2832         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2833                 cfg_req->enables |=
2834                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2835                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2836                 bp->pf.vf_info[vf].random_mac = true;
2837         } else {
2838                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2839                         RTE_ETHER_ADDR_LEN);
2840         }
2841 }
2842
2843 static void reserve_resources_from_vf(struct bnxt *bp,
2844                                       struct hwrm_func_cfg_input *cfg_req,
2845                                       int vf)
2846 {
2847         struct hwrm_func_qcaps_input req = {0};
2848         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2849         int rc;
2850
2851         /* Get the actual allocated values now */
2852         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2853         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2854         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2855
2856         if (rc) {
2857                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2858                 copy_func_cfg_to_qcaps(cfg_req, resp);
2859         } else if (resp->error_code) {
2860                 rc = rte_le_to_cpu_16(resp->error_code);
2861                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2862                 copy_func_cfg_to_qcaps(cfg_req, resp);
2863         }
2864
2865         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2866         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2867         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2868         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2869         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2870         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2871         /*
2872          * TODO: While not supporting VMDq with VFs, max_vnics is always
2873          * forced to 1 in this case
2874          */
2875         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2876         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2877
2878         HWRM_UNLOCK();
2879 }
2880
2881 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2882 {
2883         struct hwrm_func_qcfg_input req = {0};
2884         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2885         int rc;
2886
2887         /* Check for zero MAC address */
2888         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2889         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2890         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2891         if (rc) {
2892                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2893                 return -1;
2894         } else if (resp->error_code) {
2895                 rc = rte_le_to_cpu_16(resp->error_code);
2896                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2897                 return -1;
2898         }
2899         rc = rte_le_to_cpu_16(resp->vlan);
2900
2901         HWRM_UNLOCK();
2902
2903         return rc;
2904 }
2905
2906 static int update_pf_resource_max(struct bnxt *bp)
2907 {
2908         struct hwrm_func_qcfg_input req = {0};
2909         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2910         int rc;
2911
2912         /* And copy the allocated numbers into the pf struct */
2913         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2914         req.fid = rte_cpu_to_le_16(0xffff);
2915         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2916         HWRM_CHECK_RESULT();
2917
2918         /* Only TX ring value reflects actual allocation? TODO */
2919         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2920         bp->pf.evb_mode = resp->evb_mode;
2921
2922         HWRM_UNLOCK();
2923
2924         return rc;
2925 }
2926
2927 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2928 {
2929         int rc;
2930
2931         if (!BNXT_PF(bp)) {
2932                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2933                 return -1;
2934         }
2935
2936         rc = bnxt_hwrm_func_qcaps(bp);
2937         if (rc)
2938                 return rc;
2939
2940         bp->pf.func_cfg_flags &=
2941                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2942                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2943         bp->pf.func_cfg_flags |=
2944                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2945         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2946         rc = __bnxt_hwrm_func_qcaps(bp);
2947         return rc;
2948 }
2949
2950 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2951 {
2952         struct hwrm_func_cfg_input req = {0};
2953         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2954         int i;
2955         size_t sz;
2956         int rc = 0;
2957         size_t req_buf_sz;
2958
2959         if (!BNXT_PF(bp)) {
2960                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2961                 return -1;
2962         }
2963
2964         rc = bnxt_hwrm_func_qcaps(bp);
2965
2966         if (rc)
2967                 return rc;
2968
2969         bp->pf.active_vfs = num_vfs;
2970
2971         /*
2972          * First, configure the PF to only use one TX ring.  This ensures that
2973          * there are enough rings for all VFs.
2974          *
2975          * If we don't do this, when we call func_alloc() later, we will lock
2976          * extra rings to the PF that won't be available during func_cfg() of
2977          * the VFs.
2978          *
2979          * This has been fixed with firmware versions above 20.6.54
2980          */
2981         bp->pf.func_cfg_flags &=
2982                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2983                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2984         bp->pf.func_cfg_flags |=
2985                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2986         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2987         if (rc)
2988                 return rc;
2989
2990         /*
2991          * Now, create and register a buffer to hold forwarded VF requests
2992          */
2993         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2994         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2995                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2996         if (bp->pf.vf_req_buf == NULL) {
2997                 rc = -ENOMEM;
2998                 goto error_free;
2999         }
3000         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3001                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3002         for (i = 0; i < num_vfs; i++)
3003                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3004                                         (i * HWRM_MAX_REQ_LEN);
3005
3006         rc = bnxt_hwrm_func_buf_rgtr(bp);
3007         if (rc)
3008                 goto error_free;
3009
3010         populate_vf_func_cfg_req(bp, &req, num_vfs);
3011
3012         bp->pf.active_vfs = 0;
3013         for (i = 0; i < num_vfs; i++) {
3014                 add_random_mac_if_needed(bp, &req, i);
3015
3016                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3017                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3018                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3019                 rc = bnxt_hwrm_send_message(bp,
3020                                             &req,
3021                                             sizeof(req),
3022                                             BNXT_USE_CHIMP_MB);
3023
3024                 /* Clear enable flag for next pass */
3025                 req.enables &= ~rte_cpu_to_le_32(
3026                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3027
3028                 if (rc || resp->error_code) {
3029                         PMD_DRV_LOG(ERR,
3030                                 "Failed to initizlie VF %d\n", i);
3031                         PMD_DRV_LOG(ERR,
3032                                 "Not all VFs available. (%d, %d)\n",
3033                                 rc, resp->error_code);
3034                         HWRM_UNLOCK();
3035                         break;
3036                 }
3037
3038                 HWRM_UNLOCK();
3039
3040                 reserve_resources_from_vf(bp, &req, i);
3041                 bp->pf.active_vfs++;
3042                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3043         }
3044
3045         /*
3046          * Now configure the PF to use "the rest" of the resources
3047          * We're using STD_TX_RING_MODE here though which will limit the TX
3048          * rings.  This will allow QoS to function properly.  Not setting this
3049          * will cause PF rings to break bandwidth settings.
3050          */
3051         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3052         if (rc)
3053                 goto error_free;
3054
3055         rc = update_pf_resource_max(bp);
3056         if (rc)
3057                 goto error_free;
3058
3059         return rc;
3060
3061 error_free:
3062         bnxt_hwrm_func_buf_unrgtr(bp);
3063         return rc;
3064 }
3065
3066 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3067 {
3068         struct hwrm_func_cfg_input req = {0};
3069         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3070         int rc;
3071
3072         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3073
3074         req.fid = rte_cpu_to_le_16(0xffff);
3075         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3076         req.evb_mode = bp->pf.evb_mode;
3077
3078         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3079         HWRM_CHECK_RESULT();
3080         HWRM_UNLOCK();
3081
3082         return rc;
3083 }
3084
3085 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3086                                 uint8_t tunnel_type)
3087 {
3088         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3089         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3090         int rc = 0;
3091
3092         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3093         req.tunnel_type = tunnel_type;
3094         req.tunnel_dst_port_val = port;
3095         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3096         HWRM_CHECK_RESULT();
3097
3098         switch (tunnel_type) {
3099         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3100                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3101                 bp->vxlan_port = port;
3102                 break;
3103         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3104                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3105                 bp->geneve_port = port;
3106                 break;
3107         default:
3108                 break;
3109         }
3110
3111         HWRM_UNLOCK();
3112
3113         return rc;
3114 }
3115
3116 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3117                                 uint8_t tunnel_type)
3118 {
3119         struct hwrm_tunnel_dst_port_free_input req = {0};
3120         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3121         int rc = 0;
3122
3123         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3124
3125         req.tunnel_type = tunnel_type;
3126         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3127         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3128
3129         HWRM_CHECK_RESULT();
3130         HWRM_UNLOCK();
3131
3132         return rc;
3133 }
3134
3135 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3136                                         uint32_t flags)
3137 {
3138         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3139         struct hwrm_func_cfg_input req = {0};
3140         int rc;
3141
3142         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3143
3144         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3145         req.flags = rte_cpu_to_le_32(flags);
3146         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3147
3148         HWRM_CHECK_RESULT();
3149         HWRM_UNLOCK();
3150
3151         return rc;
3152 }
3153
3154 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3155 {
3156         uint32_t *flag = flagp;
3157
3158         vnic->flags = *flag;
3159 }
3160
3161 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3162 {
3163         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3164 }
3165
3166 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3167 {
3168         int rc = 0;
3169         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3170         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3171
3172         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3173
3174         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3175         req.req_buf_page_size = rte_cpu_to_le_16(
3176                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3177         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3178         req.req_buf_page_addr0 =
3179                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3180         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3181                 PMD_DRV_LOG(ERR,
3182                         "unable to map buffer address to physical memory\n");
3183                 return -ENOMEM;
3184         }
3185
3186         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3187
3188         HWRM_CHECK_RESULT();
3189         HWRM_UNLOCK();
3190
3191         return rc;
3192 }
3193
3194 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3195 {
3196         int rc = 0;
3197         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3198         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3199
3200         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3201                 return 0;
3202
3203         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3204
3205         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3206
3207         HWRM_CHECK_RESULT();
3208         HWRM_UNLOCK();
3209
3210         return rc;
3211 }
3212
3213 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3214 {
3215         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3216         struct hwrm_func_cfg_input req = {0};
3217         int rc;
3218
3219         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3220
3221         req.fid = rte_cpu_to_le_16(0xffff);
3222         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3223         req.enables = rte_cpu_to_le_32(
3224                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3225         req.async_event_cr = rte_cpu_to_le_16(
3226                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3227         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3228
3229         HWRM_CHECK_RESULT();
3230         HWRM_UNLOCK();
3231
3232         return rc;
3233 }
3234
3235 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3236 {
3237         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3238         struct hwrm_func_vf_cfg_input req = {0};
3239         int rc;
3240
3241         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3242
3243         req.enables = rte_cpu_to_le_32(
3244                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3245         req.async_event_cr = rte_cpu_to_le_16(
3246                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3247         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3248
3249         HWRM_CHECK_RESULT();
3250         HWRM_UNLOCK();
3251
3252         return rc;
3253 }
3254
3255 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3256 {
3257         struct hwrm_func_cfg_input req = {0};
3258         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3259         uint16_t dflt_vlan, fid;
3260         uint32_t func_cfg_flags;
3261         int rc = 0;
3262
3263         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3264
3265         if (is_vf) {
3266                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3267                 fid = bp->pf.vf_info[vf].fid;
3268                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3269         } else {
3270                 fid = rte_cpu_to_le_16(0xffff);
3271                 func_cfg_flags = bp->pf.func_cfg_flags;
3272                 dflt_vlan = bp->vlan;
3273         }
3274
3275         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3276         req.fid = rte_cpu_to_le_16(fid);
3277         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3278         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3279
3280         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3281
3282         HWRM_CHECK_RESULT();
3283         HWRM_UNLOCK();
3284
3285         return rc;
3286 }
3287
3288 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3289                         uint16_t max_bw, uint16_t enables)
3290 {
3291         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3292         struct hwrm_func_cfg_input req = {0};
3293         int rc;
3294
3295         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3296
3297         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3298         req.enables |= rte_cpu_to_le_32(enables);
3299         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3300         req.max_bw = rte_cpu_to_le_32(max_bw);
3301         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3302
3303         HWRM_CHECK_RESULT();
3304         HWRM_UNLOCK();
3305
3306         return rc;
3307 }
3308
3309 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3310 {
3311         struct hwrm_func_cfg_input req = {0};
3312         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3313         int rc = 0;
3314
3315         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3316
3317         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3318         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3319         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3320         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3321
3322         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3323
3324         HWRM_CHECK_RESULT();
3325         HWRM_UNLOCK();
3326
3327         return rc;
3328 }
3329
3330 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3331 {
3332         int rc;
3333
3334         if (BNXT_PF(bp))
3335                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3336         else
3337                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3338
3339         return rc;
3340 }
3341
3342 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3343                               void *encaped, size_t ec_size)
3344 {
3345         int rc = 0;
3346         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3347         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3348
3349         if (ec_size > sizeof(req.encap_request))
3350                 return -1;
3351
3352         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3353
3354         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3355         memcpy(req.encap_request, encaped, ec_size);
3356
3357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3358
3359         HWRM_CHECK_RESULT();
3360         HWRM_UNLOCK();
3361
3362         return rc;
3363 }
3364
3365 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3366                                        struct rte_ether_addr *mac)
3367 {
3368         struct hwrm_func_qcfg_input req = {0};
3369         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3370         int rc;
3371
3372         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3373
3374         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3375         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3376
3377         HWRM_CHECK_RESULT();
3378
3379         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3380
3381         HWRM_UNLOCK();
3382
3383         return rc;
3384 }
3385
3386 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3387                             void *encaped, size_t ec_size)
3388 {
3389         int rc = 0;
3390         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3391         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3392
3393         if (ec_size > sizeof(req.encap_request))
3394                 return -1;
3395
3396         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3397
3398         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3399         memcpy(req.encap_request, encaped, ec_size);
3400
3401         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3402
3403         HWRM_CHECK_RESULT();
3404         HWRM_UNLOCK();
3405
3406         return rc;
3407 }
3408
3409 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3410                          struct rte_eth_stats *stats, uint8_t rx)
3411 {
3412         int rc = 0;
3413         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3414         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3415
3416         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3417
3418         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3419
3420         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3421
3422         HWRM_CHECK_RESULT();
3423
3424         if (rx) {
3425                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3426                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3427                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3428                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3429                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3430                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3431                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3432                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3433         } else {
3434                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3435                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3436                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3437                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3438                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3439                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3440         }
3441
3442
3443         HWRM_UNLOCK();
3444
3445         return rc;
3446 }
3447
3448 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3449 {
3450         struct hwrm_port_qstats_input req = {0};
3451         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3452         struct bnxt_pf_info *pf = &bp->pf;
3453         int rc;
3454
3455         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3456
3457         req.port_id = rte_cpu_to_le_16(pf->port_id);
3458         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3459         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3460         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3461
3462         HWRM_CHECK_RESULT();
3463         HWRM_UNLOCK();
3464
3465         return rc;
3466 }
3467
3468 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3469 {
3470         struct hwrm_port_clr_stats_input req = {0};
3471         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3472         struct bnxt_pf_info *pf = &bp->pf;
3473         int rc;
3474
3475         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3476         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3477             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3478                 return 0;
3479
3480         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3481
3482         req.port_id = rte_cpu_to_le_16(pf->port_id);
3483         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3484
3485         HWRM_CHECK_RESULT();
3486         HWRM_UNLOCK();
3487
3488         return rc;
3489 }
3490
3491 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3492 {
3493         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3494         struct hwrm_port_led_qcaps_input req = {0};
3495         int rc;
3496
3497         if (BNXT_VF(bp))
3498                 return 0;
3499
3500         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3501         req.port_id = bp->pf.port_id;
3502         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3503
3504         HWRM_CHECK_RESULT();
3505
3506         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3507                 unsigned int i;
3508
3509                 bp->num_leds = resp->num_leds;
3510                 memcpy(bp->leds, &resp->led0_id,
3511                         sizeof(bp->leds[0]) * bp->num_leds);
3512                 for (i = 0; i < bp->num_leds; i++) {
3513                         struct bnxt_led_info *led = &bp->leds[i];
3514
3515                         uint16_t caps = led->led_state_caps;
3516
3517                         if (!led->led_group_id ||
3518                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3519                                 bp->num_leds = 0;
3520                                 break;
3521                         }
3522                 }
3523         }
3524
3525         HWRM_UNLOCK();
3526
3527         return rc;
3528 }
3529
3530 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3531 {
3532         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3533         struct hwrm_port_led_cfg_input req = {0};
3534         struct bnxt_led_cfg *led_cfg;
3535         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3536         uint16_t duration = 0;
3537         int rc, i;
3538
3539         if (!bp->num_leds || BNXT_VF(bp))
3540                 return -EOPNOTSUPP;
3541
3542         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3543
3544         if (led_on) {
3545                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3546                 duration = rte_cpu_to_le_16(500);
3547         }
3548         req.port_id = bp->pf.port_id;
3549         req.num_leds = bp->num_leds;
3550         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3551         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3552                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3553                 led_cfg->led_id = bp->leds[i].led_id;
3554                 led_cfg->led_state = led_state;
3555                 led_cfg->led_blink_on = duration;
3556                 led_cfg->led_blink_off = duration;
3557                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3558         }
3559
3560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3561
3562         HWRM_CHECK_RESULT();
3563         HWRM_UNLOCK();
3564
3565         return rc;
3566 }
3567
3568 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3569                                uint32_t *length)
3570 {
3571         int rc;
3572         struct hwrm_nvm_get_dir_info_input req = {0};
3573         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3574
3575         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3576
3577         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3578
3579         HWRM_CHECK_RESULT();
3580         HWRM_UNLOCK();
3581
3582         if (!rc) {
3583                 *entries = rte_le_to_cpu_32(resp->entries);
3584                 *length = rte_le_to_cpu_32(resp->entry_length);
3585         }
3586         return rc;
3587 }
3588
3589 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3590 {
3591         int rc;
3592         uint32_t dir_entries;
3593         uint32_t entry_length;
3594         uint8_t *buf;
3595         size_t buflen;
3596         rte_iova_t dma_handle;
3597         struct hwrm_nvm_get_dir_entries_input req = {0};
3598         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3599
3600         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3601         if (rc != 0)
3602                 return rc;
3603
3604         *data++ = dir_entries;
3605         *data++ = entry_length;
3606         len -= 2;
3607         memset(data, 0xff, len);
3608
3609         buflen = dir_entries * entry_length;
3610         buf = rte_malloc("nvm_dir", buflen, 0);
3611         rte_mem_lock_page(buf);
3612         if (buf == NULL)
3613                 return -ENOMEM;
3614         dma_handle = rte_mem_virt2iova(buf);
3615         if (dma_handle == RTE_BAD_IOVA) {
3616                 PMD_DRV_LOG(ERR,
3617                         "unable to map response address to physical memory\n");
3618                 return -ENOMEM;
3619         }
3620         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3621         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3622         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3623
3624         if (rc == 0)
3625                 memcpy(data, buf, len > buflen ? buflen : len);
3626
3627         rte_free(buf);
3628         HWRM_CHECK_RESULT();
3629         HWRM_UNLOCK();
3630
3631         return rc;
3632 }
3633
3634 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3635                              uint32_t offset, uint32_t length,
3636                              uint8_t *data)
3637 {
3638         int rc;
3639         uint8_t *buf;
3640         rte_iova_t dma_handle;
3641         struct hwrm_nvm_read_input req = {0};
3642         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3643
3644         buf = rte_malloc("nvm_item", length, 0);
3645         rte_mem_lock_page(buf);
3646         if (!buf)
3647                 return -ENOMEM;
3648
3649         dma_handle = rte_mem_virt2iova(buf);
3650         if (dma_handle == RTE_BAD_IOVA) {
3651                 PMD_DRV_LOG(ERR,
3652                         "unable to map response address to physical memory\n");
3653                 return -ENOMEM;
3654         }
3655         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3656         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3657         req.dir_idx = rte_cpu_to_le_16(index);
3658         req.offset = rte_cpu_to_le_32(offset);
3659         req.len = rte_cpu_to_le_32(length);
3660         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3661         if (rc == 0)
3662                 memcpy(data, buf, length);
3663
3664         rte_free(buf);
3665         HWRM_CHECK_RESULT();
3666         HWRM_UNLOCK();
3667
3668         return rc;
3669 }
3670
3671 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3672 {
3673         int rc;
3674         struct hwrm_nvm_erase_dir_entry_input req = {0};
3675         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3676
3677         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3678         req.dir_idx = rte_cpu_to_le_16(index);
3679         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3680         HWRM_CHECK_RESULT();
3681         HWRM_UNLOCK();
3682
3683         return rc;
3684 }
3685
3686
3687 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3688                           uint16_t dir_ordinal, uint16_t dir_ext,
3689                           uint16_t dir_attr, const uint8_t *data,
3690                           size_t data_len)
3691 {
3692         int rc;
3693         struct hwrm_nvm_write_input req = {0};
3694         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3695         rte_iova_t dma_handle;
3696         uint8_t *buf;
3697
3698         buf = rte_malloc("nvm_write", data_len, 0);
3699         rte_mem_lock_page(buf);
3700         if (!buf)
3701                 return -ENOMEM;
3702
3703         dma_handle = rte_mem_virt2iova(buf);
3704         if (dma_handle == RTE_BAD_IOVA) {
3705                 PMD_DRV_LOG(ERR,
3706                         "unable to map response address to physical memory\n");
3707                 return -ENOMEM;
3708         }
3709         memcpy(buf, data, data_len);
3710
3711         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3712
3713         req.dir_type = rte_cpu_to_le_16(dir_type);
3714         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3715         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3716         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3717         req.dir_data_length = rte_cpu_to_le_32(data_len);
3718         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3719
3720         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3721
3722         rte_free(buf);
3723         HWRM_CHECK_RESULT();
3724         HWRM_UNLOCK();
3725
3726         return rc;
3727 }
3728
3729 static void
3730 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3731 {
3732         uint32_t *count = cbdata;
3733
3734         *count = *count + 1;
3735 }
3736
3737 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3738                                      struct bnxt_vnic_info *vnic __rte_unused)
3739 {
3740         return 0;
3741 }
3742
3743 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3744 {
3745         uint32_t count = 0;
3746
3747         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3748             &count, bnxt_vnic_count_hwrm_stub);
3749
3750         return count;
3751 }
3752
3753 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3754                                         uint16_t *vnic_ids)
3755 {
3756         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3757         struct hwrm_func_vf_vnic_ids_query_output *resp =
3758                                                 bp->hwrm_cmd_resp_addr;
3759         int rc;
3760
3761         /* First query all VNIC ids */
3762         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3763
3764         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3765         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3766         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3767
3768         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3769                 HWRM_UNLOCK();
3770                 PMD_DRV_LOG(ERR,
3771                 "unable to map VNIC ID table address to physical memory\n");
3772                 return -ENOMEM;
3773         }
3774         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3775         HWRM_CHECK_RESULT();
3776         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3777
3778         HWRM_UNLOCK();
3779
3780         return rc;
3781 }
3782
3783 /*
3784  * This function queries the VNIC IDs  for a specified VF. It then calls
3785  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3786  * Then it calls the hwrm_cb function to program this new vnic configuration.
3787  */
3788 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3789         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3790         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3791 {
3792         struct bnxt_vnic_info vnic;
3793         int rc = 0;
3794         int i, num_vnic_ids;
3795         uint16_t *vnic_ids;
3796         size_t vnic_id_sz;
3797         size_t sz;
3798
3799         /* First query all VNIC ids */
3800         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3801         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3802                         RTE_CACHE_LINE_SIZE);
3803         if (vnic_ids == NULL) {
3804                 rc = -ENOMEM;
3805                 return rc;
3806         }
3807         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3808                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3809
3810         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3811
3812         if (num_vnic_ids < 0)
3813                 return num_vnic_ids;
3814
3815         /* Retrieve VNIC, update bd_stall then update */
3816
3817         for (i = 0; i < num_vnic_ids; i++) {
3818                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3819                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3820                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3821                 if (rc)
3822                         break;
3823                 if (vnic.mru <= 4)      /* Indicates unallocated */
3824                         continue;
3825
3826                 vnic_cb(&vnic, cbdata);
3827
3828                 rc = hwrm_cb(bp, &vnic);
3829                 if (rc)
3830                         break;
3831         }
3832
3833         rte_free(vnic_ids);
3834
3835         return rc;
3836 }
3837
3838 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3839                                               bool on)
3840 {
3841         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3842         struct hwrm_func_cfg_input req = {0};
3843         int rc;
3844
3845         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3846
3847         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3848         req.enables |= rte_cpu_to_le_32(
3849                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3850         req.vlan_antispoof_mode = on ?
3851                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3852                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3853         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3854
3855         HWRM_CHECK_RESULT();
3856         HWRM_UNLOCK();
3857
3858         return rc;
3859 }
3860
3861 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3862 {
3863         struct bnxt_vnic_info vnic;
3864         uint16_t *vnic_ids;
3865         size_t vnic_id_sz;
3866         int num_vnic_ids, i;
3867         size_t sz;
3868         int rc;
3869
3870         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3871         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3872                         RTE_CACHE_LINE_SIZE);
3873         if (vnic_ids == NULL) {
3874                 rc = -ENOMEM;
3875                 return rc;
3876         }
3877
3878         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3879                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3880
3881         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3882         if (rc <= 0)
3883                 goto exit;
3884         num_vnic_ids = rc;
3885
3886         /*
3887          * Loop through to find the default VNIC ID.
3888          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3889          * by sending the hwrm_func_qcfg command to the firmware.
3890          */
3891         for (i = 0; i < num_vnic_ids; i++) {
3892                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3893                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3894                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3895                                         bp->pf.first_vf_id + vf);
3896                 if (rc)
3897                         goto exit;
3898                 if (vnic.func_default) {
3899                         rte_free(vnic_ids);
3900                         return vnic.fw_vnic_id;
3901                 }
3902         }
3903         /* Could not find a default VNIC. */
3904         PMD_DRV_LOG(ERR, "No default VNIC\n");
3905 exit:
3906         rte_free(vnic_ids);
3907         return -1;
3908 }
3909
3910 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3911                          uint16_t dst_id,
3912                          struct bnxt_filter_info *filter)
3913 {
3914         int rc = 0;
3915         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3916         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3917         uint32_t enables = 0;
3918
3919         if (filter->fw_em_filter_id != UINT64_MAX)
3920                 bnxt_hwrm_clear_em_filter(bp, filter);
3921
3922         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3923
3924         req.flags = rte_cpu_to_le_32(filter->flags);
3925
3926         enables = filter->enables |
3927               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3928         req.dst_id = rte_cpu_to_le_16(dst_id);
3929
3930         if (filter->ip_addr_type) {
3931                 req.ip_addr_type = filter->ip_addr_type;
3932                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3933         }
3934         if (enables &
3935             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3936                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3937         if (enables &
3938             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3939                 memcpy(req.src_macaddr, filter->src_macaddr,
3940                        RTE_ETHER_ADDR_LEN);
3941         if (enables &
3942             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3943                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3944                        RTE_ETHER_ADDR_LEN);
3945         if (enables &
3946             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3947                 req.ovlan_vid = filter->l2_ovlan;
3948         if (enables &
3949             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3950                 req.ivlan_vid = filter->l2_ivlan;
3951         if (enables &
3952             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3953                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3954         if (enables &
3955             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3956                 req.ip_protocol = filter->ip_protocol;
3957         if (enables &
3958             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3959                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3960         if (enables &
3961             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3962                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3963         if (enables &
3964             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3965                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3966         if (enables &
3967             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3968                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3969         if (enables &
3970             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3971                 req.mirror_vnic_id = filter->mirror_vnic_id;
3972
3973         req.enables = rte_cpu_to_le_32(enables);
3974
3975         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3976
3977         HWRM_CHECK_RESULT();
3978
3979         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3980         HWRM_UNLOCK();
3981
3982         return rc;
3983 }
3984
3985 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3986 {
3987         int rc = 0;
3988         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3989         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3990
3991         if (filter->fw_em_filter_id == UINT64_MAX)
3992                 return 0;
3993
3994         PMD_DRV_LOG(ERR, "Clear EM filter\n");
3995         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
3996
3997         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3998
3999         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4000
4001         HWRM_CHECK_RESULT();
4002         HWRM_UNLOCK();
4003
4004         filter->fw_em_filter_id = UINT64_MAX;
4005         filter->fw_l2_filter_id = UINT64_MAX;
4006
4007         return 0;
4008 }
4009
4010 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4011                          uint16_t dst_id,
4012                          struct bnxt_filter_info *filter)
4013 {
4014         int rc = 0;
4015         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4016         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4017                                                 bp->hwrm_cmd_resp_addr;
4018         uint32_t enables = 0;
4019
4020         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4021                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4022
4023         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4024
4025         req.flags = rte_cpu_to_le_32(filter->flags);
4026
4027         enables = filter->enables |
4028               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4029         req.dst_id = rte_cpu_to_le_16(dst_id);
4030
4031
4032         if (filter->ip_addr_type) {
4033                 req.ip_addr_type = filter->ip_addr_type;
4034                 enables |=
4035                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4036         }
4037         if (enables &
4038             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4039                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4040         if (enables &
4041             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4042                 memcpy(req.src_macaddr, filter->src_macaddr,
4043                        RTE_ETHER_ADDR_LEN);
4044         //if (enables &
4045             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4046                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4047                        //RTE_ETHER_ADDR_LEN);
4048         if (enables &
4049             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4050                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4051         if (enables &
4052             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4053                 req.ip_protocol = filter->ip_protocol;
4054         if (enables &
4055             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4056                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4057         if (enables &
4058             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4059                 req.src_ipaddr_mask[0] =
4060                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4061         if (enables &
4062             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4063                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4064         if (enables &
4065             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4066                 req.dst_ipaddr_mask[0] =
4067                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4068         if (enables &
4069             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4070                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4071         if (enables &
4072             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4073                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4074         if (enables &
4075             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4076                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4077         if (enables &
4078             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4079                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4080         if (enables &
4081             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4082                 req.mirror_vnic_id = filter->mirror_vnic_id;
4083
4084         req.enables = rte_cpu_to_le_32(enables);
4085
4086         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4087
4088         HWRM_CHECK_RESULT();
4089
4090         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4091         HWRM_UNLOCK();
4092
4093         return rc;
4094 }
4095
4096 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4097                                 struct bnxt_filter_info *filter)
4098 {
4099         int rc = 0;
4100         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4101         struct hwrm_cfa_ntuple_filter_free_output *resp =
4102                                                 bp->hwrm_cmd_resp_addr;
4103
4104         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4105                 return 0;
4106
4107         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4108
4109         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4110
4111         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4112
4113         HWRM_CHECK_RESULT();
4114         HWRM_UNLOCK();
4115
4116         filter->fw_ntuple_filter_id = UINT64_MAX;
4117
4118         return 0;
4119 }
4120
4121 static int
4122 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4123 {
4124         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4125         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4126         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4127         int nr_ctxs = bp->max_ring_grps;
4128         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4129         uint16_t *ring_tbl = vnic->rss_table;
4130         int max_rings = bp->rx_nr_rings;
4131         int i, j, k, cnt;
4132         int rc = 0;
4133
4134         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4135
4136         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4137         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4138         req.hash_mode_flags = vnic->hash_mode;
4139
4140         req.ring_grp_tbl_addr =
4141             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
4142         req.hash_key_tbl_addr =
4143             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4144
4145         for (i = 0, k = 0; i < nr_ctxs; i++) {
4146                 struct bnxt_rx_ring_info *rxr;
4147                 struct bnxt_cp_ring_info *cpr;
4148
4149                 req.ring_table_pair_index = i;
4150                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4151
4152                 for (j = 0; j < 64; j++) {
4153                         uint16_t ring_id;
4154
4155                         /* Find next active ring. */
4156                         for (cnt = 0; cnt < max_rings; cnt++) {
4157                                 if (rx_queue_state[k] !=
4158                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4159                                         break;
4160                                 if (++k == max_rings)
4161                                         k = 0;
4162                         }
4163
4164                         /* Return if no rings are active. */
4165                         if (cnt == max_rings)
4166                                 return 0;
4167
4168                         /* Add rx/cp ring pair to RSS table. */
4169                         rxr = rxqs[k]->rx_ring;
4170                         cpr = rxqs[k]->cp_ring;
4171
4172                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4173                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4174                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4175                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4176
4177                         if (++k == max_rings)
4178                                 k = 0;
4179                 }
4180                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4181                                             BNXT_USE_CHIMP_MB);
4182
4183                 HWRM_CHECK_RESULT();
4184         }
4185
4186         HWRM_UNLOCK();
4187
4188         return rc;
4189 }
4190
4191 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4192 {
4193         unsigned int rss_idx, fw_idx, i;
4194
4195         if (!(vnic->rss_table && vnic->hash_type))
4196                 return 0;
4197
4198         if (BNXT_CHIP_THOR(bp))
4199                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4200
4201         /*
4202          * Fill the RSS hash & redirection table with
4203          * ring group ids for all VNICs
4204          */
4205         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4206                 rss_idx++, fw_idx++) {
4207                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4208                         fw_idx %= bp->rx_cp_nr_rings;
4209                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4210                                 break;
4211                         fw_idx++;
4212                 }
4213                 if (i == bp->rx_cp_nr_rings)
4214                         return 0;
4215                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4216         }
4217         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4218 }
4219
4220 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4221         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4222 {
4223         uint16_t flags;
4224
4225         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4226
4227         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4228         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4229
4230         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4231         req->num_cmpl_dma_aggr_during_int =
4232                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4233
4234         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4235
4236         /* min timer set to 1/2 of interrupt timer */
4237         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4238
4239         /* buf timer set to 1/4 of interrupt timer */
4240         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4241
4242         req->cmpl_aggr_dma_tmr_during_int =
4243                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4244
4245         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4246                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4247         req->flags = rte_cpu_to_le_16(flags);
4248 }
4249
4250 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4251                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4252 {
4253         struct hwrm_ring_aggint_qcaps_input req = {0};
4254         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4255         uint32_t enables;
4256         uint16_t flags;
4257         int rc;
4258
4259         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4260         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4261         HWRM_CHECK_RESULT();
4262
4263         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4264         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4265
4266         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4267                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4268         agg_req->flags = rte_cpu_to_le_16(flags);
4269         enables =
4270          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4271          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4272         agg_req->enables = rte_cpu_to_le_32(enables);
4273
4274         HWRM_UNLOCK();
4275         return rc;
4276 }
4277
4278 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4279                         struct bnxt_coal *coal, uint16_t ring_id)
4280 {
4281         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4282         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4283                                                 bp->hwrm_cmd_resp_addr;
4284         int rc;
4285
4286         /* Set ring coalesce parameters only for 100G NICs */
4287         if (BNXT_CHIP_THOR(bp)) {
4288                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4289                         return -1;
4290         } else if (bnxt_stratus_device(bp)) {
4291                 bnxt_hwrm_set_coal_params(coal, &req);
4292         } else {
4293                 return 0;
4294         }
4295
4296         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4297         req.ring_id = rte_cpu_to_le_16(ring_id);
4298         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4299         HWRM_CHECK_RESULT();
4300         HWRM_UNLOCK();
4301         return 0;
4302 }
4303
4304 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4305 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4306 {
4307         struct hwrm_func_backing_store_qcaps_input req = {0};
4308         struct hwrm_func_backing_store_qcaps_output *resp =
4309                 bp->hwrm_cmd_resp_addr;
4310         int rc;
4311
4312         if (!BNXT_CHIP_THOR(bp) ||
4313             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4314             BNXT_VF(bp) ||
4315             bp->ctx)
4316                 return 0;
4317
4318         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4319         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4320         HWRM_CHECK_RESULT_SILENT();
4321
4322         if (!rc) {
4323                 struct bnxt_ctx_pg_info *ctx_pg;
4324                 struct bnxt_ctx_mem_info *ctx;
4325                 int total_alloc_len;
4326                 int i;
4327
4328                 total_alloc_len = sizeof(*ctx);
4329                 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4330                                  RTE_CACHE_LINE_SIZE);
4331                 if (!ctx) {
4332                         rc = -ENOMEM;
4333                         goto ctx_err;
4334                 }
4335                 memset(ctx, 0, total_alloc_len);
4336
4337                 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4338                                     sizeof(*ctx_pg) * BNXT_MAX_Q,
4339                                     RTE_CACHE_LINE_SIZE);
4340                 if (!ctx_pg) {
4341                         rc = -ENOMEM;
4342                         goto ctx_err;
4343                 }
4344                 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4345                         ctx->tqm_mem[i] = ctx_pg;
4346
4347                 bp->ctx = ctx;
4348                 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4349                 ctx->qp_min_qp1_entries =
4350                         rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4351                 ctx->qp_max_l2_entries =
4352                         rte_le_to_cpu_16(resp->qp_max_l2_entries);
4353                 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4354                 ctx->srq_max_l2_entries =
4355                         rte_le_to_cpu_16(resp->srq_max_l2_entries);
4356                 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4357                 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4358                 ctx->cq_max_l2_entries =
4359                         rte_le_to_cpu_16(resp->cq_max_l2_entries);
4360                 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4361                 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4362                 ctx->vnic_max_vnic_entries =
4363                         rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4364                 ctx->vnic_max_ring_table_entries =
4365                         rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4366                 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4367                 ctx->stat_max_entries =
4368                         rte_le_to_cpu_32(resp->stat_max_entries);
4369                 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4370                 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4371                 ctx->tqm_min_entries_per_ring =
4372                         rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4373                 ctx->tqm_max_entries_per_ring =
4374                         rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4375                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4376                 if (!ctx->tqm_entries_multiple)
4377                         ctx->tqm_entries_multiple = 1;
4378                 ctx->mrav_max_entries =
4379                         rte_le_to_cpu_32(resp->mrav_max_entries);
4380                 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4381                 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4382                 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4383         } else {
4384                 rc = 0;
4385         }
4386 ctx_err:
4387         HWRM_UNLOCK();
4388         return rc;
4389 }
4390
4391 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4392 {
4393         struct hwrm_func_backing_store_cfg_input req = {0};
4394         struct hwrm_func_backing_store_cfg_output *resp =
4395                 bp->hwrm_cmd_resp_addr;
4396         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4397         struct bnxt_ctx_pg_info *ctx_pg;
4398         uint32_t *num_entries;
4399         uint64_t *pg_dir;
4400         uint8_t *pg_attr;
4401         uint32_t ena;
4402         int i, rc;
4403
4404         if (!ctx)
4405                 return 0;
4406
4407         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4408         req.enables = rte_cpu_to_le_32(enables);
4409
4410         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4411                 ctx_pg = &ctx->qp_mem;
4412                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4413                 req.qp_num_qp1_entries =
4414                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4415                 req.qp_num_l2_entries =
4416                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4417                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4418                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4419                                       &req.qpc_pg_size_qpc_lvl,
4420                                       &req.qpc_page_dir);
4421         }
4422
4423         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4424                 ctx_pg = &ctx->srq_mem;
4425                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4426                 req.srq_num_l2_entries =
4427                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4428                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4429                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4430                                       &req.srq_pg_size_srq_lvl,
4431                                       &req.srq_page_dir);
4432         }
4433
4434         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4435                 ctx_pg = &ctx->cq_mem;
4436                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4437                 req.cq_num_l2_entries =
4438                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4439                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4440                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4441                                       &req.cq_pg_size_cq_lvl,
4442                                       &req.cq_page_dir);
4443         }
4444
4445         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4446                 ctx_pg = &ctx->vnic_mem;
4447                 req.vnic_num_vnic_entries =
4448                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4449                 req.vnic_num_ring_table_entries =
4450                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4451                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4452                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4453                                       &req.vnic_pg_size_vnic_lvl,
4454                                       &req.vnic_page_dir);
4455         }
4456
4457         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4458                 ctx_pg = &ctx->stat_mem;
4459                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4460                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4461                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4462                                       &req.stat_pg_size_stat_lvl,
4463                                       &req.stat_page_dir);
4464         }
4465
4466         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4467         num_entries = &req.tqm_sp_num_entries;
4468         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4469         pg_dir = &req.tqm_sp_page_dir;
4470         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4471         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4472                 if (!(enables & ena))
4473                         continue;
4474
4475                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4476
4477                 ctx_pg = ctx->tqm_mem[i];
4478                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4479                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4480         }
4481
4482         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4483         HWRM_CHECK_RESULT();
4484         HWRM_UNLOCK();
4485
4486         return rc;
4487 }
4488
4489 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4490 {
4491         struct hwrm_port_qstats_ext_input req = {0};
4492         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4493         struct bnxt_pf_info *pf = &bp->pf;
4494         int rc;
4495
4496         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4497               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4498                 return 0;
4499
4500         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4501
4502         req.port_id = rte_cpu_to_le_16(pf->port_id);
4503         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4504                 req.tx_stat_host_addr =
4505                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4506                 req.tx_stat_size =
4507                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4508         }
4509         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4510                 req.rx_stat_host_addr =
4511                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4512                 req.rx_stat_size =
4513                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4514         }
4515         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4516
4517         if (rc) {
4518                 bp->fw_rx_port_stats_ext_size = 0;
4519                 bp->fw_tx_port_stats_ext_size = 0;
4520         } else {
4521                 bp->fw_rx_port_stats_ext_size =
4522                         rte_le_to_cpu_16(resp->rx_stat_size);
4523                 bp->fw_tx_port_stats_ext_size =
4524                         rte_le_to_cpu_16(resp->tx_stat_size);
4525         }
4526
4527         HWRM_CHECK_RESULT();
4528         HWRM_UNLOCK();
4529
4530         return rc;
4531 }
4532
4533 int
4534 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4535 {
4536         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4537         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4538                 bp->hwrm_cmd_resp_addr;
4539         int rc = 0;
4540
4541         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_KONG(bp));
4542         req.tunnel_type = type;
4543         req.dest_fid = bp->fw_fid;
4544         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4545         HWRM_CHECK_RESULT();
4546
4547         HWRM_UNLOCK();
4548
4549         return rc;
4550 }
4551
4552 int
4553 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4554 {
4555         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4556         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4557                 bp->hwrm_cmd_resp_addr;
4558         int rc = 0;
4559
4560         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_KONG(bp));
4561         req.tunnel_type = type;
4562         req.dest_fid = bp->fw_fid;
4563         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4564         HWRM_CHECK_RESULT();
4565
4566         HWRM_UNLOCK();
4567
4568         return rc;
4569 }
4570
4571 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4572 {
4573         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4574         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4575                 bp->hwrm_cmd_resp_addr;
4576         int rc = 0;
4577
4578         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_KONG(bp));
4579         req.src_fid = bp->fw_fid;
4580         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4581         HWRM_CHECK_RESULT();
4582
4583         if (type)
4584                 *type = resp->tunnel_mask;
4585
4586         HWRM_UNLOCK();
4587
4588         return rc;
4589 }
4590
4591 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4592                                    uint16_t *dst_fid)
4593 {
4594         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4595         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4596                 bp->hwrm_cmd_resp_addr;
4597         int rc = 0;
4598
4599         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_KONG(bp));
4600         req.src_fid = bp->fw_fid;
4601         req.tunnel_type = tun_type;
4602         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4603         HWRM_CHECK_RESULT();
4604
4605         if (dst_fid)
4606                 *dst_fid = resp->dest_fid;
4607
4608         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4609
4610         HWRM_UNLOCK();
4611
4612         return rc;
4613 }
4614
4615 int bnxt_hwrm_set_mac(struct bnxt *bp)
4616 {
4617         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4618         struct hwrm_func_vf_cfg_input req = {0};
4619         int rc = 0;
4620
4621         if (!BNXT_VF(bp))
4622                 return 0;
4623
4624         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4625
4626         req.enables =
4627                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4628         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4629
4630         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4631
4632         HWRM_CHECK_RESULT();
4633
4634         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4635         HWRM_UNLOCK();
4636
4637         return rc;
4638 }