drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         /* For VER_GET command, set timeout as 50ms */
 104         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 105                 timeout = HWRM_CMD_TIMEOUT;
 106         else
 107                 timeout = bp->hwrm_cmd_timeout;
 108
 109         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 110             msg_len > bp->max_req_len) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 127         }
 128
 129         /* Write request msg to hwrm channel */
 130         for (i = 0; i < msg_len; i += 4) {
 131                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 132                 rte_write32(*data, bar);
 133                 data++;
 134         }
 135
 136         /* Zero the rest of the request space */
 137         for (; i < max_req_len; i += 4) {
 138                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 139                 rte_write32(0, bar);
 140         }
 141
 142         /* Ring channel doorbell */
 143         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 144         rte_write32(1, bar);
 145         /*
 146          * Make sure the channel doorbell ring command complete before
 147          * reading the response to avoid getting stale or invalid
 148          * responses.
 149          */
 150         rte_io_mb();
 151
 152         /* Poll for the valid bit */
 153         for (i = 0; i < timeout; i++) {
 154                 /* Sanity check on the resp->resp_len */
 155                 rte_cio_rmb();
 156                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 157                         /* Last byte of resp contains the valid key */
 158                         valid = (uint8_t *)resp + resp->resp_len - 1;
 159                         if (*valid == HWRM_RESP_VALID_KEY)
 160                                 break;
 161                 }
 162                 rte_delay_us(1);
 163         }
 164
 165         if (i >= timeout) {
 166                 /* Suppress VER_GET timeout messages during reset recovery */
 167                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 168                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 169                         return -ETIMEDOUT;
 170
 171                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 172                             req->req_type);
 173                 return -ETIMEDOUT;
 174         }
 175         return 0;
 176 }
 177
 178 /*
 179  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 180  * spinlock, and does initial processing.
 181  *
 182  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 183  * releases the spinlock only if it returns. If the regular int return codes
 184  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 185  * directly, rather it should be copied and modified to suit the function.
 186  *
 187  * HWRM_UNLOCK() must be called after all response processing is completed.
 188  */
 189 #define HWRM_PREP(req, type, kong) do { \
 190         rte_spinlock_lock(&bp->hwrm_lock); \
 191         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 192         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 193         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 194         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 195                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 196         req.target_id = rte_cpu_to_le_16(0xffff); \
 197         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 198 } while (0)
 199
 200 #define HWRM_CHECK_RESULT_SILENT() do {\
 201         if (rc) { \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 return rc; \
 204         } \
 205         if (resp->error_code) { \
 206                 rc = rte_le_to_cpu_16(resp->error_code); \
 207                 rte_spinlock_unlock(&bp->hwrm_lock); \
 208                 return rc; \
 209         } \
 210 } while (0)
 211
 212 #define HWRM_CHECK_RESULT() do {\
 213         if (rc) { \
 214                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 215                 rte_spinlock_unlock(&bp->hwrm_lock); \
 216                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 217                         rc = -EACCES; \
 218                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 219                         rc = -ENOSPC; \
 220                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 221                         rc = -EINVAL; \
 222                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 223                         rc = -ENOTSUP; \
 224                 else if (rc > 0) \
 225                         rc = -EIO; \
 226                 return rc; \
 227         } \
 228         if (resp->error_code) { \
 229                 rc = rte_le_to_cpu_16(resp->error_code); \
 230                 if (resp->resp_len >= 16) { \
 231                         struct hwrm_err_output *tmp_hwrm_err_op = \
 232                                                 (void *)resp; \
 233                         PMD_DRV_LOG(ERR, \
 234                                 "error %d:%d:%08x:%04x\n", \
 235                                 rc, tmp_hwrm_err_op->cmd_err, \
 236                                 rte_le_to_cpu_32(\
 237                                         tmp_hwrm_err_op->opaque_0), \
 238                                 rte_le_to_cpu_16(\
 239                                         tmp_hwrm_err_op->opaque_1)); \
 240                 } else { \
 241                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 242                 } \
 243                 rte_spinlock_unlock(&bp->hwrm_lock); \
 244                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 245                         rc = -EACCES; \
 246                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 247                         rc = -ENOSPC; \
 248                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 249                         rc = -EINVAL; \
 250                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 251                         rc = -ENOTSUP; \
 252                 else if (rc > 0) \
 253                         rc = -EIO; \
 254                 return rc; \
 255         } \
 256 } while (0)
 257
 258 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 259
 260 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 261 {
 262         int rc = 0;
 263         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 264         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268         req.mask = 0;
 269
 270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 271
 272         HWRM_CHECK_RESULT();
 273         HWRM_UNLOCK();
 274
 275         return rc;
 276 }
 277
 278 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 279                                  struct bnxt_vnic_info *vnic,
 280                                  uint16_t vlan_count,
 281                                  struct bnxt_vlan_table_entry *vlan_table)
 282 {
 283         int rc = 0;
 284         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 285         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 286         uint32_t mask = 0;
 287
 288         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 289                 return rc;
 290
 291         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 292         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 293
 294         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 295                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 296         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 297                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 298
 299         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 300                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 301
 302         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 303                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 304         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 305                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 306                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 307                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 308         }
 309         if (vlan_table) {
 310                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 311                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 312                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 313                          rte_mem_virt2iova(vlan_table));
 314                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 315         }
 316         req.mask = rte_cpu_to_le_32(mask);
 317
 318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 319
 320         HWRM_CHECK_RESULT();
 321         HWRM_UNLOCK();
 322
 323         return rc;
 324 }
 325
 326 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 327                         uint16_t vlan_count,
 328                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 329 {
 330         int rc = 0;
 331         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 332         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 333                                                 bp->hwrm_cmd_resp_addr;
 334
 335         /*
 336          * Older HWRM versions did not support this command, and the set_rx_mask
 337          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 338          * removed from set_rx_mask call, and this command was added.
 339          *
 340          * This command is also present from 1.7.8.11 and higher,
 341          * as well as 1.7.8.0
 342          */
 343         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 344                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 345                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 346                                         (11)))
 347                                 return 0;
 348                 }
 349         }
 350         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 351         req.fid = rte_cpu_to_le_16(fid);
 352
 353         req.vlan_tag_mask_tbl_addr =
 354                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 355         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         return rc;
 363 }
 364
 365 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 366                            struct bnxt_filter_info *filter)
 367 {
 368         int rc = 0;
 369         struct bnxt_filter_info *l2_filter = filter;
 370         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 371         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 372
 373         if (filter->fw_l2_filter_id == UINT64_MAX)
 374                 return 0;
 375
 376         if (filter->matching_l2_fltr_ptr)
 377                 l2_filter = filter->matching_l2_fltr_ptr;
 378
 379         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 380                     filter, l2_filter, l2_filter->l2_ref_cnt);
 381
 382         if (l2_filter->l2_ref_cnt > 0)
 383                 l2_filter->l2_ref_cnt--;
 384
 385         if (l2_filter->l2_ref_cnt > 0)
 386                 return 0;
 387
 388         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 389
 390         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 391
 392         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 393
 394         HWRM_CHECK_RESULT();
 395         HWRM_UNLOCK();
 396
 397         filter->fw_l2_filter_id = UINT64_MAX;
 398
 399         return 0;
 400 }
 401
 402 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 403                          uint16_t dst_id,
 404                          struct bnxt_filter_info *filter)
 405 {
 406         int rc = 0;
 407         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 408         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 409         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 410         const struct rte_eth_vmdq_rx_conf *conf =
 411                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 412         uint32_t enables = 0;
 413         uint16_t j = dst_id - 1;
 414
 415         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 416         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 417             conf->pool_map[j].pools & (1UL << j)) {
 418                 PMD_DRV_LOG(DEBUG,
 419                         "Add vlan %u to vmdq pool %u\n",
 420                         conf->pool_map[j].vlan_id, j);
 421
 422                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 423                 filter->enables |=
 424                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 425                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 426         }
 427
 428         if (filter->fw_l2_filter_id != UINT64_MAX)
 429                 bnxt_hwrm_clear_l2_filter(bp, filter);
 430
 431         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 432
 433         req.flags = rte_cpu_to_le_32(filter->flags);
 434
 435         enables = filter->enables |
 436               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 437         req.dst_id = rte_cpu_to_le_16(dst_id);
 438
 439         if (enables &
 440             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 441                 memcpy(req.l2_addr, filter->l2_addr,
 442                        RTE_ETHER_ADDR_LEN);
 443         if (enables &
 444             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 445                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 446                        RTE_ETHER_ADDR_LEN);
 447         if (enables &
 448             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 449                 req.l2_ovlan = filter->l2_ovlan;
 450         if (enables &
 451             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 452                 req.l2_ivlan = filter->l2_ivlan;
 453         if (enables &
 454             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 455                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 456         if (enables &
 457             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 458                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 459         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 460                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 461         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 462                 req.src_type = filter->src_type;
 463         if (filter->pri_hint) {
 464                 req.pri_hint = filter->pri_hint;
 465                 req.l2_filter_id_hint =
 466                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 467         }
 468
 469         req.enables = rte_cpu_to_le_32(enables);
 470
 471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 472
 473         HWRM_CHECK_RESULT();
 474
 475         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 482 {
 483         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 484         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 485         uint32_t flags = 0;
 486         int rc;
 487
 488         if (!ptp)
 489                 return 0;
 490
 491         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 492
 493         if (ptp->rx_filter)
 494                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 495         else
 496                 flags |=
 497                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 498         if (ptp->tx_tstamp_en)
 499                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 500         else
 501                 flags |=
 502                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 503         req.flags = rte_cpu_to_le_32(flags);
 504         req.enables = rte_cpu_to_le_32
 505                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 506         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 507
 508         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 509         HWRM_UNLOCK();
 510
 511         return rc;
 512 }
 513
 514 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 515 {
 516         int rc = 0;
 517         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 518         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 519         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 520
 521         if (ptp)
 522                 return 0;
 523
 524         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 525
 526         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 527
 528         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 529
 530         HWRM_CHECK_RESULT();
 531
 532         if (!BNXT_CHIP_THOR(bp) &&
 533             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 534                 return 0;
 535
 536         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 537                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 538
 539         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 540         if (!ptp)
 541                 return -ENOMEM;
 542
 543         if (!BNXT_CHIP_THOR(bp)) {
 544                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 545                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 546                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 547                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 548                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 549                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 550                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 551                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 552                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 553                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 554                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 555                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 556                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 557                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 558                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 559                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 560                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 561                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 562         }
 563
 564         ptp->bp = bp;
 565         bp->ptp_cfg = ptp;
 566
 567         return 0;
 568 }
 569
 570 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 571 {
 572         int rc = 0;
 573         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 574         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 575         uint16_t new_max_vfs;
 576         uint32_t flags;
 577         int i;
 578
 579         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 580
 581         req.fid = rte_cpu_to_le_16(0xffff);
 582
 583         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 584
 585         HWRM_CHECK_RESULT();
 586
 587         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 588         flags = rte_le_to_cpu_32(resp->flags);
 589         if (BNXT_PF(bp)) {
 590                 bp->pf.port_id = resp->port_id;
 591                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 592                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 593                 new_max_vfs = bp->pdev->max_vfs;
 594                 if (new_max_vfs != bp->pf.max_vfs) {
 595                         if (bp->pf.vf_info)
 596                                 rte_free(bp->pf.vf_info);
 597                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 598                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 599                         bp->pf.max_vfs = new_max_vfs;
 600                         for (i = 0; i < new_max_vfs; i++) {
 601                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 602                                 bp->pf.vf_info[i].vlan_table =
 603                                         rte_zmalloc("VF VLAN table",
 604                                                     getpagesize(),
 605                                                     getpagesize());
 606                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 607                                         PMD_DRV_LOG(ERR,
 608                                         "Fail to alloc VLAN table for VF %d\n",
 609                                         i);
 610                                 else
 611                                         rte_mem_lock_page(
 612                                                 bp->pf.vf_info[i].vlan_table);
 613                                 bp->pf.vf_info[i].vlan_as_table =
 614                                         rte_zmalloc("VF VLAN AS table",
 615                                                     getpagesize(),
 616                                                     getpagesize());
 617                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 618                                         PMD_DRV_LOG(ERR,
 619                                         "Alloc VLAN AS table for VF %d fail\n",
 620                                         i);
 621                                 else
 622                                         rte_mem_lock_page(
 623                                                bp->pf.vf_info[i].vlan_as_table);
 624                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 625                         }
 626                 }
 627         }
 628
 629         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 630         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 631         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 632         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 633         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 634         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 635         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 636         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 637         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 638         if (!BNXT_CHIP_THOR(bp))
 639                 bp->max_l2_ctx += bp->max_rx_em_flows;
 640         /* TODO: For now, do not support VMDq/RFS on VFs. */
 641         if (BNXT_PF(bp)) {
 642                 if (bp->pf.max_vfs)
 643                         bp->max_vnics = 1;
 644                 else
 645                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 646         } else {
 647                 bp->max_vnics = 1;
 648         }
 649         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 650         if (BNXT_PF(bp)) {
 651                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 652                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 653                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 654                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 655                         HWRM_UNLOCK();
 656                         bnxt_hwrm_ptp_qcfg(bp);
 657                 }
 658         }
 659
 660         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 661                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 662
 663         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 664                 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 665                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 666         } else {
 667                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 668         }
 669
 670         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 671                 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 672         else
 673                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 674
 675         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 676                 bp->flags |= BNXT_FLAG_FW_CAP_HOT_RESET;
 677         else
 678                 bp->flags &= ~BNXT_FLAG_FW_CAP_HOT_RESET;
 679
 680         HWRM_UNLOCK();
 681
 682         return rc;
 683 }
 684
 685 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 686 {
 687         int rc;
 688
 689         rc = __bnxt_hwrm_func_qcaps(bp);
 690         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 691                 rc = bnxt_alloc_ctx_mem(bp);
 692                 if (rc)
 693                         return rc;
 694
 695                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 696                 if (!rc)
 697                         bp->flags |= BNXT_FLAG_NEW_RM;
 698         }
 699
 700         /* On older FW,
 701          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 702          * But the error can be ignored. Return success.
 703          */
 704
 705         return 0;
 706 }
 707
 708 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 709 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 710 {
 711         int rc = 0;
 712         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 713         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 714
 715         HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 716
 717         req.target_id = rte_cpu_to_le_16(0xffff);
 718
 719         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 720
 721         HWRM_CHECK_RESULT();
 722
 723         if (rte_le_to_cpu_32(resp->flags) &
 724             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 725                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 726                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 727         }
 728
 729         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 730
 731         HWRM_UNLOCK();
 732
 733         return rc;
 734 }
 735
 736 int bnxt_hwrm_func_reset(struct bnxt *bp)
 737 {
 738         int rc = 0;
 739         struct hwrm_func_reset_input req = {.req_type = 0 };
 740         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 741
 742         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 743
 744         req.enables = rte_cpu_to_le_32(0);
 745
 746         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 747
 748         HWRM_CHECK_RESULT();
 749         HWRM_UNLOCK();
 750
 751         return rc;
 752 }
 753
 754 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 755 {
 756         int rc;
 757         uint32_t flags = 0;
 758         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 759         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 760
 761         if (bp->flags & BNXT_FLAG_REGISTERED)
 762                 return 0;
 763
 764         if (bp->flags & BNXT_FLAG_FW_CAP_HOT_RESET)
 765                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 766         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 767                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 768
 769         /* PFs and trusted VFs should indicate the support of the
 770          * Master capability on non Stingray platform
 771          */
 772         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 773                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 774
 775         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 776         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 777                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 778         req.ver_maj = RTE_VER_YEAR;
 779         req.ver_min = RTE_VER_MONTH;
 780         req.ver_upd = RTE_VER_MINOR;
 781
 782         if (BNXT_PF(bp)) {
 783                 req.enables |= rte_cpu_to_le_32(
 784                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 785                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 786                        RTE_MIN(sizeof(req.vf_req_fwd),
 787                                sizeof(bp->pf.vf_req_fwd)));
 788
 789                 /*
 790                  * PF can sniff HWRM API issued by VF. This can be set up by
 791                  * linux driver and inherited by the DPDK PF driver. Clear
 792                  * this HWRM sniffer list in FW because DPDK PF driver does
 793                  * not support this.
 794                  */
 795                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 796         }
 797
 798         req.flags = rte_cpu_to_le_32(flags);
 799
 800         req.async_event_fwd[0] |=
 801                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 802                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 803                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 804                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 805                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 806         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 807                 req.async_event_fwd[0] |=
 808                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 809         req.async_event_fwd[1] |=
 810                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 811                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 812
 813         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 814
 815         HWRM_CHECK_RESULT();
 816
 817         flags = rte_le_to_cpu_32(resp->flags);
 818         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 819                 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
 820
 821         HWRM_UNLOCK();
 822
 823         bp->flags |= BNXT_FLAG_REGISTERED;
 824
 825         return rc;
 826 }
 827
 828 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 829 {
 830         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 831                 return 0;
 832
 833         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 834 }
 835
 836 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 837 {
 838         int rc;
 839         uint32_t flags = 0;
 840         uint32_t enables;
 841         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 842         struct hwrm_func_vf_cfg_input req = {0};
 843
 844         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 845
 846         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 847                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 848                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 849                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 850                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 851
 852         if (BNXT_HAS_RING_GRPS(bp)) {
 853                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 854                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 855         }
 856
 857         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 858         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 859                                             AGG_RING_MULTIPLIER);
 860         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 861         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 862                                               bp->tx_nr_rings +
 863                                               BNXT_NUM_ASYNC_CPR(bp));
 864         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 865         if (bp->vf_resv_strategy ==
 866             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 867                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 868                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 869                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 870                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 871                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 872                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 873         } else if (bp->vf_resv_strategy ==
 874                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 875                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 876                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 877         }
 878
 879         if (test)
 880                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 881                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 882                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 883                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 884                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 885                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 886
 887         if (test && BNXT_HAS_RING_GRPS(bp))
 888                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 889
 890         req.flags = rte_cpu_to_le_32(flags);
 891         req.enables |= rte_cpu_to_le_32(enables);
 892
 893         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 894
 895         if (test)
 896                 HWRM_CHECK_RESULT_SILENT();
 897         else
 898                 HWRM_CHECK_RESULT();
 899
 900         HWRM_UNLOCK();
 901         return rc;
 902 }
 903
 904 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 905 {
 906         int rc;
 907         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 908         struct hwrm_func_resource_qcaps_input req = {0};
 909
 910         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 911         req.fid = rte_cpu_to_le_16(0xffff);
 912
 913         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 914
 915         HWRM_CHECK_RESULT_SILENT();
 916
 917         if (BNXT_VF(bp)) {
 918                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 919                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 920                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 921                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 922                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 923                 /* func_resource_qcaps does not return max_rx_em_flows.
 924                  * So use the value provided by func_qcaps.
 925                  */
 926                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 927                 if (!BNXT_CHIP_THOR(bp))
 928                         bp->max_l2_ctx += bp->max_rx_em_flows;
 929                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 930                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 931         }
 932         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 933         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 934         if (bp->vf_resv_strategy >
 935             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 936                 bp->vf_resv_strategy =
 937                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 938
 939         HWRM_UNLOCK();
 940         return rc;
 941 }
 942
 943 int bnxt_hwrm_ver_get(struct bnxt *bp)
 944 {
 945         int rc = 0;
 946         struct hwrm_ver_get_input req = {.req_type = 0 };
 947         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 948         uint32_t fw_version;
 949         uint16_t max_resp_len;
 950         char type[RTE_MEMZONE_NAMESIZE];
 951         uint32_t dev_caps_cfg;
 952
 953         bp->max_req_len = HWRM_MAX_REQ_LEN;
 954         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 955
 956         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 957         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 958         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 959
 960         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 961
 962         if (bp->flags & BNXT_FLAG_FW_RESET)
 963                 HWRM_CHECK_RESULT_SILENT();
 964         else
 965                 HWRM_CHECK_RESULT();
 966
 967         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 968                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 969                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 970                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 971         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 972                      (resp->hwrm_fw_min_8b << 16) |
 973                      (resp->hwrm_fw_bld_8b << 8) |
 974                      resp->hwrm_fw_rsvd_8b;
 975         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 976                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 977
 978         fw_version = resp->hwrm_intf_maj_8b << 16;
 979         fw_version |= resp->hwrm_intf_min_8b << 8;
 980         fw_version |= resp->hwrm_intf_upd_8b;
 981         bp->hwrm_spec_code = fw_version;
 982
 983         /* def_req_timeout value is in milliseconds */
 984         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
 985         /* convert timeout to usec */
 986         bp->hwrm_cmd_timeout *= 1000;
 987         if (!bp->hwrm_cmd_timeout)
 988                 bp->hwrm_cmd_timeout = HWRM_CMD_TIMEOUT;
 989
 990         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 991                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 992                 rc = -EINVAL;
 993                 goto error;
 994         }
 995
 996         if (bp->max_req_len > resp->max_req_win_len) {
 997                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 998                 rc = -EINVAL;
 999         }
1000         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1001         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1002         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1003                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1004
1005         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1006         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1007
1008         if (bp->max_resp_len != max_resp_len) {
1009                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
1010                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1011                         bp->pdev->addr.devid, bp->pdev->addr.function);
1012
1013                 rte_free(bp->hwrm_cmd_resp_addr);
1014
1015                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1016                 if (bp->hwrm_cmd_resp_addr == NULL) {
1017                         rc = -ENOMEM;
1018                         goto error;
1019                 }
1020                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1021                 bp->hwrm_cmd_resp_dma_addr =
1022                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1023                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1024                         PMD_DRV_LOG(ERR,
1025                         "Unable to map response buffer to physical memory.\n");
1026                         rc = -ENOMEM;
1027                         goto error;
1028                 }
1029                 bp->max_resp_len = max_resp_len;
1030         }
1031
1032         if ((dev_caps_cfg &
1033                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1034             (dev_caps_cfg &
1035              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1036                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1037                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1038         }
1039
1040         if (((dev_caps_cfg &
1041               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1042              (dev_caps_cfg &
1043               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1044             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1045                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1046                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1047                         bp->pdev->addr.devid, bp->pdev->addr.function);
1048
1049                 rte_free(bp->hwrm_short_cmd_req_addr);
1050
1051                 bp->hwrm_short_cmd_req_addr =
1052                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1053                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1054                         rc = -ENOMEM;
1055                         goto error;
1056                 }
1057                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1058                 bp->hwrm_short_cmd_req_dma_addr =
1059                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1060                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1061                         rte_free(bp->hwrm_short_cmd_req_addr);
1062                         PMD_DRV_LOG(ERR,
1063                                 "Unable to map buffer to physical memory.\n");
1064                         rc = -ENOMEM;
1065                         goto error;
1066                 }
1067         }
1068         if (dev_caps_cfg &
1069             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1070                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1071                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1072         }
1073         if (dev_caps_cfg &
1074             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1075                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1076         if (dev_caps_cfg &
1077             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1078                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1079                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1080         }
1081
1082 error:
1083         HWRM_UNLOCK();
1084         return rc;
1085 }
1086
1087 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1088 {
1089         int rc;
1090         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1091         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1092
1093         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1094                 return 0;
1095
1096         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1097         req.flags = flags;
1098
1099         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1100
1101         HWRM_CHECK_RESULT();
1102         HWRM_UNLOCK();
1103
1104         return rc;
1105 }
1106
1107 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1108 {
1109         int rc = 0;
1110         struct hwrm_port_phy_cfg_input req = {0};
1111         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1112         uint32_t enables = 0;
1113
1114         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1115
1116         if (conf->link_up) {
1117                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1118                 if (bp->link_info.auto_mode && conf->link_speed) {
1119                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1120                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1121                 }
1122
1123                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1124                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1125                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1126                 /*
1127                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1128                  * any auto mode, even "none".
1129                  */
1130                 if (!conf->link_speed) {
1131                         /* No speeds specified. Enable AutoNeg - all speeds */
1132                         req.auto_mode =
1133                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1134                 }
1135                 /* AutoNeg - Advertise speeds specified. */
1136                 if (conf->auto_link_speed_mask &&
1137                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1138                         req.auto_mode =
1139                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1140                         req.auto_link_speed_mask =
1141                                 conf->auto_link_speed_mask;
1142                         enables |=
1143                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1144                 }
1145
1146                 req.auto_duplex = conf->duplex;
1147                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1148                 req.auto_pause = conf->auto_pause;
1149                 req.force_pause = conf->force_pause;
1150                 /* Set force_pause if there is no auto or if there is a force */
1151                 if (req.auto_pause && !req.force_pause)
1152                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1153                 else
1154                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1155
1156                 req.enables = rte_cpu_to_le_32(enables);
1157         } else {
1158                 req.flags =
1159                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1160                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1161         }
1162
1163         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1164
1165         HWRM_CHECK_RESULT();
1166         HWRM_UNLOCK();
1167
1168         return rc;
1169 }
1170
1171 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1172                                    struct bnxt_link_info *link_info)
1173 {
1174         int rc = 0;
1175         struct hwrm_port_phy_qcfg_input req = {0};
1176         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1177
1178         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1179
1180         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1181
1182         HWRM_CHECK_RESULT();
1183
1184         link_info->phy_link_status = resp->link;
1185         link_info->link_up =
1186                 (link_info->phy_link_status ==
1187                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1188         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1189         link_info->duplex = resp->duplex_cfg;
1190         link_info->pause = resp->pause;
1191         link_info->auto_pause = resp->auto_pause;
1192         link_info->force_pause = resp->force_pause;
1193         link_info->auto_mode = resp->auto_mode;
1194         link_info->phy_type = resp->phy_type;
1195         link_info->media_type = resp->media_type;
1196
1197         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1198         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1199         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1200         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1201         link_info->phy_ver[0] = resp->phy_maj;
1202         link_info->phy_ver[1] = resp->phy_min;
1203         link_info->phy_ver[2] = resp->phy_bld;
1204
1205         HWRM_UNLOCK();
1206
1207         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1208         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1209         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1210         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1211         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1212                     link_info->auto_link_speed_mask);
1213         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1214                     link_info->force_link_speed);
1215
1216         return rc;
1217 }
1218
1219 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1220 {
1221         int rc = 0;
1222         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1223         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1224         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1225         int i;
1226
1227 get_rx_info:
1228         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1229
1230         req.flags = rte_cpu_to_le_32(dir);
1231         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1232         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1233             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1234                 req.drv_qmap_cap =
1235                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1236         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1237
1238         HWRM_CHECK_RESULT();
1239
1240         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1241                 GET_TX_QUEUE_INFO(0);
1242                 GET_TX_QUEUE_INFO(1);
1243                 GET_TX_QUEUE_INFO(2);
1244                 GET_TX_QUEUE_INFO(3);
1245                 GET_TX_QUEUE_INFO(4);
1246                 GET_TX_QUEUE_INFO(5);
1247                 GET_TX_QUEUE_INFO(6);
1248                 GET_TX_QUEUE_INFO(7);
1249         } else  {
1250                 GET_RX_QUEUE_INFO(0);
1251                 GET_RX_QUEUE_INFO(1);
1252                 GET_RX_QUEUE_INFO(2);
1253                 GET_RX_QUEUE_INFO(3);
1254                 GET_RX_QUEUE_INFO(4);
1255                 GET_RX_QUEUE_INFO(5);
1256                 GET_RX_QUEUE_INFO(6);
1257                 GET_RX_QUEUE_INFO(7);
1258         }
1259
1260         HWRM_UNLOCK();
1261
1262         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1263                 goto done;
1264
1265         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1266                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1267         } else {
1268                 int j;
1269
1270                 /* iterate and find the COSq profile to use for Tx */
1271                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1272                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1273                                 if (bp->tx_cos_queue[i].id != 0xff)
1274                                         bp->tx_cosq_id[j++] =
1275                                                 bp->tx_cos_queue[i].id;
1276                         }
1277                 } else {
1278                         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1279                                 if (bp->tx_cos_queue[i].profile ==
1280                                         HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1281                                         bp->tx_cosq_id[0] =
1282                                                 bp->tx_cos_queue[i].id;
1283                                         break;
1284                                 }
1285                         }
1286                 }
1287         }
1288
1289         bp->max_tc = resp->max_configurable_queues;
1290         bp->max_lltc = resp->max_configurable_lossless_queues;
1291         if (bp->max_tc > BNXT_MAX_QUEUE)
1292                 bp->max_tc = BNXT_MAX_QUEUE;
1293         bp->max_q = bp->max_tc;
1294
1295         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1296                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1297                 goto get_rx_info;
1298         }
1299
1300 done:
1301         return rc;
1302 }
1303
1304 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1305                          struct bnxt_ring *ring,
1306                          uint32_t ring_type, uint32_t map_index,
1307                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1308                          uint16_t tx_cosq_id)
1309 {
1310         int rc = 0;
1311         uint32_t enables = 0;
1312         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1313         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1314         struct rte_mempool *mb_pool;
1315         uint16_t rx_buf_size;
1316
1317         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1318
1319         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1320         req.fbo = rte_cpu_to_le_32(0);
1321         /* Association of ring index with doorbell index */
1322         req.logical_id = rte_cpu_to_le_16(map_index);
1323         req.length = rte_cpu_to_le_32(ring->ring_size);
1324
1325         switch (ring_type) {
1326         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1327                 req.ring_type = ring_type;
1328                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1329                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1330                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1331                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1332                         enables |=
1333                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1334                 break;
1335         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1336                 req.ring_type = ring_type;
1337                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1338                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1339                 if (BNXT_CHIP_THOR(bp)) {
1340                         mb_pool = bp->rx_queues[0]->mb_pool;
1341                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1342                                       RTE_PKTMBUF_HEADROOM;
1343                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1344                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1345                         enables |=
1346                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1347                 }
1348                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1349                         enables |=
1350                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1351                 break;
1352         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1353                 req.ring_type = ring_type;
1354                 if (BNXT_HAS_NQ(bp)) {
1355                         /* Association of cp ring with nq */
1356                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1357                         enables |=
1358                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1359                 }
1360                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1361                 break;
1362         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1363                 req.ring_type = ring_type;
1364                 req.page_size = BNXT_PAGE_SHFT;
1365                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1366                 break;
1367         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1368                 req.ring_type = ring_type;
1369                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1370
1371                 mb_pool = bp->rx_queues[0]->mb_pool;
1372                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1373                               RTE_PKTMBUF_HEADROOM;
1374                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1375                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1376
1377                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1378                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1379                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1380                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1381                 break;
1382         default:
1383                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1384                         ring_type);
1385                 HWRM_UNLOCK();
1386                 return -EINVAL;
1387         }
1388         req.enables = rte_cpu_to_le_32(enables);
1389
1390         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1391
1392         if (rc || resp->error_code) {
1393                 if (rc == 0 && resp->error_code)
1394                         rc = rte_le_to_cpu_16(resp->error_code);
1395                 switch (ring_type) {
1396                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1397                         PMD_DRV_LOG(ERR,
1398                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1399                         HWRM_UNLOCK();
1400                         return rc;
1401                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1402                         PMD_DRV_LOG(ERR,
1403                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1404                         HWRM_UNLOCK();
1405                         return rc;
1406                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1407                         PMD_DRV_LOG(ERR,
1408                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1409                                     rc);
1410                         HWRM_UNLOCK();
1411                         return rc;
1412                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1413                         PMD_DRV_LOG(ERR,
1414                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1415                         HWRM_UNLOCK();
1416                         return rc;
1417                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1418                         PMD_DRV_LOG(ERR,
1419                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1420                         HWRM_UNLOCK();
1421                         return rc;
1422                 default:
1423                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1424                         HWRM_UNLOCK();
1425                         return rc;
1426                 }
1427         }
1428
1429         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1430         HWRM_UNLOCK();
1431         return rc;
1432 }
1433
1434 int bnxt_hwrm_ring_free(struct bnxt *bp,
1435                         struct bnxt_ring *ring, uint32_t ring_type)
1436 {
1437         int rc;
1438         struct hwrm_ring_free_input req = {.req_type = 0 };
1439         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1440
1441         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1442
1443         req.ring_type = ring_type;
1444         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1445
1446         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1447
1448         if (rc || resp->error_code) {
1449                 if (rc == 0 && resp->error_code)
1450                         rc = rte_le_to_cpu_16(resp->error_code);
1451                 HWRM_UNLOCK();
1452
1453                 switch (ring_type) {
1454                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1455                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1456                                 rc);
1457                         return rc;
1458                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1459                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1460                                 rc);
1461                         return rc;
1462                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1463                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1464                                 rc);
1465                         return rc;
1466                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1467                         PMD_DRV_LOG(ERR,
1468                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1469                         return rc;
1470                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1471                         PMD_DRV_LOG(ERR,
1472                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1473                         return rc;
1474                 default:
1475                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1476                         return rc;
1477                 }
1478         }
1479         HWRM_UNLOCK();
1480         return 0;
1481 }
1482
1483 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1484 {
1485         int rc = 0;
1486         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1487         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1488
1489         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1490
1491         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1492         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1493         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1494         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1495
1496         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1497
1498         HWRM_CHECK_RESULT();
1499
1500         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1501
1502         HWRM_UNLOCK();
1503
1504         return rc;
1505 }
1506
1507 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1508 {
1509         int rc;
1510         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1511         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1512
1513         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1514
1515         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1516
1517         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1518
1519         HWRM_CHECK_RESULT();
1520         HWRM_UNLOCK();
1521
1522         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1523         return rc;
1524 }
1525
1526 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1527 {
1528         int rc = 0;
1529         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1530         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1531
1532         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1533                 return rc;
1534
1535         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1536
1537         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1538
1539         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1540
1541         HWRM_CHECK_RESULT();
1542         HWRM_UNLOCK();
1543
1544         return rc;
1545 }
1546
1547 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1548                                 unsigned int idx __rte_unused)
1549 {
1550         int rc;
1551         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1552         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1553
1554         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1555
1556         req.update_period_ms = rte_cpu_to_le_32(0);
1557
1558         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1559
1560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1561
1562         HWRM_CHECK_RESULT();
1563
1564         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1565
1566         HWRM_UNLOCK();
1567
1568         return rc;
1569 }
1570
1571 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1572                                 unsigned int idx __rte_unused)
1573 {
1574         int rc;
1575         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1576         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1577
1578         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1579
1580         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1581
1582         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1583
1584         HWRM_CHECK_RESULT();
1585         HWRM_UNLOCK();
1586
1587         return rc;
1588 }
1589
1590 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1591 {
1592         int rc = 0, i, j;
1593         struct hwrm_vnic_alloc_input req = { 0 };
1594         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1595
1596         if (!BNXT_HAS_RING_GRPS(bp))
1597                 goto skip_ring_grps;
1598
1599         /* map ring groups to this vnic */
1600         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1601                 vnic->start_grp_id, vnic->end_grp_id);
1602         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1603                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1604
1605         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1606         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1607         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1608         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1609
1610 skip_ring_grps:
1611         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1612         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1613
1614         if (vnic->func_default)
1615                 req.flags =
1616                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1617         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1618
1619         HWRM_CHECK_RESULT();
1620
1621         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1622         HWRM_UNLOCK();
1623         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1624         return rc;
1625 }
1626
1627 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1628                                         struct bnxt_vnic_info *vnic,
1629                                         struct bnxt_plcmodes_cfg *pmode)
1630 {
1631         int rc = 0;
1632         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1633         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1634
1635         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1636
1637         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1638
1639         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1640
1641         HWRM_CHECK_RESULT();
1642
1643         pmode->flags = rte_le_to_cpu_32(resp->flags);
1644         /* dflt_vnic bit doesn't exist in the _cfg command */
1645         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1646         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1647         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1648         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1649
1650         HWRM_UNLOCK();
1651
1652         return rc;
1653 }
1654
1655 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1656                                        struct bnxt_vnic_info *vnic,
1657                                        struct bnxt_plcmodes_cfg *pmode)
1658 {
1659         int rc = 0;
1660         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1661         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1662
1663         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1664                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1665                 return rc;
1666         }
1667
1668         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1669
1670         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1671         req.flags = rte_cpu_to_le_32(pmode->flags);
1672         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1673         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1674         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1675         req.enables = rte_cpu_to_le_32(
1676             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1677             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1678             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1679         );
1680
1681         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1682
1683         HWRM_CHECK_RESULT();
1684         HWRM_UNLOCK();
1685
1686         return rc;
1687 }
1688
1689 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1690 {
1691         int rc = 0;
1692         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1693         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1694         struct bnxt_plcmodes_cfg pmodes = { 0 };
1695         uint32_t ctx_enable_flag = 0;
1696         uint32_t enables = 0;
1697
1698         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1699                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1700                 return rc;
1701         }
1702
1703         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1704         if (rc)
1705                 return rc;
1706
1707         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1708
1709         if (BNXT_CHIP_THOR(bp)) {
1710                 int dflt_rxq = vnic->start_grp_id;
1711                 struct bnxt_rx_ring_info *rxr;
1712                 struct bnxt_cp_ring_info *cpr;
1713                 struct bnxt_rx_queue *rxq;
1714                 int i;
1715
1716                 /*
1717                  * The first active receive ring is used as the VNIC
1718                  * default receive ring. If there are no active receive
1719                  * rings (all corresponding receive queues are stopped),
1720                  * the first receive ring is used.
1721                  */
1722                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1723                         rxq = bp->eth_dev->data->rx_queues[i];
1724                         if (rxq->rx_started) {
1725                                 dflt_rxq = i;
1726                                 break;
1727                         }
1728                 }
1729
1730                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1731                 rxr = rxq->rx_ring;
1732                 cpr = rxq->cp_ring;
1733
1734                 req.default_rx_ring_id =
1735                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1736                 req.default_cmpl_ring_id =
1737                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1738                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1739                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1740                 goto config_mru;
1741         }
1742
1743         /* Only RSS support for now TBD: COS & LB */
1744         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1745         if (vnic->lb_rule != 0xffff)
1746                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1747         if (vnic->cos_rule != 0xffff)
1748                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1749         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1750                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1751                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1752         }
1753         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1754                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1755                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1756         }
1757
1758         enables |= ctx_enable_flag;
1759         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1760         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1761         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1762         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1763
1764 config_mru:
1765         req.enables = rte_cpu_to_le_32(enables);
1766         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1767         req.mru = rte_cpu_to_le_16(vnic->mru);
1768         /* Configure default VNIC only once. */
1769         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1770                 req.flags |=
1771                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1772                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1773         }
1774         if (vnic->vlan_strip)
1775                 req.flags |=
1776                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1777         if (vnic->bd_stall)
1778                 req.flags |=
1779                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1780         if (vnic->roce_dual)
1781                 req.flags |= rte_cpu_to_le_32(
1782                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1783         if (vnic->roce_only)
1784                 req.flags |= rte_cpu_to_le_32(
1785                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1786         if (vnic->rss_dflt_cr)
1787                 req.flags |= rte_cpu_to_le_32(
1788                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1789
1790         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1791
1792         HWRM_CHECK_RESULT();
1793         HWRM_UNLOCK();
1794
1795         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1796
1797         return rc;
1798 }
1799
1800 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1801                 int16_t fw_vf_id)
1802 {
1803         int rc = 0;
1804         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1805         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1806
1807         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1808                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1809                 return rc;
1810         }
1811         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1812
1813         req.enables =
1814                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1815         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1816         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1817
1818         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1819
1820         HWRM_CHECK_RESULT();
1821
1822         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1823         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1824         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1825         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1826         vnic->mru = rte_le_to_cpu_16(resp->mru);
1827         vnic->func_default = rte_le_to_cpu_32(
1828                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1829         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1830                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1831         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1832                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1833         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1834                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1835         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1836                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1837         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1838                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1839
1840         HWRM_UNLOCK();
1841
1842         return rc;
1843 }
1844
1845 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1846                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1847 {
1848         int rc = 0;
1849         uint16_t ctx_id;
1850         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1851         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1852                                                 bp->hwrm_cmd_resp_addr;
1853
1854         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1855
1856         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1857         HWRM_CHECK_RESULT();
1858
1859         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1860         if (!BNXT_HAS_RING_GRPS(bp))
1861                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1862         else if (ctx_idx == 0)
1863                 vnic->rss_rule = ctx_id;
1864
1865         HWRM_UNLOCK();
1866
1867         return rc;
1868 }
1869
1870 static
1871 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1872                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1873 {
1874         int rc = 0;
1875         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1876         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1877                                                 bp->hwrm_cmd_resp_addr;
1878
1879         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1880                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1881                 return rc;
1882         }
1883         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1884
1885         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1886
1887         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1888
1889         HWRM_CHECK_RESULT();
1890         HWRM_UNLOCK();
1891
1892         return rc;
1893 }
1894
1895 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1896 {
1897         int rc = 0;
1898
1899         if (BNXT_CHIP_THOR(bp)) {
1900                 int j;
1901
1902                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1903                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1904                                                       vnic,
1905                                                       vnic->fw_grp_ids[j]);
1906                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1907                 }
1908                 vnic->num_lb_ctxts = 0;
1909         } else {
1910                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1911                 vnic->rss_rule = INVALID_HW_RING_ID;
1912         }
1913
1914         return rc;
1915 }
1916
1917 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1918 {
1919         int rc = 0;
1920         struct hwrm_vnic_free_input req = {.req_type = 0 };
1921         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1922
1923         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1924                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1925                 return rc;
1926         }
1927
1928         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1929
1930         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1931
1932         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1933
1934         HWRM_CHECK_RESULT();
1935         HWRM_UNLOCK();
1936
1937         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1938         /* Configure default VNIC again if necessary. */
1939         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1940                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1941
1942         return rc;
1943 }
1944
1945 static int
1946 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1947 {
1948         int i;
1949         int rc = 0;
1950         int nr_ctxs = vnic->num_lb_ctxts;
1951         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1952         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1953
1954         for (i = 0; i < nr_ctxs; i++) {
1955                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1956
1957                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1958                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1959                 req.hash_mode_flags = vnic->hash_mode;
1960
1961                 req.hash_key_tbl_addr =
1962                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1963
1964                 req.ring_grp_tbl_addr =
1965                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1966                                          i * HW_HASH_INDEX_SIZE);
1967                 req.ring_table_pair_index = i;
1968                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1969
1970                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1971                                             BNXT_USE_CHIMP_MB);
1972
1973                 HWRM_CHECK_RESULT();
1974                 HWRM_UNLOCK();
1975         }
1976
1977         return rc;
1978 }
1979
1980 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1981                            struct bnxt_vnic_info *vnic)
1982 {
1983         int rc = 0;
1984         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1985         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1986
1987         if (!vnic->rss_table)
1988                 return 0;
1989
1990         if (BNXT_CHIP_THOR(bp))
1991                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1992
1993         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1994
1995         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1996         req.hash_mode_flags = vnic->hash_mode;
1997
1998         req.ring_grp_tbl_addr =
1999             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2000         req.hash_key_tbl_addr =
2001             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2002         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2003         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2004
2005         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2006
2007         HWRM_CHECK_RESULT();
2008         HWRM_UNLOCK();
2009
2010         return rc;
2011 }
2012
2013 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2014                         struct bnxt_vnic_info *vnic)
2015 {
2016         int rc = 0;
2017         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2018         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2019         uint16_t size;
2020
2021         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2022                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2023                 return rc;
2024         }
2025
2026         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2027
2028         req.flags = rte_cpu_to_le_32(
2029                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2030
2031         req.enables = rte_cpu_to_le_32(
2032                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2033
2034         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2035         size -= RTE_PKTMBUF_HEADROOM;
2036         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2037
2038         req.jumbo_thresh = rte_cpu_to_le_16(size);
2039         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2040
2041         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2042
2043         HWRM_CHECK_RESULT();
2044         HWRM_UNLOCK();
2045
2046         return rc;
2047 }
2048
2049 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2050                         struct bnxt_vnic_info *vnic, bool enable)
2051 {
2052         int rc = 0;
2053         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2054         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2055
2056         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2057                 if (enable)
2058                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2059                 return -ENOTSUP;
2060         }
2061
2062         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2063                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2064                 return 0;
2065         }
2066
2067         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2068
2069         if (enable) {
2070                 req.enables = rte_cpu_to_le_32(
2071                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2072                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2073                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2074                 req.flags = rte_cpu_to_le_32(
2075                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2076                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2077                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2078                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2079                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2080                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2081                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2082                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2083                 req.min_agg_len = rte_cpu_to_le_32(512);
2084         }
2085         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2086
2087         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2088
2089         HWRM_CHECK_RESULT();
2090         HWRM_UNLOCK();
2091
2092         return rc;
2093 }
2094
2095 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2096 {
2097         struct hwrm_func_cfg_input req = {0};
2098         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2099         int rc;
2100
2101         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2102         req.enables = rte_cpu_to_le_32(
2103                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2104         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2105         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2106
2107         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2108
2109         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2110         HWRM_CHECK_RESULT();
2111         HWRM_UNLOCK();
2112
2113         bp->pf.vf_info[vf].random_mac = false;
2114
2115         return rc;
2116 }
2117
2118 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2119                                   uint64_t *dropped)
2120 {
2121         int rc = 0;
2122         struct hwrm_func_qstats_input req = {.req_type = 0};
2123         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2124
2125         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2126
2127         req.fid = rte_cpu_to_le_16(fid);
2128
2129         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2130
2131         HWRM_CHECK_RESULT();
2132
2133         if (dropped)
2134                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2135
2136         HWRM_UNLOCK();
2137
2138         return rc;
2139 }
2140
2141 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2142                           struct rte_eth_stats *stats)
2143 {
2144         int rc = 0;
2145         struct hwrm_func_qstats_input req = {.req_type = 0};
2146         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2147
2148         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2149
2150         req.fid = rte_cpu_to_le_16(fid);
2151
2152         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2153
2154         HWRM_CHECK_RESULT();
2155
2156         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2157         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2158         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2159         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2160         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2161         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2162
2163         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2164         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2165         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2166         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2167         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2168         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2169
2170         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2171         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2172         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2173
2174         HWRM_UNLOCK();
2175
2176         return rc;
2177 }
2178
2179 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2180 {
2181         int rc = 0;
2182         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2183         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2184
2185         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2186
2187         req.fid = rte_cpu_to_le_16(fid);
2188
2189         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2190
2191         HWRM_CHECK_RESULT();
2192         HWRM_UNLOCK();
2193
2194         return rc;
2195 }
2196
2197 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2198 {
2199         unsigned int i;
2200         int rc = 0;
2201
2202         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2203                 struct bnxt_tx_queue *txq;
2204                 struct bnxt_rx_queue *rxq;
2205                 struct bnxt_cp_ring_info *cpr;
2206
2207                 if (i >= bp->rx_cp_nr_rings) {
2208                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2209                         cpr = txq->cp_ring;
2210                 } else {
2211                         rxq = bp->rx_queues[i];
2212                         cpr = rxq->cp_ring;
2213                 }
2214
2215                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2216                 if (rc)
2217                         return rc;
2218         }
2219         return 0;
2220 }
2221
2222 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2223 {
2224         int rc;
2225         unsigned int i;
2226         struct bnxt_cp_ring_info *cpr;
2227
2228         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2229
2230                 if (i >= bp->rx_cp_nr_rings) {
2231                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2232                 } else {
2233                         cpr = bp->rx_queues[i]->cp_ring;
2234                         if (BNXT_HAS_RING_GRPS(bp))
2235                                 bp->grp_info[i].fw_stats_ctx = -1;
2236                 }
2237                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2238                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2239                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2240                         if (rc)
2241                                 return rc;
2242                 }
2243         }
2244         return 0;
2245 }
2246
2247 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2248 {
2249         unsigned int i;
2250         int rc = 0;
2251
2252         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2253                 struct bnxt_tx_queue *txq;
2254                 struct bnxt_rx_queue *rxq;
2255                 struct bnxt_cp_ring_info *cpr;
2256
2257                 if (i >= bp->rx_cp_nr_rings) {
2258                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2259                         cpr = txq->cp_ring;
2260                 } else {
2261                         rxq = bp->rx_queues[i];
2262                         cpr = rxq->cp_ring;
2263                 }
2264
2265                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2266
2267                 if (rc)
2268                         return rc;
2269         }
2270         return rc;
2271 }
2272
2273 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2274 {
2275         uint16_t idx;
2276         uint32_t rc = 0;
2277
2278         if (!BNXT_HAS_RING_GRPS(bp))
2279                 return 0;
2280
2281         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2282
2283                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2284                         continue;
2285
2286                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2287
2288                 if (rc)
2289                         return rc;
2290         }
2291         return rc;
2292 }
2293
2294 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2295 {
2296         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2297
2298         bnxt_hwrm_ring_free(bp, cp_ring,
2299                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2300         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2301         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2302                                      sizeof(*cpr->cp_desc_ring));
2303         cpr->cp_raw_cons = 0;
2304         cpr->valid = 0;
2305 }
2306
2307 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2308 {
2309         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2310
2311         bnxt_hwrm_ring_free(bp, cp_ring,
2312                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2313         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2314         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2315                         sizeof(*cpr->cp_desc_ring));
2316         cpr->cp_raw_cons = 0;
2317         cpr->valid = 0;
2318 }
2319
2320 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2321 {
2322         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2323         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2324         struct bnxt_ring *ring = rxr->rx_ring_struct;
2325         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2326
2327         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2328                 bnxt_hwrm_ring_free(bp, ring,
2329                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2330                 ring->fw_ring_id = INVALID_HW_RING_ID;
2331                 if (BNXT_HAS_RING_GRPS(bp))
2332                         bp->grp_info[queue_index].rx_fw_ring_id =
2333                                                         INVALID_HW_RING_ID;
2334                 memset(rxr->rx_desc_ring, 0,
2335                        rxr->rx_ring_struct->ring_size *
2336                        sizeof(*rxr->rx_desc_ring));
2337                 memset(rxr->rx_buf_ring, 0,
2338                        rxr->rx_ring_struct->ring_size *
2339                        sizeof(*rxr->rx_buf_ring));
2340                 rxr->rx_prod = 0;
2341         }
2342         ring = rxr->ag_ring_struct;
2343         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2344                 bnxt_hwrm_ring_free(bp, ring,
2345                                     BNXT_CHIP_THOR(bp) ?
2346                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2347                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2348                 ring->fw_ring_id = INVALID_HW_RING_ID;
2349                 memset(rxr->ag_buf_ring, 0,
2350                        rxr->ag_ring_struct->ring_size *
2351                        sizeof(*rxr->ag_buf_ring));
2352                 rxr->ag_prod = 0;
2353                 if (BNXT_HAS_RING_GRPS(bp))
2354                         bp->grp_info[queue_index].ag_fw_ring_id =
2355                                                         INVALID_HW_RING_ID;
2356         }
2357         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2358                 bnxt_free_cp_ring(bp, cpr);
2359
2360         if (BNXT_HAS_RING_GRPS(bp))
2361                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2362 }
2363
2364 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2365 {
2366         unsigned int i;
2367
2368         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2369                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2370                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2371                 struct bnxt_ring *ring = txr->tx_ring_struct;
2372                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2373
2374                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2375                         bnxt_hwrm_ring_free(bp, ring,
2376                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2377                         ring->fw_ring_id = INVALID_HW_RING_ID;
2378                         memset(txr->tx_desc_ring, 0,
2379                                         txr->tx_ring_struct->ring_size *
2380                                         sizeof(*txr->tx_desc_ring));
2381                         memset(txr->tx_buf_ring, 0,
2382                                         txr->tx_ring_struct->ring_size *
2383                                         sizeof(*txr->tx_buf_ring));
2384                         txr->tx_prod = 0;
2385                         txr->tx_cons = 0;
2386                 }
2387                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2388                         bnxt_free_cp_ring(bp, cpr);
2389                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2390                 }
2391         }
2392
2393         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2394                 bnxt_free_hwrm_rx_ring(bp, i);
2395
2396         return 0;
2397 }
2398
2399 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2400 {
2401         uint16_t i;
2402         uint32_t rc = 0;
2403
2404         if (!BNXT_HAS_RING_GRPS(bp))
2405                 return 0;
2406
2407         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2408                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2409                 if (rc)
2410                         return rc;
2411         }
2412         return rc;
2413 }
2414
2415 /*
2416  * HWRM utility functions
2417  */
2418
2419 void bnxt_free_hwrm_resources(struct bnxt *bp)
2420 {
2421         /* Release memzone */
2422         rte_free(bp->hwrm_cmd_resp_addr);
2423         rte_free(bp->hwrm_short_cmd_req_addr);
2424         bp->hwrm_cmd_resp_addr = NULL;
2425         bp->hwrm_short_cmd_req_addr = NULL;
2426         bp->hwrm_cmd_resp_dma_addr = 0;
2427         bp->hwrm_short_cmd_req_dma_addr = 0;
2428 }
2429
2430 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2431 {
2432         struct rte_pci_device *pdev = bp->pdev;
2433         char type[RTE_MEMZONE_NAMESIZE];
2434
2435         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2436                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2437         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2438         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2439         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2440         if (bp->hwrm_cmd_resp_addr == NULL)
2441                 return -ENOMEM;
2442         bp->hwrm_cmd_resp_dma_addr =
2443                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2444         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2445                 PMD_DRV_LOG(ERR,
2446                         "unable to map response address to physical memory\n");
2447                 return -ENOMEM;
2448         }
2449         rte_spinlock_init(&bp->hwrm_lock);
2450
2451         return 0;
2452 }
2453
2454 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2455 {
2456         struct bnxt_filter_info *filter;
2457         int rc = 0;
2458
2459         STAILQ_FOREACH(filter, &vnic->filter, next) {
2460                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2461                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2462                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2463                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2464                 else
2465                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2466                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2467                 bnxt_free_filter(bp, filter);
2468         }
2469         return rc;
2470 }
2471
2472 static int
2473 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2474 {
2475         struct bnxt_filter_info *filter;
2476         struct rte_flow *flow;
2477         int rc = 0;
2478
2479         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2480                 flow = STAILQ_FIRST(&vnic->flow_list);
2481                 filter = flow->filter;
2482                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2483                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2484                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2485                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2486                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2487                 else
2488                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2489
2490                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2491                 rte_free(flow);
2492         }
2493         return rc;
2494 }
2495
2496 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2497 {
2498         struct bnxt_filter_info *filter;
2499         int rc = 0;
2500
2501         STAILQ_FOREACH(filter, &vnic->filter, next) {
2502                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2503                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2504                                                      filter);
2505                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2506                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2507                                                          filter);
2508                 else
2509                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2510                                                      filter);
2511                 if (rc)
2512                         break;
2513         }
2514         return rc;
2515 }
2516
2517 void bnxt_free_tunnel_ports(struct bnxt *bp)
2518 {
2519         if (bp->vxlan_port_cnt)
2520                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2521                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2522         bp->vxlan_port = 0;
2523         if (bp->geneve_port_cnt)
2524                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2525                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2526         bp->geneve_port = 0;
2527 }
2528
2529 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2530 {
2531         int i;
2532
2533         if (bp->vnic_info == NULL)
2534                 return;
2535
2536         /*
2537          * Cleanup VNICs in reverse order, to make sure the L2 filter
2538          * from vnic0 is last to be cleaned up.
2539          */
2540         for (i = bp->max_vnics - 1; i >= 0; i--) {
2541                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2542
2543                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2544                         continue;
2545
2546                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2547
2548                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2549
2550                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2551
2552                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2553
2554                 bnxt_hwrm_vnic_free(bp, vnic);
2555
2556                 rte_free(vnic->fw_grp_ids);
2557         }
2558         /* Ring resources */
2559         bnxt_free_all_hwrm_rings(bp);
2560         bnxt_free_all_hwrm_ring_grps(bp);
2561         bnxt_free_all_hwrm_stat_ctxs(bp);
2562         bnxt_free_tunnel_ports(bp);
2563 }
2564
2565 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2566 {
2567         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2568
2569         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2570                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2571
2572         switch (conf_link_speed) {
2573         case ETH_LINK_SPEED_10M_HD:
2574         case ETH_LINK_SPEED_100M_HD:
2575                 /* FALLTHROUGH */
2576                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2577         }
2578         return hw_link_duplex;
2579 }
2580
2581 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2582 {
2583         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2584 }
2585
2586 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2587 {
2588         uint16_t eth_link_speed = 0;
2589
2590         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2591                 return ETH_LINK_SPEED_AUTONEG;
2592
2593         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2594         case ETH_LINK_SPEED_100M:
2595         case ETH_LINK_SPEED_100M_HD:
2596                 /* FALLTHROUGH */
2597                 eth_link_speed =
2598                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2599                 break;
2600         case ETH_LINK_SPEED_1G:
2601                 eth_link_speed =
2602                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2603                 break;
2604         case ETH_LINK_SPEED_2_5G:
2605                 eth_link_speed =
2606                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2607                 break;
2608         case ETH_LINK_SPEED_10G:
2609                 eth_link_speed =
2610                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2611                 break;
2612         case ETH_LINK_SPEED_20G:
2613                 eth_link_speed =
2614                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2615                 break;
2616         case ETH_LINK_SPEED_25G:
2617                 eth_link_speed =
2618                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2619                 break;
2620         case ETH_LINK_SPEED_40G:
2621                 eth_link_speed =
2622                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2623                 break;
2624         case ETH_LINK_SPEED_50G:
2625                 eth_link_speed =
2626                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2627                 break;
2628         case ETH_LINK_SPEED_100G:
2629                 eth_link_speed =
2630                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2631                 break;
2632         default:
2633                 PMD_DRV_LOG(ERR,
2634                         "Unsupported link speed %d; default to AUTO\n",
2635                         conf_link_speed);
2636                 break;
2637         }
2638         return eth_link_speed;
2639 }
2640
2641 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2642                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2643                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2644                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2645
2646 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2647 {
2648         uint32_t one_speed;
2649
2650         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2651                 return 0;
2652
2653         if (link_speed & ETH_LINK_SPEED_FIXED) {
2654                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2655
2656                 if (one_speed & (one_speed - 1)) {
2657                         PMD_DRV_LOG(ERR,
2658                                 "Invalid advertised speeds (%u) for port %u\n",
2659                                 link_speed, port_id);
2660                         return -EINVAL;
2661                 }
2662                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2663                         PMD_DRV_LOG(ERR,
2664                                 "Unsupported advertised speed (%u) for port %u\n",
2665                                 link_speed, port_id);
2666                         return -EINVAL;
2667                 }
2668         } else {
2669                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2670                         PMD_DRV_LOG(ERR,
2671                                 "Unsupported advertised speeds (%u) for port %u\n",
2672                                 link_speed, port_id);
2673                         return -EINVAL;
2674                 }
2675         }
2676         return 0;
2677 }
2678
2679 static uint16_t
2680 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2681 {
2682         uint16_t ret = 0;
2683
2684         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2685                 if (bp->link_info.support_speeds)
2686                         return bp->link_info.support_speeds;
2687                 link_speed = BNXT_SUPPORTED_SPEEDS;
2688         }
2689
2690         if (link_speed & ETH_LINK_SPEED_100M)
2691                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2692         if (link_speed & ETH_LINK_SPEED_100M_HD)
2693                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2694         if (link_speed & ETH_LINK_SPEED_1G)
2695                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2696         if (link_speed & ETH_LINK_SPEED_2_5G)
2697                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2698         if (link_speed & ETH_LINK_SPEED_10G)
2699                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2700         if (link_speed & ETH_LINK_SPEED_20G)
2701                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2702         if (link_speed & ETH_LINK_SPEED_25G)
2703                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2704         if (link_speed & ETH_LINK_SPEED_40G)
2705                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2706         if (link_speed & ETH_LINK_SPEED_50G)
2707                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2708         if (link_speed & ETH_LINK_SPEED_100G)
2709                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2710         return ret;
2711 }
2712
2713 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2714 {
2715         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2716
2717         switch (hw_link_speed) {
2718         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2719                 eth_link_speed = ETH_SPEED_NUM_100M;
2720                 break;
2721         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2722                 eth_link_speed = ETH_SPEED_NUM_1G;
2723                 break;
2724         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2725                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2726                 break;
2727         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2728                 eth_link_speed = ETH_SPEED_NUM_10G;
2729                 break;
2730         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2731                 eth_link_speed = ETH_SPEED_NUM_20G;
2732                 break;
2733         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2734                 eth_link_speed = ETH_SPEED_NUM_25G;
2735                 break;
2736         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2737                 eth_link_speed = ETH_SPEED_NUM_40G;
2738                 break;
2739         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2740                 eth_link_speed = ETH_SPEED_NUM_50G;
2741                 break;
2742         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2743                 eth_link_speed = ETH_SPEED_NUM_100G;
2744                 break;
2745         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2746         default:
2747                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2748                         hw_link_speed);
2749                 break;
2750         }
2751         return eth_link_speed;
2752 }
2753
2754 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2755 {
2756         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2757
2758         switch (hw_link_duplex) {
2759         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2760         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2761                 /* FALLTHROUGH */
2762                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2763                 break;
2764         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2765                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2766                 break;
2767         default:
2768                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2769                         hw_link_duplex);
2770                 break;
2771         }
2772         return eth_link_duplex;
2773 }
2774
2775 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2776 {
2777         int rc = 0;
2778         struct bnxt_link_info *link_info = &bp->link_info;
2779
2780         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2781         if (rc) {
2782                 PMD_DRV_LOG(ERR,
2783                         "Get link config failed with rc %d\n", rc);
2784                 goto exit;
2785         }
2786         if (link_info->link_speed)
2787                 link->link_speed =
2788                         bnxt_parse_hw_link_speed(link_info->link_speed);
2789         else
2790                 link->link_speed = ETH_SPEED_NUM_NONE;
2791         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2792         link->link_status = link_info->link_up;
2793         link->link_autoneg = link_info->auto_mode ==
2794                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2795                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2796 exit:
2797         return rc;
2798 }
2799
2800 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2801 {
2802         int rc = 0;
2803         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2804         struct bnxt_link_info link_req;
2805         uint16_t speed, autoneg;
2806
2807         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2808                 return 0;
2809
2810         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2811                         bp->eth_dev->data->port_id);
2812         if (rc)
2813                 goto error;
2814
2815         memset(&link_req, 0, sizeof(link_req));
2816         link_req.link_up = link_up;
2817         if (!link_up)
2818                 goto port_phy_cfg;
2819
2820         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2821         if (BNXT_CHIP_THOR(bp) &&
2822             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2823                 /* 40G is not supported as part of media auto detect.
2824                  * The speed should be forced and autoneg disabled
2825                  * to configure 40G speed.
2826                  */
2827                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2828                 autoneg = 0;
2829         }
2830
2831         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2832         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2833         /* Autoneg can be done only when the FW allows.
2834          * When user configures fixed speed of 40G and later changes to
2835          * any other speed, auto_link_speed/force_link_speed is still set
2836          * to 40G until link comes up at new speed.
2837          */
2838         if (autoneg == 1 &&
2839             !(!BNXT_CHIP_THOR(bp) &&
2840               (bp->link_info.auto_link_speed ||
2841                bp->link_info.force_link_speed))) {
2842                 link_req.phy_flags |=
2843                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2844                 link_req.auto_link_speed_mask =
2845                         bnxt_parse_eth_link_speed_mask(bp,
2846                                                        dev_conf->link_speeds);
2847         } else {
2848                 if (bp->link_info.phy_type ==
2849                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2850                     bp->link_info.phy_type ==
2851                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2852                     bp->link_info.media_type ==
2853                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2854                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2855                         return -EINVAL;
2856                 }
2857
2858                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2859                 /* If user wants a particular speed try that first. */
2860                 if (speed)
2861                         link_req.link_speed = speed;
2862                 else if (bp->link_info.force_link_speed)
2863                         link_req.link_speed = bp->link_info.force_link_speed;
2864                 else
2865                         link_req.link_speed = bp->link_info.auto_link_speed;
2866         }
2867         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2868         link_req.auto_pause = bp->link_info.auto_pause;
2869         link_req.force_pause = bp->link_info.force_pause;
2870
2871 port_phy_cfg:
2872         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2873         if (rc) {
2874                 PMD_DRV_LOG(ERR,
2875                         "Set link config failed with rc %d\n", rc);
2876         }
2877
2878 error:
2879         return rc;
2880 }
2881
2882 /* JIRA 22088 */
2883 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2884 {
2885         struct hwrm_func_qcfg_input req = {0};
2886         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2887         uint16_t flags;
2888         int rc = 0;
2889
2890         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2891         req.fid = rte_cpu_to_le_16(0xffff);
2892
2893         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2894
2895         HWRM_CHECK_RESULT();
2896
2897         /* Hard Coded.. 0xfff VLAN ID mask */
2898         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2899         flags = rte_le_to_cpu_16(resp->flags);
2900         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2901                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2902
2903         if (BNXT_VF(bp) &&
2904             !BNXT_VF_IS_TRUSTED(bp) &&
2905             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2906                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2907                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2908         } else if (BNXT_VF(bp) &&
2909                    BNXT_VF_IS_TRUSTED(bp) &&
2910                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2911                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2912                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2913         }
2914
2915         if (mtu)
2916                 *mtu = rte_le_to_cpu_16(resp->mtu);
2917
2918         switch (resp->port_partition_type) {
2919         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2920         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2921         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2922                 /* FALLTHROUGH */
2923                 bp->port_partition_type = resp->port_partition_type;
2924                 break;
2925         default:
2926                 bp->port_partition_type = 0;
2927                 break;
2928         }
2929
2930         HWRM_UNLOCK();
2931
2932         return rc;
2933 }
2934
2935 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2936                                    struct hwrm_func_qcaps_output *qcaps)
2937 {
2938         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2939         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2940                sizeof(qcaps->mac_address));
2941         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2942         qcaps->max_rx_rings = fcfg->num_rx_rings;
2943         qcaps->max_tx_rings = fcfg->num_tx_rings;
2944         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2945         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2946         qcaps->max_vfs = 0;
2947         qcaps->first_vf_id = 0;
2948         qcaps->max_vnics = fcfg->num_vnics;
2949         qcaps->max_decap_records = 0;
2950         qcaps->max_encap_records = 0;
2951         qcaps->max_tx_wm_flows = 0;
2952         qcaps->max_tx_em_flows = 0;
2953         qcaps->max_rx_wm_flows = 0;
2954         qcaps->max_rx_em_flows = 0;
2955         qcaps->max_flow_id = 0;
2956         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2957         qcaps->max_sp_tx_rings = 0;
2958         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2959 }
2960
2961 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2962 {
2963         struct hwrm_func_cfg_input req = {0};
2964         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2965         uint32_t enables;
2966         int rc;
2967
2968         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2969                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2970                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2971                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2972                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2973                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2974                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2975                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2976                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2977
2978         if (BNXT_HAS_RING_GRPS(bp)) {
2979                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2980                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2981         } else if (BNXT_HAS_NQ(bp)) {
2982                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2983                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2984         }
2985
2986         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2987         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2988         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
2989         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2990         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2991         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2992         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2993         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2994         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2995         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2996         req.fid = rte_cpu_to_le_16(0xffff);
2997         req.enables = rte_cpu_to_le_32(enables);
2998
2999         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3000
3001         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3002
3003         HWRM_CHECK_RESULT();
3004         HWRM_UNLOCK();
3005
3006         return rc;
3007 }
3008
3009 static void populate_vf_func_cfg_req(struct bnxt *bp,
3010                                      struct hwrm_func_cfg_input *req,
3011                                      int num_vfs)
3012 {
3013         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3014                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3015                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3016                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3017                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3018                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3019                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3020                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3021                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3022                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3023
3024         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3025                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3026                                     BNXT_NUM_VLANS);
3027         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3028         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3029                                                 (num_vfs + 1));
3030         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3031         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3032                                                (num_vfs + 1));
3033         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3034         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3035         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3036         /* TODO: For now, do not support VMDq/RFS on VFs. */
3037         req->num_vnics = rte_cpu_to_le_16(1);
3038         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3039                                                  (num_vfs + 1));
3040 }
3041
3042 static void add_random_mac_if_needed(struct bnxt *bp,
3043                                      struct hwrm_func_cfg_input *cfg_req,
3044                                      int vf)
3045 {
3046         struct rte_ether_addr mac;
3047
3048         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3049                 return;
3050
3051         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3052                 cfg_req->enables |=
3053                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3054                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3055                 bp->pf.vf_info[vf].random_mac = true;
3056         } else {
3057                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3058                         RTE_ETHER_ADDR_LEN);
3059         }
3060 }
3061
3062 static void reserve_resources_from_vf(struct bnxt *bp,
3063                                       struct hwrm_func_cfg_input *cfg_req,
3064                                       int vf)
3065 {
3066         struct hwrm_func_qcaps_input req = {0};
3067         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3068         int rc;
3069
3070         /* Get the actual allocated values now */
3071         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3072         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3073         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3074
3075         if (rc) {
3076                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3077                 copy_func_cfg_to_qcaps(cfg_req, resp);
3078         } else if (resp->error_code) {
3079                 rc = rte_le_to_cpu_16(resp->error_code);
3080                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3081                 copy_func_cfg_to_qcaps(cfg_req, resp);
3082         }
3083
3084         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3085         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3086         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3087         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3088         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3089         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3090         /*
3091          * TODO: While not supporting VMDq with VFs, max_vnics is always
3092          * forced to 1 in this case
3093          */
3094         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3095         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3096
3097         HWRM_UNLOCK();
3098 }
3099
3100 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3101 {
3102         struct hwrm_func_qcfg_input req = {0};
3103         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3104         int rc;
3105
3106         /* Check for zero MAC address */
3107         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3108         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3109         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3110         HWRM_CHECK_RESULT();
3111         rc = rte_le_to_cpu_16(resp->vlan);
3112
3113         HWRM_UNLOCK();
3114
3115         return rc;
3116 }
3117
3118 static int update_pf_resource_max(struct bnxt *bp)
3119 {
3120         struct hwrm_func_qcfg_input req = {0};
3121         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3122         int rc;
3123
3124         /* And copy the allocated numbers into the pf struct */
3125         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3126         req.fid = rte_cpu_to_le_16(0xffff);
3127         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3128         HWRM_CHECK_RESULT();
3129
3130         /* Only TX ring value reflects actual allocation? TODO */
3131         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3132         bp->pf.evb_mode = resp->evb_mode;
3133
3134         HWRM_UNLOCK();
3135
3136         return rc;
3137 }
3138
3139 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3140 {
3141         int rc;
3142
3143         if (!BNXT_PF(bp)) {
3144                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3145                 return -EINVAL;
3146         }
3147
3148         rc = bnxt_hwrm_func_qcaps(bp);
3149         if (rc)
3150                 return rc;
3151
3152         bp->pf.func_cfg_flags &=
3153                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3154                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3155         bp->pf.func_cfg_flags |=
3156                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3157         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3158         rc = __bnxt_hwrm_func_qcaps(bp);
3159         return rc;
3160 }
3161
3162 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3163 {
3164         struct hwrm_func_cfg_input req = {0};
3165         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3166         int i;
3167         size_t sz;
3168         int rc = 0;
3169         size_t req_buf_sz;
3170
3171         if (!BNXT_PF(bp)) {
3172                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3173                 return -EINVAL;
3174         }
3175
3176         rc = bnxt_hwrm_func_qcaps(bp);
3177
3178         if (rc)
3179                 return rc;
3180
3181         bp->pf.active_vfs = num_vfs;
3182
3183         /*
3184          * First, configure the PF to only use one TX ring.  This ensures that
3185          * there are enough rings for all VFs.
3186          *
3187          * If we don't do this, when we call func_alloc() later, we will lock
3188          * extra rings to the PF that won't be available during func_cfg() of
3189          * the VFs.
3190          *
3191          * This has been fixed with firmware versions above 20.6.54
3192          */
3193         bp->pf.func_cfg_flags &=
3194                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3195                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3196         bp->pf.func_cfg_flags |=
3197                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3198         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3199         if (rc)
3200                 return rc;
3201
3202         /*
3203          * Now, create and register a buffer to hold forwarded VF requests
3204          */
3205         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3206         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3207                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3208         if (bp->pf.vf_req_buf == NULL) {
3209                 rc = -ENOMEM;
3210                 goto error_free;
3211         }
3212         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3213                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3214         for (i = 0; i < num_vfs; i++)
3215                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3216                                         (i * HWRM_MAX_REQ_LEN);
3217
3218         rc = bnxt_hwrm_func_buf_rgtr(bp);
3219         if (rc)
3220                 goto error_free;
3221
3222         populate_vf_func_cfg_req(bp, &req, num_vfs);
3223
3224         bp->pf.active_vfs = 0;
3225         for (i = 0; i < num_vfs; i++) {
3226                 add_random_mac_if_needed(bp, &req, i);
3227
3228                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3229                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3230                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3231                 rc = bnxt_hwrm_send_message(bp,
3232                                             &req,
3233                                             sizeof(req),
3234                                             BNXT_USE_CHIMP_MB);
3235
3236                 /* Clear enable flag for next pass */
3237                 req.enables &= ~rte_cpu_to_le_32(
3238                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3239
3240                 if (rc || resp->error_code) {
3241                         PMD_DRV_LOG(ERR,
3242                                 "Failed to initizlie VF %d\n", i);
3243                         PMD_DRV_LOG(ERR,
3244                                 "Not all VFs available. (%d, %d)\n",
3245                                 rc, resp->error_code);
3246                         HWRM_UNLOCK();
3247                         break;
3248                 }
3249
3250                 HWRM_UNLOCK();
3251
3252                 reserve_resources_from_vf(bp, &req, i);
3253                 bp->pf.active_vfs++;
3254                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3255         }
3256
3257         /*
3258          * Now configure the PF to use "the rest" of the resources
3259          * We're using STD_TX_RING_MODE here though which will limit the TX
3260          * rings.  This will allow QoS to function properly.  Not setting this
3261          * will cause PF rings to break bandwidth settings.
3262          */
3263         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3264         if (rc)
3265                 goto error_free;
3266
3267         rc = update_pf_resource_max(bp);
3268         if (rc)
3269                 goto error_free;
3270
3271         return rc;
3272
3273 error_free:
3274         bnxt_hwrm_func_buf_unrgtr(bp);
3275         return rc;
3276 }
3277
3278 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3279 {
3280         struct hwrm_func_cfg_input req = {0};
3281         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3282         int rc;
3283
3284         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3285
3286         req.fid = rte_cpu_to_le_16(0xffff);
3287         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3288         req.evb_mode = bp->pf.evb_mode;
3289
3290         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3291         HWRM_CHECK_RESULT();
3292         HWRM_UNLOCK();
3293
3294         return rc;
3295 }
3296
3297 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3298                                 uint8_t tunnel_type)
3299 {
3300         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3301         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3302         int rc = 0;
3303
3304         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3305         req.tunnel_type = tunnel_type;
3306         req.tunnel_dst_port_val = port;
3307         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3308         HWRM_CHECK_RESULT();
3309
3310         switch (tunnel_type) {
3311         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3312                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3313                 bp->vxlan_port = port;
3314                 break;
3315         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3316                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3317                 bp->geneve_port = port;
3318                 break;
3319         default:
3320                 break;
3321         }
3322
3323         HWRM_UNLOCK();
3324
3325         return rc;
3326 }
3327
3328 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3329                                 uint8_t tunnel_type)
3330 {
3331         struct hwrm_tunnel_dst_port_free_input req = {0};
3332         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3333         int rc = 0;
3334
3335         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3336
3337         req.tunnel_type = tunnel_type;
3338         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3339         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3340
3341         HWRM_CHECK_RESULT();
3342         HWRM_UNLOCK();
3343
3344         return rc;
3345 }
3346
3347 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3348                                         uint32_t flags)
3349 {
3350         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3351         struct hwrm_func_cfg_input req = {0};
3352         int rc;
3353
3354         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3355
3356         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3357         req.flags = rte_cpu_to_le_32(flags);
3358         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3359
3360         HWRM_CHECK_RESULT();
3361         HWRM_UNLOCK();
3362
3363         return rc;
3364 }
3365
3366 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3367 {
3368         uint32_t *flag = flagp;
3369
3370         vnic->flags = *flag;
3371 }
3372
3373 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3374 {
3375         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3376 }
3377
3378 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3379 {
3380         int rc = 0;
3381         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3382         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3383
3384         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3385
3386         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3387         req.req_buf_page_size = rte_cpu_to_le_16(
3388                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3389         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3390         req.req_buf_page_addr0 =
3391                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3392         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3393                 PMD_DRV_LOG(ERR,
3394                         "unable to map buffer address to physical memory\n");
3395                 return -ENOMEM;
3396         }
3397
3398         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3399
3400         HWRM_CHECK_RESULT();
3401         HWRM_UNLOCK();
3402
3403         return rc;
3404 }
3405
3406 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3407 {
3408         int rc = 0;
3409         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3410         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3411
3412         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3413                 return 0;
3414
3415         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3416
3417         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3418
3419         HWRM_CHECK_RESULT();
3420         HWRM_UNLOCK();
3421
3422         return rc;
3423 }
3424
3425 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3426 {
3427         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3428         struct hwrm_func_cfg_input req = {0};
3429         int rc;
3430
3431         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3432
3433         req.fid = rte_cpu_to_le_16(0xffff);
3434         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3435         req.enables = rte_cpu_to_le_32(
3436                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3437         req.async_event_cr = rte_cpu_to_le_16(
3438                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3439         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3440
3441         HWRM_CHECK_RESULT();
3442         HWRM_UNLOCK();
3443
3444         return rc;
3445 }
3446
3447 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3448 {
3449         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3450         struct hwrm_func_vf_cfg_input req = {0};
3451         int rc;
3452
3453         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3454
3455         req.enables = rte_cpu_to_le_32(
3456                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3457         req.async_event_cr = rte_cpu_to_le_16(
3458                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3459         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3460
3461         HWRM_CHECK_RESULT();
3462         HWRM_UNLOCK();
3463
3464         return rc;
3465 }
3466
3467 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3468 {
3469         struct hwrm_func_cfg_input req = {0};
3470         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3471         uint16_t dflt_vlan, fid;
3472         uint32_t func_cfg_flags;
3473         int rc = 0;
3474
3475         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3476
3477         if (is_vf) {
3478                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3479                 fid = bp->pf.vf_info[vf].fid;
3480                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3481         } else {
3482                 fid = rte_cpu_to_le_16(0xffff);
3483                 func_cfg_flags = bp->pf.func_cfg_flags;
3484                 dflt_vlan = bp->vlan;
3485         }
3486
3487         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3488         req.fid = rte_cpu_to_le_16(fid);
3489         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3490         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3491
3492         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3493
3494         HWRM_CHECK_RESULT();
3495         HWRM_UNLOCK();
3496
3497         return rc;
3498 }
3499
3500 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3501                         uint16_t max_bw, uint16_t enables)
3502 {
3503         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3504         struct hwrm_func_cfg_input req = {0};
3505         int rc;
3506
3507         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3508
3509         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3510         req.enables |= rte_cpu_to_le_32(enables);
3511         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3512         req.max_bw = rte_cpu_to_le_32(max_bw);
3513         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3514
3515         HWRM_CHECK_RESULT();
3516         HWRM_UNLOCK();
3517
3518         return rc;
3519 }
3520
3521 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3522 {
3523         struct hwrm_func_cfg_input req = {0};
3524         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3525         int rc = 0;
3526
3527         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3528
3529         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3530         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3531         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3532         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3533
3534         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3535
3536         HWRM_CHECK_RESULT();
3537         HWRM_UNLOCK();
3538
3539         return rc;
3540 }
3541
3542 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3543 {
3544         int rc;
3545
3546         if (BNXT_PF(bp))
3547                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3548         else
3549                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3550
3551         return rc;
3552 }
3553
3554 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3555                               void *encaped, size_t ec_size)
3556 {
3557         int rc = 0;
3558         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3559         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3560
3561         if (ec_size > sizeof(req.encap_request))
3562                 return -1;
3563
3564         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3565
3566         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3567         memcpy(req.encap_request, encaped, ec_size);
3568
3569         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3570
3571         HWRM_CHECK_RESULT();
3572         HWRM_UNLOCK();
3573
3574         return rc;
3575 }
3576
3577 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3578                                        struct rte_ether_addr *mac)
3579 {
3580         struct hwrm_func_qcfg_input req = {0};
3581         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3582         int rc;
3583
3584         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3585
3586         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3587         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3588
3589         HWRM_CHECK_RESULT();
3590
3591         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3592
3593         HWRM_UNLOCK();
3594
3595         return rc;
3596 }
3597
3598 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3599                             void *encaped, size_t ec_size)
3600 {
3601         int rc = 0;
3602         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3603         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3604
3605         if (ec_size > sizeof(req.encap_request))
3606                 return -1;
3607
3608         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3609
3610         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3611         memcpy(req.encap_request, encaped, ec_size);
3612
3613         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3614
3615         HWRM_CHECK_RESULT();
3616         HWRM_UNLOCK();
3617
3618         return rc;
3619 }
3620
3621 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3622                          struct rte_eth_stats *stats, uint8_t rx)
3623 {
3624         int rc = 0;
3625         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3626         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3627
3628         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3629
3630         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3631
3632         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3633
3634         HWRM_CHECK_RESULT();
3635
3636         if (rx) {
3637                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3638                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3639                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3640                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3641                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3642                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3643                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3644                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3645         } else {
3646                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3647                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3648                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3649                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3650                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3651                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3652         }
3653
3654         HWRM_UNLOCK();
3655
3656         return rc;
3657 }
3658
3659 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3660 {
3661         struct hwrm_port_qstats_input req = {0};
3662         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3663         struct bnxt_pf_info *pf = &bp->pf;
3664         int rc;
3665
3666         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3667
3668         req.port_id = rte_cpu_to_le_16(pf->port_id);
3669         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3670         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3671         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3672
3673         HWRM_CHECK_RESULT();
3674         HWRM_UNLOCK();
3675
3676         return rc;
3677 }
3678
3679 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3680 {
3681         struct hwrm_port_clr_stats_input req = {0};
3682         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3683         struct bnxt_pf_info *pf = &bp->pf;
3684         int rc;
3685
3686         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3687         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3688             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3689                 return 0;
3690
3691         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3692
3693         req.port_id = rte_cpu_to_le_16(pf->port_id);
3694         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3695
3696         HWRM_CHECK_RESULT();
3697         HWRM_UNLOCK();
3698
3699         return rc;
3700 }
3701
3702 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3703 {
3704         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3705         struct hwrm_port_led_qcaps_input req = {0};
3706         int rc;
3707
3708         if (BNXT_VF(bp))
3709                 return 0;
3710
3711         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3712         req.port_id = bp->pf.port_id;
3713         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3714
3715         HWRM_CHECK_RESULT();
3716
3717         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3718                 unsigned int i;
3719
3720                 bp->num_leds = resp->num_leds;
3721                 memcpy(bp->leds, &resp->led0_id,
3722                         sizeof(bp->leds[0]) * bp->num_leds);
3723                 for (i = 0; i < bp->num_leds; i++) {
3724                         struct bnxt_led_info *led = &bp->leds[i];
3725
3726                         uint16_t caps = led->led_state_caps;
3727
3728                         if (!led->led_group_id ||
3729                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3730                                 bp->num_leds = 0;
3731                                 break;
3732                         }
3733                 }
3734         }
3735
3736         HWRM_UNLOCK();
3737
3738         return rc;
3739 }
3740
3741 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3742 {
3743         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3744         struct hwrm_port_led_cfg_input req = {0};
3745         struct bnxt_led_cfg *led_cfg;
3746         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3747         uint16_t duration = 0;
3748         int rc, i;
3749
3750         if (!bp->num_leds || BNXT_VF(bp))
3751                 return -EOPNOTSUPP;
3752
3753         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3754
3755         if (led_on) {
3756                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3757                 duration = rte_cpu_to_le_16(500);
3758         }
3759         req.port_id = bp->pf.port_id;
3760         req.num_leds = bp->num_leds;
3761         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3762         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3763                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3764                 led_cfg->led_id = bp->leds[i].led_id;
3765                 led_cfg->led_state = led_state;
3766                 led_cfg->led_blink_on = duration;
3767                 led_cfg->led_blink_off = duration;
3768                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3769         }
3770
3771         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3772
3773         HWRM_CHECK_RESULT();
3774         HWRM_UNLOCK();
3775
3776         return rc;
3777 }
3778
3779 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3780                                uint32_t *length)
3781 {
3782         int rc;
3783         struct hwrm_nvm_get_dir_info_input req = {0};
3784         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3785
3786         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3787
3788         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3789
3790         HWRM_CHECK_RESULT();
3791
3792         *entries = rte_le_to_cpu_32(resp->entries);
3793         *length = rte_le_to_cpu_32(resp->entry_length);
3794
3795         HWRM_UNLOCK();
3796         return rc;
3797 }
3798
3799 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3800 {
3801         int rc;
3802         uint32_t dir_entries;
3803         uint32_t entry_length;
3804         uint8_t *buf;
3805         size_t buflen;
3806         rte_iova_t dma_handle;
3807         struct hwrm_nvm_get_dir_entries_input req = {0};
3808         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3809
3810         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3811         if (rc != 0)
3812                 return rc;
3813
3814         *data++ = dir_entries;
3815         *data++ = entry_length;
3816         len -= 2;
3817         memset(data, 0xff, len);
3818
3819         buflen = dir_entries * entry_length;
3820         buf = rte_malloc("nvm_dir", buflen, 0);
3821         rte_mem_lock_page(buf);
3822         if (buf == NULL)
3823                 return -ENOMEM;
3824         dma_handle = rte_mem_virt2iova(buf);
3825         if (dma_handle == RTE_BAD_IOVA) {
3826                 PMD_DRV_LOG(ERR,
3827                         "unable to map response address to physical memory\n");
3828                 return -ENOMEM;
3829         }
3830         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3831         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3832         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3833
3834         if (rc == 0)
3835                 memcpy(data, buf, len > buflen ? buflen : len);
3836
3837         rte_free(buf);
3838         HWRM_CHECK_RESULT();
3839         HWRM_UNLOCK();
3840
3841         return rc;
3842 }
3843
3844 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3845                              uint32_t offset, uint32_t length,
3846                              uint8_t *data)
3847 {
3848         int rc;
3849         uint8_t *buf;
3850         rte_iova_t dma_handle;
3851         struct hwrm_nvm_read_input req = {0};
3852         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3853
3854         buf = rte_malloc("nvm_item", length, 0);
3855         rte_mem_lock_page(buf);
3856         if (!buf)
3857                 return -ENOMEM;
3858
3859         dma_handle = rte_mem_virt2iova(buf);
3860         if (dma_handle == RTE_BAD_IOVA) {
3861                 PMD_DRV_LOG(ERR,
3862                         "unable to map response address to physical memory\n");
3863                 return -ENOMEM;
3864         }
3865         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3866         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3867         req.dir_idx = rte_cpu_to_le_16(index);
3868         req.offset = rte_cpu_to_le_32(offset);
3869         req.len = rte_cpu_to_le_32(length);
3870         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3871         if (rc == 0)
3872                 memcpy(data, buf, length);
3873
3874         rte_free(buf);
3875         HWRM_CHECK_RESULT();
3876         HWRM_UNLOCK();
3877
3878         return rc;
3879 }
3880
3881 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3882 {
3883         int rc;
3884         struct hwrm_nvm_erase_dir_entry_input req = {0};
3885         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3886
3887         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3888         req.dir_idx = rte_cpu_to_le_16(index);
3889         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3890         HWRM_CHECK_RESULT();
3891         HWRM_UNLOCK();
3892
3893         return rc;
3894 }
3895
3896
3897 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3898                           uint16_t dir_ordinal, uint16_t dir_ext,
3899                           uint16_t dir_attr, const uint8_t *data,
3900                           size_t data_len)
3901 {
3902         int rc;
3903         struct hwrm_nvm_write_input req = {0};
3904         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3905         rte_iova_t dma_handle;
3906         uint8_t *buf;
3907
3908         buf = rte_malloc("nvm_write", data_len, 0);
3909         rte_mem_lock_page(buf);
3910         if (!buf)
3911                 return -ENOMEM;
3912
3913         dma_handle = rte_mem_virt2iova(buf);
3914         if (dma_handle == RTE_BAD_IOVA) {
3915                 PMD_DRV_LOG(ERR,
3916                         "unable to map response address to physical memory\n");
3917                 return -ENOMEM;
3918         }
3919         memcpy(buf, data, data_len);
3920
3921         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3922
3923         req.dir_type = rte_cpu_to_le_16(dir_type);
3924         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3925         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3926         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3927         req.dir_data_length = rte_cpu_to_le_32(data_len);
3928         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3929
3930         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3931
3932         rte_free(buf);
3933         HWRM_CHECK_RESULT();
3934         HWRM_UNLOCK();
3935
3936         return rc;
3937 }
3938
3939 static void
3940 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3941 {
3942         uint32_t *count = cbdata;
3943
3944         *count = *count + 1;
3945 }
3946
3947 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3948                                      struct bnxt_vnic_info *vnic __rte_unused)
3949 {
3950         return 0;
3951 }
3952
3953 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3954 {
3955         uint32_t count = 0;
3956
3957         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3958             &count, bnxt_vnic_count_hwrm_stub);
3959
3960         return count;
3961 }
3962
3963 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3964                                         uint16_t *vnic_ids)
3965 {
3966         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3967         struct hwrm_func_vf_vnic_ids_query_output *resp =
3968                                                 bp->hwrm_cmd_resp_addr;
3969         int rc;
3970
3971         /* First query all VNIC ids */
3972         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3973
3974         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3975         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3976         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3977
3978         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3979                 HWRM_UNLOCK();
3980                 PMD_DRV_LOG(ERR,
3981                 "unable to map VNIC ID table address to physical memory\n");
3982                 return -ENOMEM;
3983         }
3984         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3985         HWRM_CHECK_RESULT();
3986         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3987
3988         HWRM_UNLOCK();
3989
3990         return rc;
3991 }
3992
3993 /*
3994  * This function queries the VNIC IDs  for a specified VF. It then calls
3995  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3996  * Then it calls the hwrm_cb function to program this new vnic configuration.
3997  */
3998 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3999         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4000         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4001 {
4002         struct bnxt_vnic_info vnic;
4003         int rc = 0;
4004         int i, num_vnic_ids;
4005         uint16_t *vnic_ids;
4006         size_t vnic_id_sz;
4007         size_t sz;
4008
4009         /* First query all VNIC ids */
4010         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4011         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4012                         RTE_CACHE_LINE_SIZE);
4013         if (vnic_ids == NULL)
4014                 return -ENOMEM;
4015
4016         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4017                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4018
4019         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4020
4021         if (num_vnic_ids < 0)
4022                 return num_vnic_ids;
4023
4024         /* Retrieve VNIC, update bd_stall then update */
4025
4026         for (i = 0; i < num_vnic_ids; i++) {
4027                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4028                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4029                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4030                 if (rc)
4031                         break;
4032                 if (vnic.mru <= 4)      /* Indicates unallocated */
4033                         continue;
4034
4035                 vnic_cb(&vnic, cbdata);
4036
4037                 rc = hwrm_cb(bp, &vnic);
4038                 if (rc)
4039                         break;
4040         }
4041
4042         rte_free(vnic_ids);
4043
4044         return rc;
4045 }
4046
4047 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4048                                               bool on)
4049 {
4050         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4051         struct hwrm_func_cfg_input req = {0};
4052         int rc;
4053
4054         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4055
4056         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4057         req.enables |= rte_cpu_to_le_32(
4058                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4059         req.vlan_antispoof_mode = on ?
4060                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4061                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4062         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4063
4064         HWRM_CHECK_RESULT();
4065         HWRM_UNLOCK();
4066
4067         return rc;
4068 }
4069
4070 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4071 {
4072         struct bnxt_vnic_info vnic;
4073         uint16_t *vnic_ids;
4074         size_t vnic_id_sz;
4075         int num_vnic_ids, i;
4076         size_t sz;
4077         int rc;
4078
4079         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4080         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4081                         RTE_CACHE_LINE_SIZE);
4082         if (vnic_ids == NULL)
4083                 return -ENOMEM;
4084
4085         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4086                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4087
4088         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4089         if (rc <= 0)
4090                 goto exit;
4091         num_vnic_ids = rc;
4092
4093         /*
4094          * Loop through to find the default VNIC ID.
4095          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4096          * by sending the hwrm_func_qcfg command to the firmware.
4097          */
4098         for (i = 0; i < num_vnic_ids; i++) {
4099                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4100                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4101                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4102                                         bp->pf.first_vf_id + vf);
4103                 if (rc)
4104                         goto exit;
4105                 if (vnic.func_default) {
4106                         rte_free(vnic_ids);
4107                         return vnic.fw_vnic_id;
4108                 }
4109         }
4110         /* Could not find a default VNIC. */
4111         PMD_DRV_LOG(ERR, "No default VNIC\n");
4112 exit:
4113         rte_free(vnic_ids);
4114         return rc;
4115 }
4116
4117 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4118                          uint16_t dst_id,
4119                          struct bnxt_filter_info *filter)
4120 {
4121         int rc = 0;
4122         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4123         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4124         uint32_t enables = 0;
4125
4126         if (filter->fw_em_filter_id != UINT64_MAX)
4127                 bnxt_hwrm_clear_em_filter(bp, filter);
4128
4129         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4130
4131         req.flags = rte_cpu_to_le_32(filter->flags);
4132
4133         enables = filter->enables |
4134               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4135         req.dst_id = rte_cpu_to_le_16(dst_id);
4136
4137         if (filter->ip_addr_type) {
4138                 req.ip_addr_type = filter->ip_addr_type;
4139                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4140         }
4141         if (enables &
4142             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4143                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4144         if (enables &
4145             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4146                 memcpy(req.src_macaddr, filter->src_macaddr,
4147                        RTE_ETHER_ADDR_LEN);
4148         if (enables &
4149             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4150                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4151                        RTE_ETHER_ADDR_LEN);
4152         if (enables &
4153             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4154                 req.ovlan_vid = filter->l2_ovlan;
4155         if (enables &
4156             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4157                 req.ivlan_vid = filter->l2_ivlan;
4158         if (enables &
4159             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4160                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4161         if (enables &
4162             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4163                 req.ip_protocol = filter->ip_protocol;
4164         if (enables &
4165             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4166                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4167         if (enables &
4168             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4169                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4170         if (enables &
4171             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4172                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4173         if (enables &
4174             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4175                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4176         if (enables &
4177             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4178                 req.mirror_vnic_id = filter->mirror_vnic_id;
4179
4180         req.enables = rte_cpu_to_le_32(enables);
4181
4182         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4183
4184         HWRM_CHECK_RESULT();
4185
4186         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4187         HWRM_UNLOCK();
4188
4189         return rc;
4190 }
4191
4192 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4193 {
4194         int rc = 0;
4195         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4196         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4197
4198         if (filter->fw_em_filter_id == UINT64_MAX)
4199                 return 0;
4200
4201         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4202
4203         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4204
4205         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4206
4207         HWRM_CHECK_RESULT();
4208         HWRM_UNLOCK();
4209
4210         filter->fw_em_filter_id = UINT64_MAX;
4211         filter->fw_l2_filter_id = UINT64_MAX;
4212
4213         return 0;
4214 }
4215
4216 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4217                          uint16_t dst_id,
4218                          struct bnxt_filter_info *filter)
4219 {
4220         int rc = 0;
4221         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4222         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4223                                                 bp->hwrm_cmd_resp_addr;
4224         uint32_t enables = 0;
4225
4226         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4227                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4228
4229         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4230
4231         req.flags = rte_cpu_to_le_32(filter->flags);
4232
4233         enables = filter->enables |
4234               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4235         req.dst_id = rte_cpu_to_le_16(dst_id);
4236
4237         if (filter->ip_addr_type) {
4238                 req.ip_addr_type = filter->ip_addr_type;
4239                 enables |=
4240                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4241         }
4242         if (enables &
4243             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4244                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4245         if (enables &
4246             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4247                 memcpy(req.src_macaddr, filter->src_macaddr,
4248                        RTE_ETHER_ADDR_LEN);
4249         if (enables &
4250             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4251                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4252         if (enables &
4253             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4254                 req.ip_protocol = filter->ip_protocol;
4255         if (enables &
4256             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4257                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4258         if (enables &
4259             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4260                 req.src_ipaddr_mask[0] =
4261                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4262         if (enables &
4263             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4264                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4265         if (enables &
4266             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4267                 req.dst_ipaddr_mask[0] =
4268                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4269         if (enables &
4270             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4271                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4272         if (enables &
4273             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4274                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4275         if (enables &
4276             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4277                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4278         if (enables &
4279             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4280                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4281         if (enables &
4282             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4283                 req.mirror_vnic_id = filter->mirror_vnic_id;
4284
4285         req.enables = rte_cpu_to_le_32(enables);
4286
4287         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4288
4289         HWRM_CHECK_RESULT();
4290
4291         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4292         HWRM_UNLOCK();
4293
4294         return rc;
4295 }
4296
4297 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4298                                 struct bnxt_filter_info *filter)
4299 {
4300         int rc = 0;
4301         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4302         struct hwrm_cfa_ntuple_filter_free_output *resp =
4303                                                 bp->hwrm_cmd_resp_addr;
4304
4305         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4306                 return 0;
4307
4308         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4309
4310         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4311
4312         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4313
4314         HWRM_CHECK_RESULT();
4315         HWRM_UNLOCK();
4316
4317         filter->fw_ntuple_filter_id = UINT64_MAX;
4318
4319         return 0;
4320 }
4321
4322 static int
4323 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4324 {
4325         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4326         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4327         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4328         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4329         uint16_t *ring_tbl = vnic->rss_table;
4330         int nr_ctxs = vnic->num_lb_ctxts;
4331         int max_rings = bp->rx_nr_rings;
4332         int i, j, k, cnt;
4333         int rc = 0;
4334
4335         for (i = 0, k = 0; i < nr_ctxs; i++) {
4336                 struct bnxt_rx_ring_info *rxr;
4337                 struct bnxt_cp_ring_info *cpr;
4338
4339                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4340
4341                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4342                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4343                 req.hash_mode_flags = vnic->hash_mode;
4344
4345                 req.ring_grp_tbl_addr =
4346                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4347                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4348                                      2 * sizeof(*ring_tbl));
4349                 req.hash_key_tbl_addr =
4350                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4351
4352                 req.ring_table_pair_index = i;
4353                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4354
4355                 for (j = 0; j < 64; j++) {
4356                         uint16_t ring_id;
4357
4358                         /* Find next active ring. */
4359                         for (cnt = 0; cnt < max_rings; cnt++) {
4360                                 if (rx_queue_state[k] !=
4361                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4362                                         break;
4363                                 if (++k == max_rings)
4364                                         k = 0;
4365                         }
4366
4367                         /* Return if no rings are active. */
4368                         if (cnt == max_rings) {
4369                                 HWRM_UNLOCK();
4370                                 return 0;
4371                         }
4372
4373                         /* Add rx/cp ring pair to RSS table. */
4374                         rxr = rxqs[k]->rx_ring;
4375                         cpr = rxqs[k]->cp_ring;
4376
4377                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4378                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4379                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4380                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4381
4382                         if (++k == max_rings)
4383                                 k = 0;
4384                 }
4385                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4386                                             BNXT_USE_CHIMP_MB);
4387
4388                 HWRM_CHECK_RESULT();
4389                 HWRM_UNLOCK();
4390         }
4391
4392         return rc;
4393 }
4394
4395 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4396 {
4397         unsigned int rss_idx, fw_idx, i;
4398
4399         if (!(vnic->rss_table && vnic->hash_type))
4400                 return 0;
4401
4402         if (BNXT_CHIP_THOR(bp))
4403                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4404
4405         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4406                 return 0;
4407
4408         if (vnic->rss_table && vnic->hash_type) {
4409                 /*
4410                  * Fill the RSS hash & redirection table with
4411                  * ring group ids for all VNICs
4412                  */
4413                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4414                         rss_idx++, fw_idx++) {
4415                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4416                                 fw_idx %= bp->rx_cp_nr_rings;
4417                                 if (vnic->fw_grp_ids[fw_idx] !=
4418                                     INVALID_HW_RING_ID)
4419                                         break;
4420                                 fw_idx++;
4421                         }
4422                         if (i == bp->rx_cp_nr_rings)
4423                                 return 0;
4424                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4425                 }
4426                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4427         }
4428
4429         return 0;
4430 }
4431
4432 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4433         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4434 {
4435         uint16_t flags;
4436
4437         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4438
4439         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4440         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4441
4442         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4443         req->num_cmpl_dma_aggr_during_int =
4444                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4445
4446         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4447
4448         /* min timer set to 1/2 of interrupt timer */
4449         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4450
4451         /* buf timer set to 1/4 of interrupt timer */
4452         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4453
4454         req->cmpl_aggr_dma_tmr_during_int =
4455                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4456
4457         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4458                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4459         req->flags = rte_cpu_to_le_16(flags);
4460 }
4461
4462 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4463                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4464 {
4465         struct hwrm_ring_aggint_qcaps_input req = {0};
4466         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4467         uint32_t enables;
4468         uint16_t flags;
4469         int rc;
4470
4471         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4472         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4473         HWRM_CHECK_RESULT();
4474
4475         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4476         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4477
4478         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4479                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4480         agg_req->flags = rte_cpu_to_le_16(flags);
4481         enables =
4482          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4483          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4484         agg_req->enables = rte_cpu_to_le_32(enables);
4485
4486         HWRM_UNLOCK();
4487         return rc;
4488 }
4489
4490 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4491                         struct bnxt_coal *coal, uint16_t ring_id)
4492 {
4493         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4494         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4495                                                 bp->hwrm_cmd_resp_addr;
4496         int rc;
4497
4498         /* Set ring coalesce parameters only for 100G NICs */
4499         if (BNXT_CHIP_THOR(bp)) {
4500                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4501                         return -1;
4502         } else if (bnxt_stratus_device(bp)) {
4503                 bnxt_hwrm_set_coal_params(coal, &req);
4504         } else {
4505                 return 0;
4506         }
4507
4508         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4509         req.ring_id = rte_cpu_to_le_16(ring_id);
4510         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4511         HWRM_CHECK_RESULT();
4512         HWRM_UNLOCK();
4513         return 0;
4514 }
4515
4516 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4517 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4518 {
4519         struct hwrm_func_backing_store_qcaps_input req = {0};
4520         struct hwrm_func_backing_store_qcaps_output *resp =
4521                 bp->hwrm_cmd_resp_addr;
4522         struct bnxt_ctx_pg_info *ctx_pg;
4523         struct bnxt_ctx_mem_info *ctx;
4524         int total_alloc_len;
4525         int rc, i;
4526
4527         if (!BNXT_CHIP_THOR(bp) ||
4528             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4529             BNXT_VF(bp) ||
4530             bp->ctx)
4531                 return 0;
4532
4533         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4534         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4535         HWRM_CHECK_RESULT_SILENT();
4536
4537         total_alloc_len = sizeof(*ctx);
4538         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4539                           RTE_CACHE_LINE_SIZE);
4540         if (!ctx) {
4541                 rc = -ENOMEM;
4542                 goto ctx_err;
4543         }
4544
4545         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4546                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4547                             RTE_CACHE_LINE_SIZE);
4548         if (!ctx_pg) {
4549                 rc = -ENOMEM;
4550                 goto ctx_err;
4551         }
4552         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4553                 ctx->tqm_mem[i] = ctx_pg;
4554
4555         bp->ctx = ctx;
4556         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4557         ctx->qp_min_qp1_entries =
4558                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4559         ctx->qp_max_l2_entries =
4560                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4561         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4562         ctx->srq_max_l2_entries =
4563                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4564         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4565         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4566         ctx->cq_max_l2_entries =
4567                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4568         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4569         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4570         ctx->vnic_max_vnic_entries =
4571                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4572         ctx->vnic_max_ring_table_entries =
4573                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4574         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4575         ctx->stat_max_entries =
4576                 rte_le_to_cpu_32(resp->stat_max_entries);
4577         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4578         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4579         ctx->tqm_min_entries_per_ring =
4580                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4581         ctx->tqm_max_entries_per_ring =
4582                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4583         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4584         if (!ctx->tqm_entries_multiple)
4585                 ctx->tqm_entries_multiple = 1;
4586         ctx->mrav_max_entries =
4587                 rte_le_to_cpu_32(resp->mrav_max_entries);
4588         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4589         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4590         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4591 ctx_err:
4592         HWRM_UNLOCK();
4593         return rc;
4594 }
4595
4596 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4597 {
4598         struct hwrm_func_backing_store_cfg_input req = {0};
4599         struct hwrm_func_backing_store_cfg_output *resp =
4600                 bp->hwrm_cmd_resp_addr;
4601         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4602         struct bnxt_ctx_pg_info *ctx_pg;
4603         uint32_t *num_entries;
4604         uint64_t *pg_dir;
4605         uint8_t *pg_attr;
4606         uint32_t ena;
4607         int i, rc;
4608
4609         if (!ctx)
4610                 return 0;
4611
4612         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4613         req.enables = rte_cpu_to_le_32(enables);
4614
4615         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4616                 ctx_pg = &ctx->qp_mem;
4617                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4618                 req.qp_num_qp1_entries =
4619                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4620                 req.qp_num_l2_entries =
4621                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4622                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4623                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4624                                       &req.qpc_pg_size_qpc_lvl,
4625                                       &req.qpc_page_dir);
4626         }
4627
4628         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4629                 ctx_pg = &ctx->srq_mem;
4630                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4631                 req.srq_num_l2_entries =
4632                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4633                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4634                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4635                                       &req.srq_pg_size_srq_lvl,
4636                                       &req.srq_page_dir);
4637         }
4638
4639         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4640                 ctx_pg = &ctx->cq_mem;
4641                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4642                 req.cq_num_l2_entries =
4643                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4644                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4645                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4646                                       &req.cq_pg_size_cq_lvl,
4647                                       &req.cq_page_dir);
4648         }
4649
4650         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4651                 ctx_pg = &ctx->vnic_mem;
4652                 req.vnic_num_vnic_entries =
4653                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4654                 req.vnic_num_ring_table_entries =
4655                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4656                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4657                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4658                                       &req.vnic_pg_size_vnic_lvl,
4659                                       &req.vnic_page_dir);
4660         }
4661
4662         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4663                 ctx_pg = &ctx->stat_mem;
4664                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4665                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4666                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4667                                       &req.stat_pg_size_stat_lvl,
4668                                       &req.stat_page_dir);
4669         }
4670
4671         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4672         num_entries = &req.tqm_sp_num_entries;
4673         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4674         pg_dir = &req.tqm_sp_page_dir;
4675         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4676         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4677                 if (!(enables & ena))
4678                         continue;
4679
4680                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4681
4682                 ctx_pg = ctx->tqm_mem[i];
4683                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4684                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4685         }
4686
4687         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4688         HWRM_CHECK_RESULT();
4689         HWRM_UNLOCK();
4690
4691         return rc;
4692 }
4693
4694 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4695 {
4696         struct hwrm_port_qstats_ext_input req = {0};
4697         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4698         struct bnxt_pf_info *pf = &bp->pf;
4699         int rc;
4700
4701         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4702               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4703                 return 0;
4704
4705         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4706
4707         req.port_id = rte_cpu_to_le_16(pf->port_id);
4708         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4709                 req.tx_stat_host_addr =
4710                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4711                 req.tx_stat_size =
4712                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4713         }
4714         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4715                 req.rx_stat_host_addr =
4716                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4717                 req.rx_stat_size =
4718                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4719         }
4720         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4721
4722         if (rc) {
4723                 bp->fw_rx_port_stats_ext_size = 0;
4724                 bp->fw_tx_port_stats_ext_size = 0;
4725         } else {
4726                 bp->fw_rx_port_stats_ext_size =
4727                         rte_le_to_cpu_16(resp->rx_stat_size);
4728                 bp->fw_tx_port_stats_ext_size =
4729                         rte_le_to_cpu_16(resp->tx_stat_size);
4730         }
4731
4732         HWRM_CHECK_RESULT();
4733         HWRM_UNLOCK();
4734
4735         return rc;
4736 }
4737
4738 int
4739 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4740 {
4741         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4742         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4743                 bp->hwrm_cmd_resp_addr;
4744         int rc = 0;
4745
4746         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4747         req.tunnel_type = type;
4748         req.dest_fid = bp->fw_fid;
4749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4750         HWRM_CHECK_RESULT();
4751
4752         HWRM_UNLOCK();
4753
4754         return rc;
4755 }
4756
4757 int
4758 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4759 {
4760         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4761         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4762                 bp->hwrm_cmd_resp_addr;
4763         int rc = 0;
4764
4765         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4766         req.tunnel_type = type;
4767         req.dest_fid = bp->fw_fid;
4768         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4769         HWRM_CHECK_RESULT();
4770
4771         HWRM_UNLOCK();
4772
4773         return rc;
4774 }
4775
4776 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4777 {
4778         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4779         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4780                 bp->hwrm_cmd_resp_addr;
4781         int rc = 0;
4782
4783         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4784         req.src_fid = bp->fw_fid;
4785         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4786         HWRM_CHECK_RESULT();
4787
4788         if (type)
4789                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4790
4791         HWRM_UNLOCK();
4792
4793         return rc;
4794 }
4795
4796 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4797                                    uint16_t *dst_fid)
4798 {
4799         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4800         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4801                 bp->hwrm_cmd_resp_addr;
4802         int rc = 0;
4803
4804         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4805         req.src_fid = bp->fw_fid;
4806         req.tunnel_type = tun_type;
4807         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4808         HWRM_CHECK_RESULT();
4809
4810         if (dst_fid)
4811                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4812
4813         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4814
4815         HWRM_UNLOCK();
4816
4817         return rc;
4818 }
4819
4820 int bnxt_hwrm_set_mac(struct bnxt *bp)
4821 {
4822         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4823         struct hwrm_func_vf_cfg_input req = {0};
4824         int rc = 0;
4825
4826         if (!BNXT_VF(bp))
4827                 return 0;
4828
4829         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4830
4831         req.enables =
4832                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4833         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4834
4835         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4836
4837         HWRM_CHECK_RESULT();
4838
4839         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4840         HWRM_UNLOCK();
4841
4842         return rc;
4843 }
4844
4845 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4846 {
4847         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4848         struct hwrm_func_drv_if_change_input req = {0};
4849         uint32_t flags;
4850         int rc;
4851
4852         if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4853                 return 0;
4854
4855         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4856          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4857          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4858          */
4859         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4860                 return 0;
4861
4862         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4863
4864         if (up)
4865                 req.flags =
4866                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4867
4868         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4869
4870         HWRM_CHECK_RESULT();
4871         flags = rte_le_to_cpu_32(resp->flags);
4872         HWRM_UNLOCK();
4873
4874         if (!up)
4875                 return 0;
4876
4877         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4878                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4879                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4880         }
4881
4882         return 0;
4883 }
4884
4885 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4886 {
4887         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4888         struct bnxt_error_recovery_info *info = bp->recovery_info;
4889         struct hwrm_error_recovery_qcfg_input req = {0};
4890         uint32_t flags = 0;
4891         unsigned int i;
4892         int rc;
4893
4894         /* Older FW does not have error recovery support */
4895         if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4896                 return 0;
4897
4898         if (!info) {
4899                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4900                                    sizeof(*info), 0);
4901                 bp->recovery_info = info;
4902                 if (info == NULL)
4903                         return -ENOMEM;
4904         } else {
4905                 memset(info, 0, sizeof(*info));
4906         }
4907
4908         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4909
4910         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4911
4912         HWRM_CHECK_RESULT();
4913
4914         flags = rte_le_to_cpu_32(resp->flags);
4915         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4916                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4917         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4918                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4919
4920         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4921             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4922                 rc = -EINVAL;
4923                 goto err;
4924         }
4925
4926         /* FW returned values are in units of 100msec */
4927         info->driver_polling_freq =
4928                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4929         info->master_func_wait_period =
4930                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4931         info->normal_func_wait_period =
4932                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4933         info->master_func_wait_period_after_reset =
4934                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4935         info->max_bailout_time_after_reset =
4936                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4937         info->status_regs[BNXT_FW_STATUS_REG] =
4938                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4939         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4940                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4941         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4942                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4943         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4944                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4945         info->reg_array_cnt =
4946                 rte_le_to_cpu_32(resp->reg_array_cnt);
4947
4948         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4949                 rc = -EINVAL;
4950                 goto err;
4951         }
4952
4953         for (i = 0; i < info->reg_array_cnt; i++) {
4954                 info->reset_reg[i] =
4955                         rte_le_to_cpu_32(resp->reset_reg[i]);
4956                 info->reset_reg_val[i] =
4957                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4958                 info->delay_after_reset[i] =
4959                         resp->delay_after_reset[i];
4960         }
4961 err:
4962         HWRM_UNLOCK();
4963
4964         /* Map the FW status registers */
4965         if (!rc)
4966                 rc = bnxt_map_fw_health_status_regs(bp);
4967
4968         if (rc) {
4969                 rte_free(bp->recovery_info);
4970                 bp->recovery_info = NULL;
4971         }
4972         return rc;
4973 }
4974
4975 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4976 {
4977         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4978         struct hwrm_fw_reset_input req = {0};
4979         int rc;
4980
4981         if (!BNXT_PF(bp))
4982                 return -EOPNOTSUPP;
4983
4984         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4985
4986         req.embedded_proc_type =
4987                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4988         req.selfrst_status =
4989                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4990         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4991
4992         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4993                                     BNXT_USE_KONG(bp));
4994
4995         HWRM_CHECK_RESULT();
4996         HWRM_UNLOCK();
4997
4998         return rc;
4999 }
5000
5001 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5002 {
5003         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5004         struct hwrm_port_ts_query_input req = {0};
5005         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5006         uint32_t flags = 0;
5007         int rc;
5008
5009         if (!ptp)
5010                 return 0;
5011
5012         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5013
5014         switch (path) {
5015         case BNXT_PTP_FLAGS_PATH_TX:
5016                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5017                 break;
5018         case BNXT_PTP_FLAGS_PATH_RX:
5019                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5020                 break;
5021         case BNXT_PTP_FLAGS_CURRENT_TIME:
5022                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5023                 break;
5024         }
5025
5026         req.flags = rte_cpu_to_le_32(flags);
5027         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5028
5029         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5030
5031         HWRM_CHECK_RESULT();
5032
5033         if (timestamp) {
5034                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5035                 *timestamp |=
5036                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5037         }
5038         HWRM_UNLOCK();
5039
5040         return rc;
5041 }
5042
5043 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5044 {
5045         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5046                                         bp->hwrm_cmd_resp_addr;
5047         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5048         uint32_t flags = 0;
5049         int rc = 0;
5050
5051         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5052                 return rc;
5053
5054         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5055                 PMD_DRV_LOG(DEBUG,
5056                             "Not a PF or trusted VF. Command not supported\n");
5057                 return 0;
5058         }
5059
5060         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5061         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5062
5063         HWRM_CHECK_RESULT();
5064         flags = rte_le_to_cpu_32(resp->flags);
5065         HWRM_UNLOCK();
5066
5067         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5068                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5069                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5070         }
5071
5072         return rc;
5073 }