1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(void *) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages > 1) {
69 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
71 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
76 * HWRM Functions (sent to HWRM)
77 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
78 * HWRM command times out, or a negative error code if the HWRM
79 * command was failed by the FW.
82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
83 uint32_t msg_len, bool use_kong_mb)
86 struct input *req = msg;
87 struct output *resp = bp->hwrm_cmd_resp_addr;
91 uint16_t max_req_len = bp->max_req_len;
92 struct hwrm_short_input short_input = { 0 };
93 uint16_t bar_offset = use_kong_mb ?
94 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
95 uint16_t mb_trigger_offset = use_kong_mb ?
96 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
99 /* Do not send HWRM commands to firmware in error state */
100 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
103 timeout = bp->hwrm_cmd_timeout;
105 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
106 msg_len > bp->max_req_len) {
107 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
109 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
110 memcpy(short_cmd_req, req, msg_len);
112 short_input.req_type = rte_cpu_to_le_16(req->req_type);
113 short_input.signature = rte_cpu_to_le_16(
114 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
115 short_input.size = rte_cpu_to_le_16(msg_len);
116 short_input.req_addr =
117 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
119 data = (uint32_t *)&short_input;
120 msg_len = sizeof(short_input);
122 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
125 /* Write request msg to hwrm channel */
126 for (i = 0; i < msg_len; i += 4) {
127 bar = (uint8_t *)bp->bar0 + bar_offset + i;
128 rte_write32(*data, bar);
132 /* Zero the rest of the request space */
133 for (; i < max_req_len; i += 4) {
134 bar = (uint8_t *)bp->bar0 + bar_offset + i;
138 /* Ring channel doorbell */
139 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
142 * Make sure the channel doorbell ring command complete before
143 * reading the response to avoid getting stale or invalid
148 /* Poll for the valid bit */
149 for (i = 0; i < timeout; i++) {
150 /* Sanity check on the resp->resp_len */
152 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
153 /* Last byte of resp contains the valid key */
154 valid = (uint8_t *)resp + resp->resp_len - 1;
155 if (*valid == HWRM_RESP_VALID_KEY)
162 /* Suppress VER_GET timeout messages during reset recovery */
163 if (bp->flags & BNXT_FLAG_FW_RESET &&
164 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
167 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
175 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
176 * spinlock, and does initial processing.
178 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
179 * releases the spinlock only if it returns. If the regular int return codes
180 * are not used by the function, HWRM_CHECK_RESULT() should not be used
181 * directly, rather it should be copied and modified to suit the function.
183 * HWRM_UNLOCK() must be called after all response processing is completed.
185 #define HWRM_PREP(req, type, kong) do { \
186 rte_spinlock_lock(&bp->hwrm_lock); \
187 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
188 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
189 req.cmpl_ring = rte_cpu_to_le_16(-1); \
190 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
191 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
192 req.target_id = rte_cpu_to_le_16(0xffff); \
193 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
196 #define HWRM_CHECK_RESULT_SILENT() do {\
198 rte_spinlock_unlock(&bp->hwrm_lock); \
201 if (resp->error_code) { \
202 rc = rte_le_to_cpu_16(resp->error_code); \
203 rte_spinlock_unlock(&bp->hwrm_lock); \
208 #define HWRM_CHECK_RESULT() do {\
210 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
211 rte_spinlock_unlock(&bp->hwrm_lock); \
212 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
214 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
216 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
218 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
224 if (resp->error_code) { \
225 rc = rte_le_to_cpu_16(resp->error_code); \
226 if (resp->resp_len >= 16) { \
227 struct hwrm_err_output *tmp_hwrm_err_op = \
230 "error %d:%d:%08x:%04x\n", \
231 rc, tmp_hwrm_err_op->cmd_err, \
233 tmp_hwrm_err_op->opaque_0), \
235 tmp_hwrm_err_op->opaque_1)); \
237 PMD_DRV_LOG(ERR, "error %d\n", rc); \
239 rte_spinlock_unlock(&bp->hwrm_lock); \
240 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
242 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
244 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
246 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
254 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
256 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
259 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
260 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
262 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
263 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
266 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
274 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
275 struct bnxt_vnic_info *vnic,
277 struct bnxt_vlan_table_entry *vlan_table)
280 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
281 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
284 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
287 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
288 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
290 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
291 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
292 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
293 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
295 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
296 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
298 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
299 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
300 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
301 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
302 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
303 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
306 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
307 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
308 req.vlan_tag_tbl_addr =
309 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
310 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
312 req.mask = rte_cpu_to_le_32(mask);
314 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
322 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
324 struct bnxt_vlan_antispoof_table_entry *vlan_table)
327 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
328 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
329 bp->hwrm_cmd_resp_addr;
332 * Older HWRM versions did not support this command, and the set_rx_mask
333 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
334 * removed from set_rx_mask call, and this command was added.
336 * This command is also present from 1.7.8.11 and higher,
339 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
340 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
341 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
346 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
347 req.fid = rte_cpu_to_le_16(fid);
349 req.vlan_tag_mask_tbl_addr =
350 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
351 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
353 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
361 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
362 struct bnxt_filter_info *filter)
365 struct bnxt_filter_info *l2_filter = filter;
366 struct bnxt_vnic_info *vnic = NULL;
367 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
368 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
370 if (filter->fw_l2_filter_id == UINT64_MAX)
373 if (filter->matching_l2_fltr_ptr)
374 l2_filter = filter->matching_l2_fltr_ptr;
376 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
377 filter, l2_filter, l2_filter->l2_ref_cnt);
379 if (l2_filter->l2_ref_cnt == 0)
382 if (l2_filter->l2_ref_cnt > 0)
383 l2_filter->l2_ref_cnt--;
385 if (l2_filter->l2_ref_cnt > 0)
388 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
390 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
392 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
397 filter->fw_l2_filter_id = UINT64_MAX;
398 if (l2_filter->l2_ref_cnt == 0) {
399 vnic = l2_filter->vnic;
401 STAILQ_REMOVE(&vnic->filter, l2_filter,
402 bnxt_filter_info, next);
403 bnxt_free_filter(bp, l2_filter);
410 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
412 struct bnxt_filter_info *filter)
415 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
416 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
417 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
418 const struct rte_eth_vmdq_rx_conf *conf =
419 &dev_conf->rx_adv_conf.vmdq_rx_conf;
420 uint32_t enables = 0;
421 uint16_t j = dst_id - 1;
423 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
424 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
425 conf->pool_map[j].pools & (1UL << j)) {
427 "Add vlan %u to vmdq pool %u\n",
428 conf->pool_map[j].vlan_id, j);
430 filter->l2_ivlan = conf->pool_map[j].vlan_id;
432 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
433 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
436 if (filter->fw_l2_filter_id != UINT64_MAX)
437 bnxt_hwrm_clear_l2_filter(bp, filter);
439 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
441 req.flags = rte_cpu_to_le_32(filter->flags);
443 enables = filter->enables |
444 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
445 req.dst_id = rte_cpu_to_le_16(dst_id);
448 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
449 memcpy(req.l2_addr, filter->l2_addr,
452 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
453 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
456 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
457 req.l2_ovlan = filter->l2_ovlan;
459 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
460 req.l2_ivlan = filter->l2_ivlan;
462 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
463 req.l2_ovlan_mask = filter->l2_ovlan_mask;
465 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
466 req.l2_ivlan_mask = filter->l2_ivlan_mask;
467 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
468 req.src_id = rte_cpu_to_le_32(filter->src_id);
469 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
470 req.src_type = filter->src_type;
471 if (filter->pri_hint) {
472 req.pri_hint = filter->pri_hint;
473 req.l2_filter_id_hint =
474 rte_cpu_to_le_64(filter->l2_filter_id_hint);
477 req.enables = rte_cpu_to_le_32(enables);
479 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
483 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
484 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
487 filter->l2_ref_cnt++;
492 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
494 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
495 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
502 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
505 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
508 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
509 if (ptp->tx_tstamp_en)
510 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
513 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
514 req.flags = rte_cpu_to_le_32(flags);
515 req.enables = rte_cpu_to_le_32
516 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
517 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
519 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
525 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
528 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
529 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
530 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
535 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
537 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
539 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
543 if (!BNXT_CHIP_THOR(bp) &&
544 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
547 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
548 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
550 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
554 if (!BNXT_CHIP_THOR(bp)) {
555 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
556 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
557 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
558 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
559 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
560 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
561 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
562 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
563 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
564 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
565 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
566 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
567 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
568 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
569 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
570 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
571 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
572 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
581 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
584 struct hwrm_func_qcaps_input req = {.req_type = 0 };
585 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
586 uint16_t new_max_vfs;
590 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
592 req.fid = rte_cpu_to_le_16(0xffff);
594 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
598 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
599 flags = rte_le_to_cpu_32(resp->flags);
601 bp->pf.port_id = resp->port_id;
602 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
603 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
604 new_max_vfs = bp->pdev->max_vfs;
605 if (new_max_vfs != bp->pf.max_vfs) {
607 rte_free(bp->pf.vf_info);
608 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
609 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
610 bp->pf.max_vfs = new_max_vfs;
611 for (i = 0; i < new_max_vfs; i++) {
612 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
613 bp->pf.vf_info[i].vlan_table =
614 rte_zmalloc("VF VLAN table",
617 if (bp->pf.vf_info[i].vlan_table == NULL)
619 "Fail to alloc VLAN table for VF %d\n",
623 bp->pf.vf_info[i].vlan_table);
624 bp->pf.vf_info[i].vlan_as_table =
625 rte_zmalloc("VF VLAN AS table",
628 if (bp->pf.vf_info[i].vlan_as_table == NULL)
630 "Alloc VLAN AS table for VF %d fail\n",
634 bp->pf.vf_info[i].vlan_as_table);
635 STAILQ_INIT(&bp->pf.vf_info[i].filter);
640 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
641 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
642 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
643 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
644 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
645 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
646 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
647 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
648 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
649 if (!BNXT_CHIP_THOR(bp))
650 bp->max_l2_ctx += bp->max_rx_em_flows;
651 /* TODO: For now, do not support VMDq/RFS on VFs. */
656 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
660 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
662 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
663 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
664 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
665 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
667 bnxt_hwrm_ptp_qcfg(bp);
671 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
672 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
674 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
675 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
676 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
679 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
680 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
682 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
683 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
690 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
694 rc = __bnxt_hwrm_func_qcaps(bp);
695 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
696 rc = bnxt_alloc_ctx_mem(bp);
700 rc = bnxt_hwrm_func_resc_qcaps(bp);
702 bp->flags |= BNXT_FLAG_NEW_RM;
706 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
707 * But the error can be ignored. Return success.
713 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
714 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
717 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
718 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
720 HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
722 req.target_id = rte_cpu_to_le_16(0xffff);
724 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
728 if (rte_le_to_cpu_32(resp->flags) &
729 HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
730 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
731 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
734 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
741 int bnxt_hwrm_func_reset(struct bnxt *bp)
744 struct hwrm_func_reset_input req = {.req_type = 0 };
745 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
747 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
749 req.enables = rte_cpu_to_le_32(0);
751 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
759 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
763 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
764 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
766 if (bp->flags & BNXT_FLAG_REGISTERED)
769 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
770 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
771 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
772 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
774 /* PFs and trusted VFs should indicate the support of the
775 * Master capability on non Stingray platform
777 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
778 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
780 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
781 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
782 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
783 req.ver_maj = RTE_VER_YEAR;
784 req.ver_min = RTE_VER_MONTH;
785 req.ver_upd = RTE_VER_MINOR;
788 req.enables |= rte_cpu_to_le_32(
789 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
790 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
791 RTE_MIN(sizeof(req.vf_req_fwd),
792 sizeof(bp->pf.vf_req_fwd)));
795 * PF can sniff HWRM API issued by VF. This can be set up by
796 * linux driver and inherited by the DPDK PF driver. Clear
797 * this HWRM sniffer list in FW because DPDK PF driver does
800 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
803 req.flags = rte_cpu_to_le_32(flags);
805 req.async_event_fwd[0] |=
806 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
807 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
808 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
809 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
810 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
811 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
812 req.async_event_fwd[0] |=
813 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
814 req.async_event_fwd[1] |=
815 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
816 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
818 req.async_event_fwd[1] |=
819 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
821 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
825 flags = rte_le_to_cpu_32(resp->flags);
826 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
827 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
831 bp->flags |= BNXT_FLAG_REGISTERED;
836 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
838 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
841 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
844 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
849 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
850 struct hwrm_func_vf_cfg_input req = {0};
852 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
854 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
855 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
856 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
857 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
858 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
860 if (BNXT_HAS_RING_GRPS(bp)) {
861 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
862 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
865 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
866 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
867 AGG_RING_MULTIPLIER);
868 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
869 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
871 BNXT_NUM_ASYNC_CPR(bp));
872 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
873 if (bp->vf_resv_strategy ==
874 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
875 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
876 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
877 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
878 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
879 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
880 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
881 } else if (bp->vf_resv_strategy ==
882 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
883 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
884 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
888 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
889 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
890 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
891 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
892 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
893 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
895 if (test && BNXT_HAS_RING_GRPS(bp))
896 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
898 req.flags = rte_cpu_to_le_32(flags);
899 req.enables |= rte_cpu_to_le_32(enables);
901 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
904 HWRM_CHECK_RESULT_SILENT();
912 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
915 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
916 struct hwrm_func_resource_qcaps_input req = {0};
918 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
919 req.fid = rte_cpu_to_le_16(0xffff);
921 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
923 HWRM_CHECK_RESULT_SILENT();
926 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
927 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
928 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
929 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
930 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
931 /* func_resource_qcaps does not return max_rx_em_flows.
932 * So use the value provided by func_qcaps.
934 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
935 if (!BNXT_CHIP_THOR(bp))
936 bp->max_l2_ctx += bp->max_rx_em_flows;
937 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
938 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
940 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
941 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
942 if (bp->vf_resv_strategy >
943 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
944 bp->vf_resv_strategy =
945 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
951 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
954 struct hwrm_ver_get_input req = {.req_type = 0 };
955 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
957 uint16_t max_resp_len;
958 char type[RTE_MEMZONE_NAMESIZE];
959 uint32_t dev_caps_cfg;
961 bp->max_req_len = HWRM_MAX_REQ_LEN;
962 bp->hwrm_cmd_timeout = timeout;
963 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
965 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
966 req.hwrm_intf_min = HWRM_VERSION_MINOR;
967 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
969 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
971 if (bp->flags & BNXT_FLAG_FW_RESET)
972 HWRM_CHECK_RESULT_SILENT();
976 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
977 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
978 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
979 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
980 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
981 (resp->hwrm_fw_min_8b << 16) |
982 (resp->hwrm_fw_bld_8b << 8) |
983 resp->hwrm_fw_rsvd_8b;
984 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
985 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
987 fw_version = resp->hwrm_intf_maj_8b << 16;
988 fw_version |= resp->hwrm_intf_min_8b << 8;
989 fw_version |= resp->hwrm_intf_upd_8b;
990 bp->hwrm_spec_code = fw_version;
992 /* def_req_timeout value is in milliseconds */
993 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
994 /* convert timeout to usec */
995 bp->hwrm_cmd_timeout *= 1000;
996 if (!bp->hwrm_cmd_timeout)
997 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
999 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1000 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1005 if (bp->max_req_len > resp->max_req_win_len) {
1006 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1009 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1010 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1011 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1012 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1014 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1015 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1017 if (bp->max_resp_len != max_resp_len) {
1018 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
1019 bp->pdev->addr.domain, bp->pdev->addr.bus,
1020 bp->pdev->addr.devid, bp->pdev->addr.function);
1022 rte_free(bp->hwrm_cmd_resp_addr);
1024 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1025 if (bp->hwrm_cmd_resp_addr == NULL) {
1029 bp->hwrm_cmd_resp_dma_addr =
1030 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1031 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1033 "Unable to map response buffer to physical memory.\n");
1037 bp->max_resp_len = max_resp_len;
1041 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1043 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1044 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1045 bp->flags |= BNXT_FLAG_SHORT_CMD;
1048 if (((dev_caps_cfg &
1049 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1051 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1052 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1053 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1054 bp->pdev->addr.domain, bp->pdev->addr.bus,
1055 bp->pdev->addr.devid, bp->pdev->addr.function);
1057 rte_free(bp->hwrm_short_cmd_req_addr);
1059 bp->hwrm_short_cmd_req_addr =
1060 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1061 if (bp->hwrm_short_cmd_req_addr == NULL) {
1065 bp->hwrm_short_cmd_req_dma_addr =
1066 rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1067 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1068 rte_free(bp->hwrm_short_cmd_req_addr);
1070 "Unable to map buffer to physical memory.\n");
1076 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1077 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1078 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1081 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1082 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1084 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1085 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1086 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1094 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1097 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1098 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1100 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1103 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1106 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1108 HWRM_CHECK_RESULT();
1114 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1117 struct hwrm_port_phy_cfg_input req = {0};
1118 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1119 uint32_t enables = 0;
1121 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1123 if (conf->link_up) {
1124 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1125 if (bp->link_info.auto_mode && conf->link_speed) {
1126 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1127 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1130 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1131 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1132 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1134 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1135 * any auto mode, even "none".
1137 if (!conf->link_speed) {
1138 /* No speeds specified. Enable AutoNeg - all speeds */
1140 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1142 /* AutoNeg - Advertise speeds specified. */
1143 if (conf->auto_link_speed_mask &&
1144 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1146 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1147 req.auto_link_speed_mask =
1148 conf->auto_link_speed_mask;
1150 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1153 req.auto_duplex = conf->duplex;
1154 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1155 req.auto_pause = conf->auto_pause;
1156 req.force_pause = conf->force_pause;
1157 /* Set force_pause if there is no auto or if there is a force */
1158 if (req.auto_pause && !req.force_pause)
1159 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1161 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1163 req.enables = rte_cpu_to_le_32(enables);
1166 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1167 PMD_DRV_LOG(INFO, "Force Link Down\n");
1170 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1172 HWRM_CHECK_RESULT();
1178 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1179 struct bnxt_link_info *link_info)
1182 struct hwrm_port_phy_qcfg_input req = {0};
1183 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1185 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1187 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1189 HWRM_CHECK_RESULT();
1191 link_info->phy_link_status = resp->link;
1192 link_info->link_up =
1193 (link_info->phy_link_status ==
1194 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1195 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1196 link_info->duplex = resp->duplex_cfg;
1197 link_info->pause = resp->pause;
1198 link_info->auto_pause = resp->auto_pause;
1199 link_info->force_pause = resp->force_pause;
1200 link_info->auto_mode = resp->auto_mode;
1201 link_info->phy_type = resp->phy_type;
1202 link_info->media_type = resp->media_type;
1204 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1205 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1206 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1207 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1208 link_info->phy_ver[0] = resp->phy_maj;
1209 link_info->phy_ver[1] = resp->phy_min;
1210 link_info->phy_ver[2] = resp->phy_bld;
1214 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1215 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1216 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1217 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1218 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1219 link_info->auto_link_speed_mask);
1220 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1221 link_info->force_link_speed);
1226 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1230 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1231 if (bp->tx_cos_queue[i].profile ==
1232 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1233 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1240 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1244 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1245 if (bp->tx_cos_queue[i].profile !=
1246 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1247 bp->tx_cos_queue[i].id !=
1248 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1249 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1255 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1258 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1259 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1260 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1264 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1266 req.flags = rte_cpu_to_le_32(dir);
1267 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1268 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1269 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1271 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1272 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1274 HWRM_CHECK_RESULT();
1276 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1277 GET_TX_QUEUE_INFO(0);
1278 GET_TX_QUEUE_INFO(1);
1279 GET_TX_QUEUE_INFO(2);
1280 GET_TX_QUEUE_INFO(3);
1281 GET_TX_QUEUE_INFO(4);
1282 GET_TX_QUEUE_INFO(5);
1283 GET_TX_QUEUE_INFO(6);
1284 GET_TX_QUEUE_INFO(7);
1286 GET_RX_QUEUE_INFO(0);
1287 GET_RX_QUEUE_INFO(1);
1288 GET_RX_QUEUE_INFO(2);
1289 GET_RX_QUEUE_INFO(3);
1290 GET_RX_QUEUE_INFO(4);
1291 GET_RX_QUEUE_INFO(5);
1292 GET_RX_QUEUE_INFO(6);
1293 GET_RX_QUEUE_INFO(7);
1298 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1301 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1302 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1306 /* iterate and find the COSq profile to use for Tx */
1307 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1308 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1309 if (bp->tx_cos_queue[i].id != 0xff)
1310 bp->tx_cosq_id[j++] =
1311 bp->tx_cos_queue[i].id;
1314 /* When CoS classification is disabled, for normal NIC
1315 * operations, ideally we should look to use LOSSY.
1316 * If not found, fallback to the first valid profile
1318 if (!bnxt_find_lossy_profile(bp))
1319 bnxt_find_first_valid_profile(bp);
1324 bp->max_tc = resp->max_configurable_queues;
1325 bp->max_lltc = resp->max_configurable_lossless_queues;
1326 if (bp->max_tc > BNXT_MAX_QUEUE)
1327 bp->max_tc = BNXT_MAX_QUEUE;
1328 bp->max_q = bp->max_tc;
1330 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1331 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1339 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1340 struct bnxt_ring *ring,
1341 uint32_t ring_type, uint32_t map_index,
1342 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1343 uint16_t tx_cosq_id)
1346 uint32_t enables = 0;
1347 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1348 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1349 struct rte_mempool *mb_pool;
1350 uint16_t rx_buf_size;
1352 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1354 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1355 req.fbo = rte_cpu_to_le_32(0);
1356 /* Association of ring index with doorbell index */
1357 req.logical_id = rte_cpu_to_le_16(map_index);
1358 req.length = rte_cpu_to_le_32(ring->ring_size);
1360 switch (ring_type) {
1361 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1362 req.ring_type = ring_type;
1363 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1364 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1365 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1366 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1368 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1370 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1371 req.ring_type = ring_type;
1372 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1373 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1374 if (BNXT_CHIP_THOR(bp)) {
1375 mb_pool = bp->rx_queues[0]->mb_pool;
1376 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1377 RTE_PKTMBUF_HEADROOM;
1378 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1379 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1381 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1383 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1385 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1387 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1388 req.ring_type = ring_type;
1389 if (BNXT_HAS_NQ(bp)) {
1390 /* Association of cp ring with nq */
1391 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1393 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1395 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1397 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1398 req.ring_type = ring_type;
1399 req.page_size = BNXT_PAGE_SHFT;
1400 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1402 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1403 req.ring_type = ring_type;
1404 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1406 mb_pool = bp->rx_queues[0]->mb_pool;
1407 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1408 RTE_PKTMBUF_HEADROOM;
1409 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1410 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1412 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1413 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1414 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1415 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1418 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1423 req.enables = rte_cpu_to_le_32(enables);
1425 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1427 if (rc || resp->error_code) {
1428 if (rc == 0 && resp->error_code)
1429 rc = rte_le_to_cpu_16(resp->error_code);
1430 switch (ring_type) {
1431 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1433 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1436 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1438 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1441 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1443 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1447 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1449 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1452 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1454 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1458 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1464 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1469 int bnxt_hwrm_ring_free(struct bnxt *bp,
1470 struct bnxt_ring *ring, uint32_t ring_type)
1473 struct hwrm_ring_free_input req = {.req_type = 0 };
1474 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1476 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1478 req.ring_type = ring_type;
1479 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1481 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1483 if (rc || resp->error_code) {
1484 if (rc == 0 && resp->error_code)
1485 rc = rte_le_to_cpu_16(resp->error_code);
1488 switch (ring_type) {
1489 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1490 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1493 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1494 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1497 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1498 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1501 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1503 "hwrm_ring_free nq failed. rc:%d\n", rc);
1505 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1507 "hwrm_ring_free agg failed. rc:%d\n", rc);
1510 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1518 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1521 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1522 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1524 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1526 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1527 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1528 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1529 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1531 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1533 HWRM_CHECK_RESULT();
1535 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1542 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1545 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1546 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1548 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1550 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1552 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1554 HWRM_CHECK_RESULT();
1557 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1561 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1564 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1565 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1567 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1570 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1572 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1574 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1576 HWRM_CHECK_RESULT();
1582 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1583 unsigned int idx __rte_unused)
1586 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1587 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1589 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1591 req.update_period_ms = rte_cpu_to_le_32(0);
1593 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1595 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1597 HWRM_CHECK_RESULT();
1599 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1606 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1607 unsigned int idx __rte_unused)
1610 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1611 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1613 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1615 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1617 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1619 HWRM_CHECK_RESULT();
1625 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1628 struct hwrm_vnic_alloc_input req = { 0 };
1629 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1631 if (!BNXT_HAS_RING_GRPS(bp))
1632 goto skip_ring_grps;
1634 /* map ring groups to this vnic */
1635 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1636 vnic->start_grp_id, vnic->end_grp_id);
1637 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1638 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1640 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1641 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1642 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1643 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1646 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1647 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1649 if (vnic->func_default)
1651 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1652 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1654 HWRM_CHECK_RESULT();
1656 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1658 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1662 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1663 struct bnxt_vnic_info *vnic,
1664 struct bnxt_plcmodes_cfg *pmode)
1667 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1668 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1670 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1672 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1674 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1676 HWRM_CHECK_RESULT();
1678 pmode->flags = rte_le_to_cpu_32(resp->flags);
1679 /* dflt_vnic bit doesn't exist in the _cfg command */
1680 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1681 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1682 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1683 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1690 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1691 struct bnxt_vnic_info *vnic,
1692 struct bnxt_plcmodes_cfg *pmode)
1695 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1696 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1698 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1699 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1703 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1705 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1706 req.flags = rte_cpu_to_le_32(pmode->flags);
1707 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1708 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1709 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1710 req.enables = rte_cpu_to_le_32(
1711 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1712 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1713 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1716 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1718 HWRM_CHECK_RESULT();
1724 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1727 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1728 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1729 struct bnxt_plcmodes_cfg pmodes = { 0 };
1730 uint32_t ctx_enable_flag = 0;
1731 uint32_t enables = 0;
1733 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1734 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1738 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1742 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1744 if (BNXT_CHIP_THOR(bp)) {
1745 int dflt_rxq = vnic->start_grp_id;
1746 struct bnxt_rx_ring_info *rxr;
1747 struct bnxt_cp_ring_info *cpr;
1748 struct bnxt_rx_queue *rxq;
1752 * The first active receive ring is used as the VNIC
1753 * default receive ring. If there are no active receive
1754 * rings (all corresponding receive queues are stopped),
1755 * the first receive ring is used.
1757 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1758 rxq = bp->eth_dev->data->rx_queues[i];
1759 if (rxq->rx_started) {
1765 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1769 req.default_rx_ring_id =
1770 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1771 req.default_cmpl_ring_id =
1772 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1773 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1774 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1778 /* Only RSS support for now TBD: COS & LB */
1779 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1780 if (vnic->lb_rule != 0xffff)
1781 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1782 if (vnic->cos_rule != 0xffff)
1783 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1784 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1785 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1786 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1788 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1789 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1790 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1793 enables |= ctx_enable_flag;
1794 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1795 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1796 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1797 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1800 req.enables = rte_cpu_to_le_32(enables);
1801 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1802 req.mru = rte_cpu_to_le_16(vnic->mru);
1803 /* Configure default VNIC only once. */
1804 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1806 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1807 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1809 if (vnic->vlan_strip)
1811 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1814 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1815 if (vnic->roce_dual)
1816 req.flags |= rte_cpu_to_le_32(
1817 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1818 if (vnic->roce_only)
1819 req.flags |= rte_cpu_to_le_32(
1820 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1821 if (vnic->rss_dflt_cr)
1822 req.flags |= rte_cpu_to_le_32(
1823 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1825 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1827 HWRM_CHECK_RESULT();
1830 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1835 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1839 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1840 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1842 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1843 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1846 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1849 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1850 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1851 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1853 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1855 HWRM_CHECK_RESULT();
1857 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1858 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1859 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1860 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1861 vnic->mru = rte_le_to_cpu_16(resp->mru);
1862 vnic->func_default = rte_le_to_cpu_32(
1863 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1864 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1865 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1866 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1867 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1868 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1869 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1870 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1871 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1872 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1873 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1880 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1881 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1885 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1886 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1887 bp->hwrm_cmd_resp_addr;
1889 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1891 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1892 HWRM_CHECK_RESULT();
1894 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1895 if (!BNXT_HAS_RING_GRPS(bp))
1896 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1897 else if (ctx_idx == 0)
1898 vnic->rss_rule = ctx_id;
1906 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1907 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1910 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1911 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1912 bp->hwrm_cmd_resp_addr;
1914 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1915 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1918 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1920 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1922 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1924 HWRM_CHECK_RESULT();
1930 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1934 if (BNXT_CHIP_THOR(bp)) {
1937 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1938 rc = _bnxt_hwrm_vnic_ctx_free(bp,
1940 vnic->fw_grp_ids[j]);
1941 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1943 vnic->num_lb_ctxts = 0;
1945 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1946 vnic->rss_rule = INVALID_HW_RING_ID;
1952 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1955 struct hwrm_vnic_free_input req = {.req_type = 0 };
1956 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1958 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1959 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1963 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1965 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1967 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1969 HWRM_CHECK_RESULT();
1972 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1973 /* Configure default VNIC again if necessary. */
1974 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1975 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1981 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1985 int nr_ctxs = vnic->num_lb_ctxts;
1986 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1987 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1989 for (i = 0; i < nr_ctxs; i++) {
1990 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1992 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1993 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1994 req.hash_mode_flags = vnic->hash_mode;
1996 req.hash_key_tbl_addr =
1997 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1999 req.ring_grp_tbl_addr =
2000 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2001 i * HW_HASH_INDEX_SIZE);
2002 req.ring_table_pair_index = i;
2003 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2005 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2008 HWRM_CHECK_RESULT();
2015 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2016 struct bnxt_vnic_info *vnic)
2019 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2020 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2022 if (!vnic->rss_table)
2025 if (BNXT_CHIP_THOR(bp))
2026 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2028 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2030 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2031 req.hash_mode_flags = vnic->hash_mode;
2033 req.ring_grp_tbl_addr =
2034 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2035 req.hash_key_tbl_addr =
2036 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2037 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2038 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2040 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2042 HWRM_CHECK_RESULT();
2048 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2049 struct bnxt_vnic_info *vnic)
2052 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2053 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2056 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2057 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2061 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2063 req.flags = rte_cpu_to_le_32(
2064 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2066 req.enables = rte_cpu_to_le_32(
2067 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2069 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2070 size -= RTE_PKTMBUF_HEADROOM;
2071 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2073 req.jumbo_thresh = rte_cpu_to_le_16(size);
2074 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2076 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2078 HWRM_CHECK_RESULT();
2084 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2085 struct bnxt_vnic_info *vnic, bool enable)
2088 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2089 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2091 if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2093 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2097 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2098 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2102 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2105 req.enables = rte_cpu_to_le_32(
2106 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2107 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2108 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2109 req.flags = rte_cpu_to_le_32(
2110 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2111 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2112 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2113 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2114 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2115 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2116 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2117 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2118 req.min_agg_len = rte_cpu_to_le_32(512);
2120 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2122 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2124 HWRM_CHECK_RESULT();
2130 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2132 struct hwrm_func_cfg_input req = {0};
2133 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2136 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2137 req.enables = rte_cpu_to_le_32(
2138 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2139 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2140 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2142 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2144 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2145 HWRM_CHECK_RESULT();
2148 bp->pf.vf_info[vf].random_mac = false;
2153 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2157 struct hwrm_func_qstats_input req = {.req_type = 0};
2158 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2160 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2162 req.fid = rte_cpu_to_le_16(fid);
2164 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2166 HWRM_CHECK_RESULT();
2169 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2176 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2177 struct rte_eth_stats *stats)
2180 struct hwrm_func_qstats_input req = {.req_type = 0};
2181 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2183 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2185 req.fid = rte_cpu_to_le_16(fid);
2187 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2189 HWRM_CHECK_RESULT();
2191 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2192 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2193 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2194 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2195 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2196 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2198 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2199 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2200 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2201 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2202 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2203 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2205 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2206 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2207 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2214 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2217 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2218 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2220 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2222 req.fid = rte_cpu_to_le_16(fid);
2224 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2226 HWRM_CHECK_RESULT();
2232 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2237 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2238 struct bnxt_tx_queue *txq;
2239 struct bnxt_rx_queue *rxq;
2240 struct bnxt_cp_ring_info *cpr;
2242 if (i >= bp->rx_cp_nr_rings) {
2243 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2246 rxq = bp->rx_queues[i];
2250 rc = bnxt_hwrm_stat_clear(bp, cpr);
2258 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2262 struct bnxt_cp_ring_info *cpr;
2264 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2266 if (i >= bp->rx_cp_nr_rings) {
2267 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2269 cpr = bp->rx_queues[i]->cp_ring;
2270 if (BNXT_HAS_RING_GRPS(bp))
2271 bp->grp_info[i].fw_stats_ctx = -1;
2273 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2274 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2275 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2283 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2288 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2289 struct bnxt_tx_queue *txq;
2290 struct bnxt_rx_queue *rxq;
2291 struct bnxt_cp_ring_info *cpr;
2293 if (i >= bp->rx_cp_nr_rings) {
2294 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2297 rxq = bp->rx_queues[i];
2301 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2310 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2315 if (!BNXT_HAS_RING_GRPS(bp))
2318 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2320 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2323 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2331 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2333 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2335 bnxt_hwrm_ring_free(bp, cp_ring,
2336 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2337 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2338 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2339 sizeof(*cpr->cp_desc_ring));
2340 cpr->cp_raw_cons = 0;
2344 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2346 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2348 bnxt_hwrm_ring_free(bp, cp_ring,
2349 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2350 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2351 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2352 sizeof(*cpr->cp_desc_ring));
2353 cpr->cp_raw_cons = 0;
2357 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2359 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2360 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2361 struct bnxt_ring *ring = rxr->rx_ring_struct;
2362 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2364 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2365 bnxt_hwrm_ring_free(bp, ring,
2366 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2367 ring->fw_ring_id = INVALID_HW_RING_ID;
2368 if (BNXT_HAS_RING_GRPS(bp))
2369 bp->grp_info[queue_index].rx_fw_ring_id =
2371 memset(rxr->rx_desc_ring, 0,
2372 rxr->rx_ring_struct->ring_size *
2373 sizeof(*rxr->rx_desc_ring));
2374 memset(rxr->rx_buf_ring, 0,
2375 rxr->rx_ring_struct->ring_size *
2376 sizeof(*rxr->rx_buf_ring));
2379 ring = rxr->ag_ring_struct;
2380 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2381 bnxt_hwrm_ring_free(bp, ring,
2382 BNXT_CHIP_THOR(bp) ?
2383 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2384 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2385 ring->fw_ring_id = INVALID_HW_RING_ID;
2386 memset(rxr->ag_buf_ring, 0,
2387 rxr->ag_ring_struct->ring_size *
2388 sizeof(*rxr->ag_buf_ring));
2390 if (BNXT_HAS_RING_GRPS(bp))
2391 bp->grp_info[queue_index].ag_fw_ring_id =
2394 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2395 bnxt_free_cp_ring(bp, cpr);
2397 if (BNXT_HAS_RING_GRPS(bp))
2398 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2402 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2406 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2407 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2408 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2409 struct bnxt_ring *ring = txr->tx_ring_struct;
2410 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2412 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2413 bnxt_hwrm_ring_free(bp, ring,
2414 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2415 ring->fw_ring_id = INVALID_HW_RING_ID;
2416 memset(txr->tx_desc_ring, 0,
2417 txr->tx_ring_struct->ring_size *
2418 sizeof(*txr->tx_desc_ring));
2419 memset(txr->tx_buf_ring, 0,
2420 txr->tx_ring_struct->ring_size *
2421 sizeof(*txr->tx_buf_ring));
2425 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2426 bnxt_free_cp_ring(bp, cpr);
2427 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2431 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2432 bnxt_free_hwrm_rx_ring(bp, i);
2437 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2442 if (!BNXT_HAS_RING_GRPS(bp))
2445 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2446 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2454 * HWRM utility functions
2457 void bnxt_free_hwrm_resources(struct bnxt *bp)
2459 /* Release memzone */
2460 rte_free(bp->hwrm_cmd_resp_addr);
2461 rte_free(bp->hwrm_short_cmd_req_addr);
2462 bp->hwrm_cmd_resp_addr = NULL;
2463 bp->hwrm_short_cmd_req_addr = NULL;
2464 bp->hwrm_cmd_resp_dma_addr = 0;
2465 bp->hwrm_short_cmd_req_dma_addr = 0;
2468 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2470 struct rte_pci_device *pdev = bp->pdev;
2471 char type[RTE_MEMZONE_NAMESIZE];
2473 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2474 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2475 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2476 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2477 if (bp->hwrm_cmd_resp_addr == NULL)
2479 bp->hwrm_cmd_resp_dma_addr =
2480 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2481 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2483 "unable to map response address to physical memory\n");
2486 rte_spinlock_init(&bp->hwrm_lock);
2492 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2494 struct bnxt_filter_info *filter;
2497 STAILQ_FOREACH(filter, &vnic->filter, next) {
2498 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2499 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2500 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2501 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2502 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2503 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2504 bnxt_free_filter(bp, filter);
2510 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2512 struct bnxt_filter_info *filter;
2513 struct rte_flow *flow;
2516 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2517 flow = STAILQ_FIRST(&vnic->flow_list);
2518 filter = flow->filter;
2519 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2520 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2521 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2522 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2523 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2524 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2526 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2532 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2534 struct bnxt_filter_info *filter;
2537 STAILQ_FOREACH(filter, &vnic->filter, next) {
2538 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2539 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2541 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2542 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2545 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2554 bnxt_free_tunnel_ports(struct bnxt *bp)
2556 if (bp->vxlan_port_cnt)
2557 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2558 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2560 if (bp->geneve_port_cnt)
2561 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2562 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2563 bp->geneve_port = 0;
2566 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2570 if (bp->vnic_info == NULL)
2574 * Cleanup VNICs in reverse order, to make sure the L2 filter
2575 * from vnic0 is last to be cleaned up.
2577 for (i = bp->max_vnics - 1; i >= 0; i--) {
2578 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2580 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2583 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2585 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2587 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2589 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2591 bnxt_hwrm_vnic_free(bp, vnic);
2593 rte_free(vnic->fw_grp_ids);
2595 /* Ring resources */
2596 bnxt_free_all_hwrm_rings(bp);
2597 bnxt_free_all_hwrm_ring_grps(bp);
2598 bnxt_free_all_hwrm_stat_ctxs(bp);
2599 bnxt_free_tunnel_ports(bp);
2602 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2604 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2606 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2607 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2609 switch (conf_link_speed) {
2610 case ETH_LINK_SPEED_10M_HD:
2611 case ETH_LINK_SPEED_100M_HD:
2613 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2615 return hw_link_duplex;
2618 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2620 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2623 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2625 uint16_t eth_link_speed = 0;
2627 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2628 return ETH_LINK_SPEED_AUTONEG;
2630 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2631 case ETH_LINK_SPEED_100M:
2632 case ETH_LINK_SPEED_100M_HD:
2635 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2637 case ETH_LINK_SPEED_1G:
2639 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2641 case ETH_LINK_SPEED_2_5G:
2643 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2645 case ETH_LINK_SPEED_10G:
2647 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2649 case ETH_LINK_SPEED_20G:
2651 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2653 case ETH_LINK_SPEED_25G:
2655 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2657 case ETH_LINK_SPEED_40G:
2659 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2661 case ETH_LINK_SPEED_50G:
2663 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2665 case ETH_LINK_SPEED_100G:
2667 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2671 "Unsupported link speed %d; default to AUTO\n",
2675 return eth_link_speed;
2678 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2679 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2680 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2681 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2683 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2687 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2690 if (link_speed & ETH_LINK_SPEED_FIXED) {
2691 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2693 if (one_speed & (one_speed - 1)) {
2695 "Invalid advertised speeds (%u) for port %u\n",
2696 link_speed, port_id);
2699 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2701 "Unsupported advertised speed (%u) for port %u\n",
2702 link_speed, port_id);
2706 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2708 "Unsupported advertised speeds (%u) for port %u\n",
2709 link_speed, port_id);
2717 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2721 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2722 if (bp->link_info.support_speeds)
2723 return bp->link_info.support_speeds;
2724 link_speed = BNXT_SUPPORTED_SPEEDS;
2727 if (link_speed & ETH_LINK_SPEED_100M)
2728 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2729 if (link_speed & ETH_LINK_SPEED_100M_HD)
2730 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2731 if (link_speed & ETH_LINK_SPEED_1G)
2732 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2733 if (link_speed & ETH_LINK_SPEED_2_5G)
2734 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2735 if (link_speed & ETH_LINK_SPEED_10G)
2736 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2737 if (link_speed & ETH_LINK_SPEED_20G)
2738 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2739 if (link_speed & ETH_LINK_SPEED_25G)
2740 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2741 if (link_speed & ETH_LINK_SPEED_40G)
2742 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2743 if (link_speed & ETH_LINK_SPEED_50G)
2744 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2745 if (link_speed & ETH_LINK_SPEED_100G)
2746 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2750 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2752 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2754 switch (hw_link_speed) {
2755 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2756 eth_link_speed = ETH_SPEED_NUM_100M;
2758 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2759 eth_link_speed = ETH_SPEED_NUM_1G;
2761 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2762 eth_link_speed = ETH_SPEED_NUM_2_5G;
2764 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2765 eth_link_speed = ETH_SPEED_NUM_10G;
2767 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2768 eth_link_speed = ETH_SPEED_NUM_20G;
2770 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2771 eth_link_speed = ETH_SPEED_NUM_25G;
2773 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2774 eth_link_speed = ETH_SPEED_NUM_40G;
2776 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2777 eth_link_speed = ETH_SPEED_NUM_50G;
2779 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2780 eth_link_speed = ETH_SPEED_NUM_100G;
2782 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2784 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2788 return eth_link_speed;
2791 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2793 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2795 switch (hw_link_duplex) {
2796 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2797 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2799 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2801 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2802 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2805 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2809 return eth_link_duplex;
2812 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2815 struct bnxt_link_info *link_info = &bp->link_info;
2817 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2820 "Get link config failed with rc %d\n", rc);
2823 if (link_info->link_speed)
2825 bnxt_parse_hw_link_speed(link_info->link_speed);
2827 link->link_speed = ETH_SPEED_NUM_NONE;
2828 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2829 link->link_status = link_info->link_up;
2830 link->link_autoneg = link_info->auto_mode ==
2831 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2832 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2837 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2840 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2841 struct bnxt_link_info link_req;
2842 uint16_t speed, autoneg;
2844 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2847 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2848 bp->eth_dev->data->port_id);
2852 memset(&link_req, 0, sizeof(link_req));
2853 link_req.link_up = link_up;
2857 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2858 if (BNXT_CHIP_THOR(bp) &&
2859 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2860 /* 40G is not supported as part of media auto detect.
2861 * The speed should be forced and autoneg disabled
2862 * to configure 40G speed.
2864 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2868 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2869 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2870 /* Autoneg can be done only when the FW allows.
2871 * When user configures fixed speed of 40G and later changes to
2872 * any other speed, auto_link_speed/force_link_speed is still set
2873 * to 40G until link comes up at new speed.
2876 !(!BNXT_CHIP_THOR(bp) &&
2877 (bp->link_info.auto_link_speed ||
2878 bp->link_info.force_link_speed))) {
2879 link_req.phy_flags |=
2880 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2881 link_req.auto_link_speed_mask =
2882 bnxt_parse_eth_link_speed_mask(bp,
2883 dev_conf->link_speeds);
2885 if (bp->link_info.phy_type ==
2886 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2887 bp->link_info.phy_type ==
2888 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2889 bp->link_info.media_type ==
2890 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2891 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2895 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2896 /* If user wants a particular speed try that first. */
2898 link_req.link_speed = speed;
2899 else if (bp->link_info.force_link_speed)
2900 link_req.link_speed = bp->link_info.force_link_speed;
2902 link_req.link_speed = bp->link_info.auto_link_speed;
2904 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2905 link_req.auto_pause = bp->link_info.auto_pause;
2906 link_req.force_pause = bp->link_info.force_pause;
2909 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2912 "Set link config failed with rc %d\n", rc);
2920 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2922 struct hwrm_func_qcfg_input req = {0};
2923 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2927 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2928 req.fid = rte_cpu_to_le_16(0xffff);
2930 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2932 HWRM_CHECK_RESULT();
2934 /* Hard Coded.. 0xfff VLAN ID mask */
2935 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2936 flags = rte_le_to_cpu_16(resp->flags);
2937 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2938 bp->flags |= BNXT_FLAG_MULTI_HOST;
2941 !BNXT_VF_IS_TRUSTED(bp) &&
2942 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2943 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2944 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2945 } else if (BNXT_VF(bp) &&
2946 BNXT_VF_IS_TRUSTED(bp) &&
2947 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2948 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2949 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2953 *mtu = rte_le_to_cpu_16(resp->mtu);
2955 switch (resp->port_partition_type) {
2956 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2957 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2958 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2960 bp->flags |= BNXT_FLAG_NPAR_PF;
2963 bp->flags &= ~BNXT_FLAG_NPAR_PF;
2972 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2973 struct hwrm_func_qcaps_output *qcaps)
2975 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2976 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2977 sizeof(qcaps->mac_address));
2978 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2979 qcaps->max_rx_rings = fcfg->num_rx_rings;
2980 qcaps->max_tx_rings = fcfg->num_tx_rings;
2981 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2982 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2984 qcaps->first_vf_id = 0;
2985 qcaps->max_vnics = fcfg->num_vnics;
2986 qcaps->max_decap_records = 0;
2987 qcaps->max_encap_records = 0;
2988 qcaps->max_tx_wm_flows = 0;
2989 qcaps->max_tx_em_flows = 0;
2990 qcaps->max_rx_wm_flows = 0;
2991 qcaps->max_rx_em_flows = 0;
2992 qcaps->max_flow_id = 0;
2993 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2994 qcaps->max_sp_tx_rings = 0;
2995 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2998 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3000 struct hwrm_func_cfg_input req = {0};
3001 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3005 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3006 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3007 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3008 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3009 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3010 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3011 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3012 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3013 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3015 if (BNXT_HAS_RING_GRPS(bp)) {
3016 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3017 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3018 } else if (BNXT_HAS_NQ(bp)) {
3019 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3020 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3023 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3024 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3025 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3026 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3027 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3028 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3029 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3030 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3031 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3032 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3033 req.fid = rte_cpu_to_le_16(0xffff);
3034 req.enables = rte_cpu_to_le_32(enables);
3036 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3038 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3040 HWRM_CHECK_RESULT();
3046 static void populate_vf_func_cfg_req(struct bnxt *bp,
3047 struct hwrm_func_cfg_input *req,
3050 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3051 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3052 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3053 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3054 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3055 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3056 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3057 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3058 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3059 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3061 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3062 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3064 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3065 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3067 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3068 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3070 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3071 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3072 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3073 /* TODO: For now, do not support VMDq/RFS on VFs. */
3074 req->num_vnics = rte_cpu_to_le_16(1);
3075 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3079 static void add_random_mac_if_needed(struct bnxt *bp,
3080 struct hwrm_func_cfg_input *cfg_req,
3083 struct rte_ether_addr mac;
3085 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3088 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3090 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3091 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3092 bp->pf.vf_info[vf].random_mac = true;
3094 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3095 RTE_ETHER_ADDR_LEN);
3099 static void reserve_resources_from_vf(struct bnxt *bp,
3100 struct hwrm_func_cfg_input *cfg_req,
3103 struct hwrm_func_qcaps_input req = {0};
3104 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3107 /* Get the actual allocated values now */
3108 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3109 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3110 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3113 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3114 copy_func_cfg_to_qcaps(cfg_req, resp);
3115 } else if (resp->error_code) {
3116 rc = rte_le_to_cpu_16(resp->error_code);
3117 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3118 copy_func_cfg_to_qcaps(cfg_req, resp);
3121 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3122 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3123 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3124 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3125 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3126 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3128 * TODO: While not supporting VMDq with VFs, max_vnics is always
3129 * forced to 1 in this case
3131 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3132 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3137 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3139 struct hwrm_func_qcfg_input req = {0};
3140 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3143 /* Check for zero MAC address */
3144 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3145 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3146 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3147 HWRM_CHECK_RESULT();
3148 rc = rte_le_to_cpu_16(resp->vlan);
3155 static int update_pf_resource_max(struct bnxt *bp)
3157 struct hwrm_func_qcfg_input req = {0};
3158 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3161 /* And copy the allocated numbers into the pf struct */
3162 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3163 req.fid = rte_cpu_to_le_16(0xffff);
3164 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3165 HWRM_CHECK_RESULT();
3167 /* Only TX ring value reflects actual allocation? TODO */
3168 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3169 bp->pf.evb_mode = resp->evb_mode;
3176 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3181 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3185 rc = bnxt_hwrm_func_qcaps(bp);
3189 bp->pf.func_cfg_flags &=
3190 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3191 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3192 bp->pf.func_cfg_flags |=
3193 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3194 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3195 rc = __bnxt_hwrm_func_qcaps(bp);
3199 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3201 struct hwrm_func_cfg_input req = {0};
3202 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3209 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3213 rc = bnxt_hwrm_func_qcaps(bp);
3218 bp->pf.active_vfs = num_vfs;
3221 * First, configure the PF to only use one TX ring. This ensures that
3222 * there are enough rings for all VFs.
3224 * If we don't do this, when we call func_alloc() later, we will lock
3225 * extra rings to the PF that won't be available during func_cfg() of
3228 * This has been fixed with firmware versions above 20.6.54
3230 bp->pf.func_cfg_flags &=
3231 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3232 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3233 bp->pf.func_cfg_flags |=
3234 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3235 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3240 * Now, create and register a buffer to hold forwarded VF requests
3242 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3243 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3244 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3245 if (bp->pf.vf_req_buf == NULL) {
3249 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3250 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3251 for (i = 0; i < num_vfs; i++)
3252 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3253 (i * HWRM_MAX_REQ_LEN);
3255 rc = bnxt_hwrm_func_buf_rgtr(bp);
3259 populate_vf_func_cfg_req(bp, &req, num_vfs);
3261 bp->pf.active_vfs = 0;
3262 for (i = 0; i < num_vfs; i++) {
3263 add_random_mac_if_needed(bp, &req, i);
3265 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3266 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3267 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3268 rc = bnxt_hwrm_send_message(bp,
3273 /* Clear enable flag for next pass */
3274 req.enables &= ~rte_cpu_to_le_32(
3275 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3277 if (rc || resp->error_code) {
3279 "Failed to initizlie VF %d\n", i);
3281 "Not all VFs available. (%d, %d)\n",
3282 rc, resp->error_code);
3289 reserve_resources_from_vf(bp, &req, i);
3290 bp->pf.active_vfs++;
3291 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3295 * Now configure the PF to use "the rest" of the resources
3296 * We're using STD_TX_RING_MODE here though which will limit the TX
3297 * rings. This will allow QoS to function properly. Not setting this
3298 * will cause PF rings to break bandwidth settings.
3300 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3304 rc = update_pf_resource_max(bp);
3311 bnxt_hwrm_func_buf_unrgtr(bp);
3315 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3317 struct hwrm_func_cfg_input req = {0};
3318 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3321 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3323 req.fid = rte_cpu_to_le_16(0xffff);
3324 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3325 req.evb_mode = bp->pf.evb_mode;
3327 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3328 HWRM_CHECK_RESULT();
3334 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3335 uint8_t tunnel_type)
3337 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3338 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3341 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3342 req.tunnel_type = tunnel_type;
3343 req.tunnel_dst_port_val = port;
3344 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3345 HWRM_CHECK_RESULT();
3347 switch (tunnel_type) {
3348 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3349 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3350 bp->vxlan_port = port;
3352 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3353 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3354 bp->geneve_port = port;
3365 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3366 uint8_t tunnel_type)
3368 struct hwrm_tunnel_dst_port_free_input req = {0};
3369 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3372 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3374 req.tunnel_type = tunnel_type;
3375 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3376 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3378 HWRM_CHECK_RESULT();
3384 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3387 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3388 struct hwrm_func_cfg_input req = {0};
3391 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3393 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3394 req.flags = rte_cpu_to_le_32(flags);
3395 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3397 HWRM_CHECK_RESULT();
3403 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3405 uint32_t *flag = flagp;
3407 vnic->flags = *flag;
3410 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3412 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3415 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3418 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3419 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3421 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3423 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3424 req.req_buf_page_size = rte_cpu_to_le_16(
3425 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3426 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3427 req.req_buf_page_addr0 =
3428 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf.vf_req_buf));
3429 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3431 "unable to map buffer address to physical memory\n");
3435 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3437 HWRM_CHECK_RESULT();
3443 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3446 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3447 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3449 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3452 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3454 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3456 HWRM_CHECK_RESULT();
3462 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3464 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3465 struct hwrm_func_cfg_input req = {0};
3468 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3470 req.fid = rte_cpu_to_le_16(0xffff);
3471 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3472 req.enables = rte_cpu_to_le_32(
3473 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3474 req.async_event_cr = rte_cpu_to_le_16(
3475 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3476 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3478 HWRM_CHECK_RESULT();
3484 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3486 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3487 struct hwrm_func_vf_cfg_input req = {0};
3490 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3492 req.enables = rte_cpu_to_le_32(
3493 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3494 req.async_event_cr = rte_cpu_to_le_16(
3495 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3496 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3498 HWRM_CHECK_RESULT();
3504 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3506 struct hwrm_func_cfg_input req = {0};
3507 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3508 uint16_t dflt_vlan, fid;
3509 uint32_t func_cfg_flags;
3512 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3515 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3516 fid = bp->pf.vf_info[vf].fid;
3517 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3519 fid = rte_cpu_to_le_16(0xffff);
3520 func_cfg_flags = bp->pf.func_cfg_flags;
3521 dflt_vlan = bp->vlan;
3524 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3525 req.fid = rte_cpu_to_le_16(fid);
3526 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3527 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3529 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3531 HWRM_CHECK_RESULT();
3537 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3538 uint16_t max_bw, uint16_t enables)
3540 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3541 struct hwrm_func_cfg_input req = {0};
3544 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3546 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3547 req.enables |= rte_cpu_to_le_32(enables);
3548 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3549 req.max_bw = rte_cpu_to_le_32(max_bw);
3550 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3552 HWRM_CHECK_RESULT();
3558 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3560 struct hwrm_func_cfg_input req = {0};
3561 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3564 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3566 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3567 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3568 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3569 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3571 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3573 HWRM_CHECK_RESULT();
3579 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3584 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3586 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3591 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3592 void *encaped, size_t ec_size)
3595 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3596 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3598 if (ec_size > sizeof(req.encap_request))
3601 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3603 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3604 memcpy(req.encap_request, encaped, ec_size);
3606 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3608 HWRM_CHECK_RESULT();
3614 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3615 struct rte_ether_addr *mac)
3617 struct hwrm_func_qcfg_input req = {0};
3618 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3621 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3623 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3624 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3626 HWRM_CHECK_RESULT();
3628 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3635 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3636 void *encaped, size_t ec_size)
3639 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3640 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3642 if (ec_size > sizeof(req.encap_request))
3645 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3647 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3648 memcpy(req.encap_request, encaped, ec_size);
3650 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3652 HWRM_CHECK_RESULT();
3658 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3659 struct rte_eth_stats *stats, uint8_t rx)
3662 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3663 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3665 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3667 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3669 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3671 HWRM_CHECK_RESULT();
3674 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3675 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3676 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3677 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3678 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3679 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3680 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3681 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3683 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3684 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3685 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3686 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3687 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3688 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3696 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3698 struct hwrm_port_qstats_input req = {0};
3699 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3700 struct bnxt_pf_info *pf = &bp->pf;
3703 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3705 req.port_id = rte_cpu_to_le_16(pf->port_id);
3706 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3707 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3708 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3710 HWRM_CHECK_RESULT();
3716 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3718 struct hwrm_port_clr_stats_input req = {0};
3719 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3720 struct bnxt_pf_info *pf = &bp->pf;
3723 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3724 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3725 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3728 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3730 req.port_id = rte_cpu_to_le_16(pf->port_id);
3731 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3733 HWRM_CHECK_RESULT();
3739 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3741 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3742 struct hwrm_port_led_qcaps_input req = {0};
3748 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3749 req.port_id = bp->pf.port_id;
3750 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3752 HWRM_CHECK_RESULT();
3754 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3757 bp->num_leds = resp->num_leds;
3758 memcpy(bp->leds, &resp->led0_id,
3759 sizeof(bp->leds[0]) * bp->num_leds);
3760 for (i = 0; i < bp->num_leds; i++) {
3761 struct bnxt_led_info *led = &bp->leds[i];
3763 uint16_t caps = led->led_state_caps;
3765 if (!led->led_group_id ||
3766 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3778 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3780 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3781 struct hwrm_port_led_cfg_input req = {0};
3782 struct bnxt_led_cfg *led_cfg;
3783 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3784 uint16_t duration = 0;
3787 if (!bp->num_leds || BNXT_VF(bp))
3790 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3793 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3794 duration = rte_cpu_to_le_16(500);
3796 req.port_id = bp->pf.port_id;
3797 req.num_leds = bp->num_leds;
3798 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3799 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3800 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3801 led_cfg->led_id = bp->leds[i].led_id;
3802 led_cfg->led_state = led_state;
3803 led_cfg->led_blink_on = duration;
3804 led_cfg->led_blink_off = duration;
3805 led_cfg->led_group_id = bp->leds[i].led_group_id;
3808 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3810 HWRM_CHECK_RESULT();
3816 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3820 struct hwrm_nvm_get_dir_info_input req = {0};
3821 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3823 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3825 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3827 HWRM_CHECK_RESULT();
3829 *entries = rte_le_to_cpu_32(resp->entries);
3830 *length = rte_le_to_cpu_32(resp->entry_length);
3836 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3839 uint32_t dir_entries;
3840 uint32_t entry_length;
3843 rte_iova_t dma_handle;
3844 struct hwrm_nvm_get_dir_entries_input req = {0};
3845 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3847 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3851 *data++ = dir_entries;
3852 *data++ = entry_length;
3854 memset(data, 0xff, len);
3856 buflen = dir_entries * entry_length;
3857 buf = rte_malloc("nvm_dir", buflen, 0);
3860 dma_handle = rte_malloc_virt2iova(buf);
3861 if (dma_handle == RTE_BAD_IOVA) {
3863 "unable to map response address to physical memory\n");
3866 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3867 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3868 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3871 memcpy(data, buf, len > buflen ? buflen : len);
3874 HWRM_CHECK_RESULT();
3880 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3881 uint32_t offset, uint32_t length,
3886 rte_iova_t dma_handle;
3887 struct hwrm_nvm_read_input req = {0};
3888 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3890 buf = rte_malloc("nvm_item", length, 0);
3894 dma_handle = rte_malloc_virt2iova(buf);
3895 if (dma_handle == RTE_BAD_IOVA) {
3897 "unable to map response address to physical memory\n");
3900 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3901 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3902 req.dir_idx = rte_cpu_to_le_16(index);
3903 req.offset = rte_cpu_to_le_32(offset);
3904 req.len = rte_cpu_to_le_32(length);
3905 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3907 memcpy(data, buf, length);
3910 HWRM_CHECK_RESULT();
3916 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3919 struct hwrm_nvm_erase_dir_entry_input req = {0};
3920 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3922 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3923 req.dir_idx = rte_cpu_to_le_16(index);
3924 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3925 HWRM_CHECK_RESULT();
3932 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3933 uint16_t dir_ordinal, uint16_t dir_ext,
3934 uint16_t dir_attr, const uint8_t *data,
3938 struct hwrm_nvm_write_input req = {0};
3939 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3940 rte_iova_t dma_handle;
3943 buf = rte_malloc("nvm_write", data_len, 0);
3947 dma_handle = rte_malloc_virt2iova(buf);
3948 if (dma_handle == RTE_BAD_IOVA) {
3950 "unable to map response address to physical memory\n");
3953 memcpy(buf, data, data_len);
3955 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3957 req.dir_type = rte_cpu_to_le_16(dir_type);
3958 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3959 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3960 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3961 req.dir_data_length = rte_cpu_to_le_32(data_len);
3962 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3964 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3967 HWRM_CHECK_RESULT();
3974 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3976 uint32_t *count = cbdata;
3978 *count = *count + 1;
3981 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3982 struct bnxt_vnic_info *vnic __rte_unused)
3987 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3991 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3992 &count, bnxt_vnic_count_hwrm_stub);
3997 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4000 struct hwrm_func_vf_vnic_ids_query_input req = {0};
4001 struct hwrm_func_vf_vnic_ids_query_output *resp =
4002 bp->hwrm_cmd_resp_addr;
4005 /* First query all VNIC ids */
4006 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4008 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
4009 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
4010 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4012 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4015 "unable to map VNIC ID table address to physical memory\n");
4018 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4019 HWRM_CHECK_RESULT();
4020 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4028 * This function queries the VNIC IDs for a specified VF. It then calls
4029 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4030 * Then it calls the hwrm_cb function to program this new vnic configuration.
4032 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4033 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4034 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4036 struct bnxt_vnic_info vnic;
4038 int i, num_vnic_ids;
4043 /* First query all VNIC ids */
4044 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4045 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4046 RTE_CACHE_LINE_SIZE);
4047 if (vnic_ids == NULL)
4050 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4051 rte_mem_lock_page(((char *)vnic_ids) + sz);
4053 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4055 if (num_vnic_ids < 0)
4056 return num_vnic_ids;
4058 /* Retrieve VNIC, update bd_stall then update */
4060 for (i = 0; i < num_vnic_ids; i++) {
4061 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4062 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4063 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4066 if (vnic.mru <= 4) /* Indicates unallocated */
4069 vnic_cb(&vnic, cbdata);
4071 rc = hwrm_cb(bp, &vnic);
4081 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4084 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4085 struct hwrm_func_cfg_input req = {0};
4088 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4090 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4091 req.enables |= rte_cpu_to_le_32(
4092 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4093 req.vlan_antispoof_mode = on ?
4094 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4095 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4096 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4098 HWRM_CHECK_RESULT();
4104 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4106 struct bnxt_vnic_info vnic;
4109 int num_vnic_ids, i;
4113 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4114 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4115 RTE_CACHE_LINE_SIZE);
4116 if (vnic_ids == NULL)
4119 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4120 rte_mem_lock_page(((char *)vnic_ids) + sz);
4122 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4128 * Loop through to find the default VNIC ID.
4129 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4130 * by sending the hwrm_func_qcfg command to the firmware.
4132 for (i = 0; i < num_vnic_ids; i++) {
4133 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4134 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4135 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4136 bp->pf.first_vf_id + vf);
4139 if (vnic.func_default) {
4141 return vnic.fw_vnic_id;
4144 /* Could not find a default VNIC. */
4145 PMD_DRV_LOG(ERR, "No default VNIC\n");
4151 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4153 struct bnxt_filter_info *filter)
4156 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4157 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4158 uint32_t enables = 0;
4160 if (filter->fw_em_filter_id != UINT64_MAX)
4161 bnxt_hwrm_clear_em_filter(bp, filter);
4163 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4165 req.flags = rte_cpu_to_le_32(filter->flags);
4167 enables = filter->enables |
4168 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4169 req.dst_id = rte_cpu_to_le_16(dst_id);
4171 if (filter->ip_addr_type) {
4172 req.ip_addr_type = filter->ip_addr_type;
4173 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4176 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4177 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4179 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4180 memcpy(req.src_macaddr, filter->src_macaddr,
4181 RTE_ETHER_ADDR_LEN);
4183 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4184 memcpy(req.dst_macaddr, filter->dst_macaddr,
4185 RTE_ETHER_ADDR_LEN);
4187 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4188 req.ovlan_vid = filter->l2_ovlan;
4190 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4191 req.ivlan_vid = filter->l2_ivlan;
4193 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4194 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4196 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4197 req.ip_protocol = filter->ip_protocol;
4199 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4200 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4202 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4203 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4205 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4206 req.src_port = rte_cpu_to_be_16(filter->src_port);
4208 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4209 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4211 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4212 req.mirror_vnic_id = filter->mirror_vnic_id;
4214 req.enables = rte_cpu_to_le_32(enables);
4216 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4218 HWRM_CHECK_RESULT();
4220 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4226 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4229 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4230 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4232 if (filter->fw_em_filter_id == UINT64_MAX)
4235 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4237 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4239 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4241 HWRM_CHECK_RESULT();
4244 filter->fw_em_filter_id = UINT64_MAX;
4245 filter->fw_l2_filter_id = UINT64_MAX;
4250 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4252 struct bnxt_filter_info *filter)
4255 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4256 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4257 bp->hwrm_cmd_resp_addr;
4258 uint32_t enables = 0;
4260 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4261 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4263 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4265 req.flags = rte_cpu_to_le_32(filter->flags);
4267 enables = filter->enables |
4268 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4269 req.dst_id = rte_cpu_to_le_16(dst_id);
4271 if (filter->ip_addr_type) {
4272 req.ip_addr_type = filter->ip_addr_type;
4274 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4277 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4278 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4280 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4281 memcpy(req.src_macaddr, filter->src_macaddr,
4282 RTE_ETHER_ADDR_LEN);
4284 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4285 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4287 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4288 req.ip_protocol = filter->ip_protocol;
4290 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4291 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4293 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4294 req.src_ipaddr_mask[0] =
4295 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4297 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4298 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4300 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4301 req.dst_ipaddr_mask[0] =
4302 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4304 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4305 req.src_port = rte_cpu_to_le_16(filter->src_port);
4307 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4308 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4310 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4311 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4313 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4314 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4316 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4317 req.mirror_vnic_id = filter->mirror_vnic_id;
4319 req.enables = rte_cpu_to_le_32(enables);
4321 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4323 HWRM_CHECK_RESULT();
4325 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4326 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4332 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4333 struct bnxt_filter_info *filter)
4336 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4337 struct hwrm_cfa_ntuple_filter_free_output *resp =
4338 bp->hwrm_cmd_resp_addr;
4340 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4343 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4345 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4347 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4349 HWRM_CHECK_RESULT();
4352 filter->fw_ntuple_filter_id = UINT64_MAX;
4358 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4360 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4361 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4362 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4363 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4364 uint16_t *ring_tbl = vnic->rss_table;
4365 int nr_ctxs = vnic->num_lb_ctxts;
4366 int max_rings = bp->rx_nr_rings;
4370 for (i = 0, k = 0; i < nr_ctxs; i++) {
4371 struct bnxt_rx_ring_info *rxr;
4372 struct bnxt_cp_ring_info *cpr;
4374 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4376 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4377 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4378 req.hash_mode_flags = vnic->hash_mode;
4380 req.ring_grp_tbl_addr =
4381 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4382 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4383 2 * sizeof(*ring_tbl));
4384 req.hash_key_tbl_addr =
4385 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4387 req.ring_table_pair_index = i;
4388 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4390 for (j = 0; j < 64; j++) {
4393 /* Find next active ring. */
4394 for (cnt = 0; cnt < max_rings; cnt++) {
4395 if (rx_queue_state[k] !=
4396 RTE_ETH_QUEUE_STATE_STOPPED)
4398 if (++k == max_rings)
4402 /* Return if no rings are active. */
4403 if (cnt == max_rings) {
4408 /* Add rx/cp ring pair to RSS table. */
4409 rxr = rxqs[k]->rx_ring;
4410 cpr = rxqs[k]->cp_ring;
4412 ring_id = rxr->rx_ring_struct->fw_ring_id;
4413 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4414 ring_id = cpr->cp_ring_struct->fw_ring_id;
4415 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4417 if (++k == max_rings)
4420 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4423 HWRM_CHECK_RESULT();
4430 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4432 unsigned int rss_idx, fw_idx, i;
4434 if (!(vnic->rss_table && vnic->hash_type))
4437 if (BNXT_CHIP_THOR(bp))
4438 return bnxt_vnic_rss_configure_thor(bp, vnic);
4440 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4443 if (vnic->rss_table && vnic->hash_type) {
4445 * Fill the RSS hash & redirection table with
4446 * ring group ids for all VNICs
4448 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4449 rss_idx++, fw_idx++) {
4450 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4451 fw_idx %= bp->rx_cp_nr_rings;
4452 if (vnic->fw_grp_ids[fw_idx] !=
4457 if (i == bp->rx_cp_nr_rings)
4459 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4461 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4467 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4468 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4472 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4474 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4475 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4477 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4478 req->num_cmpl_dma_aggr_during_int =
4479 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4481 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4483 /* min timer set to 1/2 of interrupt timer */
4484 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4486 /* buf timer set to 1/4 of interrupt timer */
4487 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4489 req->cmpl_aggr_dma_tmr_during_int =
4490 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4492 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4493 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4494 req->flags = rte_cpu_to_le_16(flags);
4497 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4498 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4500 struct hwrm_ring_aggint_qcaps_input req = {0};
4501 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4506 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4507 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4508 HWRM_CHECK_RESULT();
4510 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4511 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4513 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4514 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4515 agg_req->flags = rte_cpu_to_le_16(flags);
4517 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4518 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4519 agg_req->enables = rte_cpu_to_le_32(enables);
4525 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4526 struct bnxt_coal *coal, uint16_t ring_id)
4528 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4529 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4530 bp->hwrm_cmd_resp_addr;
4533 /* Set ring coalesce parameters only for 100G NICs */
4534 if (BNXT_CHIP_THOR(bp)) {
4535 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4537 } else if (bnxt_stratus_device(bp)) {
4538 bnxt_hwrm_set_coal_params(coal, &req);
4543 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4544 req.ring_id = rte_cpu_to_le_16(ring_id);
4545 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4546 HWRM_CHECK_RESULT();
4551 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4552 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4554 struct hwrm_func_backing_store_qcaps_input req = {0};
4555 struct hwrm_func_backing_store_qcaps_output *resp =
4556 bp->hwrm_cmd_resp_addr;
4557 struct bnxt_ctx_pg_info *ctx_pg;
4558 struct bnxt_ctx_mem_info *ctx;
4559 int total_alloc_len;
4562 if (!BNXT_CHIP_THOR(bp) ||
4563 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4568 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4569 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4570 HWRM_CHECK_RESULT_SILENT();
4572 total_alloc_len = sizeof(*ctx);
4573 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4574 RTE_CACHE_LINE_SIZE);
4580 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4581 sizeof(*ctx_pg) * BNXT_MAX_Q,
4582 RTE_CACHE_LINE_SIZE);
4587 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4588 ctx->tqm_mem[i] = ctx_pg;
4591 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4592 ctx->qp_min_qp1_entries =
4593 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4594 ctx->qp_max_l2_entries =
4595 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4596 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4597 ctx->srq_max_l2_entries =
4598 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4599 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4600 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4601 ctx->cq_max_l2_entries =
4602 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4603 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4604 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4605 ctx->vnic_max_vnic_entries =
4606 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4607 ctx->vnic_max_ring_table_entries =
4608 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4609 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4610 ctx->stat_max_entries =
4611 rte_le_to_cpu_32(resp->stat_max_entries);
4612 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4613 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4614 ctx->tqm_min_entries_per_ring =
4615 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4616 ctx->tqm_max_entries_per_ring =
4617 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4618 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4619 if (!ctx->tqm_entries_multiple)
4620 ctx->tqm_entries_multiple = 1;
4621 ctx->mrav_max_entries =
4622 rte_le_to_cpu_32(resp->mrav_max_entries);
4623 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4624 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4625 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4631 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4633 struct hwrm_func_backing_store_cfg_input req = {0};
4634 struct hwrm_func_backing_store_cfg_output *resp =
4635 bp->hwrm_cmd_resp_addr;
4636 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4637 struct bnxt_ctx_pg_info *ctx_pg;
4638 uint32_t *num_entries;
4647 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4648 req.enables = rte_cpu_to_le_32(enables);
4650 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4651 ctx_pg = &ctx->qp_mem;
4652 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4653 req.qp_num_qp1_entries =
4654 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4655 req.qp_num_l2_entries =
4656 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4657 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4658 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4659 &req.qpc_pg_size_qpc_lvl,
4663 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4664 ctx_pg = &ctx->srq_mem;
4665 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4666 req.srq_num_l2_entries =
4667 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4668 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4669 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4670 &req.srq_pg_size_srq_lvl,
4674 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4675 ctx_pg = &ctx->cq_mem;
4676 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4677 req.cq_num_l2_entries =
4678 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4679 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4680 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4681 &req.cq_pg_size_cq_lvl,
4685 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4686 ctx_pg = &ctx->vnic_mem;
4687 req.vnic_num_vnic_entries =
4688 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4689 req.vnic_num_ring_table_entries =
4690 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4691 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4692 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4693 &req.vnic_pg_size_vnic_lvl,
4694 &req.vnic_page_dir);
4697 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4698 ctx_pg = &ctx->stat_mem;
4699 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4700 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4701 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4702 &req.stat_pg_size_stat_lvl,
4703 &req.stat_page_dir);
4706 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4707 num_entries = &req.tqm_sp_num_entries;
4708 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4709 pg_dir = &req.tqm_sp_page_dir;
4710 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4711 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4712 if (!(enables & ena))
4715 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4717 ctx_pg = ctx->tqm_mem[i];
4718 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4719 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4722 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4723 HWRM_CHECK_RESULT();
4729 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4731 struct hwrm_port_qstats_ext_input req = {0};
4732 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4733 struct bnxt_pf_info *pf = &bp->pf;
4736 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4737 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4740 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4742 req.port_id = rte_cpu_to_le_16(pf->port_id);
4743 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4744 req.tx_stat_host_addr =
4745 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4747 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4749 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4750 req.rx_stat_host_addr =
4751 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4753 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4755 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4758 bp->fw_rx_port_stats_ext_size = 0;
4759 bp->fw_tx_port_stats_ext_size = 0;
4761 bp->fw_rx_port_stats_ext_size =
4762 rte_le_to_cpu_16(resp->rx_stat_size);
4763 bp->fw_tx_port_stats_ext_size =
4764 rte_le_to_cpu_16(resp->tx_stat_size);
4767 HWRM_CHECK_RESULT();
4774 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4776 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4777 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4778 bp->hwrm_cmd_resp_addr;
4781 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4782 req.tunnel_type = type;
4783 req.dest_fid = bp->fw_fid;
4784 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4785 HWRM_CHECK_RESULT();
4793 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4795 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4796 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4797 bp->hwrm_cmd_resp_addr;
4800 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4801 req.tunnel_type = type;
4802 req.dest_fid = bp->fw_fid;
4803 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4804 HWRM_CHECK_RESULT();
4811 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4813 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4814 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4815 bp->hwrm_cmd_resp_addr;
4818 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4819 req.src_fid = bp->fw_fid;
4820 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4821 HWRM_CHECK_RESULT();
4824 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4831 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4834 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4835 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4836 bp->hwrm_cmd_resp_addr;
4839 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4840 req.src_fid = bp->fw_fid;
4841 req.tunnel_type = tun_type;
4842 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4843 HWRM_CHECK_RESULT();
4846 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4848 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4855 int bnxt_hwrm_set_mac(struct bnxt *bp)
4857 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4858 struct hwrm_func_vf_cfg_input req = {0};
4864 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4867 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4868 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4870 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4872 HWRM_CHECK_RESULT();
4874 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4880 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4882 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4883 struct hwrm_func_drv_if_change_input req = {0};
4887 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
4890 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4891 * If we issue FUNC_DRV_IF_CHANGE with flags down before
4892 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4894 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4897 HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4901 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4903 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4905 HWRM_CHECK_RESULT();
4906 flags = rte_le_to_cpu_32(resp->flags);
4912 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4913 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4914 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4920 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4922 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4923 struct bnxt_error_recovery_info *info = bp->recovery_info;
4924 struct hwrm_error_recovery_qcfg_input req = {0};
4929 /* Older FW does not have error recovery support */
4930 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4934 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4936 bp->recovery_info = info;
4940 memset(info, 0, sizeof(*info));
4943 HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4945 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4947 HWRM_CHECK_RESULT();
4949 flags = rte_le_to_cpu_32(resp->flags);
4950 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4951 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4952 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4953 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4955 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4956 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4961 /* FW returned values are in units of 100msec */
4962 info->driver_polling_freq =
4963 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4964 info->master_func_wait_period =
4965 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4966 info->normal_func_wait_period =
4967 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4968 info->master_func_wait_period_after_reset =
4969 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4970 info->max_bailout_time_after_reset =
4971 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4972 info->status_regs[BNXT_FW_STATUS_REG] =
4973 rte_le_to_cpu_32(resp->fw_health_status_reg);
4974 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4975 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4976 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4977 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4978 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4979 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4980 info->reg_array_cnt =
4981 rte_le_to_cpu_32(resp->reg_array_cnt);
4983 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4988 for (i = 0; i < info->reg_array_cnt; i++) {
4989 info->reset_reg[i] =
4990 rte_le_to_cpu_32(resp->reset_reg[i]);
4991 info->reset_reg_val[i] =
4992 rte_le_to_cpu_32(resp->reset_reg_val[i]);
4993 info->delay_after_reset[i] =
4994 resp->delay_after_reset[i];
4999 /* Map the FW status registers */
5001 rc = bnxt_map_fw_health_status_regs(bp);
5004 rte_free(bp->recovery_info);
5005 bp->recovery_info = NULL;
5010 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5012 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5013 struct hwrm_fw_reset_input req = {0};
5019 HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
5021 req.embedded_proc_type =
5022 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5023 req.selfrst_status =
5024 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5025 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5027 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5030 HWRM_CHECK_RESULT();
5036 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5038 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5039 struct hwrm_port_ts_query_input req = {0};
5040 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5047 HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5050 case BNXT_PTP_FLAGS_PATH_TX:
5051 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5053 case BNXT_PTP_FLAGS_PATH_RX:
5054 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5056 case BNXT_PTP_FLAGS_CURRENT_TIME:
5057 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5061 req.flags = rte_cpu_to_le_32(flags);
5062 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5064 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5066 HWRM_CHECK_RESULT();
5069 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5071 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5078 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5080 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5081 bp->hwrm_cmd_resp_addr;
5082 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5086 if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5089 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5091 "Not a PF or trusted VF. Command not supported\n");
5095 HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5096 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5098 HWRM_CHECK_RESULT();
5099 flags = rte_le_to_cpu_32(resp->flags);
5102 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5103 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5104 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");