drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SPEC_CODE_1_8_3            0x10803
  31 #define HWRM_VERSION_1_9_1              0x10901
  32
  33 struct bnxt_plcmodes_cfg {
  34         uint32_t        flags;
  35         uint16_t        jumbo_thresh;
  36         uint16_t        hds_offset;
  37         uint16_t        hds_threshold;
  38 };
  39
  40 static int page_getenum(size_t size)
  41 {
  42         if (size <= 1 << 4)
  43                 return 4;
  44         if (size <= 1 << 12)
  45                 return 12;
  46         if (size <= 1 << 13)
  47                 return 13;
  48         if (size <= 1 << 16)
  49                 return 16;
  50         if (size <= 1 << 21)
  51                 return 21;
  52         if (size <= 1 << 22)
  53                 return 22;
  54         if (size <= 1 << 30)
  55                 return 30;
  56         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  57         return sizeof(void *) * 8 - 1;
  58 }
  59
  60 static int page_roundup(size_t size)
  61 {
  62         return 1 << page_getenum(size);
  63 }
  64
  65 /*
  66  * HWRM Functions (sent to HWRM)
  67  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  68  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  69  * command was failed by the ChiMP.
  70  */
  71
  72 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  73                                   uint32_t msg_len, bool use_kong_mb)
  74 {
  75         unsigned int i;
  76         struct input *req = msg;
  77         struct output *resp = bp->hwrm_cmd_resp_addr;
  78         uint32_t *data = msg;
  79         uint8_t *bar;
  80         uint8_t *valid;
  81         uint16_t max_req_len = bp->max_req_len;
  82         struct hwrm_short_input short_input = { 0 };
  83         uint16_t bar_offset = use_kong_mb ?
  84                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  85         uint16_t mb_trigger_offset = use_kong_mb ?
  86                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  87
  88         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
  89             msg_len > bp->max_req_len) {
  90                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
  91
  92                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
  93                 memcpy(short_cmd_req, req, msg_len);
  94
  95                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
  96                 short_input.signature = rte_cpu_to_le_16(
  97                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
  98                 short_input.size = rte_cpu_to_le_16(msg_len);
  99                 short_input.req_addr =
 100                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 101
 102                 data = (uint32_t *)&short_input;
 103                 msg_len = sizeof(short_input);
 104
 105                 /* Sync memory write before updating doorbell */
 106                 rte_wmb();
 107
 108                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 109         }
 110
 111         /* Write request msg to hwrm channel */
 112         for (i = 0; i < msg_len; i += 4) {
 113                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 114                 rte_write32(*data, bar);
 115                 data++;
 116         }
 117
 118         /* Zero the rest of the request space */
 119         for (; i < max_req_len; i += 4) {
 120                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 121                 rte_write32(0, bar);
 122         }
 123
 124         /* Ring channel doorbell */
 125         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 126         rte_write32(1, bar);
 127
 128         /* Poll for the valid bit */
 129         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 130                 /* Sanity check on the resp->resp_len */
 131                 rte_rmb();
 132                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 133                         /* Last byte of resp contains the valid key */
 134                         valid = (uint8_t *)resp + resp->resp_len - 1;
 135                         if (*valid == HWRM_RESP_VALID_KEY)
 136                                 break;
 137                 }
 138                 rte_delay_us(1);
 139         }
 140
 141         if (i >= HWRM_CMD_TIMEOUT) {
 142                 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
 143                         req->req_type);
 144                 goto err_ret;
 145         }
 146         return 0;
 147
 148 err_ret:
 149         return -1;
 150 }
 151
 152 /*
 153  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 154  * spinlock, and does initial processing.
 155  *
 156  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 157  * releases the spinlock only if it returns.  If the regular int return codes
 158  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 159  * directly, rather it should be copied and modified to suit the function.
 160  *
 161  * HWRM_UNLOCK() must be called after all response processing is completed.
 162  */
 163 #define HWRM_PREP(req, type, kong) do { \
 164         rte_spinlock_lock(&bp->hwrm_lock); \
 165         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 166         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 167         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 168         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 169                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 170         req.target_id = rte_cpu_to_le_16(0xffff); \
 171         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 172 } while (0)
 173
 174 #define HWRM_CHECK_RESULT_SILENT() do {\
 175         if (rc) { \
 176                 rte_spinlock_unlock(&bp->hwrm_lock); \
 177                 return rc; \
 178         } \
 179         if (resp->error_code) { \
 180                 rc = rte_le_to_cpu_16(resp->error_code); \
 181                 rte_spinlock_unlock(&bp->hwrm_lock); \
 182                 return rc; \
 183         } \
 184 } while (0)
 185
 186 #define HWRM_CHECK_RESULT() do {\
 187         if (rc) { \
 188                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 191                         rc = -EACCES; \
 192                 else if (rc > 0) \
 193                         rc = -EINVAL; \
 194                 return rc; \
 195         } \
 196         if (resp->error_code) { \
 197                 rc = rte_le_to_cpu_16(resp->error_code); \
 198                 if (resp->resp_len >= 16) { \
 199                         struct hwrm_err_output *tmp_hwrm_err_op = \
 200                                                 (void *)resp; \
 201                         PMD_DRV_LOG(ERR, \
 202                                 "error %d:%d:%08x:%04x\n", \
 203                                 rc, tmp_hwrm_err_op->cmd_err, \
 204                                 rte_le_to_cpu_32(\
 205                                         tmp_hwrm_err_op->opaque_0), \
 206                                 rte_le_to_cpu_16(\
 207                                         tmp_hwrm_err_op->opaque_1)); \
 208                 } else { \
 209                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 210                 } \
 211                 rte_spinlock_unlock(&bp->hwrm_lock); \
 212                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 213                         rc = -EACCES; \
 214                 else if (rc > 0) \
 215                         rc = -EINVAL; \
 216                 return rc; \
 217         } \
 218 } while (0)
 219
 220 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 221
 222 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 223 {
 224         int rc = 0;
 225         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 226         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 227
 228         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 229         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 230         req.mask = 0;
 231
 232         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 233
 234         HWRM_CHECK_RESULT();
 235         HWRM_UNLOCK();
 236
 237         return rc;
 238 }
 239
 240 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 241                                  struct bnxt_vnic_info *vnic,
 242                                  uint16_t vlan_count,
 243                                  struct bnxt_vlan_table_entry *vlan_table)
 244 {
 245         int rc = 0;
 246         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 247         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 248         uint32_t mask = 0;
 249
 250         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 251                 return rc;
 252
 253         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 254         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 255
 256         /* FIXME add multicast flag, when multicast adding options is supported
 257          * by ethtool.
 258          */
 259         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 260                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 261         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 262                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 263         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 264                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 265         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 266                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 267         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 268                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 269         if (vnic->mc_addr_cnt) {
 270                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 271                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 272                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 273         }
 274         if (vlan_table) {
 275                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 276                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 277                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 278                          rte_mem_virt2iova(vlan_table));
 279                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 280         }
 281         req.mask = rte_cpu_to_le_32(mask);
 282
 283         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 284
 285         HWRM_CHECK_RESULT();
 286         HWRM_UNLOCK();
 287
 288         return rc;
 289 }
 290
 291 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 292                         uint16_t vlan_count,
 293                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 294 {
 295         int rc = 0;
 296         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 297         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 298                                                 bp->hwrm_cmd_resp_addr;
 299
 300         /*
 301          * Older HWRM versions did not support this command, and the set_rx_mask
 302          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 303          * removed from set_rx_mask call, and this command was added.
 304          *
 305          * This command is also present from 1.7.8.11 and higher,
 306          * as well as 1.7.8.0
 307          */
 308         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 309                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 310                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 311                                         (11)))
 312                                 return 0;
 313                 }
 314         }
 315         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 316         req.fid = rte_cpu_to_le_16(fid);
 317
 318         req.vlan_tag_mask_tbl_addr =
 319                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 320         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 321
 322         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 323
 324         HWRM_CHECK_RESULT();
 325         HWRM_UNLOCK();
 326
 327         return rc;
 328 }
 329
 330 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 331                            struct bnxt_filter_info *filter)
 332 {
 333         int rc = 0;
 334         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 335         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 336
 337         if (filter->fw_l2_filter_id == UINT64_MAX)
 338                 return 0;
 339
 340         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 341
 342         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 343
 344         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 345
 346         HWRM_CHECK_RESULT();
 347         HWRM_UNLOCK();
 348
 349         filter->fw_l2_filter_id = UINT64_MAX;
 350
 351         return 0;
 352 }
 353
 354 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 355                          uint16_t dst_id,
 356                          struct bnxt_filter_info *filter)
 357 {
 358         int rc = 0;
 359         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 360         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 361         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 362         const struct rte_eth_vmdq_rx_conf *conf =
 363                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 364         uint32_t enables = 0;
 365         uint16_t j = dst_id - 1;
 366
 367         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 368         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 369             conf->pool_map[j].pools & (1UL << j)) {
 370                 PMD_DRV_LOG(DEBUG,
 371                         "Add vlan %u to vmdq pool %u\n",
 372                         conf->pool_map[j].vlan_id, j);
 373
 374                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 375                 filter->enables |=
 376                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 377                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 378         }
 379
 380         if (filter->fw_l2_filter_id != UINT64_MAX)
 381                 bnxt_hwrm_clear_l2_filter(bp, filter);
 382
 383         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 384
 385         req.flags = rte_cpu_to_le_32(filter->flags);
 386         req.flags |=
 387         rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
 388
 389         enables = filter->enables |
 390               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 391         req.dst_id = rte_cpu_to_le_16(dst_id);
 392
 393         if (enables &
 394             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 395                 memcpy(req.l2_addr, filter->l2_addr,
 396                        RTE_ETHER_ADDR_LEN);
 397         if (enables &
 398             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 399                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 400                        RTE_ETHER_ADDR_LEN);
 401         if (enables &
 402             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 403                 req.l2_ovlan = filter->l2_ovlan;
 404         if (enables &
 405             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 406                 req.l2_ivlan = filter->l2_ivlan;
 407         if (enables &
 408             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 409                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 410         if (enables &
 411             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 412                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 413         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 414                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 415         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 416                 req.src_type = filter->src_type;
 417
 418         req.enables = rte_cpu_to_le_32(enables);
 419
 420         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 421
 422         HWRM_CHECK_RESULT();
 423
 424         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 425         HWRM_UNLOCK();
 426
 427         return rc;
 428 }
 429
 430 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 431 {
 432         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 433         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 434         uint32_t flags = 0;
 435         int rc;
 436
 437         if (!ptp)
 438                 return 0;
 439
 440         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 441
 442         if (ptp->rx_filter)
 443                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 444         else
 445                 flags |=
 446                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 447         if (ptp->tx_tstamp_en)
 448                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 449         else
 450                 flags |=
 451                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 452         req.flags = rte_cpu_to_le_32(flags);
 453         req.enables = rte_cpu_to_le_32
 454                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 455         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 456
 457         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 458         HWRM_UNLOCK();
 459
 460         return rc;
 461 }
 462
 463 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 464 {
 465         int rc = 0;
 466         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 467         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 468         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 469
 470 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 471         if (ptp)
 472                 return 0;
 473
 474         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 475
 476         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 477
 478         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 479
 480         HWRM_CHECK_RESULT();
 481
 482         if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 483                 return 0;
 484
 485         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 486         if (!ptp)
 487                 return -ENOMEM;
 488
 489         ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 490                 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 491         ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 492                 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 493         ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 494                 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 495         ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 496                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 497         ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 498                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 499         ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 500                 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 501         ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 502                 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 503         ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 504                 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 505         ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 506                 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 507
 508         ptp->bp = bp;
 509         bp->ptp_cfg = ptp;
 510
 511         return 0;
 512 }
 513
 514 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 515 {
 516         int rc = 0;
 517         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 518         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 519         uint16_t new_max_vfs;
 520         uint32_t flags;
 521         int i;
 522
 523         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 524
 525         req.fid = rte_cpu_to_le_16(0xffff);
 526
 527         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 528
 529         HWRM_CHECK_RESULT();
 530
 531         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 532         flags = rte_le_to_cpu_32(resp->flags);
 533         if (BNXT_PF(bp)) {
 534                 bp->pf.port_id = resp->port_id;
 535                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 536                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 537                 new_max_vfs = bp->pdev->max_vfs;
 538                 if (new_max_vfs != bp->pf.max_vfs) {
 539                         if (bp->pf.vf_info)
 540                                 rte_free(bp->pf.vf_info);
 541                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 542                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 543                         bp->pf.max_vfs = new_max_vfs;
 544                         for (i = 0; i < new_max_vfs; i++) {
 545                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 546                                 bp->pf.vf_info[i].vlan_table =
 547                                         rte_zmalloc("VF VLAN table",
 548                                                     getpagesize(),
 549                                                     getpagesize());
 550                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 551                                         PMD_DRV_LOG(ERR,
 552                                         "Fail to alloc VLAN table for VF %d\n",
 553                                         i);
 554                                 else
 555                                         rte_mem_lock_page(
 556                                                 bp->pf.vf_info[i].vlan_table);
 557                                 bp->pf.vf_info[i].vlan_as_table =
 558                                         rte_zmalloc("VF VLAN AS table",
 559                                                     getpagesize(),
 560                                                     getpagesize());
 561                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 562                                         PMD_DRV_LOG(ERR,
 563                                         "Alloc VLAN AS table for VF %d fail\n",
 564                                         i);
 565                                 else
 566                                         rte_mem_lock_page(
 567                                                bp->pf.vf_info[i].vlan_as_table);
 568                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 569                         }
 570                 }
 571         }
 572
 573         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 574         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 575         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 576         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 577         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 578         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 579         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 580         /* TODO: For now, do not support VMDq/RFS on VFs. */
 581         if (BNXT_PF(bp)) {
 582                 if (bp->pf.max_vfs)
 583                         bp->max_vnics = 1;
 584                 else
 585                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 586         } else {
 587                 bp->max_vnics = 1;
 588         }
 589         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 590         if (BNXT_PF(bp)) {
 591                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 592                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 593                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 594                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 595                         HWRM_UNLOCK();
 596                         bnxt_hwrm_ptp_qcfg(bp);
 597                 }
 598         }
 599
 600         HWRM_UNLOCK();
 601
 602         return rc;
 603 }
 604
 605 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 606 {
 607         int rc;
 608
 609         rc = __bnxt_hwrm_func_qcaps(bp);
 610         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 611                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 612                 if (!rc)
 613                         bp->flags |= BNXT_FLAG_NEW_RM;
 614         }
 615
 616         return rc;
 617 }
 618
 619 int bnxt_hwrm_func_reset(struct bnxt *bp)
 620 {
 621         int rc = 0;
 622         struct hwrm_func_reset_input req = {.req_type = 0 };
 623         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 624
 625         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 626
 627         req.enables = rte_cpu_to_le_32(0);
 628
 629         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 630
 631         HWRM_CHECK_RESULT();
 632         HWRM_UNLOCK();
 633
 634         return rc;
 635 }
 636
 637 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 638 {
 639         int rc;
 640         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 641         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 642
 643         if (bp->flags & BNXT_FLAG_REGISTERED)
 644                 return 0;
 645
 646         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 647         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 648                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 649         req.ver_maj = RTE_VER_YEAR;
 650         req.ver_min = RTE_VER_MONTH;
 651         req.ver_upd = RTE_VER_MINOR;
 652
 653         if (BNXT_PF(bp)) {
 654                 req.enables |= rte_cpu_to_le_32(
 655                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 656                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 657                        RTE_MIN(sizeof(req.vf_req_fwd),
 658                                sizeof(bp->pf.vf_req_fwd)));
 659
 660                 /*
 661                  * PF can sniff HWRM API issued by VF. This can be set up by
 662                  * linux driver and inherited by the DPDK PF driver. Clear
 663                  * this HWRM sniffer list in FW because DPDK PF driver does
 664                  * not support this.
 665                  */
 666                 req.flags =
 667                 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
 668         }
 669
 670         req.async_event_fwd[0] |=
 671                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 672                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 673                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
 674         req.async_event_fwd[1] |=
 675                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 676                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 677
 678         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 679
 680         HWRM_CHECK_RESULT();
 681         HWRM_UNLOCK();
 682
 683         bp->flags |= BNXT_FLAG_REGISTERED;
 684
 685         return rc;
 686 }
 687
 688 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 689 {
 690         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 691                 return 0;
 692
 693         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 694 }
 695
 696 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 697 {
 698         int rc;
 699         uint32_t flags = 0;
 700         uint32_t enables;
 701         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 702         struct hwrm_func_vf_cfg_input req = {0};
 703
 704         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 705
 706         req.enables = rte_cpu_to_le_32
 707                         (HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 708                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 709                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 710                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 711                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS |
 712                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS);
 713
 714         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 715         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 716                                             AGG_RING_MULTIPLIER);
 717         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 718         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 719                                               bp->tx_nr_rings);
 720         req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 721         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 722         if (bp->vf_resv_strategy ==
 723             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 724                 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 725                                 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 726                                 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 727                 req.enables |= rte_cpu_to_le_32(enables);
 728                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 729                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 730                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 731         }
 732
 733         if (test)
 734                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 735                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 736                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 737                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 738                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 739                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 740
 741         req.flags = rte_cpu_to_le_32(flags);
 742
 743         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 744
 745         if (test)
 746                 HWRM_CHECK_RESULT_SILENT();
 747         else
 748                 HWRM_CHECK_RESULT();
 749
 750         HWRM_UNLOCK();
 751         return rc;
 752 }
 753
 754 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 755 {
 756         int rc;
 757         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 758         struct hwrm_func_resource_qcaps_input req = {0};
 759
 760         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 761         req.fid = rte_cpu_to_le_16(0xffff);
 762
 763         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 764
 765         HWRM_CHECK_RESULT();
 766
 767         if (BNXT_VF(bp)) {
 768                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 769                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 770                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 771                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 772                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 773                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 774                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 775                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 776         }
 777         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 778         if (bp->vf_resv_strategy >
 779             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 780                 bp->vf_resv_strategy =
 781                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 782
 783         HWRM_UNLOCK();
 784         return rc;
 785 }
 786
 787 int bnxt_hwrm_ver_get(struct bnxt *bp)
 788 {
 789         int rc = 0;
 790         struct hwrm_ver_get_input req = {.req_type = 0 };
 791         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 792         uint32_t fw_version;
 793         uint16_t max_resp_len;
 794         char type[RTE_MEMZONE_NAMESIZE];
 795         uint32_t dev_caps_cfg;
 796
 797         bp->max_req_len = HWRM_MAX_REQ_LEN;
 798         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 799
 800         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 801         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 802         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 803
 804         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 805
 806         HWRM_CHECK_RESULT();
 807
 808         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 809                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 810                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 811                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 812         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 813                      (resp->hwrm_fw_min_8b << 16) |
 814                      (resp->hwrm_fw_bld_8b << 8) |
 815                      resp->hwrm_fw_rsvd_8b;
 816         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 817                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 818
 819         fw_version = resp->hwrm_intf_maj_8b << 16;
 820         fw_version |= resp->hwrm_intf_min_8b << 8;
 821         fw_version |= resp->hwrm_intf_upd_8b;
 822         bp->hwrm_spec_code = fw_version;
 823
 824         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 825                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 826                 rc = -EINVAL;
 827                 goto error;
 828         }
 829
 830         if (bp->max_req_len > resp->max_req_win_len) {
 831                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 832                 rc = -EINVAL;
 833         }
 834         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 835         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 836         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 837                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 838
 839         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 840         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 841
 842         if (bp->max_resp_len != max_resp_len) {
 843                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 844                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 845                         bp->pdev->addr.devid, bp->pdev->addr.function);
 846
 847                 rte_free(bp->hwrm_cmd_resp_addr);
 848
 849                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 850                 if (bp->hwrm_cmd_resp_addr == NULL) {
 851                         rc = -ENOMEM;
 852                         goto error;
 853                 }
 854                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 855                 bp->hwrm_cmd_resp_dma_addr =
 856                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 857                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 858                         PMD_DRV_LOG(ERR,
 859                         "Unable to map response buffer to physical memory.\n");
 860                         rc = -ENOMEM;
 861                         goto error;
 862                 }
 863                 bp->max_resp_len = max_resp_len;
 864         }
 865
 866         if ((dev_caps_cfg &
 867                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 868             (dev_caps_cfg &
 869              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 870                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 871                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 872         }
 873
 874         if (((dev_caps_cfg &
 875               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 876              (dev_caps_cfg &
 877               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
 878             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
 879                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
 880                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 881                         bp->pdev->addr.devid, bp->pdev->addr.function);
 882
 883                 rte_free(bp->hwrm_short_cmd_req_addr);
 884
 885                 bp->hwrm_short_cmd_req_addr =
 886                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
 887                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 888                         rc = -ENOMEM;
 889                         goto error;
 890                 }
 891                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 892                 bp->hwrm_short_cmd_req_dma_addr =
 893                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 894                 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
 895                         rte_free(bp->hwrm_short_cmd_req_addr);
 896                         PMD_DRV_LOG(ERR,
 897                                 "Unable to map buffer to physical memory.\n");
 898                         rc = -ENOMEM;
 899                         goto error;
 900                 }
 901         }
 902         if (dev_caps_cfg &
 903             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
 904                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
 905                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
 906         }
 907         if (dev_caps_cfg &
 908             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
 909                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
 910
 911 error:
 912         HWRM_UNLOCK();
 913         return rc;
 914 }
 915
 916 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 917 {
 918         int rc;
 919         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 920         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 921
 922         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 923                 return 0;
 924
 925         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
 926         req.flags = flags;
 927
 928         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 929
 930         HWRM_CHECK_RESULT();
 931         HWRM_UNLOCK();
 932
 933         bp->flags &= ~BNXT_FLAG_REGISTERED;
 934
 935         return rc;
 936 }
 937
 938 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 939 {
 940         int rc = 0;
 941         struct hwrm_port_phy_cfg_input req = {0};
 942         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 943         uint32_t enables = 0;
 944
 945         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
 946
 947         if (conf->link_up) {
 948                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
 949                 if (bp->link_info.auto_mode && conf->link_speed) {
 950                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
 951                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
 952                 }
 953
 954                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 955                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 956                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 957                 /*
 958                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 959                  * any auto mode, even "none".
 960                  */
 961                 if (!conf->link_speed) {
 962                         /* No speeds specified. Enable AutoNeg - all speeds */
 963                         req.auto_mode =
 964                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
 965                 }
 966                 /* AutoNeg - Advertise speeds specified. */
 967                 if (conf->auto_link_speed_mask &&
 968                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
 969                         req.auto_mode =
 970                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
 971                         req.auto_link_speed_mask =
 972                                 conf->auto_link_speed_mask;
 973                         enables |=
 974                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 975                 }
 976
 977                 req.auto_duplex = conf->duplex;
 978                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 979                 req.auto_pause = conf->auto_pause;
 980                 req.force_pause = conf->force_pause;
 981                 /* Set force_pause if there is no auto or if there is a force */
 982                 if (req.auto_pause && !req.force_pause)
 983                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 984                 else
 985                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 986
 987                 req.enables = rte_cpu_to_le_32(enables);
 988         } else {
 989                 req.flags =
 990                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
 991                 PMD_DRV_LOG(INFO, "Force Link Down\n");
 992         }
 993
 994         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 995
 996         HWRM_CHECK_RESULT();
 997         HWRM_UNLOCK();
 998
 999         return rc;
1000 }
1001
1002 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1003                                    struct bnxt_link_info *link_info)
1004 {
1005         int rc = 0;
1006         struct hwrm_port_phy_qcfg_input req = {0};
1007         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1008
1009         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1010
1011         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1012
1013         HWRM_CHECK_RESULT();
1014
1015         link_info->phy_link_status = resp->link;
1016         link_info->link_up =
1017                 (link_info->phy_link_status ==
1018                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1019         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1020         link_info->duplex = resp->duplex_cfg;
1021         link_info->pause = resp->pause;
1022         link_info->auto_pause = resp->auto_pause;
1023         link_info->force_pause = resp->force_pause;
1024         link_info->auto_mode = resp->auto_mode;
1025         link_info->phy_type = resp->phy_type;
1026         link_info->media_type = resp->media_type;
1027
1028         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1029         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1030         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1031         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1032         link_info->phy_ver[0] = resp->phy_maj;
1033         link_info->phy_ver[1] = resp->phy_min;
1034         link_info->phy_ver[2] = resp->phy_bld;
1035
1036         HWRM_UNLOCK();
1037
1038         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1039         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1040         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1041         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1042         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1043                     link_info->auto_link_speed_mask);
1044         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1045                     link_info->force_link_speed);
1046
1047         return rc;
1048 }
1049
1050 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1051 {
1052         int rc = 0;
1053         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1054         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1055         int i;
1056
1057         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1058
1059         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1060         /* HWRM Version >= 1.9.1 */
1061         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1062                 req.drv_qmap_cap =
1063                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1064         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1065
1066         HWRM_CHECK_RESULT();
1067
1068 #define GET_QUEUE_INFO(x) \
1069         bp->cos_queue[x].id = resp->queue_id##x; \
1070         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1071
1072         GET_QUEUE_INFO(0);
1073         GET_QUEUE_INFO(1);
1074         GET_QUEUE_INFO(2);
1075         GET_QUEUE_INFO(3);
1076         GET_QUEUE_INFO(4);
1077         GET_QUEUE_INFO(5);
1078         GET_QUEUE_INFO(6);
1079         GET_QUEUE_INFO(7);
1080
1081         HWRM_UNLOCK();
1082
1083         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1084                 bp->tx_cosq_id = bp->cos_queue[0].id;
1085         } else {
1086                 /* iterate and find the COSq profile to use for Tx */
1087                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1088                         if (bp->cos_queue[i].profile ==
1089                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1090                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1091                                 break;
1092                         }
1093                 }
1094         }
1095         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1096
1097         return rc;
1098 }
1099
1100 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1101                          struct bnxt_ring *ring,
1102                          uint32_t ring_type, uint32_t map_index,
1103                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1104 {
1105         int rc = 0;
1106         uint32_t enables = 0;
1107         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1108         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1109
1110         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1111
1112         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1113         req.fbo = rte_cpu_to_le_32(0);
1114         /* Association of ring index with doorbell index */
1115         req.logical_id = rte_cpu_to_le_16(map_index);
1116         req.length = rte_cpu_to_le_32(ring->ring_size);
1117
1118         switch (ring_type) {
1119         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1120                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1121                 /* FALLTHROUGH */
1122         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1123                 req.ring_type = ring_type;
1124                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1125                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1126                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1127                         enables |=
1128                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1129                 break;
1130         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1131                 req.ring_type = ring_type;
1132                 /*
1133                  * TODO: Some HWRM versions crash with
1134                  * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
1135                  */
1136                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1137                 break;
1138         default:
1139                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1140                         ring_type);
1141                 HWRM_UNLOCK();
1142                 return -1;
1143         }
1144         req.enables = rte_cpu_to_le_32(enables);
1145
1146         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1147
1148         if (rc || resp->error_code) {
1149                 if (rc == 0 && resp->error_code)
1150                         rc = rte_le_to_cpu_16(resp->error_code);
1151                 switch (ring_type) {
1152                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1153                         PMD_DRV_LOG(ERR,
1154                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1155                         HWRM_UNLOCK();
1156                         return rc;
1157                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1158                         PMD_DRV_LOG(ERR,
1159                                 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1160                         HWRM_UNLOCK();
1161                         return rc;
1162                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1163                         PMD_DRV_LOG(ERR,
1164                                 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1165                         HWRM_UNLOCK();
1166                         return rc;
1167                 default:
1168                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1169                         HWRM_UNLOCK();
1170                         return rc;
1171                 }
1172         }
1173
1174         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1175         HWRM_UNLOCK();
1176         return rc;
1177 }
1178
1179 int bnxt_hwrm_ring_free(struct bnxt *bp,
1180                         struct bnxt_ring *ring, uint32_t ring_type)
1181 {
1182         int rc;
1183         struct hwrm_ring_free_input req = {.req_type = 0 };
1184         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1185
1186         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1187
1188         req.ring_type = ring_type;
1189         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1190
1191         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1192
1193         if (rc || resp->error_code) {
1194                 if (rc == 0 && resp->error_code)
1195                         rc = rte_le_to_cpu_16(resp->error_code);
1196                 HWRM_UNLOCK();
1197
1198                 switch (ring_type) {
1199                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1200                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1201                                 rc);
1202                         return rc;
1203                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1204                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1205                                 rc);
1206                         return rc;
1207                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1208                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1209                                 rc);
1210                         return rc;
1211                 default:
1212                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1213                         return rc;
1214                 }
1215         }
1216         HWRM_UNLOCK();
1217         return 0;
1218 }
1219
1220 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1221 {
1222         int rc = 0;
1223         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1224         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1225
1226         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1227
1228         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1229         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1230         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1231         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1232
1233         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1234
1235         HWRM_CHECK_RESULT();
1236
1237         bp->grp_info[idx].fw_grp_id =
1238             rte_le_to_cpu_16(resp->ring_group_id);
1239
1240         HWRM_UNLOCK();
1241
1242         return rc;
1243 }
1244
1245 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1246 {
1247         int rc;
1248         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1249         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1250
1251         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1252
1253         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1254
1255         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1256
1257         HWRM_CHECK_RESULT();
1258         HWRM_UNLOCK();
1259
1260         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1261         return rc;
1262 }
1263
1264 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1265 {
1266         int rc = 0;
1267         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1268         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1269
1270         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1271                 return rc;
1272
1273         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1274
1275         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1276
1277         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1278
1279         HWRM_CHECK_RESULT();
1280         HWRM_UNLOCK();
1281
1282         return rc;
1283 }
1284
1285 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1286                                 unsigned int idx __rte_unused)
1287 {
1288         int rc;
1289         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1290         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1291
1292         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1293
1294         req.update_period_ms = rte_cpu_to_le_32(0);
1295
1296         req.stats_dma_addr =
1297             rte_cpu_to_le_64(cpr->hw_stats_map);
1298
1299         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1300
1301         HWRM_CHECK_RESULT();
1302
1303         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1304
1305         HWRM_UNLOCK();
1306
1307         return rc;
1308 }
1309
1310 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1311                                 unsigned int idx __rte_unused)
1312 {
1313         int rc;
1314         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1315         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1316
1317         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1318
1319         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1320
1321         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1322
1323         HWRM_CHECK_RESULT();
1324         HWRM_UNLOCK();
1325
1326         return rc;
1327 }
1328
1329 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1330 {
1331         int rc = 0, i, j;
1332         struct hwrm_vnic_alloc_input req = { 0 };
1333         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1334
1335         /* map ring groups to this vnic */
1336         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1337                 vnic->start_grp_id, vnic->end_grp_id);
1338         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1339                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1340
1341         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1342         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1343         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1344         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1345         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1346                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1347         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1348
1349         if (vnic->func_default)
1350                 req.flags =
1351                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1352         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1353
1354         HWRM_CHECK_RESULT();
1355
1356         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1357         HWRM_UNLOCK();
1358         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1359         return rc;
1360 }
1361
1362 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1363                                         struct bnxt_vnic_info *vnic,
1364                                         struct bnxt_plcmodes_cfg *pmode)
1365 {
1366         int rc = 0;
1367         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1368         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1369
1370         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1371
1372         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1373
1374         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1375
1376         HWRM_CHECK_RESULT();
1377
1378         pmode->flags = rte_le_to_cpu_32(resp->flags);
1379         /* dflt_vnic bit doesn't exist in the _cfg command */
1380         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1381         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1382         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1383         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1384
1385         HWRM_UNLOCK();
1386
1387         return rc;
1388 }
1389
1390 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1391                                        struct bnxt_vnic_info *vnic,
1392                                        struct bnxt_plcmodes_cfg *pmode)
1393 {
1394         int rc = 0;
1395         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1396         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1397
1398         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1399
1400         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1401         req.flags = rte_cpu_to_le_32(pmode->flags);
1402         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1403         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1404         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1405         req.enables = rte_cpu_to_le_32(
1406             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1407             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1408             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1409         );
1410
1411         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1412
1413         HWRM_CHECK_RESULT();
1414         HWRM_UNLOCK();
1415
1416         return rc;
1417 }
1418
1419 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1420 {
1421         int rc = 0;
1422         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1423         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1424         uint32_t ctx_enable_flag = 0;
1425         struct bnxt_plcmodes_cfg pmodes;
1426
1427         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1428                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1429                 return rc;
1430         }
1431
1432         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1433         if (rc)
1434                 return rc;
1435
1436         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1437
1438         /* Only RSS support for now TBD: COS & LB */
1439         req.enables =
1440             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1441         if (vnic->lb_rule != 0xffff)
1442                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1443         if (vnic->cos_rule != 0xffff)
1444                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1445         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1446                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1447                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1448         }
1449         req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1450         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1451         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1452         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1453         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1454         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1455         req.mru = rte_cpu_to_le_16(vnic->mru);
1456         /* Configure default VNIC only once. */
1457         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1458                 req.flags |=
1459                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1460                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1461         }
1462         if (vnic->vlan_strip)
1463                 req.flags |=
1464                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1465         if (vnic->bd_stall)
1466                 req.flags |=
1467                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1468         if (vnic->roce_dual)
1469                 req.flags |= rte_cpu_to_le_32(
1470                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1471         if (vnic->roce_only)
1472                 req.flags |= rte_cpu_to_le_32(
1473                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1474         if (vnic->rss_dflt_cr)
1475                 req.flags |= rte_cpu_to_le_32(
1476                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1477
1478         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1479
1480         HWRM_CHECK_RESULT();
1481         HWRM_UNLOCK();
1482
1483         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1484
1485         return rc;
1486 }
1487
1488 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1489                 int16_t fw_vf_id)
1490 {
1491         int rc = 0;
1492         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1493         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1494
1495         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1496                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1497                 return rc;
1498         }
1499         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1500
1501         req.enables =
1502                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1503         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1504         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1505
1506         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1507
1508         HWRM_CHECK_RESULT();
1509
1510         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1511         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1512         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1513         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1514         vnic->mru = rte_le_to_cpu_16(resp->mru);
1515         vnic->func_default = rte_le_to_cpu_32(
1516                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1517         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1518                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1519         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1520                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1521         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1522                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1523         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1524                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1525         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1526                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1527
1528         HWRM_UNLOCK();
1529
1530         return rc;
1531 }
1532
1533 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1534 {
1535         int rc = 0;
1536         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1537         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1538                                                 bp->hwrm_cmd_resp_addr;
1539
1540         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1541
1542         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1543
1544         HWRM_CHECK_RESULT();
1545
1546         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1547         HWRM_UNLOCK();
1548         PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1549
1550         return rc;
1551 }
1552
1553 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1554 {
1555         int rc = 0;
1556         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1557         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1558                                                 bp->hwrm_cmd_resp_addr;
1559
1560         if (vnic->rss_rule == (uint16_t)HWRM_NA_SIGNATURE) {
1561                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1562                 return rc;
1563         }
1564         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1565
1566         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1567
1568         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1569
1570         HWRM_CHECK_RESULT();
1571         HWRM_UNLOCK();
1572
1573         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1574
1575         return rc;
1576 }
1577
1578 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1579 {
1580         int rc = 0;
1581         struct hwrm_vnic_free_input req = {.req_type = 0 };
1582         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1583
1584         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1585                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1586                 return rc;
1587         }
1588
1589         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1590
1591         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1592
1593         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1594
1595         HWRM_CHECK_RESULT();
1596         HWRM_UNLOCK();
1597
1598         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1599         /* Configure default VNIC again if necessary. */
1600         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1601                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1602
1603         return rc;
1604 }
1605
1606 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1607                            struct bnxt_vnic_info *vnic)
1608 {
1609         int rc = 0;
1610         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1611         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1612
1613         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1614
1615         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1616         req.hash_mode_flags = vnic->hash_mode;
1617
1618         req.ring_grp_tbl_addr =
1619             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1620         req.hash_key_tbl_addr =
1621             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1622         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1623         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1624
1625         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1626
1627         HWRM_CHECK_RESULT();
1628         HWRM_UNLOCK();
1629
1630         return rc;
1631 }
1632
1633 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1634                         struct bnxt_vnic_info *vnic)
1635 {
1636         int rc = 0;
1637         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1638         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1639         uint16_t size;
1640
1641         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1642                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1643                 return rc;
1644         }
1645
1646         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1647
1648         req.flags = rte_cpu_to_le_32(
1649                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1650
1651         req.enables = rte_cpu_to_le_32(
1652                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1653
1654         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1655         size -= RTE_PKTMBUF_HEADROOM;
1656
1657         req.jumbo_thresh = rte_cpu_to_le_16(size);
1658         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1659
1660         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1661
1662         HWRM_CHECK_RESULT();
1663         HWRM_UNLOCK();
1664
1665         return rc;
1666 }
1667
1668 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1669                         struct bnxt_vnic_info *vnic, bool enable)
1670 {
1671         int rc = 0;
1672         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1673         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1674
1675         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1676
1677         if (enable) {
1678                 req.enables = rte_cpu_to_le_32(
1679                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1680                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1681                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1682                 req.flags = rte_cpu_to_le_32(
1683                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1684                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1685                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1686                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1687                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1688                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1689                 req.max_agg_segs = rte_cpu_to_le_16(5);
1690                 req.max_aggs =
1691                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1692                 req.min_agg_len = rte_cpu_to_le_32(512);
1693         }
1694         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1695
1696         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1697
1698         HWRM_CHECK_RESULT();
1699         HWRM_UNLOCK();
1700
1701         return rc;
1702 }
1703
1704 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1705 {
1706         struct hwrm_func_cfg_input req = {0};
1707         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1708         int rc;
1709
1710         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1711         req.enables = rte_cpu_to_le_32(
1712                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1713         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1714         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1715
1716         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1717
1718         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1719         HWRM_CHECK_RESULT();
1720         HWRM_UNLOCK();
1721
1722         bp->pf.vf_info[vf].random_mac = false;
1723
1724         return rc;
1725 }
1726
1727 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1728                                   uint64_t *dropped)
1729 {
1730         int rc = 0;
1731         struct hwrm_func_qstats_input req = {.req_type = 0};
1732         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1733
1734         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1735
1736         req.fid = rte_cpu_to_le_16(fid);
1737
1738         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1739
1740         HWRM_CHECK_RESULT();
1741
1742         if (dropped)
1743                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1744
1745         HWRM_UNLOCK();
1746
1747         return rc;
1748 }
1749
1750 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1751                           struct rte_eth_stats *stats)
1752 {
1753         int rc = 0;
1754         struct hwrm_func_qstats_input req = {.req_type = 0};
1755         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1756
1757         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1758
1759         req.fid = rte_cpu_to_le_16(fid);
1760
1761         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1762
1763         HWRM_CHECK_RESULT();
1764
1765         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1766         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1767         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1768         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1769         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1770         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1771
1772         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1773         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1774         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1775         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1776         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1777         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1778
1779         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1780         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1781         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1782
1783         HWRM_UNLOCK();
1784
1785         return rc;
1786 }
1787
1788 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1789 {
1790         int rc = 0;
1791         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1792         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1793
1794         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1795
1796         req.fid = rte_cpu_to_le_16(fid);
1797
1798         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1799
1800         HWRM_CHECK_RESULT();
1801         HWRM_UNLOCK();
1802
1803         return rc;
1804 }
1805
1806 /*
1807  * HWRM utility functions
1808  */
1809
1810 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1811 {
1812         unsigned int i;
1813         int rc = 0;
1814
1815         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1816                 struct bnxt_tx_queue *txq;
1817                 struct bnxt_rx_queue *rxq;
1818                 struct bnxt_cp_ring_info *cpr;
1819
1820                 if (i >= bp->rx_cp_nr_rings) {
1821                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1822                         cpr = txq->cp_ring;
1823                 } else {
1824                         rxq = bp->rx_queues[i];
1825                         cpr = rxq->cp_ring;
1826                 }
1827
1828                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1829                 if (rc)
1830                         return rc;
1831         }
1832         return 0;
1833 }
1834
1835 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1836 {
1837         int rc;
1838         unsigned int i;
1839         struct bnxt_cp_ring_info *cpr;
1840
1841         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1842
1843                 if (i >= bp->rx_cp_nr_rings) {
1844                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1845                 } else {
1846                         cpr = bp->rx_queues[i]->cp_ring;
1847                         bp->grp_info[i].fw_stats_ctx = -1;
1848                 }
1849                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1850                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1851                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1852                         if (rc)
1853                                 return rc;
1854                 }
1855         }
1856         return 0;
1857 }
1858
1859 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1860 {
1861         unsigned int i;
1862         int rc = 0;
1863
1864         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1865                 struct bnxt_tx_queue *txq;
1866                 struct bnxt_rx_queue *rxq;
1867                 struct bnxt_cp_ring_info *cpr;
1868
1869                 if (i >= bp->rx_cp_nr_rings) {
1870                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1871                         cpr = txq->cp_ring;
1872                 } else {
1873                         rxq = bp->rx_queues[i];
1874                         cpr = rxq->cp_ring;
1875                 }
1876
1877                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1878
1879                 if (rc)
1880                         return rc;
1881         }
1882         return rc;
1883 }
1884
1885 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1886 {
1887         uint16_t idx;
1888         uint32_t rc = 0;
1889
1890         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1891
1892                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1893                         continue;
1894
1895                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1896
1897                 if (rc)
1898                         return rc;
1899         }
1900         return rc;
1901 }
1902
1903 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1904 {
1905         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1906
1907         bnxt_hwrm_ring_free(bp, cp_ring,
1908                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1909         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1910         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1911                         sizeof(*cpr->cp_desc_ring));
1912         cpr->cp_raw_cons = 0;
1913 }
1914
1915 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
1916 {
1917         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
1918         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1919         struct bnxt_ring *ring = rxr->rx_ring_struct;
1920         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1921
1922         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1923                 bnxt_hwrm_ring_free(bp, ring,
1924                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1925                 ring->fw_ring_id = INVALID_HW_RING_ID;
1926                 bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID;
1927                 memset(rxr->rx_desc_ring, 0,
1928                        rxr->rx_ring_struct->ring_size *
1929                        sizeof(*rxr->rx_desc_ring));
1930                 memset(rxr->rx_buf_ring, 0,
1931                        rxr->rx_ring_struct->ring_size *
1932                        sizeof(*rxr->rx_buf_ring));
1933                 rxr->rx_prod = 0;
1934         }
1935         ring = rxr->ag_ring_struct;
1936         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1937                 bnxt_hwrm_ring_free(bp, ring,
1938                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1939                 ring->fw_ring_id = INVALID_HW_RING_ID;
1940                 memset(rxr->ag_buf_ring, 0,
1941                        rxr->ag_ring_struct->ring_size *
1942                        sizeof(*rxr->ag_buf_ring));
1943                 rxr->ag_prod = 0;
1944                 bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID;
1945         }
1946         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1947                 bnxt_free_cp_ring(bp, cpr);
1948
1949         bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
1950 }
1951
1952 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1953 {
1954         unsigned int i;
1955
1956         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1957                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1958                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1959                 struct bnxt_ring *ring = txr->tx_ring_struct;
1960                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1961
1962                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1963                         bnxt_hwrm_ring_free(bp, ring,
1964                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1965                         ring->fw_ring_id = INVALID_HW_RING_ID;
1966                         memset(txr->tx_desc_ring, 0,
1967                                         txr->tx_ring_struct->ring_size *
1968                                         sizeof(*txr->tx_desc_ring));
1969                         memset(txr->tx_buf_ring, 0,
1970                                         txr->tx_ring_struct->ring_size *
1971                                         sizeof(*txr->tx_buf_ring));
1972                         txr->tx_prod = 0;
1973                         txr->tx_cons = 0;
1974                 }
1975                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1976                         bnxt_free_cp_ring(bp, cpr);
1977                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1978                 }
1979         }
1980
1981         for (i = 0; i < bp->rx_cp_nr_rings; i++)
1982                 bnxt_free_hwrm_rx_ring(bp, i);
1983
1984         return 0;
1985 }
1986
1987 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1988 {
1989         uint16_t i;
1990         uint32_t rc = 0;
1991
1992         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1993                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1994                 if (rc)
1995                         return rc;
1996         }
1997         return rc;
1998 }
1999
2000 void bnxt_free_hwrm_resources(struct bnxt *bp)
2001 {
2002         /* Release memzone */
2003         rte_free(bp->hwrm_cmd_resp_addr);
2004         rte_free(bp->hwrm_short_cmd_req_addr);
2005         bp->hwrm_cmd_resp_addr = NULL;
2006         bp->hwrm_short_cmd_req_addr = NULL;
2007         bp->hwrm_cmd_resp_dma_addr = 0;
2008         bp->hwrm_short_cmd_req_dma_addr = 0;
2009 }
2010
2011 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2012 {
2013         struct rte_pci_device *pdev = bp->pdev;
2014         char type[RTE_MEMZONE_NAMESIZE];
2015
2016         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2017                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2018         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2019         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2020         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2021         if (bp->hwrm_cmd_resp_addr == NULL)
2022                 return -ENOMEM;
2023         bp->hwrm_cmd_resp_dma_addr =
2024                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2025         if (bp->hwrm_cmd_resp_dma_addr == 0) {
2026                 PMD_DRV_LOG(ERR,
2027                         "unable to map response address to physical memory\n");
2028                 return -ENOMEM;
2029         }
2030         rte_spinlock_init(&bp->hwrm_lock);
2031
2032         return 0;
2033 }
2034
2035 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2036 {
2037         struct bnxt_filter_info *filter;
2038         int rc = 0;
2039
2040         STAILQ_FOREACH(filter, &vnic->filter, next) {
2041                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2042                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2043                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2044                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2045                 else
2046                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2047                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2048                 //if (rc)
2049                         //break;
2050         }
2051         return rc;
2052 }
2053
2054 static int
2055 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2056 {
2057         struct bnxt_filter_info *filter;
2058         struct rte_flow *flow;
2059         int rc = 0;
2060
2061         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2062                 filter = flow->filter;
2063                 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
2064                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2065                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2066                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2067                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2068                 else
2069                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2070
2071                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2072                 rte_free(flow);
2073                 //if (rc)
2074                         //break;
2075         }
2076         return rc;
2077 }
2078
2079 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2080 {
2081         struct bnxt_filter_info *filter;
2082         int rc = 0;
2083
2084         STAILQ_FOREACH(filter, &vnic->filter, next) {
2085                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2086                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2087                                                      filter);
2088                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2089                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2090                                                          filter);
2091                 else
2092                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2093                                                      filter);
2094                 if (rc)
2095                         break;
2096         }
2097         return rc;
2098 }
2099
2100 void bnxt_free_tunnel_ports(struct bnxt *bp)
2101 {
2102         if (bp->vxlan_port_cnt)
2103                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2104                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2105         bp->vxlan_port = 0;
2106         if (bp->geneve_port_cnt)
2107                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2108                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2109         bp->geneve_port = 0;
2110 }
2111
2112 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2113 {
2114         int i;
2115
2116         if (bp->vnic_info == NULL)
2117                 return;
2118
2119         /*
2120          * Cleanup VNICs in reverse order, to make sure the L2 filter
2121          * from vnic0 is last to be cleaned up.
2122          */
2123         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2124                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2125
2126                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2127
2128                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2129
2130                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2131
2132                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2133
2134                 bnxt_hwrm_vnic_free(bp, vnic);
2135
2136                 rte_free(vnic->fw_grp_ids);
2137         }
2138         /* Ring resources */
2139         bnxt_free_all_hwrm_rings(bp);
2140         bnxt_free_all_hwrm_ring_grps(bp);
2141         bnxt_free_all_hwrm_stat_ctxs(bp);
2142         bnxt_free_tunnel_ports(bp);
2143 }
2144
2145 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2146 {
2147         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2148
2149         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2150                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2151
2152         switch (conf_link_speed) {
2153         case ETH_LINK_SPEED_10M_HD:
2154         case ETH_LINK_SPEED_100M_HD:
2155                 /* FALLTHROUGH */
2156                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2157         }
2158         return hw_link_duplex;
2159 }
2160
2161 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2162 {
2163         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2164 }
2165
2166 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2167 {
2168         uint16_t eth_link_speed = 0;
2169
2170         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2171                 return ETH_LINK_SPEED_AUTONEG;
2172
2173         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2174         case ETH_LINK_SPEED_100M:
2175         case ETH_LINK_SPEED_100M_HD:
2176                 /* FALLTHROUGH */
2177                 eth_link_speed =
2178                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2179                 break;
2180         case ETH_LINK_SPEED_1G:
2181                 eth_link_speed =
2182                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2183                 break;
2184         case ETH_LINK_SPEED_2_5G:
2185                 eth_link_speed =
2186                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2187                 break;
2188         case ETH_LINK_SPEED_10G:
2189                 eth_link_speed =
2190                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2191                 break;
2192         case ETH_LINK_SPEED_20G:
2193                 eth_link_speed =
2194                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2195                 break;
2196         case ETH_LINK_SPEED_25G:
2197                 eth_link_speed =
2198                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2199                 break;
2200         case ETH_LINK_SPEED_40G:
2201                 eth_link_speed =
2202                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2203                 break;
2204         case ETH_LINK_SPEED_50G:
2205                 eth_link_speed =
2206                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2207                 break;
2208         case ETH_LINK_SPEED_100G:
2209                 eth_link_speed =
2210                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2211                 break;
2212         default:
2213                 PMD_DRV_LOG(ERR,
2214                         "Unsupported link speed %d; default to AUTO\n",
2215                         conf_link_speed);
2216                 break;
2217         }
2218         return eth_link_speed;
2219 }
2220
2221 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2222                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2223                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2224                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2225
2226 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2227 {
2228         uint32_t one_speed;
2229
2230         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2231                 return 0;
2232
2233         if (link_speed & ETH_LINK_SPEED_FIXED) {
2234                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2235
2236                 if (one_speed & (one_speed - 1)) {
2237                         PMD_DRV_LOG(ERR,
2238                                 "Invalid advertised speeds (%u) for port %u\n",
2239                                 link_speed, port_id);
2240                         return -EINVAL;
2241                 }
2242                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2243                         PMD_DRV_LOG(ERR,
2244                                 "Unsupported advertised speed (%u) for port %u\n",
2245                                 link_speed, port_id);
2246                         return -EINVAL;
2247                 }
2248         } else {
2249                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2250                         PMD_DRV_LOG(ERR,
2251                                 "Unsupported advertised speeds (%u) for port %u\n",
2252                                 link_speed, port_id);
2253                         return -EINVAL;
2254                 }
2255         }
2256         return 0;
2257 }
2258
2259 static uint16_t
2260 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2261 {
2262         uint16_t ret = 0;
2263
2264         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2265                 if (bp->link_info.support_speeds)
2266                         return bp->link_info.support_speeds;
2267                 link_speed = BNXT_SUPPORTED_SPEEDS;
2268         }
2269
2270         if (link_speed & ETH_LINK_SPEED_100M)
2271                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2272         if (link_speed & ETH_LINK_SPEED_100M_HD)
2273                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2274         if (link_speed & ETH_LINK_SPEED_1G)
2275                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2276         if (link_speed & ETH_LINK_SPEED_2_5G)
2277                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2278         if (link_speed & ETH_LINK_SPEED_10G)
2279                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2280         if (link_speed & ETH_LINK_SPEED_20G)
2281                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2282         if (link_speed & ETH_LINK_SPEED_25G)
2283                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2284         if (link_speed & ETH_LINK_SPEED_40G)
2285                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2286         if (link_speed & ETH_LINK_SPEED_50G)
2287                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2288         if (link_speed & ETH_LINK_SPEED_100G)
2289                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2290         return ret;
2291 }
2292
2293 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2294 {
2295         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2296
2297         switch (hw_link_speed) {
2298         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2299                 eth_link_speed = ETH_SPEED_NUM_100M;
2300                 break;
2301         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2302                 eth_link_speed = ETH_SPEED_NUM_1G;
2303                 break;
2304         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2305                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2306                 break;
2307         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2308                 eth_link_speed = ETH_SPEED_NUM_10G;
2309                 break;
2310         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2311                 eth_link_speed = ETH_SPEED_NUM_20G;
2312                 break;
2313         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2314                 eth_link_speed = ETH_SPEED_NUM_25G;
2315                 break;
2316         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2317                 eth_link_speed = ETH_SPEED_NUM_40G;
2318                 break;
2319         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2320                 eth_link_speed = ETH_SPEED_NUM_50G;
2321                 break;
2322         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2323                 eth_link_speed = ETH_SPEED_NUM_100G;
2324                 break;
2325         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2326         default:
2327                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2328                         hw_link_speed);
2329                 break;
2330         }
2331         return eth_link_speed;
2332 }
2333
2334 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2335 {
2336         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2337
2338         switch (hw_link_duplex) {
2339         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2340         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2341                 /* FALLTHROUGH */
2342                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2343                 break;
2344         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2345                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2346                 break;
2347         default:
2348                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2349                         hw_link_duplex);
2350                 break;
2351         }
2352         return eth_link_duplex;
2353 }
2354
2355 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2356 {
2357         int rc = 0;
2358         struct bnxt_link_info *link_info = &bp->link_info;
2359
2360         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2361         if (rc) {
2362                 PMD_DRV_LOG(ERR,
2363                         "Get link config failed with rc %d\n", rc);
2364                 goto exit;
2365         }
2366         if (link_info->link_speed)
2367                 link->link_speed =
2368                         bnxt_parse_hw_link_speed(link_info->link_speed);
2369         else
2370                 link->link_speed = ETH_SPEED_NUM_NONE;
2371         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2372         link->link_status = link_info->link_up;
2373         link->link_autoneg = link_info->auto_mode ==
2374                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2375                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2376 exit:
2377         return rc;
2378 }
2379
2380 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2381 {
2382         int rc = 0;
2383         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2384         struct bnxt_link_info link_req;
2385         uint16_t speed, autoneg;
2386
2387         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2388                 return 0;
2389
2390         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2391                         bp->eth_dev->data->port_id);
2392         if (rc)
2393                 goto error;
2394
2395         memset(&link_req, 0, sizeof(link_req));
2396         link_req.link_up = link_up;
2397         if (!link_up)
2398                 goto port_phy_cfg;
2399
2400         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2401         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2402         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2403         /* Autoneg can be done only when the FW allows */
2404         if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2405                                 bp->link_info.force_link_speed)) {
2406                 link_req.phy_flags |=
2407                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2408                 link_req.auto_link_speed_mask =
2409                         bnxt_parse_eth_link_speed_mask(bp,
2410                                                        dev_conf->link_speeds);
2411         } else {
2412                 if (bp->link_info.phy_type ==
2413                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2414                     bp->link_info.phy_type ==
2415                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2416                     bp->link_info.media_type ==
2417                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2418                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2419                         return -EINVAL;
2420                 }
2421
2422                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2423                 /* If user wants a particular speed try that first. */
2424                 if (speed)
2425                         link_req.link_speed = speed;
2426                 else if (bp->link_info.force_link_speed)
2427                         link_req.link_speed = bp->link_info.force_link_speed;
2428                 else
2429                         link_req.link_speed = bp->link_info.auto_link_speed;
2430         }
2431         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2432         link_req.auto_pause = bp->link_info.auto_pause;
2433         link_req.force_pause = bp->link_info.force_pause;
2434
2435 port_phy_cfg:
2436         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2437         if (rc) {
2438                 PMD_DRV_LOG(ERR,
2439                         "Set link config failed with rc %d\n", rc);
2440         }
2441
2442 error:
2443         return rc;
2444 }
2445
2446 /* JIRA 22088 */
2447 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2448 {
2449         struct hwrm_func_qcfg_input req = {0};
2450         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2451         uint16_t flags;
2452         int rc = 0;
2453
2454         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2455         req.fid = rte_cpu_to_le_16(0xffff);
2456
2457         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2458
2459         HWRM_CHECK_RESULT();
2460
2461         /* Hard Coded.. 0xfff VLAN ID mask */
2462         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2463         flags = rte_le_to_cpu_16(resp->flags);
2464         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2465                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2466
2467         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2468                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2469                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2470         }
2471
2472         switch (resp->port_partition_type) {
2473         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2474         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2475         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2476                 /* FALLTHROUGH */
2477                 bp->port_partition_type = resp->port_partition_type;
2478                 break;
2479         default:
2480                 bp->port_partition_type = 0;
2481                 break;
2482         }
2483
2484         HWRM_UNLOCK();
2485
2486         return rc;
2487 }
2488
2489 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2490                                    struct hwrm_func_qcaps_output *qcaps)
2491 {
2492         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2493         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2494                sizeof(qcaps->mac_address));
2495         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2496         qcaps->max_rx_rings = fcfg->num_rx_rings;
2497         qcaps->max_tx_rings = fcfg->num_tx_rings;
2498         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2499         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2500         qcaps->max_vfs = 0;
2501         qcaps->first_vf_id = 0;
2502         qcaps->max_vnics = fcfg->num_vnics;
2503         qcaps->max_decap_records = 0;
2504         qcaps->max_encap_records = 0;
2505         qcaps->max_tx_wm_flows = 0;
2506         qcaps->max_tx_em_flows = 0;
2507         qcaps->max_rx_wm_flows = 0;
2508         qcaps->max_rx_em_flows = 0;
2509         qcaps->max_flow_id = 0;
2510         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2511         qcaps->max_sp_tx_rings = 0;
2512         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2513 }
2514
2515 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2516 {
2517         struct hwrm_func_cfg_input req = {0};
2518         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2519         int rc;
2520
2521         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2522                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2523                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2524                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2525                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2526                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2527                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2528                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2529                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2530                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2531         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2532         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2533         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2534                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2535                                    BNXT_NUM_VLANS);
2536         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2537         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2538         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2539         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2540         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2541         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2542         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2543         req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2544         req.fid = rte_cpu_to_le_16(0xffff);
2545
2546         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2547
2548         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2549
2550         HWRM_CHECK_RESULT();
2551         HWRM_UNLOCK();
2552
2553         return rc;
2554 }
2555
2556 static void populate_vf_func_cfg_req(struct bnxt *bp,
2557                                      struct hwrm_func_cfg_input *req,
2558                                      int num_vfs)
2559 {
2560         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2561                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2562                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2563                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2564                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2565                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2566                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2567                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2568                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2569                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2570
2571         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2572                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2573                                     BNXT_NUM_VLANS);
2574         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2575                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2576                                     BNXT_NUM_VLANS);
2577         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2578                                                 (num_vfs + 1));
2579         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2580         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2581                                                (num_vfs + 1));
2582         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2583         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2584         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2585         /* TODO: For now, do not support VMDq/RFS on VFs. */
2586         req->num_vnics = rte_cpu_to_le_16(1);
2587         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2588                                                  (num_vfs + 1));
2589 }
2590
2591 static void add_random_mac_if_needed(struct bnxt *bp,
2592                                      struct hwrm_func_cfg_input *cfg_req,
2593                                      int vf)
2594 {
2595         struct rte_ether_addr mac;
2596
2597         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2598                 return;
2599
2600         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2601                 cfg_req->enables |=
2602                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2603                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2604                 bp->pf.vf_info[vf].random_mac = true;
2605         } else {
2606                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2607                         RTE_ETHER_ADDR_LEN);
2608         }
2609 }
2610
2611 static void reserve_resources_from_vf(struct bnxt *bp,
2612                                       struct hwrm_func_cfg_input *cfg_req,
2613                                       int vf)
2614 {
2615         struct hwrm_func_qcaps_input req = {0};
2616         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2617         int rc;
2618
2619         /* Get the actual allocated values now */
2620         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2621         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2622         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2623
2624         if (rc) {
2625                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2626                 copy_func_cfg_to_qcaps(cfg_req, resp);
2627         } else if (resp->error_code) {
2628                 rc = rte_le_to_cpu_16(resp->error_code);
2629                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2630                 copy_func_cfg_to_qcaps(cfg_req, resp);
2631         }
2632
2633         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2634         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2635         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2636         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2637         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2638         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2639         /*
2640          * TODO: While not supporting VMDq with VFs, max_vnics is always
2641          * forced to 1 in this case
2642          */
2643         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2644         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2645
2646         HWRM_UNLOCK();
2647 }
2648
2649 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2650 {
2651         struct hwrm_func_qcfg_input req = {0};
2652         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2653         int rc;
2654
2655         /* Check for zero MAC address */
2656         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2657         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2658         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2659         if (rc) {
2660                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2661                 return -1;
2662         } else if (resp->error_code) {
2663                 rc = rte_le_to_cpu_16(resp->error_code);
2664                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2665                 return -1;
2666         }
2667         rc = rte_le_to_cpu_16(resp->vlan);
2668
2669         HWRM_UNLOCK();
2670
2671         return rc;
2672 }
2673
2674 static int update_pf_resource_max(struct bnxt *bp)
2675 {
2676         struct hwrm_func_qcfg_input req = {0};
2677         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2678         int rc;
2679
2680         /* And copy the allocated numbers into the pf struct */
2681         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2682         req.fid = rte_cpu_to_le_16(0xffff);
2683         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2684         HWRM_CHECK_RESULT();
2685
2686         /* Only TX ring value reflects actual allocation? TODO */
2687         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2688         bp->pf.evb_mode = resp->evb_mode;
2689
2690         HWRM_UNLOCK();
2691
2692         return rc;
2693 }
2694
2695 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2696 {
2697         int rc;
2698
2699         if (!BNXT_PF(bp)) {
2700                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2701                 return -1;
2702         }
2703
2704         rc = bnxt_hwrm_func_qcaps(bp);
2705         if (rc)
2706                 return rc;
2707
2708         bp->pf.func_cfg_flags &=
2709                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2710                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2711         bp->pf.func_cfg_flags |=
2712                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2713         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2714         return rc;
2715 }
2716
2717 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2718 {
2719         struct hwrm_func_cfg_input req = {0};
2720         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2721         int i;
2722         size_t sz;
2723         int rc = 0;
2724         size_t req_buf_sz;
2725
2726         if (!BNXT_PF(bp)) {
2727                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2728                 return -1;
2729         }
2730
2731         rc = bnxt_hwrm_func_qcaps(bp);
2732
2733         if (rc)
2734                 return rc;
2735
2736         bp->pf.active_vfs = num_vfs;
2737
2738         /*
2739          * First, configure the PF to only use one TX ring.  This ensures that
2740          * there are enough rings for all VFs.
2741          *
2742          * If we don't do this, when we call func_alloc() later, we will lock
2743          * extra rings to the PF that won't be available during func_cfg() of
2744          * the VFs.
2745          *
2746          * This has been fixed with firmware versions above 20.6.54
2747          */
2748         bp->pf.func_cfg_flags &=
2749                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2750                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2751         bp->pf.func_cfg_flags |=
2752                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2753         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2754         if (rc)
2755                 return rc;
2756
2757         /*
2758          * Now, create and register a buffer to hold forwarded VF requests
2759          */
2760         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2761         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2762                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2763         if (bp->pf.vf_req_buf == NULL) {
2764                 rc = -ENOMEM;
2765                 goto error_free;
2766         }
2767         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2768                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2769         for (i = 0; i < num_vfs; i++)
2770                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2771                                         (i * HWRM_MAX_REQ_LEN);
2772
2773         rc = bnxt_hwrm_func_buf_rgtr(bp);
2774         if (rc)
2775                 goto error_free;
2776
2777         populate_vf_func_cfg_req(bp, &req, num_vfs);
2778
2779         bp->pf.active_vfs = 0;
2780         for (i = 0; i < num_vfs; i++) {
2781                 add_random_mac_if_needed(bp, &req, i);
2782
2783                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2784                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2785                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2786                 rc = bnxt_hwrm_send_message(bp,
2787                                             &req,
2788                                             sizeof(req),
2789                                             BNXT_USE_CHIMP_MB);
2790
2791                 /* Clear enable flag for next pass */
2792                 req.enables &= ~rte_cpu_to_le_32(
2793                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2794
2795                 if (rc || resp->error_code) {
2796                         PMD_DRV_LOG(ERR,
2797                                 "Failed to initizlie VF %d\n", i);
2798                         PMD_DRV_LOG(ERR,
2799                                 "Not all VFs available. (%d, %d)\n",
2800                                 rc, resp->error_code);
2801                         HWRM_UNLOCK();
2802                         break;
2803                 }
2804
2805                 HWRM_UNLOCK();
2806
2807                 reserve_resources_from_vf(bp, &req, i);
2808                 bp->pf.active_vfs++;
2809                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2810         }
2811
2812         /*
2813          * Now configure the PF to use "the rest" of the resources
2814          * We're using STD_TX_RING_MODE here though which will limit the TX
2815          * rings.  This will allow QoS to function properly.  Not setting this
2816          * will cause PF rings to break bandwidth settings.
2817          */
2818         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2819         if (rc)
2820                 goto error_free;
2821
2822         rc = update_pf_resource_max(bp);
2823         if (rc)
2824                 goto error_free;
2825
2826         return rc;
2827
2828 error_free:
2829         bnxt_hwrm_func_buf_unrgtr(bp);
2830         return rc;
2831 }
2832
2833 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2834 {
2835         struct hwrm_func_cfg_input req = {0};
2836         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2837         int rc;
2838
2839         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2840
2841         req.fid = rte_cpu_to_le_16(0xffff);
2842         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2843         req.evb_mode = bp->pf.evb_mode;
2844
2845         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2846         HWRM_CHECK_RESULT();
2847         HWRM_UNLOCK();
2848
2849         return rc;
2850 }
2851
2852 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2853                                 uint8_t tunnel_type)
2854 {
2855         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2856         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2857         int rc = 0;
2858
2859         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
2860         req.tunnel_type = tunnel_type;
2861         req.tunnel_dst_port_val = port;
2862         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2863         HWRM_CHECK_RESULT();
2864
2865         switch (tunnel_type) {
2866         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2867                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2868                 bp->vxlan_port = port;
2869                 break;
2870         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2871                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2872                 bp->geneve_port = port;
2873                 break;
2874         default:
2875                 break;
2876         }
2877
2878         HWRM_UNLOCK();
2879
2880         return rc;
2881 }
2882
2883 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2884                                 uint8_t tunnel_type)
2885 {
2886         struct hwrm_tunnel_dst_port_free_input req = {0};
2887         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2888         int rc = 0;
2889
2890         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
2891
2892         req.tunnel_type = tunnel_type;
2893         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2894         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2895
2896         HWRM_CHECK_RESULT();
2897         HWRM_UNLOCK();
2898
2899         return rc;
2900 }
2901
2902 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2903                                         uint32_t flags)
2904 {
2905         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2906         struct hwrm_func_cfg_input req = {0};
2907         int rc;
2908
2909         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2910
2911         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2912         req.flags = rte_cpu_to_le_32(flags);
2913         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2914
2915         HWRM_CHECK_RESULT();
2916         HWRM_UNLOCK();
2917
2918         return rc;
2919 }
2920
2921 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2922 {
2923         uint32_t *flag = flagp;
2924
2925         vnic->flags = *flag;
2926 }
2927
2928 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2929 {
2930         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2931 }
2932
2933 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2934 {
2935         int rc = 0;
2936         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2937         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2938
2939         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
2940
2941         req.req_buf_num_pages = rte_cpu_to_le_16(1);
2942         req.req_buf_page_size = rte_cpu_to_le_16(
2943                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2944         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2945         req.req_buf_page_addr0 =
2946                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
2947         if (req.req_buf_page_addr0 == 0) {
2948                 PMD_DRV_LOG(ERR,
2949                         "unable to map buffer address to physical memory\n");
2950                 return -ENOMEM;
2951         }
2952
2953         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2954
2955         HWRM_CHECK_RESULT();
2956         HWRM_UNLOCK();
2957
2958         return rc;
2959 }
2960
2961 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2962 {
2963         int rc = 0;
2964         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2965         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2966
2967         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
2968
2969         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2970
2971         HWRM_CHECK_RESULT();
2972         HWRM_UNLOCK();
2973
2974         return rc;
2975 }
2976
2977 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2978 {
2979         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2980         struct hwrm_func_cfg_input req = {0};
2981         int rc;
2982
2983         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2984
2985         req.fid = rte_cpu_to_le_16(0xffff);
2986         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2987         req.enables = rte_cpu_to_le_32(
2988                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2989         req.async_event_cr = rte_cpu_to_le_16(
2990                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2991         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2992
2993         HWRM_CHECK_RESULT();
2994         HWRM_UNLOCK();
2995
2996         return rc;
2997 }
2998
2999 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3000 {
3001         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3002         struct hwrm_func_vf_cfg_input req = {0};
3003         int rc;
3004
3005         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3006
3007         req.enables = rte_cpu_to_le_32(
3008                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3009         req.async_event_cr = rte_cpu_to_le_16(
3010                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3011         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3012
3013         HWRM_CHECK_RESULT();
3014         HWRM_UNLOCK();
3015
3016         return rc;
3017 }
3018
3019 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3020 {
3021         struct hwrm_func_cfg_input req = {0};
3022         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3023         uint16_t dflt_vlan, fid;
3024         uint32_t func_cfg_flags;
3025         int rc = 0;
3026
3027         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3028
3029         if (is_vf) {
3030                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3031                 fid = bp->pf.vf_info[vf].fid;
3032                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3033         } else {
3034                 fid = rte_cpu_to_le_16(0xffff);
3035                 func_cfg_flags = bp->pf.func_cfg_flags;
3036                 dflt_vlan = bp->vlan;
3037         }
3038
3039         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3040         req.fid = rte_cpu_to_le_16(fid);
3041         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3042         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3043
3044         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3045
3046         HWRM_CHECK_RESULT();
3047         HWRM_UNLOCK();
3048
3049         return rc;
3050 }
3051
3052 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3053                         uint16_t max_bw, uint16_t enables)
3054 {
3055         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3056         struct hwrm_func_cfg_input req = {0};
3057         int rc;
3058
3059         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3060
3061         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3062         req.enables |= rte_cpu_to_le_32(enables);
3063         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3064         req.max_bw = rte_cpu_to_le_32(max_bw);
3065         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3066
3067         HWRM_CHECK_RESULT();
3068         HWRM_UNLOCK();
3069
3070         return rc;
3071 }
3072
3073 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3074 {
3075         struct hwrm_func_cfg_input req = {0};
3076         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3077         int rc = 0;
3078
3079         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3080
3081         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3082         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3083         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3084         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3085
3086         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3087
3088         HWRM_CHECK_RESULT();
3089         HWRM_UNLOCK();
3090
3091         return rc;
3092 }
3093
3094 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3095 {
3096         int rc;
3097
3098         if (BNXT_PF(bp))
3099                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3100         else
3101                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3102
3103         return rc;
3104 }
3105
3106 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3107                               void *encaped, size_t ec_size)
3108 {
3109         int rc = 0;
3110         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3111         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3112
3113         if (ec_size > sizeof(req.encap_request))
3114                 return -1;
3115
3116         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3117
3118         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3119         memcpy(req.encap_request, encaped, ec_size);
3120
3121         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3122
3123         HWRM_CHECK_RESULT();
3124         HWRM_UNLOCK();
3125
3126         return rc;
3127 }
3128
3129 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3130                                        struct rte_ether_addr *mac)
3131 {
3132         struct hwrm_func_qcfg_input req = {0};
3133         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3134         int rc;
3135
3136         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3137
3138         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3139         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3140
3141         HWRM_CHECK_RESULT();
3142
3143         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3144
3145         HWRM_UNLOCK();
3146
3147         return rc;
3148 }
3149
3150 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3151                             void *encaped, size_t ec_size)
3152 {
3153         int rc = 0;
3154         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3155         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3156
3157         if (ec_size > sizeof(req.encap_request))
3158                 return -1;
3159
3160         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3161
3162         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3163         memcpy(req.encap_request, encaped, ec_size);
3164
3165         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3166
3167         HWRM_CHECK_RESULT();
3168         HWRM_UNLOCK();
3169
3170         return rc;
3171 }
3172
3173 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3174                          struct rte_eth_stats *stats, uint8_t rx)
3175 {
3176         int rc = 0;
3177         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3178         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3179
3180         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3181
3182         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3183
3184         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3185
3186         HWRM_CHECK_RESULT();
3187
3188         if (rx) {
3189                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3190                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3191                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3192                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3193                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3194                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3195                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3196                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3197         } else {
3198                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3199                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3200                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3201                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3202                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3203                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3204         }
3205
3206
3207         HWRM_UNLOCK();
3208
3209         return rc;
3210 }
3211
3212 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3213 {
3214         struct hwrm_port_qstats_input req = {0};
3215         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3216         struct bnxt_pf_info *pf = &bp->pf;
3217         int rc;
3218
3219         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3220
3221         req.port_id = rte_cpu_to_le_16(pf->port_id);
3222         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3223         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3224         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3225
3226         HWRM_CHECK_RESULT();
3227         HWRM_UNLOCK();
3228
3229         return rc;
3230 }
3231
3232 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3233 {
3234         struct hwrm_port_clr_stats_input req = {0};
3235         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3236         struct bnxt_pf_info *pf = &bp->pf;
3237         int rc;
3238
3239         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3240         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3241             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3242                 return 0;
3243
3244         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3245
3246         req.port_id = rte_cpu_to_le_16(pf->port_id);
3247         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3248
3249         HWRM_CHECK_RESULT();
3250         HWRM_UNLOCK();
3251
3252         return rc;
3253 }
3254
3255 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3256 {
3257         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3258         struct hwrm_port_led_qcaps_input req = {0};
3259         int rc;
3260
3261         if (BNXT_VF(bp))
3262                 return 0;
3263
3264         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3265         req.port_id = bp->pf.port_id;
3266         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3267
3268         HWRM_CHECK_RESULT();
3269
3270         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3271                 unsigned int i;
3272
3273                 bp->num_leds = resp->num_leds;
3274                 memcpy(bp->leds, &resp->led0_id,
3275                         sizeof(bp->leds[0]) * bp->num_leds);
3276                 for (i = 0; i < bp->num_leds; i++) {
3277                         struct bnxt_led_info *led = &bp->leds[i];
3278
3279                         uint16_t caps = led->led_state_caps;
3280
3281                         if (!led->led_group_id ||
3282                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3283                                 bp->num_leds = 0;
3284                                 break;
3285                         }
3286                 }
3287         }
3288
3289         HWRM_UNLOCK();
3290
3291         return rc;
3292 }
3293
3294 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3295 {
3296         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3297         struct hwrm_port_led_cfg_input req = {0};
3298         struct bnxt_led_cfg *led_cfg;
3299         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3300         uint16_t duration = 0;
3301         int rc, i;
3302
3303         if (!bp->num_leds || BNXT_VF(bp))
3304                 return -EOPNOTSUPP;
3305
3306         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3307
3308         if (led_on) {
3309                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3310                 duration = rte_cpu_to_le_16(500);
3311         }
3312         req.port_id = bp->pf.port_id;
3313         req.num_leds = bp->num_leds;
3314         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3315         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3316                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3317                 led_cfg->led_id = bp->leds[i].led_id;
3318                 led_cfg->led_state = led_state;
3319                 led_cfg->led_blink_on = duration;
3320                 led_cfg->led_blink_off = duration;
3321                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3322         }
3323
3324         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3325
3326         HWRM_CHECK_RESULT();
3327         HWRM_UNLOCK();
3328
3329         return rc;
3330 }
3331
3332 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3333                                uint32_t *length)
3334 {
3335         int rc;
3336         struct hwrm_nvm_get_dir_info_input req = {0};
3337         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3338
3339         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3340
3341         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3342
3343         HWRM_CHECK_RESULT();
3344         HWRM_UNLOCK();
3345
3346         if (!rc) {
3347                 *entries = rte_le_to_cpu_32(resp->entries);
3348                 *length = rte_le_to_cpu_32(resp->entry_length);
3349         }
3350         return rc;
3351 }
3352
3353 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3354 {
3355         int rc;
3356         uint32_t dir_entries;
3357         uint32_t entry_length;
3358         uint8_t *buf;
3359         size_t buflen;
3360         rte_iova_t dma_handle;
3361         struct hwrm_nvm_get_dir_entries_input req = {0};
3362         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3363
3364         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3365         if (rc != 0)
3366                 return rc;
3367
3368         *data++ = dir_entries;
3369         *data++ = entry_length;
3370         len -= 2;
3371         memset(data, 0xff, len);
3372
3373         buflen = dir_entries * entry_length;
3374         buf = rte_malloc("nvm_dir", buflen, 0);
3375         rte_mem_lock_page(buf);
3376         if (buf == NULL)
3377                 return -ENOMEM;
3378         dma_handle = rte_mem_virt2iova(buf);
3379         if (dma_handle == 0) {
3380                 PMD_DRV_LOG(ERR,
3381                         "unable to map response address to physical memory\n");
3382                 return -ENOMEM;
3383         }
3384         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3385         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3386         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3387
3388         if (rc == 0)
3389                 memcpy(data, buf, len > buflen ? buflen : len);
3390
3391         rte_free(buf);
3392         HWRM_CHECK_RESULT();
3393         HWRM_UNLOCK();
3394
3395         return rc;
3396 }
3397
3398 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3399                              uint32_t offset, uint32_t length,
3400                              uint8_t *data)
3401 {
3402         int rc;
3403         uint8_t *buf;
3404         rte_iova_t dma_handle;
3405         struct hwrm_nvm_read_input req = {0};
3406         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3407
3408         buf = rte_malloc("nvm_item", length, 0);
3409         rte_mem_lock_page(buf);
3410         if (!buf)
3411                 return -ENOMEM;
3412
3413         dma_handle = rte_mem_virt2iova(buf);
3414         if (dma_handle == 0) {
3415                 PMD_DRV_LOG(ERR,
3416                         "unable to map response address to physical memory\n");
3417                 return -ENOMEM;
3418         }
3419         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3420         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3421         req.dir_idx = rte_cpu_to_le_16(index);
3422         req.offset = rte_cpu_to_le_32(offset);
3423         req.len = rte_cpu_to_le_32(length);
3424         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3425         if (rc == 0)
3426                 memcpy(data, buf, length);
3427
3428         rte_free(buf);
3429         HWRM_CHECK_RESULT();
3430         HWRM_UNLOCK();
3431
3432         return rc;
3433 }
3434
3435 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3436 {
3437         int rc;
3438         struct hwrm_nvm_erase_dir_entry_input req = {0};
3439         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3440
3441         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3442         req.dir_idx = rte_cpu_to_le_16(index);
3443         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3444         HWRM_CHECK_RESULT();
3445         HWRM_UNLOCK();
3446
3447         return rc;
3448 }
3449
3450
3451 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3452                           uint16_t dir_ordinal, uint16_t dir_ext,
3453                           uint16_t dir_attr, const uint8_t *data,
3454                           size_t data_len)
3455 {
3456         int rc;
3457         struct hwrm_nvm_write_input req = {0};
3458         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3459         rte_iova_t dma_handle;
3460         uint8_t *buf;
3461
3462         buf = rte_malloc("nvm_write", data_len, 0);
3463         rte_mem_lock_page(buf);
3464         if (!buf)
3465                 return -ENOMEM;
3466
3467         dma_handle = rte_mem_virt2iova(buf);
3468         if (dma_handle == 0) {
3469                 PMD_DRV_LOG(ERR,
3470                         "unable to map response address to physical memory\n");
3471                 return -ENOMEM;
3472         }
3473         memcpy(buf, data, data_len);
3474
3475         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3476
3477         req.dir_type = rte_cpu_to_le_16(dir_type);
3478         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3479         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3480         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3481         req.dir_data_length = rte_cpu_to_le_32(data_len);
3482         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3483
3484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3485
3486         rte_free(buf);
3487         HWRM_CHECK_RESULT();
3488         HWRM_UNLOCK();
3489
3490         return rc;
3491 }
3492
3493 static void
3494 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3495 {
3496         uint32_t *count = cbdata;
3497
3498         *count = *count + 1;
3499 }
3500
3501 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3502                                      struct bnxt_vnic_info *vnic __rte_unused)
3503 {
3504         return 0;
3505 }
3506
3507 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3508 {
3509         uint32_t count = 0;
3510
3511         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3512             &count, bnxt_vnic_count_hwrm_stub);
3513
3514         return count;
3515 }
3516
3517 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3518                                         uint16_t *vnic_ids)
3519 {
3520         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3521         struct hwrm_func_vf_vnic_ids_query_output *resp =
3522                                                 bp->hwrm_cmd_resp_addr;
3523         int rc;
3524
3525         /* First query all VNIC ids */
3526         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3527
3528         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3529         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3530         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3531
3532         if (req.vnic_id_tbl_addr == 0) {
3533                 HWRM_UNLOCK();
3534                 PMD_DRV_LOG(ERR,
3535                 "unable to map VNIC ID table address to physical memory\n");
3536                 return -ENOMEM;
3537         }
3538         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3539         if (rc) {
3540                 HWRM_UNLOCK();
3541                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3542                 return -1;
3543         } else if (resp->error_code) {
3544                 rc = rte_le_to_cpu_16(resp->error_code);
3545                 HWRM_UNLOCK();
3546                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3547                 return -1;
3548         }
3549         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3550
3551         HWRM_UNLOCK();
3552
3553         return rc;
3554 }
3555
3556 /*
3557  * This function queries the VNIC IDs  for a specified VF. It then calls
3558  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3559  * Then it calls the hwrm_cb function to program this new vnic configuration.
3560  */
3561 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3562         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3563         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3564 {
3565         struct bnxt_vnic_info vnic;
3566         int rc = 0;
3567         int i, num_vnic_ids;
3568         uint16_t *vnic_ids;
3569         size_t vnic_id_sz;
3570         size_t sz;
3571
3572         /* First query all VNIC ids */
3573         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3574         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3575                         RTE_CACHE_LINE_SIZE);
3576         if (vnic_ids == NULL) {
3577                 rc = -ENOMEM;
3578                 return rc;
3579         }
3580         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3581                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3582
3583         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3584
3585         if (num_vnic_ids < 0)
3586                 return num_vnic_ids;
3587
3588         /* Retrieve VNIC, update bd_stall then update */
3589
3590         for (i = 0; i < num_vnic_ids; i++) {
3591                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3592                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3593                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3594                 if (rc)
3595                         break;
3596                 if (vnic.mru <= 4)      /* Indicates unallocated */
3597                         continue;
3598
3599                 vnic_cb(&vnic, cbdata);
3600
3601                 rc = hwrm_cb(bp, &vnic);
3602                 if (rc)
3603                         break;
3604         }
3605
3606         rte_free(vnic_ids);
3607
3608         return rc;
3609 }
3610
3611 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3612                                               bool on)
3613 {
3614         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3615         struct hwrm_func_cfg_input req = {0};
3616         int rc;
3617
3618         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3619
3620         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3621         req.enables |= rte_cpu_to_le_32(
3622                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3623         req.vlan_antispoof_mode = on ?
3624                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3625                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3626         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3627
3628         HWRM_CHECK_RESULT();
3629         HWRM_UNLOCK();
3630
3631         return rc;
3632 }
3633
3634 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3635 {
3636         struct bnxt_vnic_info vnic;
3637         uint16_t *vnic_ids;
3638         size_t vnic_id_sz;
3639         int num_vnic_ids, i;
3640         size_t sz;
3641         int rc;
3642
3643         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3644         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3645                         RTE_CACHE_LINE_SIZE);
3646         if (vnic_ids == NULL) {
3647                 rc = -ENOMEM;
3648                 return rc;
3649         }
3650
3651         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3652                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3653
3654         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3655         if (rc <= 0)
3656                 goto exit;
3657         num_vnic_ids = rc;
3658
3659         /*
3660          * Loop through to find the default VNIC ID.
3661          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3662          * by sending the hwrm_func_qcfg command to the firmware.
3663          */
3664         for (i = 0; i < num_vnic_ids; i++) {
3665                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3666                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3667                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3668                                         bp->pf.first_vf_id + vf);
3669                 if (rc)
3670                         goto exit;
3671                 if (vnic.func_default) {
3672                         rte_free(vnic_ids);
3673                         return vnic.fw_vnic_id;
3674                 }
3675         }
3676         /* Could not find a default VNIC. */
3677         PMD_DRV_LOG(ERR, "No default VNIC\n");
3678 exit:
3679         rte_free(vnic_ids);
3680         return -1;
3681 }
3682
3683 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3684                          uint16_t dst_id,
3685                          struct bnxt_filter_info *filter)
3686 {
3687         int rc = 0;
3688         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3689         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3690         uint32_t enables = 0;
3691
3692         if (filter->fw_em_filter_id != UINT64_MAX)
3693                 bnxt_hwrm_clear_em_filter(bp, filter);
3694
3695         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3696
3697         req.flags = rte_cpu_to_le_32(filter->flags);
3698
3699         enables = filter->enables |
3700               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3701         req.dst_id = rte_cpu_to_le_16(dst_id);
3702
3703         if (filter->ip_addr_type) {
3704                 req.ip_addr_type = filter->ip_addr_type;
3705                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3706         }
3707         if (enables &
3708             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3709                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3710         if (enables &
3711             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3712                 memcpy(req.src_macaddr, filter->src_macaddr,
3713                        RTE_ETHER_ADDR_LEN);
3714         if (enables &
3715             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3716                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3717                        RTE_ETHER_ADDR_LEN);
3718         if (enables &
3719             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3720                 req.ovlan_vid = filter->l2_ovlan;
3721         if (enables &
3722             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3723                 req.ivlan_vid = filter->l2_ivlan;
3724         if (enables &
3725             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3726                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3727         if (enables &
3728             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3729                 req.ip_protocol = filter->ip_protocol;
3730         if (enables &
3731             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3732                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3733         if (enables &
3734             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3735                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3736         if (enables &
3737             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3738                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3739         if (enables &
3740             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3741                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3742         if (enables &
3743             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3744                 req.mirror_vnic_id = filter->mirror_vnic_id;
3745
3746         req.enables = rte_cpu_to_le_32(enables);
3747
3748         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3749
3750         HWRM_CHECK_RESULT();
3751
3752         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3753         HWRM_UNLOCK();
3754
3755         return rc;
3756 }
3757
3758 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3759 {
3760         int rc = 0;
3761         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3762         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3763
3764         if (filter->fw_em_filter_id == UINT64_MAX)
3765                 return 0;
3766
3767         PMD_DRV_LOG(ERR, "Clear EM filter\n");
3768         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
3769
3770         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3771
3772         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3773
3774         HWRM_CHECK_RESULT();
3775         HWRM_UNLOCK();
3776
3777         filter->fw_em_filter_id = UINT64_MAX;
3778         filter->fw_l2_filter_id = UINT64_MAX;
3779
3780         return 0;
3781 }
3782
3783 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3784                          uint16_t dst_id,
3785                          struct bnxt_filter_info *filter)
3786 {
3787         int rc = 0;
3788         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3789         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3790                                                 bp->hwrm_cmd_resp_addr;
3791         uint32_t enables = 0;
3792
3793         if (filter->fw_ntuple_filter_id != UINT64_MAX)
3794                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3795
3796         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
3797
3798         req.flags = rte_cpu_to_le_32(filter->flags);
3799
3800         enables = filter->enables |
3801               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3802         req.dst_id = rte_cpu_to_le_16(dst_id);
3803
3804
3805         if (filter->ip_addr_type) {
3806                 req.ip_addr_type = filter->ip_addr_type;
3807                 enables |=
3808                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3809         }
3810         if (enables &
3811             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3812                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3813         if (enables &
3814             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3815                 memcpy(req.src_macaddr, filter->src_macaddr,
3816                        RTE_ETHER_ADDR_LEN);
3817         //if (enables &
3818             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3819                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3820                        //RTE_ETHER_ADDR_LEN);
3821         if (enables &
3822             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3823                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3824         if (enables &
3825             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3826                 req.ip_protocol = filter->ip_protocol;
3827         if (enables &
3828             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3829                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3830         if (enables &
3831             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3832                 req.src_ipaddr_mask[0] =
3833                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3834         if (enables &
3835             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3836                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3837         if (enables &
3838             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3839                 req.dst_ipaddr_mask[0] =
3840                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3841         if (enables &
3842             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3843                 req.src_port = rte_cpu_to_le_16(filter->src_port);
3844         if (enables &
3845             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3846                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3847         if (enables &
3848             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3849                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3850         if (enables &
3851             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3852                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3853         if (enables &
3854             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3855                 req.mirror_vnic_id = filter->mirror_vnic_id;
3856
3857         req.enables = rte_cpu_to_le_32(enables);
3858
3859         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3860
3861         HWRM_CHECK_RESULT();
3862
3863         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3864         HWRM_UNLOCK();
3865
3866         return rc;
3867 }
3868
3869 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3870                                 struct bnxt_filter_info *filter)
3871 {
3872         int rc = 0;
3873         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3874         struct hwrm_cfa_ntuple_filter_free_output *resp =
3875                                                 bp->hwrm_cmd_resp_addr;
3876
3877         if (filter->fw_ntuple_filter_id == UINT64_MAX)
3878                 return 0;
3879
3880         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
3881
3882         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3883
3884         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3885
3886         HWRM_CHECK_RESULT();
3887         HWRM_UNLOCK();
3888
3889         filter->fw_ntuple_filter_id = UINT64_MAX;
3890
3891         return 0;
3892 }
3893
3894 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3895 {
3896         unsigned int rss_idx, fw_idx, i;
3897
3898         if (vnic->rss_table && vnic->hash_type) {
3899                 /*
3900                  * Fill the RSS hash & redirection table with
3901                  * ring group ids for all VNICs
3902                  */
3903                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
3904                         rss_idx++, fw_idx++) {
3905                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
3906                                 fw_idx %= bp->rx_cp_nr_rings;
3907                                 if (vnic->fw_grp_ids[fw_idx] !=
3908                                     INVALID_HW_RING_ID)
3909                                         break;
3910                                 fw_idx++;
3911                         }
3912                         if (i == bp->rx_cp_nr_rings)
3913                                 return 0;
3914                         vnic->rss_table[rss_idx] =
3915                                 vnic->fw_grp_ids[fw_idx];
3916                 }
3917                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
3918         }
3919         return 0;
3920 }
3921
3922 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
3923         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
3924 {
3925         uint16_t flags;
3926
3927         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
3928
3929         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
3930         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
3931
3932         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
3933         req->num_cmpl_dma_aggr_during_int =
3934                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
3935
3936         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
3937
3938         /* min timer set to 1/2 of interrupt timer */
3939         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
3940
3941         /* buf timer set to 1/4 of interrupt timer */
3942         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
3943
3944         req->cmpl_aggr_dma_tmr_during_int =
3945                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
3946
3947         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
3948                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
3949         req->flags = rte_cpu_to_le_16(flags);
3950 }
3951
3952 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
3953                         struct bnxt_coal *coal, uint16_t ring_id)
3954 {
3955         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
3956         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
3957                                                 bp->hwrm_cmd_resp_addr;
3958         int rc;
3959
3960         /* Set ring coalesce parameters only for Stratus 100G NIC */
3961         if (!bnxt_stratus_device(bp))
3962                 return 0;
3963
3964         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
3965         bnxt_hwrm_set_coal_params(coal, &req);
3966         req.ring_id = rte_cpu_to_le_16(ring_id);
3967         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3968         HWRM_CHECK_RESULT();
3969         HWRM_UNLOCK();
3970         return 0;
3971 }
3972
3973 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
3974 {
3975         struct hwrm_port_qstats_ext_input req = {0};
3976         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
3977         struct bnxt_pf_info *pf = &bp->pf;
3978         int rc;
3979
3980         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
3981               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
3982                 return 0;
3983
3984         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
3985
3986         req.port_id = rte_cpu_to_le_16(pf->port_id);
3987         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
3988                 req.tx_stat_host_addr =
3989                         rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3990                 req.tx_stat_size =
3991                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
3992         }
3993         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
3994                 req.rx_stat_host_addr =
3995                         rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3996                 req.rx_stat_size =
3997                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
3998         }
3999         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4000
4001         if (rc) {
4002                 bp->fw_rx_port_stats_ext_size = 0;
4003                 bp->fw_tx_port_stats_ext_size = 0;
4004         } else {
4005                 bp->fw_rx_port_stats_ext_size =
4006                         rte_le_to_cpu_16(resp->rx_stat_size);
4007                 bp->fw_tx_port_stats_ext_size =
4008                         rte_le_to_cpu_16(resp->tx_stat_size);
4009         }
4010
4011         HWRM_CHECK_RESULT();
4012         HWRM_UNLOCK();
4013
4014         return rc;
4015 }