drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         timeout = bp->hwrm_cmd_timeout;
 104
 105         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 106             msg_len > bp->max_req_len) {
 107                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 108
 109                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 110                 memcpy(short_cmd_req, req, msg_len);
 111
 112                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 113                 short_input.signature = rte_cpu_to_le_16(
 114                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 115                 short_input.size = rte_cpu_to_le_16(msg_len);
 116                 short_input.req_addr =
 117                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 118
 119                 data = (uint32_t *)&short_input;
 120                 msg_len = sizeof(short_input);
 121
 122                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 123         }
 124
 125         /* Write request msg to hwrm channel */
 126         for (i = 0; i < msg_len; i += 4) {
 127                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 128                 rte_write32(*data, bar);
 129                 data++;
 130         }
 131
 132         /* Zero the rest of the request space */
 133         for (; i < max_req_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 135                 rte_write32(0, bar);
 136         }
 137
 138         /* Ring channel doorbell */
 139         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 140         rte_write32(1, bar);
 141         /*
 142          * Make sure the channel doorbell ring command complete before
 143          * reading the response to avoid getting stale or invalid
 144          * responses.
 145          */
 146         rte_io_mb();
 147
 148         /* Poll for the valid bit */
 149         for (i = 0; i < timeout; i++) {
 150                 /* Sanity check on the resp->resp_len */
 151                 rte_io_rmb();
 152                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 153                         /* Last byte of resp contains the valid key */
 154                         valid = (uint8_t *)resp + resp->resp_len - 1;
 155                         if (*valid == HWRM_RESP_VALID_KEY)
 156                                 break;
 157                 }
 158                 rte_delay_us(1);
 159         }
 160
 161         if (i >= timeout) {
 162                 /* Suppress VER_GET timeout messages during reset recovery */
 163                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 164                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 165                         return -ETIMEDOUT;
 166
 167                 PMD_DRV_LOG(ERR,
 168                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 169                             req->req_type, req->seq_id);
 170                 return -ETIMEDOUT;
 171         }
 172         return 0;
 173 }
 174
 175 /*
 176  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 177  * spinlock, and does initial processing.
 178  *
 179  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 180  * releases the spinlock only if it returns. If the regular int return codes
 181  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 182  * directly, rather it should be copied and modified to suit the function.
 183  *
 184  * HWRM_UNLOCK() must be called after all response processing is completed.
 185  */
 186 #define HWRM_PREP(req, type, kong) do { \
 187         rte_spinlock_lock(&bp->hwrm_lock); \
 188         if (bp->hwrm_cmd_resp_addr == NULL) { \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 return -EACCES; \
 191         } \
 192         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 193         (req)->req_type = rte_cpu_to_le_16(type); \
 194         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 195         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 196                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 197         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 198         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 199 } while (0)
 200
 201 #define HWRM_CHECK_RESULT_SILENT() do {\
 202         if (rc) { \
 203                 rte_spinlock_unlock(&bp->hwrm_lock); \
 204                 return rc; \
 205         } \
 206         if (resp->error_code) { \
 207                 rc = rte_le_to_cpu_16(resp->error_code); \
 208                 rte_spinlock_unlock(&bp->hwrm_lock); \
 209                 return rc; \
 210         } \
 211 } while (0)
 212
 213 #define HWRM_CHECK_RESULT() do {\
 214         if (rc) { \
 215                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 216                 rte_spinlock_unlock(&bp->hwrm_lock); \
 217                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 218                         rc = -EACCES; \
 219                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 220                         rc = -ENOSPC; \
 221                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 222                         rc = -EINVAL; \
 223                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 224                         rc = -ENOTSUP; \
 225                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 226                         rc = -EAGAIN; \
 227                 else if (rc > 0) \
 228                         rc = -EIO; \
 229                 return rc; \
 230         } \
 231         if (resp->error_code) { \
 232                 rc = rte_le_to_cpu_16(resp->error_code); \
 233                 if (resp->resp_len >= 16) { \
 234                         struct hwrm_err_output *tmp_hwrm_err_op = \
 235                                                 (void *)resp; \
 236                         PMD_DRV_LOG(ERR, \
 237                                 "error %d:%d:%08x:%04x\n", \
 238                                 rc, tmp_hwrm_err_op->cmd_err, \
 239                                 rte_le_to_cpu_32(\
 240                                         tmp_hwrm_err_op->opaque_0), \
 241                                 rte_le_to_cpu_16(\
 242                                         tmp_hwrm_err_op->opaque_1)); \
 243                 } else { \
 244                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 245                 } \
 246                 rte_spinlock_unlock(&bp->hwrm_lock); \
 247                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 248                         rc = -EACCES; \
 249                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 250                         rc = -ENOSPC; \
 251                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 252                         rc = -EINVAL; \
 253                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 254                         rc = -ENOTSUP; \
 255                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 256                         rc = -EAGAIN; \
 257                 else if (rc > 0) \
 258                         rc = -EIO; \
 259                 return rc; \
 260         } \
 261 } while (0)
 262
 263 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 264
 265 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 266                                 bool use_kong_mb,
 267                                 uint16_t msg_type,
 268                                 void *msg,
 269                                 uint32_t msg_len,
 270                                 void *resp_msg,
 271                                 uint32_t resp_len)
 272 {
 273         int rc = 0;
 274         bool mailbox = BNXT_USE_CHIMP_MB;
 275         struct input *req = msg;
 276         struct output *resp = bp->hwrm_cmd_resp_addr;
 277
 278         if (use_kong_mb)
 279                 mailbox = BNXT_USE_KONG(bp);
 280
 281         HWRM_PREP(req, msg_type, mailbox);
 282
 283         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 284
 285         HWRM_CHECK_RESULT();
 286
 287         if (resp_msg)
 288                 memcpy(resp_msg, resp, resp_len);
 289
 290         HWRM_UNLOCK();
 291
 292         return rc;
 293 }
 294
 295 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 296                                   bool use_kong_mb,
 297                                   uint16_t tf_type,
 298                                   uint16_t tf_subtype,
 299                                   uint32_t *tf_response_code,
 300                                   void *msg,
 301                                   uint32_t msg_len,
 302                                   void *response,
 303                                   uint32_t response_len)
 304 {
 305         int rc = 0;
 306         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 307         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 308         bool mailbox = BNXT_USE_CHIMP_MB;
 309
 310         if (msg_len > sizeof(req.tf_req))
 311                 return -ENOMEM;
 312
 313         if (use_kong_mb)
 314                 mailbox = BNXT_USE_KONG(bp);
 315
 316         HWRM_PREP(&req, HWRM_TF, mailbox);
 317         /* Build request using the user supplied request payload.
 318          * TLV request size is checked at build time against HWRM
 319          * request max size, thus no checking required.
 320          */
 321         req.tf_type = tf_type;
 322         req.tf_subtype = tf_subtype;
 323         memcpy(req.tf_req, msg, msg_len);
 324
 325         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 326         HWRM_CHECK_RESULT();
 327
 328         /* Copy the resp to user provided response buffer */
 329         if (response != NULL)
 330                 /* Post process response data. We need to copy only
 331                  * the 'payload' as the HWRM data structure really is
 332                  * HWRM header + msg header + payload and the TFLIB
 333                  * only provided a payload place holder.
 334                  */
 335                 if (response_len != 0) {
 336                         memcpy(response,
 337                                resp->tf_resp,
 338                                response_len);
 339                 }
 340
 341         /* Extract the internal tflib response code */
 342         *tf_response_code = resp->tf_resp_code;
 343         HWRM_UNLOCK();
 344
 345         return rc;
 346 }
 347
 348 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 349 {
 350         int rc = 0;
 351         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 352         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 353
 354         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 355         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 356         req.mask = 0;
 357
 358         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 359
 360         HWRM_CHECK_RESULT();
 361         HWRM_UNLOCK();
 362
 363         return rc;
 364 }
 365
 366 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 367                                  struct bnxt_vnic_info *vnic,
 368                                  uint16_t vlan_count,
 369                                  struct bnxt_vlan_table_entry *vlan_table)
 370 {
 371         int rc = 0;
 372         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 373         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 374         uint32_t mask = 0;
 375
 376         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 377                 return rc;
 378
 379         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 380         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 381
 382         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 383                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 384         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 385                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 386
 387         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 388                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 389
 390         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 391                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 392         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 393                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 394                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 395                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 396         }
 397         if (vlan_table) {
 398                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 399                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 400                 req.vlan_tag_tbl_addr =
 401                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 402                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 403         }
 404         req.mask = rte_cpu_to_le_32(mask);
 405
 406         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 407
 408         HWRM_CHECK_RESULT();
 409         HWRM_UNLOCK();
 410
 411         return rc;
 412 }
 413
 414 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 415                         uint16_t vlan_count,
 416                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 417 {
 418         int rc = 0;
 419         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 420         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 421                                                 bp->hwrm_cmd_resp_addr;
 422
 423         /*
 424          * Older HWRM versions did not support this command, and the set_rx_mask
 425          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 426          * removed from set_rx_mask call, and this command was added.
 427          *
 428          * This command is also present from 1.7.8.11 and higher,
 429          * as well as 1.7.8.0
 430          */
 431         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 432                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 433                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 434                                         (11)))
 435                                 return 0;
 436                 }
 437         }
 438         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 439         req.fid = rte_cpu_to_le_16(fid);
 440
 441         req.vlan_tag_mask_tbl_addr =
 442                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 443         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 444
 445         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 446
 447         HWRM_CHECK_RESULT();
 448         HWRM_UNLOCK();
 449
 450         return rc;
 451 }
 452
 453 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 454                              struct bnxt_filter_info *filter)
 455 {
 456         int rc = 0;
 457         struct bnxt_filter_info *l2_filter = filter;
 458         struct bnxt_vnic_info *vnic = NULL;
 459         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 460         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 461
 462         if (filter->fw_l2_filter_id == UINT64_MAX)
 463                 return 0;
 464
 465         if (filter->matching_l2_fltr_ptr)
 466                 l2_filter = filter->matching_l2_fltr_ptr;
 467
 468         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 469                     filter, l2_filter, l2_filter->l2_ref_cnt);
 470
 471         if (l2_filter->l2_ref_cnt == 0)
 472                 return 0;
 473
 474         if (l2_filter->l2_ref_cnt > 0)
 475                 l2_filter->l2_ref_cnt--;
 476
 477         if (l2_filter->l2_ref_cnt > 0)
 478                 return 0;
 479
 480         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 481
 482         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 483
 484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 485
 486         HWRM_CHECK_RESULT();
 487         HWRM_UNLOCK();
 488
 489         filter->fw_l2_filter_id = UINT64_MAX;
 490         if (l2_filter->l2_ref_cnt == 0) {
 491                 vnic = l2_filter->vnic;
 492                 if (vnic) {
 493                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 494                                       bnxt_filter_info, next);
 495                         bnxt_free_filter(bp, l2_filter);
 496                 }
 497         }
 498
 499         return 0;
 500 }
 501
 502 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 503                          uint16_t dst_id,
 504                          struct bnxt_filter_info *filter)
 505 {
 506         int rc = 0;
 507         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 508         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 509         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 510         const struct rte_eth_vmdq_rx_conf *conf =
 511                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 512         uint32_t enables = 0;
 513         uint16_t j = dst_id - 1;
 514
 515         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 516         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 517             conf->pool_map[j].pools & (1UL << j)) {
 518                 PMD_DRV_LOG(DEBUG,
 519                         "Add vlan %u to vmdq pool %u\n",
 520                         conf->pool_map[j].vlan_id, j);
 521
 522                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 523                 filter->enables |=
 524                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 525                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 526         }
 527
 528         if (filter->fw_l2_filter_id != UINT64_MAX)
 529                 bnxt_hwrm_clear_l2_filter(bp, filter);
 530
 531         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 532
 533         /* PMD does not support XDP and RoCE */
 534         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 535                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 536         req.flags = rte_cpu_to_le_32(filter->flags);
 537
 538         enables = filter->enables |
 539               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 540         req.dst_id = rte_cpu_to_le_16(dst_id);
 541
 542         if (enables &
 543             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 544                 memcpy(req.l2_addr, filter->l2_addr,
 545                        RTE_ETHER_ADDR_LEN);
 546         if (enables &
 547             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 548                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 549                        RTE_ETHER_ADDR_LEN);
 550         if (enables &
 551             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 552                 req.l2_ovlan = filter->l2_ovlan;
 553         if (enables &
 554             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 555                 req.l2_ivlan = filter->l2_ivlan;
 556         if (enables &
 557             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 558                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 559         if (enables &
 560             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 561                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 562         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 563                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 564         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 565                 req.src_type = filter->src_type;
 566         if (filter->pri_hint) {
 567                 req.pri_hint = filter->pri_hint;
 568                 req.l2_filter_id_hint =
 569                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 570         }
 571
 572         req.enables = rte_cpu_to_le_32(enables);
 573
 574         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 575
 576         HWRM_CHECK_RESULT();
 577
 578         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 579         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 580         HWRM_UNLOCK();
 581
 582         filter->l2_ref_cnt++;
 583
 584         return rc;
 585 }
 586
 587 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 588 {
 589         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 590         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 591         uint32_t flags = 0;
 592         int rc;
 593
 594         if (!ptp)
 595                 return 0;
 596
 597         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 598
 599         if (ptp->rx_filter)
 600                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 601         else
 602                 flags |=
 603                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 604         if (ptp->tx_tstamp_en)
 605                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 606         else
 607                 flags |=
 608                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 609         req.flags = rte_cpu_to_le_32(flags);
 610         req.enables = rte_cpu_to_le_32
 611                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 612         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 613
 614         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 615         HWRM_UNLOCK();
 616
 617         return rc;
 618 }
 619
 620 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 621 {
 622         int rc = 0;
 623         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 624         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 625         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 626
 627         if (ptp)
 628                 return 0;
 629
 630         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 631
 632         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 633
 634         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 635
 636         HWRM_CHECK_RESULT();
 637
 638         if (!BNXT_CHIP_THOR(bp) &&
 639             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 640                 return 0;
 641
 642         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 643                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 644
 645         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 646         if (!ptp)
 647                 return -ENOMEM;
 648
 649         if (!BNXT_CHIP_THOR(bp)) {
 650                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 651                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 652                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 653                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 654                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 655                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 656                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 657                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 658                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 659                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 660                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 661                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 662                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 663                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 664                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 665                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 666                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 667                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 668         }
 669
 670         ptp->bp = bp;
 671         bp->ptp_cfg = ptp;
 672
 673         return 0;
 674 }
 675
 676 void bnxt_hwrm_free_vf_info(struct bnxt *bp)
 677 {
 678         int i;
 679
 680         for (i = 0; i < bp->pf->max_vfs; i++) {
 681                 rte_free(bp->pf->vf_info[i].vlan_table);
 682                 bp->pf->vf_info[i].vlan_table = NULL;
 683                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 684                 bp->pf->vf_info[i].vlan_as_table = NULL;
 685         }
 686         rte_free(bp->pf->vf_info);
 687         bp->pf->vf_info = NULL;
 688 }
 689
 690 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 691 {
 692         int rc = 0;
 693         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 694         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 695         uint16_t new_max_vfs;
 696         uint32_t flags;
 697         int i;
 698
 699         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 700
 701         req.fid = rte_cpu_to_le_16(0xffff);
 702
 703         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 704
 705         HWRM_CHECK_RESULT();
 706
 707         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 708         flags = rte_le_to_cpu_32(resp->flags);
 709         if (BNXT_PF(bp)) {
 710                 bp->pf->port_id = resp->port_id;
 711                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 712                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 713                 new_max_vfs = bp->pdev->max_vfs;
 714                 if (new_max_vfs != bp->pf->max_vfs) {
 715                         if (bp->pf->vf_info)
 716                                 bnxt_hwrm_free_vf_info(bp);
 717                         bp->pf->vf_info = rte_zmalloc("bnxt_vf_info",
 718                             sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
 719                         if (bp->pf->vf_info == NULL) {
 720                                 PMD_DRV_LOG(ERR, "Alloc vf info fail\n");
 721                                 return -ENOMEM;
 722                         }
 723                         bp->pf->max_vfs = new_max_vfs;
 724                         for (i = 0; i < new_max_vfs; i++) {
 725                                 bp->pf->vf_info[i].fid =
 726                                         bp->pf->first_vf_id + i;
 727                                 bp->pf->vf_info[i].vlan_table =
 728                                         rte_zmalloc("VF VLAN table",
 729                                                     getpagesize(),
 730                                                     getpagesize());
 731                                 if (bp->pf->vf_info[i].vlan_table == NULL)
 732                                         PMD_DRV_LOG(ERR,
 733                                         "Fail to alloc VLAN table for VF %d\n",
 734                                         i);
 735                                 else
 736                                         rte_mem_lock_page(
 737                                                 bp->pf->vf_info[i].vlan_table);
 738                                 bp->pf->vf_info[i].vlan_as_table =
 739                                         rte_zmalloc("VF VLAN AS table",
 740                                                     getpagesize(),
 741                                                     getpagesize());
 742                                 if (bp->pf->vf_info[i].vlan_as_table == NULL)
 743                                         PMD_DRV_LOG(ERR,
 744                                         "Alloc VLAN AS table for VF %d fail\n",
 745                                         i);
 746                                 else
 747                                         rte_mem_lock_page(
 748                                               bp->pf->vf_info[i].vlan_as_table);
 749                                 STAILQ_INIT(&bp->pf->vf_info[i].filter);
 750                         }
 751                 }
 752         }
 753
 754         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 755         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 756                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 757                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 758         } else {
 759                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 760         }
 761         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 762         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 763         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 764         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 765         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 766         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 767         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 768         if (!BNXT_CHIP_THOR(bp))
 769                 bp->max_l2_ctx += bp->max_rx_em_flows;
 770         /* TODO: For now, do not support VMDq/RFS on VFs. */
 771         if (BNXT_PF(bp)) {
 772                 if (bp->pf->max_vfs)
 773                         bp->max_vnics = 1;
 774                 else
 775                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 776         } else {
 777                 bp->max_vnics = 1;
 778         }
 779         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 780                     bp->max_l2_ctx, bp->max_vnics);
 781         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 782         if (BNXT_PF(bp)) {
 783                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 784                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 785                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 786                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 787                         HWRM_UNLOCK();
 788                         bnxt_hwrm_ptp_qcfg(bp);
 789                 }
 790         }
 791
 792         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 793                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 794
 795         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 796                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 797                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 798         }
 799
 800         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 801                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 802
 803         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 804                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 805
 806         HWRM_UNLOCK();
 807
 808         return rc;
 809 }
 810
 811 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 812 {
 813         int rc;
 814
 815         rc = __bnxt_hwrm_func_qcaps(bp);
 816         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 817                 rc = bnxt_alloc_ctx_mem(bp);
 818                 if (rc)
 819                         return rc;
 820
 821                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 822                 if (!rc)
 823                         bp->flags |= BNXT_FLAG_NEW_RM;
 824         }
 825
 826         /* On older FW,
 827          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 828          * But the error can be ignored. Return success.
 829          */
 830
 831         return 0;
 832 }
 833
 834 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 835 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 836 {
 837         int rc = 0;
 838         uint32_t flags;
 839         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 840         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 841
 842         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 843
 844         req.target_id = rte_cpu_to_le_16(0xffff);
 845
 846         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 847
 848         HWRM_CHECK_RESULT();
 849
 850         flags = rte_le_to_cpu_32(resp->flags);
 851
 852         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 853                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 854                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 855         }
 856
 857         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
 858                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
 859
 860         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 861
 862         HWRM_UNLOCK();
 863
 864         return rc;
 865 }
 866
 867 int bnxt_hwrm_func_reset(struct bnxt *bp)
 868 {
 869         int rc = 0;
 870         struct hwrm_func_reset_input req = {.req_type = 0 };
 871         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 872
 873         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
 874
 875         req.enables = rte_cpu_to_le_32(0);
 876
 877         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 878
 879         HWRM_CHECK_RESULT();
 880         HWRM_UNLOCK();
 881
 882         return rc;
 883 }
 884
 885 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 886 {
 887         int rc;
 888         uint32_t flags = 0;
 889         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 890         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 891
 892         if (bp->flags & BNXT_FLAG_REGISTERED)
 893                 return 0;
 894
 895         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 896                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 897         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 898                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 899
 900         /* PFs and trusted VFs should indicate the support of the
 901          * Master capability on non Stingray platform
 902          */
 903         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 904                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 905
 906         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 907         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 908                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 909         req.ver_maj = RTE_VER_YEAR;
 910         req.ver_min = RTE_VER_MONTH;
 911         req.ver_upd = RTE_VER_MINOR;
 912
 913         if (BNXT_PF(bp)) {
 914                 req.enables |= rte_cpu_to_le_32(
 915                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 916                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
 917                        RTE_MIN(sizeof(req.vf_req_fwd),
 918                                sizeof(bp->pf->vf_req_fwd)));
 919
 920                 /*
 921                  * PF can sniff HWRM API issued by VF. This can be set up by
 922                  * linux driver and inherited by the DPDK PF driver. Clear
 923                  * this HWRM sniffer list in FW because DPDK PF driver does
 924                  * not support this.
 925                  */
 926                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 927         }
 928
 929         req.flags = rte_cpu_to_le_32(flags);
 930
 931         req.async_event_fwd[0] |=
 932                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 933                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 934                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 935                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 936                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 937         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 938                 req.async_event_fwd[0] |=
 939                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 940         req.async_event_fwd[1] |=
 941                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 942                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 943         if (BNXT_PF(bp))
 944                 req.async_event_fwd[1] |=
 945                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 946
 947         if (BNXT_VF_IS_TRUSTED(bp))
 948                 req.async_event_fwd[1] |=
 949                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
 950
 951         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 952
 953         HWRM_CHECK_RESULT();
 954
 955         flags = rte_le_to_cpu_32(resp->flags);
 956         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 957                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 958
 959         HWRM_UNLOCK();
 960
 961         bp->flags |= BNXT_FLAG_REGISTERED;
 962
 963         return rc;
 964 }
 965
 966 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 967 {
 968         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 969                 return 0;
 970
 971         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 972 }
 973
 974 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 975 {
 976         int rc;
 977         uint32_t flags = 0;
 978         uint32_t enables;
 979         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 980         struct hwrm_func_vf_cfg_input req = {0};
 981
 982         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 983
 984         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 985                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 986                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 987                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 988                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 989
 990         if (BNXT_HAS_RING_GRPS(bp)) {
 991                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 992                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 993         }
 994
 995         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 996         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 997                                             AGG_RING_MULTIPLIER);
 998         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 999         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1000                                               bp->tx_nr_rings +
1001                                               BNXT_NUM_ASYNC_CPR(bp));
1002         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1003         if (bp->vf_resv_strategy ==
1004             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1005                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1006                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1007                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1008                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1009                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1010                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1011         } else if (bp->vf_resv_strategy ==
1012                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1013                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1014                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1015         }
1016
1017         if (test)
1018                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1019                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1020                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1021                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1022                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1023                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1024
1025         if (test && BNXT_HAS_RING_GRPS(bp))
1026                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1027
1028         req.flags = rte_cpu_to_le_32(flags);
1029         req.enables |= rte_cpu_to_le_32(enables);
1030
1031         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1032
1033         if (test)
1034                 HWRM_CHECK_RESULT_SILENT();
1035         else
1036                 HWRM_CHECK_RESULT();
1037
1038         HWRM_UNLOCK();
1039         return rc;
1040 }
1041
1042 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1043 {
1044         int rc;
1045         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1046         struct hwrm_func_resource_qcaps_input req = {0};
1047
1048         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1049         req.fid = rte_cpu_to_le_16(0xffff);
1050
1051         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1052
1053         HWRM_CHECK_RESULT_SILENT();
1054
1055         if (BNXT_VF(bp)) {
1056                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1057                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1058                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1059                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1060                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1061                 /* func_resource_qcaps does not return max_rx_em_flows.
1062                  * So use the value provided by func_qcaps.
1063                  */
1064                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1065                 if (!BNXT_CHIP_THOR(bp))
1066                         bp->max_l2_ctx += bp->max_rx_em_flows;
1067                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1068                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1069         }
1070         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1071         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1072         if (bp->vf_resv_strategy >
1073             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1074                 bp->vf_resv_strategy =
1075                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1076
1077         HWRM_UNLOCK();
1078         return rc;
1079 }
1080
1081 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1082 {
1083         int rc = 0;
1084         struct hwrm_ver_get_input req = {.req_type = 0 };
1085         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1086         uint32_t fw_version;
1087         uint16_t max_resp_len;
1088         char type[RTE_MEMZONE_NAMESIZE];
1089         uint32_t dev_caps_cfg;
1090
1091         bp->max_req_len = HWRM_MAX_REQ_LEN;
1092         bp->hwrm_cmd_timeout = timeout;
1093         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1094
1095         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1096         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1097         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1098
1099         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1100
1101         if (bp->flags & BNXT_FLAG_FW_RESET)
1102                 HWRM_CHECK_RESULT_SILENT();
1103         else
1104                 HWRM_CHECK_RESULT();
1105
1106         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1107                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1108                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1109                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1110         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1111                      (resp->hwrm_fw_min_8b << 16) |
1112                      (resp->hwrm_fw_bld_8b << 8) |
1113                      resp->hwrm_fw_rsvd_8b;
1114         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1115                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1116
1117         fw_version = resp->hwrm_intf_maj_8b << 16;
1118         fw_version |= resp->hwrm_intf_min_8b << 8;
1119         fw_version |= resp->hwrm_intf_upd_8b;
1120         bp->hwrm_spec_code = fw_version;
1121
1122         /* def_req_timeout value is in milliseconds */
1123         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1124         /* convert timeout to usec */
1125         bp->hwrm_cmd_timeout *= 1000;
1126         if (!bp->hwrm_cmd_timeout)
1127                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1128
1129         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1130                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1131                 rc = -EINVAL;
1132                 goto error;
1133         }
1134
1135         if (bp->max_req_len > resp->max_req_win_len) {
1136                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1137                 rc = -EINVAL;
1138         }
1139         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1140         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1141         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1142                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1143
1144         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1145         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1146
1147         if (bp->max_resp_len != max_resp_len) {
1148                 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1149                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1150                         bp->pdev->addr.devid, bp->pdev->addr.function);
1151
1152                 rte_free(bp->hwrm_cmd_resp_addr);
1153
1154                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1155                 if (bp->hwrm_cmd_resp_addr == NULL) {
1156                         rc = -ENOMEM;
1157                         goto error;
1158                 }
1159                 bp->hwrm_cmd_resp_dma_addr =
1160                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1161                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1162                         PMD_DRV_LOG(ERR,
1163                         "Unable to map response buffer to physical memory.\n");
1164                         rc = -ENOMEM;
1165                         goto error;
1166                 }
1167                 bp->max_resp_len = max_resp_len;
1168         }
1169
1170         if ((dev_caps_cfg &
1171                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1172             (dev_caps_cfg &
1173              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1174                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1175                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1176         }
1177
1178         if (((dev_caps_cfg &
1179               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1180              (dev_caps_cfg &
1181               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1182             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1183                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1184                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1185                         bp->pdev->addr.devid, bp->pdev->addr.function);
1186
1187                 rte_free(bp->hwrm_short_cmd_req_addr);
1188
1189                 bp->hwrm_short_cmd_req_addr =
1190                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1191                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1192                         rc = -ENOMEM;
1193                         goto error;
1194                 }
1195                 bp->hwrm_short_cmd_req_dma_addr =
1196                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1197                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1198                         rte_free(bp->hwrm_short_cmd_req_addr);
1199                         PMD_DRV_LOG(ERR,
1200                                 "Unable to map buffer to physical memory.\n");
1201                         rc = -ENOMEM;
1202                         goto error;
1203                 }
1204         }
1205         if (dev_caps_cfg &
1206             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1207                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1208                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1209         }
1210         if (dev_caps_cfg &
1211             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1212                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1213         if (dev_caps_cfg &
1214             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1215                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1216                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1217         }
1218
1219         if (dev_caps_cfg &
1220             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1221                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1222                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1223         }
1224
1225
1226 error:
1227         HWRM_UNLOCK();
1228         return rc;
1229 }
1230
1231 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1232 {
1233         int rc;
1234         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1235         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1236
1237         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1238                 return 0;
1239
1240         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1241         req.flags = flags;
1242
1243         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1244
1245         HWRM_CHECK_RESULT();
1246         HWRM_UNLOCK();
1247
1248         return rc;
1249 }
1250
1251 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1252 {
1253         int rc = 0;
1254         struct hwrm_port_phy_cfg_input req = {0};
1255         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1256         uint32_t enables = 0;
1257
1258         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1259
1260         if (conf->link_up) {
1261                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1262                 if (bp->link_info->auto_mode && conf->link_speed) {
1263                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1264                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1265                 }
1266
1267                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1268                 /*
1269                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1270                  * any auto mode, even "none".
1271                  */
1272                 if (!conf->link_speed) {
1273                         /* No speeds specified. Enable AutoNeg - all speeds */
1274                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1275                         req.auto_mode =
1276                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1277                 } else {
1278                         if (bp->link_info->link_signal_mode) {
1279                                 enables |=
1280                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1281                                 req.force_pam4_link_speed =
1282                                         rte_cpu_to_le_16(conf->link_speed);
1283                         }
1284                         req.force_link_speed =
1285                                         rte_cpu_to_le_16(conf->link_speed);
1286                 }
1287                 /* AutoNeg - Advertise speeds specified. */
1288                 if (conf->auto_link_speed_mask &&
1289                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1290                         req.auto_mode =
1291                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1292                         req.auto_link_speed_mask =
1293                                 conf->auto_link_speed_mask;
1294                         if (conf->auto_pam4_link_speeds) {
1295                                 enables |=
1296                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1297                                 req.auto_link_pam4_speed_mask =
1298                                         conf->auto_pam4_link_speeds;
1299                         } else {
1300                                 enables |=
1301                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1302                         }
1303                 }
1304                 if (conf->auto_link_speed &&
1305                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1306                         enables |=
1307                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1308
1309                 req.auto_duplex = conf->duplex;
1310                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1311                 req.auto_pause = conf->auto_pause;
1312                 req.force_pause = conf->force_pause;
1313                 /* Set force_pause if there is no auto or if there is a force */
1314                 if (req.auto_pause && !req.force_pause)
1315                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1316                 else
1317                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1318
1319                 req.enables = rte_cpu_to_le_32(enables);
1320         } else {
1321                 req.flags =
1322                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1323                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1324         }
1325
1326         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1327
1328         HWRM_CHECK_RESULT();
1329         HWRM_UNLOCK();
1330
1331         return rc;
1332 }
1333
1334 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1335                                    struct bnxt_link_info *link_info)
1336 {
1337         int rc = 0;
1338         struct hwrm_port_phy_qcfg_input req = {0};
1339         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1340
1341         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1342
1343         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1344
1345         HWRM_CHECK_RESULT();
1346
1347         link_info->phy_link_status = resp->link;
1348         link_info->link_up =
1349                 (link_info->phy_link_status ==
1350                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1351         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1352         link_info->duplex = resp->duplex_cfg;
1353         link_info->pause = resp->pause;
1354         link_info->auto_pause = resp->auto_pause;
1355         link_info->force_pause = resp->force_pause;
1356         link_info->auto_mode = resp->auto_mode;
1357         link_info->phy_type = resp->phy_type;
1358         link_info->media_type = resp->media_type;
1359
1360         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1361         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1362         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1363         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1364         link_info->phy_ver[0] = resp->phy_maj;
1365         link_info->phy_ver[1] = resp->phy_min;
1366         link_info->phy_ver[2] = resp->phy_bld;
1367         link_info->link_signal_mode = rte_le_to_cpu_16(resp->link_signal_mode);
1368         link_info->force_pam4_link_speed =
1369                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1370         link_info->support_pam4_speeds =
1371                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1372         link_info->auto_pam4_link_speeds =
1373                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1374         HWRM_UNLOCK();
1375
1376         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1377                     link_info->link_speed, link_info->auto_mode,
1378                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1379                     link_info->support_speeds, link_info->force_link_speed);
1380         return rc;
1381 }
1382
1383 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1384 {
1385         int rc = 0;
1386         struct hwrm_port_phy_qcaps_input req = {0};
1387         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1388         struct bnxt_link_info *link_info = bp->link_info;
1389
1390         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1391                 return 0;
1392
1393         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1394
1395         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1396
1397         HWRM_CHECK_RESULT();
1398
1399         bp->port_cnt = resp->port_cnt;
1400         if (resp->supported_speeds_auto_mode)
1401                 link_info->support_auto_speeds =
1402                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1403         if (resp->supported_pam4_speeds_auto_mode)
1404                 link_info->support_pam4_auto_speeds =
1405                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1406
1407         HWRM_UNLOCK();
1408
1409         return 0;
1410 }
1411
1412 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1413 {
1414         int i = 0;
1415
1416         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1417                 if (bp->tx_cos_queue[i].profile ==
1418                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1419                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1420                         return true;
1421                 }
1422         }
1423         return false;
1424 }
1425
1426 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1427 {
1428         int i = 0;
1429
1430         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1431                 if (bp->tx_cos_queue[i].profile !=
1432                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1433                     bp->tx_cos_queue[i].id !=
1434                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1435                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1436                         break;
1437                 }
1438         }
1439 }
1440
1441 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1442 {
1443         int rc = 0;
1444         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1445         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1446         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1447         int i;
1448
1449 get_rx_info:
1450         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1451
1452         req.flags = rte_cpu_to_le_32(dir);
1453         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1454         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1455             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1456                 req.drv_qmap_cap =
1457                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1458         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1459
1460         HWRM_CHECK_RESULT();
1461
1462         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1463                 GET_TX_QUEUE_INFO(0);
1464                 GET_TX_QUEUE_INFO(1);
1465                 GET_TX_QUEUE_INFO(2);
1466                 GET_TX_QUEUE_INFO(3);
1467                 GET_TX_QUEUE_INFO(4);
1468                 GET_TX_QUEUE_INFO(5);
1469                 GET_TX_QUEUE_INFO(6);
1470                 GET_TX_QUEUE_INFO(7);
1471         } else  {
1472                 GET_RX_QUEUE_INFO(0);
1473                 GET_RX_QUEUE_INFO(1);
1474                 GET_RX_QUEUE_INFO(2);
1475                 GET_RX_QUEUE_INFO(3);
1476                 GET_RX_QUEUE_INFO(4);
1477                 GET_RX_QUEUE_INFO(5);
1478                 GET_RX_QUEUE_INFO(6);
1479                 GET_RX_QUEUE_INFO(7);
1480         }
1481
1482         HWRM_UNLOCK();
1483
1484         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1485                 goto done;
1486
1487         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1488                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1489         } else {
1490                 int j;
1491
1492                 /* iterate and find the COSq profile to use for Tx */
1493                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1494                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1495                                 if (bp->tx_cos_queue[i].id != 0xff)
1496                                         bp->tx_cosq_id[j++] =
1497                                                 bp->tx_cos_queue[i].id;
1498                         }
1499                 } else {
1500                         /* When CoS classification is disabled, for normal NIC
1501                          * operations, ideally we should look to use LOSSY.
1502                          * If not found, fallback to the first valid profile
1503                          */
1504                         if (!bnxt_find_lossy_profile(bp))
1505                                 bnxt_find_first_valid_profile(bp);
1506
1507                 }
1508         }
1509
1510         bp->max_tc = resp->max_configurable_queues;
1511         bp->max_lltc = resp->max_configurable_lossless_queues;
1512         if (bp->max_tc > BNXT_MAX_QUEUE)
1513                 bp->max_tc = BNXT_MAX_QUEUE;
1514         bp->max_q = bp->max_tc;
1515
1516         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1517                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1518                 goto get_rx_info;
1519         }
1520
1521 done:
1522         return rc;
1523 }
1524
1525 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1526                          struct bnxt_ring *ring,
1527                          uint32_t ring_type, uint32_t map_index,
1528                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1529                          uint16_t tx_cosq_id)
1530 {
1531         int rc = 0;
1532         uint32_t enables = 0;
1533         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1534         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1535         struct rte_mempool *mb_pool;
1536         uint16_t rx_buf_size;
1537
1538         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1539
1540         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1541         req.fbo = rte_cpu_to_le_32(0);
1542         /* Association of ring index with doorbell index */
1543         req.logical_id = rte_cpu_to_le_16(map_index);
1544         req.length = rte_cpu_to_le_32(ring->ring_size);
1545
1546         switch (ring_type) {
1547         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1548                 req.ring_type = ring_type;
1549                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1550                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1551                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1552                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1553                         enables |=
1554                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1555                 break;
1556         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1557                 req.ring_type = ring_type;
1558                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1559                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1560                 if (BNXT_CHIP_THOR(bp)) {
1561                         mb_pool = bp->rx_queues[0]->mb_pool;
1562                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1563                                       RTE_PKTMBUF_HEADROOM;
1564                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1565                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1566                         enables |=
1567                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1568                 }
1569                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1570                         enables |=
1571                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1572                 break;
1573         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1574                 req.ring_type = ring_type;
1575                 if (BNXT_HAS_NQ(bp)) {
1576                         /* Association of cp ring with nq */
1577                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1578                         enables |=
1579                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1580                 }
1581                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1582                 break;
1583         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1584                 req.ring_type = ring_type;
1585                 req.page_size = BNXT_PAGE_SHFT;
1586                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1587                 break;
1588         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1589                 req.ring_type = ring_type;
1590                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1591
1592                 mb_pool = bp->rx_queues[0]->mb_pool;
1593                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1594                               RTE_PKTMBUF_HEADROOM;
1595                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1596                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1597
1598                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1599                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1600                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1601                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1602                 break;
1603         default:
1604                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1605                         ring_type);
1606                 HWRM_UNLOCK();
1607                 return -EINVAL;
1608         }
1609         req.enables = rte_cpu_to_le_32(enables);
1610
1611         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1612
1613         if (rc || resp->error_code) {
1614                 if (rc == 0 && resp->error_code)
1615                         rc = rte_le_to_cpu_16(resp->error_code);
1616                 switch (ring_type) {
1617                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1618                         PMD_DRV_LOG(ERR,
1619                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1620                         HWRM_UNLOCK();
1621                         return rc;
1622                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1623                         PMD_DRV_LOG(ERR,
1624                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1625                         HWRM_UNLOCK();
1626                         return rc;
1627                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1628                         PMD_DRV_LOG(ERR,
1629                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1630                                     rc);
1631                         HWRM_UNLOCK();
1632                         return rc;
1633                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1634                         PMD_DRV_LOG(ERR,
1635                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1636                         HWRM_UNLOCK();
1637                         return rc;
1638                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1639                         PMD_DRV_LOG(ERR,
1640                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1641                         HWRM_UNLOCK();
1642                         return rc;
1643                 default:
1644                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1645                         HWRM_UNLOCK();
1646                         return rc;
1647                 }
1648         }
1649
1650         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1651         HWRM_UNLOCK();
1652         return rc;
1653 }
1654
1655 int bnxt_hwrm_ring_free(struct bnxt *bp,
1656                         struct bnxt_ring *ring, uint32_t ring_type)
1657 {
1658         int rc;
1659         struct hwrm_ring_free_input req = {.req_type = 0 };
1660         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1661
1662         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1663
1664         req.ring_type = ring_type;
1665         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1666
1667         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1668
1669         if (rc || resp->error_code) {
1670                 if (rc == 0 && resp->error_code)
1671                         rc = rte_le_to_cpu_16(resp->error_code);
1672                 HWRM_UNLOCK();
1673
1674                 switch (ring_type) {
1675                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1676                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1677                                 rc);
1678                         return rc;
1679                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1680                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1681                                 rc);
1682                         return rc;
1683                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1684                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1685                                 rc);
1686                         return rc;
1687                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1688                         PMD_DRV_LOG(ERR,
1689                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1690                         return rc;
1691                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1692                         PMD_DRV_LOG(ERR,
1693                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1694                         return rc;
1695                 default:
1696                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1697                         return rc;
1698                 }
1699         }
1700         HWRM_UNLOCK();
1701         return 0;
1702 }
1703
1704 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1705 {
1706         int rc = 0;
1707         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1708         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1709
1710         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1711
1712         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1713         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1714         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1715         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1716
1717         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1718
1719         HWRM_CHECK_RESULT();
1720
1721         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1722
1723         HWRM_UNLOCK();
1724
1725         return rc;
1726 }
1727
1728 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1729 {
1730         int rc;
1731         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1732         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1733
1734         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1735
1736         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1737
1738         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1739
1740         HWRM_CHECK_RESULT();
1741         HWRM_UNLOCK();
1742
1743         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1744         return rc;
1745 }
1746
1747 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1748 {
1749         int rc = 0;
1750         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1751         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1752
1753         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1754                 return rc;
1755
1756         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1757
1758         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1759
1760         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1761
1762         HWRM_CHECK_RESULT();
1763         HWRM_UNLOCK();
1764
1765         return rc;
1766 }
1767
1768 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1769                                 unsigned int idx __rte_unused)
1770 {
1771         int rc;
1772         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1773         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1774
1775         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1776
1777         req.update_period_ms = rte_cpu_to_le_32(0);
1778
1779         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1780
1781         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1782
1783         HWRM_CHECK_RESULT();
1784
1785         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1786
1787         HWRM_UNLOCK();
1788
1789         return rc;
1790 }
1791
1792 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1793                                 unsigned int idx __rte_unused)
1794 {
1795         int rc;
1796         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1797         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1798
1799         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1800
1801         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1802
1803         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1804
1805         HWRM_CHECK_RESULT();
1806         HWRM_UNLOCK();
1807
1808         return rc;
1809 }
1810
1811 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1812 {
1813         int rc = 0, i, j;
1814         struct hwrm_vnic_alloc_input req = { 0 };
1815         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1816
1817         if (!BNXT_HAS_RING_GRPS(bp))
1818                 goto skip_ring_grps;
1819
1820         /* map ring groups to this vnic */
1821         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1822                 vnic->start_grp_id, vnic->end_grp_id);
1823         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1824                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1825
1826         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1827         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1828         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1829         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1830
1831 skip_ring_grps:
1832         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1833         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1834
1835         if (vnic->func_default)
1836                 req.flags =
1837                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1838         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1839
1840         HWRM_CHECK_RESULT();
1841
1842         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1843         HWRM_UNLOCK();
1844         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1845         return rc;
1846 }
1847
1848 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1849                                         struct bnxt_vnic_info *vnic,
1850                                         struct bnxt_plcmodes_cfg *pmode)
1851 {
1852         int rc = 0;
1853         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1854         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1855
1856         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1857
1858         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1859
1860         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1861
1862         HWRM_CHECK_RESULT();
1863
1864         pmode->flags = rte_le_to_cpu_32(resp->flags);
1865         /* dflt_vnic bit doesn't exist in the _cfg command */
1866         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1867         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1868         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1869         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1870
1871         HWRM_UNLOCK();
1872
1873         return rc;
1874 }
1875
1876 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1877                                        struct bnxt_vnic_info *vnic,
1878                                        struct bnxt_plcmodes_cfg *pmode)
1879 {
1880         int rc = 0;
1881         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1882         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1883
1884         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1885                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1886                 return rc;
1887         }
1888
1889         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1890
1891         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1892         req.flags = rte_cpu_to_le_32(pmode->flags);
1893         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1894         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1895         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1896         req.enables = rte_cpu_to_le_32(
1897             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1898             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1899             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1900         );
1901
1902         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1903
1904         HWRM_CHECK_RESULT();
1905         HWRM_UNLOCK();
1906
1907         return rc;
1908 }
1909
1910 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1911 {
1912         int rc = 0;
1913         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1914         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1915         struct bnxt_plcmodes_cfg pmodes = { 0 };
1916         uint32_t ctx_enable_flag = 0;
1917         uint32_t enables = 0;
1918
1919         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1920                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1921                 return rc;
1922         }
1923
1924         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1925         if (rc)
1926                 return rc;
1927
1928         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1929
1930         if (BNXT_CHIP_THOR(bp)) {
1931                 int dflt_rxq = vnic->start_grp_id;
1932                 struct bnxt_rx_ring_info *rxr;
1933                 struct bnxt_cp_ring_info *cpr;
1934                 struct bnxt_rx_queue *rxq;
1935                 int i;
1936
1937                 /*
1938                  * The first active receive ring is used as the VNIC
1939                  * default receive ring. If there are no active receive
1940                  * rings (all corresponding receive queues are stopped),
1941                  * the first receive ring is used.
1942                  */
1943                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1944                         rxq = bp->eth_dev->data->rx_queues[i];
1945                         if (rxq->rx_started) {
1946                                 dflt_rxq = i;
1947                                 break;
1948                         }
1949                 }
1950
1951                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1952                 rxr = rxq->rx_ring;
1953                 cpr = rxq->cp_ring;
1954
1955                 req.default_rx_ring_id =
1956                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1957                 req.default_cmpl_ring_id =
1958                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1959                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1960                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1961                 goto config_mru;
1962         }
1963
1964         /* Only RSS support for now TBD: COS & LB */
1965         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1966         if (vnic->lb_rule != 0xffff)
1967                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1968         if (vnic->cos_rule != 0xffff)
1969                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1970         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1971                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1972                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1973         }
1974         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1975                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1976                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1977         }
1978
1979         enables |= ctx_enable_flag;
1980         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1981         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1982         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1983         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1984
1985 config_mru:
1986         req.enables = rte_cpu_to_le_32(enables);
1987         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1988         req.mru = rte_cpu_to_le_16(vnic->mru);
1989         /* Configure default VNIC only once. */
1990         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1991                 req.flags |=
1992                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1993                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1994         }
1995         if (vnic->vlan_strip)
1996                 req.flags |=
1997                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1998         if (vnic->bd_stall)
1999                 req.flags |=
2000                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2001         if (vnic->roce_dual)
2002                 req.flags |= rte_cpu_to_le_32(
2003                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
2004         if (vnic->roce_only)
2005                 req.flags |= rte_cpu_to_le_32(
2006                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
2007         if (vnic->rss_dflt_cr)
2008                 req.flags |= rte_cpu_to_le_32(
2009                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2010
2011         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2012
2013         HWRM_CHECK_RESULT();
2014         HWRM_UNLOCK();
2015
2016         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2017
2018         return rc;
2019 }
2020
2021 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2022                 int16_t fw_vf_id)
2023 {
2024         int rc = 0;
2025         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2026         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2027
2028         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2029                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2030                 return rc;
2031         }
2032         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2033
2034         req.enables =
2035                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2036         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2037         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2038
2039         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2040
2041         HWRM_CHECK_RESULT();
2042
2043         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2044         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2045         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2046         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2047         vnic->mru = rte_le_to_cpu_16(resp->mru);
2048         vnic->func_default = rte_le_to_cpu_32(
2049                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2050         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2051                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2052         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2053                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2054         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
2055                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
2056         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
2057                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
2058         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2059                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2060
2061         HWRM_UNLOCK();
2062
2063         return rc;
2064 }
2065
2066 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2067                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2068 {
2069         int rc = 0;
2070         uint16_t ctx_id;
2071         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2072         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2073                                                 bp->hwrm_cmd_resp_addr;
2074
2075         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2076
2077         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2078         HWRM_CHECK_RESULT();
2079
2080         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2081         if (!BNXT_HAS_RING_GRPS(bp))
2082                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2083         else if (ctx_idx == 0)
2084                 vnic->rss_rule = ctx_id;
2085
2086         HWRM_UNLOCK();
2087
2088         return rc;
2089 }
2090
2091 static
2092 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2093                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2094 {
2095         int rc = 0;
2096         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2097         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2098                                                 bp->hwrm_cmd_resp_addr;
2099
2100         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2101                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2102                 return rc;
2103         }
2104         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2105
2106         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2107
2108         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2109
2110         HWRM_CHECK_RESULT();
2111         HWRM_UNLOCK();
2112
2113         return rc;
2114 }
2115
2116 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2117 {
2118         int rc = 0;
2119
2120         if (BNXT_CHIP_THOR(bp)) {
2121                 int j;
2122
2123                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2124                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2125                                                       vnic,
2126                                                       vnic->fw_grp_ids[j]);
2127                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2128                 }
2129                 vnic->num_lb_ctxts = 0;
2130         } else {
2131                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2132                 vnic->rss_rule = INVALID_HW_RING_ID;
2133         }
2134
2135         return rc;
2136 }
2137
2138 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2139 {
2140         int rc = 0;
2141         struct hwrm_vnic_free_input req = {.req_type = 0 };
2142         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2143
2144         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2145                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2146                 return rc;
2147         }
2148
2149         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2150
2151         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2152
2153         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2154
2155         HWRM_CHECK_RESULT();
2156         HWRM_UNLOCK();
2157
2158         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2159         /* Configure default VNIC again if necessary. */
2160         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2161                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2162
2163         return rc;
2164 }
2165
2166 static int
2167 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2168 {
2169         int i;
2170         int rc = 0;
2171         int nr_ctxs = vnic->num_lb_ctxts;
2172         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2173         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2174
2175         for (i = 0; i < nr_ctxs; i++) {
2176                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2177
2178                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2179                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2180                 req.hash_mode_flags = vnic->hash_mode;
2181
2182                 req.hash_key_tbl_addr =
2183                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2184
2185                 req.ring_grp_tbl_addr =
2186                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2187                                          i * HW_HASH_INDEX_SIZE);
2188                 req.ring_table_pair_index = i;
2189                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2190
2191                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2192                                             BNXT_USE_CHIMP_MB);
2193
2194                 HWRM_CHECK_RESULT();
2195                 HWRM_UNLOCK();
2196         }
2197
2198         return rc;
2199 }
2200
2201 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2202                            struct bnxt_vnic_info *vnic)
2203 {
2204         int rc = 0;
2205         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2206         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2207
2208         if (!vnic->rss_table)
2209                 return 0;
2210
2211         if (BNXT_CHIP_THOR(bp))
2212                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2213
2214         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2215
2216         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2217         req.hash_mode_flags = vnic->hash_mode;
2218
2219         req.ring_grp_tbl_addr =
2220             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2221         req.hash_key_tbl_addr =
2222             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2223         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2224         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2225
2226         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2227
2228         HWRM_CHECK_RESULT();
2229         HWRM_UNLOCK();
2230
2231         return rc;
2232 }
2233
2234 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2235                         struct bnxt_vnic_info *vnic)
2236 {
2237         int rc = 0;
2238         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2239         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2240         uint16_t size;
2241
2242         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2243                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2244                 return rc;
2245         }
2246
2247         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2248
2249         req.flags = rte_cpu_to_le_32(
2250                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2251
2252         req.enables = rte_cpu_to_le_32(
2253                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2254
2255         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2256         size -= RTE_PKTMBUF_HEADROOM;
2257         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2258
2259         req.jumbo_thresh = rte_cpu_to_le_16(size);
2260         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2261
2262         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2263
2264         HWRM_CHECK_RESULT();
2265         HWRM_UNLOCK();
2266
2267         return rc;
2268 }
2269
2270 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2271                         struct bnxt_vnic_info *vnic, bool enable)
2272 {
2273         int rc = 0;
2274         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2275         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2276
2277         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2278                 if (enable)
2279                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2280                 return -ENOTSUP;
2281         }
2282
2283         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2284                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2285                 return 0;
2286         }
2287
2288         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2289
2290         if (enable) {
2291                 req.enables = rte_cpu_to_le_32(
2292                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2293                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2294                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2295                 req.flags = rte_cpu_to_le_32(
2296                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2297                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2298                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2299                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2300                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2301                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2302                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2303                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2304                 req.min_agg_len = rte_cpu_to_le_32(512);
2305         }
2306         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2307
2308         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2309
2310         HWRM_CHECK_RESULT();
2311         HWRM_UNLOCK();
2312
2313         return rc;
2314 }
2315
2316 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2317 {
2318         struct hwrm_func_cfg_input req = {0};
2319         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2320         int rc;
2321
2322         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2323         req.enables = rte_cpu_to_le_32(
2324                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2325         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2326         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2327
2328         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2329
2330         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2331         HWRM_CHECK_RESULT();
2332         HWRM_UNLOCK();
2333
2334         bp->pf->vf_info[vf].random_mac = false;
2335
2336         return rc;
2337 }
2338
2339 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2340                                   uint64_t *dropped)
2341 {
2342         int rc = 0;
2343         struct hwrm_func_qstats_input req = {.req_type = 0};
2344         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2345
2346         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2347
2348         req.fid = rte_cpu_to_le_16(fid);
2349
2350         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2351
2352         HWRM_CHECK_RESULT();
2353
2354         if (dropped)
2355                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2356
2357         HWRM_UNLOCK();
2358
2359         return rc;
2360 }
2361
2362 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2363                           struct rte_eth_stats *stats,
2364                           struct hwrm_func_qstats_output *func_qstats)
2365 {
2366         int rc = 0;
2367         struct hwrm_func_qstats_input req = {.req_type = 0};
2368         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2369
2370         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2371
2372         req.fid = rte_cpu_to_le_16(fid);
2373
2374         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2375
2376         HWRM_CHECK_RESULT();
2377         if (func_qstats)
2378                 memcpy(func_qstats, resp,
2379                        sizeof(struct hwrm_func_qstats_output));
2380
2381         if (!stats)
2382                 goto exit;
2383
2384         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2385         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2386         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2387         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2388         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2389         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2390
2391         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2392         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2393         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2394         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2395         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2396         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2397
2398         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2399         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2400         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2401
2402 exit:
2403         HWRM_UNLOCK();
2404
2405         return rc;
2406 }
2407
2408 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2409 {
2410         int rc = 0;
2411         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2412         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2413
2414         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2415
2416         req.fid = rte_cpu_to_le_16(fid);
2417
2418         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2419
2420         HWRM_CHECK_RESULT();
2421         HWRM_UNLOCK();
2422
2423         return rc;
2424 }
2425
2426 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2427 {
2428         unsigned int i;
2429         int rc = 0;
2430
2431         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2432                 struct bnxt_tx_queue *txq;
2433                 struct bnxt_rx_queue *rxq;
2434                 struct bnxt_cp_ring_info *cpr;
2435
2436                 if (i >= bp->rx_cp_nr_rings) {
2437                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2438                         cpr = txq->cp_ring;
2439                 } else {
2440                         rxq = bp->rx_queues[i];
2441                         cpr = rxq->cp_ring;
2442                 }
2443
2444                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2445                 if (rc)
2446                         return rc;
2447         }
2448         return 0;
2449 }
2450
2451 static int
2452 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2453 {
2454         int rc;
2455         unsigned int i;
2456         struct bnxt_cp_ring_info *cpr;
2457
2458         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2459
2460                 if (i >= bp->rx_cp_nr_rings) {
2461                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2462                 } else {
2463                         cpr = bp->rx_queues[i]->cp_ring;
2464                         if (BNXT_HAS_RING_GRPS(bp))
2465                                 bp->grp_info[i].fw_stats_ctx = -1;
2466                 }
2467                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2468                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2469                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2470                         if (rc)
2471                                 return rc;
2472                 }
2473         }
2474         return 0;
2475 }
2476
2477 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2478 {
2479         unsigned int i;
2480         int rc = 0;
2481
2482         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2483                 struct bnxt_tx_queue *txq;
2484                 struct bnxt_rx_queue *rxq;
2485                 struct bnxt_cp_ring_info *cpr;
2486
2487                 if (i >= bp->rx_cp_nr_rings) {
2488                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2489                         cpr = txq->cp_ring;
2490                 } else {
2491                         rxq = bp->rx_queues[i];
2492                         cpr = rxq->cp_ring;
2493                 }
2494
2495                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2496
2497                 if (rc)
2498                         return rc;
2499         }
2500         return rc;
2501 }
2502
2503 static int
2504 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2505 {
2506         uint16_t idx;
2507         uint32_t rc = 0;
2508
2509         if (!BNXT_HAS_RING_GRPS(bp))
2510                 return 0;
2511
2512         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2513
2514                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2515                         continue;
2516
2517                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2518
2519                 if (rc)
2520                         return rc;
2521         }
2522         return rc;
2523 }
2524
2525 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2526 {
2527         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2528
2529         bnxt_hwrm_ring_free(bp, cp_ring,
2530                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2531         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2532         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2533                                      sizeof(*cpr->cp_desc_ring));
2534         cpr->cp_raw_cons = 0;
2535         cpr->valid = 0;
2536 }
2537
2538 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2539 {
2540         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2541
2542         bnxt_hwrm_ring_free(bp, cp_ring,
2543                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2544         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2545         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2546                         sizeof(*cpr->cp_desc_ring));
2547         cpr->cp_raw_cons = 0;
2548         cpr->valid = 0;
2549 }
2550
2551 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2552 {
2553         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2554         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2555         struct bnxt_ring *ring = rxr->rx_ring_struct;
2556         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2557
2558         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2559                 bnxt_hwrm_ring_free(bp, ring,
2560                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2561                 ring->fw_ring_id = INVALID_HW_RING_ID;
2562                 if (BNXT_HAS_RING_GRPS(bp))
2563                         bp->grp_info[queue_index].rx_fw_ring_id =
2564                                                         INVALID_HW_RING_ID;
2565         }
2566         ring = rxr->ag_ring_struct;
2567         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2568                 bnxt_hwrm_ring_free(bp, ring,
2569                                     BNXT_CHIP_THOR(bp) ?
2570                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2571                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2572                 if (BNXT_HAS_RING_GRPS(bp))
2573                         bp->grp_info[queue_index].ag_fw_ring_id =
2574                                                         INVALID_HW_RING_ID;
2575         }
2576         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2577                 bnxt_free_cp_ring(bp, cpr);
2578
2579         if (BNXT_HAS_RING_GRPS(bp))
2580                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2581 }
2582
2583 static int
2584 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2585 {
2586         unsigned int i;
2587
2588         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2589                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2590                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2591                 struct bnxt_ring *ring = txr->tx_ring_struct;
2592                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2593
2594                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2595                         bnxt_hwrm_ring_free(bp, ring,
2596                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2597                         ring->fw_ring_id = INVALID_HW_RING_ID;
2598                         memset(txr->tx_desc_ring, 0,
2599                                         txr->tx_ring_struct->ring_size *
2600                                         sizeof(*txr->tx_desc_ring));
2601                         memset(txr->tx_buf_ring, 0,
2602                                         txr->tx_ring_struct->ring_size *
2603                                         sizeof(*txr->tx_buf_ring));
2604                         txr->tx_prod = 0;
2605                         txr->tx_cons = 0;
2606                 }
2607                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2608                         bnxt_free_cp_ring(bp, cpr);
2609                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2610                 }
2611         }
2612
2613         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2614                 bnxt_free_hwrm_rx_ring(bp, i);
2615
2616         return 0;
2617 }
2618
2619 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2620 {
2621         uint16_t i;
2622         uint32_t rc = 0;
2623
2624         if (!BNXT_HAS_RING_GRPS(bp))
2625                 return 0;
2626
2627         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2628                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2629                 if (rc)
2630                         return rc;
2631         }
2632         return rc;
2633 }
2634
2635 /*
2636  * HWRM utility functions
2637  */
2638
2639 void bnxt_free_hwrm_resources(struct bnxt *bp)
2640 {
2641         /* Release memzone */
2642         rte_free(bp->hwrm_cmd_resp_addr);
2643         rte_free(bp->hwrm_short_cmd_req_addr);
2644         bp->hwrm_cmd_resp_addr = NULL;
2645         bp->hwrm_short_cmd_req_addr = NULL;
2646         bp->hwrm_cmd_resp_dma_addr = 0;
2647         bp->hwrm_short_cmd_req_dma_addr = 0;
2648 }
2649
2650 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2651 {
2652         struct rte_pci_device *pdev = bp->pdev;
2653         char type[RTE_MEMZONE_NAMESIZE];
2654
2655         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2656                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2657         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2658         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2659         if (bp->hwrm_cmd_resp_addr == NULL)
2660                 return -ENOMEM;
2661         bp->hwrm_cmd_resp_dma_addr =
2662                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2663         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2664                 PMD_DRV_LOG(ERR,
2665                         "unable to map response address to physical memory\n");
2666                 return -ENOMEM;
2667         }
2668         rte_spinlock_init(&bp->hwrm_lock);
2669
2670         return 0;
2671 }
2672
2673 int
2674 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2675 {
2676         int rc = 0;
2677
2678         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2679                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2680                 if (rc)
2681                         return rc;
2682         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2683                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2684                 if (rc)
2685                         return rc;
2686         }
2687
2688         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2689         return rc;
2690 }
2691
2692 static int
2693 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2694 {
2695         struct bnxt_filter_info *filter;
2696         int rc = 0;
2697
2698         STAILQ_FOREACH(filter, &vnic->filter, next) {
2699                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2700                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2701                 bnxt_free_filter(bp, filter);
2702         }
2703         return rc;
2704 }
2705
2706 static int
2707 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2708 {
2709         struct bnxt_filter_info *filter;
2710         struct rte_flow *flow;
2711         int rc = 0;
2712
2713         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2714                 flow = STAILQ_FIRST(&vnic->flow_list);
2715                 filter = flow->filter;
2716                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2717                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2718
2719                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2720                 rte_free(flow);
2721         }
2722         return rc;
2723 }
2724
2725 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2726 {
2727         struct bnxt_filter_info *filter;
2728         int rc = 0;
2729
2730         STAILQ_FOREACH(filter, &vnic->filter, next) {
2731                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2732                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2733                                                      filter);
2734                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2735                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2736                                                          filter);
2737                 else
2738                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2739                                                      filter);
2740                 if (rc)
2741                         break;
2742         }
2743         return rc;
2744 }
2745
2746 static void
2747 bnxt_free_tunnel_ports(struct bnxt *bp)
2748 {
2749         if (bp->vxlan_port_cnt)
2750                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2751                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2752         bp->vxlan_port = 0;
2753         if (bp->geneve_port_cnt)
2754                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2755                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2756         bp->geneve_port = 0;
2757 }
2758
2759 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2760 {
2761         int i;
2762
2763         if (bp->vnic_info == NULL)
2764                 return;
2765
2766         /*
2767          * Cleanup VNICs in reverse order, to make sure the L2 filter
2768          * from vnic0 is last to be cleaned up.
2769          */
2770         for (i = bp->max_vnics - 1; i >= 0; i--) {
2771                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2772
2773                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2774                         continue;
2775
2776                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2777
2778                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2779
2780                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2781
2782                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2783
2784                 bnxt_hwrm_vnic_free(bp, vnic);
2785
2786                 rte_free(vnic->fw_grp_ids);
2787         }
2788         /* Ring resources */
2789         bnxt_free_all_hwrm_rings(bp);
2790         bnxt_free_all_hwrm_ring_grps(bp);
2791         bnxt_free_all_hwrm_stat_ctxs(bp);
2792         bnxt_free_tunnel_ports(bp);
2793 }
2794
2795 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2796 {
2797         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2798
2799         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2800                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2801
2802         switch (conf_link_speed) {
2803         case ETH_LINK_SPEED_10M_HD:
2804         case ETH_LINK_SPEED_100M_HD:
2805                 /* FALLTHROUGH */
2806                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2807         }
2808         return hw_link_duplex;
2809 }
2810
2811 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2812 {
2813         return !conf_link;
2814 }
2815
2816 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2817                                           uint16_t pam4_link)
2818 {
2819         uint16_t eth_link_speed = 0;
2820
2821         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2822                 return ETH_LINK_SPEED_AUTONEG;
2823
2824         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2825         case ETH_LINK_SPEED_100M:
2826         case ETH_LINK_SPEED_100M_HD:
2827                 /* FALLTHROUGH */
2828                 eth_link_speed =
2829                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2830                 break;
2831         case ETH_LINK_SPEED_1G:
2832                 eth_link_speed =
2833                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2834                 break;
2835         case ETH_LINK_SPEED_2_5G:
2836                 eth_link_speed =
2837                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2838                 break;
2839         case ETH_LINK_SPEED_10G:
2840                 eth_link_speed =
2841                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2842                 break;
2843         case ETH_LINK_SPEED_20G:
2844                 eth_link_speed =
2845                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2846                 break;
2847         case ETH_LINK_SPEED_25G:
2848                 eth_link_speed =
2849                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2850                 break;
2851         case ETH_LINK_SPEED_40G:
2852                 eth_link_speed =
2853                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2854                 break;
2855         case ETH_LINK_SPEED_50G:
2856                 eth_link_speed = pam4_link ?
2857                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
2858                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2859                 break;
2860         case ETH_LINK_SPEED_100G:
2861                 eth_link_speed = pam4_link ?
2862                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
2863                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2864                 break;
2865         case ETH_LINK_SPEED_200G:
2866                 eth_link_speed =
2867                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2868                 break;
2869         default:
2870                 PMD_DRV_LOG(ERR,
2871                         "Unsupported link speed %d; default to AUTO\n",
2872                         conf_link_speed);
2873                 break;
2874         }
2875         return eth_link_speed;
2876 }
2877
2878 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2879                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2880                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2881                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2882                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2883
2884 static int bnxt_validate_link_speed(struct bnxt *bp)
2885 {
2886         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2887         uint16_t port_id = bp->eth_dev->data->port_id;
2888         uint32_t link_speed_capa;
2889         uint32_t one_speed;
2890
2891         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2892                 return 0;
2893
2894         link_speed_capa = bnxt_get_speed_capabilities(bp);
2895
2896         if (link_speed & ETH_LINK_SPEED_FIXED) {
2897                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2898
2899                 if (one_speed & (one_speed - 1)) {
2900                         PMD_DRV_LOG(ERR,
2901                                 "Invalid advertised speeds (%u) for port %u\n",
2902                                 link_speed, port_id);
2903                         return -EINVAL;
2904                 }
2905                 if ((one_speed & link_speed_capa) != one_speed) {
2906                         PMD_DRV_LOG(ERR,
2907                                 "Unsupported advertised speed (%u) for port %u\n",
2908                                 link_speed, port_id);
2909                         return -EINVAL;
2910                 }
2911         } else {
2912                 if (!(link_speed & link_speed_capa)) {
2913                         PMD_DRV_LOG(ERR,
2914                                 "Unsupported advertised speeds (%u) for port %u\n",
2915                                 link_speed, port_id);
2916                         return -EINVAL;
2917                 }
2918         }
2919         return 0;
2920 }
2921
2922 static uint16_t
2923 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2924 {
2925         uint16_t ret = 0;
2926
2927         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2928                 if (bp->link_info->support_speeds)
2929                         return bp->link_info->support_speeds;
2930                 link_speed = BNXT_SUPPORTED_SPEEDS;
2931         }
2932
2933         if (link_speed & ETH_LINK_SPEED_100M)
2934                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2935         if (link_speed & ETH_LINK_SPEED_100M_HD)
2936                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2937         if (link_speed & ETH_LINK_SPEED_1G)
2938                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2939         if (link_speed & ETH_LINK_SPEED_2_5G)
2940                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2941         if (link_speed & ETH_LINK_SPEED_10G)
2942                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2943         if (link_speed & ETH_LINK_SPEED_20G)
2944                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2945         if (link_speed & ETH_LINK_SPEED_25G)
2946                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2947         if (link_speed & ETH_LINK_SPEED_40G)
2948                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2949         if (link_speed & ETH_LINK_SPEED_50G)
2950                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2951         if (link_speed & ETH_LINK_SPEED_100G)
2952                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2953         if (link_speed & ETH_LINK_SPEED_200G)
2954                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2955         return ret;
2956 }
2957
2958 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2959 {
2960         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2961
2962         switch (hw_link_speed) {
2963         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2964                 eth_link_speed = ETH_SPEED_NUM_100M;
2965                 break;
2966         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2967                 eth_link_speed = ETH_SPEED_NUM_1G;
2968                 break;
2969         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2970                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2971                 break;
2972         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2973                 eth_link_speed = ETH_SPEED_NUM_10G;
2974                 break;
2975         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2976                 eth_link_speed = ETH_SPEED_NUM_20G;
2977                 break;
2978         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2979                 eth_link_speed = ETH_SPEED_NUM_25G;
2980                 break;
2981         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2982                 eth_link_speed = ETH_SPEED_NUM_40G;
2983                 break;
2984         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2985                 eth_link_speed = ETH_SPEED_NUM_50G;
2986                 break;
2987         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2988                 eth_link_speed = ETH_SPEED_NUM_100G;
2989                 break;
2990         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
2991                 eth_link_speed = ETH_SPEED_NUM_200G;
2992                 break;
2993         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2994         default:
2995                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2996                         hw_link_speed);
2997                 break;
2998         }
2999         return eth_link_speed;
3000 }
3001
3002 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3003 {
3004         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3005
3006         switch (hw_link_duplex) {
3007         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3008         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3009                 /* FALLTHROUGH */
3010                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3011                 break;
3012         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3013                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3014                 break;
3015         default:
3016                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3017                         hw_link_duplex);
3018                 break;
3019         }
3020         return eth_link_duplex;
3021 }
3022
3023 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3024 {
3025         int rc = 0;
3026         struct bnxt_link_info *link_info = bp->link_info;
3027
3028         rc = bnxt_hwrm_port_phy_qcaps(bp);
3029         if (rc)
3030                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3031
3032         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3033         if (rc) {
3034                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3035                 goto exit;
3036         }
3037
3038         if (link_info->link_speed)
3039                 link->link_speed =
3040                         bnxt_parse_hw_link_speed(link_info->link_speed);
3041         else
3042                 link->link_speed = ETH_SPEED_NUM_NONE;
3043         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3044         link->link_status = link_info->link_up;
3045         link->link_autoneg = link_info->auto_mode ==
3046                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3047                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3048 exit:
3049         return rc;
3050 }
3051
3052 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3053 {
3054         int rc = 0;
3055         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3056         struct bnxt_link_info link_req;
3057         uint16_t speed, autoneg;
3058
3059         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3060                 return 0;
3061
3062         rc = bnxt_validate_link_speed(bp);
3063         if (rc)
3064                 goto error;
3065
3066         memset(&link_req, 0, sizeof(link_req));
3067         link_req.link_up = link_up;
3068         if (!link_up)
3069                 goto port_phy_cfg;
3070
3071         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3072         if (BNXT_CHIP_THOR(bp) &&
3073             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3074                 /* 40G is not supported as part of media auto detect.
3075                  * The speed should be forced and autoneg disabled
3076                  * to configure 40G speed.
3077                  */
3078                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3079                 autoneg = 0;
3080         }
3081
3082         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3083                                           bp->link_info->link_signal_mode);
3084         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3085         /* Autoneg can be done only when the FW allows.
3086          * When user configures fixed speed of 40G and later changes to
3087          * any other speed, auto_link_speed/force_link_speed is still set
3088          * to 40G until link comes up at new speed.
3089          */
3090         if (autoneg == 1 &&
3091             !(!BNXT_CHIP_THOR(bp) &&
3092               (bp->link_info->auto_link_speed ||
3093                bp->link_info->force_link_speed))) {
3094                 link_req.phy_flags |=
3095                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3096                 link_req.auto_link_speed_mask =
3097                         bnxt_parse_eth_link_speed_mask(bp,
3098                                                        dev_conf->link_speeds);
3099         } else {
3100                 if (bp->link_info->phy_type ==
3101                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3102                     bp->link_info->phy_type ==
3103                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3104                     bp->link_info->media_type ==
3105                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3106                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3107                         return -EINVAL;
3108                 }
3109
3110                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3111                 /* If user wants a particular speed try that first. */
3112                 if (speed)
3113                         link_req.link_speed = speed;
3114                 else if (bp->link_info->force_pam4_link_speed)
3115                         link_req.link_speed =
3116                                 bp->link_info->force_pam4_link_speed;
3117                 else if (bp->link_info->auto_pam4_link_speeds)
3118                         link_req.link_speed =
3119                                 bp->link_info->auto_pam4_link_speeds;
3120                 else if (bp->link_info->support_pam4_speeds)
3121                         link_req.link_speed =
3122                                 bp->link_info->support_pam4_speeds;
3123                 else if (bp->link_info->force_link_speed)
3124                         link_req.link_speed = bp->link_info->force_link_speed;
3125                 else
3126                         link_req.link_speed = bp->link_info->auto_link_speed;
3127         }
3128         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3129         link_req.auto_pause = bp->link_info->auto_pause;
3130         link_req.force_pause = bp->link_info->force_pause;
3131
3132 port_phy_cfg:
3133         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3134         if (rc) {
3135                 PMD_DRV_LOG(ERR,
3136                         "Set link config failed with rc %d\n", rc);
3137         }
3138
3139 error:
3140         return rc;
3141 }
3142
3143 /* JIRA 22088 */
3144 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3145 {
3146         struct hwrm_func_qcfg_input req = {0};
3147         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3148         uint16_t flags;
3149         int rc = 0;
3150         bp->func_svif = BNXT_SVIF_INVALID;
3151         uint16_t svif_info;
3152
3153         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3154         req.fid = rte_cpu_to_le_16(0xffff);
3155
3156         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3157
3158         HWRM_CHECK_RESULT();
3159
3160         /* Hard Coded.. 0xfff VLAN ID mask */
3161         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3162
3163         svif_info = rte_le_to_cpu_16(resp->svif_info);
3164         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3165                 bp->func_svif = svif_info &
3166                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3167
3168         flags = rte_le_to_cpu_16(resp->flags);
3169         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3170                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3171
3172         if (BNXT_VF(bp) &&
3173             !BNXT_VF_IS_TRUSTED(bp) &&
3174             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3175                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3176                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3177         } else if (BNXT_VF(bp) &&
3178                    BNXT_VF_IS_TRUSTED(bp) &&
3179                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3180                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3181                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3182         }
3183
3184         if (mtu)
3185                 *mtu = rte_le_to_cpu_16(resp->mtu);
3186
3187         switch (resp->port_partition_type) {
3188         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3189         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3190         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3191                 /* FALLTHROUGH */
3192                 bp->flags |= BNXT_FLAG_NPAR_PF;
3193                 break;
3194         default:
3195                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3196                 break;
3197         }
3198
3199         HWRM_UNLOCK();
3200
3201         return rc;
3202 }
3203
3204 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3205 {
3206         struct hwrm_func_qcfg_input req = {0};
3207         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3208         int rc;
3209
3210         if (!BNXT_VF_IS_TRUSTED(bp))
3211                 return 0;
3212
3213         if (!bp->parent)
3214                 return -EINVAL;
3215
3216         bp->parent->fid = BNXT_PF_FID_INVALID;
3217
3218         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3219
3220         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3221
3222         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3223
3224         HWRM_CHECK_RESULT();
3225
3226         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3227         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3228         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3229         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3230
3231         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3232         if (bp->parent->vnic == 0) {
3233                 PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
3234                 /* Use hard-coded values appropriate for current Wh+ fw. */
3235                 if (bp->parent->fid == 2)
3236                         bp->parent->vnic = 0x100;
3237                 else
3238                         bp->parent->vnic = 1;
3239         }
3240
3241         HWRM_UNLOCK();
3242
3243         return 0;
3244 }
3245
3246 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3247                                  uint16_t *vnic_id, uint16_t *svif)
3248 {
3249         struct hwrm_func_qcfg_input req = {0};
3250         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3251         uint16_t svif_info;
3252         int rc = 0;
3253
3254         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3255         req.fid = rte_cpu_to_le_16(fid);
3256
3257         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3258
3259         HWRM_CHECK_RESULT();
3260
3261         if (vnic_id)
3262                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3263
3264         svif_info = rte_le_to_cpu_16(resp->svif_info);
3265         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3266                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3267
3268         HWRM_UNLOCK();
3269
3270         return rc;
3271 }
3272
3273 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3274 {
3275         struct hwrm_port_mac_qcfg_input req = {0};
3276         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3277         uint16_t port_svif_info;
3278         int rc;
3279
3280         bp->port_svif = BNXT_SVIF_INVALID;
3281
3282         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3283                 return 0;
3284
3285         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3286
3287         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3288
3289         HWRM_CHECK_RESULT_SILENT();
3290
3291         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3292         if (port_svif_info &
3293             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3294                 bp->port_svif = port_svif_info &
3295                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3296
3297         HWRM_UNLOCK();
3298
3299         return 0;
3300 }
3301
3302 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3303                                    struct hwrm_func_qcaps_output *qcaps)
3304 {
3305         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3306         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3307                sizeof(qcaps->mac_address));
3308         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3309         qcaps->max_rx_rings = fcfg->num_rx_rings;
3310         qcaps->max_tx_rings = fcfg->num_tx_rings;
3311         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3312         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3313         qcaps->max_vfs = 0;
3314         qcaps->first_vf_id = 0;
3315         qcaps->max_vnics = fcfg->num_vnics;
3316         qcaps->max_decap_records = 0;
3317         qcaps->max_encap_records = 0;
3318         qcaps->max_tx_wm_flows = 0;
3319         qcaps->max_tx_em_flows = 0;
3320         qcaps->max_rx_wm_flows = 0;
3321         qcaps->max_rx_em_flows = 0;
3322         qcaps->max_flow_id = 0;
3323         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3324         qcaps->max_sp_tx_rings = 0;
3325         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3326 }
3327
3328 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3329 {
3330         struct hwrm_func_cfg_input req = {0};
3331         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3332         uint32_t enables;
3333         int rc;
3334
3335         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3336                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3337                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3338                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3339                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3340                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3341                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3342                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3343                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3344
3345         if (BNXT_HAS_RING_GRPS(bp)) {
3346                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3347                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3348         } else if (BNXT_HAS_NQ(bp)) {
3349                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3350                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3351         }
3352
3353         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3354         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3355         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3356         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3357         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3358         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3359         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3360         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3361         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3362         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3363         req.fid = rte_cpu_to_le_16(0xffff);
3364         req.enables = rte_cpu_to_le_32(enables);
3365
3366         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3367
3368         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3369
3370         HWRM_CHECK_RESULT();
3371         HWRM_UNLOCK();
3372
3373         return rc;
3374 }
3375
3376 static void populate_vf_func_cfg_req(struct bnxt *bp,
3377                                      struct hwrm_func_cfg_input *req,
3378                                      int num_vfs)
3379 {
3380         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3381                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3382                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3383                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3384                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3385                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3386                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3387                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3388                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3389                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3390
3391         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3392                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3393                                     BNXT_NUM_VLANS);
3394         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3395         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3396                                                 (num_vfs + 1));
3397         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3398         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3399                                                (num_vfs + 1));
3400         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3401         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3402         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3403         /* TODO: For now, do not support VMDq/RFS on VFs. */
3404         req->num_vnics = rte_cpu_to_le_16(1);
3405         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3406                                                  (num_vfs + 1));
3407 }
3408
3409 static void add_random_mac_if_needed(struct bnxt *bp,
3410                                      struct hwrm_func_cfg_input *cfg_req,
3411                                      int vf)
3412 {
3413         struct rte_ether_addr mac;
3414
3415         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3416                 return;
3417
3418         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3419                 cfg_req->enables |=
3420                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3421                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3422                 bp->pf->vf_info[vf].random_mac = true;
3423         } else {
3424                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3425                         RTE_ETHER_ADDR_LEN);
3426         }
3427 }
3428
3429 static int reserve_resources_from_vf(struct bnxt *bp,
3430                                      struct hwrm_func_cfg_input *cfg_req,
3431                                      int vf)
3432 {
3433         struct hwrm_func_qcaps_input req = {0};
3434         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3435         int rc;
3436
3437         /* Get the actual allocated values now */
3438         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3439         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3441
3442         if (rc) {
3443                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3444                 copy_func_cfg_to_qcaps(cfg_req, resp);
3445         } else if (resp->error_code) {
3446                 rc = rte_le_to_cpu_16(resp->error_code);
3447                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3448                 copy_func_cfg_to_qcaps(cfg_req, resp);
3449         }
3450
3451         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3452         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3453         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3454         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3455         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3456         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3457         /*
3458          * TODO: While not supporting VMDq with VFs, max_vnics is always
3459          * forced to 1 in this case
3460          */
3461         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3462         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3463
3464         HWRM_UNLOCK();
3465
3466         return 0;
3467 }
3468
3469 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3470 {
3471         struct hwrm_func_qcfg_input req = {0};
3472         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3473         int rc;
3474
3475         /* Check for zero MAC address */
3476         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3477         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3478         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3479         HWRM_CHECK_RESULT();
3480         rc = rte_le_to_cpu_16(resp->vlan);
3481
3482         HWRM_UNLOCK();
3483
3484         return rc;
3485 }
3486
3487 static int update_pf_resource_max(struct bnxt *bp)
3488 {
3489         struct hwrm_func_qcfg_input req = {0};
3490         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3491         int rc;
3492
3493         /* And copy the allocated numbers into the pf struct */
3494         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3495         req.fid = rte_cpu_to_le_16(0xffff);
3496         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3497         HWRM_CHECK_RESULT();
3498
3499         /* Only TX ring value reflects actual allocation? TODO */
3500         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3501         bp->pf->evb_mode = resp->evb_mode;
3502
3503         HWRM_UNLOCK();
3504
3505         return rc;
3506 }
3507
3508 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3509 {
3510         int rc;
3511
3512         if (!BNXT_PF(bp)) {
3513                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3514                 return -EINVAL;
3515         }
3516
3517         rc = bnxt_hwrm_func_qcaps(bp);
3518         if (rc)
3519                 return rc;
3520
3521         bp->pf->func_cfg_flags &=
3522                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3523                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3524         bp->pf->func_cfg_flags |=
3525                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3526         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3527         rc = __bnxt_hwrm_func_qcaps(bp);
3528         return rc;
3529 }
3530
3531 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3532 {
3533         struct hwrm_func_cfg_input req = {0};
3534         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3535         int i;
3536         size_t sz;
3537         int rc = 0;
3538         size_t req_buf_sz;
3539
3540         if (!BNXT_PF(bp)) {
3541                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3542                 return -EINVAL;
3543         }
3544
3545         rc = bnxt_hwrm_func_qcaps(bp);
3546
3547         if (rc)
3548                 return rc;
3549
3550         bp->pf->active_vfs = num_vfs;
3551
3552         /*
3553          * First, configure the PF to only use one TX ring.  This ensures that
3554          * there are enough rings for all VFs.
3555          *
3556          * If we don't do this, when we call func_alloc() later, we will lock
3557          * extra rings to the PF that won't be available during func_cfg() of
3558          * the VFs.
3559          *
3560          * This has been fixed with firmware versions above 20.6.54
3561          */
3562         bp->pf->func_cfg_flags &=
3563                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3564                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3565         bp->pf->func_cfg_flags |=
3566                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3567         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3568         if (rc)
3569                 return rc;
3570
3571         /*
3572          * Now, create and register a buffer to hold forwarded VF requests
3573          */
3574         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3575         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3576                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3577         if (bp->pf->vf_req_buf == NULL) {
3578                 rc = -ENOMEM;
3579                 goto error_free;
3580         }
3581         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3582                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3583         for (i = 0; i < num_vfs; i++)
3584                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3585                                         (i * HWRM_MAX_REQ_LEN);
3586
3587         rc = bnxt_hwrm_func_buf_rgtr(bp);
3588         if (rc)
3589                 goto error_free;
3590
3591         populate_vf_func_cfg_req(bp, &req, num_vfs);
3592
3593         bp->pf->active_vfs = 0;
3594         for (i = 0; i < num_vfs; i++) {
3595                 add_random_mac_if_needed(bp, &req, i);
3596
3597                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3598                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3599                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3600                 rc = bnxt_hwrm_send_message(bp,
3601                                             &req,
3602                                             sizeof(req),
3603                                             BNXT_USE_CHIMP_MB);
3604
3605                 /* Clear enable flag for next pass */
3606                 req.enables &= ~rte_cpu_to_le_32(
3607                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3608
3609                 if (rc || resp->error_code) {
3610                         PMD_DRV_LOG(ERR,
3611                                 "Failed to initizlie VF %d\n", i);
3612                         PMD_DRV_LOG(ERR,
3613                                 "Not all VFs available. (%d, %d)\n",
3614                                 rc, resp->error_code);
3615                         HWRM_UNLOCK();
3616                         break;
3617                 }
3618
3619                 HWRM_UNLOCK();
3620
3621                 reserve_resources_from_vf(bp, &req, i);
3622                 bp->pf->active_vfs++;
3623                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3624         }
3625
3626         /*
3627          * Now configure the PF to use "the rest" of the resources
3628          * We're using STD_TX_RING_MODE here though which will limit the TX
3629          * rings.  This will allow QoS to function properly.  Not setting this
3630          * will cause PF rings to break bandwidth settings.
3631          */
3632         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3633         if (rc)
3634                 goto error_free;
3635
3636         rc = update_pf_resource_max(bp);
3637         if (rc)
3638                 goto error_free;
3639
3640         return rc;
3641
3642 error_free:
3643         bnxt_hwrm_func_buf_unrgtr(bp);
3644         return rc;
3645 }
3646
3647 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3648 {
3649         struct hwrm_func_cfg_input req = {0};
3650         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3651         int rc;
3652
3653         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3654
3655         req.fid = rte_cpu_to_le_16(0xffff);
3656         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3657         req.evb_mode = bp->pf->evb_mode;
3658
3659         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3660         HWRM_CHECK_RESULT();
3661         HWRM_UNLOCK();
3662
3663         return rc;
3664 }
3665
3666 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3667                                 uint8_t tunnel_type)
3668 {
3669         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3670         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3671         int rc = 0;
3672
3673         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3674         req.tunnel_type = tunnel_type;
3675         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3676         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3677         HWRM_CHECK_RESULT();
3678
3679         switch (tunnel_type) {
3680         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3681                 bp->vxlan_fw_dst_port_id =
3682                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3683                 bp->vxlan_port = port;
3684                 break;
3685         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3686                 bp->geneve_fw_dst_port_id =
3687                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3688                 bp->geneve_port = port;
3689                 break;
3690         default:
3691                 break;
3692         }
3693
3694         HWRM_UNLOCK();
3695
3696         return rc;
3697 }
3698
3699 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3700                                 uint8_t tunnel_type)
3701 {
3702         struct hwrm_tunnel_dst_port_free_input req = {0};
3703         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3704         int rc = 0;
3705
3706         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3707
3708         req.tunnel_type = tunnel_type;
3709         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3710         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3711
3712         HWRM_CHECK_RESULT();
3713         HWRM_UNLOCK();
3714
3715         return rc;
3716 }
3717
3718 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3719                                         uint32_t flags)
3720 {
3721         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3722         struct hwrm_func_cfg_input req = {0};
3723         int rc;
3724
3725         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3726
3727         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3728         req.flags = rte_cpu_to_le_32(flags);
3729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3730
3731         HWRM_CHECK_RESULT();
3732         HWRM_UNLOCK();
3733
3734         return rc;
3735 }
3736
3737 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3738 {
3739         uint32_t *flag = flagp;
3740
3741         vnic->flags = *flag;
3742 }
3743
3744 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3745 {
3746         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3747 }
3748
3749 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3750 {
3751         int rc = 0;
3752         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3753         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3754
3755         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3756
3757         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3758         req.req_buf_page_size = rte_cpu_to_le_16(
3759                          page_getenum(bp->pf->active_vfs * HWRM_MAX_REQ_LEN));
3760         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3761         req.req_buf_page_addr0 =
3762                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3763         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3764                 PMD_DRV_LOG(ERR,
3765                         "unable to map buffer address to physical memory\n");
3766                 return -ENOMEM;
3767         }
3768
3769         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3770
3771         HWRM_CHECK_RESULT();
3772         HWRM_UNLOCK();
3773
3774         return rc;
3775 }
3776
3777 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3778 {
3779         int rc = 0;
3780         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3781         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3782
3783         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3784                 return 0;
3785
3786         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3787
3788         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3789
3790         HWRM_CHECK_RESULT();
3791         HWRM_UNLOCK();
3792
3793         return rc;
3794 }
3795
3796 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3797 {
3798         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3799         struct hwrm_func_cfg_input req = {0};
3800         int rc;
3801
3802         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3803
3804         req.fid = rte_cpu_to_le_16(0xffff);
3805         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3806         req.enables = rte_cpu_to_le_32(
3807                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3808         req.async_event_cr = rte_cpu_to_le_16(
3809                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3810         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3811
3812         HWRM_CHECK_RESULT();
3813         HWRM_UNLOCK();
3814
3815         return rc;
3816 }
3817
3818 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3819 {
3820         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3821         struct hwrm_func_vf_cfg_input req = {0};
3822         int rc;
3823
3824         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3825
3826         req.enables = rte_cpu_to_le_32(
3827                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3828         req.async_event_cr = rte_cpu_to_le_16(
3829                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3830         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3831
3832         HWRM_CHECK_RESULT();
3833         HWRM_UNLOCK();
3834
3835         return rc;
3836 }
3837
3838 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3839 {
3840         struct hwrm_func_cfg_input req = {0};
3841         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3842         uint16_t dflt_vlan, fid;
3843         uint32_t func_cfg_flags;
3844         int rc = 0;
3845
3846         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3847
3848         if (is_vf) {
3849                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
3850                 fid = bp->pf->vf_info[vf].fid;
3851                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
3852         } else {
3853                 fid = rte_cpu_to_le_16(0xffff);
3854                 func_cfg_flags = bp->pf->func_cfg_flags;
3855                 dflt_vlan = bp->vlan;
3856         }
3857
3858         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3859         req.fid = rte_cpu_to_le_16(fid);
3860         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3861         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3862
3863         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3864
3865         HWRM_CHECK_RESULT();
3866         HWRM_UNLOCK();
3867
3868         return rc;
3869 }
3870
3871 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3872                         uint16_t max_bw, uint16_t enables)
3873 {
3874         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3875         struct hwrm_func_cfg_input req = {0};
3876         int rc;
3877
3878         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3879
3880         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3881         req.enables |= rte_cpu_to_le_32(enables);
3882         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3883         req.max_bw = rte_cpu_to_le_32(max_bw);
3884         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3885
3886         HWRM_CHECK_RESULT();
3887         HWRM_UNLOCK();
3888
3889         return rc;
3890 }
3891
3892 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3893 {
3894         struct hwrm_func_cfg_input req = {0};
3895         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3896         int rc = 0;
3897
3898         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3899
3900         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3901         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3902         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3903         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
3904
3905         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3906
3907         HWRM_CHECK_RESULT();
3908         HWRM_UNLOCK();
3909
3910         return rc;
3911 }
3912
3913 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3914 {
3915         int rc;
3916
3917         if (BNXT_PF(bp))
3918                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3919         else
3920                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3921
3922         return rc;
3923 }
3924
3925 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3926                               void *encaped, size_t ec_size)
3927 {
3928         int rc = 0;
3929         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3930         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3931
3932         if (ec_size > sizeof(req.encap_request))
3933                 return -1;
3934
3935         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3936
3937         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3938         memcpy(req.encap_request, encaped, ec_size);
3939
3940         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3941
3942         HWRM_CHECK_RESULT();
3943         HWRM_UNLOCK();
3944
3945         return rc;
3946 }
3947
3948 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3949                                        struct rte_ether_addr *mac)
3950 {
3951         struct hwrm_func_qcfg_input req = {0};
3952         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3953         int rc;
3954
3955         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3956
3957         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3958         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3959
3960         HWRM_CHECK_RESULT();
3961
3962         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3963
3964         HWRM_UNLOCK();
3965
3966         return rc;
3967 }
3968
3969 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3970                             void *encaped, size_t ec_size)
3971 {
3972         int rc = 0;
3973         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3974         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3975
3976         if (ec_size > sizeof(req.encap_request))
3977                 return -1;
3978
3979         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3980
3981         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3982         memcpy(req.encap_request, encaped, ec_size);
3983
3984         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3985
3986         HWRM_CHECK_RESULT();
3987         HWRM_UNLOCK();
3988
3989         return rc;
3990 }
3991
3992 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3993                          struct rte_eth_stats *stats, uint8_t rx)
3994 {
3995         int rc = 0;
3996         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3997         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3998
3999         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4000
4001         req.stat_ctx_id = rte_cpu_to_le_32(cid);
4002
4003         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4004
4005         HWRM_CHECK_RESULT();
4006
4007         if (rx) {
4008                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4009                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
4010                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
4011                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4012                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
4013                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
4014                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
4015                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
4016         } else {
4017                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4018                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
4019                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
4020                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4021                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
4022                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
4023         }
4024
4025         HWRM_UNLOCK();
4026
4027         return rc;
4028 }
4029
4030 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4031 {
4032         struct hwrm_port_qstats_input req = {0};
4033         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4034         struct bnxt_pf_info *pf = bp->pf;
4035         int rc;
4036
4037         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4038
4039         req.port_id = rte_cpu_to_le_16(pf->port_id);
4040         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4041         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4042         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4043
4044         HWRM_CHECK_RESULT();
4045         HWRM_UNLOCK();
4046
4047         return rc;
4048 }
4049
4050 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4051 {
4052         struct hwrm_port_clr_stats_input req = {0};
4053         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4054         struct bnxt_pf_info *pf = bp->pf;
4055         int rc;
4056
4057         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4058         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4059             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4060                 return 0;
4061
4062         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4063
4064         req.port_id = rte_cpu_to_le_16(pf->port_id);
4065         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4066
4067         HWRM_CHECK_RESULT();
4068         HWRM_UNLOCK();
4069
4070         return rc;
4071 }
4072
4073 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4074 {
4075         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4076         struct hwrm_port_led_qcaps_input req = {0};
4077         int rc;
4078
4079         if (BNXT_VF(bp))
4080                 return 0;
4081
4082         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4083         req.port_id = bp->pf->port_id;
4084         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4085
4086         HWRM_CHECK_RESULT();
4087
4088         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4089                 unsigned int i;
4090
4091                 bp->leds->num_leds = resp->num_leds;
4092                 memcpy(bp->leds, &resp->led0_id,
4093                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4094                 for (i = 0; i < bp->leds->num_leds; i++) {
4095                         struct bnxt_led_info *led = &bp->leds[i];
4096
4097                         uint16_t caps = led->led_state_caps;
4098
4099                         if (!led->led_group_id ||
4100                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4101                                 bp->leds->num_leds = 0;
4102                                 break;
4103                         }
4104                 }
4105         }
4106
4107         HWRM_UNLOCK();
4108
4109         return rc;
4110 }
4111
4112 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4113 {
4114         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4115         struct hwrm_port_led_cfg_input req = {0};
4116         struct bnxt_led_cfg *led_cfg;
4117         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4118         uint16_t duration = 0;
4119         int rc, i;
4120
4121         if (!bp->leds->num_leds || BNXT_VF(bp))
4122                 return -EOPNOTSUPP;
4123
4124         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4125
4126         if (led_on) {
4127                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4128                 duration = rte_cpu_to_le_16(500);
4129         }
4130         req.port_id = bp->pf->port_id;
4131         req.num_leds = bp->leds->num_leds;
4132         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4133         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4134                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4135                 led_cfg->led_id = bp->leds[i].led_id;
4136                 led_cfg->led_state = led_state;
4137                 led_cfg->led_blink_on = duration;
4138                 led_cfg->led_blink_off = duration;
4139                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4140         }
4141
4142         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4143
4144         HWRM_CHECK_RESULT();
4145         HWRM_UNLOCK();
4146
4147         return rc;
4148 }
4149
4150 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4151                                uint32_t *length)
4152 {
4153         int rc;
4154         struct hwrm_nvm_get_dir_info_input req = {0};
4155         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4156
4157         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4158
4159         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4160
4161         HWRM_CHECK_RESULT();
4162
4163         *entries = rte_le_to_cpu_32(resp->entries);
4164         *length = rte_le_to_cpu_32(resp->entry_length);
4165
4166         HWRM_UNLOCK();
4167         return rc;
4168 }
4169
4170 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4171 {
4172         int rc;
4173         uint32_t dir_entries;
4174         uint32_t entry_length;
4175         uint8_t *buf;
4176         size_t buflen;
4177         rte_iova_t dma_handle;
4178         struct hwrm_nvm_get_dir_entries_input req = {0};
4179         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4180
4181         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4182         if (rc != 0)
4183                 return rc;
4184
4185         *data++ = dir_entries;
4186         *data++ = entry_length;
4187         len -= 2;
4188         memset(data, 0xff, len);
4189
4190         buflen = dir_entries * entry_length;
4191         buf = rte_malloc("nvm_dir", buflen, 0);
4192         if (buf == NULL)
4193                 return -ENOMEM;
4194         dma_handle = rte_malloc_virt2iova(buf);
4195         if (dma_handle == RTE_BAD_IOVA) {
4196                 PMD_DRV_LOG(ERR,
4197                         "unable to map response address to physical memory\n");
4198                 return -ENOMEM;
4199         }
4200         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4201         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4202         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4203
4204         if (rc == 0)
4205                 memcpy(data, buf, len > buflen ? buflen : len);
4206
4207         rte_free(buf);
4208         HWRM_CHECK_RESULT();
4209         HWRM_UNLOCK();
4210
4211         return rc;
4212 }
4213
4214 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4215                              uint32_t offset, uint32_t length,
4216                              uint8_t *data)
4217 {
4218         int rc;
4219         uint8_t *buf;
4220         rte_iova_t dma_handle;
4221         struct hwrm_nvm_read_input req = {0};
4222         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4223
4224         buf = rte_malloc("nvm_item", length, 0);
4225         if (!buf)
4226                 return -ENOMEM;
4227
4228         dma_handle = rte_malloc_virt2iova(buf);
4229         if (dma_handle == RTE_BAD_IOVA) {
4230                 PMD_DRV_LOG(ERR,
4231                         "unable to map response address to physical memory\n");
4232                 return -ENOMEM;
4233         }
4234         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4235         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4236         req.dir_idx = rte_cpu_to_le_16(index);
4237         req.offset = rte_cpu_to_le_32(offset);
4238         req.len = rte_cpu_to_le_32(length);
4239         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4240         if (rc == 0)
4241                 memcpy(data, buf, length);
4242
4243         rte_free(buf);
4244         HWRM_CHECK_RESULT();
4245         HWRM_UNLOCK();
4246
4247         return rc;
4248 }
4249
4250 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4251 {
4252         int rc;
4253         struct hwrm_nvm_erase_dir_entry_input req = {0};
4254         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4255
4256         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4257         req.dir_idx = rte_cpu_to_le_16(index);
4258         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4259         HWRM_CHECK_RESULT();
4260         HWRM_UNLOCK();
4261
4262         return rc;
4263 }
4264
4265
4266 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4267                           uint16_t dir_ordinal, uint16_t dir_ext,
4268                           uint16_t dir_attr, const uint8_t *data,
4269                           size_t data_len)
4270 {
4271         int rc;
4272         struct hwrm_nvm_write_input req = {0};
4273         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4274         rte_iova_t dma_handle;
4275         uint8_t *buf;
4276
4277         buf = rte_malloc("nvm_write", data_len, 0);
4278         if (!buf)
4279                 return -ENOMEM;
4280
4281         dma_handle = rte_malloc_virt2iova(buf);
4282         if (dma_handle == RTE_BAD_IOVA) {
4283                 PMD_DRV_LOG(ERR,
4284                         "unable to map response address to physical memory\n");
4285                 return -ENOMEM;
4286         }
4287         memcpy(buf, data, data_len);
4288
4289         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4290
4291         req.dir_type = rte_cpu_to_le_16(dir_type);
4292         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4293         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4294         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4295         req.dir_data_length = rte_cpu_to_le_32(data_len);
4296         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4297
4298         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4299
4300         rte_free(buf);
4301         HWRM_CHECK_RESULT();
4302         HWRM_UNLOCK();
4303
4304         return rc;
4305 }
4306
4307 static void
4308 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4309 {
4310         uint32_t *count = cbdata;
4311
4312         *count = *count + 1;
4313 }
4314
4315 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4316                                      struct bnxt_vnic_info *vnic __rte_unused)
4317 {
4318         return 0;
4319 }
4320
4321 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4322 {
4323         uint32_t count = 0;
4324
4325         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4326             &count, bnxt_vnic_count_hwrm_stub);
4327
4328         return count;
4329 }
4330
4331 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4332                                         uint16_t *vnic_ids)
4333 {
4334         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4335         struct hwrm_func_vf_vnic_ids_query_output *resp =
4336                                                 bp->hwrm_cmd_resp_addr;
4337         int rc;
4338
4339         /* First query all VNIC ids */
4340         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4341
4342         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4343         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4344         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4345
4346         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4347                 HWRM_UNLOCK();
4348                 PMD_DRV_LOG(ERR,
4349                 "unable to map VNIC ID table address to physical memory\n");
4350                 return -ENOMEM;
4351         }
4352         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4353         HWRM_CHECK_RESULT();
4354         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4355
4356         HWRM_UNLOCK();
4357
4358         return rc;
4359 }
4360
4361 /*
4362  * This function queries the VNIC IDs  for a specified VF. It then calls
4363  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4364  * Then it calls the hwrm_cb function to program this new vnic configuration.
4365  */
4366 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4367         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4368         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4369 {
4370         struct bnxt_vnic_info vnic;
4371         int rc = 0;
4372         int i, num_vnic_ids;
4373         uint16_t *vnic_ids;
4374         size_t vnic_id_sz;
4375         size_t sz;
4376
4377         /* First query all VNIC ids */
4378         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4379         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4380                         RTE_CACHE_LINE_SIZE);
4381         if (vnic_ids == NULL)
4382                 return -ENOMEM;
4383
4384         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4385                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4386
4387         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4388
4389         if (num_vnic_ids < 0)
4390                 return num_vnic_ids;
4391
4392         /* Retrieve VNIC, update bd_stall then update */
4393
4394         for (i = 0; i < num_vnic_ids; i++) {
4395                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4396                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4397                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4398                 if (rc)
4399                         break;
4400                 if (vnic.mru <= 4)      /* Indicates unallocated */
4401                         continue;
4402
4403                 vnic_cb(&vnic, cbdata);
4404
4405                 rc = hwrm_cb(bp, &vnic);
4406                 if (rc)
4407                         break;
4408         }
4409
4410         rte_free(vnic_ids);
4411
4412         return rc;
4413 }
4414
4415 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4416                                               bool on)
4417 {
4418         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4419         struct hwrm_func_cfg_input req = {0};
4420         int rc;
4421
4422         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4423
4424         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4425         req.enables |= rte_cpu_to_le_32(
4426                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4427         req.vlan_antispoof_mode = on ?
4428                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4429                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4430         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4431
4432         HWRM_CHECK_RESULT();
4433         HWRM_UNLOCK();
4434
4435         return rc;
4436 }
4437
4438 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4439 {
4440         struct bnxt_vnic_info vnic;
4441         uint16_t *vnic_ids;
4442         size_t vnic_id_sz;
4443         int num_vnic_ids, i;
4444         size_t sz;
4445         int rc;
4446
4447         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4448         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4449                         RTE_CACHE_LINE_SIZE);
4450         if (vnic_ids == NULL)
4451                 return -ENOMEM;
4452
4453         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4454                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4455
4456         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4457         if (rc <= 0)
4458                 goto exit;
4459         num_vnic_ids = rc;
4460
4461         /*
4462          * Loop through to find the default VNIC ID.
4463          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4464          * by sending the hwrm_func_qcfg command to the firmware.
4465          */
4466         for (i = 0; i < num_vnic_ids; i++) {
4467                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4468                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4469                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4470                                         bp->pf->first_vf_id + vf);
4471                 if (rc)
4472                         goto exit;
4473                 if (vnic.func_default) {
4474                         rte_free(vnic_ids);
4475                         return vnic.fw_vnic_id;
4476                 }
4477         }
4478         /* Could not find a default VNIC. */
4479         PMD_DRV_LOG(ERR, "No default VNIC\n");
4480 exit:
4481         rte_free(vnic_ids);
4482         return rc;
4483 }
4484
4485 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4486                          uint16_t dst_id,
4487                          struct bnxt_filter_info *filter)
4488 {
4489         int rc = 0;
4490         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4491         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4492         uint32_t enables = 0;
4493
4494         if (filter->fw_em_filter_id != UINT64_MAX)
4495                 bnxt_hwrm_clear_em_filter(bp, filter);
4496
4497         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4498
4499         req.flags = rte_cpu_to_le_32(filter->flags);
4500
4501         enables = filter->enables |
4502               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4503         req.dst_id = rte_cpu_to_le_16(dst_id);
4504
4505         if (filter->ip_addr_type) {
4506                 req.ip_addr_type = filter->ip_addr_type;
4507                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4508         }
4509         if (enables &
4510             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4511                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4512         if (enables &
4513             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4514                 memcpy(req.src_macaddr, filter->src_macaddr,
4515                        RTE_ETHER_ADDR_LEN);
4516         if (enables &
4517             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4518                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4519                        RTE_ETHER_ADDR_LEN);
4520         if (enables &
4521             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4522                 req.ovlan_vid = filter->l2_ovlan;
4523         if (enables &
4524             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4525                 req.ivlan_vid = filter->l2_ivlan;
4526         if (enables &
4527             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4528                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4529         if (enables &
4530             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4531                 req.ip_protocol = filter->ip_protocol;
4532         if (enables &
4533             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4534                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4535         if (enables &
4536             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4537                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4538         if (enables &
4539             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4540                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4541         if (enables &
4542             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4543                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4544         if (enables &
4545             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4546                 req.mirror_vnic_id = filter->mirror_vnic_id;
4547
4548         req.enables = rte_cpu_to_le_32(enables);
4549
4550         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4551
4552         HWRM_CHECK_RESULT();
4553
4554         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4555         HWRM_UNLOCK();
4556
4557         return rc;
4558 }
4559
4560 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4561 {
4562         int rc = 0;
4563         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4564         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4565
4566         if (filter->fw_em_filter_id == UINT64_MAX)
4567                 return 0;
4568
4569         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4570
4571         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4572
4573         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4574
4575         HWRM_CHECK_RESULT();
4576         HWRM_UNLOCK();
4577
4578         filter->fw_em_filter_id = UINT64_MAX;
4579         filter->fw_l2_filter_id = UINT64_MAX;
4580
4581         return 0;
4582 }
4583
4584 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4585                          uint16_t dst_id,
4586                          struct bnxt_filter_info *filter)
4587 {
4588         int rc = 0;
4589         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4590         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4591                                                 bp->hwrm_cmd_resp_addr;
4592         uint32_t enables = 0;
4593
4594         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4595                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4596
4597         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4598
4599         req.flags = rte_cpu_to_le_32(filter->flags);
4600
4601         enables = filter->enables |
4602               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4603         req.dst_id = rte_cpu_to_le_16(dst_id);
4604
4605         if (filter->ip_addr_type) {
4606                 req.ip_addr_type = filter->ip_addr_type;
4607                 enables |=
4608                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4609         }
4610         if (enables &
4611             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4612                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4613         if (enables &
4614             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4615                 memcpy(req.src_macaddr, filter->src_macaddr,
4616                        RTE_ETHER_ADDR_LEN);
4617         if (enables &
4618             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4619                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4620         if (enables &
4621             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4622                 req.ip_protocol = filter->ip_protocol;
4623         if (enables &
4624             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4625                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4626         if (enables &
4627             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4628                 req.src_ipaddr_mask[0] =
4629                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4630         if (enables &
4631             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4632                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4633         if (enables &
4634             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4635                 req.dst_ipaddr_mask[0] =
4636                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4637         if (enables &
4638             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4639                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4640         if (enables &
4641             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4642                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4643         if (enables &
4644             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4645                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4646         if (enables &
4647             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4648                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4649         if (enables &
4650             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4651                 req.mirror_vnic_id = filter->mirror_vnic_id;
4652
4653         req.enables = rte_cpu_to_le_32(enables);
4654
4655         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4656
4657         HWRM_CHECK_RESULT();
4658
4659         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4660         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4661         HWRM_UNLOCK();
4662
4663         return rc;
4664 }
4665
4666 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4667                                 struct bnxt_filter_info *filter)
4668 {
4669         int rc = 0;
4670         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4671         struct hwrm_cfa_ntuple_filter_free_output *resp =
4672                                                 bp->hwrm_cmd_resp_addr;
4673
4674         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4675                 return 0;
4676
4677         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4678
4679         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4680
4681         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4682
4683         HWRM_CHECK_RESULT();
4684         HWRM_UNLOCK();
4685
4686         filter->fw_ntuple_filter_id = UINT64_MAX;
4687
4688         return 0;
4689 }
4690
4691 static int
4692 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4693 {
4694         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4695         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4696         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4697         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4698         uint16_t *ring_tbl = vnic->rss_table;
4699         int nr_ctxs = vnic->num_lb_ctxts;
4700         int max_rings = bp->rx_nr_rings;
4701         int i, j, k, cnt;
4702         int rc = 0;
4703
4704         for (i = 0, k = 0; i < nr_ctxs; i++) {
4705                 struct bnxt_rx_ring_info *rxr;
4706                 struct bnxt_cp_ring_info *cpr;
4707
4708                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4709
4710                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4711                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4712                 req.hash_mode_flags = vnic->hash_mode;
4713
4714                 req.ring_grp_tbl_addr =
4715                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4716                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4717                                      2 * sizeof(*ring_tbl));
4718                 req.hash_key_tbl_addr =
4719                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4720
4721                 req.ring_table_pair_index = i;
4722                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4723
4724                 for (j = 0; j < 64; j++) {
4725                         uint16_t ring_id;
4726
4727                         /* Find next active ring. */
4728                         for (cnt = 0; cnt < max_rings; cnt++) {
4729                                 if (rx_queue_state[k] !=
4730                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4731                                         break;
4732                                 if (++k == max_rings)
4733                                         k = 0;
4734                         }
4735
4736                         /* Return if no rings are active. */
4737                         if (cnt == max_rings) {
4738                                 HWRM_UNLOCK();
4739                                 return 0;
4740                         }
4741
4742                         /* Add rx/cp ring pair to RSS table. */
4743                         rxr = rxqs[k]->rx_ring;
4744                         cpr = rxqs[k]->cp_ring;
4745
4746                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4747                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4748                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4749                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4750
4751                         if (++k == max_rings)
4752                                 k = 0;
4753                 }
4754                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4755                                             BNXT_USE_CHIMP_MB);
4756
4757                 HWRM_CHECK_RESULT();
4758                 HWRM_UNLOCK();
4759         }
4760
4761         return rc;
4762 }
4763
4764 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4765 {
4766         unsigned int rss_idx, fw_idx, i;
4767
4768         if (!(vnic->rss_table && vnic->hash_type))
4769                 return 0;
4770
4771         if (BNXT_CHIP_THOR(bp))
4772                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4773
4774         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4775                 return 0;
4776
4777         if (vnic->rss_table && vnic->hash_type) {
4778                 /*
4779                  * Fill the RSS hash & redirection table with
4780                  * ring group ids for all VNICs
4781                  */
4782                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4783                         rss_idx++, fw_idx++) {
4784                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4785                                 fw_idx %= bp->rx_cp_nr_rings;
4786                                 if (vnic->fw_grp_ids[fw_idx] !=
4787                                     INVALID_HW_RING_ID)
4788                                         break;
4789                                 fw_idx++;
4790                         }
4791                         if (i == bp->rx_cp_nr_rings)
4792                                 return 0;
4793                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4794                 }
4795                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4796         }
4797
4798         return 0;
4799 }
4800
4801 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4802         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4803 {
4804         uint16_t flags;
4805
4806         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4807
4808         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4809         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4810
4811         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4812         req->num_cmpl_dma_aggr_during_int =
4813                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4814
4815         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4816
4817         /* min timer set to 1/2 of interrupt timer */
4818         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4819
4820         /* buf timer set to 1/4 of interrupt timer */
4821         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4822
4823         req->cmpl_aggr_dma_tmr_during_int =
4824                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4825
4826         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4827                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4828         req->flags = rte_cpu_to_le_16(flags);
4829 }
4830
4831 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4832                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4833 {
4834         struct hwrm_ring_aggint_qcaps_input req = {0};
4835         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4836         uint32_t enables;
4837         uint16_t flags;
4838         int rc;
4839
4840         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4841         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4842         HWRM_CHECK_RESULT();
4843
4844         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4845         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4846
4847         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4848                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4849         agg_req->flags = rte_cpu_to_le_16(flags);
4850         enables =
4851          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4852          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4853         agg_req->enables = rte_cpu_to_le_32(enables);
4854
4855         HWRM_UNLOCK();
4856         return rc;
4857 }
4858
4859 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4860                         struct bnxt_coal *coal, uint16_t ring_id)
4861 {
4862         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4863         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4864                                                 bp->hwrm_cmd_resp_addr;
4865         int rc;
4866
4867         /* Set ring coalesce parameters only for 100G NICs */
4868         if (BNXT_CHIP_THOR(bp)) {
4869                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4870                         return -1;
4871         } else if (bnxt_stratus_device(bp)) {
4872                 bnxt_hwrm_set_coal_params(coal, &req);
4873         } else {
4874                 return 0;
4875         }
4876
4877         HWRM_PREP(&req,
4878                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4879                   BNXT_USE_CHIMP_MB);
4880         req.ring_id = rte_cpu_to_le_16(ring_id);
4881         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4882         HWRM_CHECK_RESULT();
4883         HWRM_UNLOCK();
4884         return 0;
4885 }
4886
4887 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4888 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4889 {
4890         struct hwrm_func_backing_store_qcaps_input req = {0};
4891         struct hwrm_func_backing_store_qcaps_output *resp =
4892                 bp->hwrm_cmd_resp_addr;
4893         struct bnxt_ctx_pg_info *ctx_pg;
4894         struct bnxt_ctx_mem_info *ctx;
4895         int total_alloc_len;
4896         int rc, i, tqm_rings;
4897
4898         if (!BNXT_CHIP_THOR(bp) ||
4899             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4900             BNXT_VF(bp) ||
4901             bp->ctx)
4902                 return 0;
4903
4904         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4905         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4906         HWRM_CHECK_RESULT_SILENT();
4907
4908         total_alloc_len = sizeof(*ctx);
4909         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4910                           RTE_CACHE_LINE_SIZE);
4911         if (!ctx) {
4912                 rc = -ENOMEM;
4913                 goto ctx_err;
4914         }
4915
4916         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4917         ctx->qp_min_qp1_entries =
4918                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4919         ctx->qp_max_l2_entries =
4920                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4921         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4922         ctx->srq_max_l2_entries =
4923                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4924         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4925         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4926         ctx->cq_max_l2_entries =
4927                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4928         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4929         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4930         ctx->vnic_max_vnic_entries =
4931                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4932         ctx->vnic_max_ring_table_entries =
4933                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4934         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4935         ctx->stat_max_entries =
4936                 rte_le_to_cpu_32(resp->stat_max_entries);
4937         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4938         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4939         ctx->tqm_min_entries_per_ring =
4940                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4941         ctx->tqm_max_entries_per_ring =
4942                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4943         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4944         if (!ctx->tqm_entries_multiple)
4945                 ctx->tqm_entries_multiple = 1;
4946         ctx->mrav_max_entries =
4947                 rte_le_to_cpu_32(resp->mrav_max_entries);
4948         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4949         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4950         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4951         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
4952
4953         if (!ctx->tqm_fp_rings_count)
4954                 ctx->tqm_fp_rings_count = bp->max_q;
4955
4956         tqm_rings = ctx->tqm_fp_rings_count + 1;
4957
4958         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4959                             sizeof(*ctx_pg) * tqm_rings,
4960                             RTE_CACHE_LINE_SIZE);
4961         if (!ctx_pg) {
4962                 rc = -ENOMEM;
4963                 goto ctx_err;
4964         }
4965         for (i = 0; i < tqm_rings; i++, ctx_pg++)
4966                 ctx->tqm_mem[i] = ctx_pg;
4967
4968         bp->ctx = ctx;
4969 ctx_err:
4970         HWRM_UNLOCK();
4971         return rc;
4972 }
4973
4974 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4975 {
4976         struct hwrm_func_backing_store_cfg_input req = {0};
4977         struct hwrm_func_backing_store_cfg_output *resp =
4978                 bp->hwrm_cmd_resp_addr;
4979         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4980         struct bnxt_ctx_pg_info *ctx_pg;
4981         uint32_t *num_entries;
4982         uint64_t *pg_dir;
4983         uint8_t *pg_attr;
4984         uint32_t ena;
4985         int i, rc;
4986
4987         if (!ctx)
4988                 return 0;
4989
4990         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4991         req.enables = rte_cpu_to_le_32(enables);
4992
4993         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4994                 ctx_pg = &ctx->qp_mem;
4995                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4996                 req.qp_num_qp1_entries =
4997                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4998                 req.qp_num_l2_entries =
4999                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5000                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5001                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5002                                       &req.qpc_pg_size_qpc_lvl,
5003                                       &req.qpc_page_dir);
5004         }
5005
5006         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5007                 ctx_pg = &ctx->srq_mem;
5008                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5009                 req.srq_num_l2_entries =
5010                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5011                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5012                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5013                                       &req.srq_pg_size_srq_lvl,
5014                                       &req.srq_page_dir);
5015         }
5016
5017         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5018                 ctx_pg = &ctx->cq_mem;
5019                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5020                 req.cq_num_l2_entries =
5021                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5022                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5023                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5024                                       &req.cq_pg_size_cq_lvl,
5025                                       &req.cq_page_dir);
5026         }
5027
5028         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5029                 ctx_pg = &ctx->vnic_mem;
5030                 req.vnic_num_vnic_entries =
5031                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5032                 req.vnic_num_ring_table_entries =
5033                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5034                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5035                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5036                                       &req.vnic_pg_size_vnic_lvl,
5037                                       &req.vnic_page_dir);
5038         }
5039
5040         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5041                 ctx_pg = &ctx->stat_mem;
5042                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5043                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5044                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5045                                       &req.stat_pg_size_stat_lvl,
5046                                       &req.stat_page_dir);
5047         }
5048
5049         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5050         num_entries = &req.tqm_sp_num_entries;
5051         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5052         pg_dir = &req.tqm_sp_page_dir;
5053         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5054         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5055                 if (!(enables & ena))
5056                         continue;
5057
5058                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5059
5060                 ctx_pg = ctx->tqm_mem[i];
5061                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5062                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5063         }
5064
5065         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5066         HWRM_CHECK_RESULT();
5067         HWRM_UNLOCK();
5068
5069         return rc;
5070 }
5071
5072 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5073 {
5074         struct hwrm_port_qstats_ext_input req = {0};
5075         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5076         struct bnxt_pf_info *pf = bp->pf;
5077         int rc;
5078
5079         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5080               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5081                 return 0;
5082
5083         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5084
5085         req.port_id = rte_cpu_to_le_16(pf->port_id);
5086         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5087                 req.tx_stat_host_addr =
5088                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5089                 req.tx_stat_size =
5090                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5091         }
5092         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5093                 req.rx_stat_host_addr =
5094                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5095                 req.rx_stat_size =
5096                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5097         }
5098         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5099
5100         if (rc) {
5101                 bp->fw_rx_port_stats_ext_size = 0;
5102                 bp->fw_tx_port_stats_ext_size = 0;
5103         } else {
5104                 bp->fw_rx_port_stats_ext_size =
5105                         rte_le_to_cpu_16(resp->rx_stat_size);
5106                 bp->fw_tx_port_stats_ext_size =
5107                         rte_le_to_cpu_16(resp->tx_stat_size);
5108         }
5109
5110         HWRM_CHECK_RESULT();
5111         HWRM_UNLOCK();
5112
5113         return rc;
5114 }
5115
5116 int
5117 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5118 {
5119         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5120         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5121                 bp->hwrm_cmd_resp_addr;
5122         int rc = 0;
5123
5124         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5125         req.tunnel_type = type;
5126         req.dest_fid = bp->fw_fid;
5127         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5128         HWRM_CHECK_RESULT();
5129
5130         HWRM_UNLOCK();
5131
5132         return rc;
5133 }
5134
5135 int
5136 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5137 {
5138         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5139         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5140                 bp->hwrm_cmd_resp_addr;
5141         int rc = 0;
5142
5143         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5144         req.tunnel_type = type;
5145         req.dest_fid = bp->fw_fid;
5146         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5147         HWRM_CHECK_RESULT();
5148
5149         HWRM_UNLOCK();
5150
5151         return rc;
5152 }
5153
5154 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5155 {
5156         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5157         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5158                 bp->hwrm_cmd_resp_addr;
5159         int rc = 0;
5160
5161         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5162         req.src_fid = bp->fw_fid;
5163         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5164         HWRM_CHECK_RESULT();
5165
5166         if (type)
5167                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5168
5169         HWRM_UNLOCK();
5170
5171         return rc;
5172 }
5173
5174 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5175                                    uint16_t *dst_fid)
5176 {
5177         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5178         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5179                 bp->hwrm_cmd_resp_addr;
5180         int rc = 0;
5181
5182         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5183         req.src_fid = bp->fw_fid;
5184         req.tunnel_type = tun_type;
5185         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5186         HWRM_CHECK_RESULT();
5187
5188         if (dst_fid)
5189                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5190
5191         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5192
5193         HWRM_UNLOCK();
5194
5195         return rc;
5196 }
5197
5198 int bnxt_hwrm_set_mac(struct bnxt *bp)
5199 {
5200         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5201         struct hwrm_func_vf_cfg_input req = {0};
5202         int rc = 0;
5203
5204         if (!BNXT_VF(bp))
5205                 return 0;
5206
5207         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5208
5209         req.enables =
5210                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5211         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5212
5213         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5214
5215         HWRM_CHECK_RESULT();
5216
5217         HWRM_UNLOCK();
5218
5219         return rc;
5220 }
5221
5222 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5223 {
5224         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5225         struct hwrm_func_drv_if_change_input req = {0};
5226         uint32_t flags;
5227         int rc;
5228
5229         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5230                 return 0;
5231
5232         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5233          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5234          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5235          */
5236         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5237                 return 0;
5238
5239         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5240
5241         if (up)
5242                 req.flags =
5243                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5244
5245         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5246
5247         HWRM_CHECK_RESULT();
5248         flags = rte_le_to_cpu_32(resp->flags);
5249         HWRM_UNLOCK();
5250
5251         if (!up)
5252                 return 0;
5253
5254         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5255                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5256                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5257         }
5258
5259         return 0;
5260 }
5261
5262 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5263 {
5264         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5265         struct bnxt_error_recovery_info *info = bp->recovery_info;
5266         struct hwrm_error_recovery_qcfg_input req = {0};
5267         uint32_t flags = 0;
5268         unsigned int i;
5269         int rc;
5270
5271         /* Older FW does not have error recovery support */
5272         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5273                 return 0;
5274
5275         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5276
5277         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5278
5279         HWRM_CHECK_RESULT();
5280
5281         flags = rte_le_to_cpu_32(resp->flags);
5282         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5283                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5284         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5285                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5286
5287         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5288             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5289                 rc = -EINVAL;
5290                 goto err;
5291         }
5292
5293         /* FW returned values are in units of 100msec */
5294         info->driver_polling_freq =
5295                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5296         info->master_func_wait_period =
5297                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5298         info->normal_func_wait_period =
5299                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5300         info->master_func_wait_period_after_reset =
5301                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5302         info->max_bailout_time_after_reset =
5303                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5304         info->status_regs[BNXT_FW_STATUS_REG] =
5305                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5306         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5307                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5308         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5309                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5310         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5311                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5312         info->reg_array_cnt =
5313                 rte_le_to_cpu_32(resp->reg_array_cnt);
5314
5315         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5316                 rc = -EINVAL;
5317                 goto err;
5318         }
5319
5320         for (i = 0; i < info->reg_array_cnt; i++) {
5321                 info->reset_reg[i] =
5322                         rte_le_to_cpu_32(resp->reset_reg[i]);
5323                 info->reset_reg_val[i] =
5324                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5325                 info->delay_after_reset[i] =
5326                         resp->delay_after_reset[i];
5327         }
5328 err:
5329         HWRM_UNLOCK();
5330
5331         /* Map the FW status registers */
5332         if (!rc)
5333                 rc = bnxt_map_fw_health_status_regs(bp);
5334
5335         if (rc) {
5336                 rte_free(bp->recovery_info);
5337                 bp->recovery_info = NULL;
5338         }
5339         return rc;
5340 }
5341
5342 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5343 {
5344         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5345         struct hwrm_fw_reset_input req = {0};
5346         int rc;
5347
5348         if (!BNXT_PF(bp))
5349                 return -EOPNOTSUPP;
5350
5351         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5352
5353         req.embedded_proc_type =
5354                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5355         req.selfrst_status =
5356                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5357         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5358
5359         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5360                                     BNXT_USE_KONG(bp));
5361
5362         HWRM_CHECK_RESULT();
5363         HWRM_UNLOCK();
5364
5365         return rc;
5366 }
5367
5368 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5369 {
5370         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5371         struct hwrm_port_ts_query_input req = {0};
5372         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5373         uint32_t flags = 0;
5374         int rc;
5375
5376         if (!ptp)
5377                 return 0;
5378
5379         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5380
5381         switch (path) {
5382         case BNXT_PTP_FLAGS_PATH_TX:
5383                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5384                 break;
5385         case BNXT_PTP_FLAGS_PATH_RX:
5386                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5387                 break;
5388         case BNXT_PTP_FLAGS_CURRENT_TIME:
5389                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5390                 break;
5391         }
5392
5393         req.flags = rte_cpu_to_le_32(flags);
5394         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5395
5396         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5397
5398         HWRM_CHECK_RESULT();
5399
5400         if (timestamp) {
5401                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5402                 *timestamp |=
5403                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5404         }
5405         HWRM_UNLOCK();
5406
5407         return rc;
5408 }
5409
5410 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5411 {
5412         int rc = 0;
5413
5414         struct hwrm_cfa_counter_qcaps_input req = {0};
5415         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5416
5417         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5418                 PMD_DRV_LOG(DEBUG,
5419                             "Not a PF or trusted VF. Command not supported\n");
5420                 return 0;
5421         }
5422
5423         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5424         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5425         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5426
5427         HWRM_CHECK_RESULT();
5428         if (max_fc)
5429                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5430         HWRM_UNLOCK();
5431
5432         return 0;
5433 }
5434
5435 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5436 {
5437         int rc = 0;
5438         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5439         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5440
5441         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5442                 PMD_DRV_LOG(DEBUG,
5443                             "Not a PF or trusted VF. Command not supported\n");
5444                 return 0;
5445         }
5446
5447         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5448
5449         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5450         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5451         req.page_dir = rte_cpu_to_le_64(dma_addr);
5452
5453         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5454
5455         HWRM_CHECK_RESULT();
5456         if (ctx_id) {
5457                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5458                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5459         }
5460         HWRM_UNLOCK();
5461
5462         return 0;
5463 }
5464
5465 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5466 {
5467         int rc = 0;
5468         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5469         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5470
5471         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5472                 PMD_DRV_LOG(DEBUG,
5473                             "Not a PF or trusted VF. Command not supported\n");
5474                 return 0;
5475         }
5476
5477         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5478
5479         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5480
5481         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5482
5483         HWRM_CHECK_RESULT();
5484         HWRM_UNLOCK();
5485
5486         return rc;
5487 }
5488
5489 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5490                               uint16_t cntr, uint16_t ctx_id,
5491                               uint32_t num_entries, bool enable)
5492 {
5493         struct hwrm_cfa_counter_cfg_input req = {0};
5494         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5495         uint16_t flags = 0;
5496         int rc;
5497
5498         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5499                 PMD_DRV_LOG(DEBUG,
5500                             "Not a PF or trusted VF. Command not supported\n");
5501                 return 0;
5502         }
5503
5504         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5505
5506         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5507         req.counter_type = rte_cpu_to_le_16(cntr);
5508         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5509                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5510         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5511         if (dir == BNXT_DIR_RX)
5512                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5513         else if (dir == BNXT_DIR_TX)
5514                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5515         req.flags = rte_cpu_to_le_16(flags);
5516         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5517         req.num_entries = rte_cpu_to_le_32(num_entries);
5518
5519         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5520         HWRM_CHECK_RESULT();
5521         HWRM_UNLOCK();
5522
5523         return 0;
5524 }
5525
5526 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5527                                  enum bnxt_flow_dir dir,
5528                                  uint16_t cntr,
5529                                  uint16_t num_entries)
5530 {
5531         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5532         struct hwrm_cfa_counter_qstats_input req = {0};
5533         uint16_t flow_ctx_id = 0;
5534         uint16_t flags = 0;
5535         int rc = 0;
5536
5537         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5538                 PMD_DRV_LOG(DEBUG,
5539                             "Not a PF or trusted VF. Command not supported\n");
5540                 return 0;
5541         }
5542
5543         if (dir == BNXT_DIR_RX) {
5544                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5545                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5546         } else if (dir == BNXT_DIR_TX) {
5547                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5548                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5549         }
5550
5551         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5552         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5553         req.counter_type = rte_cpu_to_le_16(cntr);
5554         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5555         req.num_entries = rte_cpu_to_le_16(num_entries);
5556         req.flags = rte_cpu_to_le_16(flags);
5557         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5558
5559         HWRM_CHECK_RESULT();
5560         HWRM_UNLOCK();
5561
5562         return 0;
5563 }
5564
5565 int bnxt_hwrm_cfa_vfr_alloc(struct bnxt *bp, uint16_t vf_idx)
5566 {
5567         struct hwrm_cfa_vfr_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5568         struct hwrm_cfa_vfr_alloc_input req = {0};
5569         int rc;
5570
5571         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5572                 PMD_DRV_LOG(DEBUG,
5573                             "Not a PF or trusted VF. Command not supported\n");
5574                 return 0;
5575         }
5576
5577         HWRM_PREP(&req, HWRM_CFA_VFR_ALLOC, BNXT_USE_CHIMP_MB);
5578         req.vf_id = rte_cpu_to_le_16(vf_idx);
5579         snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5580                  bp->eth_dev->data->name, vf_idx);
5581
5582         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5583         HWRM_CHECK_RESULT();
5584
5585         HWRM_UNLOCK();
5586         PMD_DRV_LOG(DEBUG, "VFR %d allocated\n", vf_idx);
5587         return rc;
5588 }
5589
5590 int bnxt_hwrm_cfa_vfr_free(struct bnxt *bp, uint16_t vf_idx)
5591 {
5592         struct hwrm_cfa_vfr_free_output *resp = bp->hwrm_cmd_resp_addr;
5593         struct hwrm_cfa_vfr_free_input req = {0};
5594         int rc;
5595
5596         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5597                 PMD_DRV_LOG(DEBUG,
5598                             "Not a PF or trusted VF. Command not supported\n");
5599                 return 0;
5600         }
5601
5602         HWRM_PREP(&req, HWRM_CFA_VFR_FREE, BNXT_USE_CHIMP_MB);
5603         req.vf_id = rte_cpu_to_le_16(vf_idx);
5604         snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5605                  bp->eth_dev->data->name, vf_idx);
5606
5607         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5608         HWRM_CHECK_RESULT();
5609         HWRM_UNLOCK();
5610         PMD_DRV_LOG(DEBUG, "VFR %d freed\n", vf_idx);
5611         return rc;
5612 }
5613
5614 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5615                                 uint16_t *first_vf_id)
5616 {
5617         int rc = 0;
5618         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5619         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5620
5621         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5622
5623         req.fid = rte_cpu_to_le_16(fid);
5624
5625         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5626
5627         HWRM_CHECK_RESULT();
5628
5629         if (first_vf_id)
5630                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5631
5632         HWRM_UNLOCK();
5633
5634         return rc;
5635 }
5636
5637 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
5638 {
5639         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5640         struct hwrm_cfa_pair_alloc_input req = {0};
5641         int rc;
5642
5643         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5644                 PMD_DRV_LOG(DEBUG,
5645                             "Not a PF or trusted VF. Command not supported\n");
5646                 return 0;
5647         }
5648
5649         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
5650         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5651         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5652                  bp->eth_dev->data->name, rep_bp->vf_id);
5653
5654         req.pf_b_id = rte_cpu_to_le_32(rep_bp->rep_based_pf);
5655         req.vf_b_id = rte_cpu_to_le_16(rep_bp->vf_id);
5656         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
5657         req.host_b_id = 1; /* TBD - Confirm if this is OK */
5658
5659         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
5660                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
5661         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
5662                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
5663         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
5664                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
5665         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
5666                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
5667
5668         req.q_ab = rep_bp->rep_q_r2f;
5669         req.q_ba = rep_bp->rep_q_f2r;
5670         req.fc_ab = rep_bp->rep_fc_r2f;
5671         req.fc_ba = rep_bp->rep_fc_f2r;
5672
5673         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5674         HWRM_CHECK_RESULT();
5675
5676         HWRM_UNLOCK();
5677         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
5678                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
5679         return rc;
5680 }
5681
5682 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
5683 {
5684         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
5685         struct hwrm_cfa_pair_free_input req = {0};
5686         int rc;
5687
5688         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5689                 PMD_DRV_LOG(DEBUG,
5690                             "Not a PF or trusted VF. Command not supported\n");
5691                 return 0;
5692         }
5693
5694         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
5695         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5696                  bp->eth_dev->data->name, rep_bp->vf_id);
5697         req.pf_b_id = rte_cpu_to_le_32(rep_bp->rep_based_pf);
5698         req.vf_id = rte_cpu_to_le_16(rep_bp->vf_id);
5699         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5700
5701         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5702         HWRM_CHECK_RESULT();
5703         HWRM_UNLOCK();
5704         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
5705                     rep_bp->vf_id);
5706         return rc;
5707 }