drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         /* For VER_GET command, set timeout as 50ms */
 104         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 105                 timeout = HWRM_CMD_TIMEOUT;
 106         else
 107                 timeout = bp->hwrm_cmd_timeout;
 108
 109         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 110             msg_len > bp->max_req_len) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 127         }
 128
 129         /* Write request msg to hwrm channel */
 130         for (i = 0; i < msg_len; i += 4) {
 131                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 132                 rte_write32(*data, bar);
 133                 data++;
 134         }
 135
 136         /* Zero the rest of the request space */
 137         for (; i < max_req_len; i += 4) {
 138                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 139                 rte_write32(0, bar);
 140         }
 141
 142         /* Ring channel doorbell */
 143         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 144         rte_write32(1, bar);
 145         /*
 146          * Make sure the channel doorbell ring command complete before
 147          * reading the response to avoid getting stale or invalid
 148          * responses.
 149          */
 150         rte_io_mb();
 151
 152         /* Poll for the valid bit */
 153         for (i = 0; i < timeout; i++) {
 154                 /* Sanity check on the resp->resp_len */
 155                 rte_cio_rmb();
 156                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 157                         /* Last byte of resp contains the valid key */
 158                         valid = (uint8_t *)resp + resp->resp_len - 1;
 159                         if (*valid == HWRM_RESP_VALID_KEY)
 160                                 break;
 161                 }
 162                 rte_delay_us(1);
 163         }
 164
 165         if (i >= timeout) {
 166                 /* Suppress VER_GET timeout messages during reset recovery */
 167                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 168                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 169                         return -ETIMEDOUT;
 170
 171                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 172                             req->req_type);
 173                 return -ETIMEDOUT;
 174         }
 175         return 0;
 176 }
 177
 178 /*
 179  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 180  * spinlock, and does initial processing.
 181  *
 182  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 183  * releases the spinlock only if it returns. If the regular int return codes
 184  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 185  * directly, rather it should be copied and modified to suit the function.
 186  *
 187  * HWRM_UNLOCK() must be called after all response processing is completed.
 188  */
 189 #define HWRM_PREP(req, type, kong) do { \
 190         rte_spinlock_lock(&bp->hwrm_lock); \
 191         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 192         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 193         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 194         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 195                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 196         req.target_id = rte_cpu_to_le_16(0xffff); \
 197         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 198 } while (0)
 199
 200 #define HWRM_CHECK_RESULT_SILENT() do {\
 201         if (rc) { \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 return rc; \
 204         } \
 205         if (resp->error_code) { \
 206                 rc = rte_le_to_cpu_16(resp->error_code); \
 207                 rte_spinlock_unlock(&bp->hwrm_lock); \
 208                 return rc; \
 209         } \
 210 } while (0)
 211
 212 #define HWRM_CHECK_RESULT() do {\
 213         if (rc) { \
 214                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 215                 rte_spinlock_unlock(&bp->hwrm_lock); \
 216                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 217                         rc = -EACCES; \
 218                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 219                         rc = -ENOSPC; \
 220                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 221                         rc = -EINVAL; \
 222                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 223                         rc = -ENOTSUP; \
 224                 else if (rc > 0) \
 225                         rc = -EIO; \
 226                 return rc; \
 227         } \
 228         if (resp->error_code) { \
 229                 rc = rte_le_to_cpu_16(resp->error_code); \
 230                 if (resp->resp_len >= 16) { \
 231                         struct hwrm_err_output *tmp_hwrm_err_op = \
 232                                                 (void *)resp; \
 233                         PMD_DRV_LOG(ERR, \
 234                                 "error %d:%d:%08x:%04x\n", \
 235                                 rc, tmp_hwrm_err_op->cmd_err, \
 236                                 rte_le_to_cpu_32(\
 237                                         tmp_hwrm_err_op->opaque_0), \
 238                                 rte_le_to_cpu_16(\
 239                                         tmp_hwrm_err_op->opaque_1)); \
 240                 } else { \
 241                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 242                 } \
 243                 rte_spinlock_unlock(&bp->hwrm_lock); \
 244                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 245                         rc = -EACCES; \
 246                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 247                         rc = -ENOSPC; \
 248                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 249                         rc = -EINVAL; \
 250                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 251                         rc = -ENOTSUP; \
 252                 else if (rc > 0) \
 253                         rc = -EIO; \
 254                 return rc; \
 255         } \
 256 } while (0)
 257
 258 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 259
 260 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 261 {
 262         int rc = 0;
 263         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 264         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268         req.mask = 0;
 269
 270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 271
 272         HWRM_CHECK_RESULT();
 273         HWRM_UNLOCK();
 274
 275         return rc;
 276 }
 277
 278 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 279                                  struct bnxt_vnic_info *vnic,
 280                                  uint16_t vlan_count,
 281                                  struct bnxt_vlan_table_entry *vlan_table)
 282 {
 283         int rc = 0;
 284         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 285         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 286         uint32_t mask = 0;
 287
 288         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 289                 return rc;
 290
 291         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 292         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 293
 294         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 295                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 296         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 297                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 298
 299         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 300                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 301
 302         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 303                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 304         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 305                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 306                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 307                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 308         }
 309         if (vlan_table) {
 310                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 311                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 312                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 313                          rte_mem_virt2iova(vlan_table));
 314                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 315         }
 316         req.mask = rte_cpu_to_le_32(mask);
 317
 318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 319
 320         HWRM_CHECK_RESULT();
 321         HWRM_UNLOCK();
 322
 323         return rc;
 324 }
 325
 326 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 327                         uint16_t vlan_count,
 328                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 329 {
 330         int rc = 0;
 331         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 332         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 333                                                 bp->hwrm_cmd_resp_addr;
 334
 335         /*
 336          * Older HWRM versions did not support this command, and the set_rx_mask
 337          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 338          * removed from set_rx_mask call, and this command was added.
 339          *
 340          * This command is also present from 1.7.8.11 and higher,
 341          * as well as 1.7.8.0
 342          */
 343         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 344                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 345                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 346                                         (11)))
 347                                 return 0;
 348                 }
 349         }
 350         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 351         req.fid = rte_cpu_to_le_16(fid);
 352
 353         req.vlan_tag_mask_tbl_addr =
 354                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 355         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         return rc;
 363 }
 364
 365 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 366                            struct bnxt_filter_info *filter)
 367 {
 368         int rc = 0;
 369         struct bnxt_filter_info *l2_filter = filter;
 370         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 371         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 372
 373         if (filter->fw_l2_filter_id == UINT64_MAX)
 374                 return 0;
 375
 376         if (filter->matching_l2_fltr_ptr)
 377                 l2_filter = filter->matching_l2_fltr_ptr;
 378
 379         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 380                     filter, l2_filter, l2_filter->l2_ref_cnt);
 381
 382         if (l2_filter->l2_ref_cnt > 0)
 383                 l2_filter->l2_ref_cnt--;
 384
 385         if (l2_filter->l2_ref_cnt > 0)
 386                 return 0;
 387
 388         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 389
 390         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 391
 392         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 393
 394         HWRM_CHECK_RESULT();
 395         HWRM_UNLOCK();
 396
 397         filter->fw_l2_filter_id = UINT64_MAX;
 398
 399         return 0;
 400 }
 401
 402 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 403                          uint16_t dst_id,
 404                          struct bnxt_filter_info *filter)
 405 {
 406         int rc = 0;
 407         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 408         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 409         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 410         const struct rte_eth_vmdq_rx_conf *conf =
 411                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 412         uint32_t enables = 0;
 413         uint16_t j = dst_id - 1;
 414
 415         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 416         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 417             conf->pool_map[j].pools & (1UL << j)) {
 418                 PMD_DRV_LOG(DEBUG,
 419                         "Add vlan %u to vmdq pool %u\n",
 420                         conf->pool_map[j].vlan_id, j);
 421
 422                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 423                 filter->enables |=
 424                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 425                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 426         }
 427
 428         if (filter->fw_l2_filter_id != UINT64_MAX)
 429                 bnxt_hwrm_clear_l2_filter(bp, filter);
 430
 431         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 432
 433         req.flags = rte_cpu_to_le_32(filter->flags);
 434
 435         enables = filter->enables |
 436               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 437         req.dst_id = rte_cpu_to_le_16(dst_id);
 438
 439         if (enables &
 440             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 441                 memcpy(req.l2_addr, filter->l2_addr,
 442                        RTE_ETHER_ADDR_LEN);
 443         if (enables &
 444             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 445                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 446                        RTE_ETHER_ADDR_LEN);
 447         if (enables &
 448             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 449                 req.l2_ovlan = filter->l2_ovlan;
 450         if (enables &
 451             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 452                 req.l2_ivlan = filter->l2_ivlan;
 453         if (enables &
 454             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 455                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 456         if (enables &
 457             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 458                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 459         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 460                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 461         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 462                 req.src_type = filter->src_type;
 463         if (filter->pri_hint) {
 464                 req.pri_hint = filter->pri_hint;
 465                 req.l2_filter_id_hint =
 466                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 467         }
 468
 469         req.enables = rte_cpu_to_le_32(enables);
 470
 471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 472
 473         HWRM_CHECK_RESULT();
 474
 475         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 482 {
 483         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 484         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 485         uint32_t flags = 0;
 486         int rc;
 487
 488         if (!ptp)
 489                 return 0;
 490
 491         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 492
 493         if (ptp->rx_filter)
 494                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 495         else
 496                 flags |=
 497                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 498         if (ptp->tx_tstamp_en)
 499                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 500         else
 501                 flags |=
 502                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 503         req.flags = rte_cpu_to_le_32(flags);
 504         req.enables = rte_cpu_to_le_32
 505                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 506         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 507
 508         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 509         HWRM_UNLOCK();
 510
 511         return rc;
 512 }
 513
 514 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 515 {
 516         int rc = 0;
 517         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 518         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 519         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 520
 521         if (ptp)
 522                 return 0;
 523
 524         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 525
 526         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 527
 528         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 529
 530         HWRM_CHECK_RESULT();
 531
 532         if (!BNXT_CHIP_THOR(bp) &&
 533             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 534                 return 0;
 535
 536         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 537                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 538
 539         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 540         if (!ptp)
 541                 return -ENOMEM;
 542
 543         if (!BNXT_CHIP_THOR(bp)) {
 544                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 545                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 546                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 547                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 548                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 549                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 550                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 551                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 552                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 553                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 554                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 555                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 556                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 557                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 558                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 559                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 560                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 561                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 562         }
 563
 564         ptp->bp = bp;
 565         bp->ptp_cfg = ptp;
 566
 567         return 0;
 568 }
 569
 570 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 571 {
 572         int rc = 0;
 573         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 574         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 575         uint16_t new_max_vfs;
 576         uint32_t flags;
 577         int i;
 578
 579         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 580
 581         req.fid = rte_cpu_to_le_16(0xffff);
 582
 583         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 584
 585         HWRM_CHECK_RESULT();
 586
 587         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 588         flags = rte_le_to_cpu_32(resp->flags);
 589         if (BNXT_PF(bp)) {
 590                 bp->pf.port_id = resp->port_id;
 591                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 592                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 593                 new_max_vfs = bp->pdev->max_vfs;
 594                 if (new_max_vfs != bp->pf.max_vfs) {
 595                         if (bp->pf.vf_info)
 596                                 rte_free(bp->pf.vf_info);
 597                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 598                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 599                         bp->pf.max_vfs = new_max_vfs;
 600                         for (i = 0; i < new_max_vfs; i++) {
 601                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 602                                 bp->pf.vf_info[i].vlan_table =
 603                                         rte_zmalloc("VF VLAN table",
 604                                                     getpagesize(),
 605                                                     getpagesize());
 606                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 607                                         PMD_DRV_LOG(ERR,
 608                                         "Fail to alloc VLAN table for VF %d\n",
 609                                         i);
 610                                 else
 611                                         rte_mem_lock_page(
 612                                                 bp->pf.vf_info[i].vlan_table);
 613                                 bp->pf.vf_info[i].vlan_as_table =
 614                                         rte_zmalloc("VF VLAN AS table",
 615                                                     getpagesize(),
 616                                                     getpagesize());
 617                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 618                                         PMD_DRV_LOG(ERR,
 619                                         "Alloc VLAN AS table for VF %d fail\n",
 620                                         i);
 621                                 else
 622                                         rte_mem_lock_page(
 623                                                bp->pf.vf_info[i].vlan_as_table);
 624                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 625                         }
 626                 }
 627         }
 628
 629         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 630         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 631         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 632         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 633         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 634         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 635         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 636         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 637         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 638         if (!BNXT_CHIP_THOR(bp))
 639                 bp->max_l2_ctx += bp->max_rx_em_flows;
 640         /* TODO: For now, do not support VMDq/RFS on VFs. */
 641         if (BNXT_PF(bp)) {
 642                 if (bp->pf.max_vfs)
 643                         bp->max_vnics = 1;
 644                 else
 645                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 646         } else {
 647                 bp->max_vnics = 1;
 648         }
 649         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 650         if (BNXT_PF(bp)) {
 651                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 652                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 653                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 654                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 655                         HWRM_UNLOCK();
 656                         bnxt_hwrm_ptp_qcfg(bp);
 657                 }
 658         }
 659
 660         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 661                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 662
 663         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 664                 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 665                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 666         } else {
 667                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 668         }
 669
 670         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 671                 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 672         else
 673                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 674
 675         HWRM_UNLOCK();
 676
 677         return rc;
 678 }
 679
 680 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 681 {
 682         int rc;
 683
 684         rc = __bnxt_hwrm_func_qcaps(bp);
 685         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 686                 rc = bnxt_alloc_ctx_mem(bp);
 687                 if (rc)
 688                         return rc;
 689
 690                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 691                 if (!rc)
 692                         bp->flags |= BNXT_FLAG_NEW_RM;
 693         }
 694
 695         return rc;
 696 }
 697
 698 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 699 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 700 {
 701         int rc = 0;
 702         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 703         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 704
 705         HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 706
 707         req.target_id = rte_cpu_to_le_16(0xffff);
 708
 709         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 710
 711         HWRM_CHECK_RESULT();
 712
 713         if (rte_le_to_cpu_32(resp->flags) &
 714             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 715                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 716                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 717         }
 718
 719         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 720
 721         HWRM_UNLOCK();
 722
 723         return rc;
 724 }
 725
 726 int bnxt_hwrm_func_reset(struct bnxt *bp)
 727 {
 728         int rc = 0;
 729         struct hwrm_func_reset_input req = {.req_type = 0 };
 730         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 731
 732         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 733
 734         req.enables = rte_cpu_to_le_32(0);
 735
 736         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 737
 738         HWRM_CHECK_RESULT();
 739         HWRM_UNLOCK();
 740
 741         return rc;
 742 }
 743
 744 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 745 {
 746         int rc;
 747         uint32_t flags = 0;
 748         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 749         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 750
 751         if (bp->flags & BNXT_FLAG_REGISTERED)
 752                 return 0;
 753
 754         flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 755         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 756                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 757
 758         /* PFs and trusted VFs should indicate the support of the
 759          * Master capability on non Stingray platform
 760          */
 761         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 762                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 763
 764         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 765         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 766                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 767         req.ver_maj = RTE_VER_YEAR;
 768         req.ver_min = RTE_VER_MONTH;
 769         req.ver_upd = RTE_VER_MINOR;
 770
 771         if (BNXT_PF(bp)) {
 772                 req.enables |= rte_cpu_to_le_32(
 773                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 774                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 775                        RTE_MIN(sizeof(req.vf_req_fwd),
 776                                sizeof(bp->pf.vf_req_fwd)));
 777
 778                 /*
 779                  * PF can sniff HWRM API issued by VF. This can be set up by
 780                  * linux driver and inherited by the DPDK PF driver. Clear
 781                  * this HWRM sniffer list in FW because DPDK PF driver does
 782                  * not support this.
 783                  */
 784                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 785         }
 786
 787         req.flags = rte_cpu_to_le_32(flags);
 788
 789         req.async_event_fwd[0] |=
 790                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 791                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 792                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 793                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 794                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 795         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 796                 req.async_event_fwd[0] |=
 797                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 798         req.async_event_fwd[1] |=
 799                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 800                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 801
 802         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 803
 804         HWRM_CHECK_RESULT();
 805
 806         flags = rte_le_to_cpu_32(resp->flags);
 807         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 808                 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
 809
 810         HWRM_UNLOCK();
 811
 812         bp->flags |= BNXT_FLAG_REGISTERED;
 813
 814         return rc;
 815 }
 816
 817 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 818 {
 819         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 820                 return 0;
 821
 822         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 823 }
 824
 825 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 826 {
 827         int rc;
 828         uint32_t flags = 0;
 829         uint32_t enables;
 830         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 831         struct hwrm_func_vf_cfg_input req = {0};
 832
 833         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 834
 835         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 836                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 837                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 838                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 839                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 840
 841         if (BNXT_HAS_RING_GRPS(bp)) {
 842                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 843                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 844         }
 845
 846         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 847         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 848                                             AGG_RING_MULTIPLIER);
 849         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 850         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 851                                               bp->tx_nr_rings +
 852                                               BNXT_NUM_ASYNC_CPR(bp));
 853         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 854         if (bp->vf_resv_strategy ==
 855             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 856                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 857                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 858                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 859                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 860                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 861                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 862         } else if (bp->vf_resv_strategy ==
 863                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 864                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 865                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 866         }
 867
 868         if (test)
 869                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 870                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 871                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 872                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 873                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 874                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 875
 876         if (test && BNXT_HAS_RING_GRPS(bp))
 877                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 878
 879         req.flags = rte_cpu_to_le_32(flags);
 880         req.enables |= rte_cpu_to_le_32(enables);
 881
 882         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 883
 884         if (test)
 885                 HWRM_CHECK_RESULT_SILENT();
 886         else
 887                 HWRM_CHECK_RESULT();
 888
 889         HWRM_UNLOCK();
 890         return rc;
 891 }
 892
 893 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 894 {
 895         int rc;
 896         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 897         struct hwrm_func_resource_qcaps_input req = {0};
 898
 899         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 900         req.fid = rte_cpu_to_le_16(0xffff);
 901
 902         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 903
 904         HWRM_CHECK_RESULT();
 905
 906         if (BNXT_VF(bp)) {
 907                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 908                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 909                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 910                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 911                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 912                 /* func_resource_qcaps does not return max_rx_em_flows.
 913                  * So use the value provided by func_qcaps.
 914                  */
 915                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 916                 if (!BNXT_CHIP_THOR(bp))
 917                         bp->max_l2_ctx += bp->max_rx_em_flows;
 918                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 919                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 920         }
 921         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 922         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 923         if (bp->vf_resv_strategy >
 924             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 925                 bp->vf_resv_strategy =
 926                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 927
 928         HWRM_UNLOCK();
 929         return rc;
 930 }
 931
 932 int bnxt_hwrm_ver_get(struct bnxt *bp)
 933 {
 934         int rc = 0;
 935         struct hwrm_ver_get_input req = {.req_type = 0 };
 936         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 937         uint32_t fw_version;
 938         uint16_t max_resp_len;
 939         char type[RTE_MEMZONE_NAMESIZE];
 940         uint32_t dev_caps_cfg;
 941
 942         bp->max_req_len = HWRM_MAX_REQ_LEN;
 943         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 944
 945         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 946         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 947         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 948
 949         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 950
 951         if (bp->flags & BNXT_FLAG_FW_RESET)
 952                 HWRM_CHECK_RESULT_SILENT();
 953         else
 954                 HWRM_CHECK_RESULT();
 955
 956         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 957                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 958                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 959                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 960         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 961                      (resp->hwrm_fw_min_8b << 16) |
 962                      (resp->hwrm_fw_bld_8b << 8) |
 963                      resp->hwrm_fw_rsvd_8b;
 964         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 965                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 966
 967         fw_version = resp->hwrm_intf_maj_8b << 16;
 968         fw_version |= resp->hwrm_intf_min_8b << 8;
 969         fw_version |= resp->hwrm_intf_upd_8b;
 970         bp->hwrm_spec_code = fw_version;
 971
 972         /* def_req_timeout value is in milliseconds */
 973         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
 974         /* convert timeout to usec */
 975         bp->hwrm_cmd_timeout *= 1000;
 976         if (!bp->hwrm_cmd_timeout)
 977                 bp->hwrm_cmd_timeout = HWRM_CMD_TIMEOUT;
 978
 979         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 980                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 981                 rc = -EINVAL;
 982                 goto error;
 983         }
 984
 985         if (bp->max_req_len > resp->max_req_win_len) {
 986                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 987                 rc = -EINVAL;
 988         }
 989         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 990         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 991         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 992                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 993
 994         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 995         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 996
 997         if (bp->max_resp_len != max_resp_len) {
 998                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 999                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1000                         bp->pdev->addr.devid, bp->pdev->addr.function);
1001
1002                 rte_free(bp->hwrm_cmd_resp_addr);
1003
1004                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1005                 if (bp->hwrm_cmd_resp_addr == NULL) {
1006                         rc = -ENOMEM;
1007                         goto error;
1008                 }
1009                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1010                 bp->hwrm_cmd_resp_dma_addr =
1011                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1012                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1013                         PMD_DRV_LOG(ERR,
1014                         "Unable to map response buffer to physical memory.\n");
1015                         rc = -ENOMEM;
1016                         goto error;
1017                 }
1018                 bp->max_resp_len = max_resp_len;
1019         }
1020
1021         if ((dev_caps_cfg &
1022                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1023             (dev_caps_cfg &
1024              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1025                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1026                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1027         }
1028
1029         if (((dev_caps_cfg &
1030               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1031              (dev_caps_cfg &
1032               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1033             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1034                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1035                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1036                         bp->pdev->addr.devid, bp->pdev->addr.function);
1037
1038                 rte_free(bp->hwrm_short_cmd_req_addr);
1039
1040                 bp->hwrm_short_cmd_req_addr =
1041                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1042                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1043                         rc = -ENOMEM;
1044                         goto error;
1045                 }
1046                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1047                 bp->hwrm_short_cmd_req_dma_addr =
1048                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1049                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1050                         rte_free(bp->hwrm_short_cmd_req_addr);
1051                         PMD_DRV_LOG(ERR,
1052                                 "Unable to map buffer to physical memory.\n");
1053                         rc = -ENOMEM;
1054                         goto error;
1055                 }
1056         }
1057         if (dev_caps_cfg &
1058             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1059                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1060                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1061         }
1062         if (dev_caps_cfg &
1063             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1064                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1065         if (dev_caps_cfg &
1066             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1067                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1068                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1069         }
1070
1071 error:
1072         HWRM_UNLOCK();
1073         return rc;
1074 }
1075
1076 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1077 {
1078         int rc;
1079         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1080         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1081
1082         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1083                 return 0;
1084
1085         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1086         req.flags = flags;
1087
1088         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1089
1090         HWRM_CHECK_RESULT();
1091         HWRM_UNLOCK();
1092
1093         return rc;
1094 }
1095
1096 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1097 {
1098         int rc = 0;
1099         struct hwrm_port_phy_cfg_input req = {0};
1100         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1101         uint32_t enables = 0;
1102
1103         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1104
1105         if (conf->link_up) {
1106                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1107                 if (bp->link_info.auto_mode && conf->link_speed) {
1108                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1109                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1110                 }
1111
1112                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1113                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1114                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1115                 /*
1116                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1117                  * any auto mode, even "none".
1118                  */
1119                 if (!conf->link_speed) {
1120                         /* No speeds specified. Enable AutoNeg - all speeds */
1121                         req.auto_mode =
1122                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1123                 }
1124                 /* AutoNeg - Advertise speeds specified. */
1125                 if (conf->auto_link_speed_mask &&
1126                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1127                         req.auto_mode =
1128                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1129                         req.auto_link_speed_mask =
1130                                 conf->auto_link_speed_mask;
1131                         enables |=
1132                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1133                 }
1134
1135                 req.auto_duplex = conf->duplex;
1136                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1137                 req.auto_pause = conf->auto_pause;
1138                 req.force_pause = conf->force_pause;
1139                 /* Set force_pause if there is no auto or if there is a force */
1140                 if (req.auto_pause && !req.force_pause)
1141                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1142                 else
1143                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1144
1145                 req.enables = rte_cpu_to_le_32(enables);
1146         } else {
1147                 req.flags =
1148                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1149                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1150         }
1151
1152         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1153
1154         HWRM_CHECK_RESULT();
1155         HWRM_UNLOCK();
1156
1157         return rc;
1158 }
1159
1160 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1161                                    struct bnxt_link_info *link_info)
1162 {
1163         int rc = 0;
1164         struct hwrm_port_phy_qcfg_input req = {0};
1165         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1166
1167         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1168
1169         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1170
1171         HWRM_CHECK_RESULT();
1172
1173         link_info->phy_link_status = resp->link;
1174         link_info->link_up =
1175                 (link_info->phy_link_status ==
1176                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1177         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1178         link_info->duplex = resp->duplex_cfg;
1179         link_info->pause = resp->pause;
1180         link_info->auto_pause = resp->auto_pause;
1181         link_info->force_pause = resp->force_pause;
1182         link_info->auto_mode = resp->auto_mode;
1183         link_info->phy_type = resp->phy_type;
1184         link_info->media_type = resp->media_type;
1185
1186         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1187         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1188         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1189         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1190         link_info->phy_ver[0] = resp->phy_maj;
1191         link_info->phy_ver[1] = resp->phy_min;
1192         link_info->phy_ver[2] = resp->phy_bld;
1193
1194         HWRM_UNLOCK();
1195
1196         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1197         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1198         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1199         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1200         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1201                     link_info->auto_link_speed_mask);
1202         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1203                     link_info->force_link_speed);
1204
1205         return rc;
1206 }
1207
1208 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1209 {
1210         int rc = 0;
1211         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1212         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1213         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1214         int i;
1215
1216 get_rx_info:
1217         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1218
1219         req.flags = rte_cpu_to_le_32(dir);
1220         /* HWRM Version >= 1.9.1 */
1221         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1222                 req.drv_qmap_cap =
1223                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1224         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1225
1226         HWRM_CHECK_RESULT();
1227
1228         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1229                 GET_TX_QUEUE_INFO(0);
1230                 GET_TX_QUEUE_INFO(1);
1231                 GET_TX_QUEUE_INFO(2);
1232                 GET_TX_QUEUE_INFO(3);
1233                 GET_TX_QUEUE_INFO(4);
1234                 GET_TX_QUEUE_INFO(5);
1235                 GET_TX_QUEUE_INFO(6);
1236                 GET_TX_QUEUE_INFO(7);
1237         } else  {
1238                 GET_RX_QUEUE_INFO(0);
1239                 GET_RX_QUEUE_INFO(1);
1240                 GET_RX_QUEUE_INFO(2);
1241                 GET_RX_QUEUE_INFO(3);
1242                 GET_RX_QUEUE_INFO(4);
1243                 GET_RX_QUEUE_INFO(5);
1244                 GET_RX_QUEUE_INFO(6);
1245                 GET_RX_QUEUE_INFO(7);
1246         }
1247
1248         HWRM_UNLOCK();
1249
1250         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1251                 goto done;
1252
1253         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1254                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1255         } else {
1256                 int j;
1257
1258                 /* iterate and find the COSq profile to use for Tx */
1259                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1260                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1261                                 if (bp->tx_cos_queue[i].id != 0xff)
1262                                         bp->tx_cosq_id[j++] =
1263                                                 bp->tx_cos_queue[i].id;
1264                         }
1265                 } else {
1266                         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1267                                 if (bp->tx_cos_queue[i].profile ==
1268                                         HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1269                                         bp->tx_cosq_id[0] =
1270                                                 bp->tx_cos_queue[i].id;
1271                                         break;
1272                                 }
1273                         }
1274                 }
1275         }
1276
1277         bp->max_tc = resp->max_configurable_queues;
1278         bp->max_lltc = resp->max_configurable_lossless_queues;
1279         if (bp->max_tc > BNXT_MAX_QUEUE)
1280                 bp->max_tc = BNXT_MAX_QUEUE;
1281         bp->max_q = bp->max_tc;
1282
1283         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1284                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1285                 goto get_rx_info;
1286         }
1287
1288 done:
1289         return rc;
1290 }
1291
1292 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1293                          struct bnxt_ring *ring,
1294                          uint32_t ring_type, uint32_t map_index,
1295                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1296                          uint16_t tx_cosq_id)
1297 {
1298         int rc = 0;
1299         uint32_t enables = 0;
1300         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1301         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1302         struct rte_mempool *mb_pool;
1303         uint16_t rx_buf_size;
1304
1305         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1306
1307         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1308         req.fbo = rte_cpu_to_le_32(0);
1309         /* Association of ring index with doorbell index */
1310         req.logical_id = rte_cpu_to_le_16(map_index);
1311         req.length = rte_cpu_to_le_32(ring->ring_size);
1312
1313         switch (ring_type) {
1314         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1315                 req.ring_type = ring_type;
1316                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1317                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1318                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1319                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1320                         enables |=
1321                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1322                 break;
1323         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1324                 req.ring_type = ring_type;
1325                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1326                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1327                 if (BNXT_CHIP_THOR(bp)) {
1328                         mb_pool = bp->rx_queues[0]->mb_pool;
1329                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1330                                       RTE_PKTMBUF_HEADROOM;
1331                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1332                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1333                         enables |=
1334                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1335                 }
1336                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1337                         enables |=
1338                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1339                 break;
1340         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1341                 req.ring_type = ring_type;
1342                 if (BNXT_HAS_NQ(bp)) {
1343                         /* Association of cp ring with nq */
1344                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1345                         enables |=
1346                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1347                 }
1348                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1349                 break;
1350         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1351                 req.ring_type = ring_type;
1352                 req.page_size = BNXT_PAGE_SHFT;
1353                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1354                 break;
1355         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1356                 req.ring_type = ring_type;
1357                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1358
1359                 mb_pool = bp->rx_queues[0]->mb_pool;
1360                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1361                               RTE_PKTMBUF_HEADROOM;
1362                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1363                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1364
1365                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1366                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1367                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1368                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1369                 break;
1370         default:
1371                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1372                         ring_type);
1373                 HWRM_UNLOCK();
1374                 return -EINVAL;
1375         }
1376         req.enables = rte_cpu_to_le_32(enables);
1377
1378         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1379
1380         if (rc || resp->error_code) {
1381                 if (rc == 0 && resp->error_code)
1382                         rc = rte_le_to_cpu_16(resp->error_code);
1383                 switch (ring_type) {
1384                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1385                         PMD_DRV_LOG(ERR,
1386                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1387                         HWRM_UNLOCK();
1388                         return rc;
1389                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1390                         PMD_DRV_LOG(ERR,
1391                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1392                         HWRM_UNLOCK();
1393                         return rc;
1394                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1395                         PMD_DRV_LOG(ERR,
1396                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1397                                     rc);
1398                         HWRM_UNLOCK();
1399                         return rc;
1400                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1401                         PMD_DRV_LOG(ERR,
1402                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1403                         HWRM_UNLOCK();
1404                         return rc;
1405                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1406                         PMD_DRV_LOG(ERR,
1407                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1408                         HWRM_UNLOCK();
1409                         return rc;
1410                 default:
1411                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1412                         HWRM_UNLOCK();
1413                         return rc;
1414                 }
1415         }
1416
1417         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1418         HWRM_UNLOCK();
1419         return rc;
1420 }
1421
1422 int bnxt_hwrm_ring_free(struct bnxt *bp,
1423                         struct bnxt_ring *ring, uint32_t ring_type)
1424 {
1425         int rc;
1426         struct hwrm_ring_free_input req = {.req_type = 0 };
1427         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1428
1429         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1430
1431         req.ring_type = ring_type;
1432         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1433
1434         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1435
1436         if (rc || resp->error_code) {
1437                 if (rc == 0 && resp->error_code)
1438                         rc = rte_le_to_cpu_16(resp->error_code);
1439                 HWRM_UNLOCK();
1440
1441                 switch (ring_type) {
1442                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1443                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1444                                 rc);
1445                         return rc;
1446                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1447                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1448                                 rc);
1449                         return rc;
1450                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1451                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1452                                 rc);
1453                         return rc;
1454                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1455                         PMD_DRV_LOG(ERR,
1456                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1457                         return rc;
1458                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1459                         PMD_DRV_LOG(ERR,
1460                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1461                         return rc;
1462                 default:
1463                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1464                         return rc;
1465                 }
1466         }
1467         HWRM_UNLOCK();
1468         return 0;
1469 }
1470
1471 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1472 {
1473         int rc = 0;
1474         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1475         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1476
1477         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1478
1479         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1480         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1481         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1482         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1483
1484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1485
1486         HWRM_CHECK_RESULT();
1487
1488         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1489
1490         HWRM_UNLOCK();
1491
1492         return rc;
1493 }
1494
1495 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1496 {
1497         int rc;
1498         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1499         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1500
1501         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1502
1503         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1504
1505         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1506
1507         HWRM_CHECK_RESULT();
1508         HWRM_UNLOCK();
1509
1510         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1511         return rc;
1512 }
1513
1514 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1515 {
1516         int rc = 0;
1517         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1518         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1519
1520         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1521                 return rc;
1522
1523         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1524
1525         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1526
1527         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1528
1529         HWRM_CHECK_RESULT();
1530         HWRM_UNLOCK();
1531
1532         return rc;
1533 }
1534
1535 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1536                                 unsigned int idx __rte_unused)
1537 {
1538         int rc;
1539         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1540         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1541
1542         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1543
1544         req.update_period_ms = rte_cpu_to_le_32(0);
1545
1546         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1547
1548         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1549
1550         HWRM_CHECK_RESULT();
1551
1552         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1553
1554         HWRM_UNLOCK();
1555
1556         return rc;
1557 }
1558
1559 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1560                                 unsigned int idx __rte_unused)
1561 {
1562         int rc;
1563         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1564         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1565
1566         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1567
1568         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1569
1570         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1571
1572         HWRM_CHECK_RESULT();
1573         HWRM_UNLOCK();
1574
1575         return rc;
1576 }
1577
1578 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1579 {
1580         int rc = 0, i, j;
1581         struct hwrm_vnic_alloc_input req = { 0 };
1582         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1583
1584         if (!BNXT_HAS_RING_GRPS(bp))
1585                 goto skip_ring_grps;
1586
1587         /* map ring groups to this vnic */
1588         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1589                 vnic->start_grp_id, vnic->end_grp_id);
1590         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1591                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1592
1593         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1594         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1595         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1596         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1597
1598 skip_ring_grps:
1599         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1600         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1601
1602         if (vnic->func_default)
1603                 req.flags =
1604                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1605         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1606
1607         HWRM_CHECK_RESULT();
1608
1609         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1610         HWRM_UNLOCK();
1611         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1612         return rc;
1613 }
1614
1615 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1616                                         struct bnxt_vnic_info *vnic,
1617                                         struct bnxt_plcmodes_cfg *pmode)
1618 {
1619         int rc = 0;
1620         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1621         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1622
1623         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1624
1625         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1626
1627         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1628
1629         HWRM_CHECK_RESULT();
1630
1631         pmode->flags = rte_le_to_cpu_32(resp->flags);
1632         /* dflt_vnic bit doesn't exist in the _cfg command */
1633         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1634         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1635         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1636         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1637
1638         HWRM_UNLOCK();
1639
1640         return rc;
1641 }
1642
1643 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1644                                        struct bnxt_vnic_info *vnic,
1645                                        struct bnxt_plcmodes_cfg *pmode)
1646 {
1647         int rc = 0;
1648         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1649         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1650
1651         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1652                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1653                 return rc;
1654         }
1655
1656         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1657
1658         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1659         req.flags = rte_cpu_to_le_32(pmode->flags);
1660         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1661         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1662         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1663         req.enables = rte_cpu_to_le_32(
1664             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1665             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1666             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1667         );
1668
1669         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1670
1671         HWRM_CHECK_RESULT();
1672         HWRM_UNLOCK();
1673
1674         return rc;
1675 }
1676
1677 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1678 {
1679         int rc = 0;
1680         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1681         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1682         struct bnxt_plcmodes_cfg pmodes = { 0 };
1683         uint32_t ctx_enable_flag = 0;
1684         uint32_t enables = 0;
1685
1686         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1687                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1688                 return rc;
1689         }
1690
1691         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1692         if (rc)
1693                 return rc;
1694
1695         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1696
1697         if (BNXT_CHIP_THOR(bp)) {
1698                 struct bnxt_rx_queue *rxq =
1699                         bp->eth_dev->data->rx_queues[vnic->start_grp_id];
1700                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1701                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1702
1703                 req.default_rx_ring_id =
1704                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1705                 req.default_cmpl_ring_id =
1706                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1707                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1708                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1709                 goto config_mru;
1710         }
1711
1712         /* Only RSS support for now TBD: COS & LB */
1713         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1714         if (vnic->lb_rule != 0xffff)
1715                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1716         if (vnic->cos_rule != 0xffff)
1717                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1718         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1719                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1720                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1721         }
1722         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1723                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1724                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1725         }
1726
1727         enables |= ctx_enable_flag;
1728         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1729         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1730         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1731         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1732
1733 config_mru:
1734         req.enables = rte_cpu_to_le_32(enables);
1735         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1736         req.mru = rte_cpu_to_le_16(vnic->mru);
1737         /* Configure default VNIC only once. */
1738         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1739                 req.flags |=
1740                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1741                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1742         }
1743         if (vnic->vlan_strip)
1744                 req.flags |=
1745                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1746         if (vnic->bd_stall)
1747                 req.flags |=
1748                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1749         if (vnic->roce_dual)
1750                 req.flags |= rte_cpu_to_le_32(
1751                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1752         if (vnic->roce_only)
1753                 req.flags |= rte_cpu_to_le_32(
1754                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1755         if (vnic->rss_dflt_cr)
1756                 req.flags |= rte_cpu_to_le_32(
1757                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1758
1759         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1760
1761         HWRM_CHECK_RESULT();
1762         HWRM_UNLOCK();
1763
1764         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1765
1766         return rc;
1767 }
1768
1769 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1770                 int16_t fw_vf_id)
1771 {
1772         int rc = 0;
1773         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1774         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1775
1776         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1777                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1778                 return rc;
1779         }
1780         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1781
1782         req.enables =
1783                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1784         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1785         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1786
1787         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1788
1789         HWRM_CHECK_RESULT();
1790
1791         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1792         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1793         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1794         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1795         vnic->mru = rte_le_to_cpu_16(resp->mru);
1796         vnic->func_default = rte_le_to_cpu_32(
1797                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1798         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1799                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1800         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1801                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1802         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1803                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1804         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1805                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1806         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1807                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1808
1809         HWRM_UNLOCK();
1810
1811         return rc;
1812 }
1813
1814 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1815                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1816 {
1817         int rc = 0;
1818         uint16_t ctx_id;
1819         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1820         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1821                                                 bp->hwrm_cmd_resp_addr;
1822
1823         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1824
1825         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1826         HWRM_CHECK_RESULT();
1827
1828         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1829         if (!BNXT_HAS_RING_GRPS(bp))
1830                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1831         else if (ctx_idx == 0)
1832                 vnic->rss_rule = ctx_id;
1833
1834         HWRM_UNLOCK();
1835
1836         return rc;
1837 }
1838
1839 static
1840 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1841                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1842 {
1843         int rc = 0;
1844         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1845         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1846                                                 bp->hwrm_cmd_resp_addr;
1847
1848         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1849                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1850                 return rc;
1851         }
1852         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1853
1854         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1855
1856         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1857
1858         HWRM_CHECK_RESULT();
1859         HWRM_UNLOCK();
1860
1861         return rc;
1862 }
1863
1864 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1865 {
1866         int rc = 0;
1867
1868         if (BNXT_CHIP_THOR(bp)) {
1869                 int j;
1870
1871                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1872                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1873                                                       vnic,
1874                                                       vnic->fw_grp_ids[j]);
1875                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1876                 }
1877                 vnic->num_lb_ctxts = 0;
1878         } else {
1879                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1880                 vnic->rss_rule = INVALID_HW_RING_ID;
1881         }
1882
1883         return rc;
1884 }
1885
1886 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1887 {
1888         int rc = 0;
1889         struct hwrm_vnic_free_input req = {.req_type = 0 };
1890         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1891
1892         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1893                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1894                 return rc;
1895         }
1896
1897         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1898
1899         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1900
1901         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1902
1903         HWRM_CHECK_RESULT();
1904         HWRM_UNLOCK();
1905
1906         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1907         /* Configure default VNIC again if necessary. */
1908         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1909                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1910
1911         return rc;
1912 }
1913
1914 static int
1915 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1916 {
1917         int i;
1918         int rc = 0;
1919         int nr_ctxs = vnic->num_lb_ctxts;
1920         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1921         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1922
1923         for (i = 0; i < nr_ctxs; i++) {
1924                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1925
1926                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1927                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1928                 req.hash_mode_flags = vnic->hash_mode;
1929
1930                 req.hash_key_tbl_addr =
1931                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1932
1933                 req.ring_grp_tbl_addr =
1934                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1935                                          i * HW_HASH_INDEX_SIZE);
1936                 req.ring_table_pair_index = i;
1937                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1938
1939                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1940                                             BNXT_USE_CHIMP_MB);
1941
1942                 HWRM_CHECK_RESULT();
1943                 HWRM_UNLOCK();
1944         }
1945
1946         return rc;
1947 }
1948
1949 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1950                            struct bnxt_vnic_info *vnic)
1951 {
1952         int rc = 0;
1953         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1954         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1955
1956         if (!vnic->rss_table)
1957                 return 0;
1958
1959         if (BNXT_CHIP_THOR(bp))
1960                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1961
1962         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1963
1964         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1965         req.hash_mode_flags = vnic->hash_mode;
1966
1967         req.ring_grp_tbl_addr =
1968             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1969         req.hash_key_tbl_addr =
1970             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1971         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1972         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1973
1974         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1975
1976         HWRM_CHECK_RESULT();
1977         HWRM_UNLOCK();
1978
1979         return rc;
1980 }
1981
1982 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1983                         struct bnxt_vnic_info *vnic)
1984 {
1985         int rc = 0;
1986         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1987         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1988         uint16_t size;
1989
1990         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1991                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1992                 return rc;
1993         }
1994
1995         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1996
1997         req.flags = rte_cpu_to_le_32(
1998                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1999
2000         req.enables = rte_cpu_to_le_32(
2001                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2002
2003         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2004         size -= RTE_PKTMBUF_HEADROOM;
2005         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2006
2007         req.jumbo_thresh = rte_cpu_to_le_16(size);
2008         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2009
2010         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2011
2012         HWRM_CHECK_RESULT();
2013         HWRM_UNLOCK();
2014
2015         return rc;
2016 }
2017
2018 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2019                         struct bnxt_vnic_info *vnic, bool enable)
2020 {
2021         int rc = 0;
2022         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2023         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2024
2025         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2026                 if (enable)
2027                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2028                 return -ENOTSUP;
2029         }
2030
2031         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2032                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2033                 return 0;
2034         }
2035
2036         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2037
2038         if (enable) {
2039                 req.enables = rte_cpu_to_le_32(
2040                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2041                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2042                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2043                 req.flags = rte_cpu_to_le_32(
2044                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2045                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2046                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2047                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2048                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2049                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2050                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2051                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2052                 req.min_agg_len = rte_cpu_to_le_32(512);
2053         }
2054         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2055
2056         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2057
2058         HWRM_CHECK_RESULT();
2059         HWRM_UNLOCK();
2060
2061         return rc;
2062 }
2063
2064 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2065 {
2066         struct hwrm_func_cfg_input req = {0};
2067         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2068         int rc;
2069
2070         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2071         req.enables = rte_cpu_to_le_32(
2072                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2073         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2074         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2075
2076         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2077
2078         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2079         HWRM_CHECK_RESULT();
2080         HWRM_UNLOCK();
2081
2082         bp->pf.vf_info[vf].random_mac = false;
2083
2084         return rc;
2085 }
2086
2087 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2088                                   uint64_t *dropped)
2089 {
2090         int rc = 0;
2091         struct hwrm_func_qstats_input req = {.req_type = 0};
2092         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2093
2094         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2095
2096         req.fid = rte_cpu_to_le_16(fid);
2097
2098         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2099
2100         HWRM_CHECK_RESULT();
2101
2102         if (dropped)
2103                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2104
2105         HWRM_UNLOCK();
2106
2107         return rc;
2108 }
2109
2110 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2111                           struct rte_eth_stats *stats)
2112 {
2113         int rc = 0;
2114         struct hwrm_func_qstats_input req = {.req_type = 0};
2115         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2116
2117         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2118
2119         req.fid = rte_cpu_to_le_16(fid);
2120
2121         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2122
2123         HWRM_CHECK_RESULT();
2124
2125         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2126         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2127         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2128         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2129         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2130         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2131
2132         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2133         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2134         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2135         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2136         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2137         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2138
2139         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2140         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2141         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2142
2143         HWRM_UNLOCK();
2144
2145         return rc;
2146 }
2147
2148 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2149 {
2150         int rc = 0;
2151         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2152         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2153
2154         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2155
2156         req.fid = rte_cpu_to_le_16(fid);
2157
2158         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2159
2160         HWRM_CHECK_RESULT();
2161         HWRM_UNLOCK();
2162
2163         return rc;
2164 }
2165
2166 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2167 {
2168         unsigned int i;
2169         int rc = 0;
2170
2171         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2172                 struct bnxt_tx_queue *txq;
2173                 struct bnxt_rx_queue *rxq;
2174                 struct bnxt_cp_ring_info *cpr;
2175
2176                 if (i >= bp->rx_cp_nr_rings) {
2177                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2178                         cpr = txq->cp_ring;
2179                 } else {
2180                         rxq = bp->rx_queues[i];
2181                         cpr = rxq->cp_ring;
2182                 }
2183
2184                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2185                 if (rc)
2186                         return rc;
2187         }
2188         return 0;
2189 }
2190
2191 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2192 {
2193         int rc;
2194         unsigned int i;
2195         struct bnxt_cp_ring_info *cpr;
2196
2197         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2198
2199                 if (i >= bp->rx_cp_nr_rings) {
2200                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2201                 } else {
2202                         cpr = bp->rx_queues[i]->cp_ring;
2203                         if (BNXT_HAS_RING_GRPS(bp))
2204                                 bp->grp_info[i].fw_stats_ctx = -1;
2205                 }
2206                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2207                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2208                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2209                         if (rc)
2210                                 return rc;
2211                 }
2212         }
2213         return 0;
2214 }
2215
2216 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2217 {
2218         unsigned int i;
2219         int rc = 0;
2220
2221         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2222                 struct bnxt_tx_queue *txq;
2223                 struct bnxt_rx_queue *rxq;
2224                 struct bnxt_cp_ring_info *cpr;
2225
2226                 if (i >= bp->rx_cp_nr_rings) {
2227                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2228                         cpr = txq->cp_ring;
2229                 } else {
2230                         rxq = bp->rx_queues[i];
2231                         cpr = rxq->cp_ring;
2232                 }
2233
2234                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2235
2236                 if (rc)
2237                         return rc;
2238         }
2239         return rc;
2240 }
2241
2242 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2243 {
2244         uint16_t idx;
2245         uint32_t rc = 0;
2246
2247         if (!BNXT_HAS_RING_GRPS(bp))
2248                 return 0;
2249
2250         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2251
2252                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2253                         continue;
2254
2255                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2256
2257                 if (rc)
2258                         return rc;
2259         }
2260         return rc;
2261 }
2262
2263 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2264 {
2265         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2266
2267         bnxt_hwrm_ring_free(bp, cp_ring,
2268                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2269         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2270         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2271                                      sizeof(*cpr->cp_desc_ring));
2272         cpr->cp_raw_cons = 0;
2273         cpr->valid = 0;
2274 }
2275
2276 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2277 {
2278         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2279
2280         bnxt_hwrm_ring_free(bp, cp_ring,
2281                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2282         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2283         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2284                         sizeof(*cpr->cp_desc_ring));
2285         cpr->cp_raw_cons = 0;
2286         cpr->valid = 0;
2287 }
2288
2289 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2290 {
2291         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2292         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2293         struct bnxt_ring *ring = rxr->rx_ring_struct;
2294         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2295
2296         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2297                 bnxt_hwrm_ring_free(bp, ring,
2298                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2299                 ring->fw_ring_id = INVALID_HW_RING_ID;
2300                 if (BNXT_HAS_RING_GRPS(bp))
2301                         bp->grp_info[queue_index].rx_fw_ring_id =
2302                                                         INVALID_HW_RING_ID;
2303                 memset(rxr->rx_desc_ring, 0,
2304                        rxr->rx_ring_struct->ring_size *
2305                        sizeof(*rxr->rx_desc_ring));
2306                 memset(rxr->rx_buf_ring, 0,
2307                        rxr->rx_ring_struct->ring_size *
2308                        sizeof(*rxr->rx_buf_ring));
2309                 rxr->rx_prod = 0;
2310         }
2311         ring = rxr->ag_ring_struct;
2312         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2313                 bnxt_hwrm_ring_free(bp, ring,
2314                                     BNXT_CHIP_THOR(bp) ?
2315                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2316                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2317                 ring->fw_ring_id = INVALID_HW_RING_ID;
2318                 memset(rxr->ag_buf_ring, 0,
2319                        rxr->ag_ring_struct->ring_size *
2320                        sizeof(*rxr->ag_buf_ring));
2321                 rxr->ag_prod = 0;
2322                 if (BNXT_HAS_RING_GRPS(bp))
2323                         bp->grp_info[queue_index].ag_fw_ring_id =
2324                                                         INVALID_HW_RING_ID;
2325         }
2326         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2327                 bnxt_free_cp_ring(bp, cpr);
2328
2329         if (BNXT_HAS_RING_GRPS(bp))
2330                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2331 }
2332
2333 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2334 {
2335         unsigned int i;
2336
2337         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2338                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2339                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2340                 struct bnxt_ring *ring = txr->tx_ring_struct;
2341                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2342
2343                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2344                         bnxt_hwrm_ring_free(bp, ring,
2345                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2346                         ring->fw_ring_id = INVALID_HW_RING_ID;
2347                         memset(txr->tx_desc_ring, 0,
2348                                         txr->tx_ring_struct->ring_size *
2349                                         sizeof(*txr->tx_desc_ring));
2350                         memset(txr->tx_buf_ring, 0,
2351                                         txr->tx_ring_struct->ring_size *
2352                                         sizeof(*txr->tx_buf_ring));
2353                         txr->tx_prod = 0;
2354                         txr->tx_cons = 0;
2355                 }
2356                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2357                         bnxt_free_cp_ring(bp, cpr);
2358                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2359                 }
2360         }
2361
2362         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2363                 bnxt_free_hwrm_rx_ring(bp, i);
2364
2365         return 0;
2366 }
2367
2368 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2369 {
2370         uint16_t i;
2371         uint32_t rc = 0;
2372
2373         if (!BNXT_HAS_RING_GRPS(bp))
2374                 return 0;
2375
2376         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2377                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2378                 if (rc)
2379                         return rc;
2380         }
2381         return rc;
2382 }
2383
2384 /*
2385  * HWRM utility functions
2386  */
2387
2388 void bnxt_free_hwrm_resources(struct bnxt *bp)
2389 {
2390         /* Release memzone */
2391         rte_free(bp->hwrm_cmd_resp_addr);
2392         rte_free(bp->hwrm_short_cmd_req_addr);
2393         bp->hwrm_cmd_resp_addr = NULL;
2394         bp->hwrm_short_cmd_req_addr = NULL;
2395         bp->hwrm_cmd_resp_dma_addr = 0;
2396         bp->hwrm_short_cmd_req_dma_addr = 0;
2397 }
2398
2399 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2400 {
2401         struct rte_pci_device *pdev = bp->pdev;
2402         char type[RTE_MEMZONE_NAMESIZE];
2403
2404         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2405                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2406         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2407         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2408         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2409         if (bp->hwrm_cmd_resp_addr == NULL)
2410                 return -ENOMEM;
2411         bp->hwrm_cmd_resp_dma_addr =
2412                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2413         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2414                 PMD_DRV_LOG(ERR,
2415                         "unable to map response address to physical memory\n");
2416                 return -ENOMEM;
2417         }
2418         rte_spinlock_init(&bp->hwrm_lock);
2419
2420         return 0;
2421 }
2422
2423 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2424 {
2425         struct bnxt_filter_info *filter;
2426         int rc = 0;
2427
2428         STAILQ_FOREACH(filter, &vnic->filter, next) {
2429                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2430                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2431                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2432                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2433                 else
2434                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2435                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2436                 bnxt_free_filter(bp, filter);
2437         }
2438         return rc;
2439 }
2440
2441 static int
2442 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2443 {
2444         struct bnxt_filter_info *filter;
2445         struct rte_flow *flow;
2446         int rc = 0;
2447
2448         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2449                 flow = STAILQ_FIRST(&vnic->flow_list);
2450                 filter = flow->filter;
2451                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2452                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2453                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2454                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2455                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2456                 else
2457                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2458
2459                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2460                 rte_free(flow);
2461         }
2462         return rc;
2463 }
2464
2465 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2466 {
2467         struct bnxt_filter_info *filter;
2468         int rc = 0;
2469
2470         STAILQ_FOREACH(filter, &vnic->filter, next) {
2471                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2472                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2473                                                      filter);
2474                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2475                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2476                                                          filter);
2477                 else
2478                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2479                                                      filter);
2480                 if (rc)
2481                         break;
2482         }
2483         return rc;
2484 }
2485
2486 void bnxt_free_tunnel_ports(struct bnxt *bp)
2487 {
2488         if (bp->vxlan_port_cnt)
2489                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2490                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2491         bp->vxlan_port = 0;
2492         if (bp->geneve_port_cnt)
2493                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2494                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2495         bp->geneve_port = 0;
2496 }
2497
2498 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2499 {
2500         int i;
2501
2502         if (bp->vnic_info == NULL)
2503                 return;
2504
2505         /*
2506          * Cleanup VNICs in reverse order, to make sure the L2 filter
2507          * from vnic0 is last to be cleaned up.
2508          */
2509         for (i = bp->max_vnics - 1; i >= 0; i--) {
2510                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2511
2512                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2513                         continue;
2514
2515                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2516
2517                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2518
2519                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2520
2521                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2522
2523                 bnxt_hwrm_vnic_free(bp, vnic);
2524
2525                 rte_free(vnic->fw_grp_ids);
2526         }
2527         /* Ring resources */
2528         bnxt_free_all_hwrm_rings(bp);
2529         bnxt_free_all_hwrm_ring_grps(bp);
2530         bnxt_free_all_hwrm_stat_ctxs(bp);
2531         bnxt_free_tunnel_ports(bp);
2532 }
2533
2534 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2535 {
2536         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2537
2538         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2539                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2540
2541         switch (conf_link_speed) {
2542         case ETH_LINK_SPEED_10M_HD:
2543         case ETH_LINK_SPEED_100M_HD:
2544                 /* FALLTHROUGH */
2545                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2546         }
2547         return hw_link_duplex;
2548 }
2549
2550 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2551 {
2552         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2553 }
2554
2555 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2556 {
2557         uint16_t eth_link_speed = 0;
2558
2559         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2560                 return ETH_LINK_SPEED_AUTONEG;
2561
2562         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2563         case ETH_LINK_SPEED_100M:
2564         case ETH_LINK_SPEED_100M_HD:
2565                 /* FALLTHROUGH */
2566                 eth_link_speed =
2567                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2568                 break;
2569         case ETH_LINK_SPEED_1G:
2570                 eth_link_speed =
2571                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2572                 break;
2573         case ETH_LINK_SPEED_2_5G:
2574                 eth_link_speed =
2575                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2576                 break;
2577         case ETH_LINK_SPEED_10G:
2578                 eth_link_speed =
2579                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2580                 break;
2581         case ETH_LINK_SPEED_20G:
2582                 eth_link_speed =
2583                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2584                 break;
2585         case ETH_LINK_SPEED_25G:
2586                 eth_link_speed =
2587                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2588                 break;
2589         case ETH_LINK_SPEED_40G:
2590                 eth_link_speed =
2591                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2592                 break;
2593         case ETH_LINK_SPEED_50G:
2594                 eth_link_speed =
2595                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2596                 break;
2597         case ETH_LINK_SPEED_100G:
2598                 eth_link_speed =
2599                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2600                 break;
2601         default:
2602                 PMD_DRV_LOG(ERR,
2603                         "Unsupported link speed %d; default to AUTO\n",
2604                         conf_link_speed);
2605                 break;
2606         }
2607         return eth_link_speed;
2608 }
2609
2610 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2611                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2612                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2613                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2614
2615 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2616 {
2617         uint32_t one_speed;
2618
2619         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2620                 return 0;
2621
2622         if (link_speed & ETH_LINK_SPEED_FIXED) {
2623                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2624
2625                 if (one_speed & (one_speed - 1)) {
2626                         PMD_DRV_LOG(ERR,
2627                                 "Invalid advertised speeds (%u) for port %u\n",
2628                                 link_speed, port_id);
2629                         return -EINVAL;
2630                 }
2631                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2632                         PMD_DRV_LOG(ERR,
2633                                 "Unsupported advertised speed (%u) for port %u\n",
2634                                 link_speed, port_id);
2635                         return -EINVAL;
2636                 }
2637         } else {
2638                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2639                         PMD_DRV_LOG(ERR,
2640                                 "Unsupported advertised speeds (%u) for port %u\n",
2641                                 link_speed, port_id);
2642                         return -EINVAL;
2643                 }
2644         }
2645         return 0;
2646 }
2647
2648 static uint16_t
2649 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2650 {
2651         uint16_t ret = 0;
2652
2653         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2654                 if (bp->link_info.support_speeds)
2655                         return bp->link_info.support_speeds;
2656                 link_speed = BNXT_SUPPORTED_SPEEDS;
2657         }
2658
2659         if (link_speed & ETH_LINK_SPEED_100M)
2660                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2661         if (link_speed & ETH_LINK_SPEED_100M_HD)
2662                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2663         if (link_speed & ETH_LINK_SPEED_1G)
2664                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2665         if (link_speed & ETH_LINK_SPEED_2_5G)
2666                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2667         if (link_speed & ETH_LINK_SPEED_10G)
2668                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2669         if (link_speed & ETH_LINK_SPEED_20G)
2670                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2671         if (link_speed & ETH_LINK_SPEED_25G)
2672                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2673         if (link_speed & ETH_LINK_SPEED_40G)
2674                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2675         if (link_speed & ETH_LINK_SPEED_50G)
2676                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2677         if (link_speed & ETH_LINK_SPEED_100G)
2678                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2679         return ret;
2680 }
2681
2682 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2683 {
2684         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2685
2686         switch (hw_link_speed) {
2687         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2688                 eth_link_speed = ETH_SPEED_NUM_100M;
2689                 break;
2690         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2691                 eth_link_speed = ETH_SPEED_NUM_1G;
2692                 break;
2693         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2694                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2695                 break;
2696         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2697                 eth_link_speed = ETH_SPEED_NUM_10G;
2698                 break;
2699         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2700                 eth_link_speed = ETH_SPEED_NUM_20G;
2701                 break;
2702         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2703                 eth_link_speed = ETH_SPEED_NUM_25G;
2704                 break;
2705         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2706                 eth_link_speed = ETH_SPEED_NUM_40G;
2707                 break;
2708         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2709                 eth_link_speed = ETH_SPEED_NUM_50G;
2710                 break;
2711         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2712                 eth_link_speed = ETH_SPEED_NUM_100G;
2713                 break;
2714         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2715         default:
2716                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2717                         hw_link_speed);
2718                 break;
2719         }
2720         return eth_link_speed;
2721 }
2722
2723 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2724 {
2725         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2726
2727         switch (hw_link_duplex) {
2728         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2729         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2730                 /* FALLTHROUGH */
2731                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2732                 break;
2733         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2734                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2735                 break;
2736         default:
2737                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2738                         hw_link_duplex);
2739                 break;
2740         }
2741         return eth_link_duplex;
2742 }
2743
2744 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2745 {
2746         int rc = 0;
2747         struct bnxt_link_info *link_info = &bp->link_info;
2748
2749         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2750         if (rc) {
2751                 PMD_DRV_LOG(ERR,
2752                         "Get link config failed with rc %d\n", rc);
2753                 goto exit;
2754         }
2755         if (link_info->link_speed)
2756                 link->link_speed =
2757                         bnxt_parse_hw_link_speed(link_info->link_speed);
2758         else
2759                 link->link_speed = ETH_SPEED_NUM_NONE;
2760         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2761         link->link_status = link_info->link_up;
2762         link->link_autoneg = link_info->auto_mode ==
2763                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2764                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2765 exit:
2766         return rc;
2767 }
2768
2769 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2770 {
2771         int rc = 0;
2772         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2773         struct bnxt_link_info link_req;
2774         uint16_t speed, autoneg;
2775
2776         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2777                 return 0;
2778
2779         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2780                         bp->eth_dev->data->port_id);
2781         if (rc)
2782                 goto error;
2783
2784         memset(&link_req, 0, sizeof(link_req));
2785         link_req.link_up = link_up;
2786         if (!link_up)
2787                 goto port_phy_cfg;
2788
2789         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2790         if (BNXT_CHIP_THOR(bp) &&
2791             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2792                 /* 40G is not supported as part of media auto detect.
2793                  * The speed should be forced and autoneg disabled
2794                  * to configure 40G speed.
2795                  */
2796                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2797                 autoneg = 0;
2798         }
2799
2800         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2801         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2802         /* Autoneg can be done only when the FW allows.
2803          * When user configures fixed speed of 40G and later changes to
2804          * any other speed, auto_link_speed/force_link_speed is still set
2805          * to 40G until link comes up at new speed.
2806          */
2807         if (autoneg == 1 &&
2808             !(!BNXT_CHIP_THOR(bp) &&
2809               (bp->link_info.auto_link_speed ||
2810                bp->link_info.force_link_speed))) {
2811                 link_req.phy_flags |=
2812                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2813                 link_req.auto_link_speed_mask =
2814                         bnxt_parse_eth_link_speed_mask(bp,
2815                                                        dev_conf->link_speeds);
2816         } else {
2817                 if (bp->link_info.phy_type ==
2818                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2819                     bp->link_info.phy_type ==
2820                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2821                     bp->link_info.media_type ==
2822                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2823                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2824                         return -EINVAL;
2825                 }
2826
2827                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2828                 /* If user wants a particular speed try that first. */
2829                 if (speed)
2830                         link_req.link_speed = speed;
2831                 else if (bp->link_info.force_link_speed)
2832                         link_req.link_speed = bp->link_info.force_link_speed;
2833                 else
2834                         link_req.link_speed = bp->link_info.auto_link_speed;
2835         }
2836         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2837         link_req.auto_pause = bp->link_info.auto_pause;
2838         link_req.force_pause = bp->link_info.force_pause;
2839
2840 port_phy_cfg:
2841         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2842         if (rc) {
2843                 PMD_DRV_LOG(ERR,
2844                         "Set link config failed with rc %d\n", rc);
2845         }
2846
2847 error:
2848         return rc;
2849 }
2850
2851 /* JIRA 22088 */
2852 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2853 {
2854         struct hwrm_func_qcfg_input req = {0};
2855         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2856         uint16_t flags;
2857         int rc = 0;
2858
2859         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2860         req.fid = rte_cpu_to_le_16(0xffff);
2861
2862         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2863
2864         HWRM_CHECK_RESULT();
2865
2866         /* Hard Coded.. 0xfff VLAN ID mask */
2867         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2868         flags = rte_le_to_cpu_16(resp->flags);
2869         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2870                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2871
2872         if (BNXT_VF(bp) &&
2873             !BNXT_VF_IS_TRUSTED(bp) &&
2874             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2875                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2876                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2877         } else if (BNXT_VF(bp) &&
2878                    BNXT_VF_IS_TRUSTED(bp) &&
2879                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2880                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2881                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2882         }
2883
2884         if (mtu)
2885                 *mtu = rte_le_to_cpu_16(resp->mtu);
2886
2887         switch (resp->port_partition_type) {
2888         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2889         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2890         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2891                 /* FALLTHROUGH */
2892                 bp->port_partition_type = resp->port_partition_type;
2893                 break;
2894         default:
2895                 bp->port_partition_type = 0;
2896                 break;
2897         }
2898
2899         HWRM_UNLOCK();
2900
2901         return rc;
2902 }
2903
2904 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2905                                    struct hwrm_func_qcaps_output *qcaps)
2906 {
2907         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2908         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2909                sizeof(qcaps->mac_address));
2910         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2911         qcaps->max_rx_rings = fcfg->num_rx_rings;
2912         qcaps->max_tx_rings = fcfg->num_tx_rings;
2913         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2914         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2915         qcaps->max_vfs = 0;
2916         qcaps->first_vf_id = 0;
2917         qcaps->max_vnics = fcfg->num_vnics;
2918         qcaps->max_decap_records = 0;
2919         qcaps->max_encap_records = 0;
2920         qcaps->max_tx_wm_flows = 0;
2921         qcaps->max_tx_em_flows = 0;
2922         qcaps->max_rx_wm_flows = 0;
2923         qcaps->max_rx_em_flows = 0;
2924         qcaps->max_flow_id = 0;
2925         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2926         qcaps->max_sp_tx_rings = 0;
2927         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2928 }
2929
2930 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2931 {
2932         struct hwrm_func_cfg_input req = {0};
2933         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2934         uint32_t enables;
2935         int rc;
2936
2937         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2938                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2939                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2940                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2941                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2942                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2943                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2944                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2945                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2946
2947         if (BNXT_HAS_RING_GRPS(bp)) {
2948                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2949                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2950         } else if (BNXT_HAS_NQ(bp)) {
2951                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2952                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2953         }
2954
2955         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2956         req.mtu = rte_cpu_to_le_16(RTE_MIN(bp->eth_dev->data->mtu,
2957                                            BNXT_MAX_MTU)); //FW adds hdr sizes
2958         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
2959         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2960         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2961         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2962         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2963         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2964         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2965         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2966         req.fid = rte_cpu_to_le_16(0xffff);
2967         req.enables = rte_cpu_to_le_32(enables);
2968
2969         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2970
2971         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2972
2973         HWRM_CHECK_RESULT();
2974         HWRM_UNLOCK();
2975
2976         return rc;
2977 }
2978
2979 static void populate_vf_func_cfg_req(struct bnxt *bp,
2980                                      struct hwrm_func_cfg_input *req,
2981                                      int num_vfs)
2982 {
2983         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2984                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2985                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2986                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2987                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2988                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2989                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2990                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2991                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2992                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2993
2994         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2995                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2996                                     BNXT_NUM_VLANS);
2997         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
2998         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2999                                                 (num_vfs + 1));
3000         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3001         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3002                                                (num_vfs + 1));
3003         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3004         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3005         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3006         /* TODO: For now, do not support VMDq/RFS on VFs. */
3007         req->num_vnics = rte_cpu_to_le_16(1);
3008         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3009                                                  (num_vfs + 1));
3010 }
3011
3012 static void add_random_mac_if_needed(struct bnxt *bp,
3013                                      struct hwrm_func_cfg_input *cfg_req,
3014                                      int vf)
3015 {
3016         struct rte_ether_addr mac;
3017
3018         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3019                 return;
3020
3021         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3022                 cfg_req->enables |=
3023                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3024                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3025                 bp->pf.vf_info[vf].random_mac = true;
3026         } else {
3027                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3028                         RTE_ETHER_ADDR_LEN);
3029         }
3030 }
3031
3032 static void reserve_resources_from_vf(struct bnxt *bp,
3033                                       struct hwrm_func_cfg_input *cfg_req,
3034                                       int vf)
3035 {
3036         struct hwrm_func_qcaps_input req = {0};
3037         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3038         int rc;
3039
3040         /* Get the actual allocated values now */
3041         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3042         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3043         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3044
3045         if (rc) {
3046                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3047                 copy_func_cfg_to_qcaps(cfg_req, resp);
3048         } else if (resp->error_code) {
3049                 rc = rte_le_to_cpu_16(resp->error_code);
3050                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3051                 copy_func_cfg_to_qcaps(cfg_req, resp);
3052         }
3053
3054         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3055         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3056         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3057         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3058         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3059         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3060         /*
3061          * TODO: While not supporting VMDq with VFs, max_vnics is always
3062          * forced to 1 in this case
3063          */
3064         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3065         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3066
3067         HWRM_UNLOCK();
3068 }
3069
3070 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3071 {
3072         struct hwrm_func_qcfg_input req = {0};
3073         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3074         int rc;
3075
3076         /* Check for zero MAC address */
3077         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3078         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3079         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3080         HWRM_CHECK_RESULT();
3081         rc = rte_le_to_cpu_16(resp->vlan);
3082
3083         HWRM_UNLOCK();
3084
3085         return rc;
3086 }
3087
3088 static int update_pf_resource_max(struct bnxt *bp)
3089 {
3090         struct hwrm_func_qcfg_input req = {0};
3091         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3092         int rc;
3093
3094         /* And copy the allocated numbers into the pf struct */
3095         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3096         req.fid = rte_cpu_to_le_16(0xffff);
3097         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3098         HWRM_CHECK_RESULT();
3099
3100         /* Only TX ring value reflects actual allocation? TODO */
3101         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3102         bp->pf.evb_mode = resp->evb_mode;
3103
3104         HWRM_UNLOCK();
3105
3106         return rc;
3107 }
3108
3109 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3110 {
3111         int rc;
3112
3113         if (!BNXT_PF(bp)) {
3114                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3115                 return -EINVAL;
3116         }
3117
3118         rc = bnxt_hwrm_func_qcaps(bp);
3119         if (rc)
3120                 return rc;
3121
3122         bp->pf.func_cfg_flags &=
3123                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3124                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3125         bp->pf.func_cfg_flags |=
3126                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3127         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3128         rc = __bnxt_hwrm_func_qcaps(bp);
3129         return rc;
3130 }
3131
3132 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3133 {
3134         struct hwrm_func_cfg_input req = {0};
3135         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3136         int i;
3137         size_t sz;
3138         int rc = 0;
3139         size_t req_buf_sz;
3140
3141         if (!BNXT_PF(bp)) {
3142                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3143                 return -EINVAL;
3144         }
3145
3146         rc = bnxt_hwrm_func_qcaps(bp);
3147
3148         if (rc)
3149                 return rc;
3150
3151         bp->pf.active_vfs = num_vfs;
3152
3153         /*
3154          * First, configure the PF to only use one TX ring.  This ensures that
3155          * there are enough rings for all VFs.
3156          *
3157          * If we don't do this, when we call func_alloc() later, we will lock
3158          * extra rings to the PF that won't be available during func_cfg() of
3159          * the VFs.
3160          *
3161          * This has been fixed with firmware versions above 20.6.54
3162          */
3163         bp->pf.func_cfg_flags &=
3164                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3165                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3166         bp->pf.func_cfg_flags |=
3167                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3168         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3169         if (rc)
3170                 return rc;
3171
3172         /*
3173          * Now, create and register a buffer to hold forwarded VF requests
3174          */
3175         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3176         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3177                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3178         if (bp->pf.vf_req_buf == NULL) {
3179                 rc = -ENOMEM;
3180                 goto error_free;
3181         }
3182         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3183                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3184         for (i = 0; i < num_vfs; i++)
3185                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3186                                         (i * HWRM_MAX_REQ_LEN);
3187
3188         rc = bnxt_hwrm_func_buf_rgtr(bp);
3189         if (rc)
3190                 goto error_free;
3191
3192         populate_vf_func_cfg_req(bp, &req, num_vfs);
3193
3194         bp->pf.active_vfs = 0;
3195         for (i = 0; i < num_vfs; i++) {
3196                 add_random_mac_if_needed(bp, &req, i);
3197
3198                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3199                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3200                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3201                 rc = bnxt_hwrm_send_message(bp,
3202                                             &req,
3203                                             sizeof(req),
3204                                             BNXT_USE_CHIMP_MB);
3205
3206                 /* Clear enable flag for next pass */
3207                 req.enables &= ~rte_cpu_to_le_32(
3208                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3209
3210                 if (rc || resp->error_code) {
3211                         PMD_DRV_LOG(ERR,
3212                                 "Failed to initizlie VF %d\n", i);
3213                         PMD_DRV_LOG(ERR,
3214                                 "Not all VFs available. (%d, %d)\n",
3215                                 rc, resp->error_code);
3216                         HWRM_UNLOCK();
3217                         break;
3218                 }
3219
3220                 HWRM_UNLOCK();
3221
3222                 reserve_resources_from_vf(bp, &req, i);
3223                 bp->pf.active_vfs++;
3224                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3225         }
3226
3227         /*
3228          * Now configure the PF to use "the rest" of the resources
3229          * We're using STD_TX_RING_MODE here though which will limit the TX
3230          * rings.  This will allow QoS to function properly.  Not setting this
3231          * will cause PF rings to break bandwidth settings.
3232          */
3233         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3234         if (rc)
3235                 goto error_free;
3236
3237         rc = update_pf_resource_max(bp);
3238         if (rc)
3239                 goto error_free;
3240
3241         return rc;
3242
3243 error_free:
3244         bnxt_hwrm_func_buf_unrgtr(bp);
3245         return rc;
3246 }
3247
3248 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3249 {
3250         struct hwrm_func_cfg_input req = {0};
3251         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3252         int rc;
3253
3254         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3255
3256         req.fid = rte_cpu_to_le_16(0xffff);
3257         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3258         req.evb_mode = bp->pf.evb_mode;
3259
3260         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3261         HWRM_CHECK_RESULT();
3262         HWRM_UNLOCK();
3263
3264         return rc;
3265 }
3266
3267 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3268                                 uint8_t tunnel_type)
3269 {
3270         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3271         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3272         int rc = 0;
3273
3274         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3275         req.tunnel_type = tunnel_type;
3276         req.tunnel_dst_port_val = port;
3277         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3278         HWRM_CHECK_RESULT();
3279
3280         switch (tunnel_type) {
3281         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3282                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3283                 bp->vxlan_port = port;
3284                 break;
3285         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3286                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3287                 bp->geneve_port = port;
3288                 break;
3289         default:
3290                 break;
3291         }
3292
3293         HWRM_UNLOCK();
3294
3295         return rc;
3296 }
3297
3298 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3299                                 uint8_t tunnel_type)
3300 {
3301         struct hwrm_tunnel_dst_port_free_input req = {0};
3302         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3303         int rc = 0;
3304
3305         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3306
3307         req.tunnel_type = tunnel_type;
3308         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3309         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3310
3311         HWRM_CHECK_RESULT();
3312         HWRM_UNLOCK();
3313
3314         return rc;
3315 }
3316
3317 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3318                                         uint32_t flags)
3319 {
3320         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3321         struct hwrm_func_cfg_input req = {0};
3322         int rc;
3323
3324         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3325
3326         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3327         req.flags = rte_cpu_to_le_32(flags);
3328         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3329
3330         HWRM_CHECK_RESULT();
3331         HWRM_UNLOCK();
3332
3333         return rc;
3334 }
3335
3336 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3337 {
3338         uint32_t *flag = flagp;
3339
3340         vnic->flags = *flag;
3341 }
3342
3343 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3344 {
3345         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3346 }
3347
3348 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3349 {
3350         int rc = 0;
3351         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3352         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3353
3354         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3355
3356         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3357         req.req_buf_page_size = rte_cpu_to_le_16(
3358                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3359         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3360         req.req_buf_page_addr0 =
3361                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3362         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3363                 PMD_DRV_LOG(ERR,
3364                         "unable to map buffer address to physical memory\n");
3365                 return -ENOMEM;
3366         }
3367
3368         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3369
3370         HWRM_CHECK_RESULT();
3371         HWRM_UNLOCK();
3372
3373         return rc;
3374 }
3375
3376 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3377 {
3378         int rc = 0;
3379         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3380         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3381
3382         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3383                 return 0;
3384
3385         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3386
3387         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3388
3389         HWRM_CHECK_RESULT();
3390         HWRM_UNLOCK();
3391
3392         return rc;
3393 }
3394
3395 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3396 {
3397         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3398         struct hwrm_func_cfg_input req = {0};
3399         int rc;
3400
3401         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3402
3403         req.fid = rte_cpu_to_le_16(0xffff);
3404         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3405         req.enables = rte_cpu_to_le_32(
3406                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3407         req.async_event_cr = rte_cpu_to_le_16(
3408                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3409         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3410
3411         HWRM_CHECK_RESULT();
3412         HWRM_UNLOCK();
3413
3414         return rc;
3415 }
3416
3417 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3418 {
3419         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3420         struct hwrm_func_vf_cfg_input req = {0};
3421         int rc;
3422
3423         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3424
3425         req.enables = rte_cpu_to_le_32(
3426                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3427         req.async_event_cr = rte_cpu_to_le_16(
3428                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3429         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3430
3431         HWRM_CHECK_RESULT();
3432         HWRM_UNLOCK();
3433
3434         return rc;
3435 }
3436
3437 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3438 {
3439         struct hwrm_func_cfg_input req = {0};
3440         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3441         uint16_t dflt_vlan, fid;
3442         uint32_t func_cfg_flags;
3443         int rc = 0;
3444
3445         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3446
3447         if (is_vf) {
3448                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3449                 fid = bp->pf.vf_info[vf].fid;
3450                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3451         } else {
3452                 fid = rte_cpu_to_le_16(0xffff);
3453                 func_cfg_flags = bp->pf.func_cfg_flags;
3454                 dflt_vlan = bp->vlan;
3455         }
3456
3457         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3458         req.fid = rte_cpu_to_le_16(fid);
3459         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3460         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3461
3462         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3463
3464         HWRM_CHECK_RESULT();
3465         HWRM_UNLOCK();
3466
3467         return rc;
3468 }
3469
3470 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3471                         uint16_t max_bw, uint16_t enables)
3472 {
3473         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3474         struct hwrm_func_cfg_input req = {0};
3475         int rc;
3476
3477         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3478
3479         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3480         req.enables |= rte_cpu_to_le_32(enables);
3481         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3482         req.max_bw = rte_cpu_to_le_32(max_bw);
3483         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3484
3485         HWRM_CHECK_RESULT();
3486         HWRM_UNLOCK();
3487
3488         return rc;
3489 }
3490
3491 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3492 {
3493         struct hwrm_func_cfg_input req = {0};
3494         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3495         int rc = 0;
3496
3497         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3498
3499         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3500         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3501         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3502         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3503
3504         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3505
3506         HWRM_CHECK_RESULT();
3507         HWRM_UNLOCK();
3508
3509         return rc;
3510 }
3511
3512 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3513 {
3514         int rc;
3515
3516         if (BNXT_PF(bp))
3517                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3518         else
3519                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3520
3521         return rc;
3522 }
3523
3524 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3525                               void *encaped, size_t ec_size)
3526 {
3527         int rc = 0;
3528         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3529         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3530
3531         if (ec_size > sizeof(req.encap_request))
3532                 return -1;
3533
3534         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3535
3536         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3537         memcpy(req.encap_request, encaped, ec_size);
3538
3539         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3540
3541         HWRM_CHECK_RESULT();
3542         HWRM_UNLOCK();
3543
3544         return rc;
3545 }
3546
3547 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3548                                        struct rte_ether_addr *mac)
3549 {
3550         struct hwrm_func_qcfg_input req = {0};
3551         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3552         int rc;
3553
3554         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3555
3556         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3557         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3558
3559         HWRM_CHECK_RESULT();
3560
3561         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3562
3563         HWRM_UNLOCK();
3564
3565         return rc;
3566 }
3567
3568 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3569                             void *encaped, size_t ec_size)
3570 {
3571         int rc = 0;
3572         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3573         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3574
3575         if (ec_size > sizeof(req.encap_request))
3576                 return -1;
3577
3578         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3579
3580         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3581         memcpy(req.encap_request, encaped, ec_size);
3582
3583         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3584
3585         HWRM_CHECK_RESULT();
3586         HWRM_UNLOCK();
3587
3588         return rc;
3589 }
3590
3591 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3592                          struct rte_eth_stats *stats, uint8_t rx)
3593 {
3594         int rc = 0;
3595         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3596         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3597
3598         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3599
3600         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3601
3602         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3603
3604         HWRM_CHECK_RESULT();
3605
3606         if (rx) {
3607                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3608                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3609                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3610                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3611                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3612                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3613                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3614                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3615         } else {
3616                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3617                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3618                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3619                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3620                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3621                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3622         }
3623
3624         HWRM_UNLOCK();
3625
3626         return rc;
3627 }
3628
3629 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3630 {
3631         struct hwrm_port_qstats_input req = {0};
3632         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3633         struct bnxt_pf_info *pf = &bp->pf;
3634         int rc;
3635
3636         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3637
3638         req.port_id = rte_cpu_to_le_16(pf->port_id);
3639         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3640         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3641         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3642
3643         HWRM_CHECK_RESULT();
3644         HWRM_UNLOCK();
3645
3646         return rc;
3647 }
3648
3649 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3650 {
3651         struct hwrm_port_clr_stats_input req = {0};
3652         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3653         struct bnxt_pf_info *pf = &bp->pf;
3654         int rc;
3655
3656         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3657         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3658             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3659                 return 0;
3660
3661         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3662
3663         req.port_id = rte_cpu_to_le_16(pf->port_id);
3664         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3665
3666         HWRM_CHECK_RESULT();
3667         HWRM_UNLOCK();
3668
3669         return rc;
3670 }
3671
3672 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3673 {
3674         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3675         struct hwrm_port_led_qcaps_input req = {0};
3676         int rc;
3677
3678         if (BNXT_VF(bp))
3679                 return 0;
3680
3681         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3682         req.port_id = bp->pf.port_id;
3683         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3684
3685         HWRM_CHECK_RESULT();
3686
3687         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3688                 unsigned int i;
3689
3690                 bp->num_leds = resp->num_leds;
3691                 memcpy(bp->leds, &resp->led0_id,
3692                         sizeof(bp->leds[0]) * bp->num_leds);
3693                 for (i = 0; i < bp->num_leds; i++) {
3694                         struct bnxt_led_info *led = &bp->leds[i];
3695
3696                         uint16_t caps = led->led_state_caps;
3697
3698                         if (!led->led_group_id ||
3699                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3700                                 bp->num_leds = 0;
3701                                 break;
3702                         }
3703                 }
3704         }
3705
3706         HWRM_UNLOCK();
3707
3708         return rc;
3709 }
3710
3711 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3712 {
3713         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3714         struct hwrm_port_led_cfg_input req = {0};
3715         struct bnxt_led_cfg *led_cfg;
3716         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3717         uint16_t duration = 0;
3718         int rc, i;
3719
3720         if (!bp->num_leds || BNXT_VF(bp))
3721                 return -EOPNOTSUPP;
3722
3723         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3724
3725         if (led_on) {
3726                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3727                 duration = rte_cpu_to_le_16(500);
3728         }
3729         req.port_id = bp->pf.port_id;
3730         req.num_leds = bp->num_leds;
3731         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3732         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3733                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3734                 led_cfg->led_id = bp->leds[i].led_id;
3735                 led_cfg->led_state = led_state;
3736                 led_cfg->led_blink_on = duration;
3737                 led_cfg->led_blink_off = duration;
3738                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3739         }
3740
3741         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3742
3743         HWRM_CHECK_RESULT();
3744         HWRM_UNLOCK();
3745
3746         return rc;
3747 }
3748
3749 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3750                                uint32_t *length)
3751 {
3752         int rc;
3753         struct hwrm_nvm_get_dir_info_input req = {0};
3754         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3755
3756         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3757
3758         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3759
3760         HWRM_CHECK_RESULT();
3761
3762         *entries = rte_le_to_cpu_32(resp->entries);
3763         *length = rte_le_to_cpu_32(resp->entry_length);
3764
3765         HWRM_UNLOCK();
3766         return rc;
3767 }
3768
3769 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3770 {
3771         int rc;
3772         uint32_t dir_entries;
3773         uint32_t entry_length;
3774         uint8_t *buf;
3775         size_t buflen;
3776         rte_iova_t dma_handle;
3777         struct hwrm_nvm_get_dir_entries_input req = {0};
3778         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3779
3780         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3781         if (rc != 0)
3782                 return rc;
3783
3784         *data++ = dir_entries;
3785         *data++ = entry_length;
3786         len -= 2;
3787         memset(data, 0xff, len);
3788
3789         buflen = dir_entries * entry_length;
3790         buf = rte_malloc("nvm_dir", buflen, 0);
3791         rte_mem_lock_page(buf);
3792         if (buf == NULL)
3793                 return -ENOMEM;
3794         dma_handle = rte_mem_virt2iova(buf);
3795         if (dma_handle == RTE_BAD_IOVA) {
3796                 PMD_DRV_LOG(ERR,
3797                         "unable to map response address to physical memory\n");
3798                 return -ENOMEM;
3799         }
3800         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3801         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3802         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3803
3804         if (rc == 0)
3805                 memcpy(data, buf, len > buflen ? buflen : len);
3806
3807         rte_free(buf);
3808         HWRM_CHECK_RESULT();
3809         HWRM_UNLOCK();
3810
3811         return rc;
3812 }
3813
3814 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3815                              uint32_t offset, uint32_t length,
3816                              uint8_t *data)
3817 {
3818         int rc;
3819         uint8_t *buf;
3820         rte_iova_t dma_handle;
3821         struct hwrm_nvm_read_input req = {0};
3822         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3823
3824         buf = rte_malloc("nvm_item", length, 0);
3825         rte_mem_lock_page(buf);
3826         if (!buf)
3827                 return -ENOMEM;
3828
3829         dma_handle = rte_mem_virt2iova(buf);
3830         if (dma_handle == RTE_BAD_IOVA) {
3831                 PMD_DRV_LOG(ERR,
3832                         "unable to map response address to physical memory\n");
3833                 return -ENOMEM;
3834         }
3835         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3836         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3837         req.dir_idx = rte_cpu_to_le_16(index);
3838         req.offset = rte_cpu_to_le_32(offset);
3839         req.len = rte_cpu_to_le_32(length);
3840         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3841         if (rc == 0)
3842                 memcpy(data, buf, length);
3843
3844         rte_free(buf);
3845         HWRM_CHECK_RESULT();
3846         HWRM_UNLOCK();
3847
3848         return rc;
3849 }
3850
3851 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3852 {
3853         int rc;
3854         struct hwrm_nvm_erase_dir_entry_input req = {0};
3855         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3856
3857         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3858         req.dir_idx = rte_cpu_to_le_16(index);
3859         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3860         HWRM_CHECK_RESULT();
3861         HWRM_UNLOCK();
3862
3863         return rc;
3864 }
3865
3866
3867 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3868                           uint16_t dir_ordinal, uint16_t dir_ext,
3869                           uint16_t dir_attr, const uint8_t *data,
3870                           size_t data_len)
3871 {
3872         int rc;
3873         struct hwrm_nvm_write_input req = {0};
3874         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3875         rte_iova_t dma_handle;
3876         uint8_t *buf;
3877
3878         buf = rte_malloc("nvm_write", data_len, 0);
3879         rte_mem_lock_page(buf);
3880         if (!buf)
3881                 return -ENOMEM;
3882
3883         dma_handle = rte_mem_virt2iova(buf);
3884         if (dma_handle == RTE_BAD_IOVA) {
3885                 PMD_DRV_LOG(ERR,
3886                         "unable to map response address to physical memory\n");
3887                 return -ENOMEM;
3888         }
3889         memcpy(buf, data, data_len);
3890
3891         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3892
3893         req.dir_type = rte_cpu_to_le_16(dir_type);
3894         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3895         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3896         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3897         req.dir_data_length = rte_cpu_to_le_32(data_len);
3898         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3899
3900         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3901
3902         rte_free(buf);
3903         HWRM_CHECK_RESULT();
3904         HWRM_UNLOCK();
3905
3906         return rc;
3907 }
3908
3909 static void
3910 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3911 {
3912         uint32_t *count = cbdata;
3913
3914         *count = *count + 1;
3915 }
3916
3917 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3918                                      struct bnxt_vnic_info *vnic __rte_unused)
3919 {
3920         return 0;
3921 }
3922
3923 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3924 {
3925         uint32_t count = 0;
3926
3927         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3928             &count, bnxt_vnic_count_hwrm_stub);
3929
3930         return count;
3931 }
3932
3933 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3934                                         uint16_t *vnic_ids)
3935 {
3936         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3937         struct hwrm_func_vf_vnic_ids_query_output *resp =
3938                                                 bp->hwrm_cmd_resp_addr;
3939         int rc;
3940
3941         /* First query all VNIC ids */
3942         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3943
3944         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3945         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3946         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3947
3948         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3949                 HWRM_UNLOCK();
3950                 PMD_DRV_LOG(ERR,
3951                 "unable to map VNIC ID table address to physical memory\n");
3952                 return -ENOMEM;
3953         }
3954         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3955         HWRM_CHECK_RESULT();
3956         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3957
3958         HWRM_UNLOCK();
3959
3960         return rc;
3961 }
3962
3963 /*
3964  * This function queries the VNIC IDs  for a specified VF. It then calls
3965  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3966  * Then it calls the hwrm_cb function to program this new vnic configuration.
3967  */
3968 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3969         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3970         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3971 {
3972         struct bnxt_vnic_info vnic;
3973         int rc = 0;
3974         int i, num_vnic_ids;
3975         uint16_t *vnic_ids;
3976         size_t vnic_id_sz;
3977         size_t sz;
3978
3979         /* First query all VNIC ids */
3980         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3981         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3982                         RTE_CACHE_LINE_SIZE);
3983         if (vnic_ids == NULL)
3984                 return -ENOMEM;
3985
3986         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3987                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3988
3989         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3990
3991         if (num_vnic_ids < 0)
3992                 return num_vnic_ids;
3993
3994         /* Retrieve VNIC, update bd_stall then update */
3995
3996         for (i = 0; i < num_vnic_ids; i++) {
3997                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3998                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3999                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4000                 if (rc)
4001                         break;
4002                 if (vnic.mru <= 4)      /* Indicates unallocated */
4003                         continue;
4004
4005                 vnic_cb(&vnic, cbdata);
4006
4007                 rc = hwrm_cb(bp, &vnic);
4008                 if (rc)
4009                         break;
4010         }
4011
4012         rte_free(vnic_ids);
4013
4014         return rc;
4015 }
4016
4017 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4018                                               bool on)
4019 {
4020         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4021         struct hwrm_func_cfg_input req = {0};
4022         int rc;
4023
4024         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4025
4026         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4027         req.enables |= rte_cpu_to_le_32(
4028                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4029         req.vlan_antispoof_mode = on ?
4030                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4031                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4032         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4033
4034         HWRM_CHECK_RESULT();
4035         HWRM_UNLOCK();
4036
4037         return rc;
4038 }
4039
4040 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4041 {
4042         struct bnxt_vnic_info vnic;
4043         uint16_t *vnic_ids;
4044         size_t vnic_id_sz;
4045         int num_vnic_ids, i;
4046         size_t sz;
4047         int rc;
4048
4049         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4050         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4051                         RTE_CACHE_LINE_SIZE);
4052         if (vnic_ids == NULL)
4053                 return -ENOMEM;
4054
4055         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4056                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4057
4058         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4059         if (rc <= 0)
4060                 goto exit;
4061         num_vnic_ids = rc;
4062
4063         /*
4064          * Loop through to find the default VNIC ID.
4065          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4066          * by sending the hwrm_func_qcfg command to the firmware.
4067          */
4068         for (i = 0; i < num_vnic_ids; i++) {
4069                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4070                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4071                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4072                                         bp->pf.first_vf_id + vf);
4073                 if (rc)
4074                         goto exit;
4075                 if (vnic.func_default) {
4076                         rte_free(vnic_ids);
4077                         return vnic.fw_vnic_id;
4078                 }
4079         }
4080         /* Could not find a default VNIC. */
4081         PMD_DRV_LOG(ERR, "No default VNIC\n");
4082 exit:
4083         rte_free(vnic_ids);
4084         return rc;
4085 }
4086
4087 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4088                          uint16_t dst_id,
4089                          struct bnxt_filter_info *filter)
4090 {
4091         int rc = 0;
4092         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4093         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4094         uint32_t enables = 0;
4095
4096         if (filter->fw_em_filter_id != UINT64_MAX)
4097                 bnxt_hwrm_clear_em_filter(bp, filter);
4098
4099         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4100
4101         req.flags = rte_cpu_to_le_32(filter->flags);
4102
4103         enables = filter->enables |
4104               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4105         req.dst_id = rte_cpu_to_le_16(dst_id);
4106
4107         if (filter->ip_addr_type) {
4108                 req.ip_addr_type = filter->ip_addr_type;
4109                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4110         }
4111         if (enables &
4112             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4113                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4114         if (enables &
4115             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4116                 memcpy(req.src_macaddr, filter->src_macaddr,
4117                        RTE_ETHER_ADDR_LEN);
4118         if (enables &
4119             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4120                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4121                        RTE_ETHER_ADDR_LEN);
4122         if (enables &
4123             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4124                 req.ovlan_vid = filter->l2_ovlan;
4125         if (enables &
4126             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4127                 req.ivlan_vid = filter->l2_ivlan;
4128         if (enables &
4129             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4130                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4131         if (enables &
4132             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4133                 req.ip_protocol = filter->ip_protocol;
4134         if (enables &
4135             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4136                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4137         if (enables &
4138             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4139                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4140         if (enables &
4141             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4142                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4143         if (enables &
4144             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4145                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4146         if (enables &
4147             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4148                 req.mirror_vnic_id = filter->mirror_vnic_id;
4149
4150         req.enables = rte_cpu_to_le_32(enables);
4151
4152         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4153
4154         HWRM_CHECK_RESULT();
4155
4156         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4157         HWRM_UNLOCK();
4158
4159         return rc;
4160 }
4161
4162 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4163 {
4164         int rc = 0;
4165         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4166         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4167
4168         if (filter->fw_em_filter_id == UINT64_MAX)
4169                 return 0;
4170
4171         PMD_DRV_LOG(ERR, "Clear EM filter\n");
4172         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4173
4174         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4175
4176         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4177
4178         HWRM_CHECK_RESULT();
4179         HWRM_UNLOCK();
4180
4181         filter->fw_em_filter_id = UINT64_MAX;
4182         filter->fw_l2_filter_id = UINT64_MAX;
4183
4184         return 0;
4185 }
4186
4187 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4188                          uint16_t dst_id,
4189                          struct bnxt_filter_info *filter)
4190 {
4191         int rc = 0;
4192         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4193         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4194                                                 bp->hwrm_cmd_resp_addr;
4195         uint32_t enables = 0;
4196
4197         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4198                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4199
4200         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4201
4202         req.flags = rte_cpu_to_le_32(filter->flags);
4203
4204         enables = filter->enables |
4205               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4206         req.dst_id = rte_cpu_to_le_16(dst_id);
4207
4208         if (filter->ip_addr_type) {
4209                 req.ip_addr_type = filter->ip_addr_type;
4210                 enables |=
4211                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4212         }
4213         if (enables &
4214             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4215                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4216         if (enables &
4217             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4218                 memcpy(req.src_macaddr, filter->src_macaddr,
4219                        RTE_ETHER_ADDR_LEN);
4220         if (enables &
4221             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4222                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4223         if (enables &
4224             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4225                 req.ip_protocol = filter->ip_protocol;
4226         if (enables &
4227             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4228                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4229         if (enables &
4230             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4231                 req.src_ipaddr_mask[0] =
4232                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4233         if (enables &
4234             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4235                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4236         if (enables &
4237             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4238                 req.dst_ipaddr_mask[0] =
4239                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4240         if (enables &
4241             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4242                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4243         if (enables &
4244             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4245                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4246         if (enables &
4247             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4248                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4249         if (enables &
4250             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4251                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4252         if (enables &
4253             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4254                 req.mirror_vnic_id = filter->mirror_vnic_id;
4255
4256         req.enables = rte_cpu_to_le_32(enables);
4257
4258         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4259
4260         HWRM_CHECK_RESULT();
4261
4262         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4263         HWRM_UNLOCK();
4264
4265         return rc;
4266 }
4267
4268 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4269                                 struct bnxt_filter_info *filter)
4270 {
4271         int rc = 0;
4272         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4273         struct hwrm_cfa_ntuple_filter_free_output *resp =
4274                                                 bp->hwrm_cmd_resp_addr;
4275
4276         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4277                 return 0;
4278
4279         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4280
4281         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4282
4283         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4284
4285         HWRM_CHECK_RESULT();
4286         HWRM_UNLOCK();
4287
4288         filter->fw_ntuple_filter_id = UINT64_MAX;
4289
4290         return 0;
4291 }
4292
4293 static int
4294 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4295 {
4296         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4297         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4298         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4299         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4300         uint16_t *ring_tbl = vnic->rss_table;
4301         int nr_ctxs = vnic->num_lb_ctxts;
4302         int max_rings = bp->rx_nr_rings;
4303         int i, j, k, cnt;
4304         int rc = 0;
4305
4306         for (i = 0, k = 0; i < nr_ctxs; i++) {
4307                 struct bnxt_rx_ring_info *rxr;
4308                 struct bnxt_cp_ring_info *cpr;
4309
4310                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4311
4312                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4313                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4314                 req.hash_mode_flags = vnic->hash_mode;
4315
4316                 req.ring_grp_tbl_addr =
4317                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4318                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4319                                      2 * sizeof(*ring_tbl));
4320                 req.hash_key_tbl_addr =
4321                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4322
4323                 req.ring_table_pair_index = i;
4324                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4325
4326                 for (j = 0; j < 64; j++) {
4327                         uint16_t ring_id;
4328
4329                         /* Find next active ring. */
4330                         for (cnt = 0; cnt < max_rings; cnt++) {
4331                                 if (rx_queue_state[k] !=
4332                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4333                                         break;
4334                                 if (++k == max_rings)
4335                                         k = 0;
4336                         }
4337
4338                         /* Return if no rings are active. */
4339                         if (cnt == max_rings)
4340                                 return 0;
4341
4342                         /* Add rx/cp ring pair to RSS table. */
4343                         rxr = rxqs[k]->rx_ring;
4344                         cpr = rxqs[k]->cp_ring;
4345
4346                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4347                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4348                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4349                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4350
4351                         if (++k == max_rings)
4352                                 k = 0;
4353                 }
4354                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4355                                             BNXT_USE_CHIMP_MB);
4356
4357                 HWRM_CHECK_RESULT();
4358                 HWRM_UNLOCK();
4359         }
4360
4361         return rc;
4362 }
4363
4364 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4365 {
4366         unsigned int rss_idx, fw_idx, i;
4367
4368         if (!(vnic->rss_table && vnic->hash_type))
4369                 return 0;
4370
4371         if (BNXT_CHIP_THOR(bp))
4372                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4373
4374         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4375                 return 0;
4376
4377         if (vnic->rss_table && vnic->hash_type) {
4378                 /*
4379                  * Fill the RSS hash & redirection table with
4380                  * ring group ids for all VNICs
4381                  */
4382                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4383                         rss_idx++, fw_idx++) {
4384                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4385                                 fw_idx %= bp->rx_cp_nr_rings;
4386                                 if (vnic->fw_grp_ids[fw_idx] !=
4387                                     INVALID_HW_RING_ID)
4388                                         break;
4389                                 fw_idx++;
4390                         }
4391                         if (i == bp->rx_cp_nr_rings)
4392                                 return 0;
4393                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4394                 }
4395                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4396         }
4397
4398         return 0;
4399 }
4400
4401 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4402         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4403 {
4404         uint16_t flags;
4405
4406         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4407
4408         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4409         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4410
4411         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4412         req->num_cmpl_dma_aggr_during_int =
4413                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4414
4415         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4416
4417         /* min timer set to 1/2 of interrupt timer */
4418         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4419
4420         /* buf timer set to 1/4 of interrupt timer */
4421         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4422
4423         req->cmpl_aggr_dma_tmr_during_int =
4424                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4425
4426         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4427                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4428         req->flags = rte_cpu_to_le_16(flags);
4429 }
4430
4431 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4432                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4433 {
4434         struct hwrm_ring_aggint_qcaps_input req = {0};
4435         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4436         uint32_t enables;
4437         uint16_t flags;
4438         int rc;
4439
4440         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4441         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4442         HWRM_CHECK_RESULT();
4443
4444         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4445         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4446
4447         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4448                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4449         agg_req->flags = rte_cpu_to_le_16(flags);
4450         enables =
4451          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4452          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4453         agg_req->enables = rte_cpu_to_le_32(enables);
4454
4455         HWRM_UNLOCK();
4456         return rc;
4457 }
4458
4459 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4460                         struct bnxt_coal *coal, uint16_t ring_id)
4461 {
4462         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4463         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4464                                                 bp->hwrm_cmd_resp_addr;
4465         int rc;
4466
4467         /* Set ring coalesce parameters only for 100G NICs */
4468         if (BNXT_CHIP_THOR(bp)) {
4469                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4470                         return -1;
4471         } else if (bnxt_stratus_device(bp)) {
4472                 bnxt_hwrm_set_coal_params(coal, &req);
4473         } else {
4474                 return 0;
4475         }
4476
4477         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4478         req.ring_id = rte_cpu_to_le_16(ring_id);
4479         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4480         HWRM_CHECK_RESULT();
4481         HWRM_UNLOCK();
4482         return 0;
4483 }
4484
4485 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4486 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4487 {
4488         struct hwrm_func_backing_store_qcaps_input req = {0};
4489         struct hwrm_func_backing_store_qcaps_output *resp =
4490                 bp->hwrm_cmd_resp_addr;
4491         struct bnxt_ctx_pg_info *ctx_pg;
4492         struct bnxt_ctx_mem_info *ctx;
4493         int total_alloc_len;
4494         int rc, i;
4495
4496         if (!BNXT_CHIP_THOR(bp) ||
4497             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4498             BNXT_VF(bp) ||
4499             bp->ctx)
4500                 return 0;
4501
4502         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4503         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4504         HWRM_CHECK_RESULT_SILENT();
4505
4506         total_alloc_len = sizeof(*ctx);
4507         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4508                           RTE_CACHE_LINE_SIZE);
4509         if (!ctx) {
4510                 rc = -ENOMEM;
4511                 goto ctx_err;
4512         }
4513
4514         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4515                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4516                             RTE_CACHE_LINE_SIZE);
4517         if (!ctx_pg) {
4518                 rc = -ENOMEM;
4519                 goto ctx_err;
4520         }
4521         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4522                 ctx->tqm_mem[i] = ctx_pg;
4523
4524         bp->ctx = ctx;
4525         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4526         ctx->qp_min_qp1_entries =
4527                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4528         ctx->qp_max_l2_entries =
4529                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4530         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4531         ctx->srq_max_l2_entries =
4532                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4533         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4534         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4535         ctx->cq_max_l2_entries =
4536                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4537         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4538         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4539         ctx->vnic_max_vnic_entries =
4540                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4541         ctx->vnic_max_ring_table_entries =
4542                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4543         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4544         ctx->stat_max_entries =
4545                 rte_le_to_cpu_32(resp->stat_max_entries);
4546         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4547         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4548         ctx->tqm_min_entries_per_ring =
4549                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4550         ctx->tqm_max_entries_per_ring =
4551                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4552         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4553         if (!ctx->tqm_entries_multiple)
4554                 ctx->tqm_entries_multiple = 1;
4555         ctx->mrav_max_entries =
4556                 rte_le_to_cpu_32(resp->mrav_max_entries);
4557         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4558         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4559         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4560 ctx_err:
4561         HWRM_UNLOCK();
4562         return rc;
4563 }
4564
4565 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4566 {
4567         struct hwrm_func_backing_store_cfg_input req = {0};
4568         struct hwrm_func_backing_store_cfg_output *resp =
4569                 bp->hwrm_cmd_resp_addr;
4570         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4571         struct bnxt_ctx_pg_info *ctx_pg;
4572         uint32_t *num_entries;
4573         uint64_t *pg_dir;
4574         uint8_t *pg_attr;
4575         uint32_t ena;
4576         int i, rc;
4577
4578         if (!ctx)
4579                 return 0;
4580
4581         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4582         req.enables = rte_cpu_to_le_32(enables);
4583
4584         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4585                 ctx_pg = &ctx->qp_mem;
4586                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4587                 req.qp_num_qp1_entries =
4588                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4589                 req.qp_num_l2_entries =
4590                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4591                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4592                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4593                                       &req.qpc_pg_size_qpc_lvl,
4594                                       &req.qpc_page_dir);
4595         }
4596
4597         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4598                 ctx_pg = &ctx->srq_mem;
4599                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4600                 req.srq_num_l2_entries =
4601                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4602                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4603                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4604                                       &req.srq_pg_size_srq_lvl,
4605                                       &req.srq_page_dir);
4606         }
4607
4608         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4609                 ctx_pg = &ctx->cq_mem;
4610                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4611                 req.cq_num_l2_entries =
4612                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4613                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4614                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4615                                       &req.cq_pg_size_cq_lvl,
4616                                       &req.cq_page_dir);
4617         }
4618
4619         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4620                 ctx_pg = &ctx->vnic_mem;
4621                 req.vnic_num_vnic_entries =
4622                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4623                 req.vnic_num_ring_table_entries =
4624                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4625                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4626                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4627                                       &req.vnic_pg_size_vnic_lvl,
4628                                       &req.vnic_page_dir);
4629         }
4630
4631         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4632                 ctx_pg = &ctx->stat_mem;
4633                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4634                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4635                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4636                                       &req.stat_pg_size_stat_lvl,
4637                                       &req.stat_page_dir);
4638         }
4639
4640         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4641         num_entries = &req.tqm_sp_num_entries;
4642         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4643         pg_dir = &req.tqm_sp_page_dir;
4644         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4645         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4646                 if (!(enables & ena))
4647                         continue;
4648
4649                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4650
4651                 ctx_pg = ctx->tqm_mem[i];
4652                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4653                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4654         }
4655
4656         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4657         HWRM_CHECK_RESULT();
4658         HWRM_UNLOCK();
4659
4660         return rc;
4661 }
4662
4663 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4664 {
4665         struct hwrm_port_qstats_ext_input req = {0};
4666         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4667         struct bnxt_pf_info *pf = &bp->pf;
4668         int rc;
4669
4670         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4671               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4672                 return 0;
4673
4674         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4675
4676         req.port_id = rte_cpu_to_le_16(pf->port_id);
4677         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4678                 req.tx_stat_host_addr =
4679                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4680                 req.tx_stat_size =
4681                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4682         }
4683         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4684                 req.rx_stat_host_addr =
4685                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4686                 req.rx_stat_size =
4687                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4688         }
4689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4690
4691         if (rc) {
4692                 bp->fw_rx_port_stats_ext_size = 0;
4693                 bp->fw_tx_port_stats_ext_size = 0;
4694         } else {
4695                 bp->fw_rx_port_stats_ext_size =
4696                         rte_le_to_cpu_16(resp->rx_stat_size);
4697                 bp->fw_tx_port_stats_ext_size =
4698                         rte_le_to_cpu_16(resp->tx_stat_size);
4699         }
4700
4701         HWRM_CHECK_RESULT();
4702         HWRM_UNLOCK();
4703
4704         return rc;
4705 }
4706
4707 int
4708 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4709 {
4710         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4711         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4712                 bp->hwrm_cmd_resp_addr;
4713         int rc = 0;
4714
4715         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4716         req.tunnel_type = type;
4717         req.dest_fid = bp->fw_fid;
4718         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4719         HWRM_CHECK_RESULT();
4720
4721         HWRM_UNLOCK();
4722
4723         return rc;
4724 }
4725
4726 int
4727 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4728 {
4729         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4730         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4731                 bp->hwrm_cmd_resp_addr;
4732         int rc = 0;
4733
4734         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4735         req.tunnel_type = type;
4736         req.dest_fid = bp->fw_fid;
4737         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4738         HWRM_CHECK_RESULT();
4739
4740         HWRM_UNLOCK();
4741
4742         return rc;
4743 }
4744
4745 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4746 {
4747         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4748         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4749                 bp->hwrm_cmd_resp_addr;
4750         int rc = 0;
4751
4752         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4753         req.src_fid = bp->fw_fid;
4754         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4755         HWRM_CHECK_RESULT();
4756
4757         if (type)
4758                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4759
4760         HWRM_UNLOCK();
4761
4762         return rc;
4763 }
4764
4765 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4766                                    uint16_t *dst_fid)
4767 {
4768         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4769         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4770                 bp->hwrm_cmd_resp_addr;
4771         int rc = 0;
4772
4773         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4774         req.src_fid = bp->fw_fid;
4775         req.tunnel_type = tun_type;
4776         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4777         HWRM_CHECK_RESULT();
4778
4779         if (dst_fid)
4780                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4781
4782         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4783
4784         HWRM_UNLOCK();
4785
4786         return rc;
4787 }
4788
4789 int bnxt_hwrm_set_mac(struct bnxt *bp)
4790 {
4791         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4792         struct hwrm_func_vf_cfg_input req = {0};
4793         int rc = 0;
4794
4795         if (!BNXT_VF(bp))
4796                 return 0;
4797
4798         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4799
4800         req.enables =
4801                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4802         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4803
4804         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4805
4806         HWRM_CHECK_RESULT();
4807
4808         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4809         HWRM_UNLOCK();
4810
4811         return rc;
4812 }
4813
4814 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4815 {
4816         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4817         struct hwrm_func_drv_if_change_input req = {0};
4818         uint32_t flags;
4819         int rc;
4820
4821         if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4822                 return 0;
4823
4824         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4825          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4826          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4827          */
4828         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4829                 return 0;
4830
4831         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4832
4833         if (up)
4834                 req.flags =
4835                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4836
4837         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4838
4839         HWRM_CHECK_RESULT();
4840         flags = rte_le_to_cpu_32(resp->flags);
4841         HWRM_UNLOCK();
4842
4843         if (!up)
4844                 return 0;
4845
4846         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4847                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4848                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4849         }
4850
4851         return 0;
4852 }
4853
4854 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4855 {
4856         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4857         struct bnxt_error_recovery_info *info = bp->recovery_info;
4858         struct hwrm_error_recovery_qcfg_input req = {0};
4859         uint32_t flags = 0;
4860         unsigned int i;
4861         int rc;
4862
4863         /* Older FW does not have error recovery support */
4864         if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4865                 return 0;
4866
4867         if (!info) {
4868                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4869                                    sizeof(*info), 0);
4870                 bp->recovery_info = info;
4871                 if (info == NULL)
4872                         return -ENOMEM;
4873         } else {
4874                 memset(info, 0, sizeof(*info));
4875         }
4876
4877         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4878
4879         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4880
4881         HWRM_CHECK_RESULT();
4882
4883         flags = rte_le_to_cpu_32(resp->flags);
4884         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4885                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4886         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4887                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4888
4889         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4890             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4891                 rc = -EINVAL;
4892                 goto err;
4893         }
4894
4895         /* FW returned values are in units of 100msec */
4896         info->driver_polling_freq =
4897                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4898         info->master_func_wait_period =
4899                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4900         info->normal_func_wait_period =
4901                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4902         info->master_func_wait_period_after_reset =
4903                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4904         info->max_bailout_time_after_reset =
4905                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4906         info->status_regs[BNXT_FW_STATUS_REG] =
4907                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4908         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4909                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4910         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4911                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4912         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4913                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4914         info->reg_array_cnt =
4915                 rte_le_to_cpu_32(resp->reg_array_cnt);
4916
4917         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4918                 rc = -EINVAL;
4919                 goto err;
4920         }
4921
4922         for (i = 0; i < info->reg_array_cnt; i++) {
4923                 info->reset_reg[i] =
4924                         rte_le_to_cpu_32(resp->reset_reg[i]);
4925                 info->reset_reg_val[i] =
4926                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4927                 info->delay_after_reset[i] =
4928                         resp->delay_after_reset[i];
4929         }
4930 err:
4931         HWRM_UNLOCK();
4932
4933         /* Map the FW status registers */
4934         if (!rc)
4935                 rc = bnxt_map_fw_health_status_regs(bp);
4936
4937         if (rc) {
4938                 rte_free(bp->recovery_info);
4939                 bp->recovery_info = NULL;
4940         }
4941         return rc;
4942 }
4943
4944 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4945 {
4946         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4947         struct hwrm_fw_reset_input req = {0};
4948         int rc;
4949
4950         if (!BNXT_PF(bp))
4951                 return -EOPNOTSUPP;
4952
4953         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4954
4955         req.embedded_proc_type =
4956                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4957         req.selfrst_status =
4958                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4959         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4960
4961         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4962                                     BNXT_USE_KONG(bp));
4963
4964         HWRM_CHECK_RESULT();
4965         HWRM_UNLOCK();
4966
4967         return rc;
4968 }
4969
4970 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4971 {
4972         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4973         struct hwrm_port_ts_query_input req = {0};
4974         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4975         uint32_t flags = 0;
4976         int rc;
4977
4978         if (!ptp)
4979                 return 0;
4980
4981         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4982
4983         switch (path) {
4984         case BNXT_PTP_FLAGS_PATH_TX:
4985                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4986                 break;
4987         case BNXT_PTP_FLAGS_PATH_RX:
4988                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4989                 break;
4990         case BNXT_PTP_FLAGS_CURRENT_TIME:
4991                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
4992                 break;
4993         }
4994
4995         req.flags = rte_cpu_to_le_32(flags);
4996         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
4997
4998         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4999
5000         HWRM_CHECK_RESULT();
5001
5002         if (timestamp) {
5003                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5004                 *timestamp |=
5005                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5006         }
5007         HWRM_UNLOCK();
5008
5009         return rc;
5010 }
5011
5012 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5013 {
5014         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5015                                         bp->hwrm_cmd_resp_addr;
5016         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5017         uint32_t flags = 0;
5018         int rc = 0;
5019
5020         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5021                 return rc;
5022
5023         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5024                 PMD_DRV_LOG(DEBUG,
5025                             "Not a PF or trusted VF. Command not supported\n");
5026                 return 0;
5027         }
5028
5029         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5030         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5031
5032         HWRM_CHECK_RESULT();
5033         flags = rte_le_to_cpu_32(resp->flags);
5034         HWRM_UNLOCK();
5035
5036         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5037                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5038                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5039         }
5040
5041         return rc;
5042 }