1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SHORT_CMD_TIMEOUT 50000
31 #define HWRM_SPEC_CODE_1_8_3 0x10803
32 #define HWRM_VERSION_1_9_1 0x10901
33 #define HWRM_VERSION_1_9_2 0x10903
35 struct bnxt_plcmodes_cfg {
37 uint16_t jumbo_thresh;
39 uint16_t hds_threshold;
42 static int page_getenum(size_t size)
58 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
59 return sizeof(void *) * 8 - 1;
62 static int page_roundup(size_t size)
64 return 1 << page_getenum(size);
67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
71 if (rmem->nr_pages > 1) {
73 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
75 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
80 * HWRM Functions (sent to HWRM)
81 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
82 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
83 * command was failed by the ChiMP.
86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
87 uint32_t msg_len, bool use_kong_mb)
90 struct input *req = msg;
91 struct output *resp = bp->hwrm_cmd_resp_addr;
95 uint16_t max_req_len = bp->max_req_len;
96 struct hwrm_short_input short_input = { 0 };
97 uint16_t bar_offset = use_kong_mb ?
98 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
99 uint16_t mb_trigger_offset = use_kong_mb ?
100 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
103 /* Do not send HWRM commands to firmware in error state */
104 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
107 /* For VER_GET command, set timeout as 50ms */
108 if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
109 timeout = HWRM_SHORT_CMD_TIMEOUT;
111 timeout = HWRM_CMD_TIMEOUT;
113 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
114 msg_len > bp->max_req_len) {
115 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
117 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
118 memcpy(short_cmd_req, req, msg_len);
120 short_input.req_type = rte_cpu_to_le_16(req->req_type);
121 short_input.signature = rte_cpu_to_le_16(
122 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
123 short_input.size = rte_cpu_to_le_16(msg_len);
124 short_input.req_addr =
125 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
127 data = (uint32_t *)&short_input;
128 msg_len = sizeof(short_input);
130 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
133 /* Write request msg to hwrm channel */
134 for (i = 0; i < msg_len; i += 4) {
135 bar = (uint8_t *)bp->bar0 + bar_offset + i;
136 rte_write32(*data, bar);
140 /* Zero the rest of the request space */
141 for (; i < max_req_len; i += 4) {
142 bar = (uint8_t *)bp->bar0 + bar_offset + i;
146 /* Ring channel doorbell */
147 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
150 * Make sure the channel doorbell ring command complete before
151 * reading the response to avoid getting stale or invalid
156 /* Poll for the valid bit */
157 for (i = 0; i < timeout; i++) {
158 /* Sanity check on the resp->resp_len */
160 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
161 /* Last byte of resp contains the valid key */
162 valid = (uint8_t *)resp + resp->resp_len - 1;
163 if (*valid == HWRM_RESP_VALID_KEY)
170 /* Suppress VER_GET timeout messages during reset recovery */
171 if (bp->flags & BNXT_FLAG_FW_RESET &&
172 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
175 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
183 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
184 * spinlock, and does initial processing.
186 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
187 * releases the spinlock only if it returns. If the regular int return codes
188 * are not used by the function, HWRM_CHECK_RESULT() should not be used
189 * directly, rather it should be copied and modified to suit the function.
191 * HWRM_UNLOCK() must be called after all response processing is completed.
193 #define HWRM_PREP(req, type, kong) do { \
194 rte_spinlock_lock(&bp->hwrm_lock); \
195 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
196 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
197 req.cmpl_ring = rte_cpu_to_le_16(-1); \
198 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
199 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
200 req.target_id = rte_cpu_to_le_16(0xffff); \
201 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
204 #define HWRM_CHECK_RESULT_SILENT() do {\
206 rte_spinlock_unlock(&bp->hwrm_lock); \
209 if (resp->error_code) { \
210 rc = rte_le_to_cpu_16(resp->error_code); \
211 rte_spinlock_unlock(&bp->hwrm_lock); \
216 #define HWRM_CHECK_RESULT() do {\
218 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
219 rte_spinlock_unlock(&bp->hwrm_lock); \
220 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
222 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
224 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
226 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
232 if (resp->error_code) { \
233 rc = rte_le_to_cpu_16(resp->error_code); \
234 if (resp->resp_len >= 16) { \
235 struct hwrm_err_output *tmp_hwrm_err_op = \
238 "error %d:%d:%08x:%04x\n", \
239 rc, tmp_hwrm_err_op->cmd_err, \
241 tmp_hwrm_err_op->opaque_0), \
243 tmp_hwrm_err_op->opaque_1)); \
245 PMD_DRV_LOG(ERR, "error %d\n", rc); \
247 rte_spinlock_unlock(&bp->hwrm_lock); \
248 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
250 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
252 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
254 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
262 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
264 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
267 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
268 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
270 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
271 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
274 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
282 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
283 struct bnxt_vnic_info *vnic,
285 struct bnxt_vlan_table_entry *vlan_table)
288 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
289 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
292 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
295 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
296 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
298 /* FIXME add multicast flag, when multicast adding options is supported
301 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
302 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
303 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
304 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
305 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
306 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
307 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
308 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
309 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
310 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
311 if (vnic->mc_addr_cnt) {
312 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
313 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
314 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
317 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
318 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
319 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
320 rte_mem_virt2iova(vlan_table));
321 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
323 req.mask = rte_cpu_to_le_32(mask);
325 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
333 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
335 struct bnxt_vlan_antispoof_table_entry *vlan_table)
338 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
339 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
340 bp->hwrm_cmd_resp_addr;
343 * Older HWRM versions did not support this command, and the set_rx_mask
344 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
345 * removed from set_rx_mask call, and this command was added.
347 * This command is also present from 1.7.8.11 and higher,
350 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
351 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
352 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
357 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
358 req.fid = rte_cpu_to_le_16(fid);
360 req.vlan_tag_mask_tbl_addr =
361 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
362 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
364 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
372 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
373 struct bnxt_filter_info *filter)
376 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
377 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
379 if (filter->fw_l2_filter_id == UINT64_MAX)
382 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
384 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
386 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
391 filter->fw_l2_filter_id = UINT64_MAX;
396 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
398 struct bnxt_filter_info *filter)
401 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
402 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
403 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
404 const struct rte_eth_vmdq_rx_conf *conf =
405 &dev_conf->rx_adv_conf.vmdq_rx_conf;
406 uint32_t enables = 0;
407 uint16_t j = dst_id - 1;
409 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
410 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
411 conf->pool_map[j].pools & (1UL << j)) {
413 "Add vlan %u to vmdq pool %u\n",
414 conf->pool_map[j].vlan_id, j);
416 filter->l2_ivlan = conf->pool_map[j].vlan_id;
418 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
419 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
422 if (filter->fw_l2_filter_id != UINT64_MAX)
423 bnxt_hwrm_clear_l2_filter(bp, filter);
425 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
427 req.flags = rte_cpu_to_le_32(filter->flags);
429 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
431 enables = filter->enables |
432 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
433 req.dst_id = rte_cpu_to_le_16(dst_id);
436 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
437 memcpy(req.l2_addr, filter->l2_addr,
440 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
441 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
444 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
445 req.l2_ovlan = filter->l2_ovlan;
447 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
448 req.l2_ivlan = filter->l2_ivlan;
450 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
451 req.l2_ovlan_mask = filter->l2_ovlan_mask;
453 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
454 req.l2_ivlan_mask = filter->l2_ivlan_mask;
455 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
456 req.src_id = rte_cpu_to_le_32(filter->src_id);
457 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
458 req.src_type = filter->src_type;
460 req.enables = rte_cpu_to_le_32(enables);
462 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
466 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
472 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
474 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
475 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
482 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
485 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
488 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
489 if (ptp->tx_tstamp_en)
490 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
493 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
494 req.flags = rte_cpu_to_le_32(flags);
495 req.enables = rte_cpu_to_le_32
496 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
497 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
499 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
505 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
508 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
509 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
510 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
512 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
516 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
518 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
520 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
524 if (!BNXT_CHIP_THOR(bp) &&
525 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
528 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
529 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
531 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
535 if (!BNXT_CHIP_THOR(bp)) {
536 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
537 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
538 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
539 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
540 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
541 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
542 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
543 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
544 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
545 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
546 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
547 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
548 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
549 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
550 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
551 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
552 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
553 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
562 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
565 struct hwrm_func_qcaps_input req = {.req_type = 0 };
566 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
567 uint16_t new_max_vfs;
571 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
573 req.fid = rte_cpu_to_le_16(0xffff);
575 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
579 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
580 flags = rte_le_to_cpu_32(resp->flags);
582 bp->pf.port_id = resp->port_id;
583 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
584 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
585 new_max_vfs = bp->pdev->max_vfs;
586 if (new_max_vfs != bp->pf.max_vfs) {
588 rte_free(bp->pf.vf_info);
589 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
590 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
591 bp->pf.max_vfs = new_max_vfs;
592 for (i = 0; i < new_max_vfs; i++) {
593 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
594 bp->pf.vf_info[i].vlan_table =
595 rte_zmalloc("VF VLAN table",
598 if (bp->pf.vf_info[i].vlan_table == NULL)
600 "Fail to alloc VLAN table for VF %d\n",
604 bp->pf.vf_info[i].vlan_table);
605 bp->pf.vf_info[i].vlan_as_table =
606 rte_zmalloc("VF VLAN AS table",
609 if (bp->pf.vf_info[i].vlan_as_table == NULL)
611 "Alloc VLAN AS table for VF %d fail\n",
615 bp->pf.vf_info[i].vlan_as_table);
616 STAILQ_INIT(&bp->pf.vf_info[i].filter);
621 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
622 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
623 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
624 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
625 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
626 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
627 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
628 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
629 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
630 if (!BNXT_CHIP_THOR(bp))
631 bp->max_l2_ctx += bp->max_rx_em_flows;
632 /* TODO: For now, do not support VMDq/RFS on VFs. */
637 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
641 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
643 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
644 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
645 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
646 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
648 bnxt_hwrm_ptp_qcfg(bp);
652 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
653 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
655 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
656 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
657 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
659 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
662 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
663 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
665 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
672 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
676 rc = __bnxt_hwrm_func_qcaps(bp);
677 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
678 rc = bnxt_alloc_ctx_mem(bp);
682 rc = bnxt_hwrm_func_resc_qcaps(bp);
684 bp->flags |= BNXT_FLAG_NEW_RM;
690 int bnxt_hwrm_func_reset(struct bnxt *bp)
693 struct hwrm_func_reset_input req = {.req_type = 0 };
694 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
696 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
698 req.enables = rte_cpu_to_le_32(0);
700 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
708 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
712 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
713 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
715 if (bp->flags & BNXT_FLAG_REGISTERED)
718 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
719 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
720 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
722 /* PFs and trusted VFs should indicate the support of the
723 * Master capability on non Stingray platform
725 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
726 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
728 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
729 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
730 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
731 req.ver_maj = RTE_VER_YEAR;
732 req.ver_min = RTE_VER_MONTH;
733 req.ver_upd = RTE_VER_MINOR;
736 req.enables |= rte_cpu_to_le_32(
737 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
738 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
739 RTE_MIN(sizeof(req.vf_req_fwd),
740 sizeof(bp->pf.vf_req_fwd)));
743 * PF can sniff HWRM API issued by VF. This can be set up by
744 * linux driver and inherited by the DPDK PF driver. Clear
745 * this HWRM sniffer list in FW because DPDK PF driver does
748 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
751 req.flags = rte_cpu_to_le_32(flags);
753 req.async_event_fwd[0] |=
754 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
755 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
756 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
757 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
758 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
759 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
760 req.async_event_fwd[0] |=
761 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
762 req.async_event_fwd[1] |=
763 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
764 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
766 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
770 flags = rte_le_to_cpu_32(resp->flags);
771 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
772 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
776 bp->flags |= BNXT_FLAG_REGISTERED;
781 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
783 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
786 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
789 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
794 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
795 struct hwrm_func_vf_cfg_input req = {0};
797 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
799 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
800 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
801 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
802 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
803 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
805 if (BNXT_HAS_RING_GRPS(bp)) {
806 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
807 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
810 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
811 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
812 AGG_RING_MULTIPLIER);
813 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
815 BNXT_NUM_ASYNC_CPR(bp));
816 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
818 BNXT_NUM_ASYNC_CPR(bp));
819 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
820 if (bp->vf_resv_strategy ==
821 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
822 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
823 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
824 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
825 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
826 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
827 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
831 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
832 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
833 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
834 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
835 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
836 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
838 if (test && BNXT_HAS_RING_GRPS(bp))
839 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
841 req.flags = rte_cpu_to_le_32(flags);
842 req.enables |= rte_cpu_to_le_32(enables);
844 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
847 HWRM_CHECK_RESULT_SILENT();
855 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
858 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
859 struct hwrm_func_resource_qcaps_input req = {0};
861 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
862 req.fid = rte_cpu_to_le_16(0xffff);
864 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
869 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
870 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
871 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
872 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
873 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
874 /* func_resource_qcaps does not return max_rx_em_flows.
875 * So use the value provided by func_qcaps.
877 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
878 if (!BNXT_CHIP_THOR(bp))
879 bp->max_l2_ctx += bp->max_rx_em_flows;
880 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
881 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
883 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
884 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
885 if (bp->vf_resv_strategy >
886 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
887 bp->vf_resv_strategy =
888 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
894 int bnxt_hwrm_ver_get(struct bnxt *bp)
897 struct hwrm_ver_get_input req = {.req_type = 0 };
898 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
900 uint16_t max_resp_len;
901 char type[RTE_MEMZONE_NAMESIZE];
902 uint32_t dev_caps_cfg;
904 bp->max_req_len = HWRM_MAX_REQ_LEN;
905 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
907 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
908 req.hwrm_intf_min = HWRM_VERSION_MINOR;
909 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
911 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
913 if (bp->flags & BNXT_FLAG_FW_RESET)
914 HWRM_CHECK_RESULT_SILENT();
918 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
919 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
920 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
921 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
922 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
923 (resp->hwrm_fw_min_8b << 16) |
924 (resp->hwrm_fw_bld_8b << 8) |
925 resp->hwrm_fw_rsvd_8b;
926 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
927 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
929 fw_version = resp->hwrm_intf_maj_8b << 16;
930 fw_version |= resp->hwrm_intf_min_8b << 8;
931 fw_version |= resp->hwrm_intf_upd_8b;
932 bp->hwrm_spec_code = fw_version;
934 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
935 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
940 if (bp->max_req_len > resp->max_req_win_len) {
941 PMD_DRV_LOG(ERR, "Unsupported request length\n");
944 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
945 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
946 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
947 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
949 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
950 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
952 if (bp->max_resp_len != max_resp_len) {
953 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
954 bp->pdev->addr.domain, bp->pdev->addr.bus,
955 bp->pdev->addr.devid, bp->pdev->addr.function);
957 rte_free(bp->hwrm_cmd_resp_addr);
959 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
960 if (bp->hwrm_cmd_resp_addr == NULL) {
964 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
965 bp->hwrm_cmd_resp_dma_addr =
966 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
967 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
969 "Unable to map response buffer to physical memory.\n");
973 bp->max_resp_len = max_resp_len;
977 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
979 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
980 PMD_DRV_LOG(DEBUG, "Short command supported\n");
981 bp->flags |= BNXT_FLAG_SHORT_CMD;
985 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
987 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
988 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
989 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
990 bp->pdev->addr.domain, bp->pdev->addr.bus,
991 bp->pdev->addr.devid, bp->pdev->addr.function);
993 rte_free(bp->hwrm_short_cmd_req_addr);
995 bp->hwrm_short_cmd_req_addr =
996 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
997 if (bp->hwrm_short_cmd_req_addr == NULL) {
1001 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1002 bp->hwrm_short_cmd_req_dma_addr =
1003 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1004 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1005 rte_free(bp->hwrm_short_cmd_req_addr);
1007 "Unable to map buffer to physical memory.\n");
1013 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1014 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1015 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1018 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1019 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1026 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1029 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1030 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1032 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1035 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1038 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1040 HWRM_CHECK_RESULT();
1046 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1049 struct hwrm_port_phy_cfg_input req = {0};
1050 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1051 uint32_t enables = 0;
1053 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1055 if (conf->link_up) {
1056 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1057 if (bp->link_info.auto_mode && conf->link_speed) {
1058 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1059 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1062 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1063 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1064 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1066 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1067 * any auto mode, even "none".
1069 if (!conf->link_speed) {
1070 /* No speeds specified. Enable AutoNeg - all speeds */
1072 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1074 /* AutoNeg - Advertise speeds specified. */
1075 if (conf->auto_link_speed_mask &&
1076 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1078 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1079 req.auto_link_speed_mask =
1080 conf->auto_link_speed_mask;
1082 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1085 req.auto_duplex = conf->duplex;
1086 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1087 req.auto_pause = conf->auto_pause;
1088 req.force_pause = conf->force_pause;
1089 /* Set force_pause if there is no auto or if there is a force */
1090 if (req.auto_pause && !req.force_pause)
1091 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1093 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1095 req.enables = rte_cpu_to_le_32(enables);
1098 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1099 PMD_DRV_LOG(INFO, "Force Link Down\n");
1102 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1104 HWRM_CHECK_RESULT();
1110 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1111 struct bnxt_link_info *link_info)
1114 struct hwrm_port_phy_qcfg_input req = {0};
1115 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1117 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1119 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1121 HWRM_CHECK_RESULT();
1123 link_info->phy_link_status = resp->link;
1124 link_info->link_up =
1125 (link_info->phy_link_status ==
1126 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1127 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1128 link_info->duplex = resp->duplex_cfg;
1129 link_info->pause = resp->pause;
1130 link_info->auto_pause = resp->auto_pause;
1131 link_info->force_pause = resp->force_pause;
1132 link_info->auto_mode = resp->auto_mode;
1133 link_info->phy_type = resp->phy_type;
1134 link_info->media_type = resp->media_type;
1136 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1137 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1138 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1139 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1140 link_info->phy_ver[0] = resp->phy_maj;
1141 link_info->phy_ver[1] = resp->phy_min;
1142 link_info->phy_ver[2] = resp->phy_bld;
1146 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1147 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1148 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1149 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1150 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1151 link_info->auto_link_speed_mask);
1152 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1153 link_info->force_link_speed);
1158 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1161 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1162 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1165 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1167 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1168 /* HWRM Version >= 1.9.1 */
1169 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1171 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1172 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1174 HWRM_CHECK_RESULT();
1176 #define GET_QUEUE_INFO(x) \
1177 bp->cos_queue[x].id = resp->queue_id##x; \
1178 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1191 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1192 bp->tx_cosq_id = bp->cos_queue[0].id;
1194 /* iterate and find the COSq profile to use for Tx */
1195 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1196 if (bp->cos_queue[i].profile ==
1197 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1198 bp->tx_cosq_id = bp->cos_queue[i].id;
1204 bp->max_tc = resp->max_configurable_queues;
1205 bp->max_lltc = resp->max_configurable_lossless_queues;
1206 if (bp->max_tc > BNXT_MAX_QUEUE)
1207 bp->max_tc = BNXT_MAX_QUEUE;
1208 bp->max_q = bp->max_tc;
1210 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1215 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1216 struct bnxt_ring *ring,
1217 uint32_t ring_type, uint32_t map_index,
1218 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1221 uint32_t enables = 0;
1222 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1223 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1224 struct rte_mempool *mb_pool;
1225 uint16_t rx_buf_size;
1227 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1229 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1230 req.fbo = rte_cpu_to_le_32(0);
1231 /* Association of ring index with doorbell index */
1232 req.logical_id = rte_cpu_to_le_16(map_index);
1233 req.length = rte_cpu_to_le_32(ring->ring_size);
1235 switch (ring_type) {
1236 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1237 req.ring_type = ring_type;
1238 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1239 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1240 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1241 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1243 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1245 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1246 req.ring_type = ring_type;
1247 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1248 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1249 if (BNXT_CHIP_THOR(bp)) {
1250 mb_pool = bp->rx_queues[0]->mb_pool;
1251 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1252 RTE_PKTMBUF_HEADROOM;
1253 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1254 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1256 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1258 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1260 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1262 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1263 req.ring_type = ring_type;
1264 if (BNXT_HAS_NQ(bp)) {
1265 /* Association of cp ring with nq */
1266 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1268 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1270 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1272 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1273 req.ring_type = ring_type;
1274 req.page_size = BNXT_PAGE_SHFT;
1275 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1277 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1278 req.ring_type = ring_type;
1279 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1281 mb_pool = bp->rx_queues[0]->mb_pool;
1282 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1283 RTE_PKTMBUF_HEADROOM;
1284 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1285 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1287 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1288 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1289 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1290 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1293 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1298 req.enables = rte_cpu_to_le_32(enables);
1300 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1302 if (rc || resp->error_code) {
1303 if (rc == 0 && resp->error_code)
1304 rc = rte_le_to_cpu_16(resp->error_code);
1305 switch (ring_type) {
1306 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1308 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1311 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1313 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1316 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1318 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1322 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1324 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1327 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1329 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1333 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1339 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1344 int bnxt_hwrm_ring_free(struct bnxt *bp,
1345 struct bnxt_ring *ring, uint32_t ring_type)
1348 struct hwrm_ring_free_input req = {.req_type = 0 };
1349 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1351 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1353 req.ring_type = ring_type;
1354 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1356 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1358 if (rc || resp->error_code) {
1359 if (rc == 0 && resp->error_code)
1360 rc = rte_le_to_cpu_16(resp->error_code);
1363 switch (ring_type) {
1364 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1365 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1368 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1369 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1372 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1373 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1376 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1378 "hwrm_ring_free nq failed. rc:%d\n", rc);
1380 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1382 "hwrm_ring_free agg failed. rc:%d\n", rc);
1385 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1393 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1396 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1397 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1399 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1401 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1402 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1403 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1404 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1406 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1408 HWRM_CHECK_RESULT();
1410 bp->grp_info[idx].fw_grp_id =
1411 rte_le_to_cpu_16(resp->ring_group_id);
1418 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1421 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1422 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1424 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1426 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1428 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1430 HWRM_CHECK_RESULT();
1433 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1437 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1440 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1441 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1443 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1446 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1448 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1450 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1452 HWRM_CHECK_RESULT();
1458 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1459 unsigned int idx __rte_unused)
1462 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1463 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1465 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1467 req.update_period_ms = rte_cpu_to_le_32(0);
1469 req.stats_dma_addr =
1470 rte_cpu_to_le_64(cpr->hw_stats_map);
1472 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1474 HWRM_CHECK_RESULT();
1476 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1483 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1484 unsigned int idx __rte_unused)
1487 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1488 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1490 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1492 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1494 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1496 HWRM_CHECK_RESULT();
1502 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1505 struct hwrm_vnic_alloc_input req = { 0 };
1506 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1508 if (!BNXT_HAS_RING_GRPS(bp))
1509 goto skip_ring_grps;
1511 /* map ring groups to this vnic */
1512 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1513 vnic->start_grp_id, vnic->end_grp_id);
1514 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1515 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1517 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1518 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1519 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1520 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1523 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1524 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1525 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1527 if (vnic->func_default)
1529 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1530 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1532 HWRM_CHECK_RESULT();
1534 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1536 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1540 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1541 struct bnxt_vnic_info *vnic,
1542 struct bnxt_plcmodes_cfg *pmode)
1545 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1546 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1548 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1550 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1552 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1554 HWRM_CHECK_RESULT();
1556 pmode->flags = rte_le_to_cpu_32(resp->flags);
1557 /* dflt_vnic bit doesn't exist in the _cfg command */
1558 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1559 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1560 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1561 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1568 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1569 struct bnxt_vnic_info *vnic,
1570 struct bnxt_plcmodes_cfg *pmode)
1573 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1574 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1576 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1577 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1581 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1583 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1584 req.flags = rte_cpu_to_le_32(pmode->flags);
1585 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1586 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1587 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1588 req.enables = rte_cpu_to_le_32(
1589 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1590 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1591 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1594 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1596 HWRM_CHECK_RESULT();
1602 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1605 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1606 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1607 struct bnxt_plcmodes_cfg pmodes = { 0 };
1608 uint32_t ctx_enable_flag = 0;
1609 uint32_t enables = 0;
1611 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1612 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1616 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1620 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1622 if (BNXT_CHIP_THOR(bp)) {
1623 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1624 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1625 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1627 req.default_rx_ring_id =
1628 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1629 req.default_cmpl_ring_id =
1630 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1631 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1632 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1636 /* Only RSS support for now TBD: COS & LB */
1637 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1638 if (vnic->lb_rule != 0xffff)
1639 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1640 if (vnic->cos_rule != 0xffff)
1641 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1642 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1643 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1644 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1646 enables |= ctx_enable_flag;
1647 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1648 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1649 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1650 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1653 req.enables = rte_cpu_to_le_32(enables);
1654 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1655 req.mru = rte_cpu_to_le_16(vnic->mru);
1656 /* Configure default VNIC only once. */
1657 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1659 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1660 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1662 if (vnic->vlan_strip)
1664 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1667 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1668 if (vnic->roce_dual)
1669 req.flags |= rte_cpu_to_le_32(
1670 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1671 if (vnic->roce_only)
1672 req.flags |= rte_cpu_to_le_32(
1673 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1674 if (vnic->rss_dflt_cr)
1675 req.flags |= rte_cpu_to_le_32(
1676 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1678 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1680 HWRM_CHECK_RESULT();
1683 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1688 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1692 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1693 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1695 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1696 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1699 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1702 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1703 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1704 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1706 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1708 HWRM_CHECK_RESULT();
1710 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1711 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1712 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1713 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1714 vnic->mru = rte_le_to_cpu_16(resp->mru);
1715 vnic->func_default = rte_le_to_cpu_32(
1716 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1717 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1718 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1719 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1720 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1721 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1722 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1723 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1724 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1725 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1726 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1733 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1734 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1738 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1739 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1740 bp->hwrm_cmd_resp_addr;
1742 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1744 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1745 HWRM_CHECK_RESULT();
1747 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1748 if (!BNXT_HAS_RING_GRPS(bp))
1749 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1750 else if (ctx_idx == 0)
1751 vnic->rss_rule = ctx_id;
1758 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1759 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1762 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1763 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1764 bp->hwrm_cmd_resp_addr;
1766 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1767 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1770 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1772 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1774 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1776 HWRM_CHECK_RESULT();
1782 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1785 struct hwrm_vnic_free_input req = {.req_type = 0 };
1786 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1788 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1789 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1793 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1795 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1797 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1799 HWRM_CHECK_RESULT();
1802 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1803 /* Configure default VNIC again if necessary. */
1804 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1805 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1811 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1815 int nr_ctxs = vnic->num_lb_ctxts;
1816 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1817 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1819 for (i = 0; i < nr_ctxs; i++) {
1820 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1822 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1823 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1824 req.hash_mode_flags = vnic->hash_mode;
1826 req.hash_key_tbl_addr =
1827 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1829 req.ring_grp_tbl_addr =
1830 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1831 i * HW_HASH_INDEX_SIZE);
1832 req.ring_table_pair_index = i;
1833 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1835 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1838 HWRM_CHECK_RESULT();
1845 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1846 struct bnxt_vnic_info *vnic)
1849 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1850 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1852 if (!vnic->rss_table)
1855 if (BNXT_CHIP_THOR(bp))
1856 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1858 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1860 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1861 req.hash_mode_flags = vnic->hash_mode;
1863 req.ring_grp_tbl_addr =
1864 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1865 req.hash_key_tbl_addr =
1866 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1867 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1868 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1870 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1872 HWRM_CHECK_RESULT();
1878 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1879 struct bnxt_vnic_info *vnic)
1882 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1883 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1886 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1887 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1891 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1893 req.flags = rte_cpu_to_le_32(
1894 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1896 req.enables = rte_cpu_to_le_32(
1897 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1899 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1900 size -= RTE_PKTMBUF_HEADROOM;
1901 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
1903 req.jumbo_thresh = rte_cpu_to_le_16(size);
1904 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1906 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1908 HWRM_CHECK_RESULT();
1914 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1915 struct bnxt_vnic_info *vnic, bool enable)
1918 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1919 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1921 if (BNXT_CHIP_THOR(bp))
1924 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1927 req.enables = rte_cpu_to_le_32(
1928 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1929 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1930 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1931 req.flags = rte_cpu_to_le_32(
1932 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1933 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1934 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1935 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1936 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1937 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1938 req.max_agg_segs = rte_cpu_to_le_16(5);
1940 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1941 req.min_agg_len = rte_cpu_to_le_32(512);
1943 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1945 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1947 HWRM_CHECK_RESULT();
1953 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1955 struct hwrm_func_cfg_input req = {0};
1956 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1959 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1960 req.enables = rte_cpu_to_le_32(
1961 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1962 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1963 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1965 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1967 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1968 HWRM_CHECK_RESULT();
1971 bp->pf.vf_info[vf].random_mac = false;
1976 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1980 struct hwrm_func_qstats_input req = {.req_type = 0};
1981 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1983 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1985 req.fid = rte_cpu_to_le_16(fid);
1987 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1989 HWRM_CHECK_RESULT();
1992 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1999 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2000 struct rte_eth_stats *stats)
2003 struct hwrm_func_qstats_input req = {.req_type = 0};
2004 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2006 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2008 req.fid = rte_cpu_to_le_16(fid);
2010 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2012 HWRM_CHECK_RESULT();
2014 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2015 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2016 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2017 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2018 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2019 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2021 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2022 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2023 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2024 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2025 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2026 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2028 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2029 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2030 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2037 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2040 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2041 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2043 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2045 req.fid = rte_cpu_to_le_16(fid);
2047 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2049 HWRM_CHECK_RESULT();
2056 * HWRM utility functions
2059 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2064 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2065 struct bnxt_tx_queue *txq;
2066 struct bnxt_rx_queue *rxq;
2067 struct bnxt_cp_ring_info *cpr;
2069 if (i >= bp->rx_cp_nr_rings) {
2070 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2073 rxq = bp->rx_queues[i];
2077 rc = bnxt_hwrm_stat_clear(bp, cpr);
2084 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2088 struct bnxt_cp_ring_info *cpr;
2090 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2092 if (i >= bp->rx_cp_nr_rings) {
2093 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2095 cpr = bp->rx_queues[i]->cp_ring;
2096 if (BNXT_HAS_RING_GRPS(bp))
2097 bp->grp_info[i].fw_stats_ctx = -1;
2099 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2100 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2101 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2109 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2114 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2115 struct bnxt_tx_queue *txq;
2116 struct bnxt_rx_queue *rxq;
2117 struct bnxt_cp_ring_info *cpr;
2119 if (i >= bp->rx_cp_nr_rings) {
2120 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2123 rxq = bp->rx_queues[i];
2127 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2135 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2140 if (!BNXT_HAS_RING_GRPS(bp))
2143 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2145 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2148 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2156 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2158 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2160 bnxt_hwrm_ring_free(bp, cp_ring,
2161 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2162 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2163 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2164 sizeof(*cpr->cp_desc_ring));
2165 cpr->cp_raw_cons = 0;
2169 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2171 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2173 bnxt_hwrm_ring_free(bp, cp_ring,
2174 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2175 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2176 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2177 sizeof(*cpr->cp_desc_ring));
2178 cpr->cp_raw_cons = 0;
2182 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2184 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2185 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2186 struct bnxt_ring *ring = rxr->rx_ring_struct;
2187 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2189 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2190 bnxt_hwrm_ring_free(bp, ring,
2191 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2192 ring->fw_ring_id = INVALID_HW_RING_ID;
2193 if (BNXT_HAS_RING_GRPS(bp))
2194 bp->grp_info[queue_index].rx_fw_ring_id =
2196 memset(rxr->rx_desc_ring, 0,
2197 rxr->rx_ring_struct->ring_size *
2198 sizeof(*rxr->rx_desc_ring));
2199 memset(rxr->rx_buf_ring, 0,
2200 rxr->rx_ring_struct->ring_size *
2201 sizeof(*rxr->rx_buf_ring));
2204 ring = rxr->ag_ring_struct;
2205 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2206 bnxt_hwrm_ring_free(bp, ring,
2207 BNXT_CHIP_THOR(bp) ?
2208 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2209 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2210 ring->fw_ring_id = INVALID_HW_RING_ID;
2211 memset(rxr->ag_buf_ring, 0,
2212 rxr->ag_ring_struct->ring_size *
2213 sizeof(*rxr->ag_buf_ring));
2215 if (BNXT_HAS_RING_GRPS(bp))
2216 bp->grp_info[queue_index].ag_fw_ring_id =
2219 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2220 bnxt_free_cp_ring(bp, cpr);
2222 bnxt_free_nq_ring(bp, rxq->nq_ring);
2225 if (BNXT_HAS_RING_GRPS(bp))
2226 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2229 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2233 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2234 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2235 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2236 struct bnxt_ring *ring = txr->tx_ring_struct;
2237 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2239 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2240 bnxt_hwrm_ring_free(bp, ring,
2241 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2242 ring->fw_ring_id = INVALID_HW_RING_ID;
2243 memset(txr->tx_desc_ring, 0,
2244 txr->tx_ring_struct->ring_size *
2245 sizeof(*txr->tx_desc_ring));
2246 memset(txr->tx_buf_ring, 0,
2247 txr->tx_ring_struct->ring_size *
2248 sizeof(*txr->tx_buf_ring));
2252 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2253 bnxt_free_cp_ring(bp, cpr);
2254 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2256 bnxt_free_nq_ring(bp, txq->nq_ring);
2260 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2261 bnxt_free_hwrm_rx_ring(bp, i);
2266 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2271 if (!BNXT_HAS_RING_GRPS(bp))
2274 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2275 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2282 void bnxt_free_hwrm_resources(struct bnxt *bp)
2284 /* Release memzone */
2285 rte_free(bp->hwrm_cmd_resp_addr);
2286 rte_free(bp->hwrm_short_cmd_req_addr);
2287 bp->hwrm_cmd_resp_addr = NULL;
2288 bp->hwrm_short_cmd_req_addr = NULL;
2289 bp->hwrm_cmd_resp_dma_addr = 0;
2290 bp->hwrm_short_cmd_req_dma_addr = 0;
2293 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2295 struct rte_pci_device *pdev = bp->pdev;
2296 char type[RTE_MEMZONE_NAMESIZE];
2298 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2299 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2300 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2301 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2302 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2303 if (bp->hwrm_cmd_resp_addr == NULL)
2305 bp->hwrm_cmd_resp_dma_addr =
2306 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2307 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2309 "unable to map response address to physical memory\n");
2312 rte_spinlock_init(&bp->hwrm_lock);
2317 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2319 struct bnxt_filter_info *filter;
2322 STAILQ_FOREACH(filter, &vnic->filter, next) {
2323 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2324 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2325 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2326 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2328 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2329 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2337 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2339 struct bnxt_filter_info *filter;
2340 struct rte_flow *flow;
2343 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2344 filter = flow->filter;
2345 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2346 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2347 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2348 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2349 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2351 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2353 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2361 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2363 struct bnxt_filter_info *filter;
2366 STAILQ_FOREACH(filter, &vnic->filter, next) {
2367 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2368 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2370 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2371 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2374 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2382 void bnxt_free_tunnel_ports(struct bnxt *bp)
2384 if (bp->vxlan_port_cnt)
2385 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2386 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2388 if (bp->geneve_port_cnt)
2389 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2390 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2391 bp->geneve_port = 0;
2394 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2398 if (bp->vnic_info == NULL)
2402 * Cleanup VNICs in reverse order, to make sure the L2 filter
2403 * from vnic0 is last to be cleaned up.
2405 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2406 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2408 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2409 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2413 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2415 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2417 if (BNXT_CHIP_THOR(bp)) {
2418 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2419 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2420 vnic->fw_grp_ids[j]);
2421 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2423 vnic->num_lb_ctxts = 0;
2425 bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2426 vnic->rss_rule = INVALID_HW_RING_ID;
2429 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2431 bnxt_hwrm_vnic_free(bp, vnic);
2433 rte_free(vnic->fw_grp_ids);
2435 /* Ring resources */
2436 bnxt_free_all_hwrm_rings(bp);
2437 bnxt_free_all_hwrm_ring_grps(bp);
2438 bnxt_free_all_hwrm_stat_ctxs(bp);
2439 bnxt_free_tunnel_ports(bp);
2442 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2444 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2446 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2447 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2449 switch (conf_link_speed) {
2450 case ETH_LINK_SPEED_10M_HD:
2451 case ETH_LINK_SPEED_100M_HD:
2453 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2455 return hw_link_duplex;
2458 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2460 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2463 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2465 uint16_t eth_link_speed = 0;
2467 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2468 return ETH_LINK_SPEED_AUTONEG;
2470 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2471 case ETH_LINK_SPEED_100M:
2472 case ETH_LINK_SPEED_100M_HD:
2475 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2477 case ETH_LINK_SPEED_1G:
2479 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2481 case ETH_LINK_SPEED_2_5G:
2483 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2485 case ETH_LINK_SPEED_10G:
2487 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2489 case ETH_LINK_SPEED_20G:
2491 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2493 case ETH_LINK_SPEED_25G:
2495 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2497 case ETH_LINK_SPEED_40G:
2499 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2501 case ETH_LINK_SPEED_50G:
2503 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2505 case ETH_LINK_SPEED_100G:
2507 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2511 "Unsupported link speed %d; default to AUTO\n",
2515 return eth_link_speed;
2518 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2519 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2520 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2521 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2523 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2527 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2530 if (link_speed & ETH_LINK_SPEED_FIXED) {
2531 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2533 if (one_speed & (one_speed - 1)) {
2535 "Invalid advertised speeds (%u) for port %u\n",
2536 link_speed, port_id);
2539 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2541 "Unsupported advertised speed (%u) for port %u\n",
2542 link_speed, port_id);
2546 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2548 "Unsupported advertised speeds (%u) for port %u\n",
2549 link_speed, port_id);
2557 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2561 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2562 if (bp->link_info.support_speeds)
2563 return bp->link_info.support_speeds;
2564 link_speed = BNXT_SUPPORTED_SPEEDS;
2567 if (link_speed & ETH_LINK_SPEED_100M)
2568 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2569 if (link_speed & ETH_LINK_SPEED_100M_HD)
2570 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2571 if (link_speed & ETH_LINK_SPEED_1G)
2572 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2573 if (link_speed & ETH_LINK_SPEED_2_5G)
2574 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2575 if (link_speed & ETH_LINK_SPEED_10G)
2576 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2577 if (link_speed & ETH_LINK_SPEED_20G)
2578 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2579 if (link_speed & ETH_LINK_SPEED_25G)
2580 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2581 if (link_speed & ETH_LINK_SPEED_40G)
2582 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2583 if (link_speed & ETH_LINK_SPEED_50G)
2584 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2585 if (link_speed & ETH_LINK_SPEED_100G)
2586 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2590 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2592 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2594 switch (hw_link_speed) {
2595 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2596 eth_link_speed = ETH_SPEED_NUM_100M;
2598 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2599 eth_link_speed = ETH_SPEED_NUM_1G;
2601 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2602 eth_link_speed = ETH_SPEED_NUM_2_5G;
2604 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2605 eth_link_speed = ETH_SPEED_NUM_10G;
2607 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2608 eth_link_speed = ETH_SPEED_NUM_20G;
2610 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2611 eth_link_speed = ETH_SPEED_NUM_25G;
2613 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2614 eth_link_speed = ETH_SPEED_NUM_40G;
2616 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2617 eth_link_speed = ETH_SPEED_NUM_50G;
2619 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2620 eth_link_speed = ETH_SPEED_NUM_100G;
2622 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2624 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2628 return eth_link_speed;
2631 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2633 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2635 switch (hw_link_duplex) {
2636 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2637 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2639 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2641 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2642 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2645 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2649 return eth_link_duplex;
2652 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2655 struct bnxt_link_info *link_info = &bp->link_info;
2657 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2660 "Get link config failed with rc %d\n", rc);
2663 if (link_info->link_speed)
2665 bnxt_parse_hw_link_speed(link_info->link_speed);
2667 link->link_speed = ETH_SPEED_NUM_NONE;
2668 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2669 link->link_status = link_info->link_up;
2670 link->link_autoneg = link_info->auto_mode ==
2671 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2672 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2677 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2680 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2681 struct bnxt_link_info link_req;
2682 uint16_t speed, autoneg;
2684 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2687 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2688 bp->eth_dev->data->port_id);
2692 memset(&link_req, 0, sizeof(link_req));
2693 link_req.link_up = link_up;
2697 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2698 if (BNXT_CHIP_THOR(bp) &&
2699 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2700 /* 40G is not supported as part of media auto detect.
2701 * The speed should be forced and autoneg disabled
2702 * to configure 40G speed.
2704 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2708 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2709 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2710 /* Autoneg can be done only when the FW allows.
2711 * When user configures fixed speed of 40G and later changes to
2712 * any other speed, auto_link_speed/force_link_speed is still set
2713 * to 40G until link comes up at new speed.
2716 !(!BNXT_CHIP_THOR(bp) &&
2717 (bp->link_info.auto_link_speed ||
2718 bp->link_info.force_link_speed))) {
2719 link_req.phy_flags |=
2720 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2721 link_req.auto_link_speed_mask =
2722 bnxt_parse_eth_link_speed_mask(bp,
2723 dev_conf->link_speeds);
2725 if (bp->link_info.phy_type ==
2726 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2727 bp->link_info.phy_type ==
2728 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2729 bp->link_info.media_type ==
2730 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2731 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2735 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2736 /* If user wants a particular speed try that first. */
2738 link_req.link_speed = speed;
2739 else if (bp->link_info.force_link_speed)
2740 link_req.link_speed = bp->link_info.force_link_speed;
2742 link_req.link_speed = bp->link_info.auto_link_speed;
2744 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2745 link_req.auto_pause = bp->link_info.auto_pause;
2746 link_req.force_pause = bp->link_info.force_pause;
2749 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2752 "Set link config failed with rc %d\n", rc);
2760 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2762 struct hwrm_func_qcfg_input req = {0};
2763 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2767 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2768 req.fid = rte_cpu_to_le_16(0xffff);
2770 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2772 HWRM_CHECK_RESULT();
2774 /* Hard Coded.. 0xfff VLAN ID mask */
2775 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2776 flags = rte_le_to_cpu_16(resp->flags);
2777 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2778 bp->flags |= BNXT_FLAG_MULTI_HOST;
2780 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2781 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2782 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2783 } else if (BNXT_VF(bp) &&
2784 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2785 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2786 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2792 switch (resp->port_partition_type) {
2793 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2794 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2795 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2797 bp->port_partition_type = resp->port_partition_type;
2800 bp->port_partition_type = 0;
2809 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2810 struct hwrm_func_qcaps_output *qcaps)
2812 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2813 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2814 sizeof(qcaps->mac_address));
2815 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2816 qcaps->max_rx_rings = fcfg->num_rx_rings;
2817 qcaps->max_tx_rings = fcfg->num_tx_rings;
2818 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2819 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2821 qcaps->first_vf_id = 0;
2822 qcaps->max_vnics = fcfg->num_vnics;
2823 qcaps->max_decap_records = 0;
2824 qcaps->max_encap_records = 0;
2825 qcaps->max_tx_wm_flows = 0;
2826 qcaps->max_tx_em_flows = 0;
2827 qcaps->max_rx_wm_flows = 0;
2828 qcaps->max_rx_em_flows = 0;
2829 qcaps->max_flow_id = 0;
2830 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2831 qcaps->max_sp_tx_rings = 0;
2832 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2835 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2837 struct hwrm_func_cfg_input req = {0};
2838 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2842 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2843 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2844 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2845 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2846 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2847 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2848 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2849 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2850 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2852 if (BNXT_HAS_RING_GRPS(bp)) {
2853 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2854 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2855 } else if (BNXT_HAS_NQ(bp)) {
2856 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2857 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2860 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2861 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2862 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2863 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2865 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2866 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2867 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2868 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2869 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2870 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2871 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2872 req.fid = rte_cpu_to_le_16(0xffff);
2873 req.enables = rte_cpu_to_le_32(enables);
2875 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2877 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2879 HWRM_CHECK_RESULT();
2885 static void populate_vf_func_cfg_req(struct bnxt *bp,
2886 struct hwrm_func_cfg_input *req,
2889 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2890 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2891 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2892 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2893 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2894 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2895 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2896 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2897 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2898 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2900 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2901 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2903 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2904 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2906 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2908 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2909 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2911 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2912 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2913 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2914 /* TODO: For now, do not support VMDq/RFS on VFs. */
2915 req->num_vnics = rte_cpu_to_le_16(1);
2916 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2920 static void add_random_mac_if_needed(struct bnxt *bp,
2921 struct hwrm_func_cfg_input *cfg_req,
2924 struct rte_ether_addr mac;
2926 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2929 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2931 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2932 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2933 bp->pf.vf_info[vf].random_mac = true;
2935 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2936 RTE_ETHER_ADDR_LEN);
2940 static void reserve_resources_from_vf(struct bnxt *bp,
2941 struct hwrm_func_cfg_input *cfg_req,
2944 struct hwrm_func_qcaps_input req = {0};
2945 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2948 /* Get the actual allocated values now */
2949 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2950 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2951 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2954 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2955 copy_func_cfg_to_qcaps(cfg_req, resp);
2956 } else if (resp->error_code) {
2957 rc = rte_le_to_cpu_16(resp->error_code);
2958 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2959 copy_func_cfg_to_qcaps(cfg_req, resp);
2962 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2963 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2964 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2965 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2966 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2967 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2969 * TODO: While not supporting VMDq with VFs, max_vnics is always
2970 * forced to 1 in this case
2972 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2973 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2978 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2980 struct hwrm_func_qcfg_input req = {0};
2981 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2984 /* Check for zero MAC address */
2985 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2986 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2987 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2988 HWRM_CHECK_RESULT();
2989 rc = rte_le_to_cpu_16(resp->vlan);
2996 static int update_pf_resource_max(struct bnxt *bp)
2998 struct hwrm_func_qcfg_input req = {0};
2999 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3002 /* And copy the allocated numbers into the pf struct */
3003 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3004 req.fid = rte_cpu_to_le_16(0xffff);
3005 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3006 HWRM_CHECK_RESULT();
3008 /* Only TX ring value reflects actual allocation? TODO */
3009 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3010 bp->pf.evb_mode = resp->evb_mode;
3017 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3022 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3026 rc = bnxt_hwrm_func_qcaps(bp);
3030 bp->pf.func_cfg_flags &=
3031 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3032 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3033 bp->pf.func_cfg_flags |=
3034 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3035 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3036 rc = __bnxt_hwrm_func_qcaps(bp);
3040 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3042 struct hwrm_func_cfg_input req = {0};
3043 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3050 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3054 rc = bnxt_hwrm_func_qcaps(bp);
3059 bp->pf.active_vfs = num_vfs;
3062 * First, configure the PF to only use one TX ring. This ensures that
3063 * there are enough rings for all VFs.
3065 * If we don't do this, when we call func_alloc() later, we will lock
3066 * extra rings to the PF that won't be available during func_cfg() of
3069 * This has been fixed with firmware versions above 20.6.54
3071 bp->pf.func_cfg_flags &=
3072 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3073 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3074 bp->pf.func_cfg_flags |=
3075 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3076 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3081 * Now, create and register a buffer to hold forwarded VF requests
3083 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3084 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3085 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3086 if (bp->pf.vf_req_buf == NULL) {
3090 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3091 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3092 for (i = 0; i < num_vfs; i++)
3093 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3094 (i * HWRM_MAX_REQ_LEN);
3096 rc = bnxt_hwrm_func_buf_rgtr(bp);
3100 populate_vf_func_cfg_req(bp, &req, num_vfs);
3102 bp->pf.active_vfs = 0;
3103 for (i = 0; i < num_vfs; i++) {
3104 add_random_mac_if_needed(bp, &req, i);
3106 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3107 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3108 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3109 rc = bnxt_hwrm_send_message(bp,
3114 /* Clear enable flag for next pass */
3115 req.enables &= ~rte_cpu_to_le_32(
3116 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3118 if (rc || resp->error_code) {
3120 "Failed to initizlie VF %d\n", i);
3122 "Not all VFs available. (%d, %d)\n",
3123 rc, resp->error_code);
3130 reserve_resources_from_vf(bp, &req, i);
3131 bp->pf.active_vfs++;
3132 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3136 * Now configure the PF to use "the rest" of the resources
3137 * We're using STD_TX_RING_MODE here though which will limit the TX
3138 * rings. This will allow QoS to function properly. Not setting this
3139 * will cause PF rings to break bandwidth settings.
3141 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3145 rc = update_pf_resource_max(bp);
3152 bnxt_hwrm_func_buf_unrgtr(bp);
3156 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3158 struct hwrm_func_cfg_input req = {0};
3159 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3162 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3164 req.fid = rte_cpu_to_le_16(0xffff);
3165 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3166 req.evb_mode = bp->pf.evb_mode;
3168 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3169 HWRM_CHECK_RESULT();
3175 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3176 uint8_t tunnel_type)
3178 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3179 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3182 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3183 req.tunnel_type = tunnel_type;
3184 req.tunnel_dst_port_val = port;
3185 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3186 HWRM_CHECK_RESULT();
3188 switch (tunnel_type) {
3189 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3190 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3191 bp->vxlan_port = port;
3193 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3194 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3195 bp->geneve_port = port;
3206 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3207 uint8_t tunnel_type)
3209 struct hwrm_tunnel_dst_port_free_input req = {0};
3210 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3213 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3215 req.tunnel_type = tunnel_type;
3216 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3217 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3219 HWRM_CHECK_RESULT();
3225 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3228 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3229 struct hwrm_func_cfg_input req = {0};
3232 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3234 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3235 req.flags = rte_cpu_to_le_32(flags);
3236 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3238 HWRM_CHECK_RESULT();
3244 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3246 uint32_t *flag = flagp;
3248 vnic->flags = *flag;
3251 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3253 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3256 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3259 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3260 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3262 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3264 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3265 req.req_buf_page_size = rte_cpu_to_le_16(
3266 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3267 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3268 req.req_buf_page_addr0 =
3269 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3270 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3272 "unable to map buffer address to physical memory\n");
3276 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3278 HWRM_CHECK_RESULT();
3284 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3287 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3288 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3290 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3293 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3295 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3297 HWRM_CHECK_RESULT();
3303 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3305 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3306 struct hwrm_func_cfg_input req = {0};
3309 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3311 req.fid = rte_cpu_to_le_16(0xffff);
3312 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3313 req.enables = rte_cpu_to_le_32(
3314 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3315 req.async_event_cr = rte_cpu_to_le_16(
3316 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3317 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3319 HWRM_CHECK_RESULT();
3325 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3327 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3328 struct hwrm_func_vf_cfg_input req = {0};
3331 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3333 req.enables = rte_cpu_to_le_32(
3334 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3335 req.async_event_cr = rte_cpu_to_le_16(
3336 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3337 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3339 HWRM_CHECK_RESULT();
3345 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3347 struct hwrm_func_cfg_input req = {0};
3348 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3349 uint16_t dflt_vlan, fid;
3350 uint32_t func_cfg_flags;
3353 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3356 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3357 fid = bp->pf.vf_info[vf].fid;
3358 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3360 fid = rte_cpu_to_le_16(0xffff);
3361 func_cfg_flags = bp->pf.func_cfg_flags;
3362 dflt_vlan = bp->vlan;
3365 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3366 req.fid = rte_cpu_to_le_16(fid);
3367 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3368 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3370 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3372 HWRM_CHECK_RESULT();
3378 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3379 uint16_t max_bw, uint16_t enables)
3381 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3382 struct hwrm_func_cfg_input req = {0};
3385 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3387 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3388 req.enables |= rte_cpu_to_le_32(enables);
3389 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3390 req.max_bw = rte_cpu_to_le_32(max_bw);
3391 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3393 HWRM_CHECK_RESULT();
3399 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3401 struct hwrm_func_cfg_input req = {0};
3402 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3405 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3407 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3408 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3409 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3410 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3412 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3414 HWRM_CHECK_RESULT();
3420 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3425 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3427 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3432 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3433 void *encaped, size_t ec_size)
3436 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3437 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3439 if (ec_size > sizeof(req.encap_request))
3442 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3444 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3445 memcpy(req.encap_request, encaped, ec_size);
3447 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3449 HWRM_CHECK_RESULT();
3455 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3456 struct rte_ether_addr *mac)
3458 struct hwrm_func_qcfg_input req = {0};
3459 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3462 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3464 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3465 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3467 HWRM_CHECK_RESULT();
3469 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3476 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3477 void *encaped, size_t ec_size)
3480 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3481 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3483 if (ec_size > sizeof(req.encap_request))
3486 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3488 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3489 memcpy(req.encap_request, encaped, ec_size);
3491 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3493 HWRM_CHECK_RESULT();
3499 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3500 struct rte_eth_stats *stats, uint8_t rx)
3503 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3504 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3506 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3508 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3510 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3512 HWRM_CHECK_RESULT();
3515 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3516 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3517 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3518 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3519 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3520 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3521 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3522 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3524 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3525 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3526 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3527 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3528 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3529 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3538 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3540 struct hwrm_port_qstats_input req = {0};
3541 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3542 struct bnxt_pf_info *pf = &bp->pf;
3545 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3547 req.port_id = rte_cpu_to_le_16(pf->port_id);
3548 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3549 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3550 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3552 HWRM_CHECK_RESULT();
3558 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3560 struct hwrm_port_clr_stats_input req = {0};
3561 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3562 struct bnxt_pf_info *pf = &bp->pf;
3565 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3566 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3567 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3570 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3572 req.port_id = rte_cpu_to_le_16(pf->port_id);
3573 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3575 HWRM_CHECK_RESULT();
3581 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3583 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3584 struct hwrm_port_led_qcaps_input req = {0};
3590 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3591 req.port_id = bp->pf.port_id;
3592 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3594 HWRM_CHECK_RESULT();
3596 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3599 bp->num_leds = resp->num_leds;
3600 memcpy(bp->leds, &resp->led0_id,
3601 sizeof(bp->leds[0]) * bp->num_leds);
3602 for (i = 0; i < bp->num_leds; i++) {
3603 struct bnxt_led_info *led = &bp->leds[i];
3605 uint16_t caps = led->led_state_caps;
3607 if (!led->led_group_id ||
3608 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3620 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3622 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3623 struct hwrm_port_led_cfg_input req = {0};
3624 struct bnxt_led_cfg *led_cfg;
3625 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3626 uint16_t duration = 0;
3629 if (!bp->num_leds || BNXT_VF(bp))
3632 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3635 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3636 duration = rte_cpu_to_le_16(500);
3638 req.port_id = bp->pf.port_id;
3639 req.num_leds = bp->num_leds;
3640 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3641 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3642 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3643 led_cfg->led_id = bp->leds[i].led_id;
3644 led_cfg->led_state = led_state;
3645 led_cfg->led_blink_on = duration;
3646 led_cfg->led_blink_off = duration;
3647 led_cfg->led_group_id = bp->leds[i].led_group_id;
3650 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3652 HWRM_CHECK_RESULT();
3658 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3662 struct hwrm_nvm_get_dir_info_input req = {0};
3663 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3665 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3667 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3669 HWRM_CHECK_RESULT();
3671 *entries = rte_le_to_cpu_32(resp->entries);
3672 *length = rte_le_to_cpu_32(resp->entry_length);
3678 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3681 uint32_t dir_entries;
3682 uint32_t entry_length;
3685 rte_iova_t dma_handle;
3686 struct hwrm_nvm_get_dir_entries_input req = {0};
3687 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3689 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3693 *data++ = dir_entries;
3694 *data++ = entry_length;
3696 memset(data, 0xff, len);
3698 buflen = dir_entries * entry_length;
3699 buf = rte_malloc("nvm_dir", buflen, 0);
3700 rte_mem_lock_page(buf);
3703 dma_handle = rte_mem_virt2iova(buf);
3704 if (dma_handle == RTE_BAD_IOVA) {
3706 "unable to map response address to physical memory\n");
3709 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3710 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3711 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3714 memcpy(data, buf, len > buflen ? buflen : len);
3717 HWRM_CHECK_RESULT();
3723 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3724 uint32_t offset, uint32_t length,
3729 rte_iova_t dma_handle;
3730 struct hwrm_nvm_read_input req = {0};
3731 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3733 buf = rte_malloc("nvm_item", length, 0);
3734 rte_mem_lock_page(buf);
3738 dma_handle = rte_mem_virt2iova(buf);
3739 if (dma_handle == RTE_BAD_IOVA) {
3741 "unable to map response address to physical memory\n");
3744 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3745 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3746 req.dir_idx = rte_cpu_to_le_16(index);
3747 req.offset = rte_cpu_to_le_32(offset);
3748 req.len = rte_cpu_to_le_32(length);
3749 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3751 memcpy(data, buf, length);
3754 HWRM_CHECK_RESULT();
3760 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3763 struct hwrm_nvm_erase_dir_entry_input req = {0};
3764 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3766 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3767 req.dir_idx = rte_cpu_to_le_16(index);
3768 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3769 HWRM_CHECK_RESULT();
3776 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3777 uint16_t dir_ordinal, uint16_t dir_ext,
3778 uint16_t dir_attr, const uint8_t *data,
3782 struct hwrm_nvm_write_input req = {0};
3783 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3784 rte_iova_t dma_handle;
3787 buf = rte_malloc("nvm_write", data_len, 0);
3788 rte_mem_lock_page(buf);
3792 dma_handle = rte_mem_virt2iova(buf);
3793 if (dma_handle == RTE_BAD_IOVA) {
3795 "unable to map response address to physical memory\n");
3798 memcpy(buf, data, data_len);
3800 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3802 req.dir_type = rte_cpu_to_le_16(dir_type);
3803 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3804 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3805 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3806 req.dir_data_length = rte_cpu_to_le_32(data_len);
3807 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3809 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3812 HWRM_CHECK_RESULT();
3819 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3821 uint32_t *count = cbdata;
3823 *count = *count + 1;
3826 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3827 struct bnxt_vnic_info *vnic __rte_unused)
3832 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3836 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3837 &count, bnxt_vnic_count_hwrm_stub);
3842 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3845 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3846 struct hwrm_func_vf_vnic_ids_query_output *resp =
3847 bp->hwrm_cmd_resp_addr;
3850 /* First query all VNIC ids */
3851 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3853 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3854 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3855 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3857 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3860 "unable to map VNIC ID table address to physical memory\n");
3863 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3864 HWRM_CHECK_RESULT();
3865 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3873 * This function queries the VNIC IDs for a specified VF. It then calls
3874 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3875 * Then it calls the hwrm_cb function to program this new vnic configuration.
3877 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3878 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3879 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3881 struct bnxt_vnic_info vnic;
3883 int i, num_vnic_ids;
3888 /* First query all VNIC ids */
3889 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3890 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3891 RTE_CACHE_LINE_SIZE);
3892 if (vnic_ids == NULL)
3895 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3896 rte_mem_lock_page(((char *)vnic_ids) + sz);
3898 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3900 if (num_vnic_ids < 0)
3901 return num_vnic_ids;
3903 /* Retrieve VNIC, update bd_stall then update */
3905 for (i = 0; i < num_vnic_ids; i++) {
3906 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3907 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3908 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3911 if (vnic.mru <= 4) /* Indicates unallocated */
3914 vnic_cb(&vnic, cbdata);
3916 rc = hwrm_cb(bp, &vnic);
3926 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3929 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3930 struct hwrm_func_cfg_input req = {0};
3933 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3935 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3936 req.enables |= rte_cpu_to_le_32(
3937 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3938 req.vlan_antispoof_mode = on ?
3939 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3940 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3941 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3943 HWRM_CHECK_RESULT();
3949 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3951 struct bnxt_vnic_info vnic;
3954 int num_vnic_ids, i;
3958 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3959 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3960 RTE_CACHE_LINE_SIZE);
3961 if (vnic_ids == NULL)
3964 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3965 rte_mem_lock_page(((char *)vnic_ids) + sz);
3967 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3973 * Loop through to find the default VNIC ID.
3974 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3975 * by sending the hwrm_func_qcfg command to the firmware.
3977 for (i = 0; i < num_vnic_ids; i++) {
3978 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3979 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3980 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3981 bp->pf.first_vf_id + vf);
3984 if (vnic.func_default) {
3986 return vnic.fw_vnic_id;
3989 /* Could not find a default VNIC. */
3990 PMD_DRV_LOG(ERR, "No default VNIC\n");
3996 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3998 struct bnxt_filter_info *filter)
4001 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4002 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4003 uint32_t enables = 0;
4005 if (filter->fw_em_filter_id != UINT64_MAX)
4006 bnxt_hwrm_clear_em_filter(bp, filter);
4008 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4010 req.flags = rte_cpu_to_le_32(filter->flags);
4012 enables = filter->enables |
4013 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4014 req.dst_id = rte_cpu_to_le_16(dst_id);
4016 if (filter->ip_addr_type) {
4017 req.ip_addr_type = filter->ip_addr_type;
4018 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4021 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4022 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4024 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4025 memcpy(req.src_macaddr, filter->src_macaddr,
4026 RTE_ETHER_ADDR_LEN);
4028 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4029 memcpy(req.dst_macaddr, filter->dst_macaddr,
4030 RTE_ETHER_ADDR_LEN);
4032 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4033 req.ovlan_vid = filter->l2_ovlan;
4035 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4036 req.ivlan_vid = filter->l2_ivlan;
4038 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4039 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4041 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4042 req.ip_protocol = filter->ip_protocol;
4044 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4045 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4047 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4048 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4050 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4051 req.src_port = rte_cpu_to_be_16(filter->src_port);
4053 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4054 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4056 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4057 req.mirror_vnic_id = filter->mirror_vnic_id;
4059 req.enables = rte_cpu_to_le_32(enables);
4061 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4063 HWRM_CHECK_RESULT();
4065 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4071 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4074 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4075 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4077 if (filter->fw_em_filter_id == UINT64_MAX)
4080 PMD_DRV_LOG(ERR, "Clear EM filter\n");
4081 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4083 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4085 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4087 HWRM_CHECK_RESULT();
4090 filter->fw_em_filter_id = UINT64_MAX;
4091 filter->fw_l2_filter_id = UINT64_MAX;
4096 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4098 struct bnxt_filter_info *filter)
4101 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4102 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4103 bp->hwrm_cmd_resp_addr;
4104 uint32_t enables = 0;
4106 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4107 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4109 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4111 req.flags = rte_cpu_to_le_32(filter->flags);
4113 enables = filter->enables |
4114 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4115 req.dst_id = rte_cpu_to_le_16(dst_id);
4118 if (filter->ip_addr_type) {
4119 req.ip_addr_type = filter->ip_addr_type;
4121 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4124 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4125 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4127 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4128 memcpy(req.src_macaddr, filter->src_macaddr,
4129 RTE_ETHER_ADDR_LEN);
4131 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4132 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4133 //RTE_ETHER_ADDR_LEN);
4135 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4136 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4138 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4139 req.ip_protocol = filter->ip_protocol;
4141 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4142 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4144 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4145 req.src_ipaddr_mask[0] =
4146 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4148 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4149 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4151 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4152 req.dst_ipaddr_mask[0] =
4153 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4155 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4156 req.src_port = rte_cpu_to_le_16(filter->src_port);
4158 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4159 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4161 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4162 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4164 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4165 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4167 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4168 req.mirror_vnic_id = filter->mirror_vnic_id;
4170 req.enables = rte_cpu_to_le_32(enables);
4172 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4174 HWRM_CHECK_RESULT();
4176 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4182 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4183 struct bnxt_filter_info *filter)
4186 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4187 struct hwrm_cfa_ntuple_filter_free_output *resp =
4188 bp->hwrm_cmd_resp_addr;
4190 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4193 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4195 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4197 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4199 HWRM_CHECK_RESULT();
4202 filter->fw_ntuple_filter_id = UINT64_MAX;
4208 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4210 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4211 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4212 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4213 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4214 uint16_t *ring_tbl = vnic->rss_table;
4215 int nr_ctxs = vnic->num_lb_ctxts;
4216 int max_rings = bp->rx_nr_rings;
4220 for (i = 0, k = 0; i < nr_ctxs; i++) {
4221 struct bnxt_rx_ring_info *rxr;
4222 struct bnxt_cp_ring_info *cpr;
4224 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4226 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4227 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4228 req.hash_mode_flags = vnic->hash_mode;
4230 req.ring_grp_tbl_addr =
4231 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4232 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4233 2 * sizeof(*ring_tbl));
4234 req.hash_key_tbl_addr =
4235 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4237 req.ring_table_pair_index = i;
4238 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4240 for (j = 0; j < 64; j++) {
4243 /* Find next active ring. */
4244 for (cnt = 0; cnt < max_rings; cnt++) {
4245 if (rx_queue_state[k] !=
4246 RTE_ETH_QUEUE_STATE_STOPPED)
4248 if (++k == max_rings)
4252 /* Return if no rings are active. */
4253 if (cnt == max_rings)
4256 /* Add rx/cp ring pair to RSS table. */
4257 rxr = rxqs[k]->rx_ring;
4258 cpr = rxqs[k]->cp_ring;
4260 ring_id = rxr->rx_ring_struct->fw_ring_id;
4261 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4262 ring_id = cpr->cp_ring_struct->fw_ring_id;
4263 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4265 if (++k == max_rings)
4268 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4271 HWRM_CHECK_RESULT();
4278 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4280 unsigned int rss_idx, fw_idx, i;
4282 if (!(vnic->rss_table && vnic->hash_type))
4285 if (BNXT_CHIP_THOR(bp))
4286 return bnxt_vnic_rss_configure_thor(bp, vnic);
4289 * Fill the RSS hash & redirection table with
4290 * ring group ids for all VNICs
4292 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4293 rss_idx++, fw_idx++) {
4294 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4295 fw_idx %= bp->rx_cp_nr_rings;
4296 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4300 if (i == bp->rx_cp_nr_rings)
4302 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4304 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4307 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4308 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4312 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4314 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4315 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4317 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4318 req->num_cmpl_dma_aggr_during_int =
4319 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4321 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4323 /* min timer set to 1/2 of interrupt timer */
4324 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4326 /* buf timer set to 1/4 of interrupt timer */
4327 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4329 req->cmpl_aggr_dma_tmr_during_int =
4330 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4332 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4333 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4334 req->flags = rte_cpu_to_le_16(flags);
4337 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4338 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4340 struct hwrm_ring_aggint_qcaps_input req = {0};
4341 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4346 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4347 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4348 HWRM_CHECK_RESULT();
4350 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4351 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4353 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4354 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4355 agg_req->flags = rte_cpu_to_le_16(flags);
4357 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4358 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4359 agg_req->enables = rte_cpu_to_le_32(enables);
4365 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4366 struct bnxt_coal *coal, uint16_t ring_id)
4368 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4369 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4370 bp->hwrm_cmd_resp_addr;
4373 /* Set ring coalesce parameters only for 100G NICs */
4374 if (BNXT_CHIP_THOR(bp)) {
4375 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4377 } else if (bnxt_stratus_device(bp)) {
4378 bnxt_hwrm_set_coal_params(coal, &req);
4383 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4384 req.ring_id = rte_cpu_to_le_16(ring_id);
4385 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4386 HWRM_CHECK_RESULT();
4391 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4392 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4394 struct hwrm_func_backing_store_qcaps_input req = {0};
4395 struct hwrm_func_backing_store_qcaps_output *resp =
4396 bp->hwrm_cmd_resp_addr;
4397 struct bnxt_ctx_pg_info *ctx_pg;
4398 struct bnxt_ctx_mem_info *ctx;
4399 int total_alloc_len;
4402 if (!BNXT_CHIP_THOR(bp) ||
4403 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4408 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4409 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4410 HWRM_CHECK_RESULT_SILENT();
4412 total_alloc_len = sizeof(*ctx);
4413 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4414 RTE_CACHE_LINE_SIZE);
4420 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4421 sizeof(*ctx_pg) * BNXT_MAX_Q,
4422 RTE_CACHE_LINE_SIZE);
4427 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4428 ctx->tqm_mem[i] = ctx_pg;
4431 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4432 ctx->qp_min_qp1_entries =
4433 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4434 ctx->qp_max_l2_entries =
4435 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4436 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4437 ctx->srq_max_l2_entries =
4438 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4439 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4440 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4441 ctx->cq_max_l2_entries =
4442 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4443 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4444 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4445 ctx->vnic_max_vnic_entries =
4446 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4447 ctx->vnic_max_ring_table_entries =
4448 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4449 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4450 ctx->stat_max_entries =
4451 rte_le_to_cpu_32(resp->stat_max_entries);
4452 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4453 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4454 ctx->tqm_min_entries_per_ring =
4455 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4456 ctx->tqm_max_entries_per_ring =
4457 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4458 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4459 if (!ctx->tqm_entries_multiple)
4460 ctx->tqm_entries_multiple = 1;
4461 ctx->mrav_max_entries =
4462 rte_le_to_cpu_32(resp->mrav_max_entries);
4463 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4464 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4465 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4471 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4473 struct hwrm_func_backing_store_cfg_input req = {0};
4474 struct hwrm_func_backing_store_cfg_output *resp =
4475 bp->hwrm_cmd_resp_addr;
4476 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4477 struct bnxt_ctx_pg_info *ctx_pg;
4478 uint32_t *num_entries;
4487 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4488 req.enables = rte_cpu_to_le_32(enables);
4490 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4491 ctx_pg = &ctx->qp_mem;
4492 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4493 req.qp_num_qp1_entries =
4494 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4495 req.qp_num_l2_entries =
4496 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4497 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4498 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4499 &req.qpc_pg_size_qpc_lvl,
4503 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4504 ctx_pg = &ctx->srq_mem;
4505 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4506 req.srq_num_l2_entries =
4507 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4508 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4509 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4510 &req.srq_pg_size_srq_lvl,
4514 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4515 ctx_pg = &ctx->cq_mem;
4516 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4517 req.cq_num_l2_entries =
4518 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4519 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4520 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4521 &req.cq_pg_size_cq_lvl,
4525 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4526 ctx_pg = &ctx->vnic_mem;
4527 req.vnic_num_vnic_entries =
4528 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4529 req.vnic_num_ring_table_entries =
4530 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4531 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4532 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4533 &req.vnic_pg_size_vnic_lvl,
4534 &req.vnic_page_dir);
4537 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4538 ctx_pg = &ctx->stat_mem;
4539 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4540 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4541 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4542 &req.stat_pg_size_stat_lvl,
4543 &req.stat_page_dir);
4546 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4547 num_entries = &req.tqm_sp_num_entries;
4548 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4549 pg_dir = &req.tqm_sp_page_dir;
4550 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4551 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4552 if (!(enables & ena))
4555 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4557 ctx_pg = ctx->tqm_mem[i];
4558 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4559 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4562 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4563 HWRM_CHECK_RESULT();
4569 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4571 struct hwrm_port_qstats_ext_input req = {0};
4572 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4573 struct bnxt_pf_info *pf = &bp->pf;
4576 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4577 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4580 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4582 req.port_id = rte_cpu_to_le_16(pf->port_id);
4583 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4584 req.tx_stat_host_addr =
4585 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4587 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4589 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4590 req.rx_stat_host_addr =
4591 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4593 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4595 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4598 bp->fw_rx_port_stats_ext_size = 0;
4599 bp->fw_tx_port_stats_ext_size = 0;
4601 bp->fw_rx_port_stats_ext_size =
4602 rte_le_to_cpu_16(resp->rx_stat_size);
4603 bp->fw_tx_port_stats_ext_size =
4604 rte_le_to_cpu_16(resp->tx_stat_size);
4607 HWRM_CHECK_RESULT();
4614 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4616 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4617 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4618 bp->hwrm_cmd_resp_addr;
4621 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4622 req.tunnel_type = type;
4623 req.dest_fid = bp->fw_fid;
4624 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4625 HWRM_CHECK_RESULT();
4633 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4635 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4636 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4637 bp->hwrm_cmd_resp_addr;
4640 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4641 req.tunnel_type = type;
4642 req.dest_fid = bp->fw_fid;
4643 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4644 HWRM_CHECK_RESULT();
4651 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4653 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4654 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4655 bp->hwrm_cmd_resp_addr;
4658 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4659 req.src_fid = bp->fw_fid;
4660 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4661 HWRM_CHECK_RESULT();
4664 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4671 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4674 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4675 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4676 bp->hwrm_cmd_resp_addr;
4679 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4680 req.src_fid = bp->fw_fid;
4681 req.tunnel_type = tun_type;
4682 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4683 HWRM_CHECK_RESULT();
4686 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4688 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4695 int bnxt_hwrm_set_mac(struct bnxt *bp)
4697 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4698 struct hwrm_func_vf_cfg_input req = {0};
4704 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4707 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4708 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4710 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4712 HWRM_CHECK_RESULT();
4714 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4720 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4722 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4723 struct hwrm_func_drv_if_change_input req = {0};
4727 if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4730 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4731 * If we issue FUNC_DRV_IF_CHANGE with flags down before
4732 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4734 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4737 HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4741 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4743 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4745 HWRM_CHECK_RESULT();
4746 flags = rte_le_to_cpu_32(resp->flags);
4749 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4750 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4751 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4757 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4759 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4760 struct bnxt_error_recovery_info *info = bp->recovery_info;
4761 struct hwrm_error_recovery_qcfg_input req = {0};
4766 /* Older FW does not have error recovery support */
4767 if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4771 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4773 bp->recovery_info = info;
4777 memset(info, 0, sizeof(*info));
4780 HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4782 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4784 HWRM_CHECK_RESULT();
4786 flags = rte_le_to_cpu_32(resp->flags);
4787 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4788 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4789 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4790 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4792 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4793 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4798 /* FW returned values are in units of 100msec */
4799 info->driver_polling_freq =
4800 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4801 info->master_func_wait_period =
4802 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4803 info->normal_func_wait_period =
4804 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4805 info->master_func_wait_period_after_reset =
4806 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4807 info->max_bailout_time_after_reset =
4808 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4809 info->status_regs[BNXT_FW_STATUS_REG] =
4810 rte_le_to_cpu_32(resp->fw_health_status_reg);
4811 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4812 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4813 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4814 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4815 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4816 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4817 info->reg_array_cnt =
4818 rte_le_to_cpu_32(resp->reg_array_cnt);
4820 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4825 for (i = 0; i < info->reg_array_cnt; i++) {
4826 info->reset_reg[i] =
4827 rte_le_to_cpu_32(resp->reset_reg[i]);
4828 info->reset_reg_val[i] =
4829 rte_le_to_cpu_32(resp->reset_reg_val[i]);
4830 info->delay_after_reset[i] =
4831 resp->delay_after_reset[i];
4836 /* Map the FW status registers */
4838 rc = bnxt_map_fw_health_status_regs(bp);
4841 rte_free(bp->recovery_info);
4842 bp->recovery_info = NULL;
4847 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4849 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4850 struct hwrm_fw_reset_input req = {0};
4856 HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4858 req.embedded_proc_type =
4859 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4860 req.selfrst_status =
4861 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4862 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4864 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4867 HWRM_CHECK_RESULT();
4873 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4875 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4876 struct hwrm_port_ts_query_input req = {0};
4877 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4884 HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4887 case BNXT_PTP_FLAGS_PATH_TX:
4888 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4890 case BNXT_PTP_FLAGS_PATH_RX:
4891 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4893 case BNXT_PTP_FLAGS_CURRENT_TIME:
4894 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
4898 req.flags = rte_cpu_to_le_32(flags);
4899 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
4901 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4903 HWRM_CHECK_RESULT();
4906 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
4908 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;