drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30 #define HWRM_VERSION_1_10_2_13          0x10a020d
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages == 0)
  68                 return;
  69
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 /*
  79  * HWRM Functions (sent to HWRM)
  80  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  81  * HWRM command times out, or a negative error code if the HWRM
  82  * command was failed by the FW.
  83  */
  84
  85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  86                                   uint32_t msg_len, bool use_kong_mb)
  87 {
  88         unsigned int i;
  89         struct input *req = msg;
  90         struct output *resp = bp->hwrm_cmd_resp_addr;
  91         uint32_t *data = msg;
  92         uint8_t *bar;
  93         uint8_t *valid;
  94         uint16_t max_req_len = bp->max_req_len;
  95         struct hwrm_short_input short_input = { 0 };
  96         uint16_t bar_offset = use_kong_mb ?
  97                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  98         uint16_t mb_trigger_offset = use_kong_mb ?
  99                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 100         uint32_t timeout;
 101
 102         /* Do not send HWRM commands to firmware in error state */
 103         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 104                 return 0;
 105
 106         timeout = bp->hwrm_cmd_timeout;
 107
 108         /* Update the message length for backing store config for new FW. */
 109         if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
 110             rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
 111                 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
 112
 113         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 114             msg_len > bp->max_req_len) {
 115                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 116
 117                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 118                 memcpy(short_cmd_req, req, msg_len);
 119
 120                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 121                 short_input.signature = rte_cpu_to_le_16(
 122                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 123                 short_input.size = rte_cpu_to_le_16(msg_len);
 124                 short_input.req_addr =
 125                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 126
 127                 data = (uint32_t *)&short_input;
 128                 msg_len = sizeof(short_input);
 129
 130                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 131         }
 132
 133         /* Write request msg to hwrm channel */
 134         for (i = 0; i < msg_len; i += 4) {
 135                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 136                 rte_write32(*data, bar);
 137                 data++;
 138         }
 139
 140         /* Zero the rest of the request space */
 141         for (; i < max_req_len; i += 4) {
 142                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 143                 rte_write32(0, bar);
 144         }
 145
 146         /* Ring channel doorbell */
 147         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 148         rte_write32(1, bar);
 149         /*
 150          * Make sure the channel doorbell ring command complete before
 151          * reading the response to avoid getting stale or invalid
 152          * responses.
 153          */
 154         rte_io_mb();
 155
 156         /* Poll for the valid bit */
 157         for (i = 0; i < timeout; i++) {
 158                 /* Sanity check on the resp->resp_len */
 159                 rte_io_rmb();
 160                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 161                         /* Last byte of resp contains the valid key */
 162                         valid = (uint8_t *)resp + resp->resp_len - 1;
 163                         if (*valid == HWRM_RESP_VALID_KEY)
 164                                 break;
 165                 }
 166                 rte_delay_us(1);
 167         }
 168
 169         if (i >= timeout) {
 170                 /* Suppress VER_GET timeout messages during reset recovery */
 171                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 172                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 173                         return -ETIMEDOUT;
 174
 175                 PMD_DRV_LOG(ERR,
 176                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 177                             req->req_type, req->seq_id);
 178                 return -ETIMEDOUT;
 179         }
 180         return 0;
 181 }
 182
 183 /*
 184  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 185  * spinlock, and does initial processing.
 186  *
 187  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 188  * releases the spinlock only if it returns. If the regular int return codes
 189  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 190  * directly, rather it should be copied and modified to suit the function.
 191  *
 192  * HWRM_UNLOCK() must be called after all response processing is completed.
 193  */
 194 #define HWRM_PREP(req, type, kong) do { \
 195         rte_spinlock_lock(&bp->hwrm_lock); \
 196         if (bp->hwrm_cmd_resp_addr == NULL) { \
 197                 rte_spinlock_unlock(&bp->hwrm_lock); \
 198                 return -EACCES; \
 199         } \
 200         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 201         (req)->req_type = rte_cpu_to_le_16(type); \
 202         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 203         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 204                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 205         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 206         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 207 } while (0)
 208
 209 #define HWRM_CHECK_RESULT_SILENT() do {\
 210         if (rc) { \
 211                 rte_spinlock_unlock(&bp->hwrm_lock); \
 212                 return rc; \
 213         } \
 214         if (resp->error_code) { \
 215                 rc = rte_le_to_cpu_16(resp->error_code); \
 216                 rte_spinlock_unlock(&bp->hwrm_lock); \
 217                 return rc; \
 218         } \
 219 } while (0)
 220
 221 #define HWRM_CHECK_RESULT() do {\
 222         if (rc) { \
 223                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 224                 rte_spinlock_unlock(&bp->hwrm_lock); \
 225                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 226                         rc = -EACCES; \
 227                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 228                         rc = -ENOSPC; \
 229                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 230                         rc = -EINVAL; \
 231                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 232                         rc = -ENOTSUP; \
 233                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 234                         rc = -EAGAIN; \
 235                 else if (rc > 0) \
 236                         rc = -EIO; \
 237                 return rc; \
 238         } \
 239         if (resp->error_code) { \
 240                 rc = rte_le_to_cpu_16(resp->error_code); \
 241                 if (resp->resp_len >= 16) { \
 242                         struct hwrm_err_output *tmp_hwrm_err_op = \
 243                                                 (void *)resp; \
 244                         PMD_DRV_LOG(ERR, \
 245                                 "error %d:%d:%08x:%04x\n", \
 246                                 rc, tmp_hwrm_err_op->cmd_err, \
 247                                 rte_le_to_cpu_32(\
 248                                         tmp_hwrm_err_op->opaque_0), \
 249                                 rte_le_to_cpu_16(\
 250                                         tmp_hwrm_err_op->opaque_1)); \
 251                 } else { \
 252                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 253                 } \
 254                 rte_spinlock_unlock(&bp->hwrm_lock); \
 255                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 256                         rc = -EACCES; \
 257                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 258                         rc = -ENOSPC; \
 259                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 260                         rc = -EINVAL; \
 261                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 262                         rc = -ENOTSUP; \
 263                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 264                         rc = -EAGAIN; \
 265                 else if (rc > 0) \
 266                         rc = -EIO; \
 267                 return rc; \
 268         } \
 269 } while (0)
 270
 271 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 272
 273 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 274                                 bool use_kong_mb,
 275                                 uint16_t msg_type,
 276                                 void *msg,
 277                                 uint32_t msg_len,
 278                                 void *resp_msg,
 279                                 uint32_t resp_len)
 280 {
 281         int rc = 0;
 282         bool mailbox = BNXT_USE_CHIMP_MB;
 283         struct input *req = msg;
 284         struct output *resp = bp->hwrm_cmd_resp_addr;
 285
 286         if (use_kong_mb)
 287                 mailbox = BNXT_USE_KONG(bp);
 288
 289         HWRM_PREP(req, msg_type, mailbox);
 290
 291         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 292
 293         HWRM_CHECK_RESULT();
 294
 295         if (resp_msg)
 296                 memcpy(resp_msg, resp, resp_len);
 297
 298         HWRM_UNLOCK();
 299
 300         return rc;
 301 }
 302
 303 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 304                                   bool use_kong_mb,
 305                                   uint16_t tf_type,
 306                                   uint16_t tf_subtype,
 307                                   uint32_t *tf_response_code,
 308                                   void *msg,
 309                                   uint32_t msg_len,
 310                                   void *response,
 311                                   uint32_t response_len)
 312 {
 313         int rc = 0;
 314         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 315         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 316         bool mailbox = BNXT_USE_CHIMP_MB;
 317
 318         if (msg_len > sizeof(req.tf_req))
 319                 return -ENOMEM;
 320
 321         if (use_kong_mb)
 322                 mailbox = BNXT_USE_KONG(bp);
 323
 324         HWRM_PREP(&req, HWRM_TF, mailbox);
 325         /* Build request using the user supplied request payload.
 326          * TLV request size is checked at build time against HWRM
 327          * request max size, thus no checking required.
 328          */
 329         req.tf_type = tf_type;
 330         req.tf_subtype = tf_subtype;
 331         memcpy(req.tf_req, msg, msg_len);
 332
 333         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 334         HWRM_CHECK_RESULT();
 335
 336         /* Copy the resp to user provided response buffer */
 337         if (response != NULL)
 338                 /* Post process response data. We need to copy only
 339                  * the 'payload' as the HWRM data structure really is
 340                  * HWRM header + msg header + payload and the TFLIB
 341                  * only provided a payload place holder.
 342                  */
 343                 if (response_len != 0) {
 344                         memcpy(response,
 345                                resp->tf_resp,
 346                                response_len);
 347                 }
 348
 349         /* Extract the internal tflib response code */
 350         *tf_response_code = resp->tf_resp_code;
 351         HWRM_UNLOCK();
 352
 353         return rc;
 354 }
 355
 356 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 357 {
 358         int rc = 0;
 359         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 360         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 361
 362         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 363         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 364         req.mask = 0;
 365
 366         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 367
 368         HWRM_CHECK_RESULT();
 369         HWRM_UNLOCK();
 370
 371         return rc;
 372 }
 373
 374 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 375                                  struct bnxt_vnic_info *vnic,
 376                                  uint16_t vlan_count,
 377                                  struct bnxt_vlan_table_entry *vlan_table)
 378 {
 379         int rc = 0;
 380         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 381         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 382         uint32_t mask = 0;
 383
 384         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 385                 return rc;
 386
 387         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 388         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 389
 390         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 391                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 392         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 393                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 394
 395         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 396                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 397
 398         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 399                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 400         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 401                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 402                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 403                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 404         }
 405         if (vlan_table) {
 406                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 407                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 408                 req.vlan_tag_tbl_addr =
 409                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 410                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 411         }
 412         req.mask = rte_cpu_to_le_32(mask);
 413
 414         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 415
 416         HWRM_CHECK_RESULT();
 417         HWRM_UNLOCK();
 418
 419         return rc;
 420 }
 421
 422 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 423                         uint16_t vlan_count,
 424                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 425 {
 426         int rc = 0;
 427         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 428         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 429                                                 bp->hwrm_cmd_resp_addr;
 430
 431         /*
 432          * Older HWRM versions did not support this command, and the set_rx_mask
 433          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 434          * removed from set_rx_mask call, and this command was added.
 435          *
 436          * This command is also present from 1.7.8.11 and higher,
 437          * as well as 1.7.8.0
 438          */
 439         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 440                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 441                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 442                                         (11)))
 443                                 return 0;
 444                 }
 445         }
 446         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 447         req.fid = rte_cpu_to_le_16(fid);
 448
 449         req.vlan_tag_mask_tbl_addr =
 450                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 451         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 452
 453         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 454
 455         HWRM_CHECK_RESULT();
 456         HWRM_UNLOCK();
 457
 458         return rc;
 459 }
 460
 461 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 462                              struct bnxt_filter_info *filter)
 463 {
 464         int rc = 0;
 465         struct bnxt_filter_info *l2_filter = filter;
 466         struct bnxt_vnic_info *vnic = NULL;
 467         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 468         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 469
 470         if (filter->fw_l2_filter_id == UINT64_MAX)
 471                 return 0;
 472
 473         if (filter->matching_l2_fltr_ptr)
 474                 l2_filter = filter->matching_l2_fltr_ptr;
 475
 476         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 477                     filter, l2_filter, l2_filter->l2_ref_cnt);
 478
 479         if (l2_filter->l2_ref_cnt == 0)
 480                 return 0;
 481
 482         if (l2_filter->l2_ref_cnt > 0)
 483                 l2_filter->l2_ref_cnt--;
 484
 485         if (l2_filter->l2_ref_cnt > 0)
 486                 return 0;
 487
 488         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 489
 490         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 491
 492         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 493
 494         HWRM_CHECK_RESULT();
 495         HWRM_UNLOCK();
 496
 497         filter->fw_l2_filter_id = UINT64_MAX;
 498         if (l2_filter->l2_ref_cnt == 0) {
 499                 vnic = l2_filter->vnic;
 500                 if (vnic) {
 501                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 502                                       bnxt_filter_info, next);
 503                         bnxt_free_filter(bp, l2_filter);
 504                 }
 505         }
 506
 507         return 0;
 508 }
 509
 510 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 511                          uint16_t dst_id,
 512                          struct bnxt_filter_info *filter)
 513 {
 514         int rc = 0;
 515         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 516         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 517         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 518         const struct rte_eth_vmdq_rx_conf *conf =
 519                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 520         uint32_t enables = 0;
 521         uint16_t j = dst_id - 1;
 522
 523         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 524         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 525             conf->pool_map[j].pools & (1UL << j)) {
 526                 PMD_DRV_LOG(DEBUG,
 527                         "Add vlan %u to vmdq pool %u\n",
 528                         conf->pool_map[j].vlan_id, j);
 529
 530                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 531                 filter->enables |=
 532                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 533                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 534         }
 535
 536         if (filter->fw_l2_filter_id != UINT64_MAX)
 537                 bnxt_hwrm_clear_l2_filter(bp, filter);
 538
 539         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 540
 541         /* PMD does not support XDP and RoCE */
 542         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 543                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 544         req.flags = rte_cpu_to_le_32(filter->flags);
 545
 546         enables = filter->enables |
 547               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 548         req.dst_id = rte_cpu_to_le_16(dst_id);
 549
 550         if (enables &
 551             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 552                 memcpy(req.l2_addr, filter->l2_addr,
 553                        RTE_ETHER_ADDR_LEN);
 554         if (enables &
 555             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 556                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 557                        RTE_ETHER_ADDR_LEN);
 558         if (enables &
 559             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 560                 req.l2_ovlan = filter->l2_ovlan;
 561         if (enables &
 562             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 563                 req.l2_ivlan = filter->l2_ivlan;
 564         if (enables &
 565             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 566                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 567         if (enables &
 568             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 569                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 570         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 571                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 572         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 573                 req.src_type = filter->src_type;
 574         if (filter->pri_hint) {
 575                 req.pri_hint = filter->pri_hint;
 576                 req.l2_filter_id_hint =
 577                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 578         }
 579
 580         req.enables = rte_cpu_to_le_32(enables);
 581
 582         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 583
 584         HWRM_CHECK_RESULT();
 585
 586         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 587         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 588         HWRM_UNLOCK();
 589
 590         filter->l2_ref_cnt++;
 591
 592         return rc;
 593 }
 594
 595 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 596 {
 597         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 598         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 599         uint32_t flags = 0;
 600         int rc;
 601
 602         if (!ptp)
 603                 return 0;
 604
 605         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 606
 607         if (ptp->rx_filter)
 608                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 609         else
 610                 flags |=
 611                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 612         if (ptp->tx_tstamp_en)
 613                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 614         else
 615                 flags |=
 616                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 617         req.flags = rte_cpu_to_le_32(flags);
 618         req.enables = rte_cpu_to_le_32
 619                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 620         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 621
 622         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 623         HWRM_UNLOCK();
 624
 625         return rc;
 626 }
 627
 628 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 629 {
 630         int rc = 0;
 631         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 632         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 633         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 634
 635         if (ptp)
 636                 return 0;
 637
 638         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 639
 640         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 641
 642         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 643
 644         HWRM_CHECK_RESULT();
 645
 646         if (!BNXT_CHIP_P5(bp) &&
 647             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 648                 return 0;
 649
 650         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 651                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 652
 653         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 654         if (!ptp)
 655                 return -ENOMEM;
 656
 657         if (!BNXT_CHIP_P5(bp)) {
 658                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 659                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 660                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 661                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 662                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 663                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 664                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 665                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 666                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 667                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 668                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 669                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 670                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 671                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 672                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 673                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 674                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 675                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 676         }
 677
 678         ptp->bp = bp;
 679         bp->ptp_cfg = ptp;
 680
 681         return 0;
 682 }
 683
 684 void bnxt_hwrm_free_vf_info(struct bnxt *bp)
 685 {
 686         int i;
 687
 688         for (i = 0; i < bp->pf->max_vfs; i++) {
 689                 rte_free(bp->pf->vf_info[i].vlan_table);
 690                 bp->pf->vf_info[i].vlan_table = NULL;
 691                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 692                 bp->pf->vf_info[i].vlan_as_table = NULL;
 693         }
 694         rte_free(bp->pf->vf_info);
 695         bp->pf->vf_info = NULL;
 696 }
 697
 698 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 699 {
 700         int rc = 0;
 701         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 702         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 703         uint16_t new_max_vfs;
 704         uint32_t flags;
 705         int i;
 706
 707         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 708
 709         req.fid = rte_cpu_to_le_16(0xffff);
 710
 711         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 712
 713         HWRM_CHECK_RESULT();
 714
 715         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 716         flags = rte_le_to_cpu_32(resp->flags);
 717         if (BNXT_PF(bp)) {
 718                 bp->pf->port_id = resp->port_id;
 719                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 720                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 721                 new_max_vfs = bp->pdev->max_vfs;
 722                 if (new_max_vfs != bp->pf->max_vfs) {
 723                         if (bp->pf->vf_info)
 724                                 bnxt_hwrm_free_vf_info(bp);
 725                         bp->pf->vf_info = rte_zmalloc("bnxt_vf_info",
 726                             sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
 727                         if (bp->pf->vf_info == NULL) {
 728                                 PMD_DRV_LOG(ERR, "Alloc vf info fail\n");
 729                                 HWRM_UNLOCK();
 730                                 return -ENOMEM;
 731                         }
 732                         bp->pf->max_vfs = new_max_vfs;
 733                         for (i = 0; i < new_max_vfs; i++) {
 734                                 bp->pf->vf_info[i].fid =
 735                                         bp->pf->first_vf_id + i;
 736                                 bp->pf->vf_info[i].vlan_table =
 737                                         rte_zmalloc("VF VLAN table",
 738                                                     getpagesize(),
 739                                                     getpagesize());
 740                                 if (bp->pf->vf_info[i].vlan_table == NULL)
 741                                         PMD_DRV_LOG(ERR,
 742                                         "Fail to alloc VLAN table for VF %d\n",
 743                                         i);
 744                                 else
 745                                         rte_mem_lock_page(
 746                                                 bp->pf->vf_info[i].vlan_table);
 747                                 bp->pf->vf_info[i].vlan_as_table =
 748                                         rte_zmalloc("VF VLAN AS table",
 749                                                     getpagesize(),
 750                                                     getpagesize());
 751                                 if (bp->pf->vf_info[i].vlan_as_table == NULL)
 752                                         PMD_DRV_LOG(ERR,
 753                                         "Alloc VLAN AS table for VF %d fail\n",
 754                                         i);
 755                                 else
 756                                         rte_mem_lock_page(
 757                                               bp->pf->vf_info[i].vlan_as_table);
 758                                 STAILQ_INIT(&bp->pf->vf_info[i].filter);
 759                         }
 760                 }
 761         }
 762
 763         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 764         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 765                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 766                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 767         } else {
 768                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 769         }
 770         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 771         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 772         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 773         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 774         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 775         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 776         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 777         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
 778                 bp->max_l2_ctx += bp->max_rx_em_flows;
 779         /* TODO: For now, do not support VMDq/RFS on VFs. */
 780         if (BNXT_PF(bp)) {
 781                 if (bp->pf->max_vfs)
 782                         bp->max_vnics = 1;
 783                 else
 784                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 785         } else {
 786                 bp->max_vnics = 1;
 787         }
 788         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 789                     bp->max_l2_ctx, bp->max_vnics);
 790         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 791         if (BNXT_PF(bp)) {
 792                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 793                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 794                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 795                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 796                         HWRM_UNLOCK();
 797                         bnxt_hwrm_ptp_qcfg(bp);
 798                 }
 799         }
 800
 801         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 802                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 803
 804         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 805                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 806                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 807         }
 808
 809         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 810                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 811
 812         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 813                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 814
 815         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
 816                 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
 817
 818         HWRM_UNLOCK();
 819
 820         return rc;
 821 }
 822
 823 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 824 {
 825         int rc;
 826
 827         rc = __bnxt_hwrm_func_qcaps(bp);
 828         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 829                 rc = bnxt_alloc_ctx_mem(bp);
 830                 if (rc)
 831                         return rc;
 832
 833                 /* On older FW,
 834                  * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 835                  * But the error can be ignored. Return success.
 836                  */
 837                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 838                 if (!rc)
 839                         bp->flags |= BNXT_FLAG_NEW_RM;
 840         }
 841
 842         return 0;
 843 }
 844
 845 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 846 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 847 {
 848         int rc = 0;
 849         uint32_t flags;
 850         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 851         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 852
 853         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 854
 855         req.target_id = rte_cpu_to_le_16(0xffff);
 856
 857         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 858
 859         HWRM_CHECK_RESULT();
 860
 861         flags = rte_le_to_cpu_32(resp->flags);
 862
 863         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 864                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 865                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 866         }
 867
 868         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
 869                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
 870
 871         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
 872                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
 873
 874         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 875
 876         HWRM_UNLOCK();
 877
 878         return rc;
 879 }
 880
 881 int bnxt_hwrm_func_reset(struct bnxt *bp)
 882 {
 883         int rc = 0;
 884         struct hwrm_func_reset_input req = {.req_type = 0 };
 885         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 886
 887         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
 888
 889         req.enables = rte_cpu_to_le_32(0);
 890
 891         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 892
 893         HWRM_CHECK_RESULT();
 894         HWRM_UNLOCK();
 895
 896         return rc;
 897 }
 898
 899 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 900 {
 901         int rc;
 902         uint32_t flags = 0;
 903         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 904         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 905
 906         if (bp->flags & BNXT_FLAG_REGISTERED)
 907                 return 0;
 908
 909         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 910                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 911         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 912                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 913
 914         /* PFs and trusted VFs should indicate the support of the
 915          * Master capability on non Stingray platform
 916          */
 917         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 918                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 919
 920         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 921         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 922                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 923         req.ver_maj = RTE_VER_YEAR;
 924         req.ver_min = RTE_VER_MONTH;
 925         req.ver_upd = RTE_VER_MINOR;
 926
 927         if (BNXT_PF(bp)) {
 928                 req.enables |= rte_cpu_to_le_32(
 929                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 930                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
 931                        RTE_MIN(sizeof(req.vf_req_fwd),
 932                                sizeof(bp->pf->vf_req_fwd)));
 933         }
 934
 935         req.flags = rte_cpu_to_le_32(flags);
 936
 937         req.async_event_fwd[0] |=
 938                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 939                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 940                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 941                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 942                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 943         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 944                 req.async_event_fwd[0] |=
 945                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 946         req.async_event_fwd[1] |=
 947                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 948                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 949         if (BNXT_PF(bp))
 950                 req.async_event_fwd[1] |=
 951                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 952
 953         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
 954                 req.async_event_fwd[1] |=
 955                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
 956
 957         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 958
 959         HWRM_CHECK_RESULT();
 960
 961         flags = rte_le_to_cpu_32(resp->flags);
 962         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 963                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 964
 965         HWRM_UNLOCK();
 966
 967         bp->flags |= BNXT_FLAG_REGISTERED;
 968
 969         return rc;
 970 }
 971
 972 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 973 {
 974         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 975                 return 0;
 976
 977         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 978 }
 979
 980 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 981 {
 982         int rc;
 983         uint32_t flags = 0;
 984         uint32_t enables;
 985         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 986         struct hwrm_func_vf_cfg_input req = {0};
 987
 988         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 989
 990         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 991                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 992                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 993                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 994                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 995
 996         if (BNXT_HAS_RING_GRPS(bp)) {
 997                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 998                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 999         }
1000
1001         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1002         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1003                                             AGG_RING_MULTIPLIER);
1004         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1005         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1006                                               bp->tx_nr_rings +
1007                                               BNXT_NUM_ASYNC_CPR(bp));
1008         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1009         if (bp->vf_resv_strategy ==
1010             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1011                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1012                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1013                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1014                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1015                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1016                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1017         } else if (bp->vf_resv_strategy ==
1018                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1019                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1020                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1021         }
1022
1023         if (test)
1024                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1025                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1026                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1027                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1028                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1029                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1030
1031         if (test && BNXT_HAS_RING_GRPS(bp))
1032                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1033
1034         req.flags = rte_cpu_to_le_32(flags);
1035         req.enables |= rte_cpu_to_le_32(enables);
1036
1037         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1038
1039         if (test)
1040                 HWRM_CHECK_RESULT_SILENT();
1041         else
1042                 HWRM_CHECK_RESULT();
1043
1044         HWRM_UNLOCK();
1045         return rc;
1046 }
1047
1048 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1049 {
1050         int rc;
1051         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1052         struct hwrm_func_resource_qcaps_input req = {0};
1053
1054         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1055         req.fid = rte_cpu_to_le_16(0xffff);
1056
1057         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1058
1059         HWRM_CHECK_RESULT_SILENT();
1060
1061         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1062         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1063         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1064         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1065         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1066         /* func_resource_qcaps does not return max_rx_em_flows.
1067          * So use the value provided by func_qcaps.
1068          */
1069         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1070         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1071                 bp->max_l2_ctx += bp->max_rx_em_flows;
1072         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1073         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1074         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1075         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1076         if (bp->vf_resv_strategy >
1077             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1078                 bp->vf_resv_strategy =
1079                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1080
1081         HWRM_UNLOCK();
1082         return rc;
1083 }
1084
1085 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1086 {
1087         int rc = 0;
1088         struct hwrm_ver_get_input req = {.req_type = 0 };
1089         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1090         uint32_t fw_version;
1091         uint16_t max_resp_len;
1092         char type[RTE_MEMZONE_NAMESIZE];
1093         uint32_t dev_caps_cfg;
1094
1095         bp->max_req_len = HWRM_MAX_REQ_LEN;
1096         bp->hwrm_cmd_timeout = timeout;
1097         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1098
1099         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1100         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1101         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1102
1103         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1104
1105         if (bp->flags & BNXT_FLAG_FW_RESET)
1106                 HWRM_CHECK_RESULT_SILENT();
1107         else
1108                 HWRM_CHECK_RESULT();
1109
1110         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1111                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1112                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1113                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1114                 resp->hwrm_fw_rsvd_8b);
1115         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1116                      (resp->hwrm_fw_min_8b << 16) |
1117                      (resp->hwrm_fw_bld_8b << 8) |
1118                      resp->hwrm_fw_rsvd_8b;
1119         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1120                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1121
1122         fw_version = resp->hwrm_intf_maj_8b << 16;
1123         fw_version |= resp->hwrm_intf_min_8b << 8;
1124         fw_version |= resp->hwrm_intf_upd_8b;
1125         bp->hwrm_spec_code = fw_version;
1126
1127         /* def_req_timeout value is in milliseconds */
1128         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1129         /* convert timeout to usec */
1130         bp->hwrm_cmd_timeout *= 1000;
1131         if (!bp->hwrm_cmd_timeout)
1132                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1133
1134         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1135                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1136                 rc = -EINVAL;
1137                 goto error;
1138         }
1139
1140         if (bp->max_req_len > resp->max_req_win_len) {
1141                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1142                 rc = -EINVAL;
1143         }
1144
1145         bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1146
1147         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1148         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1149         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1150                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1151
1152         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1153         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1154
1155         if (bp->max_resp_len != max_resp_len) {
1156                 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1157                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1158                         bp->pdev->addr.devid, bp->pdev->addr.function);
1159
1160                 rte_free(bp->hwrm_cmd_resp_addr);
1161
1162                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1163                 if (bp->hwrm_cmd_resp_addr == NULL) {
1164                         rc = -ENOMEM;
1165                         goto error;
1166                 }
1167                 bp->hwrm_cmd_resp_dma_addr =
1168                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1169                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1170                         PMD_DRV_LOG(ERR,
1171                         "Unable to map response buffer to physical memory.\n");
1172                         rc = -ENOMEM;
1173                         goto error;
1174                 }
1175                 bp->max_resp_len = max_resp_len;
1176         }
1177
1178         if ((dev_caps_cfg &
1179                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1180             (dev_caps_cfg &
1181              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1182                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1183                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1184         }
1185
1186         if (((dev_caps_cfg &
1187               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1188              (dev_caps_cfg &
1189               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1190             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1191                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1192                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1193                         bp->pdev->addr.devid, bp->pdev->addr.function);
1194
1195                 rte_free(bp->hwrm_short_cmd_req_addr);
1196
1197                 bp->hwrm_short_cmd_req_addr =
1198                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1199                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1200                         rc = -ENOMEM;
1201                         goto error;
1202                 }
1203                 bp->hwrm_short_cmd_req_dma_addr =
1204                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1205                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1206                         rte_free(bp->hwrm_short_cmd_req_addr);
1207                         PMD_DRV_LOG(ERR,
1208                                 "Unable to map buffer to physical memory.\n");
1209                         rc = -ENOMEM;
1210                         goto error;
1211                 }
1212         }
1213         if (dev_caps_cfg &
1214             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1215                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1216                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1217         }
1218         if (dev_caps_cfg &
1219             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1220                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1221         if (dev_caps_cfg &
1222             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1223                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1224                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1225         }
1226
1227         if (dev_caps_cfg &
1228             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1229                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1230                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1231         }
1232
1233 error:
1234         HWRM_UNLOCK();
1235         return rc;
1236 }
1237
1238 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1239 {
1240         int rc;
1241         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1242         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1243
1244         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1245                 return 0;
1246
1247         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1248         req.flags = flags;
1249
1250         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1251
1252         HWRM_CHECK_RESULT();
1253         HWRM_UNLOCK();
1254
1255         return rc;
1256 }
1257
1258 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1259 {
1260         int rc = 0;
1261         struct hwrm_port_phy_cfg_input req = {0};
1262         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1263         uint32_t enables = 0;
1264
1265         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1266
1267         if (conf->link_up) {
1268                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1269                 if (bp->link_info->auto_mode && conf->link_speed) {
1270                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1271                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1272                 }
1273
1274                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1275                 /*
1276                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1277                  * any auto mode, even "none".
1278                  */
1279                 if (!conf->link_speed) {
1280                         /* No speeds specified. Enable AutoNeg - all speeds */
1281                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1282                         req.auto_mode =
1283                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1284                 } else {
1285                         if (bp->link_info->link_signal_mode) {
1286                                 enables |=
1287                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1288                                 req.force_pam4_link_speed =
1289                                         rte_cpu_to_le_16(conf->link_speed);
1290                         } else {
1291                                 req.force_link_speed =
1292                                         rte_cpu_to_le_16(conf->link_speed);
1293                         }
1294                 }
1295                 /* AutoNeg - Advertise speeds specified. */
1296                 if (conf->auto_link_speed_mask &&
1297                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1298                         req.auto_mode =
1299                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1300                         req.auto_link_speed_mask =
1301                                 conf->auto_link_speed_mask;
1302                         if (conf->auto_pam4_link_speeds) {
1303                                 enables |=
1304                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1305                                 req.auto_link_pam4_speed_mask =
1306                                         conf->auto_pam4_link_speeds;
1307                         } else {
1308                                 enables |=
1309                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1310                         }
1311                 }
1312                 if (conf->auto_link_speed &&
1313                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1314                         enables |=
1315                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1316
1317                 req.auto_duplex = conf->duplex;
1318                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1319                 req.auto_pause = conf->auto_pause;
1320                 req.force_pause = conf->force_pause;
1321                 /* Set force_pause if there is no auto or if there is a force */
1322                 if (req.auto_pause && !req.force_pause)
1323                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1324                 else
1325                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1326
1327                 req.enables = rte_cpu_to_le_32(enables);
1328         } else {
1329                 req.flags =
1330                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1331                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1332         }
1333
1334         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1335
1336         HWRM_CHECK_RESULT();
1337         HWRM_UNLOCK();
1338
1339         PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1340                     bp->eth_dev->data->port_id);
1341         return rc;
1342 }
1343
1344 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1345                                    struct bnxt_link_info *link_info)
1346 {
1347         int rc = 0;
1348         struct hwrm_port_phy_qcfg_input req = {0};
1349         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1350
1351         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1352
1353         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1354
1355         HWRM_CHECK_RESULT();
1356
1357         link_info->phy_link_status = resp->link;
1358         link_info->link_up =
1359                 (link_info->phy_link_status ==
1360                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1361         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1362         link_info->duplex = resp->duplex_cfg;
1363         link_info->pause = resp->pause;
1364         link_info->auto_pause = resp->auto_pause;
1365         link_info->force_pause = resp->force_pause;
1366         link_info->auto_mode = resp->auto_mode;
1367         link_info->phy_type = resp->phy_type;
1368         link_info->media_type = resp->media_type;
1369
1370         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1371         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1372         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1373         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1374         link_info->phy_ver[0] = resp->phy_maj;
1375         link_info->phy_ver[1] = resp->phy_min;
1376         link_info->phy_ver[2] = resp->phy_bld;
1377         link_info->link_signal_mode =
1378                 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1379         link_info->force_pam4_link_speed =
1380                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1381         link_info->support_pam4_speeds =
1382                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1383         link_info->auto_pam4_link_speeds =
1384                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1385         HWRM_UNLOCK();
1386
1387         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1388                     link_info->link_speed, link_info->auto_mode,
1389                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1390                     link_info->support_speeds, link_info->force_link_speed);
1391         PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1392                     link_info->link_signal_mode,
1393                     link_info->auto_pam4_link_speeds,
1394                     link_info->support_pam4_speeds,
1395                     link_info->force_pam4_link_speed);
1396         return rc;
1397 }
1398
1399 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1400 {
1401         int rc = 0;
1402         struct hwrm_port_phy_qcaps_input req = {0};
1403         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1404         struct bnxt_link_info *link_info = bp->link_info;
1405
1406         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1407                 return 0;
1408
1409         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1410
1411         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1412
1413         HWRM_CHECK_RESULT();
1414
1415         bp->port_cnt = resp->port_cnt;
1416         if (resp->supported_speeds_auto_mode)
1417                 link_info->support_auto_speeds =
1418                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1419         if (resp->supported_pam4_speeds_auto_mode)
1420                 link_info->support_pam4_auto_speeds =
1421                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1422
1423         HWRM_UNLOCK();
1424
1425         return 0;
1426 }
1427
1428 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1429 {
1430         int i = 0;
1431
1432         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1433                 if (bp->tx_cos_queue[i].profile ==
1434                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1435                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1436                         return true;
1437                 }
1438         }
1439         return false;
1440 }
1441
1442 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1443 {
1444         int i = 0;
1445
1446         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1447                 if (bp->tx_cos_queue[i].profile !=
1448                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1449                     bp->tx_cos_queue[i].id !=
1450                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1451                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1452                         break;
1453                 }
1454         }
1455 }
1456
1457 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1458 {
1459         int rc = 0;
1460         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1461         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1462         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1463         int i;
1464
1465 get_rx_info:
1466         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1467
1468         req.flags = rte_cpu_to_le_32(dir);
1469         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1470         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1471             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1472                 req.drv_qmap_cap =
1473                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1474         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1475
1476         HWRM_CHECK_RESULT();
1477
1478         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1479                 GET_TX_QUEUE_INFO(0);
1480                 GET_TX_QUEUE_INFO(1);
1481                 GET_TX_QUEUE_INFO(2);
1482                 GET_TX_QUEUE_INFO(3);
1483                 GET_TX_QUEUE_INFO(4);
1484                 GET_TX_QUEUE_INFO(5);
1485                 GET_TX_QUEUE_INFO(6);
1486                 GET_TX_QUEUE_INFO(7);
1487         } else  {
1488                 GET_RX_QUEUE_INFO(0);
1489                 GET_RX_QUEUE_INFO(1);
1490                 GET_RX_QUEUE_INFO(2);
1491                 GET_RX_QUEUE_INFO(3);
1492                 GET_RX_QUEUE_INFO(4);
1493                 GET_RX_QUEUE_INFO(5);
1494                 GET_RX_QUEUE_INFO(6);
1495                 GET_RX_QUEUE_INFO(7);
1496         }
1497
1498         HWRM_UNLOCK();
1499
1500         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1501                 goto done;
1502
1503         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1504                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1505         } else {
1506                 int j;
1507
1508                 /* iterate and find the COSq profile to use for Tx */
1509                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1510                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1511                                 if (bp->tx_cos_queue[i].id != 0xff)
1512                                         bp->tx_cosq_id[j++] =
1513                                                 bp->tx_cos_queue[i].id;
1514                         }
1515                 } else {
1516                         /* When CoS classification is disabled, for normal NIC
1517                          * operations, ideally we should look to use LOSSY.
1518                          * If not found, fallback to the first valid profile
1519                          */
1520                         if (!bnxt_find_lossy_profile(bp))
1521                                 bnxt_find_first_valid_profile(bp);
1522
1523                 }
1524         }
1525
1526         bp->max_tc = resp->max_configurable_queues;
1527         bp->max_lltc = resp->max_configurable_lossless_queues;
1528         if (bp->max_tc > BNXT_MAX_QUEUE)
1529                 bp->max_tc = BNXT_MAX_QUEUE;
1530         bp->max_q = bp->max_tc;
1531
1532         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1533                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1534                 goto get_rx_info;
1535         }
1536
1537 done:
1538         return rc;
1539 }
1540
1541 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1542                          struct bnxt_ring *ring,
1543                          uint32_t ring_type, uint32_t map_index,
1544                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1545                          uint16_t tx_cosq_id)
1546 {
1547         int rc = 0;
1548         uint32_t enables = 0;
1549         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1550         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1551         struct rte_mempool *mb_pool;
1552         uint16_t rx_buf_size;
1553
1554         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1555
1556         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1557         req.fbo = rte_cpu_to_le_32(0);
1558         /* Association of ring index with doorbell index */
1559         req.logical_id = rte_cpu_to_le_16(map_index);
1560         req.length = rte_cpu_to_le_32(ring->ring_size);
1561
1562         switch (ring_type) {
1563         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1564                 req.ring_type = ring_type;
1565                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1566                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1567                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1568                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1569                         enables |=
1570                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1571                 break;
1572         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1573                 req.ring_type = ring_type;
1574                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1575                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1576                 if (BNXT_CHIP_P5(bp)) {
1577                         mb_pool = bp->rx_queues[0]->mb_pool;
1578                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1579                                       RTE_PKTMBUF_HEADROOM;
1580                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1581                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1582                         enables |=
1583                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1584                 }
1585                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1586                         enables |=
1587                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1588                 break;
1589         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1590                 req.ring_type = ring_type;
1591                 if (BNXT_HAS_NQ(bp)) {
1592                         /* Association of cp ring with nq */
1593                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1594                         enables |=
1595                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1596                 }
1597                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1598                 break;
1599         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1600                 req.ring_type = ring_type;
1601                 req.page_size = BNXT_PAGE_SHFT;
1602                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1603                 break;
1604         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1605                 req.ring_type = ring_type;
1606                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1607
1608                 mb_pool = bp->rx_queues[0]->mb_pool;
1609                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1610                               RTE_PKTMBUF_HEADROOM;
1611                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1612                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1613
1614                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1615                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1616                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1617                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1618                 break;
1619         default:
1620                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1621                         ring_type);
1622                 HWRM_UNLOCK();
1623                 return -EINVAL;
1624         }
1625         req.enables = rte_cpu_to_le_32(enables);
1626
1627         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1628
1629         if (rc || resp->error_code) {
1630                 if (rc == 0 && resp->error_code)
1631                         rc = rte_le_to_cpu_16(resp->error_code);
1632                 switch (ring_type) {
1633                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1634                         PMD_DRV_LOG(ERR,
1635                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1636                         HWRM_UNLOCK();
1637                         return rc;
1638                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1639                         PMD_DRV_LOG(ERR,
1640                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1641                         HWRM_UNLOCK();
1642                         return rc;
1643                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1644                         PMD_DRV_LOG(ERR,
1645                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1646                                     rc);
1647                         HWRM_UNLOCK();
1648                         return rc;
1649                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1650                         PMD_DRV_LOG(ERR,
1651                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1652                         HWRM_UNLOCK();
1653                         return rc;
1654                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1655                         PMD_DRV_LOG(ERR,
1656                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1657                         HWRM_UNLOCK();
1658                         return rc;
1659                 default:
1660                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1661                         HWRM_UNLOCK();
1662                         return rc;
1663                 }
1664         }
1665
1666         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1667         HWRM_UNLOCK();
1668         return rc;
1669 }
1670
1671 int bnxt_hwrm_ring_free(struct bnxt *bp,
1672                         struct bnxt_ring *ring, uint32_t ring_type)
1673 {
1674         int rc;
1675         struct hwrm_ring_free_input req = {.req_type = 0 };
1676         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1677
1678         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1679
1680         req.ring_type = ring_type;
1681         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1682
1683         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1684
1685         if (rc || resp->error_code) {
1686                 if (rc == 0 && resp->error_code)
1687                         rc = rte_le_to_cpu_16(resp->error_code);
1688                 HWRM_UNLOCK();
1689
1690                 switch (ring_type) {
1691                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1692                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1693                                 rc);
1694                         return rc;
1695                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1696                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1697                                 rc);
1698                         return rc;
1699                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1700                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1701                                 rc);
1702                         return rc;
1703                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1704                         PMD_DRV_LOG(ERR,
1705                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1706                         return rc;
1707                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1708                         PMD_DRV_LOG(ERR,
1709                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1710                         return rc;
1711                 default:
1712                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1713                         return rc;
1714                 }
1715         }
1716         HWRM_UNLOCK();
1717         return 0;
1718 }
1719
1720 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1721 {
1722         int rc = 0;
1723         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1724         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1725
1726         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1727
1728         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1729         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1730         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1731         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1732
1733         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1734
1735         HWRM_CHECK_RESULT();
1736
1737         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1738
1739         HWRM_UNLOCK();
1740
1741         return rc;
1742 }
1743
1744 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1745 {
1746         int rc;
1747         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1748         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1749
1750         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1751
1752         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1753
1754         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1755
1756         HWRM_CHECK_RESULT();
1757         HWRM_UNLOCK();
1758
1759         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1760         return rc;
1761 }
1762
1763 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1764 {
1765         int rc = 0;
1766         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1767         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1768
1769         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1770                 return rc;
1771
1772         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1773
1774         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1775
1776         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1777
1778         HWRM_CHECK_RESULT();
1779         HWRM_UNLOCK();
1780
1781         return rc;
1782 }
1783
1784 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1785                                 unsigned int idx __rte_unused)
1786 {
1787         int rc;
1788         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1789         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1790
1791         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1792
1793         req.update_period_ms = rte_cpu_to_le_32(0);
1794
1795         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1796
1797         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1798
1799         HWRM_CHECK_RESULT();
1800
1801         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1802
1803         HWRM_UNLOCK();
1804
1805         return rc;
1806 }
1807
1808 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1809                                 unsigned int idx __rte_unused)
1810 {
1811         int rc;
1812         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1813         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1814
1815         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1816
1817         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1818
1819         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1820
1821         HWRM_CHECK_RESULT();
1822         HWRM_UNLOCK();
1823
1824         return rc;
1825 }
1826
1827 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1828 {
1829         int rc = 0, i, j;
1830         struct hwrm_vnic_alloc_input req = { 0 };
1831         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1832
1833         if (!BNXT_HAS_RING_GRPS(bp))
1834                 goto skip_ring_grps;
1835
1836         /* map ring groups to this vnic */
1837         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1838                 vnic->start_grp_id, vnic->end_grp_id);
1839         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1840                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1841
1842         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1843         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1844         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1845         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1846
1847 skip_ring_grps:
1848         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1849         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1850
1851         if (vnic->func_default)
1852                 req.flags =
1853                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1854         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1855
1856         HWRM_CHECK_RESULT();
1857
1858         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1859         HWRM_UNLOCK();
1860         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1861         return rc;
1862 }
1863
1864 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1865                                         struct bnxt_vnic_info *vnic,
1866                                         struct bnxt_plcmodes_cfg *pmode)
1867 {
1868         int rc = 0;
1869         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1870         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1871
1872         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1873
1874         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1875
1876         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1877
1878         HWRM_CHECK_RESULT();
1879
1880         pmode->flags = rte_le_to_cpu_32(resp->flags);
1881         /* dflt_vnic bit doesn't exist in the _cfg command */
1882         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1883         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1884         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1885         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1886
1887         HWRM_UNLOCK();
1888
1889         return rc;
1890 }
1891
1892 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1893                                        struct bnxt_vnic_info *vnic,
1894                                        struct bnxt_plcmodes_cfg *pmode)
1895 {
1896         int rc = 0;
1897         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1898         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1899
1900         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1901                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1902                 return rc;
1903         }
1904
1905         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1906
1907         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1908         req.flags = rte_cpu_to_le_32(pmode->flags);
1909         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1910         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1911         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1912         req.enables = rte_cpu_to_le_32(
1913             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1914             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1915             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1916         );
1917
1918         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1919
1920         HWRM_CHECK_RESULT();
1921         HWRM_UNLOCK();
1922
1923         return rc;
1924 }
1925
1926 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1927 {
1928         int rc = 0;
1929         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1930         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1931         struct bnxt_plcmodes_cfg pmodes = { 0 };
1932         uint32_t ctx_enable_flag = 0;
1933         uint32_t enables = 0;
1934
1935         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1936                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1937                 return rc;
1938         }
1939
1940         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1941         if (rc)
1942                 return rc;
1943
1944         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1945
1946         if (BNXT_CHIP_P5(bp)) {
1947                 int dflt_rxq = vnic->start_grp_id;
1948                 struct bnxt_rx_ring_info *rxr;
1949                 struct bnxt_cp_ring_info *cpr;
1950                 struct bnxt_rx_queue *rxq;
1951                 int i;
1952
1953                 /*
1954                  * The first active receive ring is used as the VNIC
1955                  * default receive ring. If there are no active receive
1956                  * rings (all corresponding receive queues are stopped),
1957                  * the first receive ring is used.
1958                  */
1959                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1960                         rxq = bp->eth_dev->data->rx_queues[i];
1961                         if (rxq->rx_started) {
1962                                 dflt_rxq = i;
1963                                 break;
1964                         }
1965                 }
1966
1967                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1968                 rxr = rxq->rx_ring;
1969                 cpr = rxq->cp_ring;
1970
1971                 req.default_rx_ring_id =
1972                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1973                 req.default_cmpl_ring_id =
1974                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1975                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1976                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1977                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
1978                         enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
1979                         req.rx_csum_v2_mode =
1980                                 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
1981                 }
1982                 goto config_mru;
1983         }
1984
1985         /* Only RSS support for now TBD: COS & LB */
1986         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1987         if (vnic->lb_rule != 0xffff)
1988                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1989         if (vnic->cos_rule != 0xffff)
1990                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1991         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1992                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1993                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1994         }
1995         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1996                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1997                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1998         }
1999
2000         enables |= ctx_enable_flag;
2001         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2002         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2003         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2004         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2005
2006 config_mru:
2007         req.enables = rte_cpu_to_le_32(enables);
2008         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2009         req.mru = rte_cpu_to_le_16(vnic->mru);
2010         /* Configure default VNIC only once. */
2011         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2012                 req.flags |=
2013                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2014                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2015         }
2016         if (vnic->vlan_strip)
2017                 req.flags |=
2018                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2019         if (vnic->bd_stall)
2020                 req.flags |=
2021                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2022         if (vnic->rss_dflt_cr)
2023                 req.flags |= rte_cpu_to_le_32(
2024                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2025
2026         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2027
2028         HWRM_CHECK_RESULT();
2029         HWRM_UNLOCK();
2030
2031         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2032
2033         return rc;
2034 }
2035
2036 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2037                 int16_t fw_vf_id)
2038 {
2039         int rc = 0;
2040         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2041         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2042
2043         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2044                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2045                 return rc;
2046         }
2047         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2048
2049         req.enables =
2050                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2051         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2052         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2053
2054         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2055
2056         HWRM_CHECK_RESULT();
2057
2058         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2059         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2060         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2061         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2062         vnic->mru = rte_le_to_cpu_16(resp->mru);
2063         vnic->func_default = rte_le_to_cpu_32(
2064                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2065         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2066                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2067         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2068                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2069         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2070                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2071
2072         HWRM_UNLOCK();
2073
2074         return rc;
2075 }
2076
2077 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2078                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2079 {
2080         int rc = 0;
2081         uint16_t ctx_id;
2082         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2083         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2084                                                 bp->hwrm_cmd_resp_addr;
2085
2086         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2087
2088         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2089         HWRM_CHECK_RESULT();
2090
2091         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2092         if (!BNXT_HAS_RING_GRPS(bp))
2093                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2094         else if (ctx_idx == 0)
2095                 vnic->rss_rule = ctx_id;
2096
2097         HWRM_UNLOCK();
2098
2099         return rc;
2100 }
2101
2102 static
2103 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2104                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2105 {
2106         int rc = 0;
2107         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2108         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2109                                                 bp->hwrm_cmd_resp_addr;
2110
2111         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2112                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2113                 return rc;
2114         }
2115         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2116
2117         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2118
2119         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2120
2121         HWRM_CHECK_RESULT();
2122         HWRM_UNLOCK();
2123
2124         return rc;
2125 }
2126
2127 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2128 {
2129         int rc = 0;
2130
2131         if (BNXT_CHIP_P5(bp)) {
2132                 int j;
2133
2134                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2135                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2136                                                       vnic,
2137                                                       vnic->fw_grp_ids[j]);
2138                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2139                 }
2140                 vnic->num_lb_ctxts = 0;
2141         } else {
2142                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2143                 vnic->rss_rule = INVALID_HW_RING_ID;
2144         }
2145
2146         return rc;
2147 }
2148
2149 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2150 {
2151         int rc = 0;
2152         struct hwrm_vnic_free_input req = {.req_type = 0 };
2153         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2154
2155         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2156                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2157                 return rc;
2158         }
2159
2160         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2161
2162         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2163
2164         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2165
2166         HWRM_CHECK_RESULT();
2167         HWRM_UNLOCK();
2168
2169         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2170         /* Configure default VNIC again if necessary. */
2171         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2172                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2173
2174         return rc;
2175 }
2176
2177 static int
2178 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2179 {
2180         int i;
2181         int rc = 0;
2182         int nr_ctxs = vnic->num_lb_ctxts;
2183         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2184         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2185
2186         for (i = 0; i < nr_ctxs; i++) {
2187                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2188
2189                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2190                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2191                 req.hash_mode_flags = vnic->hash_mode;
2192
2193                 req.hash_key_tbl_addr =
2194                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2195
2196                 req.ring_grp_tbl_addr =
2197                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2198                                          i * HW_HASH_INDEX_SIZE);
2199                 req.ring_table_pair_index = i;
2200                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2201
2202                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2203                                             BNXT_USE_CHIMP_MB);
2204
2205                 HWRM_CHECK_RESULT();
2206                 HWRM_UNLOCK();
2207         }
2208
2209         return rc;
2210 }
2211
2212 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2213                            struct bnxt_vnic_info *vnic)
2214 {
2215         int rc = 0;
2216         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2217         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2218
2219         if (!vnic->rss_table)
2220                 return 0;
2221
2222         if (BNXT_CHIP_P5(bp))
2223                 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2224
2225         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2226
2227         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2228         req.hash_mode_flags = vnic->hash_mode;
2229
2230         req.ring_grp_tbl_addr =
2231             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2232         req.hash_key_tbl_addr =
2233             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2234         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2235         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2236
2237         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2238
2239         HWRM_CHECK_RESULT();
2240         HWRM_UNLOCK();
2241
2242         return rc;
2243 }
2244
2245 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2246                         struct bnxt_vnic_info *vnic)
2247 {
2248         int rc = 0;
2249         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2250         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2251         uint16_t size;
2252
2253         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2254                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2255                 return rc;
2256         }
2257
2258         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2259
2260         req.flags = rte_cpu_to_le_32(
2261                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2262
2263         req.enables = rte_cpu_to_le_32(
2264                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2265
2266         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2267         size -= RTE_PKTMBUF_HEADROOM;
2268         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2269
2270         req.jumbo_thresh = rte_cpu_to_le_16(size);
2271         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2272
2273         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2274
2275         HWRM_CHECK_RESULT();
2276         HWRM_UNLOCK();
2277
2278         return rc;
2279 }
2280
2281 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2282                         struct bnxt_vnic_info *vnic, bool enable)
2283 {
2284         int rc = 0;
2285         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2286         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2287
2288         if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2289                 if (enable)
2290                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2291                 return -ENOTSUP;
2292         }
2293
2294         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2295                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2296                 return 0;
2297         }
2298
2299         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2300
2301         if (enable) {
2302                 req.enables = rte_cpu_to_le_32(
2303                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2304                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2305                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2306                 req.flags = rte_cpu_to_le_32(
2307                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2308                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2309                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2310                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2311                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2312                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2313                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2314                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2315                 req.min_agg_len = rte_cpu_to_le_32(512);
2316         }
2317         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2318
2319         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2320
2321         HWRM_CHECK_RESULT();
2322         HWRM_UNLOCK();
2323
2324         return rc;
2325 }
2326
2327 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2328 {
2329         struct hwrm_func_cfg_input req = {0};
2330         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2331         int rc;
2332
2333         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2334         req.enables = rte_cpu_to_le_32(
2335                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2336         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2337         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2338
2339         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2340
2341         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2342         HWRM_CHECK_RESULT();
2343         HWRM_UNLOCK();
2344
2345         bp->pf->vf_info[vf].random_mac = false;
2346
2347         return rc;
2348 }
2349
2350 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2351                                   uint64_t *dropped)
2352 {
2353         int rc = 0;
2354         struct hwrm_func_qstats_input req = {.req_type = 0};
2355         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2356
2357         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2358
2359         req.fid = rte_cpu_to_le_16(fid);
2360
2361         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2362
2363         HWRM_CHECK_RESULT();
2364
2365         if (dropped)
2366                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2367
2368         HWRM_UNLOCK();
2369
2370         return rc;
2371 }
2372
2373 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2374                           struct rte_eth_stats *stats,
2375                           struct hwrm_func_qstats_output *func_qstats)
2376 {
2377         int rc = 0;
2378         struct hwrm_func_qstats_input req = {.req_type = 0};
2379         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2380
2381         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2382
2383         req.fid = rte_cpu_to_le_16(fid);
2384
2385         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2386
2387         HWRM_CHECK_RESULT();
2388         if (func_qstats)
2389                 memcpy(func_qstats, resp,
2390                        sizeof(struct hwrm_func_qstats_output));
2391
2392         if (!stats)
2393                 goto exit;
2394
2395         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2396         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2397         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2398         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2399         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2400         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2401
2402         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2403         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2404         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2405         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2406         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2407         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2408
2409         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2410         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2411         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2412
2413 exit:
2414         HWRM_UNLOCK();
2415
2416         return rc;
2417 }
2418
2419 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2420 {
2421         int rc = 0;
2422         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2423         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2424
2425         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2426
2427         req.fid = rte_cpu_to_le_16(fid);
2428
2429         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2430
2431         HWRM_CHECK_RESULT();
2432         HWRM_UNLOCK();
2433
2434         return rc;
2435 }
2436
2437 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2438 {
2439         unsigned int i;
2440         int rc = 0;
2441
2442         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2443                 struct bnxt_tx_queue *txq;
2444                 struct bnxt_rx_queue *rxq;
2445                 struct bnxt_cp_ring_info *cpr;
2446
2447                 if (i >= bp->rx_cp_nr_rings) {
2448                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2449                         cpr = txq->cp_ring;
2450                 } else {
2451                         rxq = bp->rx_queues[i];
2452                         cpr = rxq->cp_ring;
2453                 }
2454
2455                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2456                 if (rc)
2457                         return rc;
2458         }
2459         return 0;
2460 }
2461
2462 static int
2463 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2464 {
2465         int rc;
2466         unsigned int i;
2467         struct bnxt_cp_ring_info *cpr;
2468
2469         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2470
2471                 if (i >= bp->rx_cp_nr_rings) {
2472                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2473                 } else {
2474                         cpr = bp->rx_queues[i]->cp_ring;
2475                         if (BNXT_HAS_RING_GRPS(bp))
2476                                 bp->grp_info[i].fw_stats_ctx = -1;
2477                 }
2478                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2479                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2480                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2481                         if (rc)
2482                                 return rc;
2483                 }
2484         }
2485         return 0;
2486 }
2487
2488 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2489 {
2490         unsigned int i;
2491         int rc = 0;
2492
2493         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2494                 struct bnxt_tx_queue *txq;
2495                 struct bnxt_rx_queue *rxq;
2496                 struct bnxt_cp_ring_info *cpr;
2497
2498                 if (i >= bp->rx_cp_nr_rings) {
2499                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2500                         cpr = txq->cp_ring;
2501                 } else {
2502                         rxq = bp->rx_queues[i];
2503                         cpr = rxq->cp_ring;
2504                 }
2505
2506                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2507
2508                 if (rc)
2509                         return rc;
2510         }
2511         return rc;
2512 }
2513
2514 static int
2515 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2516 {
2517         uint16_t idx;
2518         uint32_t rc = 0;
2519
2520         if (!BNXT_HAS_RING_GRPS(bp))
2521                 return 0;
2522
2523         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2524
2525                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2526                         continue;
2527
2528                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2529
2530                 if (rc)
2531                         return rc;
2532         }
2533         return rc;
2534 }
2535
2536 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2537 {
2538         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2539
2540         bnxt_hwrm_ring_free(bp, cp_ring,
2541                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2542         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2543         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2544                                      sizeof(*cpr->cp_desc_ring));
2545         cpr->cp_raw_cons = 0;
2546         cpr->valid = 0;
2547 }
2548
2549 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2550 {
2551         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2552
2553         bnxt_hwrm_ring_free(bp, cp_ring,
2554                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2555         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2556         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2557                         sizeof(*cpr->cp_desc_ring));
2558         cpr->cp_raw_cons = 0;
2559         cpr->valid = 0;
2560 }
2561
2562 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2563 {
2564         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2565         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2566         struct bnxt_ring *ring = rxr->rx_ring_struct;
2567         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2568
2569         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2570                 bnxt_hwrm_ring_free(bp, ring,
2571                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2572                 ring->fw_ring_id = INVALID_HW_RING_ID;
2573                 if (BNXT_HAS_RING_GRPS(bp))
2574                         bp->grp_info[queue_index].rx_fw_ring_id =
2575                                                         INVALID_HW_RING_ID;
2576         }
2577         ring = rxr->ag_ring_struct;
2578         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2579                 bnxt_hwrm_ring_free(bp, ring,
2580                                     BNXT_CHIP_P5(bp) ?
2581                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2582                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2583                 if (BNXT_HAS_RING_GRPS(bp))
2584                         bp->grp_info[queue_index].ag_fw_ring_id =
2585                                                         INVALID_HW_RING_ID;
2586         }
2587         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2588                 bnxt_free_cp_ring(bp, cpr);
2589
2590         if (BNXT_HAS_RING_GRPS(bp))
2591                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2592 }
2593
2594 static int
2595 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2596 {
2597         unsigned int i;
2598
2599         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2600                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2601                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2602                 struct bnxt_ring *ring = txr->tx_ring_struct;
2603                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2604
2605                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2606                         bnxt_hwrm_ring_free(bp, ring,
2607                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2608                         ring->fw_ring_id = INVALID_HW_RING_ID;
2609                         memset(txr->tx_desc_ring, 0,
2610                                         txr->tx_ring_struct->ring_size *
2611                                         sizeof(*txr->tx_desc_ring));
2612                         memset(txr->tx_buf_ring, 0,
2613                                         txr->tx_ring_struct->ring_size *
2614                                         sizeof(*txr->tx_buf_ring));
2615                         txr->tx_raw_prod = 0;
2616                         txr->tx_raw_cons = 0;
2617                 }
2618                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2619                         bnxt_free_cp_ring(bp, cpr);
2620                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2621                 }
2622         }
2623
2624         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2625                 bnxt_free_hwrm_rx_ring(bp, i);
2626
2627         return 0;
2628 }
2629
2630 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2631 {
2632         uint16_t i;
2633         uint32_t rc = 0;
2634
2635         if (!BNXT_HAS_RING_GRPS(bp))
2636                 return 0;
2637
2638         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2639                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2640                 if (rc)
2641                         return rc;
2642         }
2643         return rc;
2644 }
2645
2646 /*
2647  * HWRM utility functions
2648  */
2649
2650 void bnxt_free_hwrm_resources(struct bnxt *bp)
2651 {
2652         /* Release memzone */
2653         rte_free(bp->hwrm_cmd_resp_addr);
2654         rte_free(bp->hwrm_short_cmd_req_addr);
2655         bp->hwrm_cmd_resp_addr = NULL;
2656         bp->hwrm_short_cmd_req_addr = NULL;
2657         bp->hwrm_cmd_resp_dma_addr = 0;
2658         bp->hwrm_short_cmd_req_dma_addr = 0;
2659 }
2660
2661 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2662 {
2663         struct rte_pci_device *pdev = bp->pdev;
2664         char type[RTE_MEMZONE_NAMESIZE];
2665
2666         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2667                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2668         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2669         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2670         if (bp->hwrm_cmd_resp_addr == NULL)
2671                 return -ENOMEM;
2672         bp->hwrm_cmd_resp_dma_addr =
2673                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2674         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2675                 PMD_DRV_LOG(ERR,
2676                         "unable to map response address to physical memory\n");
2677                 return -ENOMEM;
2678         }
2679         rte_spinlock_init(&bp->hwrm_lock);
2680
2681         return 0;
2682 }
2683
2684 int
2685 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2686 {
2687         int rc = 0;
2688
2689         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2690                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2691                 if (rc)
2692                         return rc;
2693         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2694                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2695                 if (rc)
2696                         return rc;
2697         }
2698
2699         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2700         return rc;
2701 }
2702
2703 static int
2704 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2705 {
2706         struct bnxt_filter_info *filter;
2707         int rc = 0;
2708
2709         STAILQ_FOREACH(filter, &vnic->filter, next) {
2710                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2711                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2712                 bnxt_free_filter(bp, filter);
2713         }
2714         return rc;
2715 }
2716
2717 static int
2718 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2719 {
2720         struct bnxt_filter_info *filter;
2721         struct rte_flow *flow;
2722         int rc = 0;
2723
2724         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2725                 flow = STAILQ_FIRST(&vnic->flow_list);
2726                 filter = flow->filter;
2727                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2728                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2729
2730                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2731                 rte_free(flow);
2732         }
2733         return rc;
2734 }
2735
2736 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2737 {
2738         struct bnxt_filter_info *filter;
2739         int rc = 0;
2740
2741         STAILQ_FOREACH(filter, &vnic->filter, next) {
2742                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2743                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2744                                                      filter);
2745                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2746                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2747                                                          filter);
2748                 else
2749                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2750                                                      filter);
2751                 if (rc)
2752                         break;
2753         }
2754         return rc;
2755 }
2756
2757 static void
2758 bnxt_free_tunnel_ports(struct bnxt *bp)
2759 {
2760         if (bp->vxlan_port_cnt)
2761                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2762                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2763
2764         if (bp->geneve_port_cnt)
2765                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2766                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2767 }
2768
2769 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2770 {
2771         int i;
2772
2773         if (bp->vnic_info == NULL)
2774                 return;
2775
2776         /*
2777          * Cleanup VNICs in reverse order, to make sure the L2 filter
2778          * from vnic0 is last to be cleaned up.
2779          */
2780         for (i = bp->max_vnics - 1; i >= 0; i--) {
2781                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2782
2783                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2784                         continue;
2785
2786                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2787
2788                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2789
2790                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2791
2792                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2793
2794                 bnxt_hwrm_vnic_free(bp, vnic);
2795
2796                 rte_free(vnic->fw_grp_ids);
2797         }
2798         /* Ring resources */
2799         bnxt_free_all_hwrm_rings(bp);
2800         bnxt_free_all_hwrm_ring_grps(bp);
2801         bnxt_free_all_hwrm_stat_ctxs(bp);
2802         bnxt_free_tunnel_ports(bp);
2803 }
2804
2805 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2806 {
2807         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2808
2809         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2810                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2811
2812         switch (conf_link_speed) {
2813         case ETH_LINK_SPEED_10M_HD:
2814         case ETH_LINK_SPEED_100M_HD:
2815                 /* FALLTHROUGH */
2816                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2817         }
2818         return hw_link_duplex;
2819 }
2820
2821 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2822 {
2823         return !conf_link;
2824 }
2825
2826 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2827                                           uint16_t pam4_link)
2828 {
2829         uint16_t eth_link_speed = 0;
2830
2831         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2832                 return ETH_LINK_SPEED_AUTONEG;
2833
2834         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2835         case ETH_LINK_SPEED_100M:
2836         case ETH_LINK_SPEED_100M_HD:
2837                 /* FALLTHROUGH */
2838                 eth_link_speed =
2839                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2840                 break;
2841         case ETH_LINK_SPEED_1G:
2842                 eth_link_speed =
2843                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2844                 break;
2845         case ETH_LINK_SPEED_2_5G:
2846                 eth_link_speed =
2847                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2848                 break;
2849         case ETH_LINK_SPEED_10G:
2850                 eth_link_speed =
2851                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2852                 break;
2853         case ETH_LINK_SPEED_20G:
2854                 eth_link_speed =
2855                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2856                 break;
2857         case ETH_LINK_SPEED_25G:
2858                 eth_link_speed =
2859                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2860                 break;
2861         case ETH_LINK_SPEED_40G:
2862                 eth_link_speed =
2863                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2864                 break;
2865         case ETH_LINK_SPEED_50G:
2866                 eth_link_speed = pam4_link ?
2867                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
2868                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2869                 break;
2870         case ETH_LINK_SPEED_100G:
2871                 eth_link_speed = pam4_link ?
2872                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
2873                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2874                 break;
2875         case ETH_LINK_SPEED_200G:
2876                 eth_link_speed =
2877                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2878                 break;
2879         default:
2880                 PMD_DRV_LOG(ERR,
2881                         "Unsupported link speed %d; default to AUTO\n",
2882                         conf_link_speed);
2883                 break;
2884         }
2885         return eth_link_speed;
2886 }
2887
2888 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2889                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2890                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2891                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2892                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2893
2894 static int bnxt_validate_link_speed(struct bnxt *bp)
2895 {
2896         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2897         uint16_t port_id = bp->eth_dev->data->port_id;
2898         uint32_t link_speed_capa;
2899         uint32_t one_speed;
2900
2901         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2902                 return 0;
2903
2904         link_speed_capa = bnxt_get_speed_capabilities(bp);
2905
2906         if (link_speed & ETH_LINK_SPEED_FIXED) {
2907                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2908
2909                 if (one_speed & (one_speed - 1)) {
2910                         PMD_DRV_LOG(ERR,
2911                                 "Invalid advertised speeds (%u) for port %u\n",
2912                                 link_speed, port_id);
2913                         return -EINVAL;
2914                 }
2915                 if ((one_speed & link_speed_capa) != one_speed) {
2916                         PMD_DRV_LOG(ERR,
2917                                 "Unsupported advertised speed (%u) for port %u\n",
2918                                 link_speed, port_id);
2919                         return -EINVAL;
2920                 }
2921         } else {
2922                 if (!(link_speed & link_speed_capa)) {
2923                         PMD_DRV_LOG(ERR,
2924                                 "Unsupported advertised speeds (%u) for port %u\n",
2925                                 link_speed, port_id);
2926                         return -EINVAL;
2927                 }
2928         }
2929         return 0;
2930 }
2931
2932 static uint16_t
2933 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2934 {
2935         uint16_t ret = 0;
2936
2937         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2938                 if (bp->link_info->support_speeds)
2939                         return bp->link_info->support_speeds;
2940                 link_speed = BNXT_SUPPORTED_SPEEDS;
2941         }
2942
2943         if (link_speed & ETH_LINK_SPEED_100M)
2944                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2945         if (link_speed & ETH_LINK_SPEED_100M_HD)
2946                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2947         if (link_speed & ETH_LINK_SPEED_1G)
2948                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2949         if (link_speed & ETH_LINK_SPEED_2_5G)
2950                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2951         if (link_speed & ETH_LINK_SPEED_10G)
2952                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2953         if (link_speed & ETH_LINK_SPEED_20G)
2954                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2955         if (link_speed & ETH_LINK_SPEED_25G)
2956                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2957         if (link_speed & ETH_LINK_SPEED_40G)
2958                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2959         if (link_speed & ETH_LINK_SPEED_50G)
2960                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2961         if (link_speed & ETH_LINK_SPEED_100G)
2962                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2963         if (link_speed & ETH_LINK_SPEED_200G)
2964                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2965         return ret;
2966 }
2967
2968 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2969 {
2970         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2971
2972         switch (hw_link_speed) {
2973         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2974                 eth_link_speed = ETH_SPEED_NUM_100M;
2975                 break;
2976         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2977                 eth_link_speed = ETH_SPEED_NUM_1G;
2978                 break;
2979         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2980                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2981                 break;
2982         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2983                 eth_link_speed = ETH_SPEED_NUM_10G;
2984                 break;
2985         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2986                 eth_link_speed = ETH_SPEED_NUM_20G;
2987                 break;
2988         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2989                 eth_link_speed = ETH_SPEED_NUM_25G;
2990                 break;
2991         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2992                 eth_link_speed = ETH_SPEED_NUM_40G;
2993                 break;
2994         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2995                 eth_link_speed = ETH_SPEED_NUM_50G;
2996                 break;
2997         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2998                 eth_link_speed = ETH_SPEED_NUM_100G;
2999                 break;
3000         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3001                 eth_link_speed = ETH_SPEED_NUM_200G;
3002                 break;
3003         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3004         default:
3005                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3006                         hw_link_speed);
3007                 break;
3008         }
3009         return eth_link_speed;
3010 }
3011
3012 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3013 {
3014         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3015
3016         switch (hw_link_duplex) {
3017         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3018         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3019                 /* FALLTHROUGH */
3020                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3021                 break;
3022         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3023                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3024                 break;
3025         default:
3026                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3027                         hw_link_duplex);
3028                 break;
3029         }
3030         return eth_link_duplex;
3031 }
3032
3033 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3034 {
3035         int rc = 0;
3036         struct bnxt_link_info *link_info = bp->link_info;
3037
3038         rc = bnxt_hwrm_port_phy_qcaps(bp);
3039         if (rc)
3040                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3041
3042         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3043         if (rc) {
3044                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3045                 goto exit;
3046         }
3047
3048         if (link_info->link_speed)
3049                 link->link_speed =
3050                         bnxt_parse_hw_link_speed(link_info->link_speed);
3051         else
3052                 link->link_speed = ETH_SPEED_NUM_NONE;
3053         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3054         link->link_status = link_info->link_up;
3055         link->link_autoneg = link_info->auto_mode ==
3056                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3057                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3058 exit:
3059         return rc;
3060 }
3061
3062 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3063 {
3064         int rc = 0;
3065         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3066         struct bnxt_link_info link_req;
3067         uint16_t speed, autoneg;
3068
3069         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3070                 return 0;
3071
3072         rc = bnxt_validate_link_speed(bp);
3073         if (rc)
3074                 goto error;
3075
3076         memset(&link_req, 0, sizeof(link_req));
3077         link_req.link_up = link_up;
3078         if (!link_up)
3079                 goto port_phy_cfg;
3080
3081         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3082         if (BNXT_CHIP_P5(bp) &&
3083             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3084                 /* 40G is not supported as part of media auto detect.
3085                  * The speed should be forced and autoneg disabled
3086                  * to configure 40G speed.
3087                  */
3088                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3089                 autoneg = 0;
3090         }
3091
3092         /* No auto speeds and no auto_pam4_link. Disable autoneg */
3093         if (bp->link_info->auto_link_speed == 0 &&
3094             bp->link_info->link_signal_mode &&
3095             bp->link_info->auto_pam4_link_speeds == 0)
3096                 autoneg = 0;
3097
3098         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3099                                           bp->link_info->link_signal_mode);
3100         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3101         /* Autoneg can be done only when the FW allows.
3102          * When user configures fixed speed of 40G and later changes to
3103          * any other speed, auto_link_speed/force_link_speed is still set
3104          * to 40G until link comes up at new speed.
3105          */
3106         if (autoneg == 1 &&
3107             !(!BNXT_CHIP_P5(bp) &&
3108               (bp->link_info->auto_link_speed ||
3109                bp->link_info->force_link_speed))) {
3110                 link_req.phy_flags |=
3111                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3112                 link_req.auto_link_speed_mask =
3113                         bnxt_parse_eth_link_speed_mask(bp,
3114                                                        dev_conf->link_speeds);
3115         } else {
3116                 if (bp->link_info->phy_type ==
3117                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3118                     bp->link_info->phy_type ==
3119                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3120                     bp->link_info->media_type ==
3121                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3122                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3123                         return -EINVAL;
3124                 }
3125
3126                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3127                 /* If user wants a particular speed try that first. */
3128                 if (speed)
3129                         link_req.link_speed = speed;
3130                 else if (bp->link_info->force_pam4_link_speed)
3131                         link_req.link_speed =
3132                                 bp->link_info->force_pam4_link_speed;
3133                 else if (bp->link_info->auto_pam4_link_speeds)
3134                         link_req.link_speed =
3135                                 bp->link_info->auto_pam4_link_speeds;
3136                 else if (bp->link_info->support_pam4_speeds)
3137                         link_req.link_speed =
3138                                 bp->link_info->support_pam4_speeds;
3139                 else if (bp->link_info->force_link_speed)
3140                         link_req.link_speed = bp->link_info->force_link_speed;
3141                 else
3142                         link_req.link_speed = bp->link_info->auto_link_speed;
3143                 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3144                  * zero. Use the auto_link_speed.
3145                  */
3146                 if (bp->link_info->auto_link_speed != 0 &&
3147                     bp->link_info->auto_pam4_link_speeds == 0)
3148                         link_req.link_speed = bp->link_info->auto_link_speed;
3149         }
3150         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3151         link_req.auto_pause = bp->link_info->auto_pause;
3152         link_req.force_pause = bp->link_info->force_pause;
3153
3154 port_phy_cfg:
3155         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3156         if (rc) {
3157                 PMD_DRV_LOG(ERR,
3158                         "Set link config failed with rc %d\n", rc);
3159         }
3160
3161 error:
3162         return rc;
3163 }
3164
3165 /* JIRA 22088 */
3166 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3167 {
3168         struct hwrm_func_qcfg_input req = {0};
3169         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3170         uint16_t flags;
3171         int rc = 0;
3172         bp->func_svif = BNXT_SVIF_INVALID;
3173         uint16_t svif_info;
3174
3175         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3176         req.fid = rte_cpu_to_le_16(0xffff);
3177
3178         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3179
3180         HWRM_CHECK_RESULT();
3181
3182         /* Hard Coded.. 0xfff VLAN ID mask */
3183         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3184
3185         svif_info = rte_le_to_cpu_16(resp->svif_info);
3186         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3187                 bp->func_svif = svif_info &
3188                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3189
3190         flags = rte_le_to_cpu_16(resp->flags);
3191         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3192                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3193
3194         if (BNXT_VF(bp) &&
3195             !BNXT_VF_IS_TRUSTED(bp) &&
3196             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3197                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3198                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3199         } else if (BNXT_VF(bp) &&
3200                    BNXT_VF_IS_TRUSTED(bp) &&
3201                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3202                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3203                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3204         }
3205
3206         if (mtu)
3207                 *mtu = rte_le_to_cpu_16(resp->mtu);
3208
3209         switch (resp->port_partition_type) {
3210         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3211         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3212         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3213                 /* FALLTHROUGH */
3214                 bp->flags |= BNXT_FLAG_NPAR_PF;
3215                 break;
3216         default:
3217                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3218                 break;
3219         }
3220
3221         bp->legacy_db_size =
3222                 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3223
3224         HWRM_UNLOCK();
3225
3226         return rc;
3227 }
3228
3229 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3230 {
3231         struct hwrm_func_qcfg_input req = {0};
3232         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3233         int rc;
3234
3235         if (!BNXT_VF_IS_TRUSTED(bp))
3236                 return 0;
3237
3238         if (!bp->parent)
3239                 return -EINVAL;
3240
3241         bp->parent->fid = BNXT_PF_FID_INVALID;
3242
3243         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3244
3245         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3246
3247         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3248
3249         HWRM_CHECK_RESULT();
3250
3251         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3252         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3253         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3254         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3255
3256         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3257         if (bp->parent->vnic == 0) {
3258                 PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
3259                 /* Use hard-coded values appropriate for current Wh+ fw. */
3260                 if (bp->parent->fid == 2)
3261                         bp->parent->vnic = 0x100;
3262                 else
3263                         bp->parent->vnic = 1;
3264         }
3265
3266         HWRM_UNLOCK();
3267
3268         return 0;
3269 }
3270
3271 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3272                                  uint16_t *vnic_id, uint16_t *svif)
3273 {
3274         struct hwrm_func_qcfg_input req = {0};
3275         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3276         uint16_t svif_info;
3277         int rc = 0;
3278
3279         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3280         req.fid = rte_cpu_to_le_16(fid);
3281
3282         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3283
3284         HWRM_CHECK_RESULT();
3285
3286         if (vnic_id)
3287                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3288
3289         svif_info = rte_le_to_cpu_16(resp->svif_info);
3290         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3291                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3292
3293         HWRM_UNLOCK();
3294
3295         return rc;
3296 }
3297
3298 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3299 {
3300         struct hwrm_port_mac_qcfg_input req = {0};
3301         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3302         uint16_t port_svif_info;
3303         int rc;
3304
3305         bp->port_svif = BNXT_SVIF_INVALID;
3306
3307         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3308                 return 0;
3309
3310         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3311
3312         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3313
3314         HWRM_CHECK_RESULT_SILENT();
3315
3316         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3317         if (port_svif_info &
3318             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3319                 bp->port_svif = port_svif_info &
3320                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3321
3322         HWRM_UNLOCK();
3323
3324         return 0;
3325 }
3326
3327 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3328                                  struct bnxt_pf_resource_info *pf_resc)
3329 {
3330         struct hwrm_func_cfg_input req = {0};
3331         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3332         uint32_t enables;
3333         int rc;
3334
3335         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3336                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3337                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3338                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3339                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3340                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3341                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3342                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3343                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3344
3345         if (BNXT_HAS_RING_GRPS(bp)) {
3346                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3347                 req.num_hw_ring_grps =
3348                         rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3349         } else if (BNXT_HAS_NQ(bp)) {
3350                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3351                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3352         }
3353
3354         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3355         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3356         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3357         req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3358         req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3359         req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3360         req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3361         req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3362         req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3363         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3364         req.fid = rte_cpu_to_le_16(0xffff);
3365         req.enables = rte_cpu_to_le_32(enables);
3366
3367         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3368
3369         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3370
3371         HWRM_CHECK_RESULT();
3372         HWRM_UNLOCK();
3373
3374         return rc;
3375 }
3376
3377 /* min values are the guaranteed resources and max values are subject
3378  * to availability. The strategy for now is to keep both min & max
3379  * values the same.
3380  */
3381 static void
3382 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3383                               struct hwrm_func_vf_resource_cfg_input *req,
3384                               int num_vfs)
3385 {
3386         req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3387                                                (num_vfs + 1));
3388         req->min_rsscos_ctx = req->max_rsscos_ctx;
3389         req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3390         req->min_stat_ctx = req->max_stat_ctx;
3391         req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3392                                                (num_vfs + 1));
3393         req->min_cmpl_rings = req->max_cmpl_rings;
3394         req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3395         req->min_tx_rings = req->max_tx_rings;
3396         req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3397         req->min_rx_rings = req->max_rx_rings;
3398         req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3399         req->min_l2_ctxs = req->max_l2_ctxs;
3400         /* TODO: For now, do not support VMDq/RFS on VFs. */
3401         req->max_vnics = rte_cpu_to_le_16(1);
3402         req->min_vnics = req->max_vnics;
3403         req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3404                                                  (num_vfs + 1));
3405         req->min_hw_ring_grps = req->max_hw_ring_grps;
3406         req->flags =
3407          rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3408 }
3409
3410 static void
3411 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3412                               struct hwrm_func_cfg_input *req,
3413                               int num_vfs)
3414 {
3415         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3416                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3417                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3418                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3419                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3420                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3421                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3422                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3423                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3424                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3425
3426         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3427                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3428                                     BNXT_NUM_VLANS);
3429         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3430         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3431                                                 (num_vfs + 1));
3432         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3433         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3434                                                (num_vfs + 1));
3435         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3436         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3437         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3438         /* TODO: For now, do not support VMDq/RFS on VFs. */
3439         req->num_vnics = rte_cpu_to_le_16(1);
3440         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3441                                                  (num_vfs + 1));
3442 }
3443
3444 /* Update the port wide resource values based on how many resources
3445  * got allocated to the VF.
3446  */
3447 static int bnxt_update_max_resources(struct bnxt *bp,
3448                                      int vf)
3449 {
3450         struct hwrm_func_qcfg_input req = {0};
3451         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3452         int rc;
3453
3454         /* Get the actual allocated values now */
3455         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3456         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3457         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3458         HWRM_CHECK_RESULT();
3459
3460         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3461         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3462         bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3463         bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3464         bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3465         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3466         bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3467
3468         HWRM_UNLOCK();
3469
3470         return 0;
3471 }
3472
3473 /* Update the PF resource values based on how many resources
3474  * got allocated to it.
3475  */
3476 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3477 {
3478         struct hwrm_func_qcfg_input req = {0};
3479         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3480         int rc;
3481
3482         /* Get the actual allocated values now */
3483         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3484         req.fid = rte_cpu_to_le_16(0xffff);
3485         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3486         HWRM_CHECK_RESULT();
3487
3488         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3489         bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3490         bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3491         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3492         bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3493         bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3494         bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3495         bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3496
3497         HWRM_UNLOCK();
3498
3499         return 0;
3500 }
3501
3502 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3503 {
3504         struct hwrm_func_qcfg_input req = {0};
3505         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3506         int rc;
3507
3508         /* Check for zero MAC address */
3509         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3510         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3511         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3512         HWRM_CHECK_RESULT();
3513         rc = rte_le_to_cpu_16(resp->vlan);
3514
3515         HWRM_UNLOCK();
3516
3517         return rc;
3518 }
3519
3520 static int bnxt_query_pf_resources(struct bnxt *bp,
3521                                    struct bnxt_pf_resource_info *pf_resc)
3522 {
3523         struct hwrm_func_qcfg_input req = {0};
3524         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3525         int rc;
3526
3527         /* And copy the allocated numbers into the pf struct */
3528         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3529         req.fid = rte_cpu_to_le_16(0xffff);
3530         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3531         HWRM_CHECK_RESULT();
3532
3533         pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3534         pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3535         pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3536         pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3537         pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3538         pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3539         pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3540         bp->pf->evb_mode = resp->evb_mode;
3541
3542         HWRM_UNLOCK();
3543
3544         return rc;
3545 }
3546
3547 static void
3548 bnxt_calculate_pf_resources(struct bnxt *bp,
3549                             struct bnxt_pf_resource_info *pf_resc,
3550                             int num_vfs)
3551 {
3552         if (!num_vfs) {
3553                 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3554                 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3555                 pf_resc->num_cp_rings = bp->max_cp_rings;
3556                 pf_resc->num_tx_rings = bp->max_tx_rings;
3557                 pf_resc->num_rx_rings = bp->max_rx_rings;
3558                 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3559                 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3560
3561                 return;
3562         }
3563
3564         pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3565                                    bp->max_rsscos_ctx % (num_vfs + 1);
3566         pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3567                                  bp->max_stat_ctx % (num_vfs + 1);
3568         pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3569                                 bp->max_cp_rings % (num_vfs + 1);
3570         pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3571                                 bp->max_tx_rings % (num_vfs + 1);
3572         pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3573                                 bp->max_rx_rings % (num_vfs + 1);
3574         pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3575                                bp->max_l2_ctx % (num_vfs + 1);
3576         pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3577                                     bp->max_ring_grps % (num_vfs + 1);
3578 }
3579
3580 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3581 {
3582         struct bnxt_pf_resource_info pf_resc = { 0 };
3583         int rc;
3584
3585         if (!BNXT_PF(bp)) {
3586                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3587                 return -EINVAL;
3588         }
3589
3590         rc = bnxt_hwrm_func_qcaps(bp);
3591         if (rc)
3592                 return rc;
3593
3594         bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3595
3596         bp->pf->func_cfg_flags &=
3597                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3598                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3599         bp->pf->func_cfg_flags |=
3600                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3601
3602         rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3603         if (rc)
3604                 return rc;
3605
3606         rc = bnxt_update_max_resources_pf_only(bp);
3607
3608         return rc;
3609 }
3610
3611 static int
3612 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3613 {
3614         size_t req_buf_sz, sz;
3615         int i, rc;
3616
3617         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3618         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3619                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3620         if (bp->pf->vf_req_buf == NULL) {
3621                 return -ENOMEM;
3622         }
3623
3624         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3625                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3626
3627         for (i = 0; i < num_vfs; i++)
3628                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3629                                              (i * HWRM_MAX_REQ_LEN);
3630
3631         rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3632         if (rc)
3633                 rte_free(bp->pf->vf_req_buf);
3634
3635         return rc;
3636 }
3637
3638 static int
3639 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3640 {
3641         struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3642         struct hwrm_func_vf_resource_cfg_input req = {0};
3643         int i, rc = 0;
3644
3645         bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3646         bp->pf->active_vfs = 0;
3647         for (i = 0; i < num_vfs; i++) {
3648                 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3649                 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3650                 rc = bnxt_hwrm_send_message(bp,
3651                                             &req,
3652                                             sizeof(req),
3653                                             BNXT_USE_CHIMP_MB);
3654                 if (rc || resp->error_code) {
3655                         PMD_DRV_LOG(ERR,
3656                                 "Failed to initialize VF %d\n", i);
3657                         PMD_DRV_LOG(ERR,
3658                                 "Not all VFs available. (%d, %d)\n",
3659                                 rc, resp->error_code);
3660                         HWRM_UNLOCK();
3661
3662                         /* If the first VF configuration itself fails,
3663                          * unregister the vf_fwd_request buffer.
3664                          */
3665                         if (i == 0)
3666                                 bnxt_hwrm_func_buf_unrgtr(bp);
3667                         break;
3668                 }
3669                 HWRM_UNLOCK();
3670
3671                 /* Update the max resource values based on the resource values
3672                  * allocated to the VF.
3673                  */
3674                 bnxt_update_max_resources(bp, i);
3675                 bp->pf->active_vfs++;
3676                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3677         }
3678
3679         return 0;
3680 }
3681
3682 static int
3683 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3684 {
3685         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3686         struct hwrm_func_cfg_input req = {0};
3687         int i, rc;
3688
3689         bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3690
3691         bp->pf->active_vfs = 0;
3692         for (i = 0; i < num_vfs; i++) {
3693                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3694                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3695                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3696                 rc = bnxt_hwrm_send_message(bp,
3697                                             &req,
3698                                             sizeof(req),
3699                                             BNXT_USE_CHIMP_MB);
3700
3701                 /* Clear enable flag for next pass */
3702                 req.enables &= ~rte_cpu_to_le_32(
3703                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3704
3705                 if (rc || resp->error_code) {
3706                         PMD_DRV_LOG(ERR,
3707                                 "Failed to initialize VF %d\n", i);
3708                         PMD_DRV_LOG(ERR,
3709                                 "Not all VFs available. (%d, %d)\n",
3710                                 rc, resp->error_code);
3711                         HWRM_UNLOCK();
3712
3713                         /* If the first VF configuration itself fails,
3714                          * unregister the vf_fwd_request buffer.
3715                          */
3716                         if (i == 0)
3717                                 bnxt_hwrm_func_buf_unrgtr(bp);
3718                         break;
3719                 }
3720
3721                 HWRM_UNLOCK();
3722
3723                 /* Update the max resource values based on the resource values
3724                  * allocated to the VF.
3725                  */
3726                 bnxt_update_max_resources(bp, i);
3727                 bp->pf->active_vfs++;
3728                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3729         }
3730
3731         return 0;
3732 }
3733
3734 static void
3735 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3736 {
3737         if (bp->flags & BNXT_FLAG_NEW_RM)
3738                 bnxt_process_vf_resc_config_new(bp, num_vfs);
3739         else
3740                 bnxt_process_vf_resc_config_old(bp, num_vfs);
3741 }
3742
3743 static void
3744 bnxt_update_pf_resources(struct bnxt *bp,
3745                          struct bnxt_pf_resource_info *pf_resc)
3746 {
3747         bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3748         bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3749         bp->max_cp_rings = pf_resc->num_cp_rings;
3750         bp->max_tx_rings = pf_resc->num_tx_rings;
3751         bp->max_rx_rings = pf_resc->num_rx_rings;
3752         bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3753 }
3754
3755 static int32_t
3756 bnxt_configure_pf_resources(struct bnxt *bp,
3757                             struct bnxt_pf_resource_info *pf_resc)
3758 {
3759         /*
3760          * We're using STD_TX_RING_MODE here which will limit the TX
3761          * rings. This will allow QoS to function properly. Not setting this
3762          * will cause PF rings to break bandwidth settings.
3763          */
3764         bp->pf->func_cfg_flags &=
3765                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3766                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3767         bp->pf->func_cfg_flags |=
3768                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3769         return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3770 }
3771
3772 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3773 {
3774         struct bnxt_pf_resource_info pf_resc = { 0 };
3775         int rc;
3776
3777         if (!BNXT_PF(bp)) {
3778                 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3779                 return -EINVAL;
3780         }
3781
3782         rc = bnxt_hwrm_func_qcaps(bp);
3783         if (rc)
3784                 return rc;
3785
3786         bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3787
3788         rc = bnxt_configure_pf_resources(bp, &pf_resc);
3789         if (rc)
3790                 return rc;
3791
3792         rc = bnxt_query_pf_resources(bp, &pf_resc);
3793         if (rc)
3794                 return rc;
3795
3796         /*
3797          * Now, create and register a buffer to hold forwarded VF requests
3798          */
3799         rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3800         if (rc)
3801                 return rc;
3802
3803         bnxt_configure_vf_resources(bp, num_vfs);
3804
3805         bnxt_update_pf_resources(bp, &pf_resc);
3806
3807         return 0;
3808 }
3809
3810 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3811 {
3812         struct hwrm_func_cfg_input req = {0};
3813         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3814         int rc;
3815
3816         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3817
3818         req.fid = rte_cpu_to_le_16(0xffff);
3819         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3820         req.evb_mode = bp->pf->evb_mode;
3821
3822         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3823         HWRM_CHECK_RESULT();
3824         HWRM_UNLOCK();
3825
3826         return rc;
3827 }
3828
3829 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3830                                 uint8_t tunnel_type)
3831 {
3832         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3833         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3834         int rc = 0;
3835
3836         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3837         req.tunnel_type = tunnel_type;
3838         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3839         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3840         HWRM_CHECK_RESULT();
3841
3842         switch (tunnel_type) {
3843         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3844                 bp->vxlan_fw_dst_port_id =
3845                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3846                 bp->vxlan_port = port;
3847                 break;
3848         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3849                 bp->geneve_fw_dst_port_id =
3850                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3851                 bp->geneve_port = port;
3852                 break;
3853         default:
3854                 break;
3855         }
3856
3857         HWRM_UNLOCK();
3858
3859         return rc;
3860 }
3861
3862 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3863                                 uint8_t tunnel_type)
3864 {
3865         struct hwrm_tunnel_dst_port_free_input req = {0};
3866         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3867         int rc = 0;
3868
3869         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3870
3871         req.tunnel_type = tunnel_type;
3872         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3873         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3874
3875         HWRM_CHECK_RESULT();
3876         HWRM_UNLOCK();
3877
3878         if (tunnel_type ==
3879             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
3880                 bp->vxlan_port = 0;
3881                 bp->vxlan_port_cnt = 0;
3882         }
3883
3884         if (tunnel_type ==
3885             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
3886                 bp->geneve_port = 0;
3887                 bp->geneve_port_cnt = 0;
3888         }
3889
3890         return rc;
3891 }
3892
3893 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3894                                         uint32_t flags)
3895 {
3896         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3897         struct hwrm_func_cfg_input req = {0};
3898         int rc;
3899
3900         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3901
3902         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3903         req.flags = rte_cpu_to_le_32(flags);
3904         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3905
3906         HWRM_CHECK_RESULT();
3907         HWRM_UNLOCK();
3908
3909         return rc;
3910 }
3911
3912 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3913 {
3914         uint32_t *flag = flagp;
3915
3916         vnic->flags = *flag;
3917 }
3918
3919 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3920 {
3921         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3922 }
3923
3924 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
3925 {
3926         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3927         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3928         int rc;
3929
3930         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3931
3932         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3933         req.req_buf_page_size =
3934                 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
3935         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3936         req.req_buf_page_addr0 =
3937                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3938         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3939                 PMD_DRV_LOG(ERR,
3940                         "unable to map buffer address to physical memory\n");
3941                 HWRM_UNLOCK();
3942                 return -ENOMEM;
3943         }
3944
3945         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3946
3947         HWRM_CHECK_RESULT();
3948         HWRM_UNLOCK();
3949
3950         return rc;
3951 }
3952
3953 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3954 {
3955         int rc = 0;
3956         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3957         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3958
3959         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3960                 return 0;
3961
3962         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3963
3964         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3965
3966         HWRM_CHECK_RESULT();
3967         HWRM_UNLOCK();
3968
3969         return rc;
3970 }
3971
3972 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3973 {
3974         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3975         struct hwrm_func_cfg_input req = {0};
3976         int rc;
3977
3978         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3979
3980         req.fid = rte_cpu_to_le_16(0xffff);
3981         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3982         req.enables = rte_cpu_to_le_32(
3983                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3984         req.async_event_cr = rte_cpu_to_le_16(
3985                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3986         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3987
3988         HWRM_CHECK_RESULT();
3989         HWRM_UNLOCK();
3990
3991         return rc;
3992 }
3993
3994 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3995 {
3996         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3997         struct hwrm_func_vf_cfg_input req = {0};
3998         int rc;
3999
4000         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4001
4002         req.enables = rte_cpu_to_le_32(
4003                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4004         req.async_event_cr = rte_cpu_to_le_16(
4005                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4006         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4007
4008         HWRM_CHECK_RESULT();
4009         HWRM_UNLOCK();
4010
4011         return rc;
4012 }
4013
4014 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4015 {
4016         struct hwrm_func_cfg_input req = {0};
4017         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4018         uint16_t dflt_vlan, fid;
4019         uint32_t func_cfg_flags;
4020         int rc = 0;
4021
4022         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4023
4024         if (is_vf) {
4025                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4026                 fid = bp->pf->vf_info[vf].fid;
4027                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4028         } else {
4029                 fid = rte_cpu_to_le_16(0xffff);
4030                 func_cfg_flags = bp->pf->func_cfg_flags;
4031                 dflt_vlan = bp->vlan;
4032         }
4033
4034         req.flags = rte_cpu_to_le_32(func_cfg_flags);
4035         req.fid = rte_cpu_to_le_16(fid);
4036         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4037         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4038
4039         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4040
4041         HWRM_CHECK_RESULT();
4042         HWRM_UNLOCK();
4043
4044         return rc;
4045 }
4046
4047 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4048                         uint16_t max_bw, uint16_t enables)
4049 {
4050         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4051         struct hwrm_func_cfg_input req = {0};
4052         int rc;
4053
4054         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4055
4056         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4057         req.enables |= rte_cpu_to_le_32(enables);
4058         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4059         req.max_bw = rte_cpu_to_le_32(max_bw);
4060         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4061
4062         HWRM_CHECK_RESULT();
4063         HWRM_UNLOCK();
4064
4065         return rc;
4066 }
4067
4068 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4069 {
4070         struct hwrm_func_cfg_input req = {0};
4071         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4072         int rc = 0;
4073
4074         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4075
4076         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4077         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4078         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4079         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4080
4081         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4082
4083         HWRM_CHECK_RESULT();
4084         HWRM_UNLOCK();
4085
4086         return rc;
4087 }
4088
4089 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4090 {
4091         int rc;
4092
4093         if (BNXT_PF(bp))
4094                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4095         else
4096                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4097
4098         return rc;
4099 }
4100
4101 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4102                               void *encaped, size_t ec_size)
4103 {
4104         int rc = 0;
4105         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4106         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4107
4108         if (ec_size > sizeof(req.encap_request))
4109                 return -1;
4110
4111         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4112
4113         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4114         memcpy(req.encap_request, encaped, ec_size);
4115
4116         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4117
4118         HWRM_CHECK_RESULT();
4119         HWRM_UNLOCK();
4120
4121         return rc;
4122 }
4123
4124 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4125                                        struct rte_ether_addr *mac)
4126 {
4127         struct hwrm_func_qcfg_input req = {0};
4128         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4129         int rc;
4130
4131         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4132
4133         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4134         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4135
4136         HWRM_CHECK_RESULT();
4137
4138         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4139
4140         HWRM_UNLOCK();
4141
4142         return rc;
4143 }
4144
4145 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4146                             void *encaped, size_t ec_size)
4147 {
4148         int rc = 0;
4149         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4150         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4151
4152         if (ec_size > sizeof(req.encap_request))
4153                 return -1;
4154
4155         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4156
4157         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4158         memcpy(req.encap_request, encaped, ec_size);
4159
4160         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4161
4162         HWRM_CHECK_RESULT();
4163         HWRM_UNLOCK();
4164
4165         return rc;
4166 }
4167
4168 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
4169                          struct rte_eth_stats *stats, uint8_t rx)
4170 {
4171         int rc = 0;
4172         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4173         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4174
4175         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4176
4177         req.stat_ctx_id = rte_cpu_to_le_32(cid);
4178
4179         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4180
4181         HWRM_CHECK_RESULT();
4182
4183         if (rx) {
4184                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4185                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
4186                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
4187                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4188                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
4189                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
4190                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_discard_pkts);
4191                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_error_pkts);
4192         } else {
4193                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4194                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
4195                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
4196                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4197                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
4198                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
4199         }
4200
4201         HWRM_UNLOCK();
4202
4203         return rc;
4204 }
4205
4206 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4207 {
4208         struct hwrm_port_qstats_input req = {0};
4209         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4210         struct bnxt_pf_info *pf = bp->pf;
4211         int rc;
4212
4213         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4214
4215         req.port_id = rte_cpu_to_le_16(pf->port_id);
4216         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4217         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4218         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4219
4220         HWRM_CHECK_RESULT();
4221         HWRM_UNLOCK();
4222
4223         return rc;
4224 }
4225
4226 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4227 {
4228         struct hwrm_port_clr_stats_input req = {0};
4229         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4230         struct bnxt_pf_info *pf = bp->pf;
4231         int rc;
4232
4233         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4234         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4235             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4236                 return 0;
4237
4238         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4239
4240         req.port_id = rte_cpu_to_le_16(pf->port_id);
4241         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4242
4243         HWRM_CHECK_RESULT();
4244         HWRM_UNLOCK();
4245
4246         return rc;
4247 }
4248
4249 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4250 {
4251         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4252         struct hwrm_port_led_qcaps_input req = {0};
4253         int rc;
4254
4255         if (BNXT_VF(bp))
4256                 return 0;
4257
4258         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4259         req.port_id = bp->pf->port_id;
4260         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4261
4262         HWRM_CHECK_RESULT();
4263
4264         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4265                 unsigned int i;
4266
4267                 bp->leds->num_leds = resp->num_leds;
4268                 memcpy(bp->leds, &resp->led0_id,
4269                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4270                 for (i = 0; i < bp->leds->num_leds; i++) {
4271                         struct bnxt_led_info *led = &bp->leds[i];
4272
4273                         uint16_t caps = led->led_state_caps;
4274
4275                         if (!led->led_group_id ||
4276                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4277                                 bp->leds->num_leds = 0;
4278                                 break;
4279                         }
4280                 }
4281         }
4282
4283         HWRM_UNLOCK();
4284
4285         return rc;
4286 }
4287
4288 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4289 {
4290         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4291         struct hwrm_port_led_cfg_input req = {0};
4292         struct bnxt_led_cfg *led_cfg;
4293         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4294         uint16_t duration = 0;
4295         int rc, i;
4296
4297         if (!bp->leds->num_leds || BNXT_VF(bp))
4298                 return -EOPNOTSUPP;
4299
4300         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4301
4302         if (led_on) {
4303                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4304                 duration = rte_cpu_to_le_16(500);
4305         }
4306         req.port_id = bp->pf->port_id;
4307         req.num_leds = bp->leds->num_leds;
4308         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4309         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4310                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4311                 led_cfg->led_id = bp->leds[i].led_id;
4312                 led_cfg->led_state = led_state;
4313                 led_cfg->led_blink_on = duration;
4314                 led_cfg->led_blink_off = duration;
4315                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4316         }
4317
4318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4319
4320         HWRM_CHECK_RESULT();
4321         HWRM_UNLOCK();
4322
4323         return rc;
4324 }
4325
4326 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4327                                uint32_t *length)
4328 {
4329         int rc;
4330         struct hwrm_nvm_get_dir_info_input req = {0};
4331         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4332
4333         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4334
4335         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4336
4337         HWRM_CHECK_RESULT();
4338
4339         *entries = rte_le_to_cpu_32(resp->entries);
4340         *length = rte_le_to_cpu_32(resp->entry_length);
4341
4342         HWRM_UNLOCK();
4343         return rc;
4344 }
4345
4346 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4347 {
4348         int rc;
4349         uint32_t dir_entries;
4350         uint32_t entry_length;
4351         uint8_t *buf;
4352         size_t buflen;
4353         rte_iova_t dma_handle;
4354         struct hwrm_nvm_get_dir_entries_input req = {0};
4355         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4356
4357         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4358         if (rc != 0)
4359                 return rc;
4360
4361         *data++ = dir_entries;
4362         *data++ = entry_length;
4363         len -= 2;
4364         memset(data, 0xff, len);
4365
4366         buflen = dir_entries * entry_length;
4367         buf = rte_malloc("nvm_dir", buflen, 0);
4368         if (buf == NULL)
4369                 return -ENOMEM;
4370         dma_handle = rte_malloc_virt2iova(buf);
4371         if (dma_handle == RTE_BAD_IOVA) {
4372                 rte_free(buf);
4373                 PMD_DRV_LOG(ERR,
4374                         "unable to map response address to physical memory\n");
4375                 return -ENOMEM;
4376         }
4377         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4378         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4379         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4380
4381         if (rc == 0)
4382                 memcpy(data, buf, len > buflen ? buflen : len);
4383
4384         rte_free(buf);
4385         HWRM_CHECK_RESULT();
4386         HWRM_UNLOCK();
4387
4388         return rc;
4389 }
4390
4391 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4392                              uint32_t offset, uint32_t length,
4393                              uint8_t *data)
4394 {
4395         int rc;
4396         uint8_t *buf;
4397         rte_iova_t dma_handle;
4398         struct hwrm_nvm_read_input req = {0};
4399         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4400
4401         buf = rte_malloc("nvm_item", length, 0);
4402         if (!buf)
4403                 return -ENOMEM;
4404
4405         dma_handle = rte_malloc_virt2iova(buf);
4406         if (dma_handle == RTE_BAD_IOVA) {
4407                 rte_free(buf);
4408                 PMD_DRV_LOG(ERR,
4409                         "unable to map response address to physical memory\n");
4410                 return -ENOMEM;
4411         }
4412         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4413         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4414         req.dir_idx = rte_cpu_to_le_16(index);
4415         req.offset = rte_cpu_to_le_32(offset);
4416         req.len = rte_cpu_to_le_32(length);
4417         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4418         if (rc == 0)
4419                 memcpy(data, buf, length);
4420
4421         rte_free(buf);
4422         HWRM_CHECK_RESULT();
4423         HWRM_UNLOCK();
4424
4425         return rc;
4426 }
4427
4428 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4429 {
4430         int rc;
4431         struct hwrm_nvm_erase_dir_entry_input req = {0};
4432         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4433
4434         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4435         req.dir_idx = rte_cpu_to_le_16(index);
4436         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4437         HWRM_CHECK_RESULT();
4438         HWRM_UNLOCK();
4439
4440         return rc;
4441 }
4442
4443
4444 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4445                           uint16_t dir_ordinal, uint16_t dir_ext,
4446                           uint16_t dir_attr, const uint8_t *data,
4447                           size_t data_len)
4448 {
4449         int rc;
4450         struct hwrm_nvm_write_input req = {0};
4451         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4452         rte_iova_t dma_handle;
4453         uint8_t *buf;
4454
4455         buf = rte_malloc("nvm_write", data_len, 0);
4456         if (!buf)
4457                 return -ENOMEM;
4458
4459         dma_handle = rte_malloc_virt2iova(buf);
4460         if (dma_handle == RTE_BAD_IOVA) {
4461                 rte_free(buf);
4462                 PMD_DRV_LOG(ERR,
4463                         "unable to map response address to physical memory\n");
4464                 return -ENOMEM;
4465         }
4466         memcpy(buf, data, data_len);
4467
4468         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4469
4470         req.dir_type = rte_cpu_to_le_16(dir_type);
4471         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4472         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4473         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4474         req.dir_data_length = rte_cpu_to_le_32(data_len);
4475         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4476
4477         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4478
4479         rte_free(buf);
4480         HWRM_CHECK_RESULT();
4481         HWRM_UNLOCK();
4482
4483         return rc;
4484 }
4485
4486 static void
4487 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4488 {
4489         uint32_t *count = cbdata;
4490
4491         *count = *count + 1;
4492 }
4493
4494 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4495                                      struct bnxt_vnic_info *vnic __rte_unused)
4496 {
4497         return 0;
4498 }
4499
4500 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4501 {
4502         uint32_t count = 0;
4503
4504         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4505             &count, bnxt_vnic_count_hwrm_stub);
4506
4507         return count;
4508 }
4509
4510 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4511                                         uint16_t *vnic_ids)
4512 {
4513         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4514         struct hwrm_func_vf_vnic_ids_query_output *resp =
4515                                                 bp->hwrm_cmd_resp_addr;
4516         int rc;
4517
4518         /* First query all VNIC ids */
4519         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4520
4521         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4522         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4523         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4524
4525         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4526                 HWRM_UNLOCK();
4527                 PMD_DRV_LOG(ERR,
4528                 "unable to map VNIC ID table address to physical memory\n");
4529                 return -ENOMEM;
4530         }
4531         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4532         HWRM_CHECK_RESULT();
4533         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4534
4535         HWRM_UNLOCK();
4536
4537         return rc;
4538 }
4539
4540 /*
4541  * This function queries the VNIC IDs  for a specified VF. It then calls
4542  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4543  * Then it calls the hwrm_cb function to program this new vnic configuration.
4544  */
4545 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4546         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4547         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4548 {
4549         struct bnxt_vnic_info vnic;
4550         int rc = 0;
4551         int i, num_vnic_ids;
4552         uint16_t *vnic_ids;
4553         size_t vnic_id_sz;
4554         size_t sz;
4555
4556         /* First query all VNIC ids */
4557         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4558         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4559                         RTE_CACHE_LINE_SIZE);
4560         if (vnic_ids == NULL)
4561                 return -ENOMEM;
4562
4563         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4564                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4565
4566         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4567
4568         if (num_vnic_ids < 0)
4569                 return num_vnic_ids;
4570
4571         /* Retrieve VNIC, update bd_stall then update */
4572
4573         for (i = 0; i < num_vnic_ids; i++) {
4574                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4575                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4576                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4577                 if (rc)
4578                         break;
4579                 if (vnic.mru <= 4)      /* Indicates unallocated */
4580                         continue;
4581
4582                 vnic_cb(&vnic, cbdata);
4583
4584                 rc = hwrm_cb(bp, &vnic);
4585                 if (rc)
4586                         break;
4587         }
4588
4589         rte_free(vnic_ids);
4590
4591         return rc;
4592 }
4593
4594 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4595                                               bool on)
4596 {
4597         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4598         struct hwrm_func_cfg_input req = {0};
4599         int rc;
4600
4601         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4602
4603         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4604         req.enables |= rte_cpu_to_le_32(
4605                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4606         req.vlan_antispoof_mode = on ?
4607                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4608                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4609         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4610
4611         HWRM_CHECK_RESULT();
4612         HWRM_UNLOCK();
4613
4614         return rc;
4615 }
4616
4617 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4618 {
4619         struct bnxt_vnic_info vnic;
4620         uint16_t *vnic_ids;
4621         size_t vnic_id_sz;
4622         int num_vnic_ids, i;
4623         size_t sz;
4624         int rc;
4625
4626         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4627         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4628                         RTE_CACHE_LINE_SIZE);
4629         if (vnic_ids == NULL)
4630                 return -ENOMEM;
4631
4632         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4633                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4634
4635         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4636         if (rc <= 0)
4637                 goto exit;
4638         num_vnic_ids = rc;
4639
4640         /*
4641          * Loop through to find the default VNIC ID.
4642          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4643          * by sending the hwrm_func_qcfg command to the firmware.
4644          */
4645         for (i = 0; i < num_vnic_ids; i++) {
4646                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4647                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4648                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4649                                         bp->pf->first_vf_id + vf);
4650                 if (rc)
4651                         goto exit;
4652                 if (vnic.func_default) {
4653                         rte_free(vnic_ids);
4654                         return vnic.fw_vnic_id;
4655                 }
4656         }
4657         /* Could not find a default VNIC. */
4658         PMD_DRV_LOG(ERR, "No default VNIC\n");
4659 exit:
4660         rte_free(vnic_ids);
4661         return rc;
4662 }
4663
4664 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4665                          uint16_t dst_id,
4666                          struct bnxt_filter_info *filter)
4667 {
4668         int rc = 0;
4669         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4670         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4671         uint32_t enables = 0;
4672
4673         if (filter->fw_em_filter_id != UINT64_MAX)
4674                 bnxt_hwrm_clear_em_filter(bp, filter);
4675
4676         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4677
4678         req.flags = rte_cpu_to_le_32(filter->flags);
4679
4680         enables = filter->enables |
4681               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4682         req.dst_id = rte_cpu_to_le_16(dst_id);
4683
4684         if (filter->ip_addr_type) {
4685                 req.ip_addr_type = filter->ip_addr_type;
4686                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4687         }
4688         if (enables &
4689             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4690                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4691         if (enables &
4692             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4693                 memcpy(req.src_macaddr, filter->src_macaddr,
4694                        RTE_ETHER_ADDR_LEN);
4695         if (enables &
4696             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4697                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4698                        RTE_ETHER_ADDR_LEN);
4699         if (enables &
4700             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4701                 req.ovlan_vid = filter->l2_ovlan;
4702         if (enables &
4703             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4704                 req.ivlan_vid = filter->l2_ivlan;
4705         if (enables &
4706             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4707                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4708         if (enables &
4709             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4710                 req.ip_protocol = filter->ip_protocol;
4711         if (enables &
4712             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4713                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4714         if (enables &
4715             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4716                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4717         if (enables &
4718             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4719                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4720         if (enables &
4721             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4722                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4723         if (enables &
4724             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4725                 req.mirror_vnic_id = filter->mirror_vnic_id;
4726
4727         req.enables = rte_cpu_to_le_32(enables);
4728
4729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4730
4731         HWRM_CHECK_RESULT();
4732
4733         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4734         HWRM_UNLOCK();
4735
4736         return rc;
4737 }
4738
4739 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4740 {
4741         int rc = 0;
4742         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4743         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4744
4745         if (filter->fw_em_filter_id == UINT64_MAX)
4746                 return 0;
4747
4748         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4749
4750         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4751
4752         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4753
4754         HWRM_CHECK_RESULT();
4755         HWRM_UNLOCK();
4756
4757         filter->fw_em_filter_id = UINT64_MAX;
4758         filter->fw_l2_filter_id = UINT64_MAX;
4759
4760         return 0;
4761 }
4762
4763 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4764                          uint16_t dst_id,
4765                          struct bnxt_filter_info *filter)
4766 {
4767         int rc = 0;
4768         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4769         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4770                                                 bp->hwrm_cmd_resp_addr;
4771         uint32_t enables = 0;
4772
4773         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4774                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4775
4776         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4777
4778         req.flags = rte_cpu_to_le_32(filter->flags);
4779
4780         enables = filter->enables |
4781               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4782         req.dst_id = rte_cpu_to_le_16(dst_id);
4783
4784         if (filter->ip_addr_type) {
4785                 req.ip_addr_type = filter->ip_addr_type;
4786                 enables |=
4787                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4788         }
4789         if (enables &
4790             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4791                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4792         if (enables &
4793             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4794                 memcpy(req.src_macaddr, filter->src_macaddr,
4795                        RTE_ETHER_ADDR_LEN);
4796         if (enables &
4797             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4798                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4799         if (enables &
4800             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4801                 req.ip_protocol = filter->ip_protocol;
4802         if (enables &
4803             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4804                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4805         if (enables &
4806             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4807                 req.src_ipaddr_mask[0] =
4808                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4809         if (enables &
4810             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4811                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4812         if (enables &
4813             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4814                 req.dst_ipaddr_mask[0] =
4815                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4816         if (enables &
4817             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4818                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4819         if (enables &
4820             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4821                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4822         if (enables &
4823             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4824                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4825         if (enables &
4826             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4827                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4828         if (enables &
4829             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4830                 req.mirror_vnic_id = filter->mirror_vnic_id;
4831
4832         req.enables = rte_cpu_to_le_32(enables);
4833
4834         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4835
4836         HWRM_CHECK_RESULT();
4837
4838         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4839         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4840         HWRM_UNLOCK();
4841
4842         return rc;
4843 }
4844
4845 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4846                                 struct bnxt_filter_info *filter)
4847 {
4848         int rc = 0;
4849         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4850         struct hwrm_cfa_ntuple_filter_free_output *resp =
4851                                                 bp->hwrm_cmd_resp_addr;
4852
4853         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4854                 return 0;
4855
4856         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4857
4858         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4859
4860         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4861
4862         HWRM_CHECK_RESULT();
4863         HWRM_UNLOCK();
4864
4865         filter->fw_ntuple_filter_id = UINT64_MAX;
4866
4867         return 0;
4868 }
4869
4870 static int
4871 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4872 {
4873         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4874         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4875         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4876         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4877         uint16_t *ring_tbl = vnic->rss_table;
4878         int nr_ctxs = vnic->num_lb_ctxts;
4879         int max_rings = bp->rx_nr_rings;
4880         int i, j, k, cnt;
4881         int rc = 0;
4882
4883         for (i = 0, k = 0; i < nr_ctxs; i++) {
4884                 struct bnxt_rx_ring_info *rxr;
4885                 struct bnxt_cp_ring_info *cpr;
4886
4887                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4888
4889                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4890                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4891                 req.hash_mode_flags = vnic->hash_mode;
4892
4893                 req.ring_grp_tbl_addr =
4894                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4895                                      i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
4896                                      2 * sizeof(*ring_tbl));
4897                 req.hash_key_tbl_addr =
4898                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4899
4900                 req.ring_table_pair_index = i;
4901                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4902
4903                 for (j = 0; j < 64; j++) {
4904                         uint16_t ring_id;
4905
4906                         /* Find next active ring. */
4907                         for (cnt = 0; cnt < max_rings; cnt++) {
4908                                 if (rx_queue_state[k] !=
4909                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4910                                         break;
4911                                 if (++k == max_rings)
4912                                         k = 0;
4913                         }
4914
4915                         /* Return if no rings are active. */
4916                         if (cnt == max_rings) {
4917                                 HWRM_UNLOCK();
4918                                 return 0;
4919                         }
4920
4921                         /* Add rx/cp ring pair to RSS table. */
4922                         rxr = rxqs[k]->rx_ring;
4923                         cpr = rxqs[k]->cp_ring;
4924
4925                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4926                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4927                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4928                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4929
4930                         if (++k == max_rings)
4931                                 k = 0;
4932                 }
4933                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4934                                             BNXT_USE_CHIMP_MB);
4935
4936                 HWRM_CHECK_RESULT();
4937                 HWRM_UNLOCK();
4938         }
4939
4940         return rc;
4941 }
4942
4943 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4944 {
4945         unsigned int rss_idx, fw_idx, i;
4946
4947         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4948                 return 0;
4949
4950         if (!(vnic->rss_table && vnic->hash_type))
4951                 return 0;
4952
4953         if (BNXT_CHIP_P5(bp))
4954                 return bnxt_vnic_rss_configure_p5(bp, vnic);
4955
4956         /*
4957          * Fill the RSS hash & redirection table with
4958          * ring group ids for all VNICs
4959          */
4960         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4961              rss_idx++, fw_idx++) {
4962                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4963                         fw_idx %= bp->rx_cp_nr_rings;
4964                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4965                                 break;
4966                         fw_idx++;
4967                 }
4968
4969                 if (i == bp->rx_cp_nr_rings)
4970                         return 0;
4971
4972                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4973         }
4974
4975         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4976 }
4977
4978 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4979         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4980 {
4981         uint16_t flags;
4982
4983         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4984
4985         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4986         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4987
4988         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4989         req->num_cmpl_dma_aggr_during_int =
4990                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4991
4992         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4993
4994         /* min timer set to 1/2 of interrupt timer */
4995         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4996
4997         /* buf timer set to 1/4 of interrupt timer */
4998         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4999
5000         req->cmpl_aggr_dma_tmr_during_int =
5001                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5002
5003         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5004                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5005         req->flags = rte_cpu_to_le_16(flags);
5006 }
5007
5008 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5009                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5010 {
5011         struct hwrm_ring_aggint_qcaps_input req = {0};
5012         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5013         uint32_t enables;
5014         uint16_t flags;
5015         int rc;
5016
5017         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5018         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5019         HWRM_CHECK_RESULT();
5020
5021         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5022         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5023
5024         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5025                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5026         agg_req->flags = rte_cpu_to_le_16(flags);
5027         enables =
5028          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5029          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5030         agg_req->enables = rte_cpu_to_le_32(enables);
5031
5032         HWRM_UNLOCK();
5033         return rc;
5034 }
5035
5036 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5037                         struct bnxt_coal *coal, uint16_t ring_id)
5038 {
5039         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5040         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5041                                                 bp->hwrm_cmd_resp_addr;
5042         int rc;
5043
5044         /* Set ring coalesce parameters only for 100G NICs */
5045         if (BNXT_CHIP_P5(bp)) {
5046                 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5047                         return -1;
5048         } else if (bnxt_stratus_device(bp)) {
5049                 bnxt_hwrm_set_coal_params(coal, &req);
5050         } else {
5051                 return 0;
5052         }
5053
5054         HWRM_PREP(&req,
5055                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5056                   BNXT_USE_CHIMP_MB);
5057         req.ring_id = rte_cpu_to_le_16(ring_id);
5058         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5059         HWRM_CHECK_RESULT();
5060         HWRM_UNLOCK();
5061         return 0;
5062 }
5063
5064 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5065 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5066 {
5067         struct hwrm_func_backing_store_qcaps_input req = {0};
5068         struct hwrm_func_backing_store_qcaps_output *resp =
5069                 bp->hwrm_cmd_resp_addr;
5070         struct bnxt_ctx_pg_info *ctx_pg;
5071         struct bnxt_ctx_mem_info *ctx;
5072         int total_alloc_len;
5073         int rc, i, tqm_rings;
5074
5075         if (!BNXT_CHIP_P5(bp) ||
5076             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5077             BNXT_VF(bp) ||
5078             bp->ctx)
5079                 return 0;
5080
5081         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5082         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5083         HWRM_CHECK_RESULT_SILENT();
5084
5085         total_alloc_len = sizeof(*ctx);
5086         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5087                           RTE_CACHE_LINE_SIZE);
5088         if (!ctx) {
5089                 rc = -ENOMEM;
5090                 goto ctx_err;
5091         }
5092
5093         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5094         ctx->qp_min_qp1_entries =
5095                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5096         ctx->qp_max_l2_entries =
5097                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5098         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5099         ctx->srq_max_l2_entries =
5100                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5101         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5102         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5103         ctx->cq_max_l2_entries =
5104                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5105         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5106         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5107         ctx->vnic_max_vnic_entries =
5108                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5109         ctx->vnic_max_ring_table_entries =
5110                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5111         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5112         ctx->stat_max_entries =
5113                 rte_le_to_cpu_32(resp->stat_max_entries);
5114         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5115         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5116         ctx->tqm_min_entries_per_ring =
5117                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5118         ctx->tqm_max_entries_per_ring =
5119                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5120         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5121         if (!ctx->tqm_entries_multiple)
5122                 ctx->tqm_entries_multiple = 1;
5123         ctx->mrav_max_entries =
5124                 rte_le_to_cpu_32(resp->mrav_max_entries);
5125         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5126         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5127         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5128         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5129
5130         ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5131                                   RTE_MIN(ctx->tqm_fp_rings_count,
5132                                           BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5133                                   bp->max_q;
5134
5135         /* Check if the ext ring count needs to be counted.
5136          * Ext ring count is available only with new FW so we should not
5137          * look at the field on older FW.
5138          */
5139         if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5140             bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5141                 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5142                 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5143                                                   ctx->tqm_fp_rings_count);
5144         }
5145
5146         tqm_rings = ctx->tqm_fp_rings_count + 1;
5147
5148         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5149                             sizeof(*ctx_pg) * tqm_rings,
5150                             RTE_CACHE_LINE_SIZE);
5151         if (!ctx_pg) {
5152                 rc = -ENOMEM;
5153                 goto ctx_err;
5154         }
5155         for (i = 0; i < tqm_rings; i++, ctx_pg++)
5156                 ctx->tqm_mem[i] = ctx_pg;
5157
5158         bp->ctx = ctx;
5159 ctx_err:
5160         HWRM_UNLOCK();
5161         return rc;
5162 }
5163
5164 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5165 {
5166         struct hwrm_func_backing_store_cfg_input req = {0};
5167         struct hwrm_func_backing_store_cfg_output *resp =
5168                 bp->hwrm_cmd_resp_addr;
5169         struct bnxt_ctx_mem_info *ctx = bp->ctx;
5170         struct bnxt_ctx_pg_info *ctx_pg;
5171         uint32_t *num_entries;
5172         uint64_t *pg_dir;
5173         uint8_t *pg_attr;
5174         uint32_t ena;
5175         int i, rc;
5176
5177         if (!ctx)
5178                 return 0;
5179
5180         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5181         req.enables = rte_cpu_to_le_32(enables);
5182
5183         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5184                 ctx_pg = &ctx->qp_mem;
5185                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5186                 req.qp_num_qp1_entries =
5187                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5188                 req.qp_num_l2_entries =
5189                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5190                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5191                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5192                                       &req.qpc_pg_size_qpc_lvl,
5193                                       &req.qpc_page_dir);
5194         }
5195
5196         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5197                 ctx_pg = &ctx->srq_mem;
5198                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5199                 req.srq_num_l2_entries =
5200                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5201                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5202                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5203                                       &req.srq_pg_size_srq_lvl,
5204                                       &req.srq_page_dir);
5205         }
5206
5207         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5208                 ctx_pg = &ctx->cq_mem;
5209                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5210                 req.cq_num_l2_entries =
5211                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5212                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5213                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5214                                       &req.cq_pg_size_cq_lvl,
5215                                       &req.cq_page_dir);
5216         }
5217
5218         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5219                 ctx_pg = &ctx->vnic_mem;
5220                 req.vnic_num_vnic_entries =
5221                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5222                 req.vnic_num_ring_table_entries =
5223                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5224                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5225                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5226                                       &req.vnic_pg_size_vnic_lvl,
5227                                       &req.vnic_page_dir);
5228         }
5229
5230         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5231                 ctx_pg = &ctx->stat_mem;
5232                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5233                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5234                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5235                                       &req.stat_pg_size_stat_lvl,
5236                                       &req.stat_page_dir);
5237         }
5238
5239         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5240         num_entries = &req.tqm_sp_num_entries;
5241         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5242         pg_dir = &req.tqm_sp_page_dir;
5243         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5244         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5245                 if (!(enables & ena))
5246                         continue;
5247
5248                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5249
5250                 ctx_pg = ctx->tqm_mem[i];
5251                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5252                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5253         }
5254
5255         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5256                 /* DPDK does not need to configure MRAV and TIM type.
5257                  * So we are skipping over MRAV and TIM. Skip to configure
5258                  * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5259                  */
5260                 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5261                 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5262                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5263                                       &req.tqm_ring8_pg_size_tqm_ring_lvl,
5264                                       &req.tqm_ring8_page_dir);
5265         }
5266
5267         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5268         HWRM_CHECK_RESULT();
5269         HWRM_UNLOCK();
5270
5271         return rc;
5272 }
5273
5274 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5275 {
5276         struct hwrm_port_qstats_ext_input req = {0};
5277         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5278         struct bnxt_pf_info *pf = bp->pf;
5279         int rc;
5280
5281         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5282               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5283                 return 0;
5284
5285         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5286
5287         req.port_id = rte_cpu_to_le_16(pf->port_id);
5288         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5289                 req.tx_stat_host_addr =
5290                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5291                 req.tx_stat_size =
5292                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5293         }
5294         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5295                 req.rx_stat_host_addr =
5296                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5297                 req.rx_stat_size =
5298                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5299         }
5300         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5301
5302         if (rc) {
5303                 bp->fw_rx_port_stats_ext_size = 0;
5304                 bp->fw_tx_port_stats_ext_size = 0;
5305         } else {
5306                 bp->fw_rx_port_stats_ext_size =
5307                         rte_le_to_cpu_16(resp->rx_stat_size);
5308                 bp->fw_tx_port_stats_ext_size =
5309                         rte_le_to_cpu_16(resp->tx_stat_size);
5310         }
5311
5312         HWRM_CHECK_RESULT();
5313         HWRM_UNLOCK();
5314
5315         return rc;
5316 }
5317
5318 int
5319 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5320 {
5321         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5322         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5323                 bp->hwrm_cmd_resp_addr;
5324         int rc = 0;
5325
5326         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5327         req.tunnel_type = type;
5328         req.dest_fid = bp->fw_fid;
5329         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5330         HWRM_CHECK_RESULT();
5331
5332         HWRM_UNLOCK();
5333
5334         return rc;
5335 }
5336
5337 int
5338 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5339 {
5340         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5341         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5342                 bp->hwrm_cmd_resp_addr;
5343         int rc = 0;
5344
5345         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5346         req.tunnel_type = type;
5347         req.dest_fid = bp->fw_fid;
5348         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5349         HWRM_CHECK_RESULT();
5350
5351         HWRM_UNLOCK();
5352
5353         return rc;
5354 }
5355
5356 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5357 {
5358         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5359         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5360                 bp->hwrm_cmd_resp_addr;
5361         int rc = 0;
5362
5363         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5364         req.src_fid = bp->fw_fid;
5365         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5366         HWRM_CHECK_RESULT();
5367
5368         if (type)
5369                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5370
5371         HWRM_UNLOCK();
5372
5373         return rc;
5374 }
5375
5376 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5377                                    uint16_t *dst_fid)
5378 {
5379         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5380         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5381                 bp->hwrm_cmd_resp_addr;
5382         int rc = 0;
5383
5384         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5385         req.src_fid = bp->fw_fid;
5386         req.tunnel_type = tun_type;
5387         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5388         HWRM_CHECK_RESULT();
5389
5390         if (dst_fid)
5391                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5392
5393         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5394
5395         HWRM_UNLOCK();
5396
5397         return rc;
5398 }
5399
5400 int bnxt_hwrm_set_mac(struct bnxt *bp)
5401 {
5402         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5403         struct hwrm_func_vf_cfg_input req = {0};
5404         int rc = 0;
5405
5406         if (!BNXT_VF(bp))
5407                 return 0;
5408
5409         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5410
5411         req.enables =
5412                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5413         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5414
5415         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5416
5417         HWRM_CHECK_RESULT();
5418
5419         HWRM_UNLOCK();
5420
5421         return rc;
5422 }
5423
5424 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5425 {
5426         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5427         struct hwrm_func_drv_if_change_input req = {0};
5428         uint32_t flags;
5429         int rc;
5430
5431         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5432                 return 0;
5433
5434         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5435          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5436          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5437          */
5438         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5439                 return 0;
5440
5441         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5442
5443         if (up)
5444                 req.flags =
5445                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5446
5447         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5448
5449         HWRM_CHECK_RESULT();
5450         flags = rte_le_to_cpu_32(resp->flags);
5451         HWRM_UNLOCK();
5452
5453         if (!up)
5454                 return 0;
5455
5456         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5457                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5458                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5459         }
5460
5461         return 0;
5462 }
5463
5464 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5465 {
5466         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5467         struct bnxt_error_recovery_info *info = bp->recovery_info;
5468         struct hwrm_error_recovery_qcfg_input req = {0};
5469         uint32_t flags = 0;
5470         unsigned int i;
5471         int rc;
5472
5473         /* Older FW does not have error recovery support */
5474         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5475                 return 0;
5476
5477         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5478
5479         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5480
5481         HWRM_CHECK_RESULT();
5482
5483         flags = rte_le_to_cpu_32(resp->flags);
5484         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5485                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5486         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5487                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5488
5489         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5490             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5491                 rc = -EINVAL;
5492                 goto err;
5493         }
5494
5495         /* FW returned values are in units of 100msec */
5496         info->driver_polling_freq =
5497                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5498         info->master_func_wait_period =
5499                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5500         info->normal_func_wait_period =
5501                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5502         info->master_func_wait_period_after_reset =
5503                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5504         info->max_bailout_time_after_reset =
5505                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5506         info->status_regs[BNXT_FW_STATUS_REG] =
5507                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5508         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5509                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5510         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5511                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5512         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5513                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5514         info->reg_array_cnt =
5515                 rte_le_to_cpu_32(resp->reg_array_cnt);
5516
5517         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5518                 rc = -EINVAL;
5519                 goto err;
5520         }
5521
5522         for (i = 0; i < info->reg_array_cnt; i++) {
5523                 info->reset_reg[i] =
5524                         rte_le_to_cpu_32(resp->reset_reg[i]);
5525                 info->reset_reg_val[i] =
5526                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5527                 info->delay_after_reset[i] =
5528                         resp->delay_after_reset[i];
5529         }
5530 err:
5531         HWRM_UNLOCK();
5532
5533         /* Map the FW status registers */
5534         if (!rc)
5535                 rc = bnxt_map_fw_health_status_regs(bp);
5536
5537         if (rc) {
5538                 rte_free(bp->recovery_info);
5539                 bp->recovery_info = NULL;
5540         }
5541         return rc;
5542 }
5543
5544 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5545 {
5546         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5547         struct hwrm_fw_reset_input req = {0};
5548         int rc;
5549
5550         if (!BNXT_PF(bp))
5551                 return -EOPNOTSUPP;
5552
5553         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5554
5555         req.embedded_proc_type =
5556                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5557         req.selfrst_status =
5558                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5559         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5560
5561         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5562                                     BNXT_USE_KONG(bp));
5563
5564         HWRM_CHECK_RESULT();
5565         HWRM_UNLOCK();
5566
5567         return rc;
5568 }
5569
5570 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5571 {
5572         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5573         struct hwrm_port_ts_query_input req = {0};
5574         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5575         uint32_t flags = 0;
5576         int rc;
5577
5578         if (!ptp)
5579                 return 0;
5580
5581         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5582
5583         switch (path) {
5584         case BNXT_PTP_FLAGS_PATH_TX:
5585                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5586                 break;
5587         case BNXT_PTP_FLAGS_PATH_RX:
5588                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5589                 break;
5590         case BNXT_PTP_FLAGS_CURRENT_TIME:
5591                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5592                 break;
5593         }
5594
5595         req.flags = rte_cpu_to_le_32(flags);
5596         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5597
5598         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5599
5600         HWRM_CHECK_RESULT();
5601
5602         if (timestamp) {
5603                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5604                 *timestamp |=
5605                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5606         }
5607         HWRM_UNLOCK();
5608
5609         return rc;
5610 }
5611
5612 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5613 {
5614         int rc = 0;
5615
5616         struct hwrm_cfa_counter_qcaps_input req = {0};
5617         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5618
5619         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5620                 PMD_DRV_LOG(DEBUG,
5621                             "Not a PF or trusted VF. Command not supported\n");
5622                 return 0;
5623         }
5624
5625         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5626         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5627         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5628
5629         HWRM_CHECK_RESULT();
5630         if (max_fc)
5631                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5632         HWRM_UNLOCK();
5633
5634         return 0;
5635 }
5636
5637 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5638 {
5639         int rc = 0;
5640         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5641         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5642
5643         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5644                 PMD_DRV_LOG(DEBUG,
5645                             "Not a PF or trusted VF. Command not supported\n");
5646                 return 0;
5647         }
5648
5649         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5650
5651         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5652         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5653         req.page_dir = rte_cpu_to_le_64(dma_addr);
5654
5655         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5656
5657         HWRM_CHECK_RESULT();
5658         if (ctx_id) {
5659                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5660                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5661         }
5662         HWRM_UNLOCK();
5663
5664         return 0;
5665 }
5666
5667 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5668 {
5669         int rc = 0;
5670         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5671         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5672
5673         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5674                 PMD_DRV_LOG(DEBUG,
5675                             "Not a PF or trusted VF. Command not supported\n");
5676                 return 0;
5677         }
5678
5679         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5680
5681         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5682
5683         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5684
5685         HWRM_CHECK_RESULT();
5686         HWRM_UNLOCK();
5687
5688         return rc;
5689 }
5690
5691 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5692                               uint16_t cntr, uint16_t ctx_id,
5693                               uint32_t num_entries, bool enable)
5694 {
5695         struct hwrm_cfa_counter_cfg_input req = {0};
5696         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5697         uint16_t flags = 0;
5698         int rc;
5699
5700         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5701                 PMD_DRV_LOG(DEBUG,
5702                             "Not a PF or trusted VF. Command not supported\n");
5703                 return 0;
5704         }
5705
5706         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5707
5708         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5709         req.counter_type = rte_cpu_to_le_16(cntr);
5710         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5711                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5712         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5713         if (dir == BNXT_DIR_RX)
5714                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5715         else if (dir == BNXT_DIR_TX)
5716                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5717         req.flags = rte_cpu_to_le_16(flags);
5718         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5719         req.num_entries = rte_cpu_to_le_32(num_entries);
5720
5721         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5722         HWRM_CHECK_RESULT();
5723         HWRM_UNLOCK();
5724
5725         return 0;
5726 }
5727
5728 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5729                                  enum bnxt_flow_dir dir,
5730                                  uint16_t cntr,
5731                                  uint16_t num_entries)
5732 {
5733         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5734         struct hwrm_cfa_counter_qstats_input req = {0};
5735         uint16_t flow_ctx_id = 0;
5736         uint16_t flags = 0;
5737         int rc = 0;
5738
5739         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5740                 PMD_DRV_LOG(DEBUG,
5741                             "Not a PF or trusted VF. Command not supported\n");
5742                 return 0;
5743         }
5744
5745         if (dir == BNXT_DIR_RX) {
5746                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5747                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5748         } else if (dir == BNXT_DIR_TX) {
5749                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5750                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5751         }
5752
5753         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5754         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5755         req.counter_type = rte_cpu_to_le_16(cntr);
5756         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5757         req.num_entries = rte_cpu_to_le_16(num_entries);
5758         req.flags = rte_cpu_to_le_16(flags);
5759         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5760
5761         HWRM_CHECK_RESULT();
5762         HWRM_UNLOCK();
5763
5764         return 0;
5765 }
5766
5767 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5768                                 uint16_t *first_vf_id)
5769 {
5770         int rc = 0;
5771         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5772         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5773
5774         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5775
5776         req.fid = rte_cpu_to_le_16(fid);
5777
5778         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5779
5780         HWRM_CHECK_RESULT();
5781
5782         if (first_vf_id)
5783                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5784
5785         HWRM_UNLOCK();
5786
5787         return rc;
5788 }
5789
5790 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
5791 {
5792         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5793         struct hwrm_cfa_pair_alloc_input req = {0};
5794         int rc;
5795
5796         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5797                 PMD_DRV_LOG(DEBUG,
5798                             "Not a PF or trusted VF. Command not supported\n");
5799                 return 0;
5800         }
5801
5802         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
5803         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5804         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5805                  bp->eth_dev->data->name, rep_bp->vf_id);
5806
5807         req.pf_b_id = rep_bp->parent_pf_idx;
5808         req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5809                                                 rte_cpu_to_le_16(rep_bp->vf_id);
5810         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
5811         req.host_b_id = 1; /* TBD - Confirm if this is OK */
5812
5813         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
5814                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
5815         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
5816                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
5817         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
5818                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
5819         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
5820                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
5821
5822         req.q_ab = rep_bp->rep_q_r2f;
5823         req.q_ba = rep_bp->rep_q_f2r;
5824         req.fc_ab = rep_bp->rep_fc_r2f;
5825         req.fc_ba = rep_bp->rep_fc_f2r;
5826
5827         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5828         HWRM_CHECK_RESULT();
5829
5830         HWRM_UNLOCK();
5831         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
5832                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
5833         return rc;
5834 }
5835
5836 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
5837 {
5838         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
5839         struct hwrm_cfa_pair_free_input req = {0};
5840         int rc;
5841
5842         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5843                 PMD_DRV_LOG(DEBUG,
5844                             "Not a PF or trusted VF. Command not supported\n");
5845                 return 0;
5846         }
5847
5848         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
5849         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5850                  bp->eth_dev->data->name, rep_bp->vf_id);
5851         req.pf_b_id = rep_bp->parent_pf_idx;
5852         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5853         req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5854                                                 rte_cpu_to_le_16(rep_bp->vf_id);
5855         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5856         HWRM_CHECK_RESULT();
5857         HWRM_UNLOCK();
5858         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
5859                     rep_bp->vf_id);
5860         return rc;
5861 }
5862
5863 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5864 {
5865         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5866                                         bp->hwrm_cmd_resp_addr;
5867         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5868         uint32_t flags = 0;
5869         int rc = 0;
5870
5871         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
5872                 return 0;
5873
5874         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5875                 PMD_DRV_LOG(DEBUG,
5876                             "Not a PF or trusted VF. Command not supported\n");
5877                 return 0;
5878         }
5879
5880         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
5881         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5882
5883         HWRM_CHECK_RESULT();
5884         flags = rte_le_to_cpu_32(resp->flags);
5885         HWRM_UNLOCK();
5886
5887         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
5888                 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
5889         else
5890                 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
5891
5892         return rc;
5893 }