drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         timeout = bp->hwrm_cmd_timeout;
 104
 105         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 106             msg_len > bp->max_req_len) {
 107                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 108
 109                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 110                 memcpy(short_cmd_req, req, msg_len);
 111
 112                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 113                 short_input.signature = rte_cpu_to_le_16(
 114                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 115                 short_input.size = rte_cpu_to_le_16(msg_len);
 116                 short_input.req_addr =
 117                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 118
 119                 data = (uint32_t *)&short_input;
 120                 msg_len = sizeof(short_input);
 121
 122                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 123         }
 124
 125         /* Write request msg to hwrm channel */
 126         for (i = 0; i < msg_len; i += 4) {
 127                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 128                 rte_write32(*data, bar);
 129                 data++;
 130         }
 131
 132         /* Zero the rest of the request space */
 133         for (; i < max_req_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 135                 rte_write32(0, bar);
 136         }
 137
 138         /* Ring channel doorbell */
 139         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 140         rte_write32(1, bar);
 141         /*
 142          * Make sure the channel doorbell ring command complete before
 143          * reading the response to avoid getting stale or invalid
 144          * responses.
 145          */
 146         rte_io_mb();
 147
 148         /* Poll for the valid bit */
 149         for (i = 0; i < timeout; i++) {
 150                 /* Sanity check on the resp->resp_len */
 151                 rte_io_rmb();
 152                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 153                         /* Last byte of resp contains the valid key */
 154                         valid = (uint8_t *)resp + resp->resp_len - 1;
 155                         if (*valid == HWRM_RESP_VALID_KEY)
 156                                 break;
 157                 }
 158                 rte_delay_us(1);
 159         }
 160
 161         if (i >= timeout) {
 162                 /* Suppress VER_GET timeout messages during reset recovery */
 163                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 164                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 165                         return -ETIMEDOUT;
 166
 167                 PMD_DRV_LOG(ERR,
 168                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 169                             req->req_type, req->seq_id);
 170                 return -ETIMEDOUT;
 171         }
 172         return 0;
 173 }
 174
 175 /*
 176  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 177  * spinlock, and does initial processing.
 178  *
 179  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 180  * releases the spinlock only if it returns. If the regular int return codes
 181  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 182  * directly, rather it should be copied and modified to suit the function.
 183  *
 184  * HWRM_UNLOCK() must be called after all response processing is completed.
 185  */
 186 #define HWRM_PREP(req, type, kong) do { \
 187         rte_spinlock_lock(&bp->hwrm_lock); \
 188         if (bp->hwrm_cmd_resp_addr == NULL) { \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 return -EACCES; \
 191         } \
 192         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 193         (req)->req_type = rte_cpu_to_le_16(type); \
 194         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 195         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 196                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 197         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 198         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 199 } while (0)
 200
 201 #define HWRM_CHECK_RESULT_SILENT() do {\
 202         if (rc) { \
 203                 rte_spinlock_unlock(&bp->hwrm_lock); \
 204                 return rc; \
 205         } \
 206         if (resp->error_code) { \
 207                 rc = rte_le_to_cpu_16(resp->error_code); \
 208                 rte_spinlock_unlock(&bp->hwrm_lock); \
 209                 return rc; \
 210         } \
 211 } while (0)
 212
 213 #define HWRM_CHECK_RESULT() do {\
 214         if (rc) { \
 215                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 216                 rte_spinlock_unlock(&bp->hwrm_lock); \
 217                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 218                         rc = -EACCES; \
 219                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 220                         rc = -ENOSPC; \
 221                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 222                         rc = -EINVAL; \
 223                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 224                         rc = -ENOTSUP; \
 225                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 226                         rc = -EAGAIN; \
 227                 else if (rc > 0) \
 228                         rc = -EIO; \
 229                 return rc; \
 230         } \
 231         if (resp->error_code) { \
 232                 rc = rte_le_to_cpu_16(resp->error_code); \
 233                 if (resp->resp_len >= 16) { \
 234                         struct hwrm_err_output *tmp_hwrm_err_op = \
 235                                                 (void *)resp; \
 236                         PMD_DRV_LOG(ERR, \
 237                                 "error %d:%d:%08x:%04x\n", \
 238                                 rc, tmp_hwrm_err_op->cmd_err, \
 239                                 rte_le_to_cpu_32(\
 240                                         tmp_hwrm_err_op->opaque_0), \
 241                                 rte_le_to_cpu_16(\
 242                                         tmp_hwrm_err_op->opaque_1)); \
 243                 } else { \
 244                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 245                 } \
 246                 rte_spinlock_unlock(&bp->hwrm_lock); \
 247                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 248                         rc = -EACCES; \
 249                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 250                         rc = -ENOSPC; \
 251                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 252                         rc = -EINVAL; \
 253                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 254                         rc = -ENOTSUP; \
 255                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 256                         rc = -EAGAIN; \
 257                 else if (rc > 0) \
 258                         rc = -EIO; \
 259                 return rc; \
 260         } \
 261 } while (0)
 262
 263 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 264
 265 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 266                                 bool use_kong_mb,
 267                                 uint16_t msg_type,
 268                                 void *msg,
 269                                 uint32_t msg_len,
 270                                 void *resp_msg,
 271                                 uint32_t resp_len)
 272 {
 273         int rc = 0;
 274         bool mailbox = BNXT_USE_CHIMP_MB;
 275         struct input *req = msg;
 276         struct output *resp = bp->hwrm_cmd_resp_addr;
 277
 278         if (use_kong_mb)
 279                 mailbox = BNXT_USE_KONG(bp);
 280
 281         HWRM_PREP(req, msg_type, mailbox);
 282
 283         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 284
 285         HWRM_CHECK_RESULT();
 286
 287         if (resp_msg)
 288                 memcpy(resp_msg, resp, resp_len);
 289
 290         HWRM_UNLOCK();
 291
 292         return rc;
 293 }
 294
 295 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 296                                   bool use_kong_mb,
 297                                   uint16_t tf_type,
 298                                   uint16_t tf_subtype,
 299                                   uint32_t *tf_response_code,
 300                                   void *msg,
 301                                   uint32_t msg_len,
 302                                   void *response,
 303                                   uint32_t response_len)
 304 {
 305         int rc = 0;
 306         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 307         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 308         bool mailbox = BNXT_USE_CHIMP_MB;
 309
 310         if (msg_len > sizeof(req.tf_req))
 311                 return -ENOMEM;
 312
 313         if (use_kong_mb)
 314                 mailbox = BNXT_USE_KONG(bp);
 315
 316         HWRM_PREP(&req, HWRM_TF, mailbox);
 317         /* Build request using the user supplied request payload.
 318          * TLV request size is checked at build time against HWRM
 319          * request max size, thus no checking required.
 320          */
 321         req.tf_type = tf_type;
 322         req.tf_subtype = tf_subtype;
 323         memcpy(req.tf_req, msg, msg_len);
 324
 325         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 326         HWRM_CHECK_RESULT();
 327
 328         /* Copy the resp to user provided response buffer */
 329         if (response != NULL)
 330                 /* Post process response data. We need to copy only
 331                  * the 'payload' as the HWRM data structure really is
 332                  * HWRM header + msg header + payload and the TFLIB
 333                  * only provided a payload place holder.
 334                  */
 335                 if (response_len != 0) {
 336                         memcpy(response,
 337                                resp->tf_resp,
 338                                response_len);
 339                 }
 340
 341         /* Extract the internal tflib response code */
 342         *tf_response_code = resp->tf_resp_code;
 343         HWRM_UNLOCK();
 344
 345         return rc;
 346 }
 347
 348 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 349 {
 350         int rc = 0;
 351         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 352         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 353
 354         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 355         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 356         req.mask = 0;
 357
 358         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 359
 360         HWRM_CHECK_RESULT();
 361         HWRM_UNLOCK();
 362
 363         return rc;
 364 }
 365
 366 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 367                                  struct bnxt_vnic_info *vnic,
 368                                  uint16_t vlan_count,
 369                                  struct bnxt_vlan_table_entry *vlan_table)
 370 {
 371         int rc = 0;
 372         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 373         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 374         uint32_t mask = 0;
 375
 376         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 377                 return rc;
 378
 379         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 380         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 381
 382         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 383                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 384         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 385                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 386
 387         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 388                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 389
 390         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 391                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 392         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 393                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 394                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 395                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 396         }
 397         if (vlan_table) {
 398                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 399                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 400                 req.vlan_tag_tbl_addr =
 401                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 402                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 403         }
 404         req.mask = rte_cpu_to_le_32(mask);
 405
 406         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 407
 408         HWRM_CHECK_RESULT();
 409         HWRM_UNLOCK();
 410
 411         return rc;
 412 }
 413
 414 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 415                         uint16_t vlan_count,
 416                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 417 {
 418         int rc = 0;
 419         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 420         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 421                                                 bp->hwrm_cmd_resp_addr;
 422
 423         /*
 424          * Older HWRM versions did not support this command, and the set_rx_mask
 425          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 426          * removed from set_rx_mask call, and this command was added.
 427          *
 428          * This command is also present from 1.7.8.11 and higher,
 429          * as well as 1.7.8.0
 430          */
 431         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 432                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 433                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 434                                         (11)))
 435                                 return 0;
 436                 }
 437         }
 438         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 439         req.fid = rte_cpu_to_le_16(fid);
 440
 441         req.vlan_tag_mask_tbl_addr =
 442                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 443         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 444
 445         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 446
 447         HWRM_CHECK_RESULT();
 448         HWRM_UNLOCK();
 449
 450         return rc;
 451 }
 452
 453 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 454                              struct bnxt_filter_info *filter)
 455 {
 456         int rc = 0;
 457         struct bnxt_filter_info *l2_filter = filter;
 458         struct bnxt_vnic_info *vnic = NULL;
 459         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 460         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 461
 462         if (filter->fw_l2_filter_id == UINT64_MAX)
 463                 return 0;
 464
 465         if (filter->matching_l2_fltr_ptr)
 466                 l2_filter = filter->matching_l2_fltr_ptr;
 467
 468         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 469                     filter, l2_filter, l2_filter->l2_ref_cnt);
 470
 471         if (l2_filter->l2_ref_cnt == 0)
 472                 return 0;
 473
 474         if (l2_filter->l2_ref_cnt > 0)
 475                 l2_filter->l2_ref_cnt--;
 476
 477         if (l2_filter->l2_ref_cnt > 0)
 478                 return 0;
 479
 480         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 481
 482         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 483
 484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 485
 486         HWRM_CHECK_RESULT();
 487         HWRM_UNLOCK();
 488
 489         filter->fw_l2_filter_id = UINT64_MAX;
 490         if (l2_filter->l2_ref_cnt == 0) {
 491                 vnic = l2_filter->vnic;
 492                 if (vnic) {
 493                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 494                                       bnxt_filter_info, next);
 495                         bnxt_free_filter(bp, l2_filter);
 496                 }
 497         }
 498
 499         return 0;
 500 }
 501
 502 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 503                          uint16_t dst_id,
 504                          struct bnxt_filter_info *filter)
 505 {
 506         int rc = 0;
 507         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 508         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 509         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 510         const struct rte_eth_vmdq_rx_conf *conf =
 511                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 512         uint32_t enables = 0;
 513         uint16_t j = dst_id - 1;
 514
 515         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 516         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 517             conf->pool_map[j].pools & (1UL << j)) {
 518                 PMD_DRV_LOG(DEBUG,
 519                         "Add vlan %u to vmdq pool %u\n",
 520                         conf->pool_map[j].vlan_id, j);
 521
 522                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 523                 filter->enables |=
 524                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 525                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 526         }
 527
 528         if (filter->fw_l2_filter_id != UINT64_MAX)
 529                 bnxt_hwrm_clear_l2_filter(bp, filter);
 530
 531         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 532
 533         /* PMD does not support XDP and RoCE */
 534         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 535                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 536         req.flags = rte_cpu_to_le_32(filter->flags);
 537
 538         enables = filter->enables |
 539               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 540         req.dst_id = rte_cpu_to_le_16(dst_id);
 541
 542         if (enables &
 543             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 544                 memcpy(req.l2_addr, filter->l2_addr,
 545                        RTE_ETHER_ADDR_LEN);
 546         if (enables &
 547             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 548                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 549                        RTE_ETHER_ADDR_LEN);
 550         if (enables &
 551             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 552                 req.l2_ovlan = filter->l2_ovlan;
 553         if (enables &
 554             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 555                 req.l2_ivlan = filter->l2_ivlan;
 556         if (enables &
 557             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 558                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 559         if (enables &
 560             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 561                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 562         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 563                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 564         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 565                 req.src_type = filter->src_type;
 566         if (filter->pri_hint) {
 567                 req.pri_hint = filter->pri_hint;
 568                 req.l2_filter_id_hint =
 569                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 570         }
 571
 572         req.enables = rte_cpu_to_le_32(enables);
 573
 574         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 575
 576         HWRM_CHECK_RESULT();
 577
 578         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 579         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 580         HWRM_UNLOCK();
 581
 582         filter->l2_ref_cnt++;
 583
 584         return rc;
 585 }
 586
 587 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 588 {
 589         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 590         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 591         uint32_t flags = 0;
 592         int rc;
 593
 594         if (!ptp)
 595                 return 0;
 596
 597         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 598
 599         if (ptp->rx_filter)
 600                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 601         else
 602                 flags |=
 603                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 604         if (ptp->tx_tstamp_en)
 605                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 606         else
 607                 flags |=
 608                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 609         req.flags = rte_cpu_to_le_32(flags);
 610         req.enables = rte_cpu_to_le_32
 611                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 612         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 613
 614         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 615         HWRM_UNLOCK();
 616
 617         return rc;
 618 }
 619
 620 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 621 {
 622         int rc = 0;
 623         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 624         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 625         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 626
 627         if (ptp)
 628                 return 0;
 629
 630         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 631
 632         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 633
 634         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 635
 636         HWRM_CHECK_RESULT();
 637
 638         if (!BNXT_CHIP_THOR(bp) &&
 639             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 640                 return 0;
 641
 642         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 643                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 644
 645         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 646         if (!ptp)
 647                 return -ENOMEM;
 648
 649         if (!BNXT_CHIP_THOR(bp)) {
 650                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 651                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 652                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 653                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 654                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 655                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 656                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 657                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 658                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 659                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 660                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 661                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 662                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 663                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 664                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 665                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 666                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 667                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 668         }
 669
 670         ptp->bp = bp;
 671         bp->ptp_cfg = ptp;
 672
 673         return 0;
 674 }
 675
 676 void bnxt_hwrm_free_vf_info(struct bnxt *bp)
 677 {
 678         int i;
 679
 680         for (i = 0; i < bp->pf->max_vfs; i++) {
 681                 rte_free(bp->pf->vf_info[i].vlan_table);
 682                 bp->pf->vf_info[i].vlan_table = NULL;
 683                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 684                 bp->pf->vf_info[i].vlan_as_table = NULL;
 685         }
 686         rte_free(bp->pf->vf_info);
 687         bp->pf->vf_info = NULL;
 688 }
 689
 690 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 691 {
 692         int rc = 0;
 693         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 694         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 695         uint16_t new_max_vfs;
 696         uint32_t flags;
 697         int i;
 698
 699         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 700
 701         req.fid = rte_cpu_to_le_16(0xffff);
 702
 703         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 704
 705         HWRM_CHECK_RESULT();
 706
 707         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 708         flags = rte_le_to_cpu_32(resp->flags);
 709         if (BNXT_PF(bp)) {
 710                 bp->pf->port_id = resp->port_id;
 711                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 712                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 713                 new_max_vfs = bp->pdev->max_vfs;
 714                 if (new_max_vfs != bp->pf->max_vfs) {
 715                         if (bp->pf->vf_info)
 716                                 bnxt_hwrm_free_vf_info(bp);
 717                         bp->pf->vf_info = rte_zmalloc("bnxt_vf_info",
 718                             sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
 719                         if (bp->pf->vf_info == NULL) {
 720                                 PMD_DRV_LOG(ERR, "Alloc vf info fail\n");
 721                                 return -ENOMEM;
 722                         }
 723                         bp->pf->max_vfs = new_max_vfs;
 724                         for (i = 0; i < new_max_vfs; i++) {
 725                                 bp->pf->vf_info[i].fid =
 726                                         bp->pf->first_vf_id + i;
 727                                 bp->pf->vf_info[i].vlan_table =
 728                                         rte_zmalloc("VF VLAN table",
 729                                                     getpagesize(),
 730                                                     getpagesize());
 731                                 if (bp->pf->vf_info[i].vlan_table == NULL)
 732                                         PMD_DRV_LOG(ERR,
 733                                         "Fail to alloc VLAN table for VF %d\n",
 734                                         i);
 735                                 else
 736                                         rte_mem_lock_page(
 737                                                 bp->pf->vf_info[i].vlan_table);
 738                                 bp->pf->vf_info[i].vlan_as_table =
 739                                         rte_zmalloc("VF VLAN AS table",
 740                                                     getpagesize(),
 741                                                     getpagesize());
 742                                 if (bp->pf->vf_info[i].vlan_as_table == NULL)
 743                                         PMD_DRV_LOG(ERR,
 744                                         "Alloc VLAN AS table for VF %d fail\n",
 745                                         i);
 746                                 else
 747                                         rte_mem_lock_page(
 748                                               bp->pf->vf_info[i].vlan_as_table);
 749                                 STAILQ_INIT(&bp->pf->vf_info[i].filter);
 750                         }
 751                 }
 752         }
 753
 754         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 755         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 756                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 757                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 758         } else {
 759                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 760         }
 761         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 762         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 763         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 764         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 765         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 766         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 767         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 768         if (!BNXT_CHIP_THOR(bp))
 769                 bp->max_l2_ctx += bp->max_rx_em_flows;
 770         /* TODO: For now, do not support VMDq/RFS on VFs. */
 771         if (BNXT_PF(bp)) {
 772                 if (bp->pf->max_vfs)
 773                         bp->max_vnics = 1;
 774                 else
 775                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 776         } else {
 777                 bp->max_vnics = 1;
 778         }
 779         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 780                     bp->max_l2_ctx, bp->max_vnics);
 781         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 782         if (BNXT_PF(bp)) {
 783                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 784                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 785                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 786                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 787                         HWRM_UNLOCK();
 788                         bnxt_hwrm_ptp_qcfg(bp);
 789                 }
 790         }
 791
 792         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 793                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 794
 795         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 796                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 797                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 798         }
 799
 800         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 801                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 802
 803         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 804                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 805
 806         HWRM_UNLOCK();
 807
 808         return rc;
 809 }
 810
 811 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 812 {
 813         int rc;
 814
 815         rc = __bnxt_hwrm_func_qcaps(bp);
 816         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 817                 rc = bnxt_alloc_ctx_mem(bp);
 818                 if (rc)
 819                         return rc;
 820
 821                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 822                 if (!rc)
 823                         bp->flags |= BNXT_FLAG_NEW_RM;
 824         }
 825
 826         /* On older FW,
 827          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 828          * But the error can be ignored. Return success.
 829          */
 830
 831         return 0;
 832 }
 833
 834 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 835 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 836 {
 837         int rc = 0;
 838         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 839         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 840
 841         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 842
 843         req.target_id = rte_cpu_to_le_16(0xffff);
 844
 845         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 846
 847         HWRM_CHECK_RESULT();
 848
 849         if (rte_le_to_cpu_32(resp->flags) &
 850             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 851                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 852                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 853         }
 854
 855         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 856
 857         HWRM_UNLOCK();
 858
 859         return rc;
 860 }
 861
 862 int bnxt_hwrm_func_reset(struct bnxt *bp)
 863 {
 864         int rc = 0;
 865         struct hwrm_func_reset_input req = {.req_type = 0 };
 866         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 867
 868         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
 869
 870         req.enables = rte_cpu_to_le_32(0);
 871
 872         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 873
 874         HWRM_CHECK_RESULT();
 875         HWRM_UNLOCK();
 876
 877         return rc;
 878 }
 879
 880 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 881 {
 882         int rc;
 883         uint32_t flags = 0;
 884         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 885         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 886
 887         if (bp->flags & BNXT_FLAG_REGISTERED)
 888                 return 0;
 889
 890         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 891                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 892         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 893                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 894
 895         /* PFs and trusted VFs should indicate the support of the
 896          * Master capability on non Stingray platform
 897          */
 898         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 899                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 900
 901         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 902         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 903                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 904         req.ver_maj = RTE_VER_YEAR;
 905         req.ver_min = RTE_VER_MONTH;
 906         req.ver_upd = RTE_VER_MINOR;
 907
 908         if (BNXT_PF(bp)) {
 909                 req.enables |= rte_cpu_to_le_32(
 910                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 911                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
 912                        RTE_MIN(sizeof(req.vf_req_fwd),
 913                                sizeof(bp->pf->vf_req_fwd)));
 914
 915                 /*
 916                  * PF can sniff HWRM API issued by VF. This can be set up by
 917                  * linux driver and inherited by the DPDK PF driver. Clear
 918                  * this HWRM sniffer list in FW because DPDK PF driver does
 919                  * not support this.
 920                  */
 921                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 922         }
 923
 924         req.flags = rte_cpu_to_le_32(flags);
 925
 926         req.async_event_fwd[0] |=
 927                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 928                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 929                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 930                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 931                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 932         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 933                 req.async_event_fwd[0] |=
 934                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 935         req.async_event_fwd[1] |=
 936                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 937                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 938         if (BNXT_PF(bp))
 939                 req.async_event_fwd[1] |=
 940                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 941
 942         if (BNXT_VF_IS_TRUSTED(bp))
 943                 req.async_event_fwd[1] |=
 944                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
 945
 946         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 947
 948         HWRM_CHECK_RESULT();
 949
 950         flags = rte_le_to_cpu_32(resp->flags);
 951         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 952                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 953
 954         HWRM_UNLOCK();
 955
 956         bp->flags |= BNXT_FLAG_REGISTERED;
 957
 958         return rc;
 959 }
 960
 961 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 962 {
 963         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 964                 return 0;
 965
 966         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 967 }
 968
 969 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 970 {
 971         int rc;
 972         uint32_t flags = 0;
 973         uint32_t enables;
 974         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 975         struct hwrm_func_vf_cfg_input req = {0};
 976
 977         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 978
 979         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 980                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 981                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 982                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 983                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 984
 985         if (BNXT_HAS_RING_GRPS(bp)) {
 986                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 987                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 988         }
 989
 990         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 991         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 992                                             AGG_RING_MULTIPLIER);
 993         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 994         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 995                                               bp->tx_nr_rings +
 996                                               BNXT_NUM_ASYNC_CPR(bp));
 997         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 998         if (bp->vf_resv_strategy ==
 999             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1000                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1001                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1002                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1003                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1004                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1005                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1006         } else if (bp->vf_resv_strategy ==
1007                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1008                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1009                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1010         }
1011
1012         if (test)
1013                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1014                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1015                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1016                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1017                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1018                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1019
1020         if (test && BNXT_HAS_RING_GRPS(bp))
1021                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1022
1023         req.flags = rte_cpu_to_le_32(flags);
1024         req.enables |= rte_cpu_to_le_32(enables);
1025
1026         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1027
1028         if (test)
1029                 HWRM_CHECK_RESULT_SILENT();
1030         else
1031                 HWRM_CHECK_RESULT();
1032
1033         HWRM_UNLOCK();
1034         return rc;
1035 }
1036
1037 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1038 {
1039         int rc;
1040         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1041         struct hwrm_func_resource_qcaps_input req = {0};
1042
1043         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1044         req.fid = rte_cpu_to_le_16(0xffff);
1045
1046         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1047
1048         HWRM_CHECK_RESULT_SILENT();
1049
1050         if (BNXT_VF(bp)) {
1051                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1052                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1053                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1054                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1055                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1056                 /* func_resource_qcaps does not return max_rx_em_flows.
1057                  * So use the value provided by func_qcaps.
1058                  */
1059                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1060                 if (!BNXT_CHIP_THOR(bp))
1061                         bp->max_l2_ctx += bp->max_rx_em_flows;
1062                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1063                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1064         }
1065         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1066         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1067         if (bp->vf_resv_strategy >
1068             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1069                 bp->vf_resv_strategy =
1070                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1071
1072         HWRM_UNLOCK();
1073         return rc;
1074 }
1075
1076 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1077 {
1078         int rc = 0;
1079         struct hwrm_ver_get_input req = {.req_type = 0 };
1080         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1081         uint32_t fw_version;
1082         uint16_t max_resp_len;
1083         char type[RTE_MEMZONE_NAMESIZE];
1084         uint32_t dev_caps_cfg;
1085
1086         bp->max_req_len = HWRM_MAX_REQ_LEN;
1087         bp->hwrm_cmd_timeout = timeout;
1088         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1089
1090         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1091         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1092         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1093
1094         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1095
1096         if (bp->flags & BNXT_FLAG_FW_RESET)
1097                 HWRM_CHECK_RESULT_SILENT();
1098         else
1099                 HWRM_CHECK_RESULT();
1100
1101         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1102                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1103                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1104                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1105         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1106                      (resp->hwrm_fw_min_8b << 16) |
1107                      (resp->hwrm_fw_bld_8b << 8) |
1108                      resp->hwrm_fw_rsvd_8b;
1109         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1110                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1111
1112         fw_version = resp->hwrm_intf_maj_8b << 16;
1113         fw_version |= resp->hwrm_intf_min_8b << 8;
1114         fw_version |= resp->hwrm_intf_upd_8b;
1115         bp->hwrm_spec_code = fw_version;
1116
1117         /* def_req_timeout value is in milliseconds */
1118         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1119         /* convert timeout to usec */
1120         bp->hwrm_cmd_timeout *= 1000;
1121         if (!bp->hwrm_cmd_timeout)
1122                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1123
1124         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1125                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1126                 rc = -EINVAL;
1127                 goto error;
1128         }
1129
1130         if (bp->max_req_len > resp->max_req_win_len) {
1131                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1132                 rc = -EINVAL;
1133         }
1134         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1135         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1136         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1137                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1138
1139         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1140         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1141
1142         if (bp->max_resp_len != max_resp_len) {
1143                 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1144                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1145                         bp->pdev->addr.devid, bp->pdev->addr.function);
1146
1147                 rte_free(bp->hwrm_cmd_resp_addr);
1148
1149                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1150                 if (bp->hwrm_cmd_resp_addr == NULL) {
1151                         rc = -ENOMEM;
1152                         goto error;
1153                 }
1154                 bp->hwrm_cmd_resp_dma_addr =
1155                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1156                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1157                         PMD_DRV_LOG(ERR,
1158                         "Unable to map response buffer to physical memory.\n");
1159                         rc = -ENOMEM;
1160                         goto error;
1161                 }
1162                 bp->max_resp_len = max_resp_len;
1163         }
1164
1165         if ((dev_caps_cfg &
1166                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1167             (dev_caps_cfg &
1168              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1169                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1170                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1171         }
1172
1173         if (((dev_caps_cfg &
1174               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1175              (dev_caps_cfg &
1176               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1177             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1178                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1179                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1180                         bp->pdev->addr.devid, bp->pdev->addr.function);
1181
1182                 rte_free(bp->hwrm_short_cmd_req_addr);
1183
1184                 bp->hwrm_short_cmd_req_addr =
1185                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1186                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1187                         rc = -ENOMEM;
1188                         goto error;
1189                 }
1190                 bp->hwrm_short_cmd_req_dma_addr =
1191                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1192                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1193                         rte_free(bp->hwrm_short_cmd_req_addr);
1194                         PMD_DRV_LOG(ERR,
1195                                 "Unable to map buffer to physical memory.\n");
1196                         rc = -ENOMEM;
1197                         goto error;
1198                 }
1199         }
1200         if (dev_caps_cfg &
1201             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1202                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1203                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1204         }
1205         if (dev_caps_cfg &
1206             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1207                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1208         if (dev_caps_cfg &
1209             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1210                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1211                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1212         }
1213
1214         if (dev_caps_cfg &
1215             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1216                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1217                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1218         }
1219
1220
1221 error:
1222         HWRM_UNLOCK();
1223         return rc;
1224 }
1225
1226 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1227 {
1228         int rc;
1229         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1230         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1231
1232         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1233                 return 0;
1234
1235         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1236         req.flags = flags;
1237
1238         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1239
1240         HWRM_CHECK_RESULT();
1241         HWRM_UNLOCK();
1242
1243         return rc;
1244 }
1245
1246 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1247 {
1248         int rc = 0;
1249         struct hwrm_port_phy_cfg_input req = {0};
1250         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1251         uint32_t enables = 0;
1252
1253         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1254
1255         if (conf->link_up) {
1256                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1257                 if (bp->link_info->auto_mode && conf->link_speed) {
1258                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1259                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1260                 }
1261
1262                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1263                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1264                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1265                 /*
1266                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1267                  * any auto mode, even "none".
1268                  */
1269                 if (!conf->link_speed) {
1270                         /* No speeds specified. Enable AutoNeg - all speeds */
1271                         req.auto_mode =
1272                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1273                 }
1274                 /* AutoNeg - Advertise speeds specified. */
1275                 if (conf->auto_link_speed_mask &&
1276                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1277                         req.auto_mode =
1278                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1279                         req.auto_link_speed_mask =
1280                                 conf->auto_link_speed_mask;
1281                         enables |=
1282                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1283                 }
1284
1285                 req.auto_duplex = conf->duplex;
1286                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1287                 req.auto_pause = conf->auto_pause;
1288                 req.force_pause = conf->force_pause;
1289                 /* Set force_pause if there is no auto or if there is a force */
1290                 if (req.auto_pause && !req.force_pause)
1291                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1292                 else
1293                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1294
1295                 req.enables = rte_cpu_to_le_32(enables);
1296         } else {
1297                 req.flags =
1298                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1299                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1300         }
1301
1302         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1303
1304         HWRM_CHECK_RESULT();
1305         HWRM_UNLOCK();
1306
1307         return rc;
1308 }
1309
1310 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1311                                    struct bnxt_link_info *link_info)
1312 {
1313         int rc = 0;
1314         struct hwrm_port_phy_qcfg_input req = {0};
1315         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1316
1317         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1318
1319         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1320
1321         HWRM_CHECK_RESULT();
1322
1323         link_info->phy_link_status = resp->link;
1324         link_info->link_up =
1325                 (link_info->phy_link_status ==
1326                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1327         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1328         link_info->duplex = resp->duplex_cfg;
1329         link_info->pause = resp->pause;
1330         link_info->auto_pause = resp->auto_pause;
1331         link_info->force_pause = resp->force_pause;
1332         link_info->auto_mode = resp->auto_mode;
1333         link_info->phy_type = resp->phy_type;
1334         link_info->media_type = resp->media_type;
1335
1336         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1337         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1338         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1339         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1340         link_info->phy_ver[0] = resp->phy_maj;
1341         link_info->phy_ver[1] = resp->phy_min;
1342         link_info->phy_ver[2] = resp->phy_bld;
1343
1344         HWRM_UNLOCK();
1345
1346         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1347                     link_info->link_speed, link_info->auto_mode,
1348                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1349                     link_info->support_speeds, link_info->force_link_speed);
1350         return rc;
1351 }
1352
1353 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1354 {
1355         int rc = 0;
1356         struct hwrm_port_phy_qcaps_input req = {0};
1357         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1358
1359         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1360                 return 0;
1361
1362         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1363
1364         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1365
1366         HWRM_CHECK_RESULT();
1367
1368         bp->port_cnt = resp->port_cnt;
1369
1370         HWRM_UNLOCK();
1371
1372         return 0;
1373 }
1374
1375 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1376 {
1377         int i = 0;
1378
1379         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1380                 if (bp->tx_cos_queue[i].profile ==
1381                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1382                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1383                         return true;
1384                 }
1385         }
1386         return false;
1387 }
1388
1389 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1390 {
1391         int i = 0;
1392
1393         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1394                 if (bp->tx_cos_queue[i].profile !=
1395                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1396                     bp->tx_cos_queue[i].id !=
1397                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1398                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1399                         break;
1400                 }
1401         }
1402 }
1403
1404 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1405 {
1406         int rc = 0;
1407         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1408         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1409         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1410         int i;
1411
1412 get_rx_info:
1413         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1414
1415         req.flags = rte_cpu_to_le_32(dir);
1416         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1417         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1418             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1419                 req.drv_qmap_cap =
1420                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1421         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1422
1423         HWRM_CHECK_RESULT();
1424
1425         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1426                 GET_TX_QUEUE_INFO(0);
1427                 GET_TX_QUEUE_INFO(1);
1428                 GET_TX_QUEUE_INFO(2);
1429                 GET_TX_QUEUE_INFO(3);
1430                 GET_TX_QUEUE_INFO(4);
1431                 GET_TX_QUEUE_INFO(5);
1432                 GET_TX_QUEUE_INFO(6);
1433                 GET_TX_QUEUE_INFO(7);
1434         } else  {
1435                 GET_RX_QUEUE_INFO(0);
1436                 GET_RX_QUEUE_INFO(1);
1437                 GET_RX_QUEUE_INFO(2);
1438                 GET_RX_QUEUE_INFO(3);
1439                 GET_RX_QUEUE_INFO(4);
1440                 GET_RX_QUEUE_INFO(5);
1441                 GET_RX_QUEUE_INFO(6);
1442                 GET_RX_QUEUE_INFO(7);
1443         }
1444
1445         HWRM_UNLOCK();
1446
1447         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1448                 goto done;
1449
1450         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1451                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1452         } else {
1453                 int j;
1454
1455                 /* iterate and find the COSq profile to use for Tx */
1456                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1457                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1458                                 if (bp->tx_cos_queue[i].id != 0xff)
1459                                         bp->tx_cosq_id[j++] =
1460                                                 bp->tx_cos_queue[i].id;
1461                         }
1462                 } else {
1463                         /* When CoS classification is disabled, for normal NIC
1464                          * operations, ideally we should look to use LOSSY.
1465                          * If not found, fallback to the first valid profile
1466                          */
1467                         if (!bnxt_find_lossy_profile(bp))
1468                                 bnxt_find_first_valid_profile(bp);
1469
1470                 }
1471         }
1472
1473         bp->max_tc = resp->max_configurable_queues;
1474         bp->max_lltc = resp->max_configurable_lossless_queues;
1475         if (bp->max_tc > BNXT_MAX_QUEUE)
1476                 bp->max_tc = BNXT_MAX_QUEUE;
1477         bp->max_q = bp->max_tc;
1478
1479         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1480                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1481                 goto get_rx_info;
1482         }
1483
1484 done:
1485         return rc;
1486 }
1487
1488 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1489                          struct bnxt_ring *ring,
1490                          uint32_t ring_type, uint32_t map_index,
1491                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1492                          uint16_t tx_cosq_id)
1493 {
1494         int rc = 0;
1495         uint32_t enables = 0;
1496         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1497         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1498         struct rte_mempool *mb_pool;
1499         uint16_t rx_buf_size;
1500
1501         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1502
1503         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1504         req.fbo = rte_cpu_to_le_32(0);
1505         /* Association of ring index with doorbell index */
1506         req.logical_id = rte_cpu_to_le_16(map_index);
1507         req.length = rte_cpu_to_le_32(ring->ring_size);
1508
1509         switch (ring_type) {
1510         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1511                 req.ring_type = ring_type;
1512                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1513                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1514                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1515                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1516                         enables |=
1517                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1518                 break;
1519         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1520                 req.ring_type = ring_type;
1521                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1522                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1523                 if (BNXT_CHIP_THOR(bp)) {
1524                         mb_pool = bp->rx_queues[0]->mb_pool;
1525                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1526                                       RTE_PKTMBUF_HEADROOM;
1527                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1528                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1529                         enables |=
1530                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1531                 }
1532                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1533                         enables |=
1534                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1535                 break;
1536         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1537                 req.ring_type = ring_type;
1538                 if (BNXT_HAS_NQ(bp)) {
1539                         /* Association of cp ring with nq */
1540                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1541                         enables |=
1542                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1543                 }
1544                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1545                 break;
1546         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1547                 req.ring_type = ring_type;
1548                 req.page_size = BNXT_PAGE_SHFT;
1549                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1550                 break;
1551         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1552                 req.ring_type = ring_type;
1553                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1554
1555                 mb_pool = bp->rx_queues[0]->mb_pool;
1556                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1557                               RTE_PKTMBUF_HEADROOM;
1558                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1559                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1560
1561                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1562                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1563                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1564                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1565                 break;
1566         default:
1567                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1568                         ring_type);
1569                 HWRM_UNLOCK();
1570                 return -EINVAL;
1571         }
1572         req.enables = rte_cpu_to_le_32(enables);
1573
1574         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1575
1576         if (rc || resp->error_code) {
1577                 if (rc == 0 && resp->error_code)
1578                         rc = rte_le_to_cpu_16(resp->error_code);
1579                 switch (ring_type) {
1580                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1581                         PMD_DRV_LOG(ERR,
1582                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1583                         HWRM_UNLOCK();
1584                         return rc;
1585                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1586                         PMD_DRV_LOG(ERR,
1587                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1588                         HWRM_UNLOCK();
1589                         return rc;
1590                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1591                         PMD_DRV_LOG(ERR,
1592                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1593                                     rc);
1594                         HWRM_UNLOCK();
1595                         return rc;
1596                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1597                         PMD_DRV_LOG(ERR,
1598                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1599                         HWRM_UNLOCK();
1600                         return rc;
1601                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1602                         PMD_DRV_LOG(ERR,
1603                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1604                         HWRM_UNLOCK();
1605                         return rc;
1606                 default:
1607                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1608                         HWRM_UNLOCK();
1609                         return rc;
1610                 }
1611         }
1612
1613         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1614         HWRM_UNLOCK();
1615         return rc;
1616 }
1617
1618 int bnxt_hwrm_ring_free(struct bnxt *bp,
1619                         struct bnxt_ring *ring, uint32_t ring_type)
1620 {
1621         int rc;
1622         struct hwrm_ring_free_input req = {.req_type = 0 };
1623         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1624
1625         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1626
1627         req.ring_type = ring_type;
1628         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1629
1630         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1631
1632         if (rc || resp->error_code) {
1633                 if (rc == 0 && resp->error_code)
1634                         rc = rte_le_to_cpu_16(resp->error_code);
1635                 HWRM_UNLOCK();
1636
1637                 switch (ring_type) {
1638                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1639                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1640                                 rc);
1641                         return rc;
1642                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1643                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1644                                 rc);
1645                         return rc;
1646                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1647                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1648                                 rc);
1649                         return rc;
1650                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1651                         PMD_DRV_LOG(ERR,
1652                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1653                         return rc;
1654                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1655                         PMD_DRV_LOG(ERR,
1656                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1657                         return rc;
1658                 default:
1659                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1660                         return rc;
1661                 }
1662         }
1663         HWRM_UNLOCK();
1664         return 0;
1665 }
1666
1667 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1668 {
1669         int rc = 0;
1670         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1671         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1672
1673         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1674
1675         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1676         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1677         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1678         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1679
1680         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1681
1682         HWRM_CHECK_RESULT();
1683
1684         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1685
1686         HWRM_UNLOCK();
1687
1688         return rc;
1689 }
1690
1691 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1692 {
1693         int rc;
1694         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1695         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1696
1697         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1698
1699         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1700
1701         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1702
1703         HWRM_CHECK_RESULT();
1704         HWRM_UNLOCK();
1705
1706         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1707         return rc;
1708 }
1709
1710 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1711 {
1712         int rc = 0;
1713         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1714         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1715
1716         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1717                 return rc;
1718
1719         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1720
1721         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1722
1723         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1724
1725         HWRM_CHECK_RESULT();
1726         HWRM_UNLOCK();
1727
1728         return rc;
1729 }
1730
1731 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1732                                 unsigned int idx __rte_unused)
1733 {
1734         int rc;
1735         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1736         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1737
1738         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1739
1740         req.update_period_ms = rte_cpu_to_le_32(0);
1741
1742         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1743
1744         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1745
1746         HWRM_CHECK_RESULT();
1747
1748         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1749
1750         HWRM_UNLOCK();
1751
1752         return rc;
1753 }
1754
1755 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1756                                 unsigned int idx __rte_unused)
1757 {
1758         int rc;
1759         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1760         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1761
1762         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1763
1764         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1765
1766         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1767
1768         HWRM_CHECK_RESULT();
1769         HWRM_UNLOCK();
1770
1771         return rc;
1772 }
1773
1774 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1775 {
1776         int rc = 0, i, j;
1777         struct hwrm_vnic_alloc_input req = { 0 };
1778         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1779
1780         if (!BNXT_HAS_RING_GRPS(bp))
1781                 goto skip_ring_grps;
1782
1783         /* map ring groups to this vnic */
1784         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1785                 vnic->start_grp_id, vnic->end_grp_id);
1786         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1787                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1788
1789         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1790         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1791         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1792         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1793
1794 skip_ring_grps:
1795         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1796         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1797
1798         if (vnic->func_default)
1799                 req.flags =
1800                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1801         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1802
1803         HWRM_CHECK_RESULT();
1804
1805         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1806         HWRM_UNLOCK();
1807         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1808         return rc;
1809 }
1810
1811 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1812                                         struct bnxt_vnic_info *vnic,
1813                                         struct bnxt_plcmodes_cfg *pmode)
1814 {
1815         int rc = 0;
1816         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1817         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1818
1819         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1820
1821         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1822
1823         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1824
1825         HWRM_CHECK_RESULT();
1826
1827         pmode->flags = rte_le_to_cpu_32(resp->flags);
1828         /* dflt_vnic bit doesn't exist in the _cfg command */
1829         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1830         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1831         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1832         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1833
1834         HWRM_UNLOCK();
1835
1836         return rc;
1837 }
1838
1839 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1840                                        struct bnxt_vnic_info *vnic,
1841                                        struct bnxt_plcmodes_cfg *pmode)
1842 {
1843         int rc = 0;
1844         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1845         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1846
1847         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1848                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1849                 return rc;
1850         }
1851
1852         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1853
1854         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1855         req.flags = rte_cpu_to_le_32(pmode->flags);
1856         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1857         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1858         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1859         req.enables = rte_cpu_to_le_32(
1860             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1861             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1862             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1863         );
1864
1865         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1866
1867         HWRM_CHECK_RESULT();
1868         HWRM_UNLOCK();
1869
1870         return rc;
1871 }
1872
1873 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1874 {
1875         int rc = 0;
1876         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1877         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1878         struct bnxt_plcmodes_cfg pmodes = { 0 };
1879         uint32_t ctx_enable_flag = 0;
1880         uint32_t enables = 0;
1881
1882         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1883                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1884                 return rc;
1885         }
1886
1887         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1888         if (rc)
1889                 return rc;
1890
1891         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1892
1893         if (BNXT_CHIP_THOR(bp)) {
1894                 int dflt_rxq = vnic->start_grp_id;
1895                 struct bnxt_rx_ring_info *rxr;
1896                 struct bnxt_cp_ring_info *cpr;
1897                 struct bnxt_rx_queue *rxq;
1898                 int i;
1899
1900                 /*
1901                  * The first active receive ring is used as the VNIC
1902                  * default receive ring. If there are no active receive
1903                  * rings (all corresponding receive queues are stopped),
1904                  * the first receive ring is used.
1905                  */
1906                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1907                         rxq = bp->eth_dev->data->rx_queues[i];
1908                         if (rxq->rx_started) {
1909                                 dflt_rxq = i;
1910                                 break;
1911                         }
1912                 }
1913
1914                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1915                 rxr = rxq->rx_ring;
1916                 cpr = rxq->cp_ring;
1917
1918                 req.default_rx_ring_id =
1919                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1920                 req.default_cmpl_ring_id =
1921                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1922                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1923                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1924                 goto config_mru;
1925         }
1926
1927         /* Only RSS support for now TBD: COS & LB */
1928         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1929         if (vnic->lb_rule != 0xffff)
1930                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1931         if (vnic->cos_rule != 0xffff)
1932                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1933         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1934                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1935                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1936         }
1937         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1938                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1939                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1940         }
1941
1942         enables |= ctx_enable_flag;
1943         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1944         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1945         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1946         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1947
1948 config_mru:
1949         req.enables = rte_cpu_to_le_32(enables);
1950         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1951         req.mru = rte_cpu_to_le_16(vnic->mru);
1952         /* Configure default VNIC only once. */
1953         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1954                 req.flags |=
1955                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1956                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1957         }
1958         if (vnic->vlan_strip)
1959                 req.flags |=
1960                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1961         if (vnic->bd_stall)
1962                 req.flags |=
1963                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1964         if (vnic->roce_dual)
1965                 req.flags |= rte_cpu_to_le_32(
1966                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1967         if (vnic->roce_only)
1968                 req.flags |= rte_cpu_to_le_32(
1969                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1970         if (vnic->rss_dflt_cr)
1971                 req.flags |= rte_cpu_to_le_32(
1972                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1973
1974         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1975
1976         HWRM_CHECK_RESULT();
1977         HWRM_UNLOCK();
1978
1979         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1980
1981         return rc;
1982 }
1983
1984 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1985                 int16_t fw_vf_id)
1986 {
1987         int rc = 0;
1988         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1989         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1990
1991         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1992                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1993                 return rc;
1994         }
1995         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
1996
1997         req.enables =
1998                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1999         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2000         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2001
2002         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2003
2004         HWRM_CHECK_RESULT();
2005
2006         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2007         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2008         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2009         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2010         vnic->mru = rte_le_to_cpu_16(resp->mru);
2011         vnic->func_default = rte_le_to_cpu_32(
2012                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2013         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2014                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2015         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2016                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2017         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
2018                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
2019         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
2020                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
2021         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2022                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2023
2024         HWRM_UNLOCK();
2025
2026         return rc;
2027 }
2028
2029 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2030                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2031 {
2032         int rc = 0;
2033         uint16_t ctx_id;
2034         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2035         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2036                                                 bp->hwrm_cmd_resp_addr;
2037
2038         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2039
2040         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2041         HWRM_CHECK_RESULT();
2042
2043         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2044         if (!BNXT_HAS_RING_GRPS(bp))
2045                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2046         else if (ctx_idx == 0)
2047                 vnic->rss_rule = ctx_id;
2048
2049         HWRM_UNLOCK();
2050
2051         return rc;
2052 }
2053
2054 static
2055 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2056                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2057 {
2058         int rc = 0;
2059         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2060         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2061                                                 bp->hwrm_cmd_resp_addr;
2062
2063         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2064                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2065                 return rc;
2066         }
2067         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2068
2069         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2070
2071         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2072
2073         HWRM_CHECK_RESULT();
2074         HWRM_UNLOCK();
2075
2076         return rc;
2077 }
2078
2079 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2080 {
2081         int rc = 0;
2082
2083         if (BNXT_CHIP_THOR(bp)) {
2084                 int j;
2085
2086                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2087                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2088                                                       vnic,
2089                                                       vnic->fw_grp_ids[j]);
2090                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2091                 }
2092                 vnic->num_lb_ctxts = 0;
2093         } else {
2094                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2095                 vnic->rss_rule = INVALID_HW_RING_ID;
2096         }
2097
2098         return rc;
2099 }
2100
2101 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2102 {
2103         int rc = 0;
2104         struct hwrm_vnic_free_input req = {.req_type = 0 };
2105         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2106
2107         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2108                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2109                 return rc;
2110         }
2111
2112         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2113
2114         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2115
2116         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2117
2118         HWRM_CHECK_RESULT();
2119         HWRM_UNLOCK();
2120
2121         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2122         /* Configure default VNIC again if necessary. */
2123         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2124                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2125
2126         return rc;
2127 }
2128
2129 static int
2130 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2131 {
2132         int i;
2133         int rc = 0;
2134         int nr_ctxs = vnic->num_lb_ctxts;
2135         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2136         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2137
2138         for (i = 0; i < nr_ctxs; i++) {
2139                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2140
2141                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2142                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2143                 req.hash_mode_flags = vnic->hash_mode;
2144
2145                 req.hash_key_tbl_addr =
2146                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2147
2148                 req.ring_grp_tbl_addr =
2149                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2150                                          i * HW_HASH_INDEX_SIZE);
2151                 req.ring_table_pair_index = i;
2152                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2153
2154                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2155                                             BNXT_USE_CHIMP_MB);
2156
2157                 HWRM_CHECK_RESULT();
2158                 HWRM_UNLOCK();
2159         }
2160
2161         return rc;
2162 }
2163
2164 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2165                            struct bnxt_vnic_info *vnic)
2166 {
2167         int rc = 0;
2168         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2169         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2170
2171         if (!vnic->rss_table)
2172                 return 0;
2173
2174         if (BNXT_CHIP_THOR(bp))
2175                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2176
2177         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2178
2179         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2180         req.hash_mode_flags = vnic->hash_mode;
2181
2182         req.ring_grp_tbl_addr =
2183             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2184         req.hash_key_tbl_addr =
2185             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2186         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2187         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2188
2189         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2190
2191         HWRM_CHECK_RESULT();
2192         HWRM_UNLOCK();
2193
2194         return rc;
2195 }
2196
2197 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2198                         struct bnxt_vnic_info *vnic)
2199 {
2200         int rc = 0;
2201         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2202         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2203         uint16_t size;
2204
2205         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2206                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2207                 return rc;
2208         }
2209
2210         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2211
2212         req.flags = rte_cpu_to_le_32(
2213                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2214
2215         req.enables = rte_cpu_to_le_32(
2216                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2217
2218         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2219         size -= RTE_PKTMBUF_HEADROOM;
2220         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2221
2222         req.jumbo_thresh = rte_cpu_to_le_16(size);
2223         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2224
2225         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2226
2227         HWRM_CHECK_RESULT();
2228         HWRM_UNLOCK();
2229
2230         return rc;
2231 }
2232
2233 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2234                         struct bnxt_vnic_info *vnic, bool enable)
2235 {
2236         int rc = 0;
2237         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2238         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2239
2240         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2241                 if (enable)
2242                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2243                 return -ENOTSUP;
2244         }
2245
2246         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2247                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2248                 return 0;
2249         }
2250
2251         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2252
2253         if (enable) {
2254                 req.enables = rte_cpu_to_le_32(
2255                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2256                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2257                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2258                 req.flags = rte_cpu_to_le_32(
2259                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2260                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2261                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2262                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2263                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2264                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2265                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2266                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2267                 req.min_agg_len = rte_cpu_to_le_32(512);
2268         }
2269         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2270
2271         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2272
2273         HWRM_CHECK_RESULT();
2274         HWRM_UNLOCK();
2275
2276         return rc;
2277 }
2278
2279 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2280 {
2281         struct hwrm_func_cfg_input req = {0};
2282         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2283         int rc;
2284
2285         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2286         req.enables = rte_cpu_to_le_32(
2287                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2288         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2289         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2290
2291         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2292
2293         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2294         HWRM_CHECK_RESULT();
2295         HWRM_UNLOCK();
2296
2297         bp->pf->vf_info[vf].random_mac = false;
2298
2299         return rc;
2300 }
2301
2302 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2303                                   uint64_t *dropped)
2304 {
2305         int rc = 0;
2306         struct hwrm_func_qstats_input req = {.req_type = 0};
2307         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2308
2309         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2310
2311         req.fid = rte_cpu_to_le_16(fid);
2312
2313         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2314
2315         HWRM_CHECK_RESULT();
2316
2317         if (dropped)
2318                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2319
2320         HWRM_UNLOCK();
2321
2322         return rc;
2323 }
2324
2325 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2326                           struct rte_eth_stats *stats,
2327                           struct hwrm_func_qstats_output *func_qstats)
2328 {
2329         int rc = 0;
2330         struct hwrm_func_qstats_input req = {.req_type = 0};
2331         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2332
2333         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2334
2335         req.fid = rte_cpu_to_le_16(fid);
2336
2337         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2338
2339         HWRM_CHECK_RESULT();
2340         if (func_qstats)
2341                 memcpy(func_qstats, resp,
2342                        sizeof(struct hwrm_func_qstats_output));
2343
2344         if (!stats)
2345                 goto exit;
2346
2347         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2348         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2349         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2350         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2351         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2352         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2353
2354         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2355         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2356         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2357         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2358         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2359         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2360
2361         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2362         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2363         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2364
2365 exit:
2366         HWRM_UNLOCK();
2367
2368         return rc;
2369 }
2370
2371 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2372 {
2373         int rc = 0;
2374         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2375         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2376
2377         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2378
2379         req.fid = rte_cpu_to_le_16(fid);
2380
2381         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2382
2383         HWRM_CHECK_RESULT();
2384         HWRM_UNLOCK();
2385
2386         return rc;
2387 }
2388
2389 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2390 {
2391         unsigned int i;
2392         int rc = 0;
2393
2394         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2395                 struct bnxt_tx_queue *txq;
2396                 struct bnxt_rx_queue *rxq;
2397                 struct bnxt_cp_ring_info *cpr;
2398
2399                 if (i >= bp->rx_cp_nr_rings) {
2400                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2401                         cpr = txq->cp_ring;
2402                 } else {
2403                         rxq = bp->rx_queues[i];
2404                         cpr = rxq->cp_ring;
2405                 }
2406
2407                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2408                 if (rc)
2409                         return rc;
2410         }
2411         return 0;
2412 }
2413
2414 static int
2415 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2416 {
2417         int rc;
2418         unsigned int i;
2419         struct bnxt_cp_ring_info *cpr;
2420
2421         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2422
2423                 if (i >= bp->rx_cp_nr_rings) {
2424                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2425                 } else {
2426                         cpr = bp->rx_queues[i]->cp_ring;
2427                         if (BNXT_HAS_RING_GRPS(bp))
2428                                 bp->grp_info[i].fw_stats_ctx = -1;
2429                 }
2430                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2431                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2432                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2433                         if (rc)
2434                                 return rc;
2435                 }
2436         }
2437         return 0;
2438 }
2439
2440 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2441 {
2442         unsigned int i;
2443         int rc = 0;
2444
2445         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2446                 struct bnxt_tx_queue *txq;
2447                 struct bnxt_rx_queue *rxq;
2448                 struct bnxt_cp_ring_info *cpr;
2449
2450                 if (i >= bp->rx_cp_nr_rings) {
2451                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2452                         cpr = txq->cp_ring;
2453                 } else {
2454                         rxq = bp->rx_queues[i];
2455                         cpr = rxq->cp_ring;
2456                 }
2457
2458                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2459
2460                 if (rc)
2461                         return rc;
2462         }
2463         return rc;
2464 }
2465
2466 static int
2467 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2468 {
2469         uint16_t idx;
2470         uint32_t rc = 0;
2471
2472         if (!BNXT_HAS_RING_GRPS(bp))
2473                 return 0;
2474
2475         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2476
2477                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2478                         continue;
2479
2480                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2481
2482                 if (rc)
2483                         return rc;
2484         }
2485         return rc;
2486 }
2487
2488 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2489 {
2490         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2491
2492         bnxt_hwrm_ring_free(bp, cp_ring,
2493                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2494         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2495         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2496                                      sizeof(*cpr->cp_desc_ring));
2497         cpr->cp_raw_cons = 0;
2498         cpr->valid = 0;
2499 }
2500
2501 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2502 {
2503         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2504
2505         bnxt_hwrm_ring_free(bp, cp_ring,
2506                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2507         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2508         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2509                         sizeof(*cpr->cp_desc_ring));
2510         cpr->cp_raw_cons = 0;
2511         cpr->valid = 0;
2512 }
2513
2514 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2515 {
2516         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2517         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2518         struct bnxt_ring *ring = rxr->rx_ring_struct;
2519         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2520
2521         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2522                 bnxt_hwrm_ring_free(bp, ring,
2523                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2524                 ring->fw_ring_id = INVALID_HW_RING_ID;
2525                 if (BNXT_HAS_RING_GRPS(bp))
2526                         bp->grp_info[queue_index].rx_fw_ring_id =
2527                                                         INVALID_HW_RING_ID;
2528         }
2529         ring = rxr->ag_ring_struct;
2530         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2531                 bnxt_hwrm_ring_free(bp, ring,
2532                                     BNXT_CHIP_THOR(bp) ?
2533                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2534                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2535                 if (BNXT_HAS_RING_GRPS(bp))
2536                         bp->grp_info[queue_index].ag_fw_ring_id =
2537                                                         INVALID_HW_RING_ID;
2538         }
2539         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2540                 bnxt_free_cp_ring(bp, cpr);
2541
2542         if (BNXT_HAS_RING_GRPS(bp))
2543                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2544 }
2545
2546 static int
2547 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2548 {
2549         unsigned int i;
2550
2551         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2552                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2553                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2554                 struct bnxt_ring *ring = txr->tx_ring_struct;
2555                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2556
2557                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2558                         bnxt_hwrm_ring_free(bp, ring,
2559                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2560                         ring->fw_ring_id = INVALID_HW_RING_ID;
2561                         memset(txr->tx_desc_ring, 0,
2562                                         txr->tx_ring_struct->ring_size *
2563                                         sizeof(*txr->tx_desc_ring));
2564                         memset(txr->tx_buf_ring, 0,
2565                                         txr->tx_ring_struct->ring_size *
2566                                         sizeof(*txr->tx_buf_ring));
2567                         txr->tx_prod = 0;
2568                         txr->tx_cons = 0;
2569                 }
2570                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2571                         bnxt_free_cp_ring(bp, cpr);
2572                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2573                 }
2574         }
2575
2576         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2577                 bnxt_free_hwrm_rx_ring(bp, i);
2578
2579         return 0;
2580 }
2581
2582 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2583 {
2584         uint16_t i;
2585         uint32_t rc = 0;
2586
2587         if (!BNXT_HAS_RING_GRPS(bp))
2588                 return 0;
2589
2590         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2591                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2592                 if (rc)
2593                         return rc;
2594         }
2595         return rc;
2596 }
2597
2598 /*
2599  * HWRM utility functions
2600  */
2601
2602 void bnxt_free_hwrm_resources(struct bnxt *bp)
2603 {
2604         /* Release memzone */
2605         rte_free(bp->hwrm_cmd_resp_addr);
2606         rte_free(bp->hwrm_short_cmd_req_addr);
2607         bp->hwrm_cmd_resp_addr = NULL;
2608         bp->hwrm_short_cmd_req_addr = NULL;
2609         bp->hwrm_cmd_resp_dma_addr = 0;
2610         bp->hwrm_short_cmd_req_dma_addr = 0;
2611 }
2612
2613 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2614 {
2615         struct rte_pci_device *pdev = bp->pdev;
2616         char type[RTE_MEMZONE_NAMESIZE];
2617
2618         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2619                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2620         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2621         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2622         if (bp->hwrm_cmd_resp_addr == NULL)
2623                 return -ENOMEM;
2624         bp->hwrm_cmd_resp_dma_addr =
2625                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2626         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2627                 PMD_DRV_LOG(ERR,
2628                         "unable to map response address to physical memory\n");
2629                 return -ENOMEM;
2630         }
2631         rte_spinlock_init(&bp->hwrm_lock);
2632
2633         return 0;
2634 }
2635
2636 int
2637 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2638 {
2639         int rc = 0;
2640
2641         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2642                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2643                 if (rc)
2644                         return rc;
2645         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2646                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2647                 if (rc)
2648                         return rc;
2649         }
2650
2651         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2652         return rc;
2653 }
2654
2655 static int
2656 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2657 {
2658         struct bnxt_filter_info *filter;
2659         int rc = 0;
2660
2661         STAILQ_FOREACH(filter, &vnic->filter, next) {
2662                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2663                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2664                 bnxt_free_filter(bp, filter);
2665         }
2666         return rc;
2667 }
2668
2669 static int
2670 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2671 {
2672         struct bnxt_filter_info *filter;
2673         struct rte_flow *flow;
2674         int rc = 0;
2675
2676         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2677                 flow = STAILQ_FIRST(&vnic->flow_list);
2678                 filter = flow->filter;
2679                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2680                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2681
2682                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2683                 rte_free(flow);
2684         }
2685         return rc;
2686 }
2687
2688 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2689 {
2690         struct bnxt_filter_info *filter;
2691         int rc = 0;
2692
2693         STAILQ_FOREACH(filter, &vnic->filter, next) {
2694                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2695                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2696                                                      filter);
2697                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2698                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2699                                                          filter);
2700                 else
2701                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2702                                                      filter);
2703                 if (rc)
2704                         break;
2705         }
2706         return rc;
2707 }
2708
2709 static void
2710 bnxt_free_tunnel_ports(struct bnxt *bp)
2711 {
2712         if (bp->vxlan_port_cnt)
2713                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2714                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2715         bp->vxlan_port = 0;
2716         if (bp->geneve_port_cnt)
2717                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2718                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2719         bp->geneve_port = 0;
2720 }
2721
2722 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2723 {
2724         int i;
2725
2726         if (bp->vnic_info == NULL)
2727                 return;
2728
2729         /*
2730          * Cleanup VNICs in reverse order, to make sure the L2 filter
2731          * from vnic0 is last to be cleaned up.
2732          */
2733         for (i = bp->max_vnics - 1; i >= 0; i--) {
2734                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2735
2736                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2737                         continue;
2738
2739                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2740
2741                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2742
2743                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2744
2745                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2746
2747                 bnxt_hwrm_vnic_free(bp, vnic);
2748
2749                 rte_free(vnic->fw_grp_ids);
2750         }
2751         /* Ring resources */
2752         bnxt_free_all_hwrm_rings(bp);
2753         bnxt_free_all_hwrm_ring_grps(bp);
2754         bnxt_free_all_hwrm_stat_ctxs(bp);
2755         bnxt_free_tunnel_ports(bp);
2756 }
2757
2758 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2759 {
2760         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2761
2762         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2763                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2764
2765         switch (conf_link_speed) {
2766         case ETH_LINK_SPEED_10M_HD:
2767         case ETH_LINK_SPEED_100M_HD:
2768                 /* FALLTHROUGH */
2769                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2770         }
2771         return hw_link_duplex;
2772 }
2773
2774 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2775 {
2776         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2777 }
2778
2779 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2780 {
2781         uint16_t eth_link_speed = 0;
2782
2783         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2784                 return ETH_LINK_SPEED_AUTONEG;
2785
2786         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2787         case ETH_LINK_SPEED_100M:
2788         case ETH_LINK_SPEED_100M_HD:
2789                 /* FALLTHROUGH */
2790                 eth_link_speed =
2791                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2792                 break;
2793         case ETH_LINK_SPEED_1G:
2794                 eth_link_speed =
2795                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2796                 break;
2797         case ETH_LINK_SPEED_2_5G:
2798                 eth_link_speed =
2799                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2800                 break;
2801         case ETH_LINK_SPEED_10G:
2802                 eth_link_speed =
2803                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2804                 break;
2805         case ETH_LINK_SPEED_20G:
2806                 eth_link_speed =
2807                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2808                 break;
2809         case ETH_LINK_SPEED_25G:
2810                 eth_link_speed =
2811                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2812                 break;
2813         case ETH_LINK_SPEED_40G:
2814                 eth_link_speed =
2815                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2816                 break;
2817         case ETH_LINK_SPEED_50G:
2818                 eth_link_speed =
2819                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2820                 break;
2821         case ETH_LINK_SPEED_100G:
2822                 eth_link_speed =
2823                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2824                 break;
2825         case ETH_LINK_SPEED_200G:
2826                 eth_link_speed =
2827                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB;
2828                 break;
2829         default:
2830                 PMD_DRV_LOG(ERR,
2831                         "Unsupported link speed %d; default to AUTO\n",
2832                         conf_link_speed);
2833                 break;
2834         }
2835         return eth_link_speed;
2836 }
2837
2838 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2839                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2840                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2841                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2842                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2843
2844 static int bnxt_validate_link_speed(struct bnxt *bp)
2845 {
2846         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2847         uint16_t port_id = bp->eth_dev->data->port_id;
2848         uint32_t link_speed_capa;
2849         uint32_t one_speed;
2850
2851         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2852                 return 0;
2853
2854         link_speed_capa = bnxt_get_speed_capabilities(bp);
2855
2856         if (link_speed & ETH_LINK_SPEED_FIXED) {
2857                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2858
2859                 if (one_speed & (one_speed - 1)) {
2860                         PMD_DRV_LOG(ERR,
2861                                 "Invalid advertised speeds (%u) for port %u\n",
2862                                 link_speed, port_id);
2863                         return -EINVAL;
2864                 }
2865                 if ((one_speed & link_speed_capa) != one_speed) {
2866                         PMD_DRV_LOG(ERR,
2867                                 "Unsupported advertised speed (%u) for port %u\n",
2868                                 link_speed, port_id);
2869                         return -EINVAL;
2870                 }
2871         } else {
2872                 if (!(link_speed & link_speed_capa)) {
2873                         PMD_DRV_LOG(ERR,
2874                                 "Unsupported advertised speeds (%u) for port %u\n",
2875                                 link_speed, port_id);
2876                         return -EINVAL;
2877                 }
2878         }
2879         return 0;
2880 }
2881
2882 static uint16_t
2883 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2884 {
2885         uint16_t ret = 0;
2886
2887         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2888                 if (bp->link_info->support_speeds)
2889                         return bp->link_info->support_speeds;
2890                 link_speed = BNXT_SUPPORTED_SPEEDS;
2891         }
2892
2893         if (link_speed & ETH_LINK_SPEED_100M)
2894                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2895         if (link_speed & ETH_LINK_SPEED_100M_HD)
2896                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2897         if (link_speed & ETH_LINK_SPEED_1G)
2898                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2899         if (link_speed & ETH_LINK_SPEED_2_5G)
2900                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2901         if (link_speed & ETH_LINK_SPEED_10G)
2902                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2903         if (link_speed & ETH_LINK_SPEED_20G)
2904                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2905         if (link_speed & ETH_LINK_SPEED_25G)
2906                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2907         if (link_speed & ETH_LINK_SPEED_40G)
2908                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2909         if (link_speed & ETH_LINK_SPEED_50G)
2910                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2911         if (link_speed & ETH_LINK_SPEED_100G)
2912                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2913         if (link_speed & ETH_LINK_SPEED_200G)
2914                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB;
2915         return ret;
2916 }
2917
2918 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2919 {
2920         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2921
2922         switch (hw_link_speed) {
2923         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2924                 eth_link_speed = ETH_SPEED_NUM_100M;
2925                 break;
2926         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2927                 eth_link_speed = ETH_SPEED_NUM_1G;
2928                 break;
2929         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2930                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2931                 break;
2932         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2933                 eth_link_speed = ETH_SPEED_NUM_10G;
2934                 break;
2935         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2936                 eth_link_speed = ETH_SPEED_NUM_20G;
2937                 break;
2938         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2939                 eth_link_speed = ETH_SPEED_NUM_25G;
2940                 break;
2941         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2942                 eth_link_speed = ETH_SPEED_NUM_40G;
2943                 break;
2944         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2945                 eth_link_speed = ETH_SPEED_NUM_50G;
2946                 break;
2947         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2948                 eth_link_speed = ETH_SPEED_NUM_100G;
2949                 break;
2950         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
2951                 eth_link_speed = ETH_SPEED_NUM_200G;
2952                 break;
2953         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2954         default:
2955                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2956                         hw_link_speed);
2957                 break;
2958         }
2959         return eth_link_speed;
2960 }
2961
2962 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2963 {
2964         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2965
2966         switch (hw_link_duplex) {
2967         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2968         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2969                 /* FALLTHROUGH */
2970                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2971                 break;
2972         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2973                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2974                 break;
2975         default:
2976                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2977                         hw_link_duplex);
2978                 break;
2979         }
2980         return eth_link_duplex;
2981 }
2982
2983 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2984 {
2985         int rc = 0;
2986         struct bnxt_link_info *link_info = bp->link_info;
2987
2988         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2989         if (rc) {
2990                 PMD_DRV_LOG(ERR,
2991                         "Get link config failed with rc %d\n", rc);
2992                 goto exit;
2993         }
2994         if (link_info->link_speed)
2995                 link->link_speed =
2996                         bnxt_parse_hw_link_speed(link_info->link_speed);
2997         else
2998                 link->link_speed = ETH_SPEED_NUM_NONE;
2999         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3000         link->link_status = link_info->link_up;
3001         link->link_autoneg = link_info->auto_mode ==
3002                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3003                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3004 exit:
3005         return rc;
3006 }
3007
3008 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3009 {
3010         int rc = 0;
3011         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3012         struct bnxt_link_info link_req;
3013         uint16_t speed, autoneg;
3014
3015         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3016                 return 0;
3017
3018         rc = bnxt_validate_link_speed(bp);
3019         if (rc)
3020                 goto error;
3021
3022         memset(&link_req, 0, sizeof(link_req));
3023         link_req.link_up = link_up;
3024         if (!link_up)
3025                 goto port_phy_cfg;
3026
3027         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3028         if (BNXT_CHIP_THOR(bp) &&
3029             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3030                 /* 40G is not supported as part of media auto detect.
3031                  * The speed should be forced and autoneg disabled
3032                  * to configure 40G speed.
3033                  */
3034                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3035                 autoneg = 0;
3036         }
3037
3038         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
3039         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3040         /* Autoneg can be done only when the FW allows.
3041          * When user configures fixed speed of 40G and later changes to
3042          * any other speed, auto_link_speed/force_link_speed is still set
3043          * to 40G until link comes up at new speed.
3044          */
3045         if (autoneg == 1 &&
3046             !(!BNXT_CHIP_THOR(bp) &&
3047               (bp->link_info->auto_link_speed ||
3048                bp->link_info->force_link_speed))) {
3049                 link_req.phy_flags |=
3050                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3051                 link_req.auto_link_speed_mask =
3052                         bnxt_parse_eth_link_speed_mask(bp,
3053                                                        dev_conf->link_speeds);
3054         } else {
3055                 if (bp->link_info->phy_type ==
3056                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3057                     bp->link_info->phy_type ==
3058                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3059                     bp->link_info->media_type ==
3060                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3061                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3062                         return -EINVAL;
3063                 }
3064
3065                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3066                 /* If user wants a particular speed try that first. */
3067                 if (speed)
3068                         link_req.link_speed = speed;
3069                 else if (bp->link_info->force_link_speed)
3070                         link_req.link_speed = bp->link_info->force_link_speed;
3071                 else
3072                         link_req.link_speed = bp->link_info->auto_link_speed;
3073         }
3074         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3075         link_req.auto_pause = bp->link_info->auto_pause;
3076         link_req.force_pause = bp->link_info->force_pause;
3077
3078 port_phy_cfg:
3079         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3080         if (rc) {
3081                 PMD_DRV_LOG(ERR,
3082                         "Set link config failed with rc %d\n", rc);
3083         }
3084
3085 error:
3086         return rc;
3087 }
3088
3089 /* JIRA 22088 */
3090 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3091 {
3092         struct hwrm_func_qcfg_input req = {0};
3093         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3094         uint16_t flags;
3095         int rc = 0;
3096         bp->func_svif = BNXT_SVIF_INVALID;
3097         uint16_t svif_info;
3098
3099         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3100         req.fid = rte_cpu_to_le_16(0xffff);
3101
3102         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3103
3104         HWRM_CHECK_RESULT();
3105
3106         /* Hard Coded.. 0xfff VLAN ID mask */
3107         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3108
3109         svif_info = rte_le_to_cpu_16(resp->svif_info);
3110         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3111                 bp->func_svif = svif_info &
3112                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3113
3114         flags = rte_le_to_cpu_16(resp->flags);
3115         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3116                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3117
3118         if (BNXT_VF(bp) &&
3119             !BNXT_VF_IS_TRUSTED(bp) &&
3120             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3121                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3122                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3123         } else if (BNXT_VF(bp) &&
3124                    BNXT_VF_IS_TRUSTED(bp) &&
3125                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3126                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3127                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3128         }
3129
3130         if (mtu)
3131                 *mtu = rte_le_to_cpu_16(resp->mtu);
3132
3133         switch (resp->port_partition_type) {
3134         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3135         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3136         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3137                 /* FALLTHROUGH */
3138                 bp->flags |= BNXT_FLAG_NPAR_PF;
3139                 break;
3140         default:
3141                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3142                 break;
3143         }
3144
3145         HWRM_UNLOCK();
3146
3147         return rc;
3148 }
3149
3150 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3151 {
3152         struct hwrm_func_qcfg_input req = {0};
3153         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3154         int rc;
3155
3156         if (!BNXT_VF_IS_TRUSTED(bp))
3157                 return 0;
3158
3159         if (!bp->parent)
3160                 return -EINVAL;
3161
3162         bp->parent->fid = BNXT_PF_FID_INVALID;
3163
3164         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3165
3166         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3167
3168         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3169
3170         HWRM_CHECK_RESULT();
3171
3172         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3173         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3174         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3175         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3176
3177         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3178         if (bp->parent->vnic == 0) {
3179                 PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
3180                 /* Use hard-coded values appropriate for current Wh+ fw. */
3181                 if (bp->parent->fid == 2)
3182                         bp->parent->vnic = 0x100;
3183                 else
3184                         bp->parent->vnic = 1;
3185         }
3186
3187         HWRM_UNLOCK();
3188
3189         return 0;
3190 }
3191
3192 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3193                                  uint16_t *vnic_id, uint16_t *svif)
3194 {
3195         struct hwrm_func_qcfg_input req = {0};
3196         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3197         uint16_t svif_info;
3198         int rc = 0;
3199
3200         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3201         req.fid = rte_cpu_to_le_16(fid);
3202
3203         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3204
3205         HWRM_CHECK_RESULT();
3206
3207         if (vnic_id)
3208                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3209
3210         svif_info = rte_le_to_cpu_16(resp->svif_info);
3211         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3212                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3213
3214         HWRM_UNLOCK();
3215
3216         return rc;
3217 }
3218
3219 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3220 {
3221         struct hwrm_port_mac_qcfg_input req = {0};
3222         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3223         uint16_t port_svif_info;
3224         int rc;
3225
3226         bp->port_svif = BNXT_SVIF_INVALID;
3227
3228         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3229                 return 0;
3230
3231         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3232
3233         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3234
3235         HWRM_CHECK_RESULT_SILENT();
3236
3237         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3238         if (port_svif_info &
3239             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3240                 bp->port_svif = port_svif_info &
3241                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3242
3243         HWRM_UNLOCK();
3244
3245         return 0;
3246 }
3247
3248 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3249                                    struct hwrm_func_qcaps_output *qcaps)
3250 {
3251         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3252         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3253                sizeof(qcaps->mac_address));
3254         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3255         qcaps->max_rx_rings = fcfg->num_rx_rings;
3256         qcaps->max_tx_rings = fcfg->num_tx_rings;
3257         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3258         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3259         qcaps->max_vfs = 0;
3260         qcaps->first_vf_id = 0;
3261         qcaps->max_vnics = fcfg->num_vnics;
3262         qcaps->max_decap_records = 0;
3263         qcaps->max_encap_records = 0;
3264         qcaps->max_tx_wm_flows = 0;
3265         qcaps->max_tx_em_flows = 0;
3266         qcaps->max_rx_wm_flows = 0;
3267         qcaps->max_rx_em_flows = 0;
3268         qcaps->max_flow_id = 0;
3269         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3270         qcaps->max_sp_tx_rings = 0;
3271         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3272 }
3273
3274 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3275 {
3276         struct hwrm_func_cfg_input req = {0};
3277         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3278         uint32_t enables;
3279         int rc;
3280
3281         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3282                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3283                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3284                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3285                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3286                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3287                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3288                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3289                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3290
3291         if (BNXT_HAS_RING_GRPS(bp)) {
3292                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3293                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3294         } else if (BNXT_HAS_NQ(bp)) {
3295                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3296                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3297         }
3298
3299         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3300         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3301         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3302         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3303         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3304         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3305         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3306         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3307         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3308         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3309         req.fid = rte_cpu_to_le_16(0xffff);
3310         req.enables = rte_cpu_to_le_32(enables);
3311
3312         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3313
3314         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3315
3316         HWRM_CHECK_RESULT();
3317         HWRM_UNLOCK();
3318
3319         return rc;
3320 }
3321
3322 static void populate_vf_func_cfg_req(struct bnxt *bp,
3323                                      struct hwrm_func_cfg_input *req,
3324                                      int num_vfs)
3325 {
3326         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3327                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3328                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3329                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3330                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3331                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3332                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3333                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3334                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3335                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3336
3337         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3338                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3339                                     BNXT_NUM_VLANS);
3340         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3341         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3342                                                 (num_vfs + 1));
3343         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3344         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3345                                                (num_vfs + 1));
3346         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3347         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3348         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3349         /* TODO: For now, do not support VMDq/RFS on VFs. */
3350         req->num_vnics = rte_cpu_to_le_16(1);
3351         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3352                                                  (num_vfs + 1));
3353 }
3354
3355 static void add_random_mac_if_needed(struct bnxt *bp,
3356                                      struct hwrm_func_cfg_input *cfg_req,
3357                                      int vf)
3358 {
3359         struct rte_ether_addr mac;
3360
3361         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3362                 return;
3363
3364         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3365                 cfg_req->enables |=
3366                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3367                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3368                 bp->pf->vf_info[vf].random_mac = true;
3369         } else {
3370                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3371                         RTE_ETHER_ADDR_LEN);
3372         }
3373 }
3374
3375 static int reserve_resources_from_vf(struct bnxt *bp,
3376                                      struct hwrm_func_cfg_input *cfg_req,
3377                                      int vf)
3378 {
3379         struct hwrm_func_qcaps_input req = {0};
3380         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3381         int rc;
3382
3383         /* Get the actual allocated values now */
3384         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3385         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3386         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3387
3388         if (rc) {
3389                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3390                 copy_func_cfg_to_qcaps(cfg_req, resp);
3391         } else if (resp->error_code) {
3392                 rc = rte_le_to_cpu_16(resp->error_code);
3393                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3394                 copy_func_cfg_to_qcaps(cfg_req, resp);
3395         }
3396
3397         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3398         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3399         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3400         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3401         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3402         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3403         /*
3404          * TODO: While not supporting VMDq with VFs, max_vnics is always
3405          * forced to 1 in this case
3406          */
3407         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3408         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3409
3410         HWRM_UNLOCK();
3411
3412         return 0;
3413 }
3414
3415 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3416 {
3417         struct hwrm_func_qcfg_input req = {0};
3418         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3419         int rc;
3420
3421         /* Check for zero MAC address */
3422         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3423         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3424         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3425         HWRM_CHECK_RESULT();
3426         rc = rte_le_to_cpu_16(resp->vlan);
3427
3428         HWRM_UNLOCK();
3429
3430         return rc;
3431 }
3432
3433 static int update_pf_resource_max(struct bnxt *bp)
3434 {
3435         struct hwrm_func_qcfg_input req = {0};
3436         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3437         int rc;
3438
3439         /* And copy the allocated numbers into the pf struct */
3440         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3441         req.fid = rte_cpu_to_le_16(0xffff);
3442         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3443         HWRM_CHECK_RESULT();
3444
3445         /* Only TX ring value reflects actual allocation? TODO */
3446         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3447         bp->pf->evb_mode = resp->evb_mode;
3448
3449         HWRM_UNLOCK();
3450
3451         return rc;
3452 }
3453
3454 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3455 {
3456         int rc;
3457
3458         if (!BNXT_PF(bp)) {
3459                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3460                 return -EINVAL;
3461         }
3462
3463         rc = bnxt_hwrm_func_qcaps(bp);
3464         if (rc)
3465                 return rc;
3466
3467         bp->pf->func_cfg_flags &=
3468                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3469                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3470         bp->pf->func_cfg_flags |=
3471                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3472         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3473         rc = __bnxt_hwrm_func_qcaps(bp);
3474         return rc;
3475 }
3476
3477 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3478 {
3479         struct hwrm_func_cfg_input req = {0};
3480         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3481         int i;
3482         size_t sz;
3483         int rc = 0;
3484         size_t req_buf_sz;
3485
3486         if (!BNXT_PF(bp)) {
3487                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3488                 return -EINVAL;
3489         }
3490
3491         rc = bnxt_hwrm_func_qcaps(bp);
3492
3493         if (rc)
3494                 return rc;
3495
3496         bp->pf->active_vfs = num_vfs;
3497
3498         /*
3499          * First, configure the PF to only use one TX ring.  This ensures that
3500          * there are enough rings for all VFs.
3501          *
3502          * If we don't do this, when we call func_alloc() later, we will lock
3503          * extra rings to the PF that won't be available during func_cfg() of
3504          * the VFs.
3505          *
3506          * This has been fixed with firmware versions above 20.6.54
3507          */
3508         bp->pf->func_cfg_flags &=
3509                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3510                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3511         bp->pf->func_cfg_flags |=
3512                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3513         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3514         if (rc)
3515                 return rc;
3516
3517         /*
3518          * Now, create and register a buffer to hold forwarded VF requests
3519          */
3520         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3521         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3522                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3523         if (bp->pf->vf_req_buf == NULL) {
3524                 rc = -ENOMEM;
3525                 goto error_free;
3526         }
3527         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3528                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3529         for (i = 0; i < num_vfs; i++)
3530                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3531                                         (i * HWRM_MAX_REQ_LEN);
3532
3533         rc = bnxt_hwrm_func_buf_rgtr(bp);
3534         if (rc)
3535                 goto error_free;
3536
3537         populate_vf_func_cfg_req(bp, &req, num_vfs);
3538
3539         bp->pf->active_vfs = 0;
3540         for (i = 0; i < num_vfs; i++) {
3541                 add_random_mac_if_needed(bp, &req, i);
3542
3543                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3544                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3545                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3546                 rc = bnxt_hwrm_send_message(bp,
3547                                             &req,
3548                                             sizeof(req),
3549                                             BNXT_USE_CHIMP_MB);
3550
3551                 /* Clear enable flag for next pass */
3552                 req.enables &= ~rte_cpu_to_le_32(
3553                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3554
3555                 if (rc || resp->error_code) {
3556                         PMD_DRV_LOG(ERR,
3557                                 "Failed to initizlie VF %d\n", i);
3558                         PMD_DRV_LOG(ERR,
3559                                 "Not all VFs available. (%d, %d)\n",
3560                                 rc, resp->error_code);
3561                         HWRM_UNLOCK();
3562                         break;
3563                 }
3564
3565                 HWRM_UNLOCK();
3566
3567                 reserve_resources_from_vf(bp, &req, i);
3568                 bp->pf->active_vfs++;
3569                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3570         }
3571
3572         /*
3573          * Now configure the PF to use "the rest" of the resources
3574          * We're using STD_TX_RING_MODE here though which will limit the TX
3575          * rings.  This will allow QoS to function properly.  Not setting this
3576          * will cause PF rings to break bandwidth settings.
3577          */
3578         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3579         if (rc)
3580                 goto error_free;
3581
3582         rc = update_pf_resource_max(bp);
3583         if (rc)
3584                 goto error_free;
3585
3586         return rc;
3587
3588 error_free:
3589         bnxt_hwrm_func_buf_unrgtr(bp);
3590         return rc;
3591 }
3592
3593 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3594 {
3595         struct hwrm_func_cfg_input req = {0};
3596         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3597         int rc;
3598
3599         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3600
3601         req.fid = rte_cpu_to_le_16(0xffff);
3602         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3603         req.evb_mode = bp->pf->evb_mode;
3604
3605         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3606         HWRM_CHECK_RESULT();
3607         HWRM_UNLOCK();
3608
3609         return rc;
3610 }
3611
3612 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3613                                 uint8_t tunnel_type)
3614 {
3615         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3616         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3617         int rc = 0;
3618
3619         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3620         req.tunnel_type = tunnel_type;
3621         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3622         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3623         HWRM_CHECK_RESULT();
3624
3625         switch (tunnel_type) {
3626         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3627                 bp->vxlan_fw_dst_port_id =
3628                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3629                 bp->vxlan_port = port;
3630                 break;
3631         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3632                 bp->geneve_fw_dst_port_id =
3633                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3634                 bp->geneve_port = port;
3635                 break;
3636         default:
3637                 break;
3638         }
3639
3640         HWRM_UNLOCK();
3641
3642         return rc;
3643 }
3644
3645 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3646                                 uint8_t tunnel_type)
3647 {
3648         struct hwrm_tunnel_dst_port_free_input req = {0};
3649         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3650         int rc = 0;
3651
3652         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3653
3654         req.tunnel_type = tunnel_type;
3655         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3656         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3657
3658         HWRM_CHECK_RESULT();
3659         HWRM_UNLOCK();
3660
3661         return rc;
3662 }
3663
3664 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3665                                         uint32_t flags)
3666 {
3667         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3668         struct hwrm_func_cfg_input req = {0};
3669         int rc;
3670
3671         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3672
3673         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3674         req.flags = rte_cpu_to_le_32(flags);
3675         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3676
3677         HWRM_CHECK_RESULT();
3678         HWRM_UNLOCK();
3679
3680         return rc;
3681 }
3682
3683 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3684 {
3685         uint32_t *flag = flagp;
3686
3687         vnic->flags = *flag;
3688 }
3689
3690 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3691 {
3692         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3693 }
3694
3695 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3696 {
3697         int rc = 0;
3698         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3699         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3700
3701         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3702
3703         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3704         req.req_buf_page_size = rte_cpu_to_le_16(
3705                          page_getenum(bp->pf->active_vfs * HWRM_MAX_REQ_LEN));
3706         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3707         req.req_buf_page_addr0 =
3708                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3709         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3710                 PMD_DRV_LOG(ERR,
3711                         "unable to map buffer address to physical memory\n");
3712                 return -ENOMEM;
3713         }
3714
3715         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3716
3717         HWRM_CHECK_RESULT();
3718         HWRM_UNLOCK();
3719
3720         return rc;
3721 }
3722
3723 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3724 {
3725         int rc = 0;
3726         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3727         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3728
3729         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3730                 return 0;
3731
3732         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3733
3734         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3735
3736         HWRM_CHECK_RESULT();
3737         HWRM_UNLOCK();
3738
3739         return rc;
3740 }
3741
3742 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3743 {
3744         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3745         struct hwrm_func_cfg_input req = {0};
3746         int rc;
3747
3748         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3749
3750         req.fid = rte_cpu_to_le_16(0xffff);
3751         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3752         req.enables = rte_cpu_to_le_32(
3753                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3754         req.async_event_cr = rte_cpu_to_le_16(
3755                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3756         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3757
3758         HWRM_CHECK_RESULT();
3759         HWRM_UNLOCK();
3760
3761         return rc;
3762 }
3763
3764 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3765 {
3766         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3767         struct hwrm_func_vf_cfg_input req = {0};
3768         int rc;
3769
3770         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3771
3772         req.enables = rte_cpu_to_le_32(
3773                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3774         req.async_event_cr = rte_cpu_to_le_16(
3775                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3776         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3777
3778         HWRM_CHECK_RESULT();
3779         HWRM_UNLOCK();
3780
3781         return rc;
3782 }
3783
3784 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3785 {
3786         struct hwrm_func_cfg_input req = {0};
3787         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3788         uint16_t dflt_vlan, fid;
3789         uint32_t func_cfg_flags;
3790         int rc = 0;
3791
3792         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3793
3794         if (is_vf) {
3795                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
3796                 fid = bp->pf->vf_info[vf].fid;
3797                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
3798         } else {
3799                 fid = rte_cpu_to_le_16(0xffff);
3800                 func_cfg_flags = bp->pf->func_cfg_flags;
3801                 dflt_vlan = bp->vlan;
3802         }
3803
3804         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3805         req.fid = rte_cpu_to_le_16(fid);
3806         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3807         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3808
3809         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3810
3811         HWRM_CHECK_RESULT();
3812         HWRM_UNLOCK();
3813
3814         return rc;
3815 }
3816
3817 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3818                         uint16_t max_bw, uint16_t enables)
3819 {
3820         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3821         struct hwrm_func_cfg_input req = {0};
3822         int rc;
3823
3824         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3825
3826         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3827         req.enables |= rte_cpu_to_le_32(enables);
3828         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3829         req.max_bw = rte_cpu_to_le_32(max_bw);
3830         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3831
3832         HWRM_CHECK_RESULT();
3833         HWRM_UNLOCK();
3834
3835         return rc;
3836 }
3837
3838 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3839 {
3840         struct hwrm_func_cfg_input req = {0};
3841         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3842         int rc = 0;
3843
3844         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3845
3846         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3847         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3848         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3849         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
3850
3851         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3852
3853         HWRM_CHECK_RESULT();
3854         HWRM_UNLOCK();
3855
3856         return rc;
3857 }
3858
3859 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3860 {
3861         int rc;
3862
3863         if (BNXT_PF(bp))
3864                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3865         else
3866                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3867
3868         return rc;
3869 }
3870
3871 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3872                               void *encaped, size_t ec_size)
3873 {
3874         int rc = 0;
3875         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3876         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3877
3878         if (ec_size > sizeof(req.encap_request))
3879                 return -1;
3880
3881         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3882
3883         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3884         memcpy(req.encap_request, encaped, ec_size);
3885
3886         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3887
3888         HWRM_CHECK_RESULT();
3889         HWRM_UNLOCK();
3890
3891         return rc;
3892 }
3893
3894 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3895                                        struct rte_ether_addr *mac)
3896 {
3897         struct hwrm_func_qcfg_input req = {0};
3898         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3899         int rc;
3900
3901         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3902
3903         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3904         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3905
3906         HWRM_CHECK_RESULT();
3907
3908         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3909
3910         HWRM_UNLOCK();
3911
3912         return rc;
3913 }
3914
3915 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3916                             void *encaped, size_t ec_size)
3917 {
3918         int rc = 0;
3919         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3920         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3921
3922         if (ec_size > sizeof(req.encap_request))
3923                 return -1;
3924
3925         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3926
3927         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3928         memcpy(req.encap_request, encaped, ec_size);
3929
3930         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3931
3932         HWRM_CHECK_RESULT();
3933         HWRM_UNLOCK();
3934
3935         return rc;
3936 }
3937
3938 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3939                          struct rte_eth_stats *stats, uint8_t rx)
3940 {
3941         int rc = 0;
3942         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3943         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3944
3945         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3946
3947         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3948
3949         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3950
3951         HWRM_CHECK_RESULT();
3952
3953         if (rx) {
3954                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3955                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3956                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3957                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3958                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3959                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3960                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3961                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3962         } else {
3963                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3964                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3965                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3966                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3967                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3968                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3969         }
3970
3971         HWRM_UNLOCK();
3972
3973         return rc;
3974 }
3975
3976 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3977 {
3978         struct hwrm_port_qstats_input req = {0};
3979         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3980         struct bnxt_pf_info *pf = bp->pf;
3981         int rc;
3982
3983         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
3984
3985         req.port_id = rte_cpu_to_le_16(pf->port_id);
3986         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3987         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3988         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3989
3990         HWRM_CHECK_RESULT();
3991         HWRM_UNLOCK();
3992
3993         return rc;
3994 }
3995
3996 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3997 {
3998         struct hwrm_port_clr_stats_input req = {0};
3999         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4000         struct bnxt_pf_info *pf = bp->pf;
4001         int rc;
4002
4003         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4004         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4005             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4006                 return 0;
4007
4008         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4009
4010         req.port_id = rte_cpu_to_le_16(pf->port_id);
4011         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4012
4013         HWRM_CHECK_RESULT();
4014         HWRM_UNLOCK();
4015
4016         return rc;
4017 }
4018
4019 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4020 {
4021         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4022         struct hwrm_port_led_qcaps_input req = {0};
4023         int rc;
4024
4025         if (BNXT_VF(bp))
4026                 return 0;
4027
4028         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4029         req.port_id = bp->pf->port_id;
4030         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4031
4032         HWRM_CHECK_RESULT();
4033
4034         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4035                 unsigned int i;
4036
4037                 bp->leds->num_leds = resp->num_leds;
4038                 memcpy(bp->leds, &resp->led0_id,
4039                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4040                 for (i = 0; i < bp->leds->num_leds; i++) {
4041                         struct bnxt_led_info *led = &bp->leds[i];
4042
4043                         uint16_t caps = led->led_state_caps;
4044
4045                         if (!led->led_group_id ||
4046                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4047                                 bp->leds->num_leds = 0;
4048                                 break;
4049                         }
4050                 }
4051         }
4052
4053         HWRM_UNLOCK();
4054
4055         return rc;
4056 }
4057
4058 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4059 {
4060         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4061         struct hwrm_port_led_cfg_input req = {0};
4062         struct bnxt_led_cfg *led_cfg;
4063         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4064         uint16_t duration = 0;
4065         int rc, i;
4066
4067         if (!bp->leds->num_leds || BNXT_VF(bp))
4068                 return -EOPNOTSUPP;
4069
4070         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4071
4072         if (led_on) {
4073                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4074                 duration = rte_cpu_to_le_16(500);
4075         }
4076         req.port_id = bp->pf->port_id;
4077         req.num_leds = bp->leds->num_leds;
4078         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4079         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4080                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4081                 led_cfg->led_id = bp->leds[i].led_id;
4082                 led_cfg->led_state = led_state;
4083                 led_cfg->led_blink_on = duration;
4084                 led_cfg->led_blink_off = duration;
4085                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4086         }
4087
4088         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4089
4090         HWRM_CHECK_RESULT();
4091         HWRM_UNLOCK();
4092
4093         return rc;
4094 }
4095
4096 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4097                                uint32_t *length)
4098 {
4099         int rc;
4100         struct hwrm_nvm_get_dir_info_input req = {0};
4101         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4102
4103         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4104
4105         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4106
4107         HWRM_CHECK_RESULT();
4108
4109         *entries = rte_le_to_cpu_32(resp->entries);
4110         *length = rte_le_to_cpu_32(resp->entry_length);
4111
4112         HWRM_UNLOCK();
4113         return rc;
4114 }
4115
4116 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4117 {
4118         int rc;
4119         uint32_t dir_entries;
4120         uint32_t entry_length;
4121         uint8_t *buf;
4122         size_t buflen;
4123         rte_iova_t dma_handle;
4124         struct hwrm_nvm_get_dir_entries_input req = {0};
4125         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4126
4127         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4128         if (rc != 0)
4129                 return rc;
4130
4131         *data++ = dir_entries;
4132         *data++ = entry_length;
4133         len -= 2;
4134         memset(data, 0xff, len);
4135
4136         buflen = dir_entries * entry_length;
4137         buf = rte_malloc("nvm_dir", buflen, 0);
4138         if (buf == NULL)
4139                 return -ENOMEM;
4140         dma_handle = rte_malloc_virt2iova(buf);
4141         if (dma_handle == RTE_BAD_IOVA) {
4142                 PMD_DRV_LOG(ERR,
4143                         "unable to map response address to physical memory\n");
4144                 return -ENOMEM;
4145         }
4146         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4147         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4148         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4149
4150         if (rc == 0)
4151                 memcpy(data, buf, len > buflen ? buflen : len);
4152
4153         rte_free(buf);
4154         HWRM_CHECK_RESULT();
4155         HWRM_UNLOCK();
4156
4157         return rc;
4158 }
4159
4160 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4161                              uint32_t offset, uint32_t length,
4162                              uint8_t *data)
4163 {
4164         int rc;
4165         uint8_t *buf;
4166         rte_iova_t dma_handle;
4167         struct hwrm_nvm_read_input req = {0};
4168         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4169
4170         buf = rte_malloc("nvm_item", length, 0);
4171         if (!buf)
4172                 return -ENOMEM;
4173
4174         dma_handle = rte_malloc_virt2iova(buf);
4175         if (dma_handle == RTE_BAD_IOVA) {
4176                 PMD_DRV_LOG(ERR,
4177                         "unable to map response address to physical memory\n");
4178                 return -ENOMEM;
4179         }
4180         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4181         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4182         req.dir_idx = rte_cpu_to_le_16(index);
4183         req.offset = rte_cpu_to_le_32(offset);
4184         req.len = rte_cpu_to_le_32(length);
4185         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4186         if (rc == 0)
4187                 memcpy(data, buf, length);
4188
4189         rte_free(buf);
4190         HWRM_CHECK_RESULT();
4191         HWRM_UNLOCK();
4192
4193         return rc;
4194 }
4195
4196 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4197 {
4198         int rc;
4199         struct hwrm_nvm_erase_dir_entry_input req = {0};
4200         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4201
4202         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4203         req.dir_idx = rte_cpu_to_le_16(index);
4204         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4205         HWRM_CHECK_RESULT();
4206         HWRM_UNLOCK();
4207
4208         return rc;
4209 }
4210
4211
4212 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4213                           uint16_t dir_ordinal, uint16_t dir_ext,
4214                           uint16_t dir_attr, const uint8_t *data,
4215                           size_t data_len)
4216 {
4217         int rc;
4218         struct hwrm_nvm_write_input req = {0};
4219         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4220         rte_iova_t dma_handle;
4221         uint8_t *buf;
4222
4223         buf = rte_malloc("nvm_write", data_len, 0);
4224         if (!buf)
4225                 return -ENOMEM;
4226
4227         dma_handle = rte_malloc_virt2iova(buf);
4228         if (dma_handle == RTE_BAD_IOVA) {
4229                 PMD_DRV_LOG(ERR,
4230                         "unable to map response address to physical memory\n");
4231                 return -ENOMEM;
4232         }
4233         memcpy(buf, data, data_len);
4234
4235         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4236
4237         req.dir_type = rte_cpu_to_le_16(dir_type);
4238         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4239         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4240         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4241         req.dir_data_length = rte_cpu_to_le_32(data_len);
4242         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4243
4244         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4245
4246         rte_free(buf);
4247         HWRM_CHECK_RESULT();
4248         HWRM_UNLOCK();
4249
4250         return rc;
4251 }
4252
4253 static void
4254 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4255 {
4256         uint32_t *count = cbdata;
4257
4258         *count = *count + 1;
4259 }
4260
4261 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4262                                      struct bnxt_vnic_info *vnic __rte_unused)
4263 {
4264         return 0;
4265 }
4266
4267 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4268 {
4269         uint32_t count = 0;
4270
4271         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4272             &count, bnxt_vnic_count_hwrm_stub);
4273
4274         return count;
4275 }
4276
4277 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4278                                         uint16_t *vnic_ids)
4279 {
4280         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4281         struct hwrm_func_vf_vnic_ids_query_output *resp =
4282                                                 bp->hwrm_cmd_resp_addr;
4283         int rc;
4284
4285         /* First query all VNIC ids */
4286         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4287
4288         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4289         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4290         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4291
4292         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4293                 HWRM_UNLOCK();
4294                 PMD_DRV_LOG(ERR,
4295                 "unable to map VNIC ID table address to physical memory\n");
4296                 return -ENOMEM;
4297         }
4298         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4299         HWRM_CHECK_RESULT();
4300         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4301
4302         HWRM_UNLOCK();
4303
4304         return rc;
4305 }
4306
4307 /*
4308  * This function queries the VNIC IDs  for a specified VF. It then calls
4309  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4310  * Then it calls the hwrm_cb function to program this new vnic configuration.
4311  */
4312 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4313         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4314         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4315 {
4316         struct bnxt_vnic_info vnic;
4317         int rc = 0;
4318         int i, num_vnic_ids;
4319         uint16_t *vnic_ids;
4320         size_t vnic_id_sz;
4321         size_t sz;
4322
4323         /* First query all VNIC ids */
4324         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4325         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4326                         RTE_CACHE_LINE_SIZE);
4327         if (vnic_ids == NULL)
4328                 return -ENOMEM;
4329
4330         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4331                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4332
4333         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4334
4335         if (num_vnic_ids < 0)
4336                 return num_vnic_ids;
4337
4338         /* Retrieve VNIC, update bd_stall then update */
4339
4340         for (i = 0; i < num_vnic_ids; i++) {
4341                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4342                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4343                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4344                 if (rc)
4345                         break;
4346                 if (vnic.mru <= 4)      /* Indicates unallocated */
4347                         continue;
4348
4349                 vnic_cb(&vnic, cbdata);
4350
4351                 rc = hwrm_cb(bp, &vnic);
4352                 if (rc)
4353                         break;
4354         }
4355
4356         rte_free(vnic_ids);
4357
4358         return rc;
4359 }
4360
4361 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4362                                               bool on)
4363 {
4364         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4365         struct hwrm_func_cfg_input req = {0};
4366         int rc;
4367
4368         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4369
4370         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4371         req.enables |= rte_cpu_to_le_32(
4372                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4373         req.vlan_antispoof_mode = on ?
4374                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4375                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4376         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4377
4378         HWRM_CHECK_RESULT();
4379         HWRM_UNLOCK();
4380
4381         return rc;
4382 }
4383
4384 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4385 {
4386         struct bnxt_vnic_info vnic;
4387         uint16_t *vnic_ids;
4388         size_t vnic_id_sz;
4389         int num_vnic_ids, i;
4390         size_t sz;
4391         int rc;
4392
4393         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4394         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4395                         RTE_CACHE_LINE_SIZE);
4396         if (vnic_ids == NULL)
4397                 return -ENOMEM;
4398
4399         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4400                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4401
4402         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4403         if (rc <= 0)
4404                 goto exit;
4405         num_vnic_ids = rc;
4406
4407         /*
4408          * Loop through to find the default VNIC ID.
4409          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4410          * by sending the hwrm_func_qcfg command to the firmware.
4411          */
4412         for (i = 0; i < num_vnic_ids; i++) {
4413                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4414                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4415                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4416                                         bp->pf->first_vf_id + vf);
4417                 if (rc)
4418                         goto exit;
4419                 if (vnic.func_default) {
4420                         rte_free(vnic_ids);
4421                         return vnic.fw_vnic_id;
4422                 }
4423         }
4424         /* Could not find a default VNIC. */
4425         PMD_DRV_LOG(ERR, "No default VNIC\n");
4426 exit:
4427         rte_free(vnic_ids);
4428         return rc;
4429 }
4430
4431 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4432                          uint16_t dst_id,
4433                          struct bnxt_filter_info *filter)
4434 {
4435         int rc = 0;
4436         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4437         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4438         uint32_t enables = 0;
4439
4440         if (filter->fw_em_filter_id != UINT64_MAX)
4441                 bnxt_hwrm_clear_em_filter(bp, filter);
4442
4443         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4444
4445         req.flags = rte_cpu_to_le_32(filter->flags);
4446
4447         enables = filter->enables |
4448               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4449         req.dst_id = rte_cpu_to_le_16(dst_id);
4450
4451         if (filter->ip_addr_type) {
4452                 req.ip_addr_type = filter->ip_addr_type;
4453                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4454         }
4455         if (enables &
4456             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4457                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4458         if (enables &
4459             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4460                 memcpy(req.src_macaddr, filter->src_macaddr,
4461                        RTE_ETHER_ADDR_LEN);
4462         if (enables &
4463             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4464                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4465                        RTE_ETHER_ADDR_LEN);
4466         if (enables &
4467             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4468                 req.ovlan_vid = filter->l2_ovlan;
4469         if (enables &
4470             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4471                 req.ivlan_vid = filter->l2_ivlan;
4472         if (enables &
4473             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4474                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4475         if (enables &
4476             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4477                 req.ip_protocol = filter->ip_protocol;
4478         if (enables &
4479             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4480                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4481         if (enables &
4482             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4483                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4484         if (enables &
4485             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4486                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4487         if (enables &
4488             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4489                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4490         if (enables &
4491             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4492                 req.mirror_vnic_id = filter->mirror_vnic_id;
4493
4494         req.enables = rte_cpu_to_le_32(enables);
4495
4496         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4497
4498         HWRM_CHECK_RESULT();
4499
4500         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4501         HWRM_UNLOCK();
4502
4503         return rc;
4504 }
4505
4506 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4507 {
4508         int rc = 0;
4509         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4510         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4511
4512         if (filter->fw_em_filter_id == UINT64_MAX)
4513                 return 0;
4514
4515         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4516
4517         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4518
4519         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4520
4521         HWRM_CHECK_RESULT();
4522         HWRM_UNLOCK();
4523
4524         filter->fw_em_filter_id = UINT64_MAX;
4525         filter->fw_l2_filter_id = UINT64_MAX;
4526
4527         return 0;
4528 }
4529
4530 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4531                          uint16_t dst_id,
4532                          struct bnxt_filter_info *filter)
4533 {
4534         int rc = 0;
4535         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4536         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4537                                                 bp->hwrm_cmd_resp_addr;
4538         uint32_t enables = 0;
4539
4540         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4541                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4542
4543         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4544
4545         req.flags = rte_cpu_to_le_32(filter->flags);
4546
4547         enables = filter->enables |
4548               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4549         req.dst_id = rte_cpu_to_le_16(dst_id);
4550
4551         if (filter->ip_addr_type) {
4552                 req.ip_addr_type = filter->ip_addr_type;
4553                 enables |=
4554                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4555         }
4556         if (enables &
4557             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4558                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4559         if (enables &
4560             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4561                 memcpy(req.src_macaddr, filter->src_macaddr,
4562                        RTE_ETHER_ADDR_LEN);
4563         if (enables &
4564             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4565                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4566         if (enables &
4567             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4568                 req.ip_protocol = filter->ip_protocol;
4569         if (enables &
4570             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4571                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4572         if (enables &
4573             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4574                 req.src_ipaddr_mask[0] =
4575                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4576         if (enables &
4577             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4578                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4579         if (enables &
4580             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4581                 req.dst_ipaddr_mask[0] =
4582                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4583         if (enables &
4584             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4585                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4586         if (enables &
4587             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4588                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4589         if (enables &
4590             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4591                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4592         if (enables &
4593             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4594                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4595         if (enables &
4596             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4597                 req.mirror_vnic_id = filter->mirror_vnic_id;
4598
4599         req.enables = rte_cpu_to_le_32(enables);
4600
4601         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4602
4603         HWRM_CHECK_RESULT();
4604
4605         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4606         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4607         HWRM_UNLOCK();
4608
4609         return rc;
4610 }
4611
4612 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4613                                 struct bnxt_filter_info *filter)
4614 {
4615         int rc = 0;
4616         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4617         struct hwrm_cfa_ntuple_filter_free_output *resp =
4618                                                 bp->hwrm_cmd_resp_addr;
4619
4620         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4621                 return 0;
4622
4623         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4624
4625         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4626
4627         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4628
4629         HWRM_CHECK_RESULT();
4630         HWRM_UNLOCK();
4631
4632         filter->fw_ntuple_filter_id = UINT64_MAX;
4633
4634         return 0;
4635 }
4636
4637 static int
4638 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4639 {
4640         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4641         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4642         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4643         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4644         uint16_t *ring_tbl = vnic->rss_table;
4645         int nr_ctxs = vnic->num_lb_ctxts;
4646         int max_rings = bp->rx_nr_rings;
4647         int i, j, k, cnt;
4648         int rc = 0;
4649
4650         for (i = 0, k = 0; i < nr_ctxs; i++) {
4651                 struct bnxt_rx_ring_info *rxr;
4652                 struct bnxt_cp_ring_info *cpr;
4653
4654                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4655
4656                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4657                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4658                 req.hash_mode_flags = vnic->hash_mode;
4659
4660                 req.ring_grp_tbl_addr =
4661                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4662                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4663                                      2 * sizeof(*ring_tbl));
4664                 req.hash_key_tbl_addr =
4665                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4666
4667                 req.ring_table_pair_index = i;
4668                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4669
4670                 for (j = 0; j < 64; j++) {
4671                         uint16_t ring_id;
4672
4673                         /* Find next active ring. */
4674                         for (cnt = 0; cnt < max_rings; cnt++) {
4675                                 if (rx_queue_state[k] !=
4676                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4677                                         break;
4678                                 if (++k == max_rings)
4679                                         k = 0;
4680                         }
4681
4682                         /* Return if no rings are active. */
4683                         if (cnt == max_rings) {
4684                                 HWRM_UNLOCK();
4685                                 return 0;
4686                         }
4687
4688                         /* Add rx/cp ring pair to RSS table. */
4689                         rxr = rxqs[k]->rx_ring;
4690                         cpr = rxqs[k]->cp_ring;
4691
4692                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4693                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4694                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4695                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4696
4697                         if (++k == max_rings)
4698                                 k = 0;
4699                 }
4700                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4701                                             BNXT_USE_CHIMP_MB);
4702
4703                 HWRM_CHECK_RESULT();
4704                 HWRM_UNLOCK();
4705         }
4706
4707         return rc;
4708 }
4709
4710 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4711 {
4712         unsigned int rss_idx, fw_idx, i;
4713
4714         if (!(vnic->rss_table && vnic->hash_type))
4715                 return 0;
4716
4717         if (BNXT_CHIP_THOR(bp))
4718                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4719
4720         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4721                 return 0;
4722
4723         if (vnic->rss_table && vnic->hash_type) {
4724                 /*
4725                  * Fill the RSS hash & redirection table with
4726                  * ring group ids for all VNICs
4727                  */
4728                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4729                         rss_idx++, fw_idx++) {
4730                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4731                                 fw_idx %= bp->rx_cp_nr_rings;
4732                                 if (vnic->fw_grp_ids[fw_idx] !=
4733                                     INVALID_HW_RING_ID)
4734                                         break;
4735                                 fw_idx++;
4736                         }
4737                         if (i == bp->rx_cp_nr_rings)
4738                                 return 0;
4739                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4740                 }
4741                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4742         }
4743
4744         return 0;
4745 }
4746
4747 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4748         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4749 {
4750         uint16_t flags;
4751
4752         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4753
4754         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4755         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4756
4757         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4758         req->num_cmpl_dma_aggr_during_int =
4759                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4760
4761         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4762
4763         /* min timer set to 1/2 of interrupt timer */
4764         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4765
4766         /* buf timer set to 1/4 of interrupt timer */
4767         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4768
4769         req->cmpl_aggr_dma_tmr_during_int =
4770                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4771
4772         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4773                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4774         req->flags = rte_cpu_to_le_16(flags);
4775 }
4776
4777 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4778                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4779 {
4780         struct hwrm_ring_aggint_qcaps_input req = {0};
4781         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4782         uint32_t enables;
4783         uint16_t flags;
4784         int rc;
4785
4786         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4787         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4788         HWRM_CHECK_RESULT();
4789
4790         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4791         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4792
4793         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4794                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4795         agg_req->flags = rte_cpu_to_le_16(flags);
4796         enables =
4797          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4798          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4799         agg_req->enables = rte_cpu_to_le_32(enables);
4800
4801         HWRM_UNLOCK();
4802         return rc;
4803 }
4804
4805 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4806                         struct bnxt_coal *coal, uint16_t ring_id)
4807 {
4808         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4809         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4810                                                 bp->hwrm_cmd_resp_addr;
4811         int rc;
4812
4813         /* Set ring coalesce parameters only for 100G NICs */
4814         if (BNXT_CHIP_THOR(bp)) {
4815                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4816                         return -1;
4817         } else if (bnxt_stratus_device(bp)) {
4818                 bnxt_hwrm_set_coal_params(coal, &req);
4819         } else {
4820                 return 0;
4821         }
4822
4823         HWRM_PREP(&req,
4824                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4825                   BNXT_USE_CHIMP_MB);
4826         req.ring_id = rte_cpu_to_le_16(ring_id);
4827         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4828         HWRM_CHECK_RESULT();
4829         HWRM_UNLOCK();
4830         return 0;
4831 }
4832
4833 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4834 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4835 {
4836         struct hwrm_func_backing_store_qcaps_input req = {0};
4837         struct hwrm_func_backing_store_qcaps_output *resp =
4838                 bp->hwrm_cmd_resp_addr;
4839         struct bnxt_ctx_pg_info *ctx_pg;
4840         struct bnxt_ctx_mem_info *ctx;
4841         int total_alloc_len;
4842         int rc, i, tqm_rings;
4843
4844         if (!BNXT_CHIP_THOR(bp) ||
4845             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4846             BNXT_VF(bp) ||
4847             bp->ctx)
4848                 return 0;
4849
4850         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4851         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4852         HWRM_CHECK_RESULT_SILENT();
4853
4854         total_alloc_len = sizeof(*ctx);
4855         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4856                           RTE_CACHE_LINE_SIZE);
4857         if (!ctx) {
4858                 rc = -ENOMEM;
4859                 goto ctx_err;
4860         }
4861
4862         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4863         ctx->qp_min_qp1_entries =
4864                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4865         ctx->qp_max_l2_entries =
4866                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4867         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4868         ctx->srq_max_l2_entries =
4869                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4870         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4871         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4872         ctx->cq_max_l2_entries =
4873                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4874         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4875         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4876         ctx->vnic_max_vnic_entries =
4877                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4878         ctx->vnic_max_ring_table_entries =
4879                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4880         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4881         ctx->stat_max_entries =
4882                 rte_le_to_cpu_32(resp->stat_max_entries);
4883         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4884         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4885         ctx->tqm_min_entries_per_ring =
4886                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4887         ctx->tqm_max_entries_per_ring =
4888                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4889         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4890         if (!ctx->tqm_entries_multiple)
4891                 ctx->tqm_entries_multiple = 1;
4892         ctx->mrav_max_entries =
4893                 rte_le_to_cpu_32(resp->mrav_max_entries);
4894         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4895         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4896         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4897         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
4898
4899         if (!ctx->tqm_fp_rings_count)
4900                 ctx->tqm_fp_rings_count = bp->max_q;
4901
4902         tqm_rings = ctx->tqm_fp_rings_count + 1;
4903
4904         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4905                             sizeof(*ctx_pg) * tqm_rings,
4906                             RTE_CACHE_LINE_SIZE);
4907         if (!ctx_pg) {
4908                 rc = -ENOMEM;
4909                 goto ctx_err;
4910         }
4911         for (i = 0; i < tqm_rings; i++, ctx_pg++)
4912                 ctx->tqm_mem[i] = ctx_pg;
4913
4914         bp->ctx = ctx;
4915 ctx_err:
4916         HWRM_UNLOCK();
4917         return rc;
4918 }
4919
4920 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4921 {
4922         struct hwrm_func_backing_store_cfg_input req = {0};
4923         struct hwrm_func_backing_store_cfg_output *resp =
4924                 bp->hwrm_cmd_resp_addr;
4925         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4926         struct bnxt_ctx_pg_info *ctx_pg;
4927         uint32_t *num_entries;
4928         uint64_t *pg_dir;
4929         uint8_t *pg_attr;
4930         uint32_t ena;
4931         int i, rc;
4932
4933         if (!ctx)
4934                 return 0;
4935
4936         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4937         req.enables = rte_cpu_to_le_32(enables);
4938
4939         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4940                 ctx_pg = &ctx->qp_mem;
4941                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4942                 req.qp_num_qp1_entries =
4943                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4944                 req.qp_num_l2_entries =
4945                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4946                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4947                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4948                                       &req.qpc_pg_size_qpc_lvl,
4949                                       &req.qpc_page_dir);
4950         }
4951
4952         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4953                 ctx_pg = &ctx->srq_mem;
4954                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4955                 req.srq_num_l2_entries =
4956                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4957                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4958                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4959                                       &req.srq_pg_size_srq_lvl,
4960                                       &req.srq_page_dir);
4961         }
4962
4963         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4964                 ctx_pg = &ctx->cq_mem;
4965                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4966                 req.cq_num_l2_entries =
4967                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4968                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4969                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4970                                       &req.cq_pg_size_cq_lvl,
4971                                       &req.cq_page_dir);
4972         }
4973
4974         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4975                 ctx_pg = &ctx->vnic_mem;
4976                 req.vnic_num_vnic_entries =
4977                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4978                 req.vnic_num_ring_table_entries =
4979                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4980                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4981                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4982                                       &req.vnic_pg_size_vnic_lvl,
4983                                       &req.vnic_page_dir);
4984         }
4985
4986         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4987                 ctx_pg = &ctx->stat_mem;
4988                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4989                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4990                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4991                                       &req.stat_pg_size_stat_lvl,
4992                                       &req.stat_page_dir);
4993         }
4994
4995         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4996         num_entries = &req.tqm_sp_num_entries;
4997         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4998         pg_dir = &req.tqm_sp_page_dir;
4999         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5000         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5001                 if (!(enables & ena))
5002                         continue;
5003
5004                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5005
5006                 ctx_pg = ctx->tqm_mem[i];
5007                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5008                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5009         }
5010
5011         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5012         HWRM_CHECK_RESULT();
5013         HWRM_UNLOCK();
5014
5015         return rc;
5016 }
5017
5018 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5019 {
5020         struct hwrm_port_qstats_ext_input req = {0};
5021         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5022         struct bnxt_pf_info *pf = bp->pf;
5023         int rc;
5024
5025         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5026               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5027                 return 0;
5028
5029         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5030
5031         req.port_id = rte_cpu_to_le_16(pf->port_id);
5032         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5033                 req.tx_stat_host_addr =
5034                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5035                 req.tx_stat_size =
5036                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5037         }
5038         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5039                 req.rx_stat_host_addr =
5040                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5041                 req.rx_stat_size =
5042                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5043         }
5044         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5045
5046         if (rc) {
5047                 bp->fw_rx_port_stats_ext_size = 0;
5048                 bp->fw_tx_port_stats_ext_size = 0;
5049         } else {
5050                 bp->fw_rx_port_stats_ext_size =
5051                         rte_le_to_cpu_16(resp->rx_stat_size);
5052                 bp->fw_tx_port_stats_ext_size =
5053                         rte_le_to_cpu_16(resp->tx_stat_size);
5054         }
5055
5056         HWRM_CHECK_RESULT();
5057         HWRM_UNLOCK();
5058
5059         return rc;
5060 }
5061
5062 int
5063 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5064 {
5065         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5066         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5067                 bp->hwrm_cmd_resp_addr;
5068         int rc = 0;
5069
5070         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5071         req.tunnel_type = type;
5072         req.dest_fid = bp->fw_fid;
5073         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5074         HWRM_CHECK_RESULT();
5075
5076         HWRM_UNLOCK();
5077
5078         return rc;
5079 }
5080
5081 int
5082 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5083 {
5084         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5085         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5086                 bp->hwrm_cmd_resp_addr;
5087         int rc = 0;
5088
5089         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5090         req.tunnel_type = type;
5091         req.dest_fid = bp->fw_fid;
5092         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5093         HWRM_CHECK_RESULT();
5094
5095         HWRM_UNLOCK();
5096
5097         return rc;
5098 }
5099
5100 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5101 {
5102         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5103         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5104                 bp->hwrm_cmd_resp_addr;
5105         int rc = 0;
5106
5107         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5108         req.src_fid = bp->fw_fid;
5109         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5110         HWRM_CHECK_RESULT();
5111
5112         if (type)
5113                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5114
5115         HWRM_UNLOCK();
5116
5117         return rc;
5118 }
5119
5120 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5121                                    uint16_t *dst_fid)
5122 {
5123         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5124         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5125                 bp->hwrm_cmd_resp_addr;
5126         int rc = 0;
5127
5128         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5129         req.src_fid = bp->fw_fid;
5130         req.tunnel_type = tun_type;
5131         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5132         HWRM_CHECK_RESULT();
5133
5134         if (dst_fid)
5135                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5136
5137         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5138
5139         HWRM_UNLOCK();
5140
5141         return rc;
5142 }
5143
5144 int bnxt_hwrm_set_mac(struct bnxt *bp)
5145 {
5146         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5147         struct hwrm_func_vf_cfg_input req = {0};
5148         int rc = 0;
5149
5150         if (!BNXT_VF(bp))
5151                 return 0;
5152
5153         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5154
5155         req.enables =
5156                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5157         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5158
5159         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5160
5161         HWRM_CHECK_RESULT();
5162
5163         HWRM_UNLOCK();
5164
5165         return rc;
5166 }
5167
5168 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5169 {
5170         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5171         struct hwrm_func_drv_if_change_input req = {0};
5172         uint32_t flags;
5173         int rc;
5174
5175         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5176                 return 0;
5177
5178         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5179          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5180          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5181          */
5182         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5183                 return 0;
5184
5185         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5186
5187         if (up)
5188                 req.flags =
5189                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5190
5191         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5192
5193         HWRM_CHECK_RESULT();
5194         flags = rte_le_to_cpu_32(resp->flags);
5195         HWRM_UNLOCK();
5196
5197         if (!up)
5198                 return 0;
5199
5200         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5201                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5202                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5203         }
5204
5205         return 0;
5206 }
5207
5208 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5209 {
5210         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5211         struct bnxt_error_recovery_info *info = bp->recovery_info;
5212         struct hwrm_error_recovery_qcfg_input req = {0};
5213         uint32_t flags = 0;
5214         unsigned int i;
5215         int rc;
5216
5217         /* Older FW does not have error recovery support */
5218         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5219                 return 0;
5220
5221         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5222
5223         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5224
5225         HWRM_CHECK_RESULT();
5226
5227         flags = rte_le_to_cpu_32(resp->flags);
5228         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5229                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5230         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5231                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5232
5233         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5234             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5235                 rc = -EINVAL;
5236                 goto err;
5237         }
5238
5239         /* FW returned values are in units of 100msec */
5240         info->driver_polling_freq =
5241                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5242         info->master_func_wait_period =
5243                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5244         info->normal_func_wait_period =
5245                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5246         info->master_func_wait_period_after_reset =
5247                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5248         info->max_bailout_time_after_reset =
5249                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5250         info->status_regs[BNXT_FW_STATUS_REG] =
5251                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5252         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5253                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5254         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5255                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5256         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5257                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5258         info->reg_array_cnt =
5259                 rte_le_to_cpu_32(resp->reg_array_cnt);
5260
5261         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5262                 rc = -EINVAL;
5263                 goto err;
5264         }
5265
5266         for (i = 0; i < info->reg_array_cnt; i++) {
5267                 info->reset_reg[i] =
5268                         rte_le_to_cpu_32(resp->reset_reg[i]);
5269                 info->reset_reg_val[i] =
5270                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5271                 info->delay_after_reset[i] =
5272                         resp->delay_after_reset[i];
5273         }
5274 err:
5275         HWRM_UNLOCK();
5276
5277         /* Map the FW status registers */
5278         if (!rc)
5279                 rc = bnxt_map_fw_health_status_regs(bp);
5280
5281         if (rc) {
5282                 rte_free(bp->recovery_info);
5283                 bp->recovery_info = NULL;
5284         }
5285         return rc;
5286 }
5287
5288 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5289 {
5290         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5291         struct hwrm_fw_reset_input req = {0};
5292         int rc;
5293
5294         if (!BNXT_PF(bp))
5295                 return -EOPNOTSUPP;
5296
5297         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5298
5299         req.embedded_proc_type =
5300                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5301         req.selfrst_status =
5302                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5303         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5304
5305         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5306                                     BNXT_USE_KONG(bp));
5307
5308         HWRM_CHECK_RESULT();
5309         HWRM_UNLOCK();
5310
5311         return rc;
5312 }
5313
5314 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5315 {
5316         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5317         struct hwrm_port_ts_query_input req = {0};
5318         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5319         uint32_t flags = 0;
5320         int rc;
5321
5322         if (!ptp)
5323                 return 0;
5324
5325         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5326
5327         switch (path) {
5328         case BNXT_PTP_FLAGS_PATH_TX:
5329                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5330                 break;
5331         case BNXT_PTP_FLAGS_PATH_RX:
5332                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5333                 break;
5334         case BNXT_PTP_FLAGS_CURRENT_TIME:
5335                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5336                 break;
5337         }
5338
5339         req.flags = rte_cpu_to_le_32(flags);
5340         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5341
5342         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5343
5344         HWRM_CHECK_RESULT();
5345
5346         if (timestamp) {
5347                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5348                 *timestamp |=
5349                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5350         }
5351         HWRM_UNLOCK();
5352
5353         return rc;
5354 }
5355
5356 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5357 {
5358         int rc = 0;
5359
5360         struct hwrm_cfa_counter_qcaps_input req = {0};
5361         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5362
5363         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5364                 PMD_DRV_LOG(DEBUG,
5365                             "Not a PF or trusted VF. Command not supported\n");
5366                 return 0;
5367         }
5368
5369         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5370         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5371         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5372
5373         HWRM_CHECK_RESULT();
5374         if (max_fc)
5375                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5376         HWRM_UNLOCK();
5377
5378         return 0;
5379 }
5380
5381 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5382 {
5383         int rc = 0;
5384         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5385         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5386
5387         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5388                 PMD_DRV_LOG(DEBUG,
5389                             "Not a PF or trusted VF. Command not supported\n");
5390                 return 0;
5391         }
5392
5393         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5394
5395         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5396         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5397         req.page_dir = rte_cpu_to_le_64(dma_addr);
5398
5399         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5400
5401         HWRM_CHECK_RESULT();
5402         if (ctx_id) {
5403                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5404                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5405         }
5406         HWRM_UNLOCK();
5407
5408         return 0;
5409 }
5410
5411 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5412 {
5413         int rc = 0;
5414         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5415         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5416
5417         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5418                 PMD_DRV_LOG(DEBUG,
5419                             "Not a PF or trusted VF. Command not supported\n");
5420                 return 0;
5421         }
5422
5423         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5424
5425         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5426
5427         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5428
5429         HWRM_CHECK_RESULT();
5430         HWRM_UNLOCK();
5431
5432         return rc;
5433 }
5434
5435 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5436                               uint16_t cntr, uint16_t ctx_id,
5437                               uint32_t num_entries, bool enable)
5438 {
5439         struct hwrm_cfa_counter_cfg_input req = {0};
5440         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5441         uint16_t flags = 0;
5442         int rc;
5443
5444         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5445                 PMD_DRV_LOG(DEBUG,
5446                             "Not a PF or trusted VF. Command not supported\n");
5447                 return 0;
5448         }
5449
5450         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5451
5452         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5453         req.counter_type = rte_cpu_to_le_16(cntr);
5454         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5455                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5456         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5457         if (dir == BNXT_DIR_RX)
5458                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5459         else if (dir == BNXT_DIR_TX)
5460                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5461         req.flags = rte_cpu_to_le_16(flags);
5462         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5463         req.num_entries = rte_cpu_to_le_32(num_entries);
5464
5465         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5466         HWRM_CHECK_RESULT();
5467         HWRM_UNLOCK();
5468
5469         return 0;
5470 }
5471
5472 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5473                                  enum bnxt_flow_dir dir,
5474                                  uint16_t cntr,
5475                                  uint16_t num_entries)
5476 {
5477         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5478         struct hwrm_cfa_counter_qstats_input req = {0};
5479         uint16_t flow_ctx_id = 0;
5480         uint16_t flags = 0;
5481         int rc = 0;
5482
5483         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5484                 PMD_DRV_LOG(DEBUG,
5485                             "Not a PF or trusted VF. Command not supported\n");
5486                 return 0;
5487         }
5488
5489         if (dir == BNXT_DIR_RX) {
5490                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5491                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5492         } else if (dir == BNXT_DIR_TX) {
5493                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5494                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5495         }
5496
5497         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5498         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5499         req.counter_type = rte_cpu_to_le_16(cntr);
5500         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5501         req.num_entries = rte_cpu_to_le_16(num_entries);
5502         req.flags = rte_cpu_to_le_16(flags);
5503         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5504
5505         HWRM_CHECK_RESULT();
5506         HWRM_UNLOCK();
5507
5508         return 0;
5509 }
5510
5511 int bnxt_hwrm_cfa_vfr_alloc(struct bnxt *bp, uint16_t vf_idx)
5512 {
5513         struct hwrm_cfa_vfr_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5514         struct hwrm_cfa_vfr_alloc_input req = {0};
5515         int rc;
5516
5517         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5518                 PMD_DRV_LOG(DEBUG,
5519                             "Not a PF or trusted VF. Command not supported\n");
5520                 return 0;
5521         }
5522
5523         HWRM_PREP(&req, HWRM_CFA_VFR_ALLOC, BNXT_USE_CHIMP_MB);
5524         req.vf_id = rte_cpu_to_le_16(vf_idx);
5525         snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5526                  bp->eth_dev->data->name, vf_idx);
5527
5528         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5529         HWRM_CHECK_RESULT();
5530
5531         HWRM_UNLOCK();
5532         PMD_DRV_LOG(DEBUG, "VFR %d allocated\n", vf_idx);
5533         return rc;
5534 }
5535
5536 int bnxt_hwrm_cfa_vfr_free(struct bnxt *bp, uint16_t vf_idx)
5537 {
5538         struct hwrm_cfa_vfr_free_output *resp = bp->hwrm_cmd_resp_addr;
5539         struct hwrm_cfa_vfr_free_input req = {0};
5540         int rc;
5541
5542         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5543                 PMD_DRV_LOG(DEBUG,
5544                             "Not a PF or trusted VF. Command not supported\n");
5545                 return 0;
5546         }
5547
5548         HWRM_PREP(&req, HWRM_CFA_VFR_FREE, BNXT_USE_CHIMP_MB);
5549         req.vf_id = rte_cpu_to_le_16(vf_idx);
5550         snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5551                  bp->eth_dev->data->name, vf_idx);
5552
5553         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5554         HWRM_CHECK_RESULT();
5555         HWRM_UNLOCK();
5556         PMD_DRV_LOG(DEBUG, "VFR %d freed\n", vf_idx);
5557         return rc;
5558 }