drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SPEC_CODE_1_8_3            0x10803
  31 #define HWRM_VERSION_1_9_1              0x10901
  32 #define HWRM_VERSION_1_9_2              0x10903
  33
  34 struct bnxt_plcmodes_cfg {
  35         uint32_t        flags;
  36         uint16_t        jumbo_thresh;
  37         uint16_t        hds_offset;
  38         uint16_t        hds_threshold;
  39 };
  40
  41 static int page_getenum(size_t size)
  42 {
  43         if (size <= 1 << 4)
  44                 return 4;
  45         if (size <= 1 << 12)
  46                 return 12;
  47         if (size <= 1 << 13)
  48                 return 13;
  49         if (size <= 1 << 16)
  50                 return 16;
  51         if (size <= 1 << 21)
  52                 return 21;
  53         if (size <= 1 << 22)
  54                 return 22;
  55         if (size <= 1 << 30)
  56                 return 30;
  57         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  58         return sizeof(void *) * 8 - 1;
  59 }
  60
  61 static int page_roundup(size_t size)
  62 {
  63         return 1 << page_getenum(size);
  64 }
  65
  66 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  67                                   uint8_t *pg_attr,
  68                                   uint64_t *pg_dir)
  69 {
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 /*
  79  * HWRM Functions (sent to HWRM)
  80  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  81  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  82  * command was failed by the ChiMP.
  83  */
  84
  85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  86                                   uint32_t msg_len, bool use_kong_mb)
  87 {
  88         unsigned int i;
  89         struct input *req = msg;
  90         struct output *resp = bp->hwrm_cmd_resp_addr;
  91         uint32_t *data = msg;
  92         uint8_t *bar;
  93         uint8_t *valid;
  94         uint16_t max_req_len = bp->max_req_len;
  95         struct hwrm_short_input short_input = { 0 };
  96         uint16_t bar_offset = use_kong_mb ?
  97                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  98         uint16_t mb_trigger_offset = use_kong_mb ?
  99                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 100
 101         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 102             msg_len > bp->max_req_len) {
 103                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 104
 105                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 106                 memcpy(short_cmd_req, req, msg_len);
 107
 108                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 109                 short_input.signature = rte_cpu_to_le_16(
 110                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 111                 short_input.size = rte_cpu_to_le_16(msg_len);
 112                 short_input.req_addr =
 113                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 114
 115                 data = (uint32_t *)&short_input;
 116                 msg_len = sizeof(short_input);
 117
 118                 /* Sync memory write before updating doorbell */
 119                 rte_wmb();
 120
 121                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 122         }
 123
 124         /* Write request msg to hwrm channel */
 125         for (i = 0; i < msg_len; i += 4) {
 126                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 127                 rte_write32(*data, bar);
 128                 data++;
 129         }
 130
 131         /* Zero the rest of the request space */
 132         for (; i < max_req_len; i += 4) {
 133                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 134                 rte_write32(0, bar);
 135         }
 136
 137         /* Ring channel doorbell */
 138         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 139         rte_write32(1, bar);
 140
 141         /* Poll for the valid bit */
 142         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 143                 /* Sanity check on the resp->resp_len */
 144                 rte_rmb();
 145                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 146                         /* Last byte of resp contains the valid key */
 147                         valid = (uint8_t *)resp + resp->resp_len - 1;
 148                         if (*valid == HWRM_RESP_VALID_KEY)
 149                                 break;
 150                 }
 151                 rte_delay_us(1);
 152         }
 153
 154         if (i >= HWRM_CMD_TIMEOUT) {
 155                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 156                             req->req_type);
 157                 return -ETIMEDOUT;
 158         }
 159         return 0;
 160 }
 161
 162 /*
 163  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 164  * spinlock, and does initial processing.
 165  *
 166  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 167  * releases the spinlock only if it returns.  If the regular int return codes
 168  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 169  * directly, rather it should be copied and modified to suit the function.
 170  *
 171  * HWRM_UNLOCK() must be called after all response processing is completed.
 172  */
 173 #define HWRM_PREP(req, type, kong) do { \
 174         rte_spinlock_lock(&bp->hwrm_lock); \
 175         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 176         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 177         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 178         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 179                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 180         req.target_id = rte_cpu_to_le_16(0xffff); \
 181         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 182 } while (0)
 183
 184 #define HWRM_CHECK_RESULT_SILENT() do {\
 185         if (rc) { \
 186                 rte_spinlock_unlock(&bp->hwrm_lock); \
 187                 return rc; \
 188         } \
 189         if (resp->error_code) { \
 190                 rc = rte_le_to_cpu_16(resp->error_code); \
 191                 rte_spinlock_unlock(&bp->hwrm_lock); \
 192                 return rc; \
 193         } \
 194 } while (0)
 195
 196 #define HWRM_CHECK_RESULT() do {\
 197         if (rc) { \
 198                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 199                 rte_spinlock_unlock(&bp->hwrm_lock); \
 200                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 201                         rc = -EACCES; \
 202                 else if (rc > 0) \
 203                         rc = -EINVAL; \
 204                 return rc; \
 205         } \
 206         if (resp->error_code) { \
 207                 rc = rte_le_to_cpu_16(resp->error_code); \
 208                 if (resp->resp_len >= 16) { \
 209                         struct hwrm_err_output *tmp_hwrm_err_op = \
 210                                                 (void *)resp; \
 211                         PMD_DRV_LOG(ERR, \
 212                                 "error %d:%d:%08x:%04x\n", \
 213                                 rc, tmp_hwrm_err_op->cmd_err, \
 214                                 rte_le_to_cpu_32(\
 215                                         tmp_hwrm_err_op->opaque_0), \
 216                                 rte_le_to_cpu_16(\
 217                                         tmp_hwrm_err_op->opaque_1)); \
 218                 } else { \
 219                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 220                 } \
 221                 rte_spinlock_unlock(&bp->hwrm_lock); \
 222                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 223                         rc = -EACCES; \
 224                 else if (rc > 0) \
 225                         rc = -EINVAL; \
 226                 return rc; \
 227         } \
 228 } while (0)
 229
 230 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 231
 232 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 233 {
 234         int rc = 0;
 235         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 236         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 237
 238         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 239         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 240         req.mask = 0;
 241
 242         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 243
 244         HWRM_CHECK_RESULT();
 245         HWRM_UNLOCK();
 246
 247         return rc;
 248 }
 249
 250 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 251                                  struct bnxt_vnic_info *vnic,
 252                                  uint16_t vlan_count,
 253                                  struct bnxt_vlan_table_entry *vlan_table)
 254 {
 255         int rc = 0;
 256         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 257         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 258         uint32_t mask = 0;
 259
 260         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 261                 return rc;
 262
 263         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 264         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 265
 266         /* FIXME add multicast flag, when multicast adding options is supported
 267          * by ethtool.
 268          */
 269         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 270                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 271         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 272                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 273         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 274                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 275         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 276                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 277         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 278                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 279         if (vnic->mc_addr_cnt) {
 280                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 281                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 282                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 283         }
 284         if (vlan_table) {
 285                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 286                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 287                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 288                          rte_mem_virt2iova(vlan_table));
 289                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 290         }
 291         req.mask = rte_cpu_to_le_32(mask);
 292
 293         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 294
 295         HWRM_CHECK_RESULT();
 296         HWRM_UNLOCK();
 297
 298         return rc;
 299 }
 300
 301 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 302                         uint16_t vlan_count,
 303                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 304 {
 305         int rc = 0;
 306         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 307         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 308                                                 bp->hwrm_cmd_resp_addr;
 309
 310         /*
 311          * Older HWRM versions did not support this command, and the set_rx_mask
 312          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 313          * removed from set_rx_mask call, and this command was added.
 314          *
 315          * This command is also present from 1.7.8.11 and higher,
 316          * as well as 1.7.8.0
 317          */
 318         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 319                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 320                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 321                                         (11)))
 322                                 return 0;
 323                 }
 324         }
 325         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 326         req.fid = rte_cpu_to_le_16(fid);
 327
 328         req.vlan_tag_mask_tbl_addr =
 329                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 330         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 331
 332         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 333
 334         HWRM_CHECK_RESULT();
 335         HWRM_UNLOCK();
 336
 337         return rc;
 338 }
 339
 340 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 341                            struct bnxt_filter_info *filter)
 342 {
 343         int rc = 0;
 344         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 345         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 346
 347         if (filter->fw_l2_filter_id == UINT64_MAX)
 348                 return 0;
 349
 350         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 351
 352         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 353
 354         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 355
 356         HWRM_CHECK_RESULT();
 357         HWRM_UNLOCK();
 358
 359         filter->fw_l2_filter_id = UINT64_MAX;
 360
 361         return 0;
 362 }
 363
 364 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 365                          uint16_t dst_id,
 366                          struct bnxt_filter_info *filter)
 367 {
 368         int rc = 0;
 369         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 370         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 371         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 372         const struct rte_eth_vmdq_rx_conf *conf =
 373                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 374         uint32_t enables = 0;
 375         uint16_t j = dst_id - 1;
 376
 377         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 378         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 379             conf->pool_map[j].pools & (1UL << j)) {
 380                 PMD_DRV_LOG(DEBUG,
 381                         "Add vlan %u to vmdq pool %u\n",
 382                         conf->pool_map[j].vlan_id, j);
 383
 384                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 385                 filter->enables |=
 386                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 387                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 388         }
 389
 390         if (filter->fw_l2_filter_id != UINT64_MAX)
 391                 bnxt_hwrm_clear_l2_filter(bp, filter);
 392
 393         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 394
 395         req.flags = rte_cpu_to_le_32(filter->flags);
 396         req.flags |=
 397         rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
 398
 399         enables = filter->enables |
 400               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 401         req.dst_id = rte_cpu_to_le_16(dst_id);
 402
 403         if (enables &
 404             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 405                 memcpy(req.l2_addr, filter->l2_addr,
 406                        RTE_ETHER_ADDR_LEN);
 407         if (enables &
 408             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 409                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 410                        RTE_ETHER_ADDR_LEN);
 411         if (enables &
 412             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 413                 req.l2_ovlan = filter->l2_ovlan;
 414         if (enables &
 415             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 416                 req.l2_ivlan = filter->l2_ivlan;
 417         if (enables &
 418             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 419                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 420         if (enables &
 421             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 422                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 423         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 424                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 425         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 426                 req.src_type = filter->src_type;
 427
 428         req.enables = rte_cpu_to_le_32(enables);
 429
 430         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 431
 432         HWRM_CHECK_RESULT();
 433
 434         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 435         HWRM_UNLOCK();
 436
 437         return rc;
 438 }
 439
 440 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 441 {
 442         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 443         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 444         uint32_t flags = 0;
 445         int rc;
 446
 447         if (!ptp)
 448                 return 0;
 449
 450         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 451
 452         if (ptp->rx_filter)
 453                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 454         else
 455                 flags |=
 456                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 457         if (ptp->tx_tstamp_en)
 458                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 459         else
 460                 flags |=
 461                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 462         req.flags = rte_cpu_to_le_32(flags);
 463         req.enables = rte_cpu_to_le_32
 464                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 465         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 466
 467         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 468         HWRM_UNLOCK();
 469
 470         return rc;
 471 }
 472
 473 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 474 {
 475         int rc = 0;
 476         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 477         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 478         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 479
 480 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 481         if (ptp)
 482                 return 0;
 483
 484         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 485
 486         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 487
 488         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 489
 490         HWRM_CHECK_RESULT();
 491
 492         if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 493                 return 0;
 494
 495         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 496         if (!ptp)
 497                 return -ENOMEM;
 498
 499         ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 500                 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 501         ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 502                 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 503         ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 504                 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 505         ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 506                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 507         ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 508                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 509         ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 510                 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 511         ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 512                 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 513         ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 514                 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 515         ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 516                 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 517
 518         ptp->bp = bp;
 519         bp->ptp_cfg = ptp;
 520
 521         return 0;
 522 }
 523
 524 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 525 {
 526         int rc = 0;
 527         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 528         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 529         uint16_t new_max_vfs;
 530         uint32_t flags;
 531         int i;
 532
 533         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 534
 535         req.fid = rte_cpu_to_le_16(0xffff);
 536
 537         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 538
 539         HWRM_CHECK_RESULT();
 540
 541         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 542         flags = rte_le_to_cpu_32(resp->flags);
 543         if (BNXT_PF(bp)) {
 544                 bp->pf.port_id = resp->port_id;
 545                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 546                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 547                 new_max_vfs = bp->pdev->max_vfs;
 548                 if (new_max_vfs != bp->pf.max_vfs) {
 549                         if (bp->pf.vf_info)
 550                                 rte_free(bp->pf.vf_info);
 551                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 552                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 553                         bp->pf.max_vfs = new_max_vfs;
 554                         for (i = 0; i < new_max_vfs; i++) {
 555                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 556                                 bp->pf.vf_info[i].vlan_table =
 557                                         rte_zmalloc("VF VLAN table",
 558                                                     getpagesize(),
 559                                                     getpagesize());
 560                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 561                                         PMD_DRV_LOG(ERR,
 562                                         "Fail to alloc VLAN table for VF %d\n",
 563                                         i);
 564                                 else
 565                                         rte_mem_lock_page(
 566                                                 bp->pf.vf_info[i].vlan_table);
 567                                 bp->pf.vf_info[i].vlan_as_table =
 568                                         rte_zmalloc("VF VLAN AS table",
 569                                                     getpagesize(),
 570                                                     getpagesize());
 571                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 572                                         PMD_DRV_LOG(ERR,
 573                                         "Alloc VLAN AS table for VF %d fail\n",
 574                                         i);
 575                                 else
 576                                         rte_mem_lock_page(
 577                                                bp->pf.vf_info[i].vlan_as_table);
 578                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 579                         }
 580                 }
 581         }
 582
 583         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 584         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 585         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 586         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 587         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 588         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 589         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 590         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 591         bp->max_l2_ctx =
 592                 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
 593         /* TODO: For now, do not support VMDq/RFS on VFs. */
 594         if (BNXT_PF(bp)) {
 595                 if (bp->pf.max_vfs)
 596                         bp->max_vnics = 1;
 597                 else
 598                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 599         } else {
 600                 bp->max_vnics = 1;
 601         }
 602         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 603         if (BNXT_PF(bp)) {
 604                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 605                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 606                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 607                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 608                         HWRM_UNLOCK();
 609                         bnxt_hwrm_ptp_qcfg(bp);
 610                 }
 611         }
 612
 613         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 614                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 615
 616         HWRM_UNLOCK();
 617
 618         return rc;
 619 }
 620
 621 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 622 {
 623         int rc;
 624
 625         rc = __bnxt_hwrm_func_qcaps(bp);
 626         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 627                 rc = bnxt_alloc_ctx_mem(bp);
 628                 if (rc)
 629                         return rc;
 630
 631                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 632                 if (!rc)
 633                         bp->flags |= BNXT_FLAG_NEW_RM;
 634         }
 635
 636         return rc;
 637 }
 638
 639 int bnxt_hwrm_func_reset(struct bnxt *bp)
 640 {
 641         int rc = 0;
 642         struct hwrm_func_reset_input req = {.req_type = 0 };
 643         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 644
 645         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 646
 647         req.enables = rte_cpu_to_le_32(0);
 648
 649         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 650
 651         HWRM_CHECK_RESULT();
 652         HWRM_UNLOCK();
 653
 654         return rc;
 655 }
 656
 657 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 658 {
 659         int rc;
 660         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 661         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 662
 663         if (bp->flags & BNXT_FLAG_REGISTERED)
 664                 return 0;
 665
 666         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 667         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 668                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 669         req.ver_maj = RTE_VER_YEAR;
 670         req.ver_min = RTE_VER_MONTH;
 671         req.ver_upd = RTE_VER_MINOR;
 672
 673         if (BNXT_PF(bp)) {
 674                 req.enables |= rte_cpu_to_le_32(
 675                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 676                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 677                        RTE_MIN(sizeof(req.vf_req_fwd),
 678                                sizeof(bp->pf.vf_req_fwd)));
 679
 680                 /*
 681                  * PF can sniff HWRM API issued by VF. This can be set up by
 682                  * linux driver and inherited by the DPDK PF driver. Clear
 683                  * this HWRM sniffer list in FW because DPDK PF driver does
 684                  * not support this.
 685                  */
 686                 req.flags =
 687                 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
 688         }
 689
 690         req.async_event_fwd[0] |=
 691                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 692                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 693                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
 694         req.async_event_fwd[1] |=
 695                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 696                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 697
 698         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 699
 700         HWRM_CHECK_RESULT();
 701         HWRM_UNLOCK();
 702
 703         bp->flags |= BNXT_FLAG_REGISTERED;
 704
 705         return rc;
 706 }
 707
 708 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 709 {
 710         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 711                 return 0;
 712
 713         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 714 }
 715
 716 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 717 {
 718         int rc;
 719         uint32_t flags = 0;
 720         uint32_t enables;
 721         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 722         struct hwrm_func_vf_cfg_input req = {0};
 723
 724         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 725
 726         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 727                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 728                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 729                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 730                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 731
 732         if (BNXT_HAS_RING_GRPS(bp)) {
 733                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 734                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 735         }
 736
 737         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 738         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 739                                             AGG_RING_MULTIPLIER);
 740         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 741         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 742                                               bp->tx_nr_rings);
 743         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 744         if (bp->vf_resv_strategy ==
 745             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 746                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 747                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 748                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 749                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 750                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 751                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 752         }
 753
 754         if (test)
 755                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 756                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 757                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 758                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 759                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 760                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 761
 762         if (test && BNXT_HAS_RING_GRPS(bp))
 763                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 764
 765         req.flags = rte_cpu_to_le_32(flags);
 766         req.enables |= rte_cpu_to_le_32(enables);
 767
 768         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 769
 770         if (test)
 771                 HWRM_CHECK_RESULT_SILENT();
 772         else
 773                 HWRM_CHECK_RESULT();
 774
 775         HWRM_UNLOCK();
 776         return rc;
 777 }
 778
 779 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 780 {
 781         int rc;
 782         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 783         struct hwrm_func_resource_qcaps_input req = {0};
 784
 785         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 786         req.fid = rte_cpu_to_le_16(0xffff);
 787
 788         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 789
 790         HWRM_CHECK_RESULT();
 791
 792         if (BNXT_VF(bp)) {
 793                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 794                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 795                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 796                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 797                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 798                 /* func_resource_qcaps does not return max_rx_em_flows.
 799                  * So use the value provided by func_qcaps.
 800                  */
 801                 bp->max_l2_ctx =
 802                         rte_le_to_cpu_16(resp->max_l2_ctxs) +
 803                         bp->max_rx_em_flows;
 804                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 805                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 806         }
 807         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 808         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 809         if (bp->vf_resv_strategy >
 810             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 811                 bp->vf_resv_strategy =
 812                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 813
 814         HWRM_UNLOCK();
 815         return rc;
 816 }
 817
 818 int bnxt_hwrm_ver_get(struct bnxt *bp)
 819 {
 820         int rc = 0;
 821         struct hwrm_ver_get_input req = {.req_type = 0 };
 822         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 823         uint32_t fw_version;
 824         uint16_t max_resp_len;
 825         char type[RTE_MEMZONE_NAMESIZE];
 826         uint32_t dev_caps_cfg;
 827
 828         bp->max_req_len = HWRM_MAX_REQ_LEN;
 829         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 830
 831         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 832         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 833         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 834
 835         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 836
 837         HWRM_CHECK_RESULT();
 838
 839         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 840                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 841                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 842                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 843         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 844                      (resp->hwrm_fw_min_8b << 16) |
 845                      (resp->hwrm_fw_bld_8b << 8) |
 846                      resp->hwrm_fw_rsvd_8b;
 847         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 848                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 849
 850         fw_version = resp->hwrm_intf_maj_8b << 16;
 851         fw_version |= resp->hwrm_intf_min_8b << 8;
 852         fw_version |= resp->hwrm_intf_upd_8b;
 853         bp->hwrm_spec_code = fw_version;
 854
 855         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 856                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 857                 rc = -EINVAL;
 858                 goto error;
 859         }
 860
 861         if (bp->max_req_len > resp->max_req_win_len) {
 862                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 863                 rc = -EINVAL;
 864         }
 865         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 866         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 867         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 868                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 869
 870         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 871         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 872
 873         if (bp->max_resp_len != max_resp_len) {
 874                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 875                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 876                         bp->pdev->addr.devid, bp->pdev->addr.function);
 877
 878                 rte_free(bp->hwrm_cmd_resp_addr);
 879
 880                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 881                 if (bp->hwrm_cmd_resp_addr == NULL) {
 882                         rc = -ENOMEM;
 883                         goto error;
 884                 }
 885                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 886                 bp->hwrm_cmd_resp_dma_addr =
 887                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 888                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
 889                         PMD_DRV_LOG(ERR,
 890                         "Unable to map response buffer to physical memory.\n");
 891                         rc = -ENOMEM;
 892                         goto error;
 893                 }
 894                 bp->max_resp_len = max_resp_len;
 895         }
 896
 897         if ((dev_caps_cfg &
 898                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 899             (dev_caps_cfg &
 900              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 901                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 902                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 903         }
 904
 905         if (((dev_caps_cfg &
 906               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 907              (dev_caps_cfg &
 908               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
 909             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
 910                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
 911                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 912                         bp->pdev->addr.devid, bp->pdev->addr.function);
 913
 914                 rte_free(bp->hwrm_short_cmd_req_addr);
 915
 916                 bp->hwrm_short_cmd_req_addr =
 917                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
 918                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 919                         rc = -ENOMEM;
 920                         goto error;
 921                 }
 922                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 923                 bp->hwrm_short_cmd_req_dma_addr =
 924                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 925                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
 926                         rte_free(bp->hwrm_short_cmd_req_addr);
 927                         PMD_DRV_LOG(ERR,
 928                                 "Unable to map buffer to physical memory.\n");
 929                         rc = -ENOMEM;
 930                         goto error;
 931                 }
 932         }
 933         if (dev_caps_cfg &
 934             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
 935                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
 936                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
 937         }
 938         if (dev_caps_cfg &
 939             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
 940                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
 941
 942 error:
 943         HWRM_UNLOCK();
 944         return rc;
 945 }
 946
 947 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 948 {
 949         int rc;
 950         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 951         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 952
 953         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 954                 return 0;
 955
 956         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
 957         req.flags = flags;
 958
 959         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 960
 961         HWRM_CHECK_RESULT();
 962         HWRM_UNLOCK();
 963
 964         bp->flags &= ~BNXT_FLAG_REGISTERED;
 965
 966         return rc;
 967 }
 968
 969 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 970 {
 971         int rc = 0;
 972         struct hwrm_port_phy_cfg_input req = {0};
 973         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 974         uint32_t enables = 0;
 975
 976         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
 977
 978         if (conf->link_up) {
 979                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
 980                 if (bp->link_info.auto_mode && conf->link_speed) {
 981                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
 982                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
 983                 }
 984
 985                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 986                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 987                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 988                 /*
 989                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 990                  * any auto mode, even "none".
 991                  */
 992                 if (!conf->link_speed) {
 993                         /* No speeds specified. Enable AutoNeg - all speeds */
 994                         req.auto_mode =
 995                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
 996                 }
 997                 /* AutoNeg - Advertise speeds specified. */
 998                 if (conf->auto_link_speed_mask &&
 999                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1000                         req.auto_mode =
1001                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1002                         req.auto_link_speed_mask =
1003                                 conf->auto_link_speed_mask;
1004                         enables |=
1005                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1006                 }
1007
1008                 req.auto_duplex = conf->duplex;
1009                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1010                 req.auto_pause = conf->auto_pause;
1011                 req.force_pause = conf->force_pause;
1012                 /* Set force_pause if there is no auto or if there is a force */
1013                 if (req.auto_pause && !req.force_pause)
1014                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1015                 else
1016                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1017
1018                 req.enables = rte_cpu_to_le_32(enables);
1019         } else {
1020                 req.flags =
1021                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1022                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1023         }
1024
1025         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1026
1027         HWRM_CHECK_RESULT();
1028         HWRM_UNLOCK();
1029
1030         return rc;
1031 }
1032
1033 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1034                                    struct bnxt_link_info *link_info)
1035 {
1036         int rc = 0;
1037         struct hwrm_port_phy_qcfg_input req = {0};
1038         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1039
1040         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1041
1042         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1043
1044         HWRM_CHECK_RESULT();
1045
1046         link_info->phy_link_status = resp->link;
1047         link_info->link_up =
1048                 (link_info->phy_link_status ==
1049                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1050         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1051         link_info->duplex = resp->duplex_cfg;
1052         link_info->pause = resp->pause;
1053         link_info->auto_pause = resp->auto_pause;
1054         link_info->force_pause = resp->force_pause;
1055         link_info->auto_mode = resp->auto_mode;
1056         link_info->phy_type = resp->phy_type;
1057         link_info->media_type = resp->media_type;
1058
1059         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1060         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1061         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1062         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1063         link_info->phy_ver[0] = resp->phy_maj;
1064         link_info->phy_ver[1] = resp->phy_min;
1065         link_info->phy_ver[2] = resp->phy_bld;
1066
1067         HWRM_UNLOCK();
1068
1069         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1070         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1071         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1072         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1073         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1074                     link_info->auto_link_speed_mask);
1075         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1076                     link_info->force_link_speed);
1077
1078         return rc;
1079 }
1080
1081 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1082 {
1083         int rc = 0;
1084         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1085         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1086         int i;
1087
1088         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1089
1090         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1091         /* HWRM Version >= 1.9.1 */
1092         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1093                 req.drv_qmap_cap =
1094                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1095         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1096
1097         HWRM_CHECK_RESULT();
1098
1099 #define GET_QUEUE_INFO(x) \
1100         bp->cos_queue[x].id = resp->queue_id##x; \
1101         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1102
1103         GET_QUEUE_INFO(0);
1104         GET_QUEUE_INFO(1);
1105         GET_QUEUE_INFO(2);
1106         GET_QUEUE_INFO(3);
1107         GET_QUEUE_INFO(4);
1108         GET_QUEUE_INFO(5);
1109         GET_QUEUE_INFO(6);
1110         GET_QUEUE_INFO(7);
1111
1112         HWRM_UNLOCK();
1113
1114         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1115                 bp->tx_cosq_id = bp->cos_queue[0].id;
1116         } else {
1117                 /* iterate and find the COSq profile to use for Tx */
1118                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1119                         if (bp->cos_queue[i].profile ==
1120                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1121                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1122                                 break;
1123                         }
1124                 }
1125         }
1126
1127         bp->max_tc = resp->max_configurable_queues;
1128         bp->max_lltc = resp->max_configurable_lossless_queues;
1129         if (bp->max_tc > BNXT_MAX_QUEUE)
1130                 bp->max_tc = BNXT_MAX_QUEUE;
1131         bp->max_q = bp->max_tc;
1132
1133         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1134
1135         return rc;
1136 }
1137
1138 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1139                          struct bnxt_ring *ring,
1140                          uint32_t ring_type, uint32_t map_index,
1141                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1142 {
1143         int rc = 0;
1144         uint32_t enables = 0;
1145         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1146         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1147         struct rte_mempool *mb_pool;
1148         uint16_t rx_buf_size;
1149
1150         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1151
1152         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1153         req.fbo = rte_cpu_to_le_32(0);
1154         /* Association of ring index with doorbell index */
1155         req.logical_id = rte_cpu_to_le_16(map_index);
1156         req.length = rte_cpu_to_le_32(ring->ring_size);
1157
1158         switch (ring_type) {
1159         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1160                 req.ring_type = ring_type;
1161                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1162                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1163                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1164                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1165                         enables |=
1166                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1167                 break;
1168         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1169                 req.ring_type = ring_type;
1170                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1171                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1172                 if (BNXT_CHIP_THOR(bp)) {
1173                         mb_pool = bp->rx_queues[0]->mb_pool;
1174                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1175                                       RTE_PKTMBUF_HEADROOM;
1176                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1177                         enables |=
1178                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1179                 }
1180                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1181                         enables |=
1182                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1183                 break;
1184         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1185                 req.ring_type = ring_type;
1186                 if (BNXT_HAS_NQ(bp)) {
1187                         /* Association of cp ring with nq */
1188                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1189                         enables |=
1190                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1191                 }
1192                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1193                 break;
1194         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1195                 req.ring_type = ring_type;
1196                 req.page_size = BNXT_PAGE_SHFT;
1197                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1198                 break;
1199         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1200                 req.ring_type = ring_type;
1201                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1202
1203                 mb_pool = bp->rx_queues[0]->mb_pool;
1204                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1205                               RTE_PKTMBUF_HEADROOM;
1206                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1207
1208                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1209                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1210                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1211                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1212                 break;
1213         default:
1214                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1215                         ring_type);
1216                 HWRM_UNLOCK();
1217                 return -EINVAL;
1218         }
1219         req.enables = rte_cpu_to_le_32(enables);
1220
1221         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1222
1223         if (rc || resp->error_code) {
1224                 if (rc == 0 && resp->error_code)
1225                         rc = rte_le_to_cpu_16(resp->error_code);
1226                 switch (ring_type) {
1227                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1228                         PMD_DRV_LOG(ERR,
1229                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1230                         HWRM_UNLOCK();
1231                         return rc;
1232                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1233                         PMD_DRV_LOG(ERR,
1234                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1235                         HWRM_UNLOCK();
1236                         return rc;
1237                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1238                         PMD_DRV_LOG(ERR,
1239                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1240                                     rc);
1241                         HWRM_UNLOCK();
1242                         return rc;
1243                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1244                         PMD_DRV_LOG(ERR,
1245                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1246                         HWRM_UNLOCK();
1247                         return rc;
1248                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1249                         PMD_DRV_LOG(ERR,
1250                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1251                         HWRM_UNLOCK();
1252                         return rc;
1253                 default:
1254                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1255                         HWRM_UNLOCK();
1256                         return rc;
1257                 }
1258         }
1259
1260         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1261         HWRM_UNLOCK();
1262         return rc;
1263 }
1264
1265 int bnxt_hwrm_ring_free(struct bnxt *bp,
1266                         struct bnxt_ring *ring, uint32_t ring_type)
1267 {
1268         int rc;
1269         struct hwrm_ring_free_input req = {.req_type = 0 };
1270         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1271
1272         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1273
1274         req.ring_type = ring_type;
1275         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1276
1277         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1278
1279         if (rc || resp->error_code) {
1280                 if (rc == 0 && resp->error_code)
1281                         rc = rte_le_to_cpu_16(resp->error_code);
1282                 HWRM_UNLOCK();
1283
1284                 switch (ring_type) {
1285                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1286                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1287                                 rc);
1288                         return rc;
1289                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1290                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1291                                 rc);
1292                         return rc;
1293                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1294                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1295                                 rc);
1296                         return rc;
1297                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1298                         PMD_DRV_LOG(ERR,
1299                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1300                         return rc;
1301                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1302                         PMD_DRV_LOG(ERR,
1303                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1304                         return rc;
1305                 default:
1306                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1307                         return rc;
1308                 }
1309         }
1310         HWRM_UNLOCK();
1311         return 0;
1312 }
1313
1314 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1315 {
1316         int rc = 0;
1317         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1318         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1319
1320         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1321
1322         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1323         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1324         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1325         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1326
1327         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1328
1329         HWRM_CHECK_RESULT();
1330
1331         bp->grp_info[idx].fw_grp_id =
1332             rte_le_to_cpu_16(resp->ring_group_id);
1333
1334         HWRM_UNLOCK();
1335
1336         return rc;
1337 }
1338
1339 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1340 {
1341         int rc;
1342         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1343         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1344
1345         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1346
1347         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1348
1349         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1350
1351         HWRM_CHECK_RESULT();
1352         HWRM_UNLOCK();
1353
1354         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1355         return rc;
1356 }
1357
1358 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1359 {
1360         int rc = 0;
1361         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1362         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1363
1364         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1365                 return rc;
1366
1367         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1368
1369         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1370
1371         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1372
1373         HWRM_CHECK_RESULT();
1374         HWRM_UNLOCK();
1375
1376         return rc;
1377 }
1378
1379 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1380                                 unsigned int idx __rte_unused)
1381 {
1382         int rc;
1383         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1384         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1385
1386         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1387
1388         req.update_period_ms = rte_cpu_to_le_32(0);
1389
1390         req.stats_dma_addr =
1391             rte_cpu_to_le_64(cpr->hw_stats_map);
1392
1393         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1394
1395         HWRM_CHECK_RESULT();
1396
1397         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1398
1399         HWRM_UNLOCK();
1400
1401         return rc;
1402 }
1403
1404 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1405                                 unsigned int idx __rte_unused)
1406 {
1407         int rc;
1408         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1409         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1410
1411         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1412
1413         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1414
1415         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1416
1417         HWRM_CHECK_RESULT();
1418         HWRM_UNLOCK();
1419
1420         return rc;
1421 }
1422
1423 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1424 {
1425         int rc = 0, i, j;
1426         struct hwrm_vnic_alloc_input req = { 0 };
1427         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1428
1429         if (!BNXT_HAS_RING_GRPS(bp))
1430                 goto skip_ring_grps;
1431
1432         /* map ring groups to this vnic */
1433         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1434                 vnic->start_grp_id, vnic->end_grp_id);
1435         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1436                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1437
1438         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1439         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1440         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1441         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1442
1443 skip_ring_grps:
1444         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1445                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1446         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1447
1448         if (vnic->func_default)
1449                 req.flags =
1450                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1451         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1452
1453         HWRM_CHECK_RESULT();
1454
1455         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1456         HWRM_UNLOCK();
1457         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1458         return rc;
1459 }
1460
1461 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1462                                         struct bnxt_vnic_info *vnic,
1463                                         struct bnxt_plcmodes_cfg *pmode)
1464 {
1465         int rc = 0;
1466         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1467         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1468
1469         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1470
1471         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1472
1473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1474
1475         HWRM_CHECK_RESULT();
1476
1477         pmode->flags = rte_le_to_cpu_32(resp->flags);
1478         /* dflt_vnic bit doesn't exist in the _cfg command */
1479         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1480         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1481         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1482         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1483
1484         HWRM_UNLOCK();
1485
1486         return rc;
1487 }
1488
1489 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1490                                        struct bnxt_vnic_info *vnic,
1491                                        struct bnxt_plcmodes_cfg *pmode)
1492 {
1493         int rc = 0;
1494         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1495         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1496
1497         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1498                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1499                 return rc;
1500         }
1501
1502         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1503
1504         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1505         req.flags = rte_cpu_to_le_32(pmode->flags);
1506         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1507         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1508         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1509         req.enables = rte_cpu_to_le_32(
1510             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1511             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1512             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1513         );
1514
1515         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1516
1517         HWRM_CHECK_RESULT();
1518         HWRM_UNLOCK();
1519
1520         return rc;
1521 }
1522
1523 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1524 {
1525         int rc = 0;
1526         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1527         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1528         struct bnxt_plcmodes_cfg pmodes = { 0 };
1529         uint32_t ctx_enable_flag = 0;
1530         uint32_t enables = 0;
1531
1532         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1533                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1534                 return rc;
1535         }
1536
1537         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1538         if (rc)
1539                 return rc;
1540
1541         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1542
1543         if (BNXT_CHIP_THOR(bp)) {
1544                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1545                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1546                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1547
1548                 req.default_rx_ring_id =
1549                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1550                 req.default_cmpl_ring_id =
1551                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1552                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1553                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1554                 goto config_mru;
1555         }
1556
1557         /* Only RSS support for now TBD: COS & LB */
1558         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1559         if (vnic->lb_rule != 0xffff)
1560                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1561         if (vnic->cos_rule != 0xffff)
1562                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1563         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1564                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1565                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1566         }
1567         enables |= ctx_enable_flag;
1568         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1569         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1570         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1571         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1572
1573 config_mru:
1574         req.enables = rte_cpu_to_le_32(enables);
1575         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1576         req.mru = rte_cpu_to_le_16(vnic->mru);
1577         /* Configure default VNIC only once. */
1578         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1579                 req.flags |=
1580                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1581                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1582         }
1583         if (vnic->vlan_strip)
1584                 req.flags |=
1585                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1586         if (vnic->bd_stall)
1587                 req.flags |=
1588                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1589         if (vnic->roce_dual)
1590                 req.flags |= rte_cpu_to_le_32(
1591                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1592         if (vnic->roce_only)
1593                 req.flags |= rte_cpu_to_le_32(
1594                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1595         if (vnic->rss_dflt_cr)
1596                 req.flags |= rte_cpu_to_le_32(
1597                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1598
1599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1600
1601         HWRM_CHECK_RESULT();
1602         HWRM_UNLOCK();
1603
1604         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1605
1606         return rc;
1607 }
1608
1609 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1610                 int16_t fw_vf_id)
1611 {
1612         int rc = 0;
1613         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1614         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1615
1616         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1617                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1618                 return rc;
1619         }
1620         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1621
1622         req.enables =
1623                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1624         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1625         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1626
1627         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1628
1629         HWRM_CHECK_RESULT();
1630
1631         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1632         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1633         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1634         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1635         vnic->mru = rte_le_to_cpu_16(resp->mru);
1636         vnic->func_default = rte_le_to_cpu_32(
1637                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1638         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1639                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1640         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1641                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1642         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1643                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1644         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1645                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1646         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1647                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1648
1649         HWRM_UNLOCK();
1650
1651         return rc;
1652 }
1653
1654 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1655                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1656 {
1657         int rc = 0;
1658         uint16_t ctx_id;
1659         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1660         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1661                                                 bp->hwrm_cmd_resp_addr;
1662
1663         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1664
1665         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1666         HWRM_CHECK_RESULT();
1667
1668         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1669         if (!BNXT_HAS_RING_GRPS(bp))
1670                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1671         else if (ctx_idx == 0)
1672                 vnic->rss_rule = ctx_id;
1673
1674         HWRM_UNLOCK();
1675
1676         return rc;
1677 }
1678
1679 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1680                             struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1681 {
1682         int rc = 0;
1683         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1684         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1685                                                 bp->hwrm_cmd_resp_addr;
1686
1687         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1688                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1689                 return rc;
1690         }
1691         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1692
1693         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1694
1695         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1696
1697         HWRM_CHECK_RESULT();
1698         HWRM_UNLOCK();
1699
1700         return rc;
1701 }
1702
1703 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1704 {
1705         int rc = 0;
1706         struct hwrm_vnic_free_input req = {.req_type = 0 };
1707         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1708
1709         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1710                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1711                 return rc;
1712         }
1713
1714         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1715
1716         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1717
1718         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1719
1720         HWRM_CHECK_RESULT();
1721         HWRM_UNLOCK();
1722
1723         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1724         /* Configure default VNIC again if necessary. */
1725         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1726                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1727
1728         return rc;
1729 }
1730
1731 static int
1732 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1733 {
1734         int i;
1735         int rc = 0;
1736         int nr_ctxs = bp->max_ring_grps;
1737         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1738         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1739
1740         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1741
1742         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1743         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1744         req.hash_mode_flags = vnic->hash_mode;
1745
1746         req.hash_key_tbl_addr =
1747             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1748
1749         for (i = 0; i < nr_ctxs; i++) {
1750                 req.ring_grp_tbl_addr =
1751                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1752                                          i * HW_HASH_INDEX_SIZE);
1753                 req.ring_table_pair_index = i;
1754                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1755
1756                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1757                                             BNXT_USE_CHIMP_MB);
1758
1759                 HWRM_CHECK_RESULT();
1760         }
1761
1762         HWRM_UNLOCK();
1763
1764         return rc;
1765 }
1766
1767 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1768                            struct bnxt_vnic_info *vnic)
1769 {
1770         int rc = 0;
1771         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1772         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1773
1774         if (!vnic->rss_table)
1775                 return 0;
1776
1777         if (BNXT_CHIP_THOR(bp))
1778                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1779
1780         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1781
1782         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1783         req.hash_mode_flags = vnic->hash_mode;
1784
1785         req.ring_grp_tbl_addr =
1786             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1787         req.hash_key_tbl_addr =
1788             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1789         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1790         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1791
1792         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1793
1794         HWRM_CHECK_RESULT();
1795         HWRM_UNLOCK();
1796
1797         return rc;
1798 }
1799
1800 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1801                         struct bnxt_vnic_info *vnic)
1802 {
1803         int rc = 0;
1804         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1805         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1806         uint16_t size;
1807
1808         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1809                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1810                 return rc;
1811         }
1812
1813         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1814
1815         req.flags = rte_cpu_to_le_32(
1816                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1817
1818         req.enables = rte_cpu_to_le_32(
1819                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1820
1821         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1822         size -= RTE_PKTMBUF_HEADROOM;
1823
1824         req.jumbo_thresh = rte_cpu_to_le_16(size);
1825         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1826
1827         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1828
1829         HWRM_CHECK_RESULT();
1830         HWRM_UNLOCK();
1831
1832         return rc;
1833 }
1834
1835 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1836                         struct bnxt_vnic_info *vnic, bool enable)
1837 {
1838         int rc = 0;
1839         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1840         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1841
1842         if (BNXT_CHIP_THOR(bp))
1843                 return 0;
1844
1845         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1846
1847         if (enable) {
1848                 req.enables = rte_cpu_to_le_32(
1849                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1850                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1851                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1852                 req.flags = rte_cpu_to_le_32(
1853                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1854                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1855                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1856                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1857                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1858                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1859                 req.max_agg_segs = rte_cpu_to_le_16(5);
1860                 req.max_aggs =
1861                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1862                 req.min_agg_len = rte_cpu_to_le_32(512);
1863         }
1864         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1865
1866         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1867
1868         HWRM_CHECK_RESULT();
1869         HWRM_UNLOCK();
1870
1871         return rc;
1872 }
1873
1874 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1875 {
1876         struct hwrm_func_cfg_input req = {0};
1877         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1878         int rc;
1879
1880         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1881         req.enables = rte_cpu_to_le_32(
1882                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1883         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1884         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1885
1886         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1887
1888         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1889         HWRM_CHECK_RESULT();
1890         HWRM_UNLOCK();
1891
1892         bp->pf.vf_info[vf].random_mac = false;
1893
1894         return rc;
1895 }
1896
1897 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1898                                   uint64_t *dropped)
1899 {
1900         int rc = 0;
1901         struct hwrm_func_qstats_input req = {.req_type = 0};
1902         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1903
1904         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1905
1906         req.fid = rte_cpu_to_le_16(fid);
1907
1908         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1909
1910         HWRM_CHECK_RESULT();
1911
1912         if (dropped)
1913                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1914
1915         HWRM_UNLOCK();
1916
1917         return rc;
1918 }
1919
1920 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1921                           struct rte_eth_stats *stats)
1922 {
1923         int rc = 0;
1924         struct hwrm_func_qstats_input req = {.req_type = 0};
1925         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1926
1927         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1928
1929         req.fid = rte_cpu_to_le_16(fid);
1930
1931         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1932
1933         HWRM_CHECK_RESULT();
1934
1935         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1936         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1937         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1938         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1939         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1940         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1941
1942         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1943         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1944         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1945         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1946         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1947         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1948
1949         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1950         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1951         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1952
1953         HWRM_UNLOCK();
1954
1955         return rc;
1956 }
1957
1958 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1959 {
1960         int rc = 0;
1961         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1962         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1963
1964         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1965
1966         req.fid = rte_cpu_to_le_16(fid);
1967
1968         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1969
1970         HWRM_CHECK_RESULT();
1971         HWRM_UNLOCK();
1972
1973         return rc;
1974 }
1975
1976 /*
1977  * HWRM utility functions
1978  */
1979
1980 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1981 {
1982         unsigned int i;
1983         int rc = 0;
1984
1985         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1986                 struct bnxt_tx_queue *txq;
1987                 struct bnxt_rx_queue *rxq;
1988                 struct bnxt_cp_ring_info *cpr;
1989
1990                 if (i >= bp->rx_cp_nr_rings) {
1991                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1992                         cpr = txq->cp_ring;
1993                 } else {
1994                         rxq = bp->rx_queues[i];
1995                         cpr = rxq->cp_ring;
1996                 }
1997
1998                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1999                 if (rc)
2000                         return rc;
2001         }
2002         return 0;
2003 }
2004
2005 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2006 {
2007         int rc;
2008         unsigned int i;
2009         struct bnxt_cp_ring_info *cpr;
2010
2011         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2012
2013                 if (i >= bp->rx_cp_nr_rings) {
2014                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2015                 } else {
2016                         cpr = bp->rx_queues[i]->cp_ring;
2017                         if (BNXT_HAS_RING_GRPS(bp))
2018                                 bp->grp_info[i].fw_stats_ctx = -1;
2019                 }
2020                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2021                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2022                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2023                         if (rc)
2024                                 return rc;
2025                 }
2026         }
2027         return 0;
2028 }
2029
2030 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2031 {
2032         unsigned int i;
2033         int rc = 0;
2034
2035         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2036                 struct bnxt_tx_queue *txq;
2037                 struct bnxt_rx_queue *rxq;
2038                 struct bnxt_cp_ring_info *cpr;
2039
2040                 if (i >= bp->rx_cp_nr_rings) {
2041                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2042                         cpr = txq->cp_ring;
2043                 } else {
2044                         rxq = bp->rx_queues[i];
2045                         cpr = rxq->cp_ring;
2046                 }
2047
2048                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2049
2050                 if (rc)
2051                         return rc;
2052         }
2053         return rc;
2054 }
2055
2056 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2057 {
2058         uint16_t idx;
2059         uint32_t rc = 0;
2060
2061         if (!BNXT_HAS_RING_GRPS(bp))
2062                 return 0;
2063
2064         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2065
2066                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2067                         continue;
2068
2069                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2070
2071                 if (rc)
2072                         return rc;
2073         }
2074         return rc;
2075 }
2076
2077 static void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2078 {
2079         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2080
2081         bnxt_hwrm_ring_free(bp, cp_ring,
2082                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2083         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2084         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2085                                      sizeof(*cpr->cp_desc_ring));
2086         cpr->cp_raw_cons = 0;
2087 }
2088
2089 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2090 {
2091         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2092
2093         bnxt_hwrm_ring_free(bp, cp_ring,
2094                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2095         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2096         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2097                         sizeof(*cpr->cp_desc_ring));
2098         cpr->cp_raw_cons = 0;
2099         cpr->valid = 0;
2100 }
2101
2102 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2103 {
2104         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2105         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2106         struct bnxt_ring *ring = rxr->rx_ring_struct;
2107         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2108
2109         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2110                 bnxt_hwrm_ring_free(bp, ring,
2111                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2112                 ring->fw_ring_id = INVALID_HW_RING_ID;
2113                 if (BNXT_HAS_RING_GRPS(bp))
2114                         bp->grp_info[queue_index].rx_fw_ring_id =
2115                                                         INVALID_HW_RING_ID;
2116                 memset(rxr->rx_desc_ring, 0,
2117                        rxr->rx_ring_struct->ring_size *
2118                        sizeof(*rxr->rx_desc_ring));
2119                 memset(rxr->rx_buf_ring, 0,
2120                        rxr->rx_ring_struct->ring_size *
2121                        sizeof(*rxr->rx_buf_ring));
2122                 rxr->rx_prod = 0;
2123         }
2124         ring = rxr->ag_ring_struct;
2125         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2126                 bnxt_hwrm_ring_free(bp, ring,
2127                                     BNXT_CHIP_THOR(bp) ?
2128                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2129                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2130                 ring->fw_ring_id = INVALID_HW_RING_ID;
2131                 memset(rxr->ag_buf_ring, 0,
2132                        rxr->ag_ring_struct->ring_size *
2133                        sizeof(*rxr->ag_buf_ring));
2134                 rxr->ag_prod = 0;
2135                 if (BNXT_HAS_RING_GRPS(bp))
2136                         bp->grp_info[queue_index].ag_fw_ring_id =
2137                                                         INVALID_HW_RING_ID;
2138         }
2139         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2140                 bnxt_free_cp_ring(bp, cpr);
2141                 if (rxq->nq_ring)
2142                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2143         }
2144
2145         if (BNXT_HAS_RING_GRPS(bp))
2146                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2147 }
2148
2149 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2150 {
2151         unsigned int i;
2152
2153         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2154                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2155                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2156                 struct bnxt_ring *ring = txr->tx_ring_struct;
2157                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2158
2159                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2160                         bnxt_hwrm_ring_free(bp, ring,
2161                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2162                         ring->fw_ring_id = INVALID_HW_RING_ID;
2163                         memset(txr->tx_desc_ring, 0,
2164                                         txr->tx_ring_struct->ring_size *
2165                                         sizeof(*txr->tx_desc_ring));
2166                         memset(txr->tx_buf_ring, 0,
2167                                         txr->tx_ring_struct->ring_size *
2168                                         sizeof(*txr->tx_buf_ring));
2169                         txr->tx_prod = 0;
2170                         txr->tx_cons = 0;
2171                 }
2172                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2173                         bnxt_free_cp_ring(bp, cpr);
2174                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2175                         if (txq->nq_ring)
2176                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2177                 }
2178         }
2179
2180         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2181                 bnxt_free_hwrm_rx_ring(bp, i);
2182
2183         return 0;
2184 }
2185
2186 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2187 {
2188         uint16_t i;
2189         uint32_t rc = 0;
2190
2191         if (!BNXT_HAS_RING_GRPS(bp))
2192                 return 0;
2193
2194         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2195                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2196                 if (rc)
2197                         return rc;
2198         }
2199         return rc;
2200 }
2201
2202 void bnxt_free_hwrm_resources(struct bnxt *bp)
2203 {
2204         /* Release memzone */
2205         rte_free(bp->hwrm_cmd_resp_addr);
2206         rte_free(bp->hwrm_short_cmd_req_addr);
2207         bp->hwrm_cmd_resp_addr = NULL;
2208         bp->hwrm_short_cmd_req_addr = NULL;
2209         bp->hwrm_cmd_resp_dma_addr = 0;
2210         bp->hwrm_short_cmd_req_dma_addr = 0;
2211 }
2212
2213 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2214 {
2215         struct rte_pci_device *pdev = bp->pdev;
2216         char type[RTE_MEMZONE_NAMESIZE];
2217
2218         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2219                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2220         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2221         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2222         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2223         if (bp->hwrm_cmd_resp_addr == NULL)
2224                 return -ENOMEM;
2225         bp->hwrm_cmd_resp_dma_addr =
2226                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2227         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2228                 PMD_DRV_LOG(ERR,
2229                         "unable to map response address to physical memory\n");
2230                 return -ENOMEM;
2231         }
2232         rte_spinlock_init(&bp->hwrm_lock);
2233
2234         return 0;
2235 }
2236
2237 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2238 {
2239         struct bnxt_filter_info *filter;
2240         int rc = 0;
2241
2242         STAILQ_FOREACH(filter, &vnic->filter, next) {
2243                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2244                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2245                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2246                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2247                 else
2248                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2249                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2250                 //if (rc)
2251                         //break;
2252         }
2253         return rc;
2254 }
2255
2256 static int
2257 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2258 {
2259         struct bnxt_filter_info *filter;
2260         struct rte_flow *flow;
2261         int rc = 0;
2262
2263         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2264                 filter = flow->filter;
2265                 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
2266                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2267                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2268                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2269                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2270                 else
2271                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2272
2273                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2274                 rte_free(flow);
2275                 //if (rc)
2276                         //break;
2277         }
2278         return rc;
2279 }
2280
2281 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2282 {
2283         struct bnxt_filter_info *filter;
2284         int rc = 0;
2285
2286         STAILQ_FOREACH(filter, &vnic->filter, next) {
2287                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2288                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2289                                                      filter);
2290                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2291                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2292                                                          filter);
2293                 else
2294                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2295                                                      filter);
2296                 if (rc)
2297                         break;
2298         }
2299         return rc;
2300 }
2301
2302 void bnxt_free_tunnel_ports(struct bnxt *bp)
2303 {
2304         if (bp->vxlan_port_cnt)
2305                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2306                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2307         bp->vxlan_port = 0;
2308         if (bp->geneve_port_cnt)
2309                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2310                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2311         bp->geneve_port = 0;
2312 }
2313
2314 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2315 {
2316         int i, j;
2317
2318         if (bp->vnic_info == NULL)
2319                 return;
2320
2321         /*
2322          * Cleanup VNICs in reverse order, to make sure the L2 filter
2323          * from vnic0 is last to be cleaned up.
2324          */
2325         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2326                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2327
2328                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2329                         PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2330                         return;
2331                 }
2332
2333                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2334
2335                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2336
2337                 if (BNXT_CHIP_THOR(bp)) {
2338                         for (j = 0; j < vnic->num_lb_ctxts; j++) {
2339                                 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2340                                                         vnic->fw_grp_ids[j]);
2341                                 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2342                         }
2343                         vnic->num_lb_ctxts = 0;
2344                 } else {
2345                         bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2346                         vnic->rss_rule = INVALID_HW_RING_ID;
2347                 }
2348
2349                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2350
2351                 bnxt_hwrm_vnic_free(bp, vnic);
2352
2353                 rte_free(vnic->fw_grp_ids);
2354         }
2355         /* Ring resources */
2356         bnxt_free_all_hwrm_rings(bp);
2357         bnxt_free_all_hwrm_ring_grps(bp);
2358         bnxt_free_all_hwrm_stat_ctxs(bp);
2359         bnxt_free_tunnel_ports(bp);
2360 }
2361
2362 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2363 {
2364         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2365
2366         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2367                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2368
2369         switch (conf_link_speed) {
2370         case ETH_LINK_SPEED_10M_HD:
2371         case ETH_LINK_SPEED_100M_HD:
2372                 /* FALLTHROUGH */
2373                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2374         }
2375         return hw_link_duplex;
2376 }
2377
2378 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2379 {
2380         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2381 }
2382
2383 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2384 {
2385         uint16_t eth_link_speed = 0;
2386
2387         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2388                 return ETH_LINK_SPEED_AUTONEG;
2389
2390         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2391         case ETH_LINK_SPEED_100M:
2392         case ETH_LINK_SPEED_100M_HD:
2393                 /* FALLTHROUGH */
2394                 eth_link_speed =
2395                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2396                 break;
2397         case ETH_LINK_SPEED_1G:
2398                 eth_link_speed =
2399                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2400                 break;
2401         case ETH_LINK_SPEED_2_5G:
2402                 eth_link_speed =
2403                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2404                 break;
2405         case ETH_LINK_SPEED_10G:
2406                 eth_link_speed =
2407                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2408                 break;
2409         case ETH_LINK_SPEED_20G:
2410                 eth_link_speed =
2411                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2412                 break;
2413         case ETH_LINK_SPEED_25G:
2414                 eth_link_speed =
2415                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2416                 break;
2417         case ETH_LINK_SPEED_40G:
2418                 eth_link_speed =
2419                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2420                 break;
2421         case ETH_LINK_SPEED_50G:
2422                 eth_link_speed =
2423                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2424                 break;
2425         case ETH_LINK_SPEED_100G:
2426                 eth_link_speed =
2427                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2428                 break;
2429         default:
2430                 PMD_DRV_LOG(ERR,
2431                         "Unsupported link speed %d; default to AUTO\n",
2432                         conf_link_speed);
2433                 break;
2434         }
2435         return eth_link_speed;
2436 }
2437
2438 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2439                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2440                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2441                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2442
2443 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2444 {
2445         uint32_t one_speed;
2446
2447         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2448                 return 0;
2449
2450         if (link_speed & ETH_LINK_SPEED_FIXED) {
2451                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2452
2453                 if (one_speed & (one_speed - 1)) {
2454                         PMD_DRV_LOG(ERR,
2455                                 "Invalid advertised speeds (%u) for port %u\n",
2456                                 link_speed, port_id);
2457                         return -EINVAL;
2458                 }
2459                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2460                         PMD_DRV_LOG(ERR,
2461                                 "Unsupported advertised speed (%u) for port %u\n",
2462                                 link_speed, port_id);
2463                         return -EINVAL;
2464                 }
2465         } else {
2466                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2467                         PMD_DRV_LOG(ERR,
2468                                 "Unsupported advertised speeds (%u) for port %u\n",
2469                                 link_speed, port_id);
2470                         return -EINVAL;
2471                 }
2472         }
2473         return 0;
2474 }
2475
2476 static uint16_t
2477 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2478 {
2479         uint16_t ret = 0;
2480
2481         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2482                 if (bp->link_info.support_speeds)
2483                         return bp->link_info.support_speeds;
2484                 link_speed = BNXT_SUPPORTED_SPEEDS;
2485         }
2486
2487         if (link_speed & ETH_LINK_SPEED_100M)
2488                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2489         if (link_speed & ETH_LINK_SPEED_100M_HD)
2490                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2491         if (link_speed & ETH_LINK_SPEED_1G)
2492                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2493         if (link_speed & ETH_LINK_SPEED_2_5G)
2494                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2495         if (link_speed & ETH_LINK_SPEED_10G)
2496                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2497         if (link_speed & ETH_LINK_SPEED_20G)
2498                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2499         if (link_speed & ETH_LINK_SPEED_25G)
2500                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2501         if (link_speed & ETH_LINK_SPEED_40G)
2502                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2503         if (link_speed & ETH_LINK_SPEED_50G)
2504                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2505         if (link_speed & ETH_LINK_SPEED_100G)
2506                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2507         return ret;
2508 }
2509
2510 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2511 {
2512         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2513
2514         switch (hw_link_speed) {
2515         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2516                 eth_link_speed = ETH_SPEED_NUM_100M;
2517                 break;
2518         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2519                 eth_link_speed = ETH_SPEED_NUM_1G;
2520                 break;
2521         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2522                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2523                 break;
2524         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2525                 eth_link_speed = ETH_SPEED_NUM_10G;
2526                 break;
2527         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2528                 eth_link_speed = ETH_SPEED_NUM_20G;
2529                 break;
2530         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2531                 eth_link_speed = ETH_SPEED_NUM_25G;
2532                 break;
2533         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2534                 eth_link_speed = ETH_SPEED_NUM_40G;
2535                 break;
2536         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2537                 eth_link_speed = ETH_SPEED_NUM_50G;
2538                 break;
2539         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2540                 eth_link_speed = ETH_SPEED_NUM_100G;
2541                 break;
2542         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2543         default:
2544                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2545                         hw_link_speed);
2546                 break;
2547         }
2548         return eth_link_speed;
2549 }
2550
2551 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2552 {
2553         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2554
2555         switch (hw_link_duplex) {
2556         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2557         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2558                 /* FALLTHROUGH */
2559                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2560                 break;
2561         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2562                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2563                 break;
2564         default:
2565                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2566                         hw_link_duplex);
2567                 break;
2568         }
2569         return eth_link_duplex;
2570 }
2571
2572 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2573 {
2574         int rc = 0;
2575         struct bnxt_link_info *link_info = &bp->link_info;
2576
2577         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2578         if (rc) {
2579                 PMD_DRV_LOG(ERR,
2580                         "Get link config failed with rc %d\n", rc);
2581                 goto exit;
2582         }
2583         if (link_info->link_speed)
2584                 link->link_speed =
2585                         bnxt_parse_hw_link_speed(link_info->link_speed);
2586         else
2587                 link->link_speed = ETH_SPEED_NUM_NONE;
2588         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2589         link->link_status = link_info->link_up;
2590         link->link_autoneg = link_info->auto_mode ==
2591                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2592                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2593 exit:
2594         return rc;
2595 }
2596
2597 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2598 {
2599         int rc = 0;
2600         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2601         struct bnxt_link_info link_req;
2602         uint16_t speed, autoneg;
2603
2604         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2605                 return 0;
2606
2607         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2608                         bp->eth_dev->data->port_id);
2609         if (rc)
2610                 goto error;
2611
2612         memset(&link_req, 0, sizeof(link_req));
2613         link_req.link_up = link_up;
2614         if (!link_up)
2615                 goto port_phy_cfg;
2616
2617         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2618         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2619         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2620         /* Autoneg can be done only when the FW allows */
2621         if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2622                                 bp->link_info.force_link_speed)) {
2623                 link_req.phy_flags |=
2624                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2625                 link_req.auto_link_speed_mask =
2626                         bnxt_parse_eth_link_speed_mask(bp,
2627                                                        dev_conf->link_speeds);
2628         } else {
2629                 if (bp->link_info.phy_type ==
2630                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2631                     bp->link_info.phy_type ==
2632                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2633                     bp->link_info.media_type ==
2634                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2635                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2636                         return -EINVAL;
2637                 }
2638
2639                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2640                 /* If user wants a particular speed try that first. */
2641                 if (speed)
2642                         link_req.link_speed = speed;
2643                 else if (bp->link_info.force_link_speed)
2644                         link_req.link_speed = bp->link_info.force_link_speed;
2645                 else
2646                         link_req.link_speed = bp->link_info.auto_link_speed;
2647         }
2648         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2649         link_req.auto_pause = bp->link_info.auto_pause;
2650         link_req.force_pause = bp->link_info.force_pause;
2651
2652 port_phy_cfg:
2653         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2654         if (rc) {
2655                 PMD_DRV_LOG(ERR,
2656                         "Set link config failed with rc %d\n", rc);
2657         }
2658
2659 error:
2660         return rc;
2661 }
2662
2663 /* JIRA 22088 */
2664 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2665 {
2666         struct hwrm_func_qcfg_input req = {0};
2667         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2668         uint16_t flags;
2669         int rc = 0;
2670
2671         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2672         req.fid = rte_cpu_to_le_16(0xffff);
2673
2674         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2675
2676         HWRM_CHECK_RESULT();
2677
2678         /* Hard Coded.. 0xfff VLAN ID mask */
2679         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2680         flags = rte_le_to_cpu_16(resp->flags);
2681         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2682                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2683
2684         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2685                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2686                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2687         }
2688
2689         if (mtu)
2690                 *mtu = resp->mtu;
2691
2692         switch (resp->port_partition_type) {
2693         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2694         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2695         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2696                 /* FALLTHROUGH */
2697                 bp->port_partition_type = resp->port_partition_type;
2698                 break;
2699         default:
2700                 bp->port_partition_type = 0;
2701                 break;
2702         }
2703
2704         HWRM_UNLOCK();
2705
2706         return rc;
2707 }
2708
2709 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2710                                    struct hwrm_func_qcaps_output *qcaps)
2711 {
2712         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2713         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2714                sizeof(qcaps->mac_address));
2715         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2716         qcaps->max_rx_rings = fcfg->num_rx_rings;
2717         qcaps->max_tx_rings = fcfg->num_tx_rings;
2718         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2719         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2720         qcaps->max_vfs = 0;
2721         qcaps->first_vf_id = 0;
2722         qcaps->max_vnics = fcfg->num_vnics;
2723         qcaps->max_decap_records = 0;
2724         qcaps->max_encap_records = 0;
2725         qcaps->max_tx_wm_flows = 0;
2726         qcaps->max_tx_em_flows = 0;
2727         qcaps->max_rx_wm_flows = 0;
2728         qcaps->max_rx_em_flows = 0;
2729         qcaps->max_flow_id = 0;
2730         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2731         qcaps->max_sp_tx_rings = 0;
2732         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2733 }
2734
2735 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2736 {
2737         struct hwrm_func_cfg_input req = {0};
2738         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2739         uint32_t enables;
2740         int rc;
2741
2742         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2743                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2744                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2745                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2746                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2747                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2748                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2749                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2750                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2751
2752         if (BNXT_HAS_RING_GRPS(bp)) {
2753                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2754                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2755         } else if (BNXT_HAS_NQ(bp)) {
2756                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2757                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2758         }
2759
2760         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2761         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2762         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2763                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2764                                    BNXT_NUM_VLANS);
2765         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2766         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2767         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2768         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2769         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2770         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2771         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2772         req.fid = rte_cpu_to_le_16(0xffff);
2773         req.enables = rte_cpu_to_le_32(enables);
2774
2775         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2776
2777         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2778
2779         HWRM_CHECK_RESULT();
2780         HWRM_UNLOCK();
2781
2782         return rc;
2783 }
2784
2785 static void populate_vf_func_cfg_req(struct bnxt *bp,
2786                                      struct hwrm_func_cfg_input *req,
2787                                      int num_vfs)
2788 {
2789         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2790                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2791                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2792                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2793                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2794                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2795                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2796                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2797                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2798                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2799
2800         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2801                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2802                                     BNXT_NUM_VLANS);
2803         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2804                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2805                                     BNXT_NUM_VLANS);
2806         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2807                                                 (num_vfs + 1));
2808         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2809         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2810                                                (num_vfs + 1));
2811         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2812         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2813         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2814         /* TODO: For now, do not support VMDq/RFS on VFs. */
2815         req->num_vnics = rte_cpu_to_le_16(1);
2816         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2817                                                  (num_vfs + 1));
2818 }
2819
2820 static void add_random_mac_if_needed(struct bnxt *bp,
2821                                      struct hwrm_func_cfg_input *cfg_req,
2822                                      int vf)
2823 {
2824         struct rte_ether_addr mac;
2825
2826         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2827                 return;
2828
2829         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2830                 cfg_req->enables |=
2831                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2832                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2833                 bp->pf.vf_info[vf].random_mac = true;
2834         } else {
2835                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2836                         RTE_ETHER_ADDR_LEN);
2837         }
2838 }
2839
2840 static void reserve_resources_from_vf(struct bnxt *bp,
2841                                       struct hwrm_func_cfg_input *cfg_req,
2842                                       int vf)
2843 {
2844         struct hwrm_func_qcaps_input req = {0};
2845         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2846         int rc;
2847
2848         /* Get the actual allocated values now */
2849         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2850         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2851         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2852
2853         if (rc) {
2854                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2855                 copy_func_cfg_to_qcaps(cfg_req, resp);
2856         } else if (resp->error_code) {
2857                 rc = rte_le_to_cpu_16(resp->error_code);
2858                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2859                 copy_func_cfg_to_qcaps(cfg_req, resp);
2860         }
2861
2862         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2863         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2864         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2865         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2866         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2867         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2868         /*
2869          * TODO: While not supporting VMDq with VFs, max_vnics is always
2870          * forced to 1 in this case
2871          */
2872         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2873         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2874
2875         HWRM_UNLOCK();
2876 }
2877
2878 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2879 {
2880         struct hwrm_func_qcfg_input req = {0};
2881         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2882         int rc;
2883
2884         /* Check for zero MAC address */
2885         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2886         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2887         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2888         if (rc) {
2889                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2890                 return -1;
2891         } else if (resp->error_code) {
2892                 rc = rte_le_to_cpu_16(resp->error_code);
2893                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2894                 return -1;
2895         }
2896         rc = rte_le_to_cpu_16(resp->vlan);
2897
2898         HWRM_UNLOCK();
2899
2900         return rc;
2901 }
2902
2903 static int update_pf_resource_max(struct bnxt *bp)
2904 {
2905         struct hwrm_func_qcfg_input req = {0};
2906         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2907         int rc;
2908
2909         /* And copy the allocated numbers into the pf struct */
2910         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2911         req.fid = rte_cpu_to_le_16(0xffff);
2912         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2913         HWRM_CHECK_RESULT();
2914
2915         /* Only TX ring value reflects actual allocation? TODO */
2916         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2917         bp->pf.evb_mode = resp->evb_mode;
2918
2919         HWRM_UNLOCK();
2920
2921         return rc;
2922 }
2923
2924 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2925 {
2926         int rc;
2927
2928         if (!BNXT_PF(bp)) {
2929                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2930                 return -EINVAL;
2931         }
2932
2933         rc = bnxt_hwrm_func_qcaps(bp);
2934         if (rc)
2935                 return rc;
2936
2937         bp->pf.func_cfg_flags &=
2938                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2939                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2940         bp->pf.func_cfg_flags |=
2941                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2942         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2943         rc = __bnxt_hwrm_func_qcaps(bp);
2944         return rc;
2945 }
2946
2947 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2948 {
2949         struct hwrm_func_cfg_input req = {0};
2950         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2951         int i;
2952         size_t sz;
2953         int rc = 0;
2954         size_t req_buf_sz;
2955
2956         if (!BNXT_PF(bp)) {
2957                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2958                 return -EINVAL;
2959         }
2960
2961         rc = bnxt_hwrm_func_qcaps(bp);
2962
2963         if (rc)
2964                 return rc;
2965
2966         bp->pf.active_vfs = num_vfs;
2967
2968         /*
2969          * First, configure the PF to only use one TX ring.  This ensures that
2970          * there are enough rings for all VFs.
2971          *
2972          * If we don't do this, when we call func_alloc() later, we will lock
2973          * extra rings to the PF that won't be available during func_cfg() of
2974          * the VFs.
2975          *
2976          * This has been fixed with firmware versions above 20.6.54
2977          */
2978         bp->pf.func_cfg_flags &=
2979                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2980                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2981         bp->pf.func_cfg_flags |=
2982                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2983         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2984         if (rc)
2985                 return rc;
2986
2987         /*
2988          * Now, create and register a buffer to hold forwarded VF requests
2989          */
2990         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2991         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2992                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2993         if (bp->pf.vf_req_buf == NULL) {
2994                 rc = -ENOMEM;
2995                 goto error_free;
2996         }
2997         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2998                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2999         for (i = 0; i < num_vfs; i++)
3000                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3001                                         (i * HWRM_MAX_REQ_LEN);
3002
3003         rc = bnxt_hwrm_func_buf_rgtr(bp);
3004         if (rc)
3005                 goto error_free;
3006
3007         populate_vf_func_cfg_req(bp, &req, num_vfs);
3008
3009         bp->pf.active_vfs = 0;
3010         for (i = 0; i < num_vfs; i++) {
3011                 add_random_mac_if_needed(bp, &req, i);
3012
3013                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3014                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3015                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3016                 rc = bnxt_hwrm_send_message(bp,
3017                                             &req,
3018                                             sizeof(req),
3019                                             BNXT_USE_CHIMP_MB);
3020
3021                 /* Clear enable flag for next pass */
3022                 req.enables &= ~rte_cpu_to_le_32(
3023                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3024
3025                 if (rc || resp->error_code) {
3026                         PMD_DRV_LOG(ERR,
3027                                 "Failed to initizlie VF %d\n", i);
3028                         PMD_DRV_LOG(ERR,
3029                                 "Not all VFs available. (%d, %d)\n",
3030                                 rc, resp->error_code);
3031                         HWRM_UNLOCK();
3032                         break;
3033                 }
3034
3035                 HWRM_UNLOCK();
3036
3037                 reserve_resources_from_vf(bp, &req, i);
3038                 bp->pf.active_vfs++;
3039                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3040         }
3041
3042         /*
3043          * Now configure the PF to use "the rest" of the resources
3044          * We're using STD_TX_RING_MODE here though which will limit the TX
3045          * rings.  This will allow QoS to function properly.  Not setting this
3046          * will cause PF rings to break bandwidth settings.
3047          */
3048         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3049         if (rc)
3050                 goto error_free;
3051
3052         rc = update_pf_resource_max(bp);
3053         if (rc)
3054                 goto error_free;
3055
3056         return rc;
3057
3058 error_free:
3059         bnxt_hwrm_func_buf_unrgtr(bp);
3060         return rc;
3061 }
3062
3063 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3064 {
3065         struct hwrm_func_cfg_input req = {0};
3066         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3067         int rc;
3068
3069         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3070
3071         req.fid = rte_cpu_to_le_16(0xffff);
3072         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3073         req.evb_mode = bp->pf.evb_mode;
3074
3075         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3076         HWRM_CHECK_RESULT();
3077         HWRM_UNLOCK();
3078
3079         return rc;
3080 }
3081
3082 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3083                                 uint8_t tunnel_type)
3084 {
3085         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3086         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3087         int rc = 0;
3088
3089         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3090         req.tunnel_type = tunnel_type;
3091         req.tunnel_dst_port_val = port;
3092         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3093         HWRM_CHECK_RESULT();
3094
3095         switch (tunnel_type) {
3096         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3097                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3098                 bp->vxlan_port = port;
3099                 break;
3100         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3101                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3102                 bp->geneve_port = port;
3103                 break;
3104         default:
3105                 break;
3106         }
3107
3108         HWRM_UNLOCK();
3109
3110         return rc;
3111 }
3112
3113 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3114                                 uint8_t tunnel_type)
3115 {
3116         struct hwrm_tunnel_dst_port_free_input req = {0};
3117         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3118         int rc = 0;
3119
3120         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3121
3122         req.tunnel_type = tunnel_type;
3123         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3124         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3125
3126         HWRM_CHECK_RESULT();
3127         HWRM_UNLOCK();
3128
3129         return rc;
3130 }
3131
3132 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3133                                         uint32_t flags)
3134 {
3135         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3136         struct hwrm_func_cfg_input req = {0};
3137         int rc;
3138
3139         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3140
3141         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3142         req.flags = rte_cpu_to_le_32(flags);
3143         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3144
3145         HWRM_CHECK_RESULT();
3146         HWRM_UNLOCK();
3147
3148         return rc;
3149 }
3150
3151 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3152 {
3153         uint32_t *flag = flagp;
3154
3155         vnic->flags = *flag;
3156 }
3157
3158 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3159 {
3160         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3161 }
3162
3163 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3164 {
3165         int rc = 0;
3166         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3167         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3168
3169         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3170
3171         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3172         req.req_buf_page_size = rte_cpu_to_le_16(
3173                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3174         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3175         req.req_buf_page_addr0 =
3176                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3177         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3178                 PMD_DRV_LOG(ERR,
3179                         "unable to map buffer address to physical memory\n");
3180                 return -ENOMEM;
3181         }
3182
3183         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3184
3185         HWRM_CHECK_RESULT();
3186         HWRM_UNLOCK();
3187
3188         return rc;
3189 }
3190
3191 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3192 {
3193         int rc = 0;
3194         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3195         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3196
3197         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3198                 return 0;
3199
3200         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3201
3202         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3203
3204         HWRM_CHECK_RESULT();
3205         HWRM_UNLOCK();
3206
3207         return rc;
3208 }
3209
3210 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3211 {
3212         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3213         struct hwrm_func_cfg_input req = {0};
3214         int rc;
3215
3216         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3217
3218         req.fid = rte_cpu_to_le_16(0xffff);
3219         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3220         req.enables = rte_cpu_to_le_32(
3221                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3222         req.async_event_cr = rte_cpu_to_le_16(
3223                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3224         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3225
3226         HWRM_CHECK_RESULT();
3227         HWRM_UNLOCK();
3228
3229         return rc;
3230 }
3231
3232 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3233 {
3234         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3235         struct hwrm_func_vf_cfg_input req = {0};
3236         int rc;
3237
3238         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3239
3240         req.enables = rte_cpu_to_le_32(
3241                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3242         req.async_event_cr = rte_cpu_to_le_16(
3243                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3244         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3245
3246         HWRM_CHECK_RESULT();
3247         HWRM_UNLOCK();
3248
3249         return rc;
3250 }
3251
3252 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3253 {
3254         struct hwrm_func_cfg_input req = {0};
3255         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3256         uint16_t dflt_vlan, fid;
3257         uint32_t func_cfg_flags;
3258         int rc = 0;
3259
3260         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3261
3262         if (is_vf) {
3263                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3264                 fid = bp->pf.vf_info[vf].fid;
3265                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3266         } else {
3267                 fid = rte_cpu_to_le_16(0xffff);
3268                 func_cfg_flags = bp->pf.func_cfg_flags;
3269                 dflt_vlan = bp->vlan;
3270         }
3271
3272         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3273         req.fid = rte_cpu_to_le_16(fid);
3274         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3275         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3276
3277         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3278
3279         HWRM_CHECK_RESULT();
3280         HWRM_UNLOCK();
3281
3282         return rc;
3283 }
3284
3285 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3286                         uint16_t max_bw, uint16_t enables)
3287 {
3288         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3289         struct hwrm_func_cfg_input req = {0};
3290         int rc;
3291
3292         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3293
3294         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3295         req.enables |= rte_cpu_to_le_32(enables);
3296         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3297         req.max_bw = rte_cpu_to_le_32(max_bw);
3298         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3299
3300         HWRM_CHECK_RESULT();
3301         HWRM_UNLOCK();
3302
3303         return rc;
3304 }
3305
3306 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3307 {
3308         struct hwrm_func_cfg_input req = {0};
3309         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3310         int rc = 0;
3311
3312         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3313
3314         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3315         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3316         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3317         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3318
3319         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3320
3321         HWRM_CHECK_RESULT();
3322         HWRM_UNLOCK();
3323
3324         return rc;
3325 }
3326
3327 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3328 {
3329         int rc;
3330
3331         if (BNXT_PF(bp))
3332                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3333         else
3334                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3335
3336         return rc;
3337 }
3338
3339 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3340                               void *encaped, size_t ec_size)
3341 {
3342         int rc = 0;
3343         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3344         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3345
3346         if (ec_size > sizeof(req.encap_request))
3347                 return -1;
3348
3349         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3350
3351         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3352         memcpy(req.encap_request, encaped, ec_size);
3353
3354         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3355
3356         HWRM_CHECK_RESULT();
3357         HWRM_UNLOCK();
3358
3359         return rc;
3360 }
3361
3362 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3363                                        struct rte_ether_addr *mac)
3364 {
3365         struct hwrm_func_qcfg_input req = {0};
3366         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3367         int rc;
3368
3369         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3370
3371         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3372         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3373
3374         HWRM_CHECK_RESULT();
3375
3376         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3377
3378         HWRM_UNLOCK();
3379
3380         return rc;
3381 }
3382
3383 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3384                             void *encaped, size_t ec_size)
3385 {
3386         int rc = 0;
3387         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3388         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3389
3390         if (ec_size > sizeof(req.encap_request))
3391                 return -1;
3392
3393         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3394
3395         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3396         memcpy(req.encap_request, encaped, ec_size);
3397
3398         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3399
3400         HWRM_CHECK_RESULT();
3401         HWRM_UNLOCK();
3402
3403         return rc;
3404 }
3405
3406 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3407                          struct rte_eth_stats *stats, uint8_t rx)
3408 {
3409         int rc = 0;
3410         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3411         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3412
3413         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3414
3415         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3416
3417         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3418
3419         HWRM_CHECK_RESULT();
3420
3421         if (rx) {
3422                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3423                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3424                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3425                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3426                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3427                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3428                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3429                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3430         } else {
3431                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3432                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3433                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3434                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3435                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3436                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3437         }
3438
3439
3440         HWRM_UNLOCK();
3441
3442         return rc;
3443 }
3444
3445 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3446 {
3447         struct hwrm_port_qstats_input req = {0};
3448         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3449         struct bnxt_pf_info *pf = &bp->pf;
3450         int rc;
3451
3452         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3453
3454         req.port_id = rte_cpu_to_le_16(pf->port_id);
3455         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3456         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3457         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3458
3459         HWRM_CHECK_RESULT();
3460         HWRM_UNLOCK();
3461
3462         return rc;
3463 }
3464
3465 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3466 {
3467         struct hwrm_port_clr_stats_input req = {0};
3468         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3469         struct bnxt_pf_info *pf = &bp->pf;
3470         int rc;
3471
3472         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3473         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3474             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3475                 return 0;
3476
3477         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3478
3479         req.port_id = rte_cpu_to_le_16(pf->port_id);
3480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3481
3482         HWRM_CHECK_RESULT();
3483         HWRM_UNLOCK();
3484
3485         return rc;
3486 }
3487
3488 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3489 {
3490         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3491         struct hwrm_port_led_qcaps_input req = {0};
3492         int rc;
3493
3494         if (BNXT_VF(bp))
3495                 return 0;
3496
3497         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3498         req.port_id = bp->pf.port_id;
3499         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3500
3501         HWRM_CHECK_RESULT();
3502
3503         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3504                 unsigned int i;
3505
3506                 bp->num_leds = resp->num_leds;
3507                 memcpy(bp->leds, &resp->led0_id,
3508                         sizeof(bp->leds[0]) * bp->num_leds);
3509                 for (i = 0; i < bp->num_leds; i++) {
3510                         struct bnxt_led_info *led = &bp->leds[i];
3511
3512                         uint16_t caps = led->led_state_caps;
3513
3514                         if (!led->led_group_id ||
3515                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3516                                 bp->num_leds = 0;
3517                                 break;
3518                         }
3519                 }
3520         }
3521
3522         HWRM_UNLOCK();
3523
3524         return rc;
3525 }
3526
3527 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3528 {
3529         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3530         struct hwrm_port_led_cfg_input req = {0};
3531         struct bnxt_led_cfg *led_cfg;
3532         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3533         uint16_t duration = 0;
3534         int rc, i;
3535
3536         if (!bp->num_leds || BNXT_VF(bp))
3537                 return -EOPNOTSUPP;
3538
3539         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3540
3541         if (led_on) {
3542                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3543                 duration = rte_cpu_to_le_16(500);
3544         }
3545         req.port_id = bp->pf.port_id;
3546         req.num_leds = bp->num_leds;
3547         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3548         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3549                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3550                 led_cfg->led_id = bp->leds[i].led_id;
3551                 led_cfg->led_state = led_state;
3552                 led_cfg->led_blink_on = duration;
3553                 led_cfg->led_blink_off = duration;
3554                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3555         }
3556
3557         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3558
3559         HWRM_CHECK_RESULT();
3560         HWRM_UNLOCK();
3561
3562         return rc;
3563 }
3564
3565 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3566                                uint32_t *length)
3567 {
3568         int rc;
3569         struct hwrm_nvm_get_dir_info_input req = {0};
3570         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3571
3572         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3573
3574         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3575
3576         HWRM_CHECK_RESULT();
3577
3578         *entries = rte_le_to_cpu_32(resp->entries);
3579         *length = rte_le_to_cpu_32(resp->entry_length);
3580
3581         HWRM_UNLOCK();
3582         return rc;
3583 }
3584
3585 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3586 {
3587         int rc;
3588         uint32_t dir_entries;
3589         uint32_t entry_length;
3590         uint8_t *buf;
3591         size_t buflen;
3592         rte_iova_t dma_handle;
3593         struct hwrm_nvm_get_dir_entries_input req = {0};
3594         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3595
3596         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3597         if (rc != 0)
3598                 return rc;
3599
3600         *data++ = dir_entries;
3601         *data++ = entry_length;
3602         len -= 2;
3603         memset(data, 0xff, len);
3604
3605         buflen = dir_entries * entry_length;
3606         buf = rte_malloc("nvm_dir", buflen, 0);
3607         rte_mem_lock_page(buf);
3608         if (buf == NULL)
3609                 return -ENOMEM;
3610         dma_handle = rte_mem_virt2iova(buf);
3611         if (dma_handle == RTE_BAD_IOVA) {
3612                 PMD_DRV_LOG(ERR,
3613                         "unable to map response address to physical memory\n");
3614                 return -ENOMEM;
3615         }
3616         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3617         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3618         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3619
3620         if (rc == 0)
3621                 memcpy(data, buf, len > buflen ? buflen : len);
3622
3623         rte_free(buf);
3624         HWRM_CHECK_RESULT();
3625         HWRM_UNLOCK();
3626
3627         return rc;
3628 }
3629
3630 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3631                              uint32_t offset, uint32_t length,
3632                              uint8_t *data)
3633 {
3634         int rc;
3635         uint8_t *buf;
3636         rte_iova_t dma_handle;
3637         struct hwrm_nvm_read_input req = {0};
3638         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3639
3640         buf = rte_malloc("nvm_item", length, 0);
3641         rte_mem_lock_page(buf);
3642         if (!buf)
3643                 return -ENOMEM;
3644
3645         dma_handle = rte_mem_virt2iova(buf);
3646         if (dma_handle == RTE_BAD_IOVA) {
3647                 PMD_DRV_LOG(ERR,
3648                         "unable to map response address to physical memory\n");
3649                 return -ENOMEM;
3650         }
3651         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3652         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3653         req.dir_idx = rte_cpu_to_le_16(index);
3654         req.offset = rte_cpu_to_le_32(offset);
3655         req.len = rte_cpu_to_le_32(length);
3656         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3657         if (rc == 0)
3658                 memcpy(data, buf, length);
3659
3660         rte_free(buf);
3661         HWRM_CHECK_RESULT();
3662         HWRM_UNLOCK();
3663
3664         return rc;
3665 }
3666
3667 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3668 {
3669         int rc;
3670         struct hwrm_nvm_erase_dir_entry_input req = {0};
3671         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3672
3673         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3674         req.dir_idx = rte_cpu_to_le_16(index);
3675         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3676         HWRM_CHECK_RESULT();
3677         HWRM_UNLOCK();
3678
3679         return rc;
3680 }
3681
3682
3683 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3684                           uint16_t dir_ordinal, uint16_t dir_ext,
3685                           uint16_t dir_attr, const uint8_t *data,
3686                           size_t data_len)
3687 {
3688         int rc;
3689         struct hwrm_nvm_write_input req = {0};
3690         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3691         rte_iova_t dma_handle;
3692         uint8_t *buf;
3693
3694         buf = rte_malloc("nvm_write", data_len, 0);
3695         rte_mem_lock_page(buf);
3696         if (!buf)
3697                 return -ENOMEM;
3698
3699         dma_handle = rte_mem_virt2iova(buf);
3700         if (dma_handle == RTE_BAD_IOVA) {
3701                 PMD_DRV_LOG(ERR,
3702                         "unable to map response address to physical memory\n");
3703                 return -ENOMEM;
3704         }
3705         memcpy(buf, data, data_len);
3706
3707         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3708
3709         req.dir_type = rte_cpu_to_le_16(dir_type);
3710         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3711         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3712         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3713         req.dir_data_length = rte_cpu_to_le_32(data_len);
3714         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3715
3716         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3717
3718         rte_free(buf);
3719         HWRM_CHECK_RESULT();
3720         HWRM_UNLOCK();
3721
3722         return rc;
3723 }
3724
3725 static void
3726 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3727 {
3728         uint32_t *count = cbdata;
3729
3730         *count = *count + 1;
3731 }
3732
3733 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3734                                      struct bnxt_vnic_info *vnic __rte_unused)
3735 {
3736         return 0;
3737 }
3738
3739 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3740 {
3741         uint32_t count = 0;
3742
3743         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3744             &count, bnxt_vnic_count_hwrm_stub);
3745
3746         return count;
3747 }
3748
3749 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3750                                         uint16_t *vnic_ids)
3751 {
3752         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3753         struct hwrm_func_vf_vnic_ids_query_output *resp =
3754                                                 bp->hwrm_cmd_resp_addr;
3755         int rc;
3756
3757         /* First query all VNIC ids */
3758         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3759
3760         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3761         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3762         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3763
3764         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3765                 HWRM_UNLOCK();
3766                 PMD_DRV_LOG(ERR,
3767                 "unable to map VNIC ID table address to physical memory\n");
3768                 return -ENOMEM;
3769         }
3770         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3771         HWRM_CHECK_RESULT();
3772         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3773
3774         HWRM_UNLOCK();
3775
3776         return rc;
3777 }
3778
3779 /*
3780  * This function queries the VNIC IDs  for a specified VF. It then calls
3781  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3782  * Then it calls the hwrm_cb function to program this new vnic configuration.
3783  */
3784 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3785         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3786         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3787 {
3788         struct bnxt_vnic_info vnic;
3789         int rc = 0;
3790         int i, num_vnic_ids;
3791         uint16_t *vnic_ids;
3792         size_t vnic_id_sz;
3793         size_t sz;
3794
3795         /* First query all VNIC ids */
3796         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3797         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3798                         RTE_CACHE_LINE_SIZE);
3799         if (vnic_ids == NULL)
3800                 return -ENOMEM;
3801
3802         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3803                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3804
3805         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3806
3807         if (num_vnic_ids < 0)
3808                 return num_vnic_ids;
3809
3810         /* Retrieve VNIC, update bd_stall then update */
3811
3812         for (i = 0; i < num_vnic_ids; i++) {
3813                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3814                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3815                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3816                 if (rc)
3817                         break;
3818                 if (vnic.mru <= 4)      /* Indicates unallocated */
3819                         continue;
3820
3821                 vnic_cb(&vnic, cbdata);
3822
3823                 rc = hwrm_cb(bp, &vnic);
3824                 if (rc)
3825                         break;
3826         }
3827
3828         rte_free(vnic_ids);
3829
3830         return rc;
3831 }
3832
3833 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3834                                               bool on)
3835 {
3836         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3837         struct hwrm_func_cfg_input req = {0};
3838         int rc;
3839
3840         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3841
3842         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3843         req.enables |= rte_cpu_to_le_32(
3844                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3845         req.vlan_antispoof_mode = on ?
3846                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3847                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3848         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3849
3850         HWRM_CHECK_RESULT();
3851         HWRM_UNLOCK();
3852
3853         return rc;
3854 }
3855
3856 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3857 {
3858         struct bnxt_vnic_info vnic;
3859         uint16_t *vnic_ids;
3860         size_t vnic_id_sz;
3861         int num_vnic_ids, i;
3862         size_t sz;
3863         int rc;
3864
3865         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3866         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3867                         RTE_CACHE_LINE_SIZE);
3868         if (vnic_ids == NULL)
3869                 return -ENOMEM;
3870
3871         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3872                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3873
3874         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3875         if (rc <= 0)
3876                 goto exit;
3877         num_vnic_ids = rc;
3878
3879         /*
3880          * Loop through to find the default VNIC ID.
3881          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3882          * by sending the hwrm_func_qcfg command to the firmware.
3883          */
3884         for (i = 0; i < num_vnic_ids; i++) {
3885                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3886                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3887                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3888                                         bp->pf.first_vf_id + vf);
3889                 if (rc)
3890                         goto exit;
3891                 if (vnic.func_default) {
3892                         rte_free(vnic_ids);
3893                         return vnic.fw_vnic_id;
3894                 }
3895         }
3896         /* Could not find a default VNIC. */
3897         PMD_DRV_LOG(ERR, "No default VNIC\n");
3898 exit:
3899         rte_free(vnic_ids);
3900         return rc;
3901 }
3902
3903 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3904                          uint16_t dst_id,
3905                          struct bnxt_filter_info *filter)
3906 {
3907         int rc = 0;
3908         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3909         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3910         uint32_t enables = 0;
3911
3912         if (filter->fw_em_filter_id != UINT64_MAX)
3913                 bnxt_hwrm_clear_em_filter(bp, filter);
3914
3915         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3916
3917         req.flags = rte_cpu_to_le_32(filter->flags);
3918
3919         enables = filter->enables |
3920               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3921         req.dst_id = rte_cpu_to_le_16(dst_id);
3922
3923         if (filter->ip_addr_type) {
3924                 req.ip_addr_type = filter->ip_addr_type;
3925                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3926         }
3927         if (enables &
3928             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3929                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3930         if (enables &
3931             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3932                 memcpy(req.src_macaddr, filter->src_macaddr,
3933                        RTE_ETHER_ADDR_LEN);
3934         if (enables &
3935             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3936                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3937                        RTE_ETHER_ADDR_LEN);
3938         if (enables &
3939             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3940                 req.ovlan_vid = filter->l2_ovlan;
3941         if (enables &
3942             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3943                 req.ivlan_vid = filter->l2_ivlan;
3944         if (enables &
3945             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3946                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3947         if (enables &
3948             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3949                 req.ip_protocol = filter->ip_protocol;
3950         if (enables &
3951             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3952                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3953         if (enables &
3954             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3955                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3956         if (enables &
3957             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3958                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3959         if (enables &
3960             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3961                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3962         if (enables &
3963             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3964                 req.mirror_vnic_id = filter->mirror_vnic_id;
3965
3966         req.enables = rte_cpu_to_le_32(enables);
3967
3968         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3969
3970         HWRM_CHECK_RESULT();
3971
3972         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3973         HWRM_UNLOCK();
3974
3975         return rc;
3976 }
3977
3978 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3979 {
3980         int rc = 0;
3981         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3982         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3983
3984         if (filter->fw_em_filter_id == UINT64_MAX)
3985                 return 0;
3986
3987         PMD_DRV_LOG(ERR, "Clear EM filter\n");
3988         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
3989
3990         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3991
3992         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3993
3994         HWRM_CHECK_RESULT();
3995         HWRM_UNLOCK();
3996
3997         filter->fw_em_filter_id = UINT64_MAX;
3998         filter->fw_l2_filter_id = UINT64_MAX;
3999
4000         return 0;
4001 }
4002
4003 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4004                          uint16_t dst_id,
4005                          struct bnxt_filter_info *filter)
4006 {
4007         int rc = 0;
4008         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4009         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4010                                                 bp->hwrm_cmd_resp_addr;
4011         uint32_t enables = 0;
4012
4013         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4014                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4015
4016         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4017
4018         req.flags = rte_cpu_to_le_32(filter->flags);
4019
4020         enables = filter->enables |
4021               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4022         req.dst_id = rte_cpu_to_le_16(dst_id);
4023
4024
4025         if (filter->ip_addr_type) {
4026                 req.ip_addr_type = filter->ip_addr_type;
4027                 enables |=
4028                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4029         }
4030         if (enables &
4031             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4032                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4033         if (enables &
4034             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4035                 memcpy(req.src_macaddr, filter->src_macaddr,
4036                        RTE_ETHER_ADDR_LEN);
4037         //if (enables &
4038             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4039                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4040                        //RTE_ETHER_ADDR_LEN);
4041         if (enables &
4042             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4043                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4044         if (enables &
4045             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4046                 req.ip_protocol = filter->ip_protocol;
4047         if (enables &
4048             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4049                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4050         if (enables &
4051             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4052                 req.src_ipaddr_mask[0] =
4053                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4054         if (enables &
4055             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4056                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4057         if (enables &
4058             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4059                 req.dst_ipaddr_mask[0] =
4060                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4061         if (enables &
4062             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4063                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4064         if (enables &
4065             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4066                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4067         if (enables &
4068             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4069                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4070         if (enables &
4071             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4072                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4073         if (enables &
4074             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4075                 req.mirror_vnic_id = filter->mirror_vnic_id;
4076
4077         req.enables = rte_cpu_to_le_32(enables);
4078
4079         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4080
4081         HWRM_CHECK_RESULT();
4082
4083         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4084         HWRM_UNLOCK();
4085
4086         return rc;
4087 }
4088
4089 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4090                                 struct bnxt_filter_info *filter)
4091 {
4092         int rc = 0;
4093         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4094         struct hwrm_cfa_ntuple_filter_free_output *resp =
4095                                                 bp->hwrm_cmd_resp_addr;
4096
4097         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4098                 return 0;
4099
4100         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4101
4102         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4103
4104         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4105
4106         HWRM_CHECK_RESULT();
4107         HWRM_UNLOCK();
4108
4109         filter->fw_ntuple_filter_id = UINT64_MAX;
4110
4111         return 0;
4112 }
4113
4114 static int
4115 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4116 {
4117         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4118         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4119         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4120         int nr_ctxs = bp->max_ring_grps;
4121         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4122         uint16_t *ring_tbl = vnic->rss_table;
4123         int max_rings = bp->rx_nr_rings;
4124         int i, j, k, cnt;
4125         int rc = 0;
4126
4127         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4128
4129         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4130         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4131         req.hash_mode_flags = vnic->hash_mode;
4132
4133         req.ring_grp_tbl_addr =
4134             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
4135         req.hash_key_tbl_addr =
4136             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4137
4138         for (i = 0, k = 0; i < nr_ctxs; i++) {
4139                 struct bnxt_rx_ring_info *rxr;
4140                 struct bnxt_cp_ring_info *cpr;
4141
4142                 req.ring_table_pair_index = i;
4143                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4144
4145                 for (j = 0; j < 64; j++) {
4146                         uint16_t ring_id;
4147
4148                         /* Find next active ring. */
4149                         for (cnt = 0; cnt < max_rings; cnt++) {
4150                                 if (rx_queue_state[k] !=
4151                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4152                                         break;
4153                                 if (++k == max_rings)
4154                                         k = 0;
4155                         }
4156
4157                         /* Return if no rings are active. */
4158                         if (cnt == max_rings)
4159                                 return 0;
4160
4161                         /* Add rx/cp ring pair to RSS table. */
4162                         rxr = rxqs[k]->rx_ring;
4163                         cpr = rxqs[k]->cp_ring;
4164
4165                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4166                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4167                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4168                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4169
4170                         if (++k == max_rings)
4171                                 k = 0;
4172                 }
4173                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4174                                             BNXT_USE_CHIMP_MB);
4175
4176                 HWRM_CHECK_RESULT();
4177         }
4178
4179         HWRM_UNLOCK();
4180
4181         return rc;
4182 }
4183
4184 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4185 {
4186         unsigned int rss_idx, fw_idx, i;
4187
4188         if (!(vnic->rss_table && vnic->hash_type))
4189                 return 0;
4190
4191         if (BNXT_CHIP_THOR(bp))
4192                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4193
4194         /*
4195          * Fill the RSS hash & redirection table with
4196          * ring group ids for all VNICs
4197          */
4198         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4199                 rss_idx++, fw_idx++) {
4200                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4201                         fw_idx %= bp->rx_cp_nr_rings;
4202                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4203                                 break;
4204                         fw_idx++;
4205                 }
4206                 if (i == bp->rx_cp_nr_rings)
4207                         return 0;
4208                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4209         }
4210         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4211 }
4212
4213 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4214         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4215 {
4216         uint16_t flags;
4217
4218         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4219
4220         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4221         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4222
4223         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4224         req->num_cmpl_dma_aggr_during_int =
4225                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4226
4227         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4228
4229         /* min timer set to 1/2 of interrupt timer */
4230         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4231
4232         /* buf timer set to 1/4 of interrupt timer */
4233         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4234
4235         req->cmpl_aggr_dma_tmr_during_int =
4236                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4237
4238         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4239                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4240         req->flags = rte_cpu_to_le_16(flags);
4241 }
4242
4243 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4244                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4245 {
4246         struct hwrm_ring_aggint_qcaps_input req = {0};
4247         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4248         uint32_t enables;
4249         uint16_t flags;
4250         int rc;
4251
4252         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4253         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4254         HWRM_CHECK_RESULT();
4255
4256         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4257         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4258
4259         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4260                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4261         agg_req->flags = rte_cpu_to_le_16(flags);
4262         enables =
4263          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4264          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4265         agg_req->enables = rte_cpu_to_le_32(enables);
4266
4267         HWRM_UNLOCK();
4268         return rc;
4269 }
4270
4271 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4272                         struct bnxt_coal *coal, uint16_t ring_id)
4273 {
4274         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4275         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4276                                                 bp->hwrm_cmd_resp_addr;
4277         int rc;
4278
4279         /* Set ring coalesce parameters only for 100G NICs */
4280         if (BNXT_CHIP_THOR(bp)) {
4281                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4282                         return -1;
4283         } else if (bnxt_stratus_device(bp)) {
4284                 bnxt_hwrm_set_coal_params(coal, &req);
4285         } else {
4286                 return 0;
4287         }
4288
4289         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4290         req.ring_id = rte_cpu_to_le_16(ring_id);
4291         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4292         HWRM_CHECK_RESULT();
4293         HWRM_UNLOCK();
4294         return 0;
4295 }
4296
4297 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4298 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4299 {
4300         struct hwrm_func_backing_store_qcaps_input req = {0};
4301         struct hwrm_func_backing_store_qcaps_output *resp =
4302                 bp->hwrm_cmd_resp_addr;
4303         int rc;
4304
4305         if (!BNXT_CHIP_THOR(bp) ||
4306             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4307             BNXT_VF(bp) ||
4308             bp->ctx)
4309                 return 0;
4310
4311         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4312         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4313         HWRM_CHECK_RESULT_SILENT();
4314
4315         if (!rc) {
4316                 struct bnxt_ctx_pg_info *ctx_pg;
4317                 struct bnxt_ctx_mem_info *ctx;
4318                 int total_alloc_len;
4319                 int i;
4320
4321                 total_alloc_len = sizeof(*ctx);
4322                 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4323                                  RTE_CACHE_LINE_SIZE);
4324                 if (!ctx) {
4325                         rc = -ENOMEM;
4326                         goto ctx_err;
4327                 }
4328                 memset(ctx, 0, total_alloc_len);
4329
4330                 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4331                                     sizeof(*ctx_pg) * BNXT_MAX_Q,
4332                                     RTE_CACHE_LINE_SIZE);
4333                 if (!ctx_pg) {
4334                         rc = -ENOMEM;
4335                         goto ctx_err;
4336                 }
4337                 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4338                         ctx->tqm_mem[i] = ctx_pg;
4339
4340                 bp->ctx = ctx;
4341                 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4342                 ctx->qp_min_qp1_entries =
4343                         rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4344                 ctx->qp_max_l2_entries =
4345                         rte_le_to_cpu_16(resp->qp_max_l2_entries);
4346                 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4347                 ctx->srq_max_l2_entries =
4348                         rte_le_to_cpu_16(resp->srq_max_l2_entries);
4349                 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4350                 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4351                 ctx->cq_max_l2_entries =
4352                         rte_le_to_cpu_16(resp->cq_max_l2_entries);
4353                 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4354                 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4355                 ctx->vnic_max_vnic_entries =
4356                         rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4357                 ctx->vnic_max_ring_table_entries =
4358                         rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4359                 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4360                 ctx->stat_max_entries =
4361                         rte_le_to_cpu_32(resp->stat_max_entries);
4362                 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4363                 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4364                 ctx->tqm_min_entries_per_ring =
4365                         rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4366                 ctx->tqm_max_entries_per_ring =
4367                         rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4368                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4369                 if (!ctx->tqm_entries_multiple)
4370                         ctx->tqm_entries_multiple = 1;
4371                 ctx->mrav_max_entries =
4372                         rte_le_to_cpu_32(resp->mrav_max_entries);
4373                 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4374                 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4375                 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4376         } else {
4377                 rc = 0;
4378         }
4379 ctx_err:
4380         HWRM_UNLOCK();
4381         return rc;
4382 }
4383
4384 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4385 {
4386         struct hwrm_func_backing_store_cfg_input req = {0};
4387         struct hwrm_func_backing_store_cfg_output *resp =
4388                 bp->hwrm_cmd_resp_addr;
4389         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4390         struct bnxt_ctx_pg_info *ctx_pg;
4391         uint32_t *num_entries;
4392         uint64_t *pg_dir;
4393         uint8_t *pg_attr;
4394         uint32_t ena;
4395         int i, rc;
4396
4397         if (!ctx)
4398                 return 0;
4399
4400         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4401         req.enables = rte_cpu_to_le_32(enables);
4402
4403         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4404                 ctx_pg = &ctx->qp_mem;
4405                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4406                 req.qp_num_qp1_entries =
4407                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4408                 req.qp_num_l2_entries =
4409                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4410                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4411                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4412                                       &req.qpc_pg_size_qpc_lvl,
4413                                       &req.qpc_page_dir);
4414         }
4415
4416         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4417                 ctx_pg = &ctx->srq_mem;
4418                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4419                 req.srq_num_l2_entries =
4420                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4421                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4422                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4423                                       &req.srq_pg_size_srq_lvl,
4424                                       &req.srq_page_dir);
4425         }
4426
4427         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4428                 ctx_pg = &ctx->cq_mem;
4429                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4430                 req.cq_num_l2_entries =
4431                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4432                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4433                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4434                                       &req.cq_pg_size_cq_lvl,
4435                                       &req.cq_page_dir);
4436         }
4437
4438         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4439                 ctx_pg = &ctx->vnic_mem;
4440                 req.vnic_num_vnic_entries =
4441                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4442                 req.vnic_num_ring_table_entries =
4443                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4444                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4445                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4446                                       &req.vnic_pg_size_vnic_lvl,
4447                                       &req.vnic_page_dir);
4448         }
4449
4450         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4451                 ctx_pg = &ctx->stat_mem;
4452                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4453                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4454                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4455                                       &req.stat_pg_size_stat_lvl,
4456                                       &req.stat_page_dir);
4457         }
4458
4459         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4460         num_entries = &req.tqm_sp_num_entries;
4461         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4462         pg_dir = &req.tqm_sp_page_dir;
4463         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4464         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4465                 if (!(enables & ena))
4466                         continue;
4467
4468                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4469
4470                 ctx_pg = ctx->tqm_mem[i];
4471                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4472                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4473         }
4474
4475         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4476         HWRM_CHECK_RESULT();
4477         HWRM_UNLOCK();
4478
4479         return rc;
4480 }
4481
4482 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4483 {
4484         struct hwrm_port_qstats_ext_input req = {0};
4485         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4486         struct bnxt_pf_info *pf = &bp->pf;
4487         int rc;
4488
4489         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4490               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4491                 return 0;
4492
4493         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4494
4495         req.port_id = rte_cpu_to_le_16(pf->port_id);
4496         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4497                 req.tx_stat_host_addr =
4498                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4499                 req.tx_stat_size =
4500                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4501         }
4502         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4503                 req.rx_stat_host_addr =
4504                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4505                 req.rx_stat_size =
4506                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4507         }
4508         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4509
4510         if (rc) {
4511                 bp->fw_rx_port_stats_ext_size = 0;
4512                 bp->fw_tx_port_stats_ext_size = 0;
4513         } else {
4514                 bp->fw_rx_port_stats_ext_size =
4515                         rte_le_to_cpu_16(resp->rx_stat_size);
4516                 bp->fw_tx_port_stats_ext_size =
4517                         rte_le_to_cpu_16(resp->tx_stat_size);
4518         }
4519
4520         HWRM_CHECK_RESULT();
4521         HWRM_UNLOCK();
4522
4523         return rc;
4524 }
4525
4526 int
4527 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4528 {
4529         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4530         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4531                 bp->hwrm_cmd_resp_addr;
4532         int rc = 0;
4533
4534         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_KONG(bp));
4535         req.tunnel_type = type;
4536         req.dest_fid = bp->fw_fid;
4537         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4538         HWRM_CHECK_RESULT();
4539
4540         HWRM_UNLOCK();
4541
4542         return rc;
4543 }
4544
4545 int
4546 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4547 {
4548         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4549         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4550                 bp->hwrm_cmd_resp_addr;
4551         int rc = 0;
4552
4553         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_KONG(bp));
4554         req.tunnel_type = type;
4555         req.dest_fid = bp->fw_fid;
4556         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4557         HWRM_CHECK_RESULT();
4558
4559         HWRM_UNLOCK();
4560
4561         return rc;
4562 }
4563
4564 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4565 {
4566         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4567         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4568                 bp->hwrm_cmd_resp_addr;
4569         int rc = 0;
4570
4571         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_KONG(bp));
4572         req.src_fid = bp->fw_fid;
4573         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4574         HWRM_CHECK_RESULT();
4575
4576         if (type)
4577                 *type = resp->tunnel_mask;
4578
4579         HWRM_UNLOCK();
4580
4581         return rc;
4582 }
4583
4584 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4585                                    uint16_t *dst_fid)
4586 {
4587         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4588         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4589                 bp->hwrm_cmd_resp_addr;
4590         int rc = 0;
4591
4592         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_KONG(bp));
4593         req.src_fid = bp->fw_fid;
4594         req.tunnel_type = tun_type;
4595         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4596         HWRM_CHECK_RESULT();
4597
4598         if (dst_fid)
4599                 *dst_fid = resp->dest_fid;
4600
4601         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4602
4603         HWRM_UNLOCK();
4604
4605         return rc;
4606 }
4607
4608 int bnxt_hwrm_set_mac(struct bnxt *bp)
4609 {
4610         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4611         struct hwrm_func_vf_cfg_input req = {0};
4612         int rc = 0;
4613
4614         if (!BNXT_VF(bp))
4615                 return 0;
4616
4617         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4618
4619         req.enables =
4620                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4621         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4622
4623         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4624
4625         HWRM_CHECK_RESULT();
4626
4627         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4628         HWRM_UNLOCK();
4629
4630         return rc;
4631 }