drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SPEC_CODE_1_8_3            0x10803
  31 #define HWRM_VERSION_1_9_1              0x10901
  32 #define HWRM_VERSION_1_9_2              0x10903
  33
  34 struct bnxt_plcmodes_cfg {
  35         uint32_t        flags;
  36         uint16_t        jumbo_thresh;
  37         uint16_t        hds_offset;
  38         uint16_t        hds_threshold;
  39 };
  40
  41 static int page_getenum(size_t size)
  42 {
  43         if (size <= 1 << 4)
  44                 return 4;
  45         if (size <= 1 << 12)
  46                 return 12;
  47         if (size <= 1 << 13)
  48                 return 13;
  49         if (size <= 1 << 16)
  50                 return 16;
  51         if (size <= 1 << 21)
  52                 return 21;
  53         if (size <= 1 << 22)
  54                 return 22;
  55         if (size <= 1 << 30)
  56                 return 30;
  57         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  58         return sizeof(void *) * 8 - 1;
  59 }
  60
  61 static int page_roundup(size_t size)
  62 {
  63         return 1 << page_getenum(size);
  64 }
  65
  66 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  67                                   uint8_t *pg_attr,
  68                                   uint64_t *pg_dir)
  69 {
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 /*
  79  * HWRM Functions (sent to HWRM)
  80  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  81  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  82  * command was failed by the ChiMP.
  83  */
  84
  85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  86                                   uint32_t msg_len, bool use_kong_mb)
  87 {
  88         unsigned int i;
  89         struct input *req = msg;
  90         struct output *resp = bp->hwrm_cmd_resp_addr;
  91         uint32_t *data = msg;
  92         uint8_t *bar;
  93         uint8_t *valid;
  94         uint16_t max_req_len = bp->max_req_len;
  95         struct hwrm_short_input short_input = { 0 };
  96         uint16_t bar_offset = use_kong_mb ?
  97                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  98         uint16_t mb_trigger_offset = use_kong_mb ?
  99                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 100
 101         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 102             msg_len > bp->max_req_len) {
 103                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 104
 105                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 106                 memcpy(short_cmd_req, req, msg_len);
 107
 108                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 109                 short_input.signature = rte_cpu_to_le_16(
 110                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 111                 short_input.size = rte_cpu_to_le_16(msg_len);
 112                 short_input.req_addr =
 113                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 114
 115                 data = (uint32_t *)&short_input;
 116                 msg_len = sizeof(short_input);
 117
 118                 /* Sync memory write before updating doorbell */
 119                 rte_wmb();
 120
 121                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 122         }
 123
 124         /* Write request msg to hwrm channel */
 125         for (i = 0; i < msg_len; i += 4) {
 126                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 127                 rte_write32(*data, bar);
 128                 data++;
 129         }
 130
 131         /* Zero the rest of the request space */
 132         for (; i < max_req_len; i += 4) {
 133                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 134                 rte_write32(0, bar);
 135         }
 136
 137         /* Ring channel doorbell */
 138         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 139         rte_write32(1, bar);
 140
 141         /* Poll for the valid bit */
 142         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 143                 /* Sanity check on the resp->resp_len */
 144                 rte_rmb();
 145                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 146                         /* Last byte of resp contains the valid key */
 147                         valid = (uint8_t *)resp + resp->resp_len - 1;
 148                         if (*valid == HWRM_RESP_VALID_KEY)
 149                                 break;
 150                 }
 151                 rte_delay_us(1);
 152         }
 153
 154         if (i >= HWRM_CMD_TIMEOUT) {
 155                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 156                             req->req_type);
 157                 return -ETIMEDOUT;
 158         }
 159         return 0;
 160 }
 161
 162 /*
 163  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 164  * spinlock, and does initial processing.
 165  *
 166  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 167  * releases the spinlock only if it returns.  If the regular int return codes
 168  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 169  * directly, rather it should be copied and modified to suit the function.
 170  *
 171  * HWRM_UNLOCK() must be called after all response processing is completed.
 172  */
 173 #define HWRM_PREP(req, type, kong) do { \
 174         rte_spinlock_lock(&bp->hwrm_lock); \
 175         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 176         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 177         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 178         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 179                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 180         req.target_id = rte_cpu_to_le_16(0xffff); \
 181         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 182 } while (0)
 183
 184 #define HWRM_CHECK_RESULT_SILENT() do {\
 185         if (rc) { \
 186                 rte_spinlock_unlock(&bp->hwrm_lock); \
 187                 return rc; \
 188         } \
 189         if (resp->error_code) { \
 190                 rc = rte_le_to_cpu_16(resp->error_code); \
 191                 rte_spinlock_unlock(&bp->hwrm_lock); \
 192                 return rc; \
 193         } \
 194 } while (0)
 195
 196 #define HWRM_CHECK_RESULT() do {\
 197         if (rc) { \
 198                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 199                 rte_spinlock_unlock(&bp->hwrm_lock); \
 200                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 201                         rc = -EACCES; \
 202                 else if (rc > 0) \
 203                         rc = -EINVAL; \
 204                 return rc; \
 205         } \
 206         if (resp->error_code) { \
 207                 rc = rte_le_to_cpu_16(resp->error_code); \
 208                 if (resp->resp_len >= 16) { \
 209                         struct hwrm_err_output *tmp_hwrm_err_op = \
 210                                                 (void *)resp; \
 211                         PMD_DRV_LOG(ERR, \
 212                                 "error %d:%d:%08x:%04x\n", \
 213                                 rc, tmp_hwrm_err_op->cmd_err, \
 214                                 rte_le_to_cpu_32(\
 215                                         tmp_hwrm_err_op->opaque_0), \
 216                                 rte_le_to_cpu_16(\
 217                                         tmp_hwrm_err_op->opaque_1)); \
 218                 } else { \
 219                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 220                 } \
 221                 rte_spinlock_unlock(&bp->hwrm_lock); \
 222                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 223                         rc = -EACCES; \
 224                 else if (rc > 0) \
 225                         rc = -EINVAL; \
 226                 return rc; \
 227         } \
 228 } while (0)
 229
 230 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 231
 232 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 233 {
 234         int rc = 0;
 235         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 236         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 237
 238         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 239         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 240         req.mask = 0;
 241
 242         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 243
 244         HWRM_CHECK_RESULT();
 245         HWRM_UNLOCK();
 246
 247         return rc;
 248 }
 249
 250 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 251                                  struct bnxt_vnic_info *vnic,
 252                                  uint16_t vlan_count,
 253                                  struct bnxt_vlan_table_entry *vlan_table)
 254 {
 255         int rc = 0;
 256         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 257         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 258         uint32_t mask = 0;
 259
 260         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 261                 return rc;
 262
 263         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 264         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 265
 266         /* FIXME add multicast flag, when multicast adding options is supported
 267          * by ethtool.
 268          */
 269         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 270                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 271         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 272                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 273         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 274                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 275         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 276                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 277         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 278                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 279         if (vnic->mc_addr_cnt) {
 280                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 281                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 282                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 283         }
 284         if (vlan_table) {
 285                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 286                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 287                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 288                          rte_mem_virt2iova(vlan_table));
 289                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 290         }
 291         req.mask = rte_cpu_to_le_32(mask);
 292
 293         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 294
 295         HWRM_CHECK_RESULT();
 296         HWRM_UNLOCK();
 297
 298         return rc;
 299 }
 300
 301 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 302                         uint16_t vlan_count,
 303                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 304 {
 305         int rc = 0;
 306         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 307         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 308                                                 bp->hwrm_cmd_resp_addr;
 309
 310         /*
 311          * Older HWRM versions did not support this command, and the set_rx_mask
 312          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 313          * removed from set_rx_mask call, and this command was added.
 314          *
 315          * This command is also present from 1.7.8.11 and higher,
 316          * as well as 1.7.8.0
 317          */
 318         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 319                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 320                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 321                                         (11)))
 322                                 return 0;
 323                 }
 324         }
 325         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 326         req.fid = rte_cpu_to_le_16(fid);
 327
 328         req.vlan_tag_mask_tbl_addr =
 329                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 330         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 331
 332         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 333
 334         HWRM_CHECK_RESULT();
 335         HWRM_UNLOCK();
 336
 337         return rc;
 338 }
 339
 340 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 341                            struct bnxt_filter_info *filter)
 342 {
 343         int rc = 0;
 344         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 345         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 346
 347         if (filter->fw_l2_filter_id == UINT64_MAX)
 348                 return 0;
 349
 350         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 351
 352         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 353
 354         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 355
 356         HWRM_CHECK_RESULT();
 357         HWRM_UNLOCK();
 358
 359         filter->fw_l2_filter_id = UINT64_MAX;
 360
 361         return 0;
 362 }
 363
 364 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 365                          uint16_t dst_id,
 366                          struct bnxt_filter_info *filter)
 367 {
 368         int rc = 0;
 369         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 370         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 371         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 372         const struct rte_eth_vmdq_rx_conf *conf =
 373                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 374         uint32_t enables = 0;
 375         uint16_t j = dst_id - 1;
 376
 377         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 378         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 379             conf->pool_map[j].pools & (1UL << j)) {
 380                 PMD_DRV_LOG(DEBUG,
 381                         "Add vlan %u to vmdq pool %u\n",
 382                         conf->pool_map[j].vlan_id, j);
 383
 384                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 385                 filter->enables |=
 386                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 387                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 388         }
 389
 390         if (filter->fw_l2_filter_id != UINT64_MAX)
 391                 bnxt_hwrm_clear_l2_filter(bp, filter);
 392
 393         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 394
 395         req.flags = rte_cpu_to_le_32(filter->flags);
 396         req.flags |=
 397         rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
 398
 399         enables = filter->enables |
 400               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 401         req.dst_id = rte_cpu_to_le_16(dst_id);
 402
 403         if (enables &
 404             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 405                 memcpy(req.l2_addr, filter->l2_addr,
 406                        RTE_ETHER_ADDR_LEN);
 407         if (enables &
 408             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 409                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 410                        RTE_ETHER_ADDR_LEN);
 411         if (enables &
 412             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 413                 req.l2_ovlan = filter->l2_ovlan;
 414         if (enables &
 415             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 416                 req.l2_ivlan = filter->l2_ivlan;
 417         if (enables &
 418             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 419                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 420         if (enables &
 421             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 422                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 423         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 424                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 425         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 426                 req.src_type = filter->src_type;
 427
 428         req.enables = rte_cpu_to_le_32(enables);
 429
 430         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 431
 432         HWRM_CHECK_RESULT();
 433
 434         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 435         HWRM_UNLOCK();
 436
 437         return rc;
 438 }
 439
 440 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 441 {
 442         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 443         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 444         uint32_t flags = 0;
 445         int rc;
 446
 447         if (!ptp)
 448                 return 0;
 449
 450         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 451
 452         if (ptp->rx_filter)
 453                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 454         else
 455                 flags |=
 456                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 457         if (ptp->tx_tstamp_en)
 458                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 459         else
 460                 flags |=
 461                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 462         req.flags = rte_cpu_to_le_32(flags);
 463         req.enables = rte_cpu_to_le_32
 464                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 465         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 466
 467         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 468         HWRM_UNLOCK();
 469
 470         return rc;
 471 }
 472
 473 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 474 {
 475         int rc = 0;
 476         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 477         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 478         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 479
 480 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 481         if (ptp)
 482                 return 0;
 483
 484         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 485
 486         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 487
 488         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 489
 490         HWRM_CHECK_RESULT();
 491
 492         if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 493                 return 0;
 494
 495         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 496         if (!ptp)
 497                 return -ENOMEM;
 498
 499         ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 500                 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 501         ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 502                 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 503         ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 504                 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 505         ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 506                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 507         ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 508                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 509         ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 510                 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 511         ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 512                 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 513         ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 514                 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 515         ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 516                 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 517
 518         ptp->bp = bp;
 519         bp->ptp_cfg = ptp;
 520
 521         return 0;
 522 }
 523
 524 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 525 {
 526         int rc = 0;
 527         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 528         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 529         uint16_t new_max_vfs;
 530         uint32_t flags;
 531         int i;
 532
 533         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 534
 535         req.fid = rte_cpu_to_le_16(0xffff);
 536
 537         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 538
 539         HWRM_CHECK_RESULT();
 540
 541         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 542         flags = rte_le_to_cpu_32(resp->flags);
 543         if (BNXT_PF(bp)) {
 544                 bp->pf.port_id = resp->port_id;
 545                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 546                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 547                 new_max_vfs = bp->pdev->max_vfs;
 548                 if (new_max_vfs != bp->pf.max_vfs) {
 549                         if (bp->pf.vf_info)
 550                                 rte_free(bp->pf.vf_info);
 551                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 552                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 553                         bp->pf.max_vfs = new_max_vfs;
 554                         for (i = 0; i < new_max_vfs; i++) {
 555                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 556                                 bp->pf.vf_info[i].vlan_table =
 557                                         rte_zmalloc("VF VLAN table",
 558                                                     getpagesize(),
 559                                                     getpagesize());
 560                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 561                                         PMD_DRV_LOG(ERR,
 562                                         "Fail to alloc VLAN table for VF %d\n",
 563                                         i);
 564                                 else
 565                                         rte_mem_lock_page(
 566                                                 bp->pf.vf_info[i].vlan_table);
 567                                 bp->pf.vf_info[i].vlan_as_table =
 568                                         rte_zmalloc("VF VLAN AS table",
 569                                                     getpagesize(),
 570                                                     getpagesize());
 571                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 572                                         PMD_DRV_LOG(ERR,
 573                                         "Alloc VLAN AS table for VF %d fail\n",
 574                                         i);
 575                                 else
 576                                         rte_mem_lock_page(
 577                                                bp->pf.vf_info[i].vlan_as_table);
 578                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 579                         }
 580                 }
 581         }
 582
 583         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 584         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 585         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 586         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 587         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 588         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 589         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 590         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 591         bp->max_l2_ctx =
 592                 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
 593         /* TODO: For now, do not support VMDq/RFS on VFs. */
 594         if (BNXT_PF(bp)) {
 595                 if (bp->pf.max_vfs)
 596                         bp->max_vnics = 1;
 597                 else
 598                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 599         } else {
 600                 bp->max_vnics = 1;
 601         }
 602         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 603         if (BNXT_PF(bp)) {
 604                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 605                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 606                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 607                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 608                         HWRM_UNLOCK();
 609                         bnxt_hwrm_ptp_qcfg(bp);
 610                 }
 611         }
 612
 613         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 614                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 615
 616         HWRM_UNLOCK();
 617
 618         return rc;
 619 }
 620
 621 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 622 {
 623         int rc;
 624
 625         rc = __bnxt_hwrm_func_qcaps(bp);
 626         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 627                 rc = bnxt_alloc_ctx_mem(bp);
 628                 if (rc)
 629                         return rc;
 630
 631                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 632                 if (!rc)
 633                         bp->flags |= BNXT_FLAG_NEW_RM;
 634         }
 635
 636         return rc;
 637 }
 638
 639 int bnxt_hwrm_func_reset(struct bnxt *bp)
 640 {
 641         int rc = 0;
 642         struct hwrm_func_reset_input req = {.req_type = 0 };
 643         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 644
 645         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 646
 647         req.enables = rte_cpu_to_le_32(0);
 648
 649         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 650
 651         HWRM_CHECK_RESULT();
 652         HWRM_UNLOCK();
 653
 654         return rc;
 655 }
 656
 657 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 658 {
 659         int rc;
 660         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 661         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 662
 663         if (bp->flags & BNXT_FLAG_REGISTERED)
 664                 return 0;
 665
 666         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 667         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 668                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 669         req.ver_maj = RTE_VER_YEAR;
 670         req.ver_min = RTE_VER_MONTH;
 671         req.ver_upd = RTE_VER_MINOR;
 672
 673         if (BNXT_PF(bp)) {
 674                 req.enables |= rte_cpu_to_le_32(
 675                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 676                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 677                        RTE_MIN(sizeof(req.vf_req_fwd),
 678                                sizeof(bp->pf.vf_req_fwd)));
 679
 680                 /*
 681                  * PF can sniff HWRM API issued by VF. This can be set up by
 682                  * linux driver and inherited by the DPDK PF driver. Clear
 683                  * this HWRM sniffer list in FW because DPDK PF driver does
 684                  * not support this.
 685                  */
 686                 req.flags =
 687                 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
 688         }
 689
 690         req.async_event_fwd[0] |=
 691                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 692                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 693                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
 694         req.async_event_fwd[1] |=
 695                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 696                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 697
 698         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 699
 700         HWRM_CHECK_RESULT();
 701         HWRM_UNLOCK();
 702
 703         bp->flags |= BNXT_FLAG_REGISTERED;
 704
 705         return rc;
 706 }
 707
 708 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 709 {
 710         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 711                 return 0;
 712
 713         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 714 }
 715
 716 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 717 {
 718         int rc;
 719         uint32_t flags = 0;
 720         uint32_t enables;
 721         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 722         struct hwrm_func_vf_cfg_input req = {0};
 723
 724         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 725
 726         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 727                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 728                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 729                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 730                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 731
 732         if (BNXT_HAS_RING_GRPS(bp)) {
 733                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 734                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 735         }
 736
 737         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 738         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 739                                             AGG_RING_MULTIPLIER);
 740         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 741         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 742                                               bp->tx_nr_rings);
 743         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 744         if (bp->vf_resv_strategy ==
 745             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 746                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 747                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 748                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 749                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 750                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 751                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 752         }
 753
 754         if (test)
 755                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 756                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 757                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 758                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 759                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 760                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 761
 762         if (test && BNXT_HAS_RING_GRPS(bp))
 763                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 764
 765         req.flags = rte_cpu_to_le_32(flags);
 766         req.enables |= rte_cpu_to_le_32(enables);
 767
 768         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 769
 770         if (test)
 771                 HWRM_CHECK_RESULT_SILENT();
 772         else
 773                 HWRM_CHECK_RESULT();
 774
 775         HWRM_UNLOCK();
 776         return rc;
 777 }
 778
 779 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 780 {
 781         int rc;
 782         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 783         struct hwrm_func_resource_qcaps_input req = {0};
 784
 785         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 786         req.fid = rte_cpu_to_le_16(0xffff);
 787
 788         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 789
 790         HWRM_CHECK_RESULT();
 791
 792         if (BNXT_VF(bp)) {
 793                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 794                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 795                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 796                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 797                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 798                 /* func_resource_qcaps does not return max_rx_em_flows.
 799                  * So use the value provided by func_qcaps.
 800                  */
 801                 bp->max_l2_ctx =
 802                         rte_le_to_cpu_16(resp->max_l2_ctxs) +
 803                         bp->max_rx_em_flows;
 804                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 805                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 806         }
 807         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 808         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 809         if (bp->vf_resv_strategy >
 810             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 811                 bp->vf_resv_strategy =
 812                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 813
 814         HWRM_UNLOCK();
 815         return rc;
 816 }
 817
 818 int bnxt_hwrm_ver_get(struct bnxt *bp)
 819 {
 820         int rc = 0;
 821         struct hwrm_ver_get_input req = {.req_type = 0 };
 822         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 823         uint32_t fw_version;
 824         uint16_t max_resp_len;
 825         char type[RTE_MEMZONE_NAMESIZE];
 826         uint32_t dev_caps_cfg;
 827
 828         bp->max_req_len = HWRM_MAX_REQ_LEN;
 829         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 830
 831         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 832         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 833         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 834
 835         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 836
 837         HWRM_CHECK_RESULT();
 838
 839         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 840                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 841                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 842                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 843         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 844                      (resp->hwrm_fw_min_8b << 16) |
 845                      (resp->hwrm_fw_bld_8b << 8) |
 846                      resp->hwrm_fw_rsvd_8b;
 847         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 848                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 849
 850         fw_version = resp->hwrm_intf_maj_8b << 16;
 851         fw_version |= resp->hwrm_intf_min_8b << 8;
 852         fw_version |= resp->hwrm_intf_upd_8b;
 853         bp->hwrm_spec_code = fw_version;
 854
 855         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 856                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 857                 rc = -EINVAL;
 858                 goto error;
 859         }
 860
 861         if (bp->max_req_len > resp->max_req_win_len) {
 862                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 863                 rc = -EINVAL;
 864         }
 865         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 866         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 867         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 868                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 869
 870         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 871         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 872
 873         if (bp->max_resp_len != max_resp_len) {
 874                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 875                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 876                         bp->pdev->addr.devid, bp->pdev->addr.function);
 877
 878                 rte_free(bp->hwrm_cmd_resp_addr);
 879
 880                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 881                 if (bp->hwrm_cmd_resp_addr == NULL) {
 882                         rc = -ENOMEM;
 883                         goto error;
 884                 }
 885                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 886                 bp->hwrm_cmd_resp_dma_addr =
 887                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 888                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
 889                         PMD_DRV_LOG(ERR,
 890                         "Unable to map response buffer to physical memory.\n");
 891                         rc = -ENOMEM;
 892                         goto error;
 893                 }
 894                 bp->max_resp_len = max_resp_len;
 895         }
 896
 897         if ((dev_caps_cfg &
 898                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 899             (dev_caps_cfg &
 900              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 901                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 902                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 903         }
 904
 905         if (((dev_caps_cfg &
 906               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 907              (dev_caps_cfg &
 908               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
 909             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
 910                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
 911                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 912                         bp->pdev->addr.devid, bp->pdev->addr.function);
 913
 914                 rte_free(bp->hwrm_short_cmd_req_addr);
 915
 916                 bp->hwrm_short_cmd_req_addr =
 917                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
 918                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 919                         rc = -ENOMEM;
 920                         goto error;
 921                 }
 922                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 923                 bp->hwrm_short_cmd_req_dma_addr =
 924                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 925                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
 926                         rte_free(bp->hwrm_short_cmd_req_addr);
 927                         PMD_DRV_LOG(ERR,
 928                                 "Unable to map buffer to physical memory.\n");
 929                         rc = -ENOMEM;
 930                         goto error;
 931                 }
 932         }
 933         if (dev_caps_cfg &
 934             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
 935                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
 936                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
 937         }
 938         if (dev_caps_cfg &
 939             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
 940                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
 941
 942 error:
 943         HWRM_UNLOCK();
 944         return rc;
 945 }
 946
 947 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 948 {
 949         int rc;
 950         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 951         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 952
 953         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 954                 return 0;
 955
 956         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
 957         req.flags = flags;
 958
 959         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 960
 961         HWRM_CHECK_RESULT();
 962         HWRM_UNLOCK();
 963
 964         bp->flags &= ~BNXT_FLAG_REGISTERED;
 965
 966         return rc;
 967 }
 968
 969 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 970 {
 971         int rc = 0;
 972         struct hwrm_port_phy_cfg_input req = {0};
 973         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 974         uint32_t enables = 0;
 975
 976         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
 977
 978         if (conf->link_up) {
 979                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
 980                 if (bp->link_info.auto_mode && conf->link_speed) {
 981                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
 982                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
 983                 }
 984
 985                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 986                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 987                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 988                 /*
 989                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 990                  * any auto mode, even "none".
 991                  */
 992                 if (!conf->link_speed) {
 993                         /* No speeds specified. Enable AutoNeg - all speeds */
 994                         req.auto_mode =
 995                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
 996                 }
 997                 /* AutoNeg - Advertise speeds specified. */
 998                 if (conf->auto_link_speed_mask &&
 999                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1000                         req.auto_mode =
1001                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1002                         req.auto_link_speed_mask =
1003                                 conf->auto_link_speed_mask;
1004                         enables |=
1005                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1006                 }
1007
1008                 req.auto_duplex = conf->duplex;
1009                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1010                 req.auto_pause = conf->auto_pause;
1011                 req.force_pause = conf->force_pause;
1012                 /* Set force_pause if there is no auto or if there is a force */
1013                 if (req.auto_pause && !req.force_pause)
1014                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1015                 else
1016                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1017
1018                 req.enables = rte_cpu_to_le_32(enables);
1019         } else {
1020                 req.flags =
1021                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1022                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1023         }
1024
1025         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1026
1027         HWRM_CHECK_RESULT();
1028         HWRM_UNLOCK();
1029
1030         return rc;
1031 }
1032
1033 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1034                                    struct bnxt_link_info *link_info)
1035 {
1036         int rc = 0;
1037         struct hwrm_port_phy_qcfg_input req = {0};
1038         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1039
1040         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1041
1042         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1043
1044         HWRM_CHECK_RESULT();
1045
1046         link_info->phy_link_status = resp->link;
1047         link_info->link_up =
1048                 (link_info->phy_link_status ==
1049                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1050         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1051         link_info->duplex = resp->duplex_cfg;
1052         link_info->pause = resp->pause;
1053         link_info->auto_pause = resp->auto_pause;
1054         link_info->force_pause = resp->force_pause;
1055         link_info->auto_mode = resp->auto_mode;
1056         link_info->phy_type = resp->phy_type;
1057         link_info->media_type = resp->media_type;
1058
1059         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1060         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1061         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1062         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1063         link_info->phy_ver[0] = resp->phy_maj;
1064         link_info->phy_ver[1] = resp->phy_min;
1065         link_info->phy_ver[2] = resp->phy_bld;
1066
1067         HWRM_UNLOCK();
1068
1069         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1070         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1071         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1072         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1073         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1074                     link_info->auto_link_speed_mask);
1075         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1076                     link_info->force_link_speed);
1077
1078         return rc;
1079 }
1080
1081 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1082 {
1083         int rc = 0;
1084         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1085         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1086         int i;
1087
1088         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1089
1090         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1091         /* HWRM Version >= 1.9.1 */
1092         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1093                 req.drv_qmap_cap =
1094                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1095         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1096
1097         HWRM_CHECK_RESULT();
1098
1099 #define GET_QUEUE_INFO(x) \
1100         bp->cos_queue[x].id = resp->queue_id##x; \
1101         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1102
1103         GET_QUEUE_INFO(0);
1104         GET_QUEUE_INFO(1);
1105         GET_QUEUE_INFO(2);
1106         GET_QUEUE_INFO(3);
1107         GET_QUEUE_INFO(4);
1108         GET_QUEUE_INFO(5);
1109         GET_QUEUE_INFO(6);
1110         GET_QUEUE_INFO(7);
1111
1112         HWRM_UNLOCK();
1113
1114         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1115                 bp->tx_cosq_id = bp->cos_queue[0].id;
1116         } else {
1117                 /* iterate and find the COSq profile to use for Tx */
1118                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1119                         if (bp->cos_queue[i].profile ==
1120                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1121                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1122                                 break;
1123                         }
1124                 }
1125         }
1126
1127         bp->max_tc = resp->max_configurable_queues;
1128         bp->max_lltc = resp->max_configurable_lossless_queues;
1129         if (bp->max_tc > BNXT_MAX_QUEUE)
1130                 bp->max_tc = BNXT_MAX_QUEUE;
1131         bp->max_q = bp->max_tc;
1132
1133         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1134
1135         return rc;
1136 }
1137
1138 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1139                          struct bnxt_ring *ring,
1140                          uint32_t ring_type, uint32_t map_index,
1141                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1142 {
1143         int rc = 0;
1144         uint32_t enables = 0;
1145         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1146         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1147         struct rte_mempool *mb_pool;
1148         uint16_t rx_buf_size;
1149
1150         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1151
1152         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1153         req.fbo = rte_cpu_to_le_32(0);
1154         /* Association of ring index with doorbell index */
1155         req.logical_id = rte_cpu_to_le_16(map_index);
1156         req.length = rte_cpu_to_le_32(ring->ring_size);
1157
1158         switch (ring_type) {
1159         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1160                 req.ring_type = ring_type;
1161                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1162                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1163                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1164                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1165                         enables |=
1166                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1167                 break;
1168         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1169                 req.ring_type = ring_type;
1170                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1171                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1172                 if (BNXT_CHIP_THOR(bp)) {
1173                         mb_pool = bp->rx_queues[0]->mb_pool;
1174                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1175                                       RTE_PKTMBUF_HEADROOM;
1176                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1177                         enables |=
1178                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1179                 }
1180                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1181                         enables |=
1182                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1183                 break;
1184         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1185                 req.ring_type = ring_type;
1186                 if (BNXT_HAS_NQ(bp)) {
1187                         /* Association of cp ring with nq */
1188                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1189                         enables |=
1190                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1191                 }
1192                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1193                 break;
1194         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1195                 req.ring_type = ring_type;
1196                 req.page_size = BNXT_PAGE_SHFT;
1197                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1198                 break;
1199         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1200                 req.ring_type = ring_type;
1201                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1202
1203                 mb_pool = bp->rx_queues[0]->mb_pool;
1204                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1205                               RTE_PKTMBUF_HEADROOM;
1206                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1207
1208                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1209                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1210                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1211                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1212                 break;
1213         default:
1214                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1215                         ring_type);
1216                 HWRM_UNLOCK();
1217                 return -EINVAL;
1218         }
1219         req.enables = rte_cpu_to_le_32(enables);
1220
1221         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1222
1223         if (rc || resp->error_code) {
1224                 if (rc == 0 && resp->error_code)
1225                         rc = rte_le_to_cpu_16(resp->error_code);
1226                 switch (ring_type) {
1227                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1228                         PMD_DRV_LOG(ERR,
1229                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1230                         HWRM_UNLOCK();
1231                         return rc;
1232                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1233                         PMD_DRV_LOG(ERR,
1234                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1235                         HWRM_UNLOCK();
1236                         return rc;
1237                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1238                         PMD_DRV_LOG(ERR,
1239                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1240                                     rc);
1241                         HWRM_UNLOCK();
1242                         return rc;
1243                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1244                         PMD_DRV_LOG(ERR,
1245                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1246                         HWRM_UNLOCK();
1247                         return rc;
1248                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1249                         PMD_DRV_LOG(ERR,
1250                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1251                         HWRM_UNLOCK();
1252                         return rc;
1253                 default:
1254                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1255                         HWRM_UNLOCK();
1256                         return rc;
1257                 }
1258         }
1259
1260         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1261         HWRM_UNLOCK();
1262         return rc;
1263 }
1264
1265 int bnxt_hwrm_ring_free(struct bnxt *bp,
1266                         struct bnxt_ring *ring, uint32_t ring_type)
1267 {
1268         int rc;
1269         struct hwrm_ring_free_input req = {.req_type = 0 };
1270         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1271
1272         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1273
1274         req.ring_type = ring_type;
1275         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1276
1277         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1278
1279         if (rc || resp->error_code) {
1280                 if (rc == 0 && resp->error_code)
1281                         rc = rte_le_to_cpu_16(resp->error_code);
1282                 HWRM_UNLOCK();
1283
1284                 switch (ring_type) {
1285                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1286                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1287                                 rc);
1288                         return rc;
1289                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1290                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1291                                 rc);
1292                         return rc;
1293                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1294                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1295                                 rc);
1296                         return rc;
1297                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1298                         PMD_DRV_LOG(ERR,
1299                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1300                         return rc;
1301                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1302                         PMD_DRV_LOG(ERR,
1303                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1304                         return rc;
1305                 default:
1306                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1307                         return rc;
1308                 }
1309         }
1310         HWRM_UNLOCK();
1311         return 0;
1312 }
1313
1314 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1315 {
1316         int rc = 0;
1317         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1318         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1319
1320         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1321
1322         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1323         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1324         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1325         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1326
1327         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1328
1329         HWRM_CHECK_RESULT();
1330
1331         bp->grp_info[idx].fw_grp_id =
1332             rte_le_to_cpu_16(resp->ring_group_id);
1333
1334         HWRM_UNLOCK();
1335
1336         return rc;
1337 }
1338
1339 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1340 {
1341         int rc;
1342         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1343         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1344
1345         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1346
1347         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1348
1349         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1350
1351         HWRM_CHECK_RESULT();
1352         HWRM_UNLOCK();
1353
1354         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1355         return rc;
1356 }
1357
1358 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1359 {
1360         int rc = 0;
1361         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1362         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1363
1364         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1365                 return rc;
1366
1367         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1368
1369         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1370
1371         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1372
1373         HWRM_CHECK_RESULT();
1374         HWRM_UNLOCK();
1375
1376         return rc;
1377 }
1378
1379 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1380                                 unsigned int idx __rte_unused)
1381 {
1382         int rc;
1383         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1384         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1385
1386         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1387
1388         req.update_period_ms = rte_cpu_to_le_32(0);
1389
1390         req.stats_dma_addr =
1391             rte_cpu_to_le_64(cpr->hw_stats_map);
1392
1393         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1394
1395         HWRM_CHECK_RESULT();
1396
1397         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1398
1399         HWRM_UNLOCK();
1400
1401         return rc;
1402 }
1403
1404 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1405                                 unsigned int idx __rte_unused)
1406 {
1407         int rc;
1408         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1409         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1410
1411         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1412
1413         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1414
1415         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1416
1417         HWRM_CHECK_RESULT();
1418         HWRM_UNLOCK();
1419
1420         return rc;
1421 }
1422
1423 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1424 {
1425         int rc = 0, i, j;
1426         struct hwrm_vnic_alloc_input req = { 0 };
1427         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1428
1429         if (!BNXT_HAS_RING_GRPS(bp))
1430                 goto skip_ring_grps;
1431
1432         /* map ring groups to this vnic */
1433         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1434                 vnic->start_grp_id, vnic->end_grp_id);
1435         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1436                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1437
1438         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1439         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1440         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1441         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1442
1443 skip_ring_grps:
1444         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1445                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1446         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1447
1448         if (vnic->func_default)
1449                 req.flags =
1450                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1451         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1452
1453         HWRM_CHECK_RESULT();
1454
1455         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1456         HWRM_UNLOCK();
1457         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1458         return rc;
1459 }
1460
1461 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1462                                         struct bnxt_vnic_info *vnic,
1463                                         struct bnxt_plcmodes_cfg *pmode)
1464 {
1465         int rc = 0;
1466         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1467         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1468
1469         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1470
1471         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1472
1473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1474
1475         HWRM_CHECK_RESULT();
1476
1477         pmode->flags = rte_le_to_cpu_32(resp->flags);
1478         /* dflt_vnic bit doesn't exist in the _cfg command */
1479         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1480         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1481         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1482         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1483
1484         HWRM_UNLOCK();
1485
1486         return rc;
1487 }
1488
1489 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1490                                        struct bnxt_vnic_info *vnic,
1491                                        struct bnxt_plcmodes_cfg *pmode)
1492 {
1493         int rc = 0;
1494         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1495         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1496
1497         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1498                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1499                 return rc;
1500         }
1501
1502         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1503
1504         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1505         req.flags = rte_cpu_to_le_32(pmode->flags);
1506         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1507         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1508         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1509         req.enables = rte_cpu_to_le_32(
1510             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1511             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1512             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1513         );
1514
1515         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1516
1517         HWRM_CHECK_RESULT();
1518         HWRM_UNLOCK();
1519
1520         return rc;
1521 }
1522
1523 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1524 {
1525         int rc = 0;
1526         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1527         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1528         struct bnxt_plcmodes_cfg pmodes = { 0 };
1529         uint32_t ctx_enable_flag = 0;
1530         uint32_t enables = 0;
1531
1532         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1533                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1534                 return rc;
1535         }
1536
1537         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1538         if (rc)
1539                 return rc;
1540
1541         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1542
1543         if (BNXT_CHIP_THOR(bp)) {
1544                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1545                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1546                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1547
1548                 req.default_rx_ring_id =
1549                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1550                 req.default_cmpl_ring_id =
1551                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1552                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1553                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1554                 goto config_mru;
1555         }
1556
1557         /* Only RSS support for now TBD: COS & LB */
1558         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1559         if (vnic->lb_rule != 0xffff)
1560                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1561         if (vnic->cos_rule != 0xffff)
1562                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1563         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1564                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1565                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1566         }
1567         enables |= ctx_enable_flag;
1568         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1569         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1570         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1571         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1572
1573 config_mru:
1574         req.enables = rte_cpu_to_le_32(enables);
1575         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1576         req.mru = rte_cpu_to_le_16(vnic->mru);
1577         /* Configure default VNIC only once. */
1578         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1579                 req.flags |=
1580                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1581                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1582         }
1583         if (vnic->vlan_strip)
1584                 req.flags |=
1585                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1586         if (vnic->bd_stall)
1587                 req.flags |=
1588                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1589         if (vnic->roce_dual)
1590                 req.flags |= rte_cpu_to_le_32(
1591                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1592         if (vnic->roce_only)
1593                 req.flags |= rte_cpu_to_le_32(
1594                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1595         if (vnic->rss_dflt_cr)
1596                 req.flags |= rte_cpu_to_le_32(
1597                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1598
1599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1600
1601         HWRM_CHECK_RESULT();
1602         HWRM_UNLOCK();
1603
1604         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1605
1606         return rc;
1607 }
1608
1609 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1610                 int16_t fw_vf_id)
1611 {
1612         int rc = 0;
1613         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1614         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1615
1616         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1617                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1618                 return rc;
1619         }
1620         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1621
1622         req.enables =
1623                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1624         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1625         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1626
1627         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1628
1629         HWRM_CHECK_RESULT();
1630
1631         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1632         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1633         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1634         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1635         vnic->mru = rte_le_to_cpu_16(resp->mru);
1636         vnic->func_default = rte_le_to_cpu_32(
1637                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1638         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1639                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1640         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1641                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1642         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1643                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1644         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1645                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1646         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1647                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1648
1649         HWRM_UNLOCK();
1650
1651         return rc;
1652 }
1653
1654 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1655                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1656 {
1657         int rc = 0;
1658         uint16_t ctx_id;
1659         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1660         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1661                                                 bp->hwrm_cmd_resp_addr;
1662
1663         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1664
1665         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1666         HWRM_CHECK_RESULT();
1667
1668         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1669         if (!BNXT_HAS_RING_GRPS(bp))
1670                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1671         else if (ctx_idx == 0)
1672                 vnic->rss_rule = ctx_id;
1673
1674         HWRM_UNLOCK();
1675
1676         return rc;
1677 }
1678
1679 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1680                             struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1681 {
1682         int rc = 0;
1683         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1684         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1685                                                 bp->hwrm_cmd_resp_addr;
1686
1687         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1688                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1689                 return rc;
1690         }
1691         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1692
1693         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1694
1695         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1696
1697         HWRM_CHECK_RESULT();
1698         HWRM_UNLOCK();
1699
1700         return rc;
1701 }
1702
1703 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1704 {
1705         int rc = 0;
1706         struct hwrm_vnic_free_input req = {.req_type = 0 };
1707         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1708
1709         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1710                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1711                 return rc;
1712         }
1713
1714         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1715
1716         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1717
1718         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1719
1720         HWRM_CHECK_RESULT();
1721         HWRM_UNLOCK();
1722
1723         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1724         /* Configure default VNIC again if necessary. */
1725         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1726                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1727
1728         return rc;
1729 }
1730
1731 static int
1732 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1733 {
1734         int i;
1735         int rc = 0;
1736         int nr_ctxs = bp->max_ring_grps;
1737         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1738         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1739
1740         for (i = 0; i < nr_ctxs; i++) {
1741                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1742
1743                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1744                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1745                 req.hash_mode_flags = vnic->hash_mode;
1746
1747                 req.hash_key_tbl_addr =
1748                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1749
1750                 req.ring_grp_tbl_addr =
1751                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1752                                          i * HW_HASH_INDEX_SIZE);
1753                 req.ring_table_pair_index = i;
1754                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1755
1756                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1757                                             BNXT_USE_CHIMP_MB);
1758
1759                 HWRM_CHECK_RESULT();
1760                 HWRM_UNLOCK();
1761         }
1762
1763         return rc;
1764 }
1765
1766 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1767                            struct bnxt_vnic_info *vnic)
1768 {
1769         int rc = 0;
1770         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1771         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1772
1773         if (!vnic->rss_table)
1774                 return 0;
1775
1776         if (BNXT_CHIP_THOR(bp))
1777                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1778
1779         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1780
1781         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1782         req.hash_mode_flags = vnic->hash_mode;
1783
1784         req.ring_grp_tbl_addr =
1785             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1786         req.hash_key_tbl_addr =
1787             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1788         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1789         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1790
1791         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1792
1793         HWRM_CHECK_RESULT();
1794         HWRM_UNLOCK();
1795
1796         return rc;
1797 }
1798
1799 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1800                         struct bnxt_vnic_info *vnic)
1801 {
1802         int rc = 0;
1803         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1804         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1805         uint16_t size;
1806
1807         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1808                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1809                 return rc;
1810         }
1811
1812         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1813
1814         req.flags = rte_cpu_to_le_32(
1815                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1816
1817         req.enables = rte_cpu_to_le_32(
1818                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1819
1820         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1821         size -= RTE_PKTMBUF_HEADROOM;
1822
1823         req.jumbo_thresh = rte_cpu_to_le_16(size);
1824         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1825
1826         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1827
1828         HWRM_CHECK_RESULT();
1829         HWRM_UNLOCK();
1830
1831         return rc;
1832 }
1833
1834 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1835                         struct bnxt_vnic_info *vnic, bool enable)
1836 {
1837         int rc = 0;
1838         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1839         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1840
1841         if (BNXT_CHIP_THOR(bp))
1842                 return 0;
1843
1844         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1845
1846         if (enable) {
1847                 req.enables = rte_cpu_to_le_32(
1848                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1849                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1850                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1851                 req.flags = rte_cpu_to_le_32(
1852                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1853                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1854                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1855                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1856                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1857                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1858                 req.max_agg_segs = rte_cpu_to_le_16(5);
1859                 req.max_aggs =
1860                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1861                 req.min_agg_len = rte_cpu_to_le_32(512);
1862         }
1863         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1864
1865         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1866
1867         HWRM_CHECK_RESULT();
1868         HWRM_UNLOCK();
1869
1870         return rc;
1871 }
1872
1873 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1874 {
1875         struct hwrm_func_cfg_input req = {0};
1876         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1877         int rc;
1878
1879         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1880         req.enables = rte_cpu_to_le_32(
1881                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1882         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1883         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1884
1885         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1886
1887         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1888         HWRM_CHECK_RESULT();
1889         HWRM_UNLOCK();
1890
1891         bp->pf.vf_info[vf].random_mac = false;
1892
1893         return rc;
1894 }
1895
1896 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1897                                   uint64_t *dropped)
1898 {
1899         int rc = 0;
1900         struct hwrm_func_qstats_input req = {.req_type = 0};
1901         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1902
1903         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1904
1905         req.fid = rte_cpu_to_le_16(fid);
1906
1907         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1908
1909         HWRM_CHECK_RESULT();
1910
1911         if (dropped)
1912                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1913
1914         HWRM_UNLOCK();
1915
1916         return rc;
1917 }
1918
1919 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1920                           struct rte_eth_stats *stats)
1921 {
1922         int rc = 0;
1923         struct hwrm_func_qstats_input req = {.req_type = 0};
1924         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1925
1926         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1927
1928         req.fid = rte_cpu_to_le_16(fid);
1929
1930         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1931
1932         HWRM_CHECK_RESULT();
1933
1934         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1935         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1936         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1937         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1938         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1939         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1940
1941         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1942         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1943         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1944         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1945         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1946         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1947
1948         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1949         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1950         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1951
1952         HWRM_UNLOCK();
1953
1954         return rc;
1955 }
1956
1957 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1958 {
1959         int rc = 0;
1960         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1961         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1962
1963         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1964
1965         req.fid = rte_cpu_to_le_16(fid);
1966
1967         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1968
1969         HWRM_CHECK_RESULT();
1970         HWRM_UNLOCK();
1971
1972         return rc;
1973 }
1974
1975 /*
1976  * HWRM utility functions
1977  */
1978
1979 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1980 {
1981         unsigned int i;
1982         int rc = 0;
1983
1984         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1985                 struct bnxt_tx_queue *txq;
1986                 struct bnxt_rx_queue *rxq;
1987                 struct bnxt_cp_ring_info *cpr;
1988
1989                 if (i >= bp->rx_cp_nr_rings) {
1990                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1991                         cpr = txq->cp_ring;
1992                 } else {
1993                         rxq = bp->rx_queues[i];
1994                         cpr = rxq->cp_ring;
1995                 }
1996
1997                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1998                 if (rc)
1999                         return rc;
2000         }
2001         return 0;
2002 }
2003
2004 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2005 {
2006         int rc;
2007         unsigned int i;
2008         struct bnxt_cp_ring_info *cpr;
2009
2010         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2011
2012                 if (i >= bp->rx_cp_nr_rings) {
2013                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2014                 } else {
2015                         cpr = bp->rx_queues[i]->cp_ring;
2016                         if (BNXT_HAS_RING_GRPS(bp))
2017                                 bp->grp_info[i].fw_stats_ctx = -1;
2018                 }
2019                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2020                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2021                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2022                         if (rc)
2023                                 return rc;
2024                 }
2025         }
2026         return 0;
2027 }
2028
2029 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2030 {
2031         unsigned int i;
2032         int rc = 0;
2033
2034         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2035                 struct bnxt_tx_queue *txq;
2036                 struct bnxt_rx_queue *rxq;
2037                 struct bnxt_cp_ring_info *cpr;
2038
2039                 if (i >= bp->rx_cp_nr_rings) {
2040                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2041                         cpr = txq->cp_ring;
2042                 } else {
2043                         rxq = bp->rx_queues[i];
2044                         cpr = rxq->cp_ring;
2045                 }
2046
2047                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2048
2049                 if (rc)
2050                         return rc;
2051         }
2052         return rc;
2053 }
2054
2055 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2056 {
2057         uint16_t idx;
2058         uint32_t rc = 0;
2059
2060         if (!BNXT_HAS_RING_GRPS(bp))
2061                 return 0;
2062
2063         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2064
2065                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2066                         continue;
2067
2068                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2069
2070                 if (rc)
2071                         return rc;
2072         }
2073         return rc;
2074 }
2075
2076 static void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2077 {
2078         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2079
2080         bnxt_hwrm_ring_free(bp, cp_ring,
2081                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2082         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2083         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2084                                      sizeof(*cpr->cp_desc_ring));
2085         cpr->cp_raw_cons = 0;
2086 }
2087
2088 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2089 {
2090         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2091
2092         bnxt_hwrm_ring_free(bp, cp_ring,
2093                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2094         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2095         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2096                         sizeof(*cpr->cp_desc_ring));
2097         cpr->cp_raw_cons = 0;
2098         cpr->valid = 0;
2099 }
2100
2101 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2102 {
2103         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2104         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2105         struct bnxt_ring *ring = rxr->rx_ring_struct;
2106         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2107
2108         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2109                 bnxt_hwrm_ring_free(bp, ring,
2110                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2111                 ring->fw_ring_id = INVALID_HW_RING_ID;
2112                 if (BNXT_HAS_RING_GRPS(bp))
2113                         bp->grp_info[queue_index].rx_fw_ring_id =
2114                                                         INVALID_HW_RING_ID;
2115                 memset(rxr->rx_desc_ring, 0,
2116                        rxr->rx_ring_struct->ring_size *
2117                        sizeof(*rxr->rx_desc_ring));
2118                 memset(rxr->rx_buf_ring, 0,
2119                        rxr->rx_ring_struct->ring_size *
2120                        sizeof(*rxr->rx_buf_ring));
2121                 rxr->rx_prod = 0;
2122         }
2123         ring = rxr->ag_ring_struct;
2124         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2125                 bnxt_hwrm_ring_free(bp, ring,
2126                                     BNXT_CHIP_THOR(bp) ?
2127                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2128                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2129                 ring->fw_ring_id = INVALID_HW_RING_ID;
2130                 memset(rxr->ag_buf_ring, 0,
2131                        rxr->ag_ring_struct->ring_size *
2132                        sizeof(*rxr->ag_buf_ring));
2133                 rxr->ag_prod = 0;
2134                 if (BNXT_HAS_RING_GRPS(bp))
2135                         bp->grp_info[queue_index].ag_fw_ring_id =
2136                                                         INVALID_HW_RING_ID;
2137         }
2138         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2139                 bnxt_free_cp_ring(bp, cpr);
2140                 if (rxq->nq_ring)
2141                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2142         }
2143
2144         if (BNXT_HAS_RING_GRPS(bp))
2145                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2146 }
2147
2148 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2149 {
2150         unsigned int i;
2151
2152         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2153                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2154                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2155                 struct bnxt_ring *ring = txr->tx_ring_struct;
2156                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2157
2158                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2159                         bnxt_hwrm_ring_free(bp, ring,
2160                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2161                         ring->fw_ring_id = INVALID_HW_RING_ID;
2162                         memset(txr->tx_desc_ring, 0,
2163                                         txr->tx_ring_struct->ring_size *
2164                                         sizeof(*txr->tx_desc_ring));
2165                         memset(txr->tx_buf_ring, 0,
2166                                         txr->tx_ring_struct->ring_size *
2167                                         sizeof(*txr->tx_buf_ring));
2168                         txr->tx_prod = 0;
2169                         txr->tx_cons = 0;
2170                 }
2171                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2172                         bnxt_free_cp_ring(bp, cpr);
2173                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2174                         if (txq->nq_ring)
2175                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2176                 }
2177         }
2178
2179         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2180                 bnxt_free_hwrm_rx_ring(bp, i);
2181
2182         return 0;
2183 }
2184
2185 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2186 {
2187         uint16_t i;
2188         uint32_t rc = 0;
2189
2190         if (!BNXT_HAS_RING_GRPS(bp))
2191                 return 0;
2192
2193         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2194                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2195                 if (rc)
2196                         return rc;
2197         }
2198         return rc;
2199 }
2200
2201 void bnxt_free_hwrm_resources(struct bnxt *bp)
2202 {
2203         /* Release memzone */
2204         rte_free(bp->hwrm_cmd_resp_addr);
2205         rte_free(bp->hwrm_short_cmd_req_addr);
2206         bp->hwrm_cmd_resp_addr = NULL;
2207         bp->hwrm_short_cmd_req_addr = NULL;
2208         bp->hwrm_cmd_resp_dma_addr = 0;
2209         bp->hwrm_short_cmd_req_dma_addr = 0;
2210 }
2211
2212 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2213 {
2214         struct rte_pci_device *pdev = bp->pdev;
2215         char type[RTE_MEMZONE_NAMESIZE];
2216
2217         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2218                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2219         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2220         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2221         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2222         if (bp->hwrm_cmd_resp_addr == NULL)
2223                 return -ENOMEM;
2224         bp->hwrm_cmd_resp_dma_addr =
2225                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2226         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2227                 PMD_DRV_LOG(ERR,
2228                         "unable to map response address to physical memory\n");
2229                 return -ENOMEM;
2230         }
2231         rte_spinlock_init(&bp->hwrm_lock);
2232
2233         return 0;
2234 }
2235
2236 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2237 {
2238         struct bnxt_filter_info *filter;
2239         int rc = 0;
2240
2241         STAILQ_FOREACH(filter, &vnic->filter, next) {
2242                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2243                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2244                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2245                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2246                 else
2247                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2248                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2249                 //if (rc)
2250                         //break;
2251         }
2252         return rc;
2253 }
2254
2255 static int
2256 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2257 {
2258         struct bnxt_filter_info *filter;
2259         struct rte_flow *flow;
2260         int rc = 0;
2261
2262         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2263                 filter = flow->filter;
2264                 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
2265                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2266                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2267                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2268                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2269                 else
2270                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2271
2272                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2273                 rte_free(flow);
2274                 //if (rc)
2275                         //break;
2276         }
2277         return rc;
2278 }
2279
2280 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2281 {
2282         struct bnxt_filter_info *filter;
2283         int rc = 0;
2284
2285         STAILQ_FOREACH(filter, &vnic->filter, next) {
2286                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2287                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2288                                                      filter);
2289                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2290                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2291                                                          filter);
2292                 else
2293                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2294                                                      filter);
2295                 if (rc)
2296                         break;
2297         }
2298         return rc;
2299 }
2300
2301 void bnxt_free_tunnel_ports(struct bnxt *bp)
2302 {
2303         if (bp->vxlan_port_cnt)
2304                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2305                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2306         bp->vxlan_port = 0;
2307         if (bp->geneve_port_cnt)
2308                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2309                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2310         bp->geneve_port = 0;
2311 }
2312
2313 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2314 {
2315         int i, j;
2316
2317         if (bp->vnic_info == NULL)
2318                 return;
2319
2320         /*
2321          * Cleanup VNICs in reverse order, to make sure the L2 filter
2322          * from vnic0 is last to be cleaned up.
2323          */
2324         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2325                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2326
2327                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2328                         PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2329                         return;
2330                 }
2331
2332                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2333
2334                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2335
2336                 if (BNXT_CHIP_THOR(bp)) {
2337                         for (j = 0; j < vnic->num_lb_ctxts; j++) {
2338                                 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2339                                                         vnic->fw_grp_ids[j]);
2340                                 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2341                         }
2342                         vnic->num_lb_ctxts = 0;
2343                 } else {
2344                         bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2345                         vnic->rss_rule = INVALID_HW_RING_ID;
2346                 }
2347
2348                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2349
2350                 bnxt_hwrm_vnic_free(bp, vnic);
2351
2352                 rte_free(vnic->fw_grp_ids);
2353         }
2354         /* Ring resources */
2355         bnxt_free_all_hwrm_rings(bp);
2356         bnxt_free_all_hwrm_ring_grps(bp);
2357         bnxt_free_all_hwrm_stat_ctxs(bp);
2358         bnxt_free_tunnel_ports(bp);
2359 }
2360
2361 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2362 {
2363         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2364
2365         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2366                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2367
2368         switch (conf_link_speed) {
2369         case ETH_LINK_SPEED_10M_HD:
2370         case ETH_LINK_SPEED_100M_HD:
2371                 /* FALLTHROUGH */
2372                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2373         }
2374         return hw_link_duplex;
2375 }
2376
2377 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2378 {
2379         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2380 }
2381
2382 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2383 {
2384         uint16_t eth_link_speed = 0;
2385
2386         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2387                 return ETH_LINK_SPEED_AUTONEG;
2388
2389         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2390         case ETH_LINK_SPEED_100M:
2391         case ETH_LINK_SPEED_100M_HD:
2392                 /* FALLTHROUGH */
2393                 eth_link_speed =
2394                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2395                 break;
2396         case ETH_LINK_SPEED_1G:
2397                 eth_link_speed =
2398                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2399                 break;
2400         case ETH_LINK_SPEED_2_5G:
2401                 eth_link_speed =
2402                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2403                 break;
2404         case ETH_LINK_SPEED_10G:
2405                 eth_link_speed =
2406                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2407                 break;
2408         case ETH_LINK_SPEED_20G:
2409                 eth_link_speed =
2410                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2411                 break;
2412         case ETH_LINK_SPEED_25G:
2413                 eth_link_speed =
2414                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2415                 break;
2416         case ETH_LINK_SPEED_40G:
2417                 eth_link_speed =
2418                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2419                 break;
2420         case ETH_LINK_SPEED_50G:
2421                 eth_link_speed =
2422                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2423                 break;
2424         case ETH_LINK_SPEED_100G:
2425                 eth_link_speed =
2426                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2427                 break;
2428         default:
2429                 PMD_DRV_LOG(ERR,
2430                         "Unsupported link speed %d; default to AUTO\n",
2431                         conf_link_speed);
2432                 break;
2433         }
2434         return eth_link_speed;
2435 }
2436
2437 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2438                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2439                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2440                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2441
2442 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2443 {
2444         uint32_t one_speed;
2445
2446         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2447                 return 0;
2448
2449         if (link_speed & ETH_LINK_SPEED_FIXED) {
2450                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2451
2452                 if (one_speed & (one_speed - 1)) {
2453                         PMD_DRV_LOG(ERR,
2454                                 "Invalid advertised speeds (%u) for port %u\n",
2455                                 link_speed, port_id);
2456                         return -EINVAL;
2457                 }
2458                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2459                         PMD_DRV_LOG(ERR,
2460                                 "Unsupported advertised speed (%u) for port %u\n",
2461                                 link_speed, port_id);
2462                         return -EINVAL;
2463                 }
2464         } else {
2465                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2466                         PMD_DRV_LOG(ERR,
2467                                 "Unsupported advertised speeds (%u) for port %u\n",
2468                                 link_speed, port_id);
2469                         return -EINVAL;
2470                 }
2471         }
2472         return 0;
2473 }
2474
2475 static uint16_t
2476 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2477 {
2478         uint16_t ret = 0;
2479
2480         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2481                 if (bp->link_info.support_speeds)
2482                         return bp->link_info.support_speeds;
2483                 link_speed = BNXT_SUPPORTED_SPEEDS;
2484         }
2485
2486         if (link_speed & ETH_LINK_SPEED_100M)
2487                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2488         if (link_speed & ETH_LINK_SPEED_100M_HD)
2489                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2490         if (link_speed & ETH_LINK_SPEED_1G)
2491                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2492         if (link_speed & ETH_LINK_SPEED_2_5G)
2493                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2494         if (link_speed & ETH_LINK_SPEED_10G)
2495                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2496         if (link_speed & ETH_LINK_SPEED_20G)
2497                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2498         if (link_speed & ETH_LINK_SPEED_25G)
2499                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2500         if (link_speed & ETH_LINK_SPEED_40G)
2501                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2502         if (link_speed & ETH_LINK_SPEED_50G)
2503                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2504         if (link_speed & ETH_LINK_SPEED_100G)
2505                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2506         return ret;
2507 }
2508
2509 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2510 {
2511         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2512
2513         switch (hw_link_speed) {
2514         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2515                 eth_link_speed = ETH_SPEED_NUM_100M;
2516                 break;
2517         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2518                 eth_link_speed = ETH_SPEED_NUM_1G;
2519                 break;
2520         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2521                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2522                 break;
2523         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2524                 eth_link_speed = ETH_SPEED_NUM_10G;
2525                 break;
2526         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2527                 eth_link_speed = ETH_SPEED_NUM_20G;
2528                 break;
2529         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2530                 eth_link_speed = ETH_SPEED_NUM_25G;
2531                 break;
2532         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2533                 eth_link_speed = ETH_SPEED_NUM_40G;
2534                 break;
2535         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2536                 eth_link_speed = ETH_SPEED_NUM_50G;
2537                 break;
2538         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2539                 eth_link_speed = ETH_SPEED_NUM_100G;
2540                 break;
2541         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2542         default:
2543                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2544                         hw_link_speed);
2545                 break;
2546         }
2547         return eth_link_speed;
2548 }
2549
2550 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2551 {
2552         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2553
2554         switch (hw_link_duplex) {
2555         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2556         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2557                 /* FALLTHROUGH */
2558                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2559                 break;
2560         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2561                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2562                 break;
2563         default:
2564                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2565                         hw_link_duplex);
2566                 break;
2567         }
2568         return eth_link_duplex;
2569 }
2570
2571 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2572 {
2573         int rc = 0;
2574         struct bnxt_link_info *link_info = &bp->link_info;
2575
2576         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2577         if (rc) {
2578                 PMD_DRV_LOG(ERR,
2579                         "Get link config failed with rc %d\n", rc);
2580                 goto exit;
2581         }
2582         if (link_info->link_speed)
2583                 link->link_speed =
2584                         bnxt_parse_hw_link_speed(link_info->link_speed);
2585         else
2586                 link->link_speed = ETH_SPEED_NUM_NONE;
2587         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2588         link->link_status = link_info->link_up;
2589         link->link_autoneg = link_info->auto_mode ==
2590                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2591                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2592 exit:
2593         return rc;
2594 }
2595
2596 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2597 {
2598         int rc = 0;
2599         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2600         struct bnxt_link_info link_req;
2601         uint16_t speed, autoneg;
2602
2603         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2604                 return 0;
2605
2606         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2607                         bp->eth_dev->data->port_id);
2608         if (rc)
2609                 goto error;
2610
2611         memset(&link_req, 0, sizeof(link_req));
2612         link_req.link_up = link_up;
2613         if (!link_up)
2614                 goto port_phy_cfg;
2615
2616         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2617         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2618         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2619         /* Autoneg can be done only when the FW allows */
2620         if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2621                                 bp->link_info.force_link_speed)) {
2622                 link_req.phy_flags |=
2623                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2624                 link_req.auto_link_speed_mask =
2625                         bnxt_parse_eth_link_speed_mask(bp,
2626                                                        dev_conf->link_speeds);
2627         } else {
2628                 if (bp->link_info.phy_type ==
2629                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2630                     bp->link_info.phy_type ==
2631                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2632                     bp->link_info.media_type ==
2633                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2634                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2635                         return -EINVAL;
2636                 }
2637
2638                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2639                 /* If user wants a particular speed try that first. */
2640                 if (speed)
2641                         link_req.link_speed = speed;
2642                 else if (bp->link_info.force_link_speed)
2643                         link_req.link_speed = bp->link_info.force_link_speed;
2644                 else
2645                         link_req.link_speed = bp->link_info.auto_link_speed;
2646         }
2647         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2648         link_req.auto_pause = bp->link_info.auto_pause;
2649         link_req.force_pause = bp->link_info.force_pause;
2650
2651 port_phy_cfg:
2652         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2653         if (rc) {
2654                 PMD_DRV_LOG(ERR,
2655                         "Set link config failed with rc %d\n", rc);
2656         }
2657
2658 error:
2659         return rc;
2660 }
2661
2662 /* JIRA 22088 */
2663 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2664 {
2665         struct hwrm_func_qcfg_input req = {0};
2666         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2667         uint16_t flags;
2668         int rc = 0;
2669
2670         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2671         req.fid = rte_cpu_to_le_16(0xffff);
2672
2673         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2674
2675         HWRM_CHECK_RESULT();
2676
2677         /* Hard Coded.. 0xfff VLAN ID mask */
2678         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2679         flags = rte_le_to_cpu_16(resp->flags);
2680         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2681                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2682
2683         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2684                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2685                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2686         }
2687
2688         if (mtu)
2689                 *mtu = resp->mtu;
2690
2691         switch (resp->port_partition_type) {
2692         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2693         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2694         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2695                 /* FALLTHROUGH */
2696                 bp->port_partition_type = resp->port_partition_type;
2697                 break;
2698         default:
2699                 bp->port_partition_type = 0;
2700                 break;
2701         }
2702
2703         HWRM_UNLOCK();
2704
2705         return rc;
2706 }
2707
2708 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2709                                    struct hwrm_func_qcaps_output *qcaps)
2710 {
2711         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2712         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2713                sizeof(qcaps->mac_address));
2714         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2715         qcaps->max_rx_rings = fcfg->num_rx_rings;
2716         qcaps->max_tx_rings = fcfg->num_tx_rings;
2717         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2718         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2719         qcaps->max_vfs = 0;
2720         qcaps->first_vf_id = 0;
2721         qcaps->max_vnics = fcfg->num_vnics;
2722         qcaps->max_decap_records = 0;
2723         qcaps->max_encap_records = 0;
2724         qcaps->max_tx_wm_flows = 0;
2725         qcaps->max_tx_em_flows = 0;
2726         qcaps->max_rx_wm_flows = 0;
2727         qcaps->max_rx_em_flows = 0;
2728         qcaps->max_flow_id = 0;
2729         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2730         qcaps->max_sp_tx_rings = 0;
2731         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2732 }
2733
2734 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2735 {
2736         struct hwrm_func_cfg_input req = {0};
2737         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2738         uint32_t enables;
2739         int rc;
2740
2741         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2742                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2743                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2744                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2745                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2746                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2747                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2748                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2749                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2750
2751         if (BNXT_HAS_RING_GRPS(bp)) {
2752                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2753                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2754         } else if (BNXT_HAS_NQ(bp)) {
2755                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2756                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2757         }
2758
2759         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2760         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2761         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2762                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2763                                    BNXT_NUM_VLANS);
2764         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2765         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2766         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2767         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2768         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2769         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2770         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2771         req.fid = rte_cpu_to_le_16(0xffff);
2772         req.enables = rte_cpu_to_le_32(enables);
2773
2774         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2775
2776         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2777
2778         HWRM_CHECK_RESULT();
2779         HWRM_UNLOCK();
2780
2781         return rc;
2782 }
2783
2784 static void populate_vf_func_cfg_req(struct bnxt *bp,
2785                                      struct hwrm_func_cfg_input *req,
2786                                      int num_vfs)
2787 {
2788         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2789                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2790                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2791                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2792                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2793                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2794                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2795                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2796                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2797                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2798
2799         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2800                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2801                                     BNXT_NUM_VLANS);
2802         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2803                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2804                                     BNXT_NUM_VLANS);
2805         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2806                                                 (num_vfs + 1));
2807         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2808         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2809                                                (num_vfs + 1));
2810         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2811         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2812         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2813         /* TODO: For now, do not support VMDq/RFS on VFs. */
2814         req->num_vnics = rte_cpu_to_le_16(1);
2815         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2816                                                  (num_vfs + 1));
2817 }
2818
2819 static void add_random_mac_if_needed(struct bnxt *bp,
2820                                      struct hwrm_func_cfg_input *cfg_req,
2821                                      int vf)
2822 {
2823         struct rte_ether_addr mac;
2824
2825         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2826                 return;
2827
2828         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2829                 cfg_req->enables |=
2830                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2831                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2832                 bp->pf.vf_info[vf].random_mac = true;
2833         } else {
2834                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2835                         RTE_ETHER_ADDR_LEN);
2836         }
2837 }
2838
2839 static void reserve_resources_from_vf(struct bnxt *bp,
2840                                       struct hwrm_func_cfg_input *cfg_req,
2841                                       int vf)
2842 {
2843         struct hwrm_func_qcaps_input req = {0};
2844         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2845         int rc;
2846
2847         /* Get the actual allocated values now */
2848         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2849         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2850         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2851
2852         if (rc) {
2853                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2854                 copy_func_cfg_to_qcaps(cfg_req, resp);
2855         } else if (resp->error_code) {
2856                 rc = rte_le_to_cpu_16(resp->error_code);
2857                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2858                 copy_func_cfg_to_qcaps(cfg_req, resp);
2859         }
2860
2861         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2862         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2863         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2864         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2865         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2866         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2867         /*
2868          * TODO: While not supporting VMDq with VFs, max_vnics is always
2869          * forced to 1 in this case
2870          */
2871         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2872         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2873
2874         HWRM_UNLOCK();
2875 }
2876
2877 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2878 {
2879         struct hwrm_func_qcfg_input req = {0};
2880         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2881         int rc;
2882
2883         /* Check for zero MAC address */
2884         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2885         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2886         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2887         if (rc) {
2888                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2889                 return -1;
2890         } else if (resp->error_code) {
2891                 rc = rte_le_to_cpu_16(resp->error_code);
2892                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2893                 return -1;
2894         }
2895         rc = rte_le_to_cpu_16(resp->vlan);
2896
2897         HWRM_UNLOCK();
2898
2899         return rc;
2900 }
2901
2902 static int update_pf_resource_max(struct bnxt *bp)
2903 {
2904         struct hwrm_func_qcfg_input req = {0};
2905         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2906         int rc;
2907
2908         /* And copy the allocated numbers into the pf struct */
2909         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2910         req.fid = rte_cpu_to_le_16(0xffff);
2911         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2912         HWRM_CHECK_RESULT();
2913
2914         /* Only TX ring value reflects actual allocation? TODO */
2915         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2916         bp->pf.evb_mode = resp->evb_mode;
2917
2918         HWRM_UNLOCK();
2919
2920         return rc;
2921 }
2922
2923 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2924 {
2925         int rc;
2926
2927         if (!BNXT_PF(bp)) {
2928                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2929                 return -EINVAL;
2930         }
2931
2932         rc = bnxt_hwrm_func_qcaps(bp);
2933         if (rc)
2934                 return rc;
2935
2936         bp->pf.func_cfg_flags &=
2937                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2938                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2939         bp->pf.func_cfg_flags |=
2940                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2941         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2942         rc = __bnxt_hwrm_func_qcaps(bp);
2943         return rc;
2944 }
2945
2946 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2947 {
2948         struct hwrm_func_cfg_input req = {0};
2949         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2950         int i;
2951         size_t sz;
2952         int rc = 0;
2953         size_t req_buf_sz;
2954
2955         if (!BNXT_PF(bp)) {
2956                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2957                 return -EINVAL;
2958         }
2959
2960         rc = bnxt_hwrm_func_qcaps(bp);
2961
2962         if (rc)
2963                 return rc;
2964
2965         bp->pf.active_vfs = num_vfs;
2966
2967         /*
2968          * First, configure the PF to only use one TX ring.  This ensures that
2969          * there are enough rings for all VFs.
2970          *
2971          * If we don't do this, when we call func_alloc() later, we will lock
2972          * extra rings to the PF that won't be available during func_cfg() of
2973          * the VFs.
2974          *
2975          * This has been fixed with firmware versions above 20.6.54
2976          */
2977         bp->pf.func_cfg_flags &=
2978                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2979                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2980         bp->pf.func_cfg_flags |=
2981                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2982         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2983         if (rc)
2984                 return rc;
2985
2986         /*
2987          * Now, create and register a buffer to hold forwarded VF requests
2988          */
2989         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2990         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2991                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2992         if (bp->pf.vf_req_buf == NULL) {
2993                 rc = -ENOMEM;
2994                 goto error_free;
2995         }
2996         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2997                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2998         for (i = 0; i < num_vfs; i++)
2999                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3000                                         (i * HWRM_MAX_REQ_LEN);
3001
3002         rc = bnxt_hwrm_func_buf_rgtr(bp);
3003         if (rc)
3004                 goto error_free;
3005
3006         populate_vf_func_cfg_req(bp, &req, num_vfs);
3007
3008         bp->pf.active_vfs = 0;
3009         for (i = 0; i < num_vfs; i++) {
3010                 add_random_mac_if_needed(bp, &req, i);
3011
3012                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3013                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3014                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3015                 rc = bnxt_hwrm_send_message(bp,
3016                                             &req,
3017                                             sizeof(req),
3018                                             BNXT_USE_CHIMP_MB);
3019
3020                 /* Clear enable flag for next pass */
3021                 req.enables &= ~rte_cpu_to_le_32(
3022                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3023
3024                 if (rc || resp->error_code) {
3025                         PMD_DRV_LOG(ERR,
3026                                 "Failed to initizlie VF %d\n", i);
3027                         PMD_DRV_LOG(ERR,
3028                                 "Not all VFs available. (%d, %d)\n",
3029                                 rc, resp->error_code);
3030                         HWRM_UNLOCK();
3031                         break;
3032                 }
3033
3034                 HWRM_UNLOCK();
3035
3036                 reserve_resources_from_vf(bp, &req, i);
3037                 bp->pf.active_vfs++;
3038                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3039         }
3040
3041         /*
3042          * Now configure the PF to use "the rest" of the resources
3043          * We're using STD_TX_RING_MODE here though which will limit the TX
3044          * rings.  This will allow QoS to function properly.  Not setting this
3045          * will cause PF rings to break bandwidth settings.
3046          */
3047         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3048         if (rc)
3049                 goto error_free;
3050
3051         rc = update_pf_resource_max(bp);
3052         if (rc)
3053                 goto error_free;
3054
3055         return rc;
3056
3057 error_free:
3058         bnxt_hwrm_func_buf_unrgtr(bp);
3059         return rc;
3060 }
3061
3062 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3063 {
3064         struct hwrm_func_cfg_input req = {0};
3065         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3066         int rc;
3067
3068         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3069
3070         req.fid = rte_cpu_to_le_16(0xffff);
3071         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3072         req.evb_mode = bp->pf.evb_mode;
3073
3074         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3075         HWRM_CHECK_RESULT();
3076         HWRM_UNLOCK();
3077
3078         return rc;
3079 }
3080
3081 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3082                                 uint8_t tunnel_type)
3083 {
3084         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3085         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3086         int rc = 0;
3087
3088         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3089         req.tunnel_type = tunnel_type;
3090         req.tunnel_dst_port_val = port;
3091         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3092         HWRM_CHECK_RESULT();
3093
3094         switch (tunnel_type) {
3095         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3096                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3097                 bp->vxlan_port = port;
3098                 break;
3099         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3100                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3101                 bp->geneve_port = port;
3102                 break;
3103         default:
3104                 break;
3105         }
3106
3107         HWRM_UNLOCK();
3108
3109         return rc;
3110 }
3111
3112 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3113                                 uint8_t tunnel_type)
3114 {
3115         struct hwrm_tunnel_dst_port_free_input req = {0};
3116         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3117         int rc = 0;
3118
3119         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3120
3121         req.tunnel_type = tunnel_type;
3122         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3123         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3124
3125         HWRM_CHECK_RESULT();
3126         HWRM_UNLOCK();
3127
3128         return rc;
3129 }
3130
3131 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3132                                         uint32_t flags)
3133 {
3134         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3135         struct hwrm_func_cfg_input req = {0};
3136         int rc;
3137
3138         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3139
3140         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3141         req.flags = rte_cpu_to_le_32(flags);
3142         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3143
3144         HWRM_CHECK_RESULT();
3145         HWRM_UNLOCK();
3146
3147         return rc;
3148 }
3149
3150 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3151 {
3152         uint32_t *flag = flagp;
3153
3154         vnic->flags = *flag;
3155 }
3156
3157 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3158 {
3159         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3160 }
3161
3162 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3163 {
3164         int rc = 0;
3165         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3166         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3167
3168         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3169
3170         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3171         req.req_buf_page_size = rte_cpu_to_le_16(
3172                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3173         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3174         req.req_buf_page_addr0 =
3175                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3176         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3177                 PMD_DRV_LOG(ERR,
3178                         "unable to map buffer address to physical memory\n");
3179                 return -ENOMEM;
3180         }
3181
3182         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3183
3184         HWRM_CHECK_RESULT();
3185         HWRM_UNLOCK();
3186
3187         return rc;
3188 }
3189
3190 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3191 {
3192         int rc = 0;
3193         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3194         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3195
3196         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3197                 return 0;
3198
3199         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3200
3201         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3202
3203         HWRM_CHECK_RESULT();
3204         HWRM_UNLOCK();
3205
3206         return rc;
3207 }
3208
3209 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3210 {
3211         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3212         struct hwrm_func_cfg_input req = {0};
3213         int rc;
3214
3215         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3216
3217         req.fid = rte_cpu_to_le_16(0xffff);
3218         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3219         req.enables = rte_cpu_to_le_32(
3220                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3221         req.async_event_cr = rte_cpu_to_le_16(
3222                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3223         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3224
3225         HWRM_CHECK_RESULT();
3226         HWRM_UNLOCK();
3227
3228         return rc;
3229 }
3230
3231 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3232 {
3233         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3234         struct hwrm_func_vf_cfg_input req = {0};
3235         int rc;
3236
3237         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3238
3239         req.enables = rte_cpu_to_le_32(
3240                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3241         req.async_event_cr = rte_cpu_to_le_16(
3242                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3243         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3244
3245         HWRM_CHECK_RESULT();
3246         HWRM_UNLOCK();
3247
3248         return rc;
3249 }
3250
3251 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3252 {
3253         struct hwrm_func_cfg_input req = {0};
3254         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3255         uint16_t dflt_vlan, fid;
3256         uint32_t func_cfg_flags;
3257         int rc = 0;
3258
3259         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3260
3261         if (is_vf) {
3262                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3263                 fid = bp->pf.vf_info[vf].fid;
3264                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3265         } else {
3266                 fid = rte_cpu_to_le_16(0xffff);
3267                 func_cfg_flags = bp->pf.func_cfg_flags;
3268                 dflt_vlan = bp->vlan;
3269         }
3270
3271         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3272         req.fid = rte_cpu_to_le_16(fid);
3273         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3274         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3275
3276         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3277
3278         HWRM_CHECK_RESULT();
3279         HWRM_UNLOCK();
3280
3281         return rc;
3282 }
3283
3284 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3285                         uint16_t max_bw, uint16_t enables)
3286 {
3287         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3288         struct hwrm_func_cfg_input req = {0};
3289         int rc;
3290
3291         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3292
3293         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3294         req.enables |= rte_cpu_to_le_32(enables);
3295         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3296         req.max_bw = rte_cpu_to_le_32(max_bw);
3297         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3298
3299         HWRM_CHECK_RESULT();
3300         HWRM_UNLOCK();
3301
3302         return rc;
3303 }
3304
3305 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3306 {
3307         struct hwrm_func_cfg_input req = {0};
3308         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3309         int rc = 0;
3310
3311         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3312
3313         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3314         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3315         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3316         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3317
3318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3319
3320         HWRM_CHECK_RESULT();
3321         HWRM_UNLOCK();
3322
3323         return rc;
3324 }
3325
3326 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3327 {
3328         int rc;
3329
3330         if (BNXT_PF(bp))
3331                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3332         else
3333                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3334
3335         return rc;
3336 }
3337
3338 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3339                               void *encaped, size_t ec_size)
3340 {
3341         int rc = 0;
3342         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3343         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3344
3345         if (ec_size > sizeof(req.encap_request))
3346                 return -1;
3347
3348         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3349
3350         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3351         memcpy(req.encap_request, encaped, ec_size);
3352
3353         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3354
3355         HWRM_CHECK_RESULT();
3356         HWRM_UNLOCK();
3357
3358         return rc;
3359 }
3360
3361 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3362                                        struct rte_ether_addr *mac)
3363 {
3364         struct hwrm_func_qcfg_input req = {0};
3365         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3366         int rc;
3367
3368         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3369
3370         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3371         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3372
3373         HWRM_CHECK_RESULT();
3374
3375         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3376
3377         HWRM_UNLOCK();
3378
3379         return rc;
3380 }
3381
3382 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3383                             void *encaped, size_t ec_size)
3384 {
3385         int rc = 0;
3386         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3387         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3388
3389         if (ec_size > sizeof(req.encap_request))
3390                 return -1;
3391
3392         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3393
3394         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3395         memcpy(req.encap_request, encaped, ec_size);
3396
3397         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3398
3399         HWRM_CHECK_RESULT();
3400         HWRM_UNLOCK();
3401
3402         return rc;
3403 }
3404
3405 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3406                          struct rte_eth_stats *stats, uint8_t rx)
3407 {
3408         int rc = 0;
3409         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3410         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3411
3412         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3413
3414         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3415
3416         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3417
3418         HWRM_CHECK_RESULT();
3419
3420         if (rx) {
3421                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3422                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3423                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3424                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3425                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3426                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3427                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3428                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3429         } else {
3430                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3431                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3432                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3433                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3434                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3435                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3436         }
3437
3438
3439         HWRM_UNLOCK();
3440
3441         return rc;
3442 }
3443
3444 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3445 {
3446         struct hwrm_port_qstats_input req = {0};
3447         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3448         struct bnxt_pf_info *pf = &bp->pf;
3449         int rc;
3450
3451         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3452
3453         req.port_id = rte_cpu_to_le_16(pf->port_id);
3454         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3455         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3456         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3457
3458         HWRM_CHECK_RESULT();
3459         HWRM_UNLOCK();
3460
3461         return rc;
3462 }
3463
3464 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3465 {
3466         struct hwrm_port_clr_stats_input req = {0};
3467         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3468         struct bnxt_pf_info *pf = &bp->pf;
3469         int rc;
3470
3471         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3472         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3473             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3474                 return 0;
3475
3476         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3477
3478         req.port_id = rte_cpu_to_le_16(pf->port_id);
3479         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3480
3481         HWRM_CHECK_RESULT();
3482         HWRM_UNLOCK();
3483
3484         return rc;
3485 }
3486
3487 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3488 {
3489         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3490         struct hwrm_port_led_qcaps_input req = {0};
3491         int rc;
3492
3493         if (BNXT_VF(bp))
3494                 return 0;
3495
3496         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3497         req.port_id = bp->pf.port_id;
3498         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3499
3500         HWRM_CHECK_RESULT();
3501
3502         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3503                 unsigned int i;
3504
3505                 bp->num_leds = resp->num_leds;
3506                 memcpy(bp->leds, &resp->led0_id,
3507                         sizeof(bp->leds[0]) * bp->num_leds);
3508                 for (i = 0; i < bp->num_leds; i++) {
3509                         struct bnxt_led_info *led = &bp->leds[i];
3510
3511                         uint16_t caps = led->led_state_caps;
3512
3513                         if (!led->led_group_id ||
3514                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3515                                 bp->num_leds = 0;
3516                                 break;
3517                         }
3518                 }
3519         }
3520
3521         HWRM_UNLOCK();
3522
3523         return rc;
3524 }
3525
3526 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3527 {
3528         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3529         struct hwrm_port_led_cfg_input req = {0};
3530         struct bnxt_led_cfg *led_cfg;
3531         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3532         uint16_t duration = 0;
3533         int rc, i;
3534
3535         if (!bp->num_leds || BNXT_VF(bp))
3536                 return -EOPNOTSUPP;
3537
3538         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3539
3540         if (led_on) {
3541                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3542                 duration = rte_cpu_to_le_16(500);
3543         }
3544         req.port_id = bp->pf.port_id;
3545         req.num_leds = bp->num_leds;
3546         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3547         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3548                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3549                 led_cfg->led_id = bp->leds[i].led_id;
3550                 led_cfg->led_state = led_state;
3551                 led_cfg->led_blink_on = duration;
3552                 led_cfg->led_blink_off = duration;
3553                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3554         }
3555
3556         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3557
3558         HWRM_CHECK_RESULT();
3559         HWRM_UNLOCK();
3560
3561         return rc;
3562 }
3563
3564 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3565                                uint32_t *length)
3566 {
3567         int rc;
3568         struct hwrm_nvm_get_dir_info_input req = {0};
3569         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3570
3571         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3572
3573         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3574
3575         HWRM_CHECK_RESULT();
3576
3577         *entries = rte_le_to_cpu_32(resp->entries);
3578         *length = rte_le_to_cpu_32(resp->entry_length);
3579
3580         HWRM_UNLOCK();
3581         return rc;
3582 }
3583
3584 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3585 {
3586         int rc;
3587         uint32_t dir_entries;
3588         uint32_t entry_length;
3589         uint8_t *buf;
3590         size_t buflen;
3591         rte_iova_t dma_handle;
3592         struct hwrm_nvm_get_dir_entries_input req = {0};
3593         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3594
3595         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3596         if (rc != 0)
3597                 return rc;
3598
3599         *data++ = dir_entries;
3600         *data++ = entry_length;
3601         len -= 2;
3602         memset(data, 0xff, len);
3603
3604         buflen = dir_entries * entry_length;
3605         buf = rte_malloc("nvm_dir", buflen, 0);
3606         rte_mem_lock_page(buf);
3607         if (buf == NULL)
3608                 return -ENOMEM;
3609         dma_handle = rte_mem_virt2iova(buf);
3610         if (dma_handle == RTE_BAD_IOVA) {
3611                 PMD_DRV_LOG(ERR,
3612                         "unable to map response address to physical memory\n");
3613                 return -ENOMEM;
3614         }
3615         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3616         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3617         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3618
3619         if (rc == 0)
3620                 memcpy(data, buf, len > buflen ? buflen : len);
3621
3622         rte_free(buf);
3623         HWRM_CHECK_RESULT();
3624         HWRM_UNLOCK();
3625
3626         return rc;
3627 }
3628
3629 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3630                              uint32_t offset, uint32_t length,
3631                              uint8_t *data)
3632 {
3633         int rc;
3634         uint8_t *buf;
3635         rte_iova_t dma_handle;
3636         struct hwrm_nvm_read_input req = {0};
3637         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3638
3639         buf = rte_malloc("nvm_item", length, 0);
3640         rte_mem_lock_page(buf);
3641         if (!buf)
3642                 return -ENOMEM;
3643
3644         dma_handle = rte_mem_virt2iova(buf);
3645         if (dma_handle == RTE_BAD_IOVA) {
3646                 PMD_DRV_LOG(ERR,
3647                         "unable to map response address to physical memory\n");
3648                 return -ENOMEM;
3649         }
3650         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3651         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3652         req.dir_idx = rte_cpu_to_le_16(index);
3653         req.offset = rte_cpu_to_le_32(offset);
3654         req.len = rte_cpu_to_le_32(length);
3655         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3656         if (rc == 0)
3657                 memcpy(data, buf, length);
3658
3659         rte_free(buf);
3660         HWRM_CHECK_RESULT();
3661         HWRM_UNLOCK();
3662
3663         return rc;
3664 }
3665
3666 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3667 {
3668         int rc;
3669         struct hwrm_nvm_erase_dir_entry_input req = {0};
3670         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3671
3672         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3673         req.dir_idx = rte_cpu_to_le_16(index);
3674         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3675         HWRM_CHECK_RESULT();
3676         HWRM_UNLOCK();
3677
3678         return rc;
3679 }
3680
3681
3682 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3683                           uint16_t dir_ordinal, uint16_t dir_ext,
3684                           uint16_t dir_attr, const uint8_t *data,
3685                           size_t data_len)
3686 {
3687         int rc;
3688         struct hwrm_nvm_write_input req = {0};
3689         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3690         rte_iova_t dma_handle;
3691         uint8_t *buf;
3692
3693         buf = rte_malloc("nvm_write", data_len, 0);
3694         rte_mem_lock_page(buf);
3695         if (!buf)
3696                 return -ENOMEM;
3697
3698         dma_handle = rte_mem_virt2iova(buf);
3699         if (dma_handle == RTE_BAD_IOVA) {
3700                 PMD_DRV_LOG(ERR,
3701                         "unable to map response address to physical memory\n");
3702                 return -ENOMEM;
3703         }
3704         memcpy(buf, data, data_len);
3705
3706         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3707
3708         req.dir_type = rte_cpu_to_le_16(dir_type);
3709         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3710         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3711         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3712         req.dir_data_length = rte_cpu_to_le_32(data_len);
3713         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3714
3715         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3716
3717         rte_free(buf);
3718         HWRM_CHECK_RESULT();
3719         HWRM_UNLOCK();
3720
3721         return rc;
3722 }
3723
3724 static void
3725 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3726 {
3727         uint32_t *count = cbdata;
3728
3729         *count = *count + 1;
3730 }
3731
3732 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3733                                      struct bnxt_vnic_info *vnic __rte_unused)
3734 {
3735         return 0;
3736 }
3737
3738 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3739 {
3740         uint32_t count = 0;
3741
3742         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3743             &count, bnxt_vnic_count_hwrm_stub);
3744
3745         return count;
3746 }
3747
3748 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3749                                         uint16_t *vnic_ids)
3750 {
3751         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3752         struct hwrm_func_vf_vnic_ids_query_output *resp =
3753                                                 bp->hwrm_cmd_resp_addr;
3754         int rc;
3755
3756         /* First query all VNIC ids */
3757         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3758
3759         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3760         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3761         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3762
3763         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3764                 HWRM_UNLOCK();
3765                 PMD_DRV_LOG(ERR,
3766                 "unable to map VNIC ID table address to physical memory\n");
3767                 return -ENOMEM;
3768         }
3769         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3770         HWRM_CHECK_RESULT();
3771         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3772
3773         HWRM_UNLOCK();
3774
3775         return rc;
3776 }
3777
3778 /*
3779  * This function queries the VNIC IDs  for a specified VF. It then calls
3780  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3781  * Then it calls the hwrm_cb function to program this new vnic configuration.
3782  */
3783 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3784         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3785         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3786 {
3787         struct bnxt_vnic_info vnic;
3788         int rc = 0;
3789         int i, num_vnic_ids;
3790         uint16_t *vnic_ids;
3791         size_t vnic_id_sz;
3792         size_t sz;
3793
3794         /* First query all VNIC ids */
3795         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3796         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3797                         RTE_CACHE_LINE_SIZE);
3798         if (vnic_ids == NULL)
3799                 return -ENOMEM;
3800
3801         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3802                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3803
3804         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3805
3806         if (num_vnic_ids < 0)
3807                 return num_vnic_ids;
3808
3809         /* Retrieve VNIC, update bd_stall then update */
3810
3811         for (i = 0; i < num_vnic_ids; i++) {
3812                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3813                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3814                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3815                 if (rc)
3816                         break;
3817                 if (vnic.mru <= 4)      /* Indicates unallocated */
3818                         continue;
3819
3820                 vnic_cb(&vnic, cbdata);
3821
3822                 rc = hwrm_cb(bp, &vnic);
3823                 if (rc)
3824                         break;
3825         }
3826
3827         rte_free(vnic_ids);
3828
3829         return rc;
3830 }
3831
3832 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3833                                               bool on)
3834 {
3835         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3836         struct hwrm_func_cfg_input req = {0};
3837         int rc;
3838
3839         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3840
3841         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3842         req.enables |= rte_cpu_to_le_32(
3843                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3844         req.vlan_antispoof_mode = on ?
3845                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3846                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3847         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3848
3849         HWRM_CHECK_RESULT();
3850         HWRM_UNLOCK();
3851
3852         return rc;
3853 }
3854
3855 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3856 {
3857         struct bnxt_vnic_info vnic;
3858         uint16_t *vnic_ids;
3859         size_t vnic_id_sz;
3860         int num_vnic_ids, i;
3861         size_t sz;
3862         int rc;
3863
3864         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3865         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3866                         RTE_CACHE_LINE_SIZE);
3867         if (vnic_ids == NULL)
3868                 return -ENOMEM;
3869
3870         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3871                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3872
3873         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3874         if (rc <= 0)
3875                 goto exit;
3876         num_vnic_ids = rc;
3877
3878         /*
3879          * Loop through to find the default VNIC ID.
3880          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3881          * by sending the hwrm_func_qcfg command to the firmware.
3882          */
3883         for (i = 0; i < num_vnic_ids; i++) {
3884                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3885                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3886                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3887                                         bp->pf.first_vf_id + vf);
3888                 if (rc)
3889                         goto exit;
3890                 if (vnic.func_default) {
3891                         rte_free(vnic_ids);
3892                         return vnic.fw_vnic_id;
3893                 }
3894         }
3895         /* Could not find a default VNIC. */
3896         PMD_DRV_LOG(ERR, "No default VNIC\n");
3897 exit:
3898         rte_free(vnic_ids);
3899         return rc;
3900 }
3901
3902 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3903                          uint16_t dst_id,
3904                          struct bnxt_filter_info *filter)
3905 {
3906         int rc = 0;
3907         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3908         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3909         uint32_t enables = 0;
3910
3911         if (filter->fw_em_filter_id != UINT64_MAX)
3912                 bnxt_hwrm_clear_em_filter(bp, filter);
3913
3914         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3915
3916         req.flags = rte_cpu_to_le_32(filter->flags);
3917
3918         enables = filter->enables |
3919               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3920         req.dst_id = rte_cpu_to_le_16(dst_id);
3921
3922         if (filter->ip_addr_type) {
3923                 req.ip_addr_type = filter->ip_addr_type;
3924                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3925         }
3926         if (enables &
3927             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3928                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3929         if (enables &
3930             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3931                 memcpy(req.src_macaddr, filter->src_macaddr,
3932                        RTE_ETHER_ADDR_LEN);
3933         if (enables &
3934             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3935                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3936                        RTE_ETHER_ADDR_LEN);
3937         if (enables &
3938             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3939                 req.ovlan_vid = filter->l2_ovlan;
3940         if (enables &
3941             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3942                 req.ivlan_vid = filter->l2_ivlan;
3943         if (enables &
3944             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3945                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3946         if (enables &
3947             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3948                 req.ip_protocol = filter->ip_protocol;
3949         if (enables &
3950             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3951                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3952         if (enables &
3953             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3954                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3955         if (enables &
3956             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3957                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3958         if (enables &
3959             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3960                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3961         if (enables &
3962             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3963                 req.mirror_vnic_id = filter->mirror_vnic_id;
3964
3965         req.enables = rte_cpu_to_le_32(enables);
3966
3967         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3968
3969         HWRM_CHECK_RESULT();
3970
3971         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3972         HWRM_UNLOCK();
3973
3974         return rc;
3975 }
3976
3977 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3978 {
3979         int rc = 0;
3980         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3981         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3982
3983         if (filter->fw_em_filter_id == UINT64_MAX)
3984                 return 0;
3985
3986         PMD_DRV_LOG(ERR, "Clear EM filter\n");
3987         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
3988
3989         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3990
3991         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3992
3993         HWRM_CHECK_RESULT();
3994         HWRM_UNLOCK();
3995
3996         filter->fw_em_filter_id = UINT64_MAX;
3997         filter->fw_l2_filter_id = UINT64_MAX;
3998
3999         return 0;
4000 }
4001
4002 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4003                          uint16_t dst_id,
4004                          struct bnxt_filter_info *filter)
4005 {
4006         int rc = 0;
4007         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4008         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4009                                                 bp->hwrm_cmd_resp_addr;
4010         uint32_t enables = 0;
4011
4012         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4013                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4014
4015         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4016
4017         req.flags = rte_cpu_to_le_32(filter->flags);
4018
4019         enables = filter->enables |
4020               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4021         req.dst_id = rte_cpu_to_le_16(dst_id);
4022
4023
4024         if (filter->ip_addr_type) {
4025                 req.ip_addr_type = filter->ip_addr_type;
4026                 enables |=
4027                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4028         }
4029         if (enables &
4030             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4031                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4032         if (enables &
4033             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4034                 memcpy(req.src_macaddr, filter->src_macaddr,
4035                        RTE_ETHER_ADDR_LEN);
4036         //if (enables &
4037             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4038                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4039                        //RTE_ETHER_ADDR_LEN);
4040         if (enables &
4041             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4042                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4043         if (enables &
4044             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4045                 req.ip_protocol = filter->ip_protocol;
4046         if (enables &
4047             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4048                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4049         if (enables &
4050             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4051                 req.src_ipaddr_mask[0] =
4052                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4053         if (enables &
4054             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4055                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4056         if (enables &
4057             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4058                 req.dst_ipaddr_mask[0] =
4059                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4060         if (enables &
4061             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4062                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4063         if (enables &
4064             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4065                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4066         if (enables &
4067             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4068                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4069         if (enables &
4070             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4071                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4072         if (enables &
4073             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4074                 req.mirror_vnic_id = filter->mirror_vnic_id;
4075
4076         req.enables = rte_cpu_to_le_32(enables);
4077
4078         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4079
4080         HWRM_CHECK_RESULT();
4081
4082         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4083         HWRM_UNLOCK();
4084
4085         return rc;
4086 }
4087
4088 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4089                                 struct bnxt_filter_info *filter)
4090 {
4091         int rc = 0;
4092         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4093         struct hwrm_cfa_ntuple_filter_free_output *resp =
4094                                                 bp->hwrm_cmd_resp_addr;
4095
4096         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4097                 return 0;
4098
4099         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4100
4101         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4102
4103         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4104
4105         HWRM_CHECK_RESULT();
4106         HWRM_UNLOCK();
4107
4108         filter->fw_ntuple_filter_id = UINT64_MAX;
4109
4110         return 0;
4111 }
4112
4113 static int
4114 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4115 {
4116         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4117         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4118         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4119         int nr_ctxs = bp->max_ring_grps;
4120         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4121         uint16_t *ring_tbl = vnic->rss_table;
4122         int max_rings = bp->rx_nr_rings;
4123         int i, j, k, cnt;
4124         int rc = 0;
4125
4126         for (i = 0, k = 0; i < nr_ctxs; i++) {
4127                 struct bnxt_rx_ring_info *rxr;
4128                 struct bnxt_cp_ring_info *cpr;
4129
4130                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4131
4132                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4133                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4134                 req.hash_mode_flags = vnic->hash_mode;
4135
4136                 req.ring_grp_tbl_addr =
4137                     rte_cpu_to_le_64(vnic->rss_table_dma_addr);
4138                 req.hash_key_tbl_addr =
4139                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4140
4141                 req.ring_table_pair_index = i;
4142                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4143
4144                 for (j = 0; j < 64; j++) {
4145                         uint16_t ring_id;
4146
4147                         /* Find next active ring. */
4148                         for (cnt = 0; cnt < max_rings; cnt++) {
4149                                 if (rx_queue_state[k] !=
4150                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4151                                         break;
4152                                 if (++k == max_rings)
4153                                         k = 0;
4154                         }
4155
4156                         /* Return if no rings are active. */
4157                         if (cnt == max_rings)
4158                                 return 0;
4159
4160                         /* Add rx/cp ring pair to RSS table. */
4161                         rxr = rxqs[k]->rx_ring;
4162                         cpr = rxqs[k]->cp_ring;
4163
4164                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4165                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4166                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4167                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4168
4169                         if (++k == max_rings)
4170                                 k = 0;
4171                 }
4172                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4173                                             BNXT_USE_CHIMP_MB);
4174
4175                 HWRM_CHECK_RESULT();
4176                 HWRM_UNLOCK();
4177         }
4178
4179         return rc;
4180 }
4181
4182 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4183 {
4184         unsigned int rss_idx, fw_idx, i;
4185
4186         if (!(vnic->rss_table && vnic->hash_type))
4187                 return 0;
4188
4189         if (BNXT_CHIP_THOR(bp))
4190                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4191
4192         /*
4193          * Fill the RSS hash & redirection table with
4194          * ring group ids for all VNICs
4195          */
4196         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4197                 rss_idx++, fw_idx++) {
4198                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4199                         fw_idx %= bp->rx_cp_nr_rings;
4200                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4201                                 break;
4202                         fw_idx++;
4203                 }
4204                 if (i == bp->rx_cp_nr_rings)
4205                         return 0;
4206                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4207         }
4208         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4209 }
4210
4211 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4212         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4213 {
4214         uint16_t flags;
4215
4216         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4217
4218         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4219         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4220
4221         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4222         req->num_cmpl_dma_aggr_during_int =
4223                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4224
4225         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4226
4227         /* min timer set to 1/2 of interrupt timer */
4228         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4229
4230         /* buf timer set to 1/4 of interrupt timer */
4231         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4232
4233         req->cmpl_aggr_dma_tmr_during_int =
4234                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4235
4236         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4237                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4238         req->flags = rte_cpu_to_le_16(flags);
4239 }
4240
4241 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4242                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4243 {
4244         struct hwrm_ring_aggint_qcaps_input req = {0};
4245         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4246         uint32_t enables;
4247         uint16_t flags;
4248         int rc;
4249
4250         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4251         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4252         HWRM_CHECK_RESULT();
4253
4254         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4255         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4256
4257         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4258                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4259         agg_req->flags = rte_cpu_to_le_16(flags);
4260         enables =
4261          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4262          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4263         agg_req->enables = rte_cpu_to_le_32(enables);
4264
4265         HWRM_UNLOCK();
4266         return rc;
4267 }
4268
4269 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4270                         struct bnxt_coal *coal, uint16_t ring_id)
4271 {
4272         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4273         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4274                                                 bp->hwrm_cmd_resp_addr;
4275         int rc;
4276
4277         /* Set ring coalesce parameters only for 100G NICs */
4278         if (BNXT_CHIP_THOR(bp)) {
4279                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4280                         return -1;
4281         } else if (bnxt_stratus_device(bp)) {
4282                 bnxt_hwrm_set_coal_params(coal, &req);
4283         } else {
4284                 return 0;
4285         }
4286
4287         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4288         req.ring_id = rte_cpu_to_le_16(ring_id);
4289         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4290         HWRM_CHECK_RESULT();
4291         HWRM_UNLOCK();
4292         return 0;
4293 }
4294
4295 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4296 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4297 {
4298         struct hwrm_func_backing_store_qcaps_input req = {0};
4299         struct hwrm_func_backing_store_qcaps_output *resp =
4300                 bp->hwrm_cmd_resp_addr;
4301         int rc;
4302
4303         if (!BNXT_CHIP_THOR(bp) ||
4304             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4305             BNXT_VF(bp) ||
4306             bp->ctx)
4307                 return 0;
4308
4309         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4310         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4311         HWRM_CHECK_RESULT_SILENT();
4312
4313         if (!rc) {
4314                 struct bnxt_ctx_pg_info *ctx_pg;
4315                 struct bnxt_ctx_mem_info *ctx;
4316                 int total_alloc_len;
4317                 int i;
4318
4319                 total_alloc_len = sizeof(*ctx);
4320                 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4321                                  RTE_CACHE_LINE_SIZE);
4322                 if (!ctx) {
4323                         rc = -ENOMEM;
4324                         goto ctx_err;
4325                 }
4326                 memset(ctx, 0, total_alloc_len);
4327
4328                 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4329                                     sizeof(*ctx_pg) * BNXT_MAX_Q,
4330                                     RTE_CACHE_LINE_SIZE);
4331                 if (!ctx_pg) {
4332                         rc = -ENOMEM;
4333                         goto ctx_err;
4334                 }
4335                 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4336                         ctx->tqm_mem[i] = ctx_pg;
4337
4338                 bp->ctx = ctx;
4339                 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4340                 ctx->qp_min_qp1_entries =
4341                         rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4342                 ctx->qp_max_l2_entries =
4343                         rte_le_to_cpu_16(resp->qp_max_l2_entries);
4344                 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4345                 ctx->srq_max_l2_entries =
4346                         rte_le_to_cpu_16(resp->srq_max_l2_entries);
4347                 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4348                 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4349                 ctx->cq_max_l2_entries =
4350                         rte_le_to_cpu_16(resp->cq_max_l2_entries);
4351                 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4352                 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4353                 ctx->vnic_max_vnic_entries =
4354                         rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4355                 ctx->vnic_max_ring_table_entries =
4356                         rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4357                 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4358                 ctx->stat_max_entries =
4359                         rte_le_to_cpu_32(resp->stat_max_entries);
4360                 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4361                 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4362                 ctx->tqm_min_entries_per_ring =
4363                         rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4364                 ctx->tqm_max_entries_per_ring =
4365                         rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4366                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4367                 if (!ctx->tqm_entries_multiple)
4368                         ctx->tqm_entries_multiple = 1;
4369                 ctx->mrav_max_entries =
4370                         rte_le_to_cpu_32(resp->mrav_max_entries);
4371                 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4372                 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4373                 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4374         } else {
4375                 rc = 0;
4376         }
4377 ctx_err:
4378         HWRM_UNLOCK();
4379         return rc;
4380 }
4381
4382 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4383 {
4384         struct hwrm_func_backing_store_cfg_input req = {0};
4385         struct hwrm_func_backing_store_cfg_output *resp =
4386                 bp->hwrm_cmd_resp_addr;
4387         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4388         struct bnxt_ctx_pg_info *ctx_pg;
4389         uint32_t *num_entries;
4390         uint64_t *pg_dir;
4391         uint8_t *pg_attr;
4392         uint32_t ena;
4393         int i, rc;
4394
4395         if (!ctx)
4396                 return 0;
4397
4398         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4399         req.enables = rte_cpu_to_le_32(enables);
4400
4401         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4402                 ctx_pg = &ctx->qp_mem;
4403                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4404                 req.qp_num_qp1_entries =
4405                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4406                 req.qp_num_l2_entries =
4407                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4408                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4409                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4410                                       &req.qpc_pg_size_qpc_lvl,
4411                                       &req.qpc_page_dir);
4412         }
4413
4414         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4415                 ctx_pg = &ctx->srq_mem;
4416                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4417                 req.srq_num_l2_entries =
4418                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4419                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4420                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4421                                       &req.srq_pg_size_srq_lvl,
4422                                       &req.srq_page_dir);
4423         }
4424
4425         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4426                 ctx_pg = &ctx->cq_mem;
4427                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4428                 req.cq_num_l2_entries =
4429                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4430                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4431                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4432                                       &req.cq_pg_size_cq_lvl,
4433                                       &req.cq_page_dir);
4434         }
4435
4436         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4437                 ctx_pg = &ctx->vnic_mem;
4438                 req.vnic_num_vnic_entries =
4439                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4440                 req.vnic_num_ring_table_entries =
4441                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4442                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4443                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4444                                       &req.vnic_pg_size_vnic_lvl,
4445                                       &req.vnic_page_dir);
4446         }
4447
4448         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4449                 ctx_pg = &ctx->stat_mem;
4450                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4451                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4452                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4453                                       &req.stat_pg_size_stat_lvl,
4454                                       &req.stat_page_dir);
4455         }
4456
4457         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4458         num_entries = &req.tqm_sp_num_entries;
4459         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4460         pg_dir = &req.tqm_sp_page_dir;
4461         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4462         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4463                 if (!(enables & ena))
4464                         continue;
4465
4466                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4467
4468                 ctx_pg = ctx->tqm_mem[i];
4469                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4470                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4471         }
4472
4473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4474         HWRM_CHECK_RESULT();
4475         HWRM_UNLOCK();
4476
4477         return rc;
4478 }
4479
4480 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4481 {
4482         struct hwrm_port_qstats_ext_input req = {0};
4483         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4484         struct bnxt_pf_info *pf = &bp->pf;
4485         int rc;
4486
4487         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4488               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4489                 return 0;
4490
4491         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4492
4493         req.port_id = rte_cpu_to_le_16(pf->port_id);
4494         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4495                 req.tx_stat_host_addr =
4496                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4497                 req.tx_stat_size =
4498                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4499         }
4500         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4501                 req.rx_stat_host_addr =
4502                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4503                 req.rx_stat_size =
4504                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4505         }
4506         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4507
4508         if (rc) {
4509                 bp->fw_rx_port_stats_ext_size = 0;
4510                 bp->fw_tx_port_stats_ext_size = 0;
4511         } else {
4512                 bp->fw_rx_port_stats_ext_size =
4513                         rte_le_to_cpu_16(resp->rx_stat_size);
4514                 bp->fw_tx_port_stats_ext_size =
4515                         rte_le_to_cpu_16(resp->tx_stat_size);
4516         }
4517
4518         HWRM_CHECK_RESULT();
4519         HWRM_UNLOCK();
4520
4521         return rc;
4522 }
4523
4524 int
4525 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4526 {
4527         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4528         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4529                 bp->hwrm_cmd_resp_addr;
4530         int rc = 0;
4531
4532         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_KONG(bp));
4533         req.tunnel_type = type;
4534         req.dest_fid = bp->fw_fid;
4535         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4536         HWRM_CHECK_RESULT();
4537
4538         HWRM_UNLOCK();
4539
4540         return rc;
4541 }
4542
4543 int
4544 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4545 {
4546         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4547         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4548                 bp->hwrm_cmd_resp_addr;
4549         int rc = 0;
4550
4551         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_KONG(bp));
4552         req.tunnel_type = type;
4553         req.dest_fid = bp->fw_fid;
4554         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4555         HWRM_CHECK_RESULT();
4556
4557         HWRM_UNLOCK();
4558
4559         return rc;
4560 }
4561
4562 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4563 {
4564         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4565         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4566                 bp->hwrm_cmd_resp_addr;
4567         int rc = 0;
4568
4569         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_KONG(bp));
4570         req.src_fid = bp->fw_fid;
4571         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4572         HWRM_CHECK_RESULT();
4573
4574         if (type)
4575                 *type = resp->tunnel_mask;
4576
4577         HWRM_UNLOCK();
4578
4579         return rc;
4580 }
4581
4582 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4583                                    uint16_t *dst_fid)
4584 {
4585         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4586         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4587                 bp->hwrm_cmd_resp_addr;
4588         int rc = 0;
4589
4590         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_KONG(bp));
4591         req.src_fid = bp->fw_fid;
4592         req.tunnel_type = tun_type;
4593         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4594         HWRM_CHECK_RESULT();
4595
4596         if (dst_fid)
4597                 *dst_fid = resp->dest_fid;
4598
4599         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4600
4601         HWRM_UNLOCK();
4602
4603         return rc;
4604 }
4605
4606 int bnxt_hwrm_set_mac(struct bnxt *bp)
4607 {
4608         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4609         struct hwrm_func_vf_cfg_input req = {0};
4610         int rc = 0;
4611
4612         if (!BNXT_VF(bp))
4613                 return 0;
4614
4615         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4616
4617         req.enables =
4618                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4619         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4620
4621         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4622
4623         HWRM_CHECK_RESULT();
4624
4625         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4626         HWRM_UNLOCK();
4627
4628         return rc;
4629 }