drivers/net/bnxt/bnxt_rxr.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_bitmap.h>
  10 #include <rte_byteorder.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memory.h>
  13 #include <rte_alarm.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_reps.h"
  17 #include "bnxt_ring.h"
  18 #include "bnxt_rxr.h"
  19 #include "bnxt_rxq.h"
  20 #include "hsi_struct_def_dpdk.h"
  21 #include "bnxt_hwrm.h"
  22
  23 #include <bnxt_tf_common.h>
  24 #include <ulp_mark_mgr.h>
  25
  26 /*
  27  * RX Ring handling
  28  */
  29
  30 static inline struct rte_mbuf *__bnxt_alloc_rx_data(struct rte_mempool *mb)
  31 {
  32         struct rte_mbuf *data;
  33
  34         data = rte_mbuf_raw_alloc(mb);
  35
  36         return data;
  37 }
  38
  39 static inline int bnxt_alloc_rx_data(struct bnxt_rx_queue *rxq,
  40                                      struct bnxt_rx_ring_info *rxr,
  41                                      uint16_t raw_prod)
  42 {
  43         uint16_t prod = RING_IDX(rxr->rx_ring_struct, raw_prod);
  44         struct rx_prod_pkt_bd *rxbd;
  45         struct rte_mbuf **rx_buf;
  46         struct rte_mbuf *mbuf;
  47
  48         rxbd = &rxr->rx_desc_ring[prod];
  49         rx_buf = &rxr->rx_buf_ring[prod];
  50         mbuf = __bnxt_alloc_rx_data(rxq->mb_pool);
  51         if (!mbuf) {
  52                 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
  53                 return -ENOMEM;
  54         }
  55
  56         *rx_buf = mbuf;
  57         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
  58
  59         rxbd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
  60
  61         return 0;
  62 }
  63
  64 static inline int bnxt_alloc_ag_data(struct bnxt_rx_queue *rxq,
  65                                      struct bnxt_rx_ring_info *rxr,
  66                                      uint16_t raw_prod)
  67 {
  68         uint16_t prod = RING_IDX(rxr->ag_ring_struct, raw_prod);
  69         struct rx_prod_pkt_bd *rxbd;
  70         struct rte_mbuf **rx_buf;
  71         struct rte_mbuf *mbuf;
  72
  73         rxbd = &rxr->ag_desc_ring[prod];
  74         rx_buf = &rxr->ag_buf_ring[prod];
  75         if (rxbd == NULL) {
  76                 PMD_DRV_LOG(ERR, "Jumbo Frame. rxbd is NULL\n");
  77                 return -EINVAL;
  78         }
  79
  80         if (rx_buf == NULL) {
  81                 PMD_DRV_LOG(ERR, "Jumbo Frame. rx_buf is NULL\n");
  82                 return -EINVAL;
  83         }
  84
  85         mbuf = __bnxt_alloc_rx_data(rxq->mb_pool);
  86         if (!mbuf) {
  87                 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
  88                 return -ENOMEM;
  89         }
  90
  91         *rx_buf = mbuf;
  92         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
  93
  94         rxbd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
  95
  96         return 0;
  97 }
  98
  99 static inline void bnxt_reuse_rx_mbuf(struct bnxt_rx_ring_info *rxr,
 100                                struct rte_mbuf *mbuf)
 101 {
 102         uint16_t prod, raw_prod = RING_NEXT(rxr->rx_raw_prod);
 103         struct rte_mbuf **prod_rx_buf;
 104         struct rx_prod_pkt_bd *prod_bd;
 105
 106         prod = RING_IDX(rxr->rx_ring_struct, raw_prod);
 107         prod_rx_buf = &rxr->rx_buf_ring[prod];
 108
 109         RTE_ASSERT(*prod_rx_buf == NULL);
 110         RTE_ASSERT(mbuf != NULL);
 111
 112         *prod_rx_buf = mbuf;
 113
 114         prod_bd = &rxr->rx_desc_ring[prod];
 115
 116         prod_bd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 117
 118         rxr->rx_raw_prod = raw_prod;
 119 }
 120
 121 static inline
 122 struct rte_mbuf *bnxt_consume_rx_buf(struct bnxt_rx_ring_info *rxr,
 123                                      uint16_t cons)
 124 {
 125         struct rte_mbuf **cons_rx_buf;
 126         struct rte_mbuf *mbuf;
 127
 128         cons_rx_buf = &rxr->rx_buf_ring[RING_IDX(rxr->rx_ring_struct, cons)];
 129         RTE_ASSERT(*cons_rx_buf != NULL);
 130         mbuf = *cons_rx_buf;
 131         *cons_rx_buf = NULL;
 132
 133         return mbuf;
 134 }
 135
 136 static void bnxt_rx_ring_reset(void *arg)
 137 {
 138         struct bnxt *bp = arg;
 139         int i, rc = 0;
 140         struct bnxt_rx_queue *rxq;
 141
 142
 143         for (i = 0; i < (int)bp->rx_nr_rings; i++) {
 144                 struct bnxt_rx_ring_info *rxr;
 145
 146                 rxq = bp->rx_queues[i];
 147                 if (!rxq || !rxq->in_reset)
 148                         continue;
 149
 150                 rxr = rxq->rx_ring;
 151                 /* Disable and flush TPA before resetting the RX ring */
 152                 if (rxr->tpa_info)
 153                         bnxt_hwrm_vnic_tpa_cfg(bp, rxq->vnic, false);
 154                 rc = bnxt_hwrm_rx_ring_reset(bp, i);
 155                 if (rc) {
 156                         PMD_DRV_LOG(ERR, "Rx ring%d reset failed\n", i);
 157                         continue;
 158                 }
 159
 160                 bnxt_rx_queue_release_mbufs(rxq);
 161                 rxr->rx_raw_prod = 0;
 162                 rxr->ag_raw_prod = 0;
 163                 rxr->rx_next_cons = 0;
 164                 bnxt_init_one_rx_ring(rxq);
 165                 bnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);
 166                 bnxt_db_write(&rxr->ag_db, rxr->ag_raw_prod);
 167                 if (rxr->tpa_info)
 168                         bnxt_hwrm_vnic_tpa_cfg(bp, rxq->vnic, true);
 169
 170                 rxq->in_reset = 0;
 171         }
 172 }
 173
 174
 175 static void bnxt_sched_ring_reset(struct bnxt_rx_queue *rxq)
 176 {
 177         rxq->in_reset = 1;
 178         rte_eal_alarm_set(1, bnxt_rx_ring_reset, (void *)rxq->bp);
 179 }
 180
 181 static void bnxt_tpa_get_metadata(struct bnxt *bp,
 182                                   struct bnxt_tpa_info *tpa_info,
 183                                   struct rx_tpa_start_cmpl *tpa_start,
 184                                   struct rx_tpa_start_cmpl_hi *tpa_start1)
 185 {
 186         tpa_info->cfa_code_valid = 0;
 187         tpa_info->vlan_valid = 0;
 188         tpa_info->hash_valid = 0;
 189         tpa_info->l4_csum_valid = 0;
 190
 191         if (likely(tpa_start->flags_type &
 192                    rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS_RSS_VALID))) {
 193                 tpa_info->hash_valid = 1;
 194                 tpa_info->rss_hash = rte_le_to_cpu_32(tpa_start->rss_hash);
 195         }
 196
 197         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
 198                 struct rx_tpa_start_v2_cmpl *v2_tpa_start = (void *)tpa_start;
 199                 struct rx_tpa_start_v2_cmpl_hi *v2_tpa_start1 =
 200                         (void *)tpa_start1;
 201
 202                 if (v2_tpa_start->agg_id &
 203                     RX_TPA_START_V2_CMPL_METADATA1_VALID) {
 204                         tpa_info->vlan_valid = 1;
 205                         tpa_info->vlan =
 206                                 rte_le_to_cpu_16(v2_tpa_start1->metadata0);
 207                 }
 208
 209                 if (v2_tpa_start1->flags2 & RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK)
 210                         tpa_info->l4_csum_valid = 1;
 211
 212                 return;
 213         }
 214
 215         tpa_info->cfa_code_valid = 1;
 216         tpa_info->cfa_code = rte_le_to_cpu_16(tpa_start1->cfa_code);
 217         if (tpa_start1->flags2 &
 218             rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN)) {
 219                 tpa_info->vlan_valid = 1;
 220                 tpa_info->vlan = rte_le_to_cpu_32(tpa_start1->metadata);
 221         }
 222
 223         if (likely(tpa_start1->flags2 &
 224                    rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC)))
 225                 tpa_info->l4_csum_valid = 1;
 226 }
 227
 228 static void bnxt_tpa_start(struct bnxt_rx_queue *rxq,
 229                            struct rx_tpa_start_cmpl *tpa_start,
 230                            struct rx_tpa_start_cmpl_hi *tpa_start1)
 231 {
 232         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
 233         uint16_t agg_id;
 234         uint16_t data_cons;
 235         struct bnxt_tpa_info *tpa_info;
 236         struct rte_mbuf *mbuf;
 237
 238         agg_id = bnxt_tpa_start_agg_id(rxq->bp, tpa_start);
 239
 240         data_cons = tpa_start->opaque;
 241         tpa_info = &rxr->tpa_info[agg_id];
 242         if (unlikely(data_cons != rxr->rx_next_cons)) {
 243                 PMD_DRV_LOG(ERR, "TPA cons %x, expected cons %x\n",
 244                             data_cons, rxr->rx_next_cons);
 245                 bnxt_sched_ring_reset(rxq);
 246                 return;
 247         }
 248
 249         mbuf = bnxt_consume_rx_buf(rxr, data_cons);
 250
 251         bnxt_reuse_rx_mbuf(rxr, tpa_info->mbuf);
 252
 253         tpa_info->agg_count = 0;
 254         tpa_info->mbuf = mbuf;
 255         tpa_info->len = rte_le_to_cpu_32(tpa_start->len);
 256
 257         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 258         mbuf->nb_segs = 1;
 259         mbuf->next = NULL;
 260         mbuf->pkt_len = rte_le_to_cpu_32(tpa_start->len);
 261         mbuf->data_len = mbuf->pkt_len;
 262         mbuf->port = rxq->port_id;
 263         mbuf->ol_flags = PKT_RX_LRO;
 264
 265         bnxt_tpa_get_metadata(rxq->bp, tpa_info, tpa_start, tpa_start1);
 266
 267         if (likely(tpa_info->hash_valid)) {
 268                 mbuf->hash.rss = tpa_info->rss_hash;
 269                 mbuf->ol_flags |= PKT_RX_RSS_HASH;
 270         } else if (tpa_info->cfa_code_valid) {
 271                 mbuf->hash.fdir.id = tpa_info->cfa_code;
 272                 mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 273         }
 274
 275         if (tpa_info->vlan_valid) {
 276                 mbuf->vlan_tci = tpa_info->vlan;
 277                 mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
 278         }
 279
 280         if (likely(tpa_info->l4_csum_valid))
 281                 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
 282
 283         /* recycle next mbuf */
 284         data_cons = RING_NEXT(data_cons);
 285         bnxt_reuse_rx_mbuf(rxr, bnxt_consume_rx_buf(rxr, data_cons));
 286
 287         rxr->rx_next_cons = RING_IDX(rxr->rx_ring_struct,
 288                                      RING_NEXT(data_cons));
 289 }
 290
 291 static int bnxt_agg_bufs_valid(struct bnxt_cp_ring_info *cpr,
 292                 uint8_t agg_bufs, uint32_t raw_cp_cons)
 293 {
 294         uint16_t last_cp_cons;
 295         struct rx_pkt_cmpl *agg_cmpl;
 296
 297         raw_cp_cons = ADV_RAW_CMP(raw_cp_cons, agg_bufs);
 298         last_cp_cons = RING_CMP(cpr->cp_ring_struct, raw_cp_cons);
 299         agg_cmpl = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[last_cp_cons];
 300         return CMP_VALID(agg_cmpl, raw_cp_cons, cpr->cp_ring_struct);
 301 }
 302
 303 /* TPA consume agg buffer out of order, allocate connected data only */
 304 static int bnxt_prod_ag_mbuf(struct bnxt_rx_queue *rxq)
 305 {
 306         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
 307         uint16_t raw_next = RING_NEXT(rxr->ag_raw_prod);
 308         uint16_t bmap_next = RING_IDX(rxr->ag_ring_struct, raw_next);
 309
 310         /* TODO batch allocation for better performance */
 311         while (rte_bitmap_get(rxr->ag_bitmap, bmap_next)) {
 312                 if (unlikely(bnxt_alloc_ag_data(rxq, rxr, raw_next))) {
 313                         PMD_DRV_LOG(ERR, "agg mbuf alloc failed: prod=0x%x\n",
 314                                     raw_next);
 315                         break;
 316                 }
 317                 rte_bitmap_clear(rxr->ag_bitmap, bmap_next);
 318                 rxr->ag_raw_prod = raw_next;
 319                 raw_next = RING_NEXT(raw_next);
 320                 bmap_next = RING_IDX(rxr->ag_ring_struct, raw_next);
 321         }
 322
 323         return 0;
 324 }
 325
 326 static int bnxt_rx_pages(struct bnxt_rx_queue *rxq,
 327                          struct rte_mbuf *mbuf, uint32_t *tmp_raw_cons,
 328                          uint8_t agg_buf, struct bnxt_tpa_info *tpa_info)
 329 {
 330         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
 331         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
 332         int i;
 333         uint16_t cp_cons, ag_cons;
 334         struct rx_pkt_cmpl *rxcmp;
 335         struct rte_mbuf *last = mbuf;
 336         bool is_p5_tpa = tpa_info && BNXT_CHIP_P5(rxq->bp);
 337
 338         for (i = 0; i < agg_buf; i++) {
 339                 struct rte_mbuf **ag_buf;
 340                 struct rte_mbuf *ag_mbuf;
 341
 342                 if (is_p5_tpa) {
 343                         rxcmp = (void *)&tpa_info->agg_arr[i];
 344                 } else {
 345                         *tmp_raw_cons = NEXT_RAW_CMP(*tmp_raw_cons);
 346                         cp_cons = RING_CMP(cpr->cp_ring_struct, *tmp_raw_cons);
 347                         rxcmp = (struct rx_pkt_cmpl *)
 348                                         &cpr->cp_desc_ring[cp_cons];
 349                 }
 350
 351 #ifdef BNXT_DEBUG
 352                 bnxt_dump_cmpl(cp_cons, rxcmp);
 353 #endif
 354
 355                 ag_cons = rxcmp->opaque;
 356                 RTE_ASSERT(ag_cons <= rxr->ag_ring_struct->ring_mask);
 357                 ag_buf = &rxr->ag_buf_ring[ag_cons];
 358                 ag_mbuf = *ag_buf;
 359                 RTE_ASSERT(ag_mbuf != NULL);
 360
 361                 ag_mbuf->data_len = rte_le_to_cpu_16(rxcmp->len);
 362
 363                 mbuf->nb_segs++;
 364                 mbuf->pkt_len += ag_mbuf->data_len;
 365
 366                 last->next = ag_mbuf;
 367                 last = ag_mbuf;
 368
 369                 *ag_buf = NULL;
 370
 371                 /*
 372                  * As aggregation buffer consumed out of order in TPA module,
 373                  * use bitmap to track freed slots to be allocated and notified
 374                  * to NIC
 375                  */
 376                 rte_bitmap_set(rxr->ag_bitmap, ag_cons);
 377         }
 378         last->next = NULL;
 379         bnxt_prod_ag_mbuf(rxq);
 380         return 0;
 381 }
 382
 383 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 384                            uint32_t *raw_cons, void *cmp)
 385 {
 386         struct rx_pkt_cmpl *rxcmp = cmp;
 387         uint32_t tmp_raw_cons = *raw_cons;
 388         uint8_t cmp_type, agg_bufs = 0;
 389
 390         cmp_type = CMP_TYPE(rxcmp);
 391
 392         if (cmp_type == CMPL_BASE_TYPE_RX_L2) {
 393                 agg_bufs = BNXT_RX_L2_AGG_BUFS(rxcmp);
 394         } else if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
 395                 struct rx_tpa_end_cmpl *tpa_end = cmp;
 396
 397                 if (BNXT_CHIP_P5(bp))
 398                         return 0;
 399
 400                 agg_bufs = BNXT_TPA_END_AGG_BUFS(tpa_end);
 401         }
 402
 403         if (agg_bufs) {
 404                 if (!bnxt_agg_bufs_valid(cpr, agg_bufs, tmp_raw_cons))
 405                         return -EBUSY;
 406         }
 407         *raw_cons = tmp_raw_cons;
 408         return 0;
 409 }
 410
 411 static inline struct rte_mbuf *bnxt_tpa_end(
 412                 struct bnxt_rx_queue *rxq,
 413                 uint32_t *raw_cp_cons,
 414                 struct rx_tpa_end_cmpl *tpa_end,
 415                 struct rx_tpa_end_cmpl_hi *tpa_end1)
 416 {
 417         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
 418         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
 419         uint16_t agg_id;
 420         struct rte_mbuf *mbuf;
 421         uint8_t agg_bufs;
 422         uint8_t payload_offset;
 423         struct bnxt_tpa_info *tpa_info;
 424
 425         if (unlikely(rxq->in_reset)) {
 426                 PMD_DRV_LOG(ERR, "rxq->in_reset: raw_cp_cons:%d\n",
 427                             *raw_cp_cons);
 428                 bnxt_discard_rx(rxq->bp, cpr, raw_cp_cons, tpa_end);
 429                 return NULL;
 430         }
 431
 432         if (BNXT_CHIP_P5(rxq->bp)) {
 433                 struct rx_tpa_v2_end_cmpl *th_tpa_end;
 434                 struct rx_tpa_v2_end_cmpl_hi *th_tpa_end1;
 435
 436                 th_tpa_end = (void *)tpa_end;
 437                 th_tpa_end1 = (void *)tpa_end1;
 438                 agg_id = BNXT_TPA_END_AGG_ID_TH(th_tpa_end);
 439                 agg_bufs = BNXT_TPA_END_AGG_BUFS_TH(th_tpa_end1);
 440                 payload_offset = th_tpa_end1->payload_offset;
 441         } else {
 442                 agg_id = BNXT_TPA_END_AGG_ID(tpa_end);
 443                 agg_bufs = BNXT_TPA_END_AGG_BUFS(tpa_end);
 444                 if (!bnxt_agg_bufs_valid(cpr, agg_bufs, *raw_cp_cons))
 445                         return NULL;
 446                 payload_offset = tpa_end->payload_offset;
 447         }
 448
 449         tpa_info = &rxr->tpa_info[agg_id];
 450         mbuf = tpa_info->mbuf;
 451         RTE_ASSERT(mbuf != NULL);
 452
 453         if (agg_bufs) {
 454                 bnxt_rx_pages(rxq, mbuf, raw_cp_cons, agg_bufs, tpa_info);
 455         }
 456         mbuf->l4_len = payload_offset;
 457
 458         struct rte_mbuf *new_data = __bnxt_alloc_rx_data(rxq->mb_pool);
 459         RTE_ASSERT(new_data != NULL);
 460         if (!new_data) {
 461                 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
 462                 return NULL;
 463         }
 464         tpa_info->mbuf = new_data;
 465
 466         return mbuf;
 467 }
 468
 469 uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM] __rte_cache_aligned;
 470
 471 static void __rte_cold
 472 bnxt_init_ptype_table(void)
 473 {
 474         uint32_t *pt = bnxt_ptype_table;
 475         static bool initialized;
 476         int ip6, tun, type;
 477         uint32_t l3;
 478         int i;
 479
 480         if (initialized)
 481                 return;
 482
 483         for (i = 0; i < BNXT_PTYPE_TBL_DIM; i++) {
 484                 if (i & BNXT_PTYPE_TBL_VLAN_MSK)
 485                         pt[i] = RTE_PTYPE_L2_ETHER_VLAN;
 486                 else
 487                         pt[i] = RTE_PTYPE_L2_ETHER;
 488
 489                 ip6 = !!(i & BNXT_PTYPE_TBL_IP_VER_MSK);
 490                 tun = !!(i & BNXT_PTYPE_TBL_TUN_MSK);
 491                 type = (i & BNXT_PTYPE_TBL_TYPE_MSK) >> BNXT_PTYPE_TBL_TYPE_SFT;
 492
 493                 if (!tun && !ip6)
 494                         l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
 495                 else if (!tun && ip6)
 496                         l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
 497                 else if (tun && !ip6)
 498                         l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
 499                 else
 500                         l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
 501
 502                 switch (type) {
 503                 case BNXT_PTYPE_TBL_TYPE_ICMP:
 504                         if (tun)
 505                                 pt[i] |= l3 | RTE_PTYPE_INNER_L4_ICMP;
 506                         else
 507                                 pt[i] |= l3 | RTE_PTYPE_L4_ICMP;
 508                         break;
 509                 case BNXT_PTYPE_TBL_TYPE_TCP:
 510                         if (tun)
 511                                 pt[i] |= l3 | RTE_PTYPE_INNER_L4_TCP;
 512                         else
 513                                 pt[i] |= l3 | RTE_PTYPE_L4_TCP;
 514                         break;
 515                 case BNXT_PTYPE_TBL_TYPE_UDP:
 516                         if (tun)
 517                                 pt[i] |= l3 | RTE_PTYPE_INNER_L4_UDP;
 518                         else
 519                                 pt[i] |= l3 | RTE_PTYPE_L4_UDP;
 520                         break;
 521                 case BNXT_PTYPE_TBL_TYPE_IP:
 522                         pt[i] |= l3;
 523                         break;
 524                 }
 525         }
 526         initialized = true;
 527 }
 528
 529 static uint32_t
 530 bnxt_parse_pkt_type(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1)
 531 {
 532         uint32_t flags_type, flags2;
 533         uint8_t index;
 534
 535         flags_type = rte_le_to_cpu_16(rxcmp->flags_type);
 536         flags2 = rte_le_to_cpu_32(rxcmp1->flags2);
 537
 538         /* Validate ptype table indexing at build time. */
 539         bnxt_check_ptype_constants();
 540
 541         /*
 542          * Index format:
 543          *     bit 0: Set if IP tunnel encapsulated packet.
 544          *     bit 1: Set if IPv6 packet, clear if IPv4.
 545          *     bit 2: Set if VLAN tag present.
 546          *     bits 3-6: Four-bit hardware packet type field.
 547          */
 548         index = BNXT_CMPL_ITYPE_TO_IDX(flags_type) |
 549                 BNXT_CMPL_VLAN_TUN_TO_IDX(flags2) |
 550                 BNXT_CMPL_IP_VER_TO_IDX(flags2);
 551
 552         return bnxt_ptype_table[index];
 553 }
 554
 555 static void __rte_cold
 556 bnxt_init_ol_flags_tables(struct bnxt_rx_queue *rxq)
 557 {
 558         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
 559         struct rte_eth_conf *dev_conf;
 560         bool outer_cksum_enabled;
 561         uint64_t offloads;
 562         uint32_t *pt;
 563         int i;
 564
 565         dev_conf = &rxq->bp->eth_dev->data->dev_conf;
 566         offloads = dev_conf->rxmode.offloads;
 567
 568         outer_cksum_enabled = !!(offloads & (DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 569                                              DEV_RX_OFFLOAD_OUTER_UDP_CKSUM));
 570
 571         /* Initialize ol_flags table. */
 572         pt = rxr->ol_flags_table;
 573         for (i = 0; i < BNXT_OL_FLAGS_TBL_DIM; i++) {
 574                 pt[i] = 0;
 575
 576                 if (i & RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN)
 577                         pt[i] |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
 578
 579                 if (i & (RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC << 3)) {
 580                         /* Tunnel case. */
 581                         if (outer_cksum_enabled) {
 582                                 if (i & RX_PKT_CMPL_FLAGS2_IP_CS_CALC)
 583                                         pt[i] |= PKT_RX_IP_CKSUM_GOOD;
 584
 585                                 if (i & RX_PKT_CMPL_FLAGS2_L4_CS_CALC)
 586                                         pt[i] |= PKT_RX_L4_CKSUM_GOOD;
 587
 588                                 if (i & RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC)
 589                                         pt[i] |= PKT_RX_OUTER_L4_CKSUM_GOOD;
 590                         } else {
 591                                 if (i & RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC)
 592                                         pt[i] |= PKT_RX_IP_CKSUM_GOOD;
 593
 594                                 if (i & RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC)
 595                                         pt[i] |= PKT_RX_L4_CKSUM_GOOD;
 596                         }
 597                 } else {
 598                         /* Non-tunnel case. */
 599                         if (i & RX_PKT_CMPL_FLAGS2_IP_CS_CALC)
 600                                 pt[i] |= PKT_RX_IP_CKSUM_GOOD;
 601
 602                         if (i & RX_PKT_CMPL_FLAGS2_L4_CS_CALC)
 603                                 pt[i] |= PKT_RX_L4_CKSUM_GOOD;
 604                 }
 605         }
 606
 607         /* Initialize checksum error table. */
 608         pt = rxr->ol_flags_err_table;
 609         for (i = 0; i < BNXT_OL_FLAGS_ERR_TBL_DIM; i++) {
 610                 pt[i] = 0;
 611
 612                 if (i & (RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC << 2)) {
 613                         /* Tunnel case. */
 614                         if (outer_cksum_enabled) {
 615                                 if (i & (RX_PKT_CMPL_ERRORS_IP_CS_ERROR >> 4))
 616                                         pt[i] |= PKT_RX_IP_CKSUM_BAD;
 617
 618                                 if (i & (RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR >> 4))
 619                                         pt[i] |= PKT_RX_OUTER_IP_CKSUM_BAD;
 620
 621                                 if (i & (RX_PKT_CMPL_ERRORS_L4_CS_ERROR >> 4))
 622                                         pt[i] |= PKT_RX_L4_CKSUM_BAD;
 623
 624                                 if (i & (RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR >> 4))
 625                                         pt[i] |= PKT_RX_OUTER_L4_CKSUM_BAD;
 626                         } else {
 627                                 if (i & (RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR >> 4))
 628                                         pt[i] |= PKT_RX_IP_CKSUM_BAD;
 629
 630                                 if (i & (RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR >> 4))
 631                                         pt[i] |= PKT_RX_L4_CKSUM_BAD;
 632                         }
 633                 } else {
 634                         /* Non-tunnel case. */
 635                         if (i & (RX_PKT_CMPL_ERRORS_IP_CS_ERROR >> 4))
 636                                 pt[i] |= PKT_RX_IP_CKSUM_BAD;
 637
 638                         if (i & (RX_PKT_CMPL_ERRORS_L4_CS_ERROR >> 4))
 639                                 pt[i] |= PKT_RX_L4_CKSUM_BAD;
 640                 }
 641         }
 642 }
 643
 644 static void
 645 bnxt_set_ol_flags(struct bnxt_rx_ring_info *rxr, struct rx_pkt_cmpl *rxcmp,
 646                   struct rx_pkt_cmpl_hi *rxcmp1, struct rte_mbuf *mbuf)
 647 {
 648         uint16_t flags_type, errors, flags;
 649         uint64_t ol_flags;
 650
 651         flags_type = rte_le_to_cpu_16(rxcmp->flags_type);
 652
 653         flags = rte_le_to_cpu_32(rxcmp1->flags2) &
 654                                 (RX_PKT_CMPL_FLAGS2_IP_CS_CALC |
 655                                  RX_PKT_CMPL_FLAGS2_L4_CS_CALC |
 656                                  RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC |
 657                                  RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC |
 658                                  RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN);
 659
 660         flags |= (flags & RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC) << 3;
 661         errors = rte_le_to_cpu_16(rxcmp1->errors_v2) &
 662                                 (RX_PKT_CMPL_ERRORS_IP_CS_ERROR |
 663                                  RX_PKT_CMPL_ERRORS_L4_CS_ERROR |
 664                                  RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR |
 665                                  RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR);
 666         errors = (errors >> 4) & flags;
 667
 668         ol_flags = rxr->ol_flags_table[flags & ~errors];
 669
 670         if (unlikely(errors)) {
 671                 errors |= (flags & RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC) << 2;
 672                 ol_flags |= rxr->ol_flags_err_table[errors];
 673         }
 674
 675         if (flags_type & RX_PKT_CMPL_FLAGS_RSS_VALID) {
 676                 mbuf->hash.rss = rte_le_to_cpu_32(rxcmp->rss_hash);
 677                 ol_flags |= PKT_RX_RSS_HASH;
 678         }
 679
 680 #ifdef RTE_LIBRTE_IEEE1588
 681         if (unlikely((flags_type & RX_PKT_CMPL_FLAGS_MASK) ==
 682                      RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP))
 683                 ol_flags |= PKT_RX_IEEE1588_PTP | PKT_RX_IEEE1588_TMST;
 684 #endif
 685
 686         mbuf->ol_flags = ol_flags;
 687 }
 688
 689 #ifdef RTE_LIBRTE_IEEE1588
 690 static void
 691 bnxt_get_rx_ts_p5(struct bnxt *bp, uint32_t rx_ts_cmpl)
 692 {
 693         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 694         uint64_t last_hwrm_time;
 695         uint64_t pkt_time = 0;
 696
 697         if (!BNXT_CHIP_P5(bp) || !ptp)
 698                 return;
 699
 700         /* On Thor, Rx timestamps are provided directly in the
 701          * Rx completion records to the driver. Only 32 bits of
 702          * the timestamp is present in the completion. Driver needs
 703          * to read the current 48 bit free running timer using the
 704          * HWRM_PORT_TS_QUERY command and combine the upper 16 bits
 705          * from the HWRM response with the lower 32 bits in the
 706          * Rx completion to produce the 48 bit timestamp for the Rx packet
 707          */
 708         last_hwrm_time = ptp->current_time;
 709         pkt_time = (last_hwrm_time & BNXT_PTP_CURRENT_TIME_MASK) | rx_ts_cmpl;
 710         if (rx_ts_cmpl < (uint32_t)last_hwrm_time) {
 711                 /* timer has rolled over */
 712                 pkt_time += (1ULL << 32);
 713         }
 714         ptp->rx_timestamp = pkt_time;
 715 }
 716 #endif
 717
 718 static uint32_t
 719 bnxt_ulp_set_mark_in_mbuf(struct bnxt *bp, struct rx_pkt_cmpl_hi *rxcmp1,
 720                           struct rte_mbuf *mbuf, uint32_t *vfr_flag)
 721 {
 722         uint32_t cfa_code;
 723         uint32_t meta_fmt;
 724         uint32_t meta;
 725         bool gfid = false;
 726         uint32_t mark_id;
 727         uint32_t flags2;
 728         uint32_t gfid_support = 0;
 729         int rc;
 730
 731         if (BNXT_GFID_ENABLED(bp))
 732                 gfid_support = 1;
 733
 734         cfa_code = rte_le_to_cpu_16(rxcmp1->cfa_code);
 735         flags2 = rte_le_to_cpu_32(rxcmp1->flags2);
 736         meta = rte_le_to_cpu_32(rxcmp1->metadata);
 737
 738         /*
 739          * The flags field holds extra bits of info from [6:4]
 740          * which indicate if the flow is in TCAM or EM or EEM
 741          */
 742         meta_fmt = (flags2 & BNXT_CFA_META_FMT_MASK) >>
 743                 BNXT_CFA_META_FMT_SHFT;
 744
 745         switch (meta_fmt) {
 746         case 0:
 747                 if (gfid_support) {
 748                         /* Not an LFID or GFID, a flush cmd. */
 749                         goto skip_mark;
 750                 } else {
 751                         /* LFID mode, no vlan scenario */
 752                         gfid = false;
 753                 }
 754                 break;
 755         case 4:
 756         case 5:
 757                 /*
 758                  * EM/TCAM case
 759                  * Assume that EM doesn't support Mark due to GFID
 760                  * collisions with EEM.  Simply return without setting the mark
 761                  * in the mbuf.
 762                  */
 763                 if (BNXT_CFA_META_EM_TEST(meta)) {
 764                         /*This is EM hit {EM(1), GFID[27:16], 19'd0 or vtag } */
 765                         gfid = true;
 766                         meta >>= BNXT_RX_META_CFA_CODE_SHIFT;
 767                         cfa_code |= meta << BNXT_CFA_CODE_META_SHIFT;
 768                 } else {
 769                         /*
 770                          * It is a TCAM entry, so it is an LFID.
 771                          * The TCAM IDX and Mode can also be determined
 772                          * by decoding the meta_data. We are not
 773                          * using these for now.
 774                          */
 775                 }
 776                 break;
 777         case 6:
 778         case 7:
 779                 /* EEM Case, only using gfid in EEM for now. */
 780                 gfid = true;
 781
 782                 /*
 783                  * For EEM flows, The first part of cfa_code is 16 bits.
 784                  * The second part is embedded in the
 785                  * metadata field from bit 19 onwards. The driver needs to
 786                  * ignore the first 19 bits of metadata and use the next 12
 787                  * bits as higher 12 bits of cfa_code.
 788                  */
 789                 meta >>= BNXT_RX_META_CFA_CODE_SHIFT;
 790                 cfa_code |= meta << BNXT_CFA_CODE_META_SHIFT;
 791                 break;
 792         default:
 793                 /* For other values, the cfa_code is assumed to be an LFID. */
 794                 break;
 795         }
 796
 797         rc = ulp_mark_db_mark_get(bp->ulp_ctx, gfid,
 798                                   cfa_code, vfr_flag, &mark_id);
 799         if (!rc) {
 800                 /* VF to VFR Rx path. So, skip mark_id injection in mbuf */
 801                 if (vfr_flag && *vfr_flag)
 802                         return mark_id;
 803                 /* Got the mark, write it to the mbuf and return */
 804                 mbuf->hash.fdir.hi = mark_id;
 805                 *bnxt_cfa_code_dynfield(mbuf) = cfa_code & 0xffffffffull;
 806                 mbuf->hash.fdir.id = rxcmp1->cfa_code;
 807                 mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 808                 return mark_id;
 809         }
 810
 811 skip_mark:
 812         mbuf->hash.fdir.hi = 0;
 813         mbuf->hash.fdir.id = 0;
 814
 815         return 0;
 816 }
 817
 818 void bnxt_set_mark_in_mbuf(struct bnxt *bp,
 819                            struct rx_pkt_cmpl_hi *rxcmp1,
 820                            struct rte_mbuf *mbuf)
 821 {
 822         uint32_t cfa_code = 0;
 823         uint8_t meta_fmt = 0;
 824         uint16_t flags2 = 0;
 825         uint32_t meta =  0;
 826
 827         cfa_code = rte_le_to_cpu_16(rxcmp1->cfa_code);
 828         if (!cfa_code)
 829                 return;
 830
 831         if (cfa_code && !bp->mark_table[cfa_code].valid)
 832                 return;
 833
 834         flags2 = rte_le_to_cpu_16(rxcmp1->flags2);
 835         meta = rte_le_to_cpu_32(rxcmp1->metadata);
 836         if (meta) {
 837                 meta >>= BNXT_RX_META_CFA_CODE_SHIFT;
 838
 839                 /* The flags field holds extra bits of info from [6:4]
 840                  * which indicate if the flow is in TCAM or EM or EEM
 841                  */
 842                 meta_fmt = (flags2 & BNXT_CFA_META_FMT_MASK) >>
 843                            BNXT_CFA_META_FMT_SHFT;
 844
 845                 /* meta_fmt == 4 => 'b100 => 'b10x => EM.
 846                  * meta_fmt == 5 => 'b101 => 'b10x => EM + VLAN
 847                  * meta_fmt == 6 => 'b110 => 'b11x => EEM
 848                  * meta_fmt == 7 => 'b111 => 'b11x => EEM + VLAN.
 849                  */
 850                 meta_fmt >>= BNXT_CFA_META_FMT_EM_EEM_SHFT;
 851         }
 852
 853         mbuf->hash.fdir.hi = bp->mark_table[cfa_code].mark_id;
 854         mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 855 }
 856
 857 static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
 858                        struct bnxt_rx_queue *rxq, uint32_t *raw_cons)
 859 {
 860         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
 861         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
 862         struct rx_pkt_cmpl *rxcmp;
 863         struct rx_pkt_cmpl_hi *rxcmp1;
 864         uint32_t tmp_raw_cons = *raw_cons;
 865         uint16_t cons, raw_prod, cp_cons =
 866             RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);
 867         struct rte_mbuf *mbuf;
 868         int rc = 0;
 869         uint8_t agg_buf = 0;
 870         uint16_t cmp_type;
 871         uint32_t vfr_flag = 0, mark_id = 0;
 872         struct bnxt *bp = rxq->bp;
 873
 874         rxcmp = (struct rx_pkt_cmpl *)
 875             &cpr->cp_desc_ring[cp_cons];
 876
 877         cmp_type = CMP_TYPE(rxcmp);
 878
 879         if (cmp_type == RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG) {
 880                 struct rx_tpa_v2_abuf_cmpl *rx_agg = (void *)rxcmp;
 881                 uint16_t agg_id = rte_cpu_to_le_16(rx_agg->agg_id);
 882                 struct bnxt_tpa_info *tpa_info;
 883
 884                 tpa_info = &rxr->tpa_info[agg_id];
 885                 RTE_ASSERT(tpa_info->agg_count < 16);
 886                 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg;
 887                 rc = -EINVAL; /* Continue w/o new mbuf */
 888                 goto next_rx;
 889         }
 890
 891         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
 892         cp_cons = RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);
 893         rxcmp1 = (struct rx_pkt_cmpl_hi *)&cpr->cp_desc_ring[cp_cons];
 894
 895         if (!CMP_VALID(rxcmp1, tmp_raw_cons, cpr->cp_ring_struct))
 896                 return -EBUSY;
 897
 898         if (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START ||
 899             cmp_type == RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2) {
 900                 bnxt_tpa_start(rxq, (struct rx_tpa_start_cmpl *)rxcmp,
 901                                (struct rx_tpa_start_cmpl_hi *)rxcmp1);
 902                 rc = -EINVAL; /* Continue w/o new mbuf */
 903                 goto next_rx;
 904         } else if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
 905                 mbuf = bnxt_tpa_end(rxq, &tmp_raw_cons,
 906                                    (struct rx_tpa_end_cmpl *)rxcmp,
 907                                    (struct rx_tpa_end_cmpl_hi *)rxcmp1);
 908                 if (unlikely(!mbuf))
 909                         return -EBUSY;
 910                 *rx_pkt = mbuf;
 911                 goto next_rx;
 912         } else if ((cmp_type != CMPL_BASE_TYPE_RX_L2) &&
 913                    (cmp_type != CMPL_BASE_TYPE_RX_L2_V2)) {
 914                 rc = -EINVAL;
 915                 goto next_rx;
 916         }
 917
 918         agg_buf = BNXT_RX_L2_AGG_BUFS(rxcmp);
 919         if (agg_buf && !bnxt_agg_bufs_valid(cpr, agg_buf, tmp_raw_cons))
 920                 return -EBUSY;
 921
 922         raw_prod = rxr->rx_raw_prod;
 923
 924         cons = rxcmp->opaque;
 925         if (unlikely(cons != rxr->rx_next_cons)) {
 926                 bnxt_discard_rx(bp, cpr, &tmp_raw_cons, rxcmp);
 927                 PMD_DRV_LOG(ERR, "RX cons %x != expected cons %x\n",
 928                             cons, rxr->rx_next_cons);
 929                 bnxt_sched_ring_reset(rxq);
 930                 rc = -EBUSY;
 931                 goto next_rx;
 932         }
 933         mbuf = bnxt_consume_rx_buf(rxr, cons);
 934         if (mbuf == NULL)
 935                 return -EBUSY;
 936
 937         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 938         mbuf->nb_segs = 1;
 939         mbuf->next = NULL;
 940         mbuf->pkt_len = rxcmp->len;
 941         mbuf->data_len = mbuf->pkt_len;
 942         mbuf->port = rxq->port_id;
 943
 944 #ifdef RTE_LIBRTE_IEEE1588
 945         if (unlikely((rte_le_to_cpu_16(rxcmp->flags_type) &
 946                       RX_PKT_CMPL_FLAGS_MASK) ==
 947                      RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP))
 948                 bnxt_get_rx_ts_p5(rxq->bp, rxcmp1->reorder);
 949 #endif
 950
 951         if (cmp_type == CMPL_BASE_TYPE_RX_L2_V2) {
 952                 bnxt_parse_csum_v2(mbuf, rxcmp1);
 953                 bnxt_parse_pkt_type_v2(mbuf, rxcmp, rxcmp1);
 954                 bnxt_rx_vlan_v2(mbuf, rxcmp, rxcmp1);
 955                 /* TODO Add support for cfa_code parsing */
 956                 goto reuse_rx_mbuf;
 957         }
 958
 959         bnxt_set_ol_flags(rxr, rxcmp, rxcmp1, mbuf);
 960
 961         mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
 962
 963         if (BNXT_TRUFLOW_EN(bp))
 964                 mark_id = bnxt_ulp_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf,
 965                                                     &vfr_flag);
 966         else
 967                 bnxt_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf);
 968
 969 reuse_rx_mbuf:
 970         if (agg_buf)
 971                 bnxt_rx_pages(rxq, mbuf, &tmp_raw_cons, agg_buf, NULL);
 972
 973 #ifdef BNXT_DEBUG
 974         if (rxcmp1->errors_v2 & RX_CMP_L2_ERRORS) {
 975                 /* Re-install the mbuf back to the rx ring */
 976                 bnxt_reuse_rx_mbuf(rxr, cons, mbuf);
 977
 978                 rc = -EIO;
 979                 goto next_rx;
 980         }
 981 #endif
 982         /*
 983          * TODO: Redesign this....
 984          * If the allocation fails, the packet does not get received.
 985          * Simply returning this will result in slowly falling behind
 986          * on the producer ring buffers.
 987          * Instead, "filling up" the producer just before ringing the
 988          * doorbell could be a better solution since it will let the
 989          * producer ring starve until memory is available again pushing
 990          * the drops into hardware and getting them out of the driver
 991          * allowing recovery to a full producer ring.
 992          *
 993          * This could also help with cache usage by preventing per-packet
 994          * calls in favour of a tight loop with the same function being called
 995          * in it.
 996          */
 997         raw_prod = RING_NEXT(raw_prod);
 998         if (bnxt_alloc_rx_data(rxq, rxr, raw_prod)) {
 999                 PMD_DRV_LOG(ERR, "mbuf alloc failed with prod=0x%x\n",
1000                             raw_prod);
1001                 rc = -ENOMEM;
1002                 goto rx;
1003         }
1004         rxr->rx_raw_prod = raw_prod;
1005         rxr->rx_next_cons = RING_IDX(rxr->rx_ring_struct, RING_NEXT(cons));
1006
1007         if (BNXT_TRUFLOW_EN(bp) && (BNXT_VF_IS_TRUSTED(bp) || BNXT_PF(bp)) &&
1008             vfr_flag) {
1009                 bnxt_vfr_recv(mark_id, rxq->queue_id, mbuf);
1010                 /* Now return an error so that nb_rx_pkts is not
1011                  * incremented.
1012                  * This packet was meant to be given to the representor.
1013                  * So no need to account the packet and give it to
1014                  * parent Rx burst function.
1015                  */
1016                 rc = -ENODEV;
1017                 goto next_rx;
1018         }
1019         /*
1020          * All MBUFs are allocated with the same size under DPDK,
1021          * no optimization for rx_copy_thresh
1022          */
1023 rx:
1024         *rx_pkt = mbuf;
1025
1026 next_rx:
1027
1028         *raw_cons = tmp_raw_cons;
1029
1030         return rc;
1031 }
1032
1033 uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1034                                uint16_t nb_pkts)
1035 {
1036         struct bnxt_rx_queue *rxq = rx_queue;
1037         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1038         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1039         uint16_t rx_raw_prod = rxr->rx_raw_prod;
1040         uint16_t ag_raw_prod = rxr->ag_raw_prod;
1041         uint32_t raw_cons = cpr->cp_raw_cons;
1042         bool alloc_failed = false;
1043         uint32_t cons;
1044         int nb_rx_pkts = 0;
1045         int nb_rep_rx_pkts = 0;
1046         struct rx_pkt_cmpl *rxcmp;
1047         int rc = 0;
1048         bool evt = false;
1049
1050         if (unlikely(is_bnxt_in_error(rxq->bp)))
1051                 return 0;
1052
1053         /* If Rx Q was stopped return */
1054         if (unlikely(!rxq->rx_started))
1055                 return 0;
1056
1057 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1058         /*
1059          * Replenish buffers if needed when a transition has been made from
1060          * vector- to non-vector- receive processing.
1061          */
1062         while (unlikely(rxq->rxrearm_nb)) {
1063                 if (!bnxt_alloc_rx_data(rxq, rxr, rxq->rxrearm_start)) {
1064                         rxr->rx_raw_prod = rxq->rxrearm_start;
1065                         bnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);
1066                         rxq->rxrearm_start++;
1067                         rxq->rxrearm_nb--;
1068                 } else {
1069                         /* Retry allocation on next call. */
1070                         break;
1071                 }
1072         }
1073 #endif
1074
1075         /* Handle RX burst request */
1076         while (1) {
1077                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1078                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1079
1080                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
1081                         break;
1082                 if (CMP_TYPE(rxcmp) == CMPL_BASE_TYPE_HWRM_DONE) {
1083                         PMD_DRV_LOG(ERR, "Rx flush done\n");
1084                 } else if ((CMP_TYPE(rxcmp) >= CMPL_BASE_TYPE_RX_TPA_START_V2) &&
1085                      (CMP_TYPE(rxcmp) <= RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG)) {
1086                         rc = bnxt_rx_pkt(&rx_pkts[nb_rx_pkts], rxq, &raw_cons);
1087                         if (!rc)
1088                                 nb_rx_pkts++;
1089                         else if (rc == -EBUSY)  /* partial completion */
1090                                 break;
1091                         else if (rc == -ENODEV) /* completion for representor */
1092                                 nb_rep_rx_pkts++;
1093                         else if (rc == -ENOMEM) {
1094                                 nb_rx_pkts++;
1095                                 alloc_failed = true;
1096                         }
1097                 } else if (!BNXT_NUM_ASYNC_CPR(rxq->bp)) {
1098                         evt =
1099                         bnxt_event_hwrm_resp_handler(rxq->bp,
1100                                                      (struct cmpl_base *)rxcmp);
1101                         /* If the async event is Fatal error, return */
1102                         if (unlikely(is_bnxt_in_error(rxq->bp)))
1103                                 goto done;
1104                 }
1105
1106                 raw_cons = NEXT_RAW_CMP(raw_cons);
1107                 if (nb_rx_pkts == nb_pkts || nb_rep_rx_pkts == nb_pkts || evt)
1108                         break;
1109         }
1110
1111         cpr->cp_raw_cons = raw_cons;
1112         if (!nb_rx_pkts && !nb_rep_rx_pkts && !evt) {
1113                 /*
1114                  * For PMD, there is no need to keep on pushing to REARM
1115                  * the doorbell if there are no new completions
1116                  */
1117                 goto done;
1118         }
1119
1120         /* Ring the completion queue doorbell. */
1121         bnxt_db_cq(cpr);
1122
1123         /* Ring the receive descriptor doorbell. */
1124         if (rx_raw_prod != rxr->rx_raw_prod)
1125                 bnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);
1126
1127         /* Ring the AGG ring DB */
1128         if (ag_raw_prod != rxr->ag_raw_prod)
1129                 bnxt_db_write(&rxr->ag_db, rxr->ag_raw_prod);
1130
1131         /* Attempt to alloc Rx buf in case of a previous allocation failure. */
1132         if (alloc_failed) {
1133                 int cnt;
1134
1135                 rx_raw_prod = RING_NEXT(rx_raw_prod);
1136                 for (cnt = 0; cnt < nb_rx_pkts + nb_rep_rx_pkts; cnt++) {
1137                         struct rte_mbuf **rx_buf;
1138                         uint16_t ndx;
1139
1140                         ndx = RING_IDX(rxr->rx_ring_struct, rx_raw_prod + cnt);
1141                         rx_buf = &rxr->rx_buf_ring[ndx];
1142
1143                         /* Buffer already allocated for this index. */
1144                         if (*rx_buf != NULL && *rx_buf != &rxq->fake_mbuf)
1145                                 continue;
1146
1147                         /* This slot is empty. Alloc buffer for Rx */
1148                         if (!bnxt_alloc_rx_data(rxq, rxr, rx_raw_prod + cnt)) {
1149                                 rxr->rx_raw_prod = rx_raw_prod + cnt;
1150                                 bnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);
1151                         } else {
1152                                 PMD_DRV_LOG(ERR, "Alloc  mbuf failed\n");
1153                                 break;
1154                         }
1155                 }
1156         }
1157
1158 done:
1159         return nb_rx_pkts;
1160 }
1161
1162 /*
1163  * Dummy DPDK callback for RX.
1164  *
1165  * This function is used to temporarily replace the real callback during
1166  * unsafe control operations on the queue, or in case of error.
1167  */
1168 uint16_t
1169 bnxt_dummy_recv_pkts(void *rx_queue __rte_unused,
1170                      struct rte_mbuf **rx_pkts __rte_unused,
1171                      uint16_t nb_pkts __rte_unused)
1172 {
1173         return 0;
1174 }
1175
1176 void bnxt_free_rx_rings(struct bnxt *bp)
1177 {
1178         int i;
1179         struct bnxt_rx_queue *rxq;
1180
1181         if (!bp->rx_queues)
1182                 return;
1183
1184         for (i = 0; i < (int)bp->rx_nr_rings; i++) {
1185                 rxq = bp->rx_queues[i];
1186                 if (!rxq)
1187                         continue;
1188
1189                 bnxt_free_ring(rxq->rx_ring->rx_ring_struct);
1190                 rte_free(rxq->rx_ring->rx_ring_struct);
1191
1192                 /* Free the Aggregator ring */
1193                 bnxt_free_ring(rxq->rx_ring->ag_ring_struct);
1194                 rte_free(rxq->rx_ring->ag_ring_struct);
1195                 rxq->rx_ring->ag_ring_struct = NULL;
1196
1197                 rte_free(rxq->rx_ring);
1198
1199                 bnxt_free_ring(rxq->cp_ring->cp_ring_struct);
1200                 rte_free(rxq->cp_ring->cp_ring_struct);
1201                 rte_free(rxq->cp_ring);
1202
1203                 rte_free(rxq);
1204                 bp->rx_queues[i] = NULL;
1205         }
1206 }
1207
1208 int bnxt_init_rx_ring_struct(struct bnxt_rx_queue *rxq, unsigned int socket_id)
1209 {
1210         struct bnxt_cp_ring_info *cpr;
1211         struct bnxt_rx_ring_info *rxr;
1212         struct bnxt_ring *ring;
1213
1214         rxq->rx_buf_size = BNXT_MAX_PKT_LEN + sizeof(struct rte_mbuf);
1215
1216         rxr = rte_zmalloc_socket("bnxt_rx_ring",
1217                                  sizeof(struct bnxt_rx_ring_info),
1218                                  RTE_CACHE_LINE_SIZE, socket_id);
1219         if (rxr == NULL)
1220                 return -ENOMEM;
1221         rxq->rx_ring = rxr;
1222
1223         ring = rte_zmalloc_socket("bnxt_rx_ring_struct",
1224                                    sizeof(struct bnxt_ring),
1225                                    RTE_CACHE_LINE_SIZE, socket_id);
1226         if (ring == NULL)
1227                 return -ENOMEM;
1228         rxr->rx_ring_struct = ring;
1229         ring->ring_size = rte_align32pow2(rxq->nb_rx_desc);
1230         ring->ring_mask = ring->ring_size - 1;
1231         ring->bd = (void *)rxr->rx_desc_ring;
1232         ring->bd_dma = rxr->rx_desc_mapping;
1233
1234         /* Allocate extra rx ring entries for vector rx. */
1235         ring->vmem_size = sizeof(struct rte_mbuf *) *
1236                           (ring->ring_size + BNXT_RX_EXTRA_MBUF_ENTRIES);
1237
1238         ring->vmem = (void **)&rxr->rx_buf_ring;
1239         ring->fw_ring_id = INVALID_HW_RING_ID;
1240
1241         cpr = rte_zmalloc_socket("bnxt_rx_ring",
1242                                  sizeof(struct bnxt_cp_ring_info),
1243                                  RTE_CACHE_LINE_SIZE, socket_id);
1244         if (cpr == NULL)
1245                 return -ENOMEM;
1246         rxq->cp_ring = cpr;
1247
1248         ring = rte_zmalloc_socket("bnxt_rx_ring_struct",
1249                                    sizeof(struct bnxt_ring),
1250                                    RTE_CACHE_LINE_SIZE, socket_id);
1251         if (ring == NULL)
1252                 return -ENOMEM;
1253         cpr->cp_ring_struct = ring;
1254
1255         /* Allocate two completion slots per entry in desc ring. */
1256         ring->ring_size = rxr->rx_ring_struct->ring_size * 2;
1257         ring->ring_size *= AGG_RING_SIZE_FACTOR;
1258
1259         ring->ring_size = rte_align32pow2(ring->ring_size);
1260         ring->ring_mask = ring->ring_size - 1;
1261         ring->bd = (void *)cpr->cp_desc_ring;
1262         ring->bd_dma = cpr->cp_desc_mapping;
1263         ring->vmem_size = 0;
1264         ring->vmem = NULL;
1265         ring->fw_ring_id = INVALID_HW_RING_ID;
1266
1267         /* Allocate Aggregator rings */
1268         ring = rte_zmalloc_socket("bnxt_rx_ring_struct",
1269                                    sizeof(struct bnxt_ring),
1270                                    RTE_CACHE_LINE_SIZE, socket_id);
1271         if (ring == NULL)
1272                 return -ENOMEM;
1273         rxr->ag_ring_struct = ring;
1274         ring->ring_size = rte_align32pow2(rxq->nb_rx_desc *
1275                                           AGG_RING_SIZE_FACTOR);
1276         ring->ring_mask = ring->ring_size - 1;
1277         ring->bd = (void *)rxr->ag_desc_ring;
1278         ring->bd_dma = rxr->ag_desc_mapping;
1279         ring->vmem_size = ring->ring_size * sizeof(struct rte_mbuf *);
1280         ring->vmem = (void **)&rxr->ag_buf_ring;
1281         ring->fw_ring_id = INVALID_HW_RING_ID;
1282
1283         return 0;
1284 }
1285
1286 static void bnxt_init_rxbds(struct bnxt_ring *ring, uint32_t type,
1287                             uint16_t len)
1288 {
1289         uint32_t j;
1290         struct rx_prod_pkt_bd *rx_bd_ring = (struct rx_prod_pkt_bd *)ring->bd;
1291
1292         if (!rx_bd_ring)
1293                 return;
1294         for (j = 0; j < ring->ring_size; j++) {
1295                 rx_bd_ring[j].flags_type = rte_cpu_to_le_16(type);
1296                 rx_bd_ring[j].len = rte_cpu_to_le_16(len);
1297                 rx_bd_ring[j].opaque = j;
1298         }
1299 }
1300
1301 int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq)
1302 {
1303         struct bnxt_rx_ring_info *rxr;
1304         struct bnxt_ring *ring;
1305         uint32_t raw_prod, type;
1306         unsigned int i;
1307         uint16_t size;
1308
1309         /* Initialize packet type table. */
1310         bnxt_init_ptype_table();
1311
1312         size = rte_pktmbuf_data_room_size(rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
1313         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
1314
1315         type = RX_PROD_PKT_BD_TYPE_RX_PROD_PKT;
1316
1317         rxr = rxq->rx_ring;
1318         ring = rxr->rx_ring_struct;
1319         bnxt_init_rxbds(ring, type, size);
1320
1321         /* Initialize offload flags parsing table. */
1322         bnxt_init_ol_flags_tables(rxq);
1323
1324         raw_prod = rxr->rx_raw_prod;
1325         for (i = 0; i < ring->ring_size; i++) {
1326                 if (unlikely(!rxr->rx_buf_ring[i])) {
1327                         if (bnxt_alloc_rx_data(rxq, rxr, raw_prod) != 0) {
1328                                 PMD_DRV_LOG(WARNING,
1329                                             "init'ed rx ring %d with %d/%d mbufs only\n",
1330                                             rxq->queue_id, i, ring->ring_size);
1331                                 break;
1332                         }
1333                 }
1334                 rxr->rx_raw_prod = raw_prod;
1335                 raw_prod = RING_NEXT(raw_prod);
1336         }
1337
1338         /* Initialize dummy mbuf pointers for vector mode rx. */
1339         for (i = ring->ring_size;
1340              i < ring->ring_size + BNXT_RX_EXTRA_MBUF_ENTRIES; i++) {
1341                 rxr->rx_buf_ring[i] = &rxq->fake_mbuf;
1342         }
1343
1344         ring = rxr->ag_ring_struct;
1345         type = RX_PROD_AGG_BD_TYPE_RX_PROD_AGG;
1346         bnxt_init_rxbds(ring, type, size);
1347         raw_prod = rxr->ag_raw_prod;
1348
1349         for (i = 0; i < ring->ring_size; i++) {
1350                 if (unlikely(!rxr->ag_buf_ring[i])) {
1351                         if (bnxt_alloc_ag_data(rxq, rxr, raw_prod) != 0) {
1352                                 PMD_DRV_LOG(WARNING,
1353                                             "init'ed AG ring %d with %d/%d mbufs only\n",
1354                                             rxq->queue_id, i, ring->ring_size);
1355                                 break;
1356                         }
1357                 }
1358                 rxr->ag_raw_prod = raw_prod;
1359                 raw_prod = RING_NEXT(raw_prod);
1360         }
1361         PMD_DRV_LOG(DEBUG, "AGG Done!\n");
1362
1363         if (rxr->tpa_info) {
1364                 unsigned int max_aggs = BNXT_TPA_MAX_AGGS(rxq->bp);
1365
1366                 for (i = 0; i < max_aggs; i++) {
1367                         if (unlikely(!rxr->tpa_info[i].mbuf)) {
1368                                 rxr->tpa_info[i].mbuf =
1369                                         __bnxt_alloc_rx_data(rxq->mb_pool);
1370                                 if (!rxr->tpa_info[i].mbuf) {
1371                                         rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
1372                                         return -ENOMEM;
1373                                 }
1374                         }
1375                 }
1376         }
1377         PMD_DRV_LOG(DEBUG, "TPA alloc Done!\n");
1378
1379         return 0;
1380 }
1381
1382 /* Sweep the Rx completion queue till HWRM_DONE for ring flush is received.
1383  * The mbufs will not be freed in this call.
1384  * They will be freed during ring free as a part of mem cleanup.
1385  */
1386 int bnxt_flush_rx_cmp(struct bnxt_cp_ring_info *cpr)
1387 {
1388         struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
1389         uint32_t ring_mask = cp_ring_struct->ring_mask;
1390         uint32_t raw_cons = cpr->cp_raw_cons;
1391         struct rx_pkt_cmpl *rxcmp;
1392         uint32_t nb_rx = 0;
1393         uint32_t cons;
1394
1395         do {
1396                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1397                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1398
1399                 if (CMP_TYPE(rxcmp) == CMPL_BASE_TYPE_HWRM_DONE)
1400                         return 1;
1401
1402                 raw_cons = NEXT_RAW_CMP(raw_cons);
1403                 nb_rx++;
1404         } while (nb_rx < ring_mask);
1405
1406         cpr->cp_raw_cons = raw_cons;
1407
1408         /* Ring the completion queue doorbell. */
1409         bnxt_db_cq(cpr);
1410
1411         return 0;
1412 }