1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Broadcom All rights reserved. */
7 #include <rte_bitmap.h>
8 #include <rte_byteorder.h>
9 #include <rte_malloc.h>
10 #include <rte_memory.h>
15 #include "bnxt_ring.h"
18 #include "hsi_struct_def_dpdk.h"
19 #include "bnxt_rxtx_vec_common.h"
29 bnxt_rxq_rearm(struct bnxt_rx_queue *rxq, struct bnxt_rx_ring_info *rxr)
31 struct rx_prod_pkt_bd *rxbds = &rxr->rx_desc_ring[rxq->rxrearm_start];
32 struct bnxt_sw_rx_bd *rx_bufs = &rxr->rx_buf_ring[rxq->rxrearm_start];
33 struct rte_mbuf *mb0, *mb1;
36 const uint64x2_t hdr_room = {0, RTE_PKTMBUF_HEADROOM};
37 const uint64x2_t addrmask = {0, UINT64_MAX};
39 /* Pull RTE_BNXT_RXQ_REARM_THRESH more mbufs into the software ring */
40 if (rte_mempool_get_bulk(rxq->mb_pool,
42 RTE_BNXT_RXQ_REARM_THRESH) < 0) {
43 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
44 RTE_BNXT_RXQ_REARM_THRESH;
49 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
50 for (i = 0; i < RTE_BNXT_RXQ_REARM_THRESH; i += 2, rx_bufs += 2) {
51 uint64x2_t buf_addr0, buf_addr1;
52 uint64x2_t rxbd0, rxbd1;
54 mb0 = rx_bufs[0].mbuf;
55 mb1 = rx_bufs[1].mbuf;
57 /* Load address fields from both mbufs */
58 buf_addr0 = vld1q_u64((uint64_t *)&mb0->buf_addr);
59 buf_addr1 = vld1q_u64((uint64_t *)&mb1->buf_addr);
61 /* Load both rx descriptors (preserving some existing fields) */
62 rxbd0 = vld1q_u64((uint64_t *)(rxbds + 0));
63 rxbd1 = vld1q_u64((uint64_t *)(rxbds + 1));
65 /* Add default offset to buffer address. */
66 buf_addr0 = vaddq_u64(buf_addr0, hdr_room);
67 buf_addr1 = vaddq_u64(buf_addr1, hdr_room);
69 /* Clear all fields except address. */
70 buf_addr0 = vandq_u64(buf_addr0, addrmask);
71 buf_addr1 = vandq_u64(buf_addr1, addrmask);
73 /* Clear address field in descriptor. */
74 rxbd0 = vbicq_u64(rxbd0, addrmask);
75 rxbd1 = vbicq_u64(rxbd1, addrmask);
77 /* Set address field in descriptor. */
78 rxbd0 = vaddq_u64(rxbd0, buf_addr0);
79 rxbd1 = vaddq_u64(rxbd1, buf_addr1);
81 /* Store descriptors to memory. */
82 vst1q_u64((uint64_t *)(rxbds++), rxbd0);
83 vst1q_u64((uint64_t *)(rxbds++), rxbd1);
86 rxq->rxrearm_start += RTE_BNXT_RXQ_REARM_THRESH;
87 bnxt_db_write(&rxr->rx_db, rxq->rxrearm_start - 1);
88 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
89 rxq->rxrearm_start = 0;
91 rxq->rxrearm_nb -= RTE_BNXT_RXQ_REARM_THRESH;
95 bnxt_parse_pkt_type(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1)
97 uint32_t l3, pkt_type = 0;
98 uint32_t t_ipcs = 0, ip6 = 0, vlan = 0;
101 vlan = !!(rxcmp1->flags2 &
102 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN));
103 pkt_type |= vlan ? RTE_PTYPE_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER;
105 t_ipcs = !!(rxcmp1->flags2 &
106 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC));
107 ip6 = !!(rxcmp1->flags2 &
108 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_TYPE));
110 flags_type = rxcmp->flags_type &
111 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS_ITYPE_MASK);
114 l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
115 else if (!t_ipcs && ip6)
116 l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
117 else if (t_ipcs && !ip6)
118 l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
120 l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
122 switch (flags_type) {
123 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_ICMP):
125 pkt_type |= l3 | RTE_PTYPE_L4_ICMP;
127 pkt_type |= l3 | RTE_PTYPE_INNER_L4_ICMP;
130 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_TCP):
132 pkt_type |= l3 | RTE_PTYPE_L4_TCP;
134 pkt_type |= l3 | RTE_PTYPE_INNER_L4_TCP;
137 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_UDP):
139 pkt_type |= l3 | RTE_PTYPE_L4_UDP;
141 pkt_type |= l3 | RTE_PTYPE_INNER_L4_UDP;
144 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_IP):
153 bnxt_parse_csum(struct rte_mbuf *mbuf, struct rx_pkt_cmpl_hi *rxcmp1)
157 flags = flags2_0xf(rxcmp1);
159 if (likely(IS_IP_NONTUNNEL_PKT(flags))) {
160 if (unlikely(RX_CMP_IP_CS_ERROR(rxcmp1)))
161 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
163 mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
164 } else if (IS_IP_TUNNEL_PKT(flags)) {
165 if (unlikely(RX_CMP_IP_OUTER_CS_ERROR(rxcmp1) ||
166 RX_CMP_IP_CS_ERROR(rxcmp1)))
167 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
169 mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
170 } else if (unlikely(RX_CMP_IP_CS_UNKNOWN(rxcmp1))) {
171 mbuf->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN;
175 if (likely(IS_L4_NONTUNNEL_PKT(flags))) {
176 if (unlikely(RX_CMP_L4_INNER_CS_ERR2(rxcmp1)))
177 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
179 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
180 } else if (IS_L4_TUNNEL_PKT(flags)) {
181 if (unlikely(RX_CMP_L4_INNER_CS_ERR2(rxcmp1)))
182 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
184 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
185 if (unlikely(RX_CMP_L4_OUTER_CS_ERR2(rxcmp1))) {
186 mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
187 } else if (unlikely(IS_L4_TUNNEL_PKT_ONLY_INNER_L4_CS
189 mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_UNKNOWN;
191 mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
193 } else if (unlikely(RX_CMP_L4_CS_UNKNOWN(rxcmp1))) {
194 mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
199 bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
202 struct bnxt_rx_queue *rxq = rx_queue;
203 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
204 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
205 uint32_t raw_cons = cpr->cp_raw_cons;
208 struct rx_pkt_cmpl *rxcmp;
210 const uint64x2_t mbuf_init = {rxq->mbuf_initializer, 0};
211 const uint8x16_t shuf_msk = {
212 0xFF, 0xFF, 0xFF, 0xFF, /* pkt_type (zeroes) */
213 2, 3, 0xFF, 0xFF, /* pkt_len */
215 0xFF, 0xFF, /* vlan_tci (zeroes) */
216 12, 13, 14, 15 /* rss hash */
219 /* If Rx Q was stopped return */
220 if (unlikely(!rxq->rx_started))
223 if (rxq->rxrearm_nb >= RTE_BNXT_RXQ_REARM_THRESH)
224 bnxt_rxq_rearm(rxq, rxr);
226 /* Return no more than RTE_BNXT_MAX_RX_BURST per call. */
227 nb_pkts = RTE_MIN(nb_pkts, RTE_BNXT_MAX_RX_BURST);
229 /* Make nb_pkts an integer multiple of RTE_BNXT_DESCS_PER_LOOP */
230 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_BNXT_DESCS_PER_LOOP);
234 /* Handle RX burst request */
236 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
238 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
240 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
243 if (likely(CMP_TYPE(rxcmp) == RX_PKT_CMPL_TYPE_RX_L2)) {
244 struct rx_pkt_cmpl_hi *rxcmp1;
245 uint32_t tmp_raw_cons;
247 struct rte_mbuf *mbuf;
251 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
252 cp_cons = RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);
253 rxcmp1 = (struct rx_pkt_cmpl_hi *)
254 &cpr->cp_desc_ring[cp_cons];
256 if (!CMP_VALID(rxcmp1, tmp_raw_cons,
257 cpr->cp_ring_struct))
260 raw_cons = tmp_raw_cons;
261 cons = rxcmp->opaque;
263 mbuf = rxr->rx_buf_ring[cons].mbuf;
265 rxr->rx_buf_ring[cons].mbuf = NULL;
267 /* Set constant fields from mbuf initializer. */
268 vst1q_u64((uint64_t *)&mbuf->rearm_data, mbuf_init);
270 /* Set mbuf pkt_len, data_len, and rss_hash fields. */
271 mm_rxcmp = vld1q_u64((uint64_t *)rxcmp);
272 pkt_mb = vqtbl1q_u8(vreinterpretq_u8_u64(mm_rxcmp),
274 vst1q_u64((uint64_t *)&mbuf->rx_descriptor_fields1,
275 vreinterpretq_u64_u8(pkt_mb));
277 rte_compiler_barrier();
279 if (rxcmp->flags_type & RX_PKT_CMPL_FLAGS_RSS_VALID)
280 mbuf->ol_flags |= PKT_RX_RSS_HASH;
283 RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN) {
284 mbuf->vlan_tci = rxcmp1->metadata &
285 (RX_PKT_CMPL_METADATA_VID_MASK |
286 RX_PKT_CMPL_METADATA_DE |
287 RX_PKT_CMPL_METADATA_PRI_MASK);
289 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
292 bnxt_parse_csum(mbuf, rxcmp1);
293 mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
295 rx_pkts[nb_rx_pkts++] = mbuf;
296 } else if (!BNXT_NUM_ASYNC_CPR(rxq->bp)) {
298 bnxt_event_hwrm_resp_handler(rxq->bp,
299 (struct cmpl_base *)rxcmp);
302 raw_cons = NEXT_RAW_CMP(raw_cons);
303 if (nb_rx_pkts == nb_pkts || evt)
306 rxr->rx_prod = RING_ADV(rxr->rx_ring_struct, rxr->rx_prod, nb_rx_pkts);
308 rxq->rxrearm_nb += nb_rx_pkts;
309 cpr->cp_raw_cons = raw_cons;
310 cpr->valid = !!(cpr->cp_raw_cons & cpr->cp_ring_struct->ring_size);
311 if (nb_rx_pkts || evt)
318 bnxt_tx_cmp_vec(struct bnxt_tx_queue *txq, int nr_pkts)
320 struct bnxt_tx_ring_info *txr = txq->tx_ring;
321 struct rte_mbuf **free = txq->free;
322 uint16_t cons = txr->tx_cons;
323 unsigned int blk = 0;
326 struct bnxt_sw_tx_bd *tx_buf;
327 struct rte_mbuf *mbuf;
329 tx_buf = &txr->tx_buf_ring[cons];
330 cons = RING_NEXT(txr->tx_ring_struct, cons);
331 mbuf = rte_pktmbuf_prefree_seg(tx_buf->mbuf);
334 if (blk && mbuf->pool != free[0]->pool) {
335 rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
341 rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
347 bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
349 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
350 uint32_t raw_cons = cpr->cp_raw_cons;
352 uint32_t nb_tx_pkts = 0;
353 struct tx_cmpl *txcmp;
354 struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
355 struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
356 uint32_t ring_mask = cp_ring_struct->ring_mask;
359 cons = RING_CMPL(ring_mask, raw_cons);
360 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
362 if (!CMP_VALID(txcmp, raw_cons, cp_ring_struct))
365 if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2))
366 nb_tx_pkts += txcmp->opaque;
369 "Unhandled CMP type %02x\n",
371 raw_cons = NEXT_RAW_CMP(raw_cons);
372 } while (nb_tx_pkts < ring_mask);
374 cpr->valid = !!(raw_cons & cp_ring_struct->ring_size);
376 bnxt_tx_cmp_vec(txq, nb_tx_pkts);
377 cpr->cp_raw_cons = raw_cons;
383 bnxt_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
386 struct bnxt_tx_queue *txq = tx_queue;
387 struct bnxt_tx_ring_info *txr = txq->tx_ring;
388 uint16_t prod = txr->tx_prod;
389 struct rte_mbuf *tx_mbuf;
390 struct tx_bd_long *txbd = NULL;
391 struct bnxt_sw_tx_bd *tx_buf;
394 nb_pkts = RTE_MIN(nb_pkts, bnxt_tx_avail(txq));
396 if (unlikely(nb_pkts == 0))
399 /* Handle TX burst request */
402 tx_mbuf = *tx_pkts++;
403 rte_prefetch0(tx_mbuf);
405 tx_buf = &txr->tx_buf_ring[prod];
406 tx_buf->mbuf = tx_mbuf;
409 txbd = &txr->tx_desc_ring[prod];
410 txbd->address = tx_mbuf->buf_iova + tx_mbuf->data_off;
411 txbd->len = tx_mbuf->data_len;
412 txbd->flags_type = bnxt_xmit_flags_len(tx_mbuf->data_len,
414 prod = RING_NEXT(txr->tx_ring_struct, prod);
418 /* Request a completion for last packet in burst */
420 txbd->opaque = nb_pkts;
421 txbd->flags_type &= ~TX_BD_LONG_FLAGS_NO_CMPL;
424 rte_compiler_barrier();
425 bnxt_db_write(&txr->tx_db, prod);
433 bnxt_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
437 struct bnxt_tx_queue *txq = tx_queue;
439 /* Tx queue was stopped; wait for it to be restarted */
440 if (unlikely(!txq->tx_started)) {
441 PMD_DRV_LOG(DEBUG, "Tx q stopped;return\n");
445 /* Handle TX completions */
446 if (bnxt_tx_bds_in_hw(txq) >= txq->tx_free_thresh)
447 bnxt_handle_tx_cp_vec(txq);
452 num = RTE_MIN(nb_pkts, RTE_BNXT_MAX_TX_BURST);
453 ret = bnxt_xmit_fixed_burst_vec(tx_queue,
466 bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq)
468 return bnxt_rxq_vec_setup_common(rxq);