drivers/net/bnxt/tf_core/tf_device_p4.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019-2020 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _TF_DEVICE_P4_H_
   7 #define _TF_DEVICE_P4_H_
   8
   9 #include <cfa_resource_types.h>
  10
  11 #include "tf_core.h"
  12 #include "tf_rm_new.h"
  13
  14 struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {
  15         { TF_RM_ELEM_CFG_PRIVATE, 0 /* CFA_RESOURCE_TYPE_P4_INVALID */ },
  16         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_PROF_FUNC },
  17         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID },
  18         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_PROF_ID },
  19         { TF_RM_ELEM_CFG_NULL, 0    /* CFA_RESOURCE_TYPE_P4_L2_FUNC */ }
  20 };
  21
  22 struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {
  23         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM },
  24         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_PROF_TCAM },
  25         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_WC_TCAM },
  26         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_SP_TCAM },
  27         { TF_RM_ELEM_CFG_NULL, 0 /* CFA_RESOURCE_TYPE_P4_CT_RULE_TCAM */ },
  28         { TF_RM_ELEM_CFG_NULL, 0  /* CFA_RESOURCE_TYPE_P4_VEB_TCAM */ }
  29 };
  30
  31 struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
  32         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_SRAM_FULL_ACTION },
  33         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_SRAM_MCG },
  34         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_SRAM_ENCAP_8B },
  35         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_SRAM_ENCAP_16B },
  36         { TF_RM_ELEM_CFG_NULL, 0, /* CFA_RESOURCE_TYPE_P4_SRAM_ENCAP_32B */ },
  37         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_SRAM_ENCAP_64B },
  38         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_SRAM_SP_MAC },
  39         { TF_RM_ELEM_CFG_NULL, 0 /* CFA_RESOURCE_TYPE_P4_SRAM_SP_SMAC_IPV4 */ },
  40         { TF_RM_ELEM_CFG_NULL, 0 /* CFA_RESOURCE_TYPE_P4_SRAM_SP_SMAC_IPV6 */ },
  41         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_SRAM_COUNTER_64B },
  42         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_SRAM_NAT_SPORT },
  43         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_SRAM_NAT_DPORT },
  44         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_SRAM_NAT_S_IPV4 },
  45         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_SRAM_NAT_D_IPV4 },
  46         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_SRAM_NAT_S_IPV6 },
  47         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_SRAM_NAT_D_IPV6 },
  48         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_METER_PROF },
  49         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_METER },
  50         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_MIRROR },
  51         { TF_RM_ELEM_CFG_NULL, /* CFA_RESOURCE_TYPE_P4_UPAR */ },
  52         { TF_RM_ELEM_CFG_NULL, /* CFA_RESOURCE_TYPE_P4_EPOC */ },
  53         { TF_RM_ELEM_CFG_NULL, /* CFA_RESOURCE_TYPE_P4_METADATA */ },
  54         { TF_RM_ELEM_CFG_NULL, /* CFA_RESOURCE_TYPE_P4_CT_STATE */ },
  55         { TF_RM_ELEM_CFG_NULL, /* CFA_RESOURCE_TYPE_P4_RANGE_PROF */ },
  56         { TF_RM_ELEM_CFG_NULL, /* CFA_RESOURCE_TYPE_P4_RANGE_ENTRY */ },
  57         { TF_RM_ELEM_CFG_NULL, /* CFA_RESOURCE_TYPE_P4_LAG */ },
  58         { TF_RM_ELEM_CFG_NULL, /* CFA_RESOURCE_TYPE_P4_VNIC_SVIF */ },
  59         { TF_RM_ELEM_CFG_NULL, /* CFA_RESOURCE_TYPE_P4_EM_FBK */ },
  60         { TF_RM_ELEM_CFG_NULL, /* CFA_RESOURCE_TYPE_P4_WC_FKB */ },
  61         { TF_RM_ELEM_CFG_NULL, /* CFA_RESOURCE_TYPE_P4_EXT */ }
  62 };
  63
  64 #endif /* _TF_DEVICE_P4_H_ */