drivers/net/bnxt/tf_core/tf_device_p4.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _TF_DEVICE_P4_H_
   7 #define _TF_DEVICE_P4_H_
   8
   9 #include "cfa_resource_types.h"
  10 #include "tf_core.h"
  11 #include "tf_rm.h"
  12 #include "tf_if_tbl.h"
  13 #include "tf_global_cfg.h"
  14
  15 struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {
  16         [TF_IDENT_TYPE_L2_CTXT_HIGH] = {
  17                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH,
  18                 0, 0
  19         },
  20         [TF_IDENT_TYPE_L2_CTXT_LOW] = {
  21                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW,
  22                 0, 0
  23         },
  24         [TF_IDENT_TYPE_PROF_FUNC] = {
  25                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_FUNC,
  26                 0, 0
  27         },
  28         [TF_IDENT_TYPE_WC_PROF] = {
  29                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID,
  30                 0, 0
  31         },
  32         [TF_IDENT_TYPE_EM_PROF] = {
  33                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_EM_PROF_ID,
  34                 0, 0
  35         },
  36 };
  37
  38 struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {
  39         [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = {
  40                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH,
  41                 0, 0
  42         },
  43         [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = {
  44                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW,
  45                 0, 0
  46         },
  47         [TF_TCAM_TBL_TYPE_PROF_TCAM] = {
  48                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_TCAM,
  49                 0, 0
  50         },
  51         [TF_TCAM_TBL_TYPE_WC_TCAM] = {
  52                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM,
  53                 0, 0
  54         },
  55         [TF_TCAM_TBL_TYPE_SP_TCAM] = {
  56                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_TCAM,
  57                 0, 0
  58         },
  59 };
  60
  61 struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
  62         [TF_TBL_TYPE_FULL_ACT_RECORD] = {
  63                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION,
  64                 0, 0
  65         },
  66         [TF_TBL_TYPE_MCAST_GROUPS] = {
  67                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG,
  68                 0, 0
  69         },
  70         [TF_TBL_TYPE_ACT_ENCAP_8B] = {
  71                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B,
  72                 0, 0
  73         },
  74         [TF_TBL_TYPE_ACT_ENCAP_16B] = {
  75                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B,
  76                 0, 0
  77         },
  78         [TF_TBL_TYPE_ACT_ENCAP_64B] = {
  79                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B,
  80                 0, 0
  81         },
  82         [TF_TBL_TYPE_ACT_SP_SMAC] = {
  83                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC,
  84                 0, 0
  85         },
  86         [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
  87                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4,
  88                 0, 0
  89         },
  90         [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
  91                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6,
  92                 0, 0
  93         },
  94         [TF_TBL_TYPE_ACT_STATS_64] = {
  95                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B,
  96                 0, 0
  97         },
  98         [TF_TBL_TYPE_ACT_MODIFY_IPV4] = {
  99                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4,
 100                 0, 0
 101         },
 102         [TF_TBL_TYPE_METER_PROF] = {
 103                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF,
 104                 0, 0
 105         },
 106         [TF_TBL_TYPE_METER_INST] = {
 107                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER,
 108                 0, 0
 109         },
 110         [TF_TBL_TYPE_MIRROR_CONFIG] = {
 111                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR,
 112                 0, 0
 113         },
 114
 115 };
 116
 117 struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
 118         [TF_EM_TBL_TYPE_TBL_SCOPE] = {
 119                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE,
 120                 0, 0
 121         },
 122 };
 123
 124 struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {
 125         [TF_EM_TBL_TYPE_EM_RECORD] = {
 126                 TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC,
 127                 0, 0
 128         },
 129 };
 130
 131 /* Note that hcapi_types from this table are from hcapi_cfa_p4.h
 132  * These are not CFA resource types because they are not allocated
 133  * CFA resources - they are identifiers for the interface tables
 134  * shared between the firmware and the host.  It may make sense to
 135  * move these types to cfa_resource_types.h.
 136  */
 137 struct tf_if_tbl_cfg tf_if_tbl_p4[TF_IF_TBL_TYPE_MAX] = {
 138         [TF_IF_TBL_TYPE_PROF_SPIF_DFLT_L2_CTXT] = {
 139                 TF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT
 140         },
 141         [TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR] = {
 142                 TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR
 143         },
 144         [TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR] = {
 145                 TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR
 146         },
 147         [TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR] = {
 148                 TF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR
 149         },
 150 };
 151
 152 struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = {
 153         [TF_TUNNEL_ENCAP] = {
 154                 TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP
 155         },
 156         [TF_ACTION_BLOCK] = {
 157                 TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK
 158         },
 159 };
 160
 161 const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = {
 162         [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH] = {
 163                 TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_HIGH
 164         },
 165         [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW] = {
 166                 TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_LOW
 167         },
 168         [CFA_RESOURCE_TYPE_P4_PROF_FUNC] = {
 169                 TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_PROF_FUNC
 170         },
 171         [CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID] = {
 172                 TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_WC_PROF
 173         },
 174         [CFA_RESOURCE_TYPE_P4_EM_PROF_ID] = {
 175                 TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_EM_PROF
 176         },
 177         [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH] = {
 178                 TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH
 179         },
 180         [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW] = {
 181                 TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW
 182         },
 183         [CFA_RESOURCE_TYPE_P4_PROF_TCAM] = {
 184                 TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_PROF_TCAM
 185         },
 186         [CFA_RESOURCE_TYPE_P4_WC_TCAM] = {
 187                 TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_WC_TCAM
 188         },
 189         [CFA_RESOURCE_TYPE_P4_SP_TCAM] = {
 190                 TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_SP_TCAM
 191         },
 192         [CFA_RESOURCE_TYPE_P4_NAT_IPV4] = {
 193                 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_MODIFY_IPV4
 194         },
 195         [CFA_RESOURCE_TYPE_P4_METER_PROF] = {
 196                 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_PROF
 197         },
 198         [CFA_RESOURCE_TYPE_P4_METER] = {
 199                 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_INST
 200         },
 201         [CFA_RESOURCE_TYPE_P4_MIRROR] = {
 202                 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MIRROR_CONFIG
 203         },
 204         [CFA_RESOURCE_TYPE_P4_FULL_ACTION] = {
 205                 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_FULL_ACT_RECORD
 206         },
 207         [CFA_RESOURCE_TYPE_P4_MCG] = {
 208                 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MCAST_GROUPS
 209         },
 210         [CFA_RESOURCE_TYPE_P4_ENCAP_8B] = {
 211                 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_8B
 212         },
 213         [CFA_RESOURCE_TYPE_P4_ENCAP_16B] = {
 214                 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_16B
 215         },
 216         [CFA_RESOURCE_TYPE_P4_ENCAP_64B] = {
 217                 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_64B
 218         },
 219         [CFA_RESOURCE_TYPE_P4_SP_MAC] = {
 220                 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC
 221         },
 222         [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4] = {
 223                 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV4
 224         },
 225         [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6] = {
 226                 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV6
 227         },
 228         [CFA_RESOURCE_TYPE_P4_COUNTER_64B] = {
 229                 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_STATS_64
 230         },
 231         [CFA_RESOURCE_TYPE_P4_EM_REC] = {
 232                 TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_EM_RECORD
 233         },
 234         [CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = {
 235                 TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_TBL_SCOPE
 236         },
 237 };
 238
 239 #endif /* _TF_DEVICE_P4_H_ */