1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019-2020 Broadcom
20 #define TF_SESSIONS_MAX 1 /** max # sessions */
21 #define TF_SESSION_ID_INVALID 0xFFFFFFFF /** Invalid Session ID define */
24 * Number of EM entries. Static for now will be removed
25 * when parameter added at a later date. At this stage we
26 * are using fixed size entries so that each stack entry
27 * represents 4 RT (f/n)blocks. So we take the total block
28 * allocation for truflow and divide that by 4.
30 #define TF_SESSION_TOTAL_FN_BLOCKS (1024 * 8) /* 8K blocks */
31 #define TF_SESSION_EM_ENTRY_SIZE 4 /* 4 blocks per entry */
32 #define TF_SESSION_EM_POOL_SIZE \
33 (TF_SESSION_TOTAL_FN_BLOCKS / TF_SESSION_EM_ENTRY_SIZE)
37 * Shared memory containing private TruFlow session information.
38 * Through this structure the session can keep track of resource
39 * allocations and (if so configured) any shadow copy of flow
42 * Memory is assigned to the Truflow instance by way of
43 * tf_open_session. Memory is allocated and owned by i.e. ULP.
45 * Access control to this shared memory is handled by the spin_lock in
49 /** TrueFlow Version. Used to control the structure layout
50 * when sharing sessions. No guarantee that a secondary
51 * process would come from the same version of an executable.
53 struct tf_session_version ver;
55 /** Device type, provided by tf_open_session().
57 enum tf_device_type device_type;
59 /** Session ID, allocated by FW on tf_open_session().
61 union tf_session_id session_id;
64 * String containing name of control channel interface to be
65 * used for this session to communicate with firmware.
67 * ctrl_chan_name will be used as part of a name for any
68 * shared memory allocation.
70 char ctrl_chan_name[TF_SESSION_NAME_MAX];
73 * Boolean controlling the use and availability of shadow
74 * copy. Shadow copy will allow the TruFlow Core to keep track
75 * of resource content on the firmware side without having to
76 * query firmware. Additional private session core_data will
77 * be allocated if this boolean is set to 'true', default
80 * Size of memory depends on the NVM Resource settings for the
86 * Session Reference Count. To keep track of functions per
87 * session the ref_count is incremented. There is also a
88 * parallel TruFlow Firmware ref_count in case the TruFlow
89 * Core goes away without informing the Firmware.
93 /** Session HW and SRAM resources */
96 /* Session HW resource pools */
98 /** RX L2 CTXT TCAM Pool */
99 BITALLOC_INST(TF_L2_CTXT_TCAM_POOL_NAME_RX, TF_NUM_L2_CTXT_TCAM);
100 /** TX L2 CTXT TCAM Pool */
101 BITALLOC_INST(TF_L2_CTXT_TCAM_POOL_NAME_TX, TF_NUM_L2_CTXT_TCAM);
103 /** RX Profile Func Pool */
104 BITALLOC_INST(TF_PROF_FUNC_POOL_NAME_RX, TF_NUM_PROF_FUNC);
105 /** TX Profile Func Pool */
106 BITALLOC_INST(TF_PROF_FUNC_POOL_NAME_TX, TF_NUM_PROF_FUNC);
108 /** RX Profile TCAM Pool */
109 BITALLOC_INST(TF_PROF_TCAM_POOL_NAME_RX, TF_NUM_PROF_TCAM);
110 /** TX Profile TCAM Pool */
111 BITALLOC_INST(TF_PROF_TCAM_POOL_NAME_TX, TF_NUM_PROF_TCAM);
113 /** RX EM Profile ID Pool */
114 BITALLOC_INST(TF_EM_PROF_ID_POOL_NAME_RX, TF_NUM_EM_PROF_ID);
115 /** TX EM Key Pool */
116 BITALLOC_INST(TF_EM_PROF_ID_POOL_NAME_TX, TF_NUM_EM_PROF_ID);
118 /** RX WC Profile Pool */
119 BITALLOC_INST(TF_WC_TCAM_PROF_ID_POOL_NAME_RX, TF_NUM_WC_PROF_ID);
120 /** TX WC Profile Pool */
121 BITALLOC_INST(TF_WC_TCAM_PROF_ID_POOL_NAME_TX, TF_NUM_WC_PROF_ID);
123 /* TBD, how do we want to handle EM records ?*/
124 /* EM Records are not controlled by way of a pool */
126 /** RX WC TCAM Pool */
127 BITALLOC_INST(TF_WC_TCAM_POOL_NAME_RX, TF_NUM_WC_TCAM_ROW);
128 /** TX WC TCAM Pool */
129 BITALLOC_INST(TF_WC_TCAM_POOL_NAME_TX, TF_NUM_WC_TCAM_ROW);
131 /** RX Meter Profile Pool */
132 BITALLOC_INST(TF_METER_PROF_POOL_NAME_RX, TF_NUM_METER_PROF);
133 /** TX Meter Profile Pool */
134 BITALLOC_INST(TF_METER_PROF_POOL_NAME_TX, TF_NUM_METER_PROF);
136 /** RX Meter Instance Pool */
137 BITALLOC_INST(TF_METER_INST_POOL_NAME_RX, TF_NUM_METER);
139 BITALLOC_INST(TF_METER_INST_POOL_NAME_TX, TF_NUM_METER);
141 /** RX Mirror Configuration Pool*/
142 BITALLOC_INST(TF_MIRROR_POOL_NAME_RX, TF_NUM_MIRROR);
143 /** RX Mirror Configuration Pool */
144 BITALLOC_INST(TF_MIRROR_POOL_NAME_TX, TF_NUM_MIRROR);
147 BITALLOC_INST(TF_UPAR_POOL_NAME_RX, TF_NUM_UPAR);
149 BITALLOC_INST(TF_UPAR_POOL_NAME_TX, TF_NUM_UPAR);
151 /** RX SP TCAM Pool */
152 BITALLOC_INST(TF_SP_TCAM_POOL_NAME_RX, TF_NUM_SP_TCAM);
153 /** TX SP TCAM Pool */
154 BITALLOC_INST(TF_SP_TCAM_POOL_NAME_TX, TF_NUM_SP_TCAM);
157 BITALLOC_INST(TF_FKB_POOL_NAME_RX, TF_NUM_FKB);
159 BITALLOC_INST(TF_FKB_POOL_NAME_TX, TF_NUM_FKB);
161 /** RX Table Scope Pool */
162 BITALLOC_INST(TF_TBL_SCOPE_POOL_NAME_RX, TF_NUM_TBL_SCOPE);
163 /** TX Table Scope Pool */
164 BITALLOC_INST(TF_TBL_SCOPE_POOL_NAME_TX, TF_NUM_TBL_SCOPE);
166 /** RX L2 Func Pool */
167 BITALLOC_INST(TF_L2_FUNC_POOL_NAME_RX, TF_NUM_L2_FUNC);
168 /** TX L2 Func Pool */
169 BITALLOC_INST(TF_L2_FUNC_POOL_NAME_TX, TF_NUM_L2_FUNC);
171 /** RX Epoch0 Pool */
172 BITALLOC_INST(TF_EPOCH0_POOL_NAME_RX, TF_NUM_EPOCH0);
173 /** TX Epoch0 Pool */
174 BITALLOC_INST(TF_EPOCH0_POOL_NAME_TX, TF_NUM_EPOCH0);
176 /** TX Epoch1 Pool */
177 BITALLOC_INST(TF_EPOCH1_POOL_NAME_RX, TF_NUM_EPOCH1);
178 /** TX Epoch1 Pool */
179 BITALLOC_INST(TF_EPOCH1_POOL_NAME_TX, TF_NUM_EPOCH1);
181 /** RX MetaData Profile Pool */
182 BITALLOC_INST(TF_METADATA_POOL_NAME_RX, TF_NUM_METADATA);
183 /** TX MetaData Profile Pool */
184 BITALLOC_INST(TF_METADATA_POOL_NAME_TX, TF_NUM_METADATA);
186 /** RX Connection Tracking State Pool */
187 BITALLOC_INST(TF_CT_STATE_POOL_NAME_RX, TF_NUM_CT_STATE);
188 /** TX Connection Tracking State Pool */
189 BITALLOC_INST(TF_CT_STATE_POOL_NAME_TX, TF_NUM_CT_STATE);
191 /** RX Range Profile Pool */
192 BITALLOC_INST(TF_RANGE_PROF_POOL_NAME_RX, TF_NUM_RANGE_PROF);
193 /** TX Range Profile Pool */
194 BITALLOC_INST(TF_RANGE_PROF_POOL_NAME_TX, TF_NUM_RANGE_PROF);
197 BITALLOC_INST(TF_RANGE_ENTRY_POOL_NAME_RX, TF_NUM_RANGE_ENTRY);
199 BITALLOC_INST(TF_RANGE_ENTRY_POOL_NAME_TX, TF_NUM_RANGE_ENTRY);
202 BITALLOC_INST(TF_LAG_ENTRY_POOL_NAME_RX, TF_NUM_LAG_ENTRY);
204 BITALLOC_INST(TF_LAG_ENTRY_POOL_NAME_TX, TF_NUM_LAG_ENTRY);
206 /* Session SRAM pools */
208 /** RX Full Action Record Pool */
209 BITALLOC_INST(TF_SRAM_FULL_ACTION_POOL_NAME_RX,
210 TF_RSVD_SRAM_FULL_ACTION_RX);
211 /** TX Full Action Record Pool */
212 BITALLOC_INST(TF_SRAM_FULL_ACTION_POOL_NAME_TX,
213 TF_RSVD_SRAM_FULL_ACTION_TX);
215 /** RX Multicast Group Pool, only RX is supported */
216 BITALLOC_INST(TF_SRAM_MCG_POOL_NAME_RX,
217 TF_RSVD_SRAM_MCG_RX);
219 /** RX Encap 8B Pool*/
220 BITALLOC_INST(TF_SRAM_ENCAP_8B_POOL_NAME_RX,
221 TF_RSVD_SRAM_ENCAP_8B_RX);
222 /** TX Encap 8B Pool*/
223 BITALLOC_INST(TF_SRAM_ENCAP_8B_POOL_NAME_TX,
224 TF_RSVD_SRAM_ENCAP_8B_TX);
226 /** RX Encap 16B Pool */
227 BITALLOC_INST(TF_SRAM_ENCAP_16B_POOL_NAME_RX,
228 TF_RSVD_SRAM_ENCAP_16B_RX);
229 /** TX Encap 16B Pool */
230 BITALLOC_INST(TF_SRAM_ENCAP_16B_POOL_NAME_TX,
231 TF_RSVD_SRAM_ENCAP_16B_TX);
233 /** TX Encap 64B Pool, only TX is supported */
234 BITALLOC_INST(TF_SRAM_ENCAP_64B_POOL_NAME_TX,
235 TF_RSVD_SRAM_ENCAP_64B_TX);
237 /** RX Source Properties SMAC Pool */
238 BITALLOC_INST(TF_SRAM_SP_SMAC_POOL_NAME_RX,
239 TF_RSVD_SRAM_SP_SMAC_RX);
240 /** TX Source Properties SMAC Pool */
241 BITALLOC_INST(TF_SRAM_SP_SMAC_POOL_NAME_TX,
242 TF_RSVD_SRAM_SP_SMAC_TX);
244 /** TX Source Properties SMAC IPv4 Pool, only TX is supported */
245 BITALLOC_INST(TF_SRAM_SP_SMAC_IPV4_POOL_NAME_TX,
246 TF_RSVD_SRAM_SP_SMAC_IPV4_TX);
248 /** TX Source Properties SMAC IPv6 Pool, only TX is supported */
249 BITALLOC_INST(TF_SRAM_SP_SMAC_IPV6_POOL_NAME_TX,
250 TF_RSVD_SRAM_SP_SMAC_IPV6_TX);
252 /** RX Counter 64B Pool */
253 BITALLOC_INST(TF_SRAM_STATS_64B_POOL_NAME_RX,
254 TF_RSVD_SRAM_COUNTER_64B_RX);
255 /** TX Counter 64B Pool */
256 BITALLOC_INST(TF_SRAM_STATS_64B_POOL_NAME_TX,
257 TF_RSVD_SRAM_COUNTER_64B_TX);
259 /** RX NAT Source Port Pool */
260 BITALLOC_INST(TF_SRAM_NAT_SPORT_POOL_NAME_RX,
261 TF_RSVD_SRAM_NAT_SPORT_RX);
262 /** TX NAT Source Port Pool */
263 BITALLOC_INST(TF_SRAM_NAT_SPORT_POOL_NAME_TX,
264 TF_RSVD_SRAM_NAT_SPORT_TX);
266 /** RX NAT Destination Port Pool */
267 BITALLOC_INST(TF_SRAM_NAT_DPORT_POOL_NAME_RX,
268 TF_RSVD_SRAM_NAT_DPORT_RX);
269 /** TX NAT Destination Port Pool */
270 BITALLOC_INST(TF_SRAM_NAT_DPORT_POOL_NAME_TX,
271 TF_RSVD_SRAM_NAT_DPORT_TX);
273 /** RX NAT Source IPv4 Pool */
274 BITALLOC_INST(TF_SRAM_NAT_S_IPV4_POOL_NAME_RX,
275 TF_RSVD_SRAM_NAT_S_IPV4_RX);
276 /** TX NAT Source IPv4 Pool */
277 BITALLOC_INST(TF_SRAM_NAT_S_IPV4_POOL_NAME_TX,
278 TF_RSVD_SRAM_NAT_S_IPV4_TX);
280 /** RX NAT Destination IPv4 Pool */
281 BITALLOC_INST(TF_SRAM_NAT_D_IPV4_POOL_NAME_RX,
282 TF_RSVD_SRAM_NAT_D_IPV4_RX);
283 /** TX NAT IPv4 Destination Pool */
284 BITALLOC_INST(TF_SRAM_NAT_D_IPV4_POOL_NAME_TX,
285 TF_RSVD_SRAM_NAT_D_IPV4_TX);
288 * Pools not allocated from HCAPI RM
291 /** RX L2 Ctx Remap ID Pool */
292 BITALLOC_INST(TF_L2_CTXT_REMAP_POOL_NAME_RX, TF_NUM_L2_CTXT_TCAM);
293 /** TX L2 Ctx Remap ID Pool */
294 BITALLOC_INST(TF_L2_CTXT_REMAP_POOL_NAME_TX, TF_NUM_L2_CTXT_TCAM);
296 /** CRC32 seed table */
297 #define TF_LKUP_SEED_MEM_SIZE 512
298 uint32_t lkup_em_seed_mem[TF_DIR_MAX][TF_LKUP_SEED_MEM_SIZE];
300 /** Lookup3 init values */
301 uint32_t lkup_lkup3_init_cfg[TF_DIR_MAX];
303 /** Table scope array */
304 struct tf_tbl_scope_cb tbl_scopes[TF_NUM_TBL_SCOPE];
309 struct stack em_pool[TF_DIR_MAX];
312 #endif /* _TF_SESSION_H_ */