drivers/net/bnxt/tf_ulp/ulp_template_db.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2020 Broadcom
   3  * All rights reserved.
   4  */
   5
   6
   7 #ifndef ULP_TEMPLATE_DB_H_
   8 #define ULP_TEMPLATE_DB_H_
   9
  10 #define BNXT_ULP_REGFILE_MAX_SZ 15
  11 #define BNXT_ULP_MAX_NUM_DEVICES 4
  12 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2
  13 #define BNXT_ULP_CACHE_TBL_MAX_SZ 4
  14 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256
  15 #define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 2
  16 #define BNXT_ULP_CLASS_HID_LOW_PRIME 7919
  17 #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7919
  18 #define BNXT_ULP_CLASS_HID_SHFTR 0
  19 #define BNXT_ULP_CLASS_HID_SHFTL 23
  20 #define BNXT_ULP_CLASS_HID_MASK 255
  21 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 256
  22 #define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 2
  23 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919
  24 #define BNXT_ULP_ACT_HID_HIGH_PRIME 7919
  25 #define BNXT_ULP_ACT_HID_SHFTR 0
  26 #define BNXT_ULP_ACT_HID_SHFTL 23
  27 #define BNXT_ULP_ACT_HID_MASK 255
  28 #define BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM 2
  29 #define BNXT_ULP_GLB_RESOURCE_INFO_TBL_MAX_SZ 2
  30
  31 enum bnxt_ulp_action_bit {
  32         BNXT_ULP_ACTION_BIT_MARK             = 0x0000000000000001,
  33         BNXT_ULP_ACTION_BIT_DROP             = 0x0000000000000002,
  34         BNXT_ULP_ACTION_BIT_COUNT            = 0x0000000000000004,
  35         BNXT_ULP_ACTION_BIT_RSS              = 0x0000000000000008,
  36         BNXT_ULP_ACTION_BIT_METER            = 0x0000000000000010,
  37         BNXT_ULP_ACTION_BIT_VNIC             = 0x0000000000000020,
  38         BNXT_ULP_ACTION_BIT_VPORT            = 0x0000000000000040,
  39         BNXT_ULP_ACTION_BIT_VXLAN_DECAP      = 0x0000000000000080,
  40         BNXT_ULP_ACTION_BIT_NVGRE_DECAP      = 0x0000000000000100,
  41         BNXT_ULP_ACTION_BIT_POP_MPLS         = 0x0000000000000200,
  42         BNXT_ULP_ACTION_BIT_PUSH_MPLS        = 0x0000000000000400,
  43         BNXT_ULP_ACTION_BIT_MAC_SWAP         = 0x0000000000000800,
  44         BNXT_ULP_ACTION_BIT_SET_MAC_SRC      = 0x0000000000001000,
  45         BNXT_ULP_ACTION_BIT_SET_MAC_DST      = 0x0000000000002000,
  46         BNXT_ULP_ACTION_BIT_POP_VLAN         = 0x0000000000004000,
  47         BNXT_ULP_ACTION_BIT_PUSH_VLAN        = 0x0000000000008000,
  48         BNXT_ULP_ACTION_BIT_SET_VLAN_PCP     = 0x0000000000010000,
  49         BNXT_ULP_ACTION_BIT_SET_VLAN_VID     = 0x0000000000020000,
  50         BNXT_ULP_ACTION_BIT_SET_IPV4_SRC     = 0x0000000000040000,
  51         BNXT_ULP_ACTION_BIT_SET_IPV4_DST     = 0x0000000000080000,
  52         BNXT_ULP_ACTION_BIT_SET_IPV6_SRC     = 0x0000000000100000,
  53         BNXT_ULP_ACTION_BIT_SET_IPV6_DST     = 0x0000000000200000,
  54         BNXT_ULP_ACTION_BIT_DEC_TTL          = 0x0000000000400000,
  55         BNXT_ULP_ACTION_BIT_SET_TP_SRC       = 0x0000000000800000,
  56         BNXT_ULP_ACTION_BIT_SET_TP_DST       = 0x0000000001000000,
  57         BNXT_ULP_ACTION_BIT_VXLAN_ENCAP      = 0x0000000002000000,
  58         BNXT_ULP_ACTION_BIT_NVGRE_ENCAP      = 0x0000000004000000,
  59         BNXT_ULP_ACTION_BIT_LAST             = 0x0000000008000000
  60 };
  61
  62 enum bnxt_ulp_hdr_bit {
  63         BNXT_ULP_HDR_BIT_O_ETH               = 0x0000000000000001,
  64         BNXT_ULP_HDR_BIT_O_IPV4              = 0x0000000000000002,
  65         BNXT_ULP_HDR_BIT_O_IPV6              = 0x0000000000000004,
  66         BNXT_ULP_HDR_BIT_O_TCP               = 0x0000000000000008,
  67         BNXT_ULP_HDR_BIT_O_UDP               = 0x0000000000000010,
  68         BNXT_ULP_HDR_BIT_T_VXLAN             = 0x0000000000000020,
  69         BNXT_ULP_HDR_BIT_T_GRE               = 0x0000000000000040,
  70         BNXT_ULP_HDR_BIT_I_ETH               = 0x0000000000000080,
  71         BNXT_ULP_HDR_BIT_I_IPV4              = 0x0000000000000100,
  72         BNXT_ULP_HDR_BIT_I_IPV6              = 0x0000000000000200,
  73         BNXT_ULP_HDR_BIT_I_TCP               = 0x0000000000000400,
  74         BNXT_ULP_HDR_BIT_I_UDP               = 0x0000000000000800,
  75         BNXT_ULP_HDR_BIT_LAST                = 0x0000000000001000
  76 };
  77
  78 enum bnxt_ulp_act_type {
  79         BNXT_ULP_ACT_TYPE_NOT_SUPPORTED = 0,
  80         BNXT_ULP_ACT_TYPE_SUPPORTED = 1,
  81         BNXT_ULP_ACT_TYPE_END = 2,
  82         BNXT_ULP_ACT_TYPE_LAST = 3
  83 };
  84
  85 enum bnxt_ulp_byte_order {
  86         BNXT_ULP_BYTE_ORDER_BE = 0,
  87         BNXT_ULP_BYTE_ORDER_LE = 1,
  88         BNXT_ULP_BYTE_ORDER_LAST = 2
  89 };
  90
  91 enum bnxt_ulp_cf_idx {
  92         BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 0,
  93         BNXT_ULP_CF_IDX_O_VTAG_NUM = 1,
  94         BNXT_ULP_CF_IDX_O_VTAG_PRESENT = 2,
  95         BNXT_ULP_CF_IDX_O_TWO_VTAGS = 3,
  96         BNXT_ULP_CF_IDX_I_VTAG_NUM = 4,
  97         BNXT_ULP_CF_IDX_I_VTAG_PRESENT = 5,
  98         BNXT_ULP_CF_IDX_I_TWO_VTAGS = 6,
  99         BNXT_ULP_CF_IDX_INCOMING_IF = 7,
 100         BNXT_ULP_CF_IDX_DIRECTION = 8,
 101         BNXT_ULP_CF_IDX_SVIF_FLAG = 9,
 102         BNXT_ULP_CF_IDX_O_L3 = 10,
 103         BNXT_ULP_CF_IDX_I_L3 = 11,
 104         BNXT_ULP_CF_IDX_O_L4 = 12,
 105         BNXT_ULP_CF_IDX_I_L4 = 13,
 106         BNXT_ULP_CF_IDX_DEV_PORT_ID = 14,
 107         BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 15,
 108         BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 16,
 109         BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 17,
 110         BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 18,
 111         BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 19,
 112         BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 20,
 113         BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 21,
 114         BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 22,
 115         BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 23,
 116         BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 24,
 117         BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 25,
 118         BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 26,
 119         BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 27,
 120         BNXT_ULP_CF_IDX_VFR_FLAG = 28,
 121         BNXT_ULP_CF_IDX_LAST = 29
 122 };
 123
 124 enum bnxt_ulp_critical_resource {
 125         BNXT_ULP_CRITICAL_RESOURCE_NO = 0,
 126         BNXT_ULP_CRITICAL_RESOURCE_YES = 1,
 127         BNXT_ULP_CRITICAL_RESOURCE_LAST = 2
 128 };
 129
 130 enum bnxt_ulp_device_id {
 131         BNXT_ULP_DEVICE_ID_WH_PLUS = 0,
 132         BNXT_ULP_DEVICE_ID_THOR = 1,
 133         BNXT_ULP_DEVICE_ID_STINGRAY = 2,
 134         BNXT_ULP_DEVICE_ID_STINGRAY2 = 3,
 135         BNXT_ULP_DEVICE_ID_LAST = 4
 136 };
 137
 138 enum bnxt_ulp_direction {
 139         BNXT_ULP_DIRECTION_INGRESS = 0,
 140         BNXT_ULP_DIRECTION_EGRESS = 1,
 141         BNXT_ULP_DIRECTION_LAST = 2
 142 };
 143
 144 enum bnxt_ulp_glb_regfile_index {
 145         BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID = 0,
 146         BNXT_ULP_GLB_REGFILE_INDEX_LAST = 1
 147 };
 148
 149 enum bnxt_ulp_hdr_type {
 150         BNXT_ULP_HDR_TYPE_NOT_SUPPORTED = 0,
 151         BNXT_ULP_HDR_TYPE_SUPPORTED = 1,
 152         BNXT_ULP_HDR_TYPE_END = 2,
 153         BNXT_ULP_HDR_TYPE_LAST = 3
 154 };
 155
 156 enum bnxt_ulp_mark_enable {
 157         BNXT_ULP_MARK_ENABLE_NO = 0,
 158         BNXT_ULP_MARK_ENABLE_YES = 1,
 159         BNXT_ULP_MARK_ENABLE_LAST = 2
 160 };
 161
 162 enum bnxt_ulp_mask_opc {
 163         BNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0,
 164         BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1,
 165         BNXT_ULP_MASK_OPC_SET_TO_REGFILE = 2,
 166         BNXT_ULP_MASK_OPC_SET_TO_GLB_REGFILE = 3,
 167         BNXT_ULP_MASK_OPC_ADD_PAD = 4,
 168         BNXT_ULP_MASK_OPC_LAST = 5
 169 };
 170
 171 enum bnxt_ulp_match_type {
 172         BNXT_ULP_MATCH_TYPE_EM = 0,
 173         BNXT_ULP_MATCH_TYPE_WC = 1,
 174         BNXT_ULP_MATCH_TYPE_LAST = 2
 175 };
 176
 177 enum bnxt_ulp_priority {
 178         BNXT_ULP_PRIORITY_LEVEL_0 = 0,
 179         BNXT_ULP_PRIORITY_LEVEL_1 = 1,
 180         BNXT_ULP_PRIORITY_LEVEL_2 = 2,
 181         BNXT_ULP_PRIORITY_LEVEL_3 = 3,
 182         BNXT_ULP_PRIORITY_LEVEL_4 = 4,
 183         BNXT_ULP_PRIORITY_LEVEL_5 = 5,
 184         BNXT_ULP_PRIORITY_LEVEL_6 = 6,
 185         BNXT_ULP_PRIORITY_LEVEL_7 = 7,
 186         BNXT_ULP_PRIORITY_NOT_USED = 8,
 187         BNXT_ULP_PRIORITY_LAST = 9
 188 };
 189
 190 enum bnxt_ulp_regfile_index {
 191         BNXT_ULP_REGFILE_INDEX_CLASS_TID = 0,
 192         BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 1,
 193         BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 2,
 194         BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 3,
 195         BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 4,
 196         BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 5,
 197         BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 6,
 198         BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 7,
 199         BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 8,
 200         BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR = 9,
 201         BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 10,
 202         BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 11,
 203         BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 12,
 204         BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 13,
 205         BNXT_ULP_REGFILE_INDEX_NOT_USED = 14,
 206         BNXT_ULP_REGFILE_INDEX_LAST = 15
 207 };
 208
 209 enum bnxt_ulp_result_opc {
 210         BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT = 0,
 211         BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP = 1,
 212         BNXT_ULP_RESULT_OPC_SET_TO_ACT_BIT = 2,
 213         BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 3,
 214         BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 4,
 215         BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE = 5,
 216         BNXT_ULP_RESULT_OPC_SET_TO_COMP_FIELD = 6,
 217         BNXT_ULP_RESULT_OPC_LAST = 7
 218 };
 219
 220 enum bnxt_ulp_search_before_alloc {
 221         BNXT_ULP_SEARCH_BEFORE_ALLOC_NO = 0,
 222         BNXT_ULP_SEARCH_BEFORE_ALLOC_YES = 1,
 223         BNXT_ULP_SEARCH_BEFORE_ALLOC_LAST = 2
 224 };
 225
 226 enum bnxt_ulp_spec_opc {
 227         BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT = 0,
 228         BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD = 1,
 229         BNXT_ULP_SPEC_OPC_SET_TO_COMP_FIELD = 2,
 230         BNXT_ULP_SPEC_OPC_SET_TO_REGFILE = 3,
 231         BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE = 4,
 232         BNXT_ULP_SPEC_OPC_ADD_PAD = 5,
 233         BNXT_ULP_SPEC_OPC_LAST = 6
 234 };
 235
 236 enum bnxt_ulp_encap_vtag_encoding {
 237         BNXT_ULP_ENCAP_VTAG_ENCODING_DTAG_ECAP_PRI = 4,
 238         BNXT_ULP_ENCAP_VTAG_ENCODING_DTAG_REMAP_DIFFSERV = 5,
 239         BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_ECAP_PRI = 6,
 240         BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_DIFFSERV = 7,
 241         BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_0 = 8,
 242         BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_1 = 9,
 243         BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_2 = 10,
 244         BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_3 = 11,
 245         BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_4 = 12,
 246         BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_5 = 13,
 247         BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_6 = 14,
 248         BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_7 = 15,
 249         BNXT_ULP_ENCAP_VTAG_ENCODING_NOP = 0,
 250         BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_ECAP_PRI = 1,
 251         BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_IVLAN_PRI = 2,
 252         BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_REMAP_DIFFSERV = 3
 253 };
 254
 255 enum bnxt_ulp_fdb_resource_flags {
 256         BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01,
 257         BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00
 258 };
 259
 260 enum bnxt_ulp_fdb_type {
 261         BNXT_ULP_FDB_TYPE_DEFAULT = 1,
 262         BNXT_ULP_FDB_TYPE_REGULAR = 0
 263 };
 264
 265 enum bnxt_ulp_flow_dir_bitmask {
 266         BNXT_ULP_FLOW_DIR_BITMASK_EGR = 0x8000000000000000,
 267         BNXT_ULP_FLOW_DIR_BITMASK_ING = 0x0000000000000000
 268 };
 269
 270 enum bnxt_ulp_match_type_bitmask {
 271         BNXT_ULP_MATCH_TYPE_BITMASK_EM = 0x0000000000000000,
 272         BNXT_ULP_MATCH_TYPE_BITMASK_WM = 0x0000000000000001
 273 };
 274
 275 enum bnxt_ulp_resource_func {
 276         BNXT_ULP_RESOURCE_FUNC_INVALID = 0x00,
 277         BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 0x20,
 278         BNXT_ULP_RESOURCE_FUNC_RSVD1 = 0x40,
 279         BNXT_ULP_RESOURCE_FUNC_RSVD2 = 0x60,
 280         BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0x80,
 281         BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 0x81,
 282         BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE = 0x82,
 283         BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 0x83,
 284         BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84,
 285         BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85
 286 };
 287
 288 enum bnxt_ulp_resource_sub_type {
 289         BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM = 0,
 290         BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM = 1,
 291         BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_CNT_IDX = 3,
 292         BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_CNT_IDX = 2,
 293         BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL = 0,
 294         BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_ACT_IDX = 1,
 295         BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED = 0
 296 };
 297
 298 enum bnxt_ulp_sym {
 299         BNXT_ULP_SYM_BIG_ENDIAN = 0,
 300         BNXT_ULP_SYM_DECAP_FUNC_NONE = 0,
 301         BNXT_ULP_SYM_DECAP_FUNC_THRU_L2 = 11,
 302         BNXT_ULP_SYM_DECAP_FUNC_THRU_L3 = 12,
 303         BNXT_ULP_SYM_DECAP_FUNC_THRU_L4 = 13,
 304         BNXT_ULP_SYM_DECAP_FUNC_THRU_TL2 = 3,
 305         BNXT_ULP_SYM_DECAP_FUNC_THRU_TL3 = 8,
 306         BNXT_ULP_SYM_DECAP_FUNC_THRU_TL4 = 9,
 307         BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN = 10,
 308         BNXT_ULP_SYM_ECV_CUSTOM_EN_NO = 0,
 309         BNXT_ULP_SYM_ECV_CUSTOM_EN_YES = 1,
 310         BNXT_ULP_SYM_ECV_L2_EN_NO = 0,
 311         BNXT_ULP_SYM_ECV_L2_EN_YES = 1,
 312         BNXT_ULP_SYM_ECV_L3_TYPE_IPV4 = 4,
 313         BNXT_ULP_SYM_ECV_L3_TYPE_IPV6 = 5,
 314         BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8847 = 6,
 315         BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8848 = 7,
 316         BNXT_ULP_SYM_ECV_L3_TYPE_NONE = 0,
 317         BNXT_ULP_SYM_ECV_L4_TYPE_NONE = 0,
 318         BNXT_ULP_SYM_ECV_L4_TYPE_UDP = 4,
 319         BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM = 5,
 320         BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,
 321         BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,
 322         BNXT_ULP_SYM_ECV_TUN_TYPE_GENERIC = 1,
 323         BNXT_ULP_SYM_ECV_TUN_TYPE_GRE = 5,
 324         BNXT_ULP_SYM_ECV_TUN_TYPE_NGE = 3,
 325         BNXT_ULP_SYM_ECV_TUN_TYPE_NONE = 0,
 326         BNXT_ULP_SYM_ECV_TUN_TYPE_NVGRE = 4,
 327         BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2,
 328         BNXT_ULP_SYM_ECV_VALID_NO = 0,
 329         BNXT_ULP_SYM_ECV_VALID_YES = 1,
 330         BNXT_ULP_SYM_IP_PROTO_UDP = 17,
 331         BNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0,
 332         BNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2,
 333         BNXT_ULP_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
 334         BNXT_ULP_SYM_L3_HDR_TYPE_ARP = 2,
 335         BNXT_ULP_SYM_L3_HDR_TYPE_EAPOL = 4,
 336         BNXT_ULP_SYM_L3_HDR_TYPE_FCOE = 6,
 337         BNXT_ULP_SYM_L3_HDR_TYPE_IPV4 = 0,
 338         BNXT_ULP_SYM_L3_HDR_TYPE_IPV6 = 1,
 339         BNXT_ULP_SYM_L3_HDR_TYPE_PTP = 3,
 340         BNXT_ULP_SYM_L3_HDR_TYPE_ROCE = 5,
 341         BNXT_ULP_SYM_L3_HDR_TYPE_UPAR1 = 7,
 342         BNXT_ULP_SYM_L3_HDR_TYPE_UPAR2 = 8,
 343         BNXT_ULP_SYM_L4_HDR_TYPE_BTH_V1 = 5,
 344         BNXT_ULP_SYM_L4_HDR_TYPE_ICMP = 2,
 345         BNXT_ULP_SYM_L4_HDR_TYPE_TCP = 0,
 346         BNXT_ULP_SYM_L4_HDR_TYPE_UDP = 1,
 347         BNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3,
 348         BNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4,
 349         BNXT_ULP_SYM_LITTLE_ENDIAN = 1,
 350         BNXT_ULP_SYM_MATCH_TYPE_EM = 0,
 351         BNXT_ULP_SYM_MATCH_TYPE_WM = 1,
 352         BNXT_ULP_SYM_NO = 0,
 353         BNXT_ULP_SYM_PKT_TYPE_L2 = 0,
 354         BNXT_ULP_SYM_POP_VLAN_NO = 0,
 355         BNXT_ULP_SYM_POP_VLAN_YES = 1,
 356         BNXT_ULP_SYM_STINGRAY2_LOOPBACK_PORT = 3,
 357         BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT = 3,
 358         BNXT_ULP_SYM_THOR_LOOPBACK_PORT = 3,
 359         BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0,
 360         BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4 = 0,
 361         BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6 = 1,
 362         BNXT_ULP_SYM_TL4_HDR_TYPE_TCP = 0,
 363         BNXT_ULP_SYM_TL4_HDR_TYPE_UDP = 1,
 364         BNXT_ULP_SYM_TUN_HDR_TYPE_GENEVE = 1,
 365         BNXT_ULP_SYM_TUN_HDR_TYPE_GRE = 3,
 366         BNXT_ULP_SYM_TUN_HDR_TYPE_IPV4 = 4,
 367         BNXT_ULP_SYM_TUN_HDR_TYPE_IPV6 = 5,
 368         BNXT_ULP_SYM_TUN_HDR_TYPE_MPLS = 7,
 369         BNXT_ULP_SYM_TUN_HDR_TYPE_NONE = 15,
 370         BNXT_ULP_SYM_TUN_HDR_TYPE_NVGRE = 2,
 371         BNXT_ULP_SYM_TUN_HDR_TYPE_PPPOE = 6,
 372         BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR1 = 8,
 373         BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR2 = 9,
 374         BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0,
 375         BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT = 3,
 376         BNXT_ULP_SYM_YES = 1
 377 };
 378
 379 enum bnxt_ulp_act_prop_sz {
 380         BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ = 4,
 381         BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ = 4,
 382         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ = 4,
 383         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE = 4,
 384         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM = 4,
 385         BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE = 4,
 386         BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM = 4,
 387         BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM = 4,
 388         BNXT_ULP_ACT_PROP_SZ_PORT_ID = 4,
 389         BNXT_ULP_ACT_PROP_SZ_VNIC = 4,
 390         BNXT_ULP_ACT_PROP_SZ_VPORT = 4,
 391         BNXT_ULP_ACT_PROP_SZ_MARK = 4,
 392         BNXT_ULP_ACT_PROP_SZ_COUNT = 4,
 393         BNXT_ULP_ACT_PROP_SZ_METER = 4,
 394         BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC = 8,
 395         BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST = 8,
 396         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_VLAN = 4,
 397         BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_PCP = 4,
 398         BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_VID = 4,
 399         BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC = 4,
 400         BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST = 4,
 401         BNXT_ULP_ACT_PROP_SZ_SET_IPV6_SRC = 16,
 402         BNXT_ULP_ACT_PROP_SZ_SET_IPV6_DST = 16,
 403         BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC = 4,
 404         BNXT_ULP_ACT_PROP_SZ_SET_TP_DST = 4,
 405         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_0 = 4,
 406         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_1 = 4,
 407         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_2 = 4,
 408         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_3 = 4,
 409         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_4 = 4,
 410         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_5 = 4,
 411         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_6 = 4,
 412         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_7 = 4,
 413         BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC = 6,
 414         BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC = 6,
 415         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG = 8,
 416         BNXT_ULP_ACT_PROP_SZ_ENCAP_IP = 32,
 417         BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC = 16,
 418         BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP = 4,
 419         BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32,
 420         BNXT_ULP_ACT_PROP_SZ_LAST = 4
 421 };
 422
 423 enum bnxt_ulp_act_prop_idx {
 424         BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ = 0,
 425         BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ = 4,
 426         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ = 8,
 427         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE = 12,
 428         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM = 16,
 429         BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE = 20,
 430         BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM = 24,
 431         BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM = 28,
 432         BNXT_ULP_ACT_PROP_IDX_PORT_ID = 32,
 433         BNXT_ULP_ACT_PROP_IDX_VNIC = 36,
 434         BNXT_ULP_ACT_PROP_IDX_VPORT = 40,
 435         BNXT_ULP_ACT_PROP_IDX_MARK = 44,
 436         BNXT_ULP_ACT_PROP_IDX_COUNT = 48,
 437         BNXT_ULP_ACT_PROP_IDX_METER = 52,
 438         BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC = 56,
 439         BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 64,
 440         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_VLAN = 72,
 441         BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_PCP = 76,
 442         BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_VID = 80,
 443         BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 84,
 444         BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 88,
 445         BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 92,
 446         BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 108,
 447         BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 124,
 448         BNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 128,
 449         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 132,
 450         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 136,
 451         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 140,
 452         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 144,
 453         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 148,
 454         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 152,
 455         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 156,
 456         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 160,
 457         BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 164,
 458         BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 170,
 459         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 176,
 460         BNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 184,
 461         BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 216,
 462         BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 232,
 463         BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 236,
 464         BNXT_ULP_ACT_PROP_IDX_LAST = 268
 465 };
 466
 467 enum bnxt_ulp_class_hid {
 468         BNXT_ULP_CLASS_HID_0013 = 0x0013
 469 };
 470
 471 enum bnxt_ulp_act_hid {
 472         BNXT_ULP_ACT_HID_0029 = 0x0029
 473 };
 474
 475 #endif