drivers/net/cnxk/cn9k_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #include "cn9k_ethdev.h"
   6 #include "cn9k_rx.h"
   7
   8 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
   9         uint16_t __rte_noinline __rte_hot cn9k_nix_recv_pkts_##name(           \
  10                 void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts)      \
  11         {                                                                      \
  12                 return cn9k_nix_recv_pkts(rx_queue, rx_pkts, pkts, (flags));   \
  13         }
  14
  15 NIX_RX_FASTPATH_MODES
  16 #undef R
  17
  18 static inline void
  19 pick_rx_func(struct rte_eth_dev *eth_dev,
  20              const eth_rx_burst_t rx_burst[2][2][2][2][2][2][2])
  21 {
  22         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
  23
  24         /* [TSP] [MARK] [VLAN] [CKSUM] [PTYPE] [RSS] */
  25         eth_dev->rx_pkt_burst = rx_burst
  26                 [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_SECURITY_F)]
  27                 [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
  28                 [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_TSTAMP_F)]
  29                 [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
  30                 [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_CHECKSUM_F)]
  31                 [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_PTYPE_F)]
  32                 [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_RSS_F)];
  33
  34         rte_atomic_thread_fence(__ATOMIC_RELEASE);
  35 }
  36
  37 void
  38 cn9k_eth_set_rx_function(struct rte_eth_dev *eth_dev)
  39 {
  40         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
  41
  42         const eth_rx_burst_t nix_eth_rx_burst[2][2][2][2][2][2][2] = {
  43 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
  44         [f6][f5][f4][f3][f2][f1][f0] = cn9k_nix_recv_pkts_##name,
  45
  46                 NIX_RX_FASTPATH_MODES
  47 #undef R
  48         };
  49
  50         const eth_rx_burst_t nix_eth_rx_burst_mseg[2][2][2][2][2][2][2] = {
  51 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
  52         [f6][f5][f4][f3][f2][f1][f0] = cn9k_nix_recv_pkts_mseg_##name,
  53
  54                 NIX_RX_FASTPATH_MODES
  55 #undef R
  56         };
  57
  58         const eth_rx_burst_t nix_eth_rx_vec_burst[2][2][2][2][2][2][2] = {
  59 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
  60         [f6][f5][f4][f3][f2][f1][f0] = cn9k_nix_recv_pkts_vec_##name,
  61
  62                 NIX_RX_FASTPATH_MODES
  63 #undef R
  64         };
  65
  66         const eth_rx_burst_t nix_eth_rx_vec_burst_mseg[2][2][2][2][2][2][2] = {
  67 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                             \
  68         [f6][f5][f4][f3][f2][f1][f0] = cn9k_nix_recv_pkts_vec_mseg_##name,
  69
  70                 NIX_RX_FASTPATH_MODES
  71 #undef R
  72         };
  73
  74         /* Copy multi seg version with no offload for tear down sequence */
  75         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
  76                 dev->rx_pkt_burst_no_offload =
  77                         nix_eth_rx_burst_mseg[0][0][0][0][0][0][0];
  78
  79         if (dev->scalar_ena) {
  80                 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
  81                         return pick_rx_func(eth_dev, nix_eth_rx_burst_mseg);
  82                 return pick_rx_func(eth_dev, nix_eth_rx_burst);
  83         }
  84
  85         if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
  86                 return pick_rx_func(eth_dev, nix_eth_rx_vec_burst_mseg);
  87         return pick_rx_func(eth_dev, nix_eth_rx_vec_burst);
  88 }