drivers/net/cnxk/cnxk_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #ifndef __CNXK_ETHDEV_H__
   5 #define __CNXK_ETHDEV_H__
   6
   7 #include <math.h>
   8 #include <stdint.h>
   9
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_kvargs.h>
  13 #include <rte_mbuf.h>
  14 #include <rte_mbuf_pool_ops.h>
  15 #include <rte_mempool.h>
  16 #include <rte_mtr_driver.h>
  17 #include <rte_security.h>
  18 #include <rte_security_driver.h>
  19 #include <rte_tailq.h>
  20 #include <rte_time.h>
  21
  22 #include "roc_api.h"
  23
  24 #define CNXK_ETH_DEV_PMD_VERSION "1.0"
  25
  26 /* Used for struct cnxk_eth_dev::flags */
  27 #define CNXK_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
  28
  29 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
  30  * In Tx space is always reserved for this in FRS.
  31  */
  32 #define CNXK_NIX_MAX_VTAG_INS      2
  33 #define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS)
  34
  35 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
  36 #define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + \
  37                               RTE_ETHER_CRC_LEN + \
  38                               CNXK_NIX_MAX_VTAG_ACT_SIZE)
  39
  40 #define CNXK_NIX_RX_MIN_DESC        16
  41 #define CNXK_NIX_RX_MIN_DESC_ALIGN  16
  42 #define CNXK_NIX_RX_NB_SEG_MAX      6
  43 #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
  44 /* Max supported SQB count */
  45 #define CNXK_NIX_TX_MAX_SQB 512
  46
  47 /* If PTP is enabled additional SEND MEM DESC is required which
  48  * takes 2 words, hence max 7 iova address are possible
  49  */
  50 #if defined(RTE_LIBRTE_IEEE1588)
  51 #define CNXK_NIX_TX_NB_SEG_MAX 7
  52 #else
  53 #define CNXK_NIX_TX_NB_SEG_MAX 9
  54 #endif
  55
  56 #define CNXK_NIX_TX_MSEG_SG_DWORDS                                             \
  57         ((RTE_ALIGN_MUL_CEIL(CNXK_NIX_TX_NB_SEG_MAX, 3) / 3) +                 \
  58          CNXK_NIX_TX_NB_SEG_MAX)
  59
  60 #define CNXK_NIX_RSS_L3_L4_SRC_DST                                             \
  61         (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY |     \
  62          ETH_RSS_L4_DST_ONLY)
  63
  64 #define CNXK_NIX_RSS_OFFLOAD                                                   \
  65         (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP |               \
  66          ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD |                  \
  67          CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN)
  68
  69 #define CNXK_NIX_TX_OFFLOAD_CAPA                                               \
  70         (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE |          \
  71          DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT |             \
  72          DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM |    \
  73          DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM |                 \
  74          DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO |                  \
  75          DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO |        \
  76          DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS |              \
  77          DEV_TX_OFFLOAD_IPV4_CKSUM | DEV_TX_OFFLOAD_SECURITY)
  78
  79 #define CNXK_NIX_RX_OFFLOAD_CAPA                                               \
  80         (DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM |                 \
  81          DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER |            \
  82          DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | DEV_RX_OFFLOAD_RSS_HASH |            \
  83          DEV_RX_OFFLOAD_TIMESTAMP | DEV_RX_OFFLOAD_VLAN_STRIP |                \
  84          DEV_RX_OFFLOAD_SECURITY)
  85
  86 #define RSS_IPV4_ENABLE                                                        \
  87         (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_UDP |         \
  88          ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_SCTP)
  89
  90 #define RSS_IPV6_ENABLE                                                        \
  91         (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_UDP |         \
  92          ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_NONFRAG_IPV6_SCTP)
  93
  94 #define RSS_IPV6_EX_ENABLE                                                     \
  95         (ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | ETH_RSS_IPV6_UDP_EX)
  96
  97 #define RSS_MAX_LEVELS 3
  98
  99 #define RSS_IPV4_INDEX 0
 100 #define RSS_IPV6_INDEX 1
 101 #define RSS_TCP_INDEX  2
 102 #define RSS_UDP_INDEX  3
 103 #define RSS_SCTP_INDEX 4
 104 #define RSS_DMAC_INDEX 5
 105
 106 /* Default mark value used when none is provided. */
 107 #define CNXK_FLOW_ACTION_FLAG_DEFAULT 0xffff
 108
 109 /* Default cycle counter mask */
 110 #define CNXK_CYCLECOUNTER_MASK     0xffffffffffffffffULL
 111 #define CNXK_NIX_TIMESYNC_RX_OFFSET 8
 112
 113 #define PTYPE_NON_TUNNEL_WIDTH    16
 114 #define PTYPE_TUNNEL_WIDTH        12
 115 #define PTYPE_NON_TUNNEL_ARRAY_SZ BIT(PTYPE_NON_TUNNEL_WIDTH)
 116 #define PTYPE_TUNNEL_ARRAY_SZ     BIT(PTYPE_TUNNEL_WIDTH)
 117 #define PTYPE_ARRAY_SZ                                                         \
 118         ((PTYPE_NON_TUNNEL_ARRAY_SZ + PTYPE_TUNNEL_ARRAY_SZ) * sizeof(uint16_t))
 119
 120 /* NIX_RX_PARSE_S's ERRCODE + ERRLEV (12 bits) */
 121 #define ERRCODE_ERRLEN_WIDTH 12
 122 #define ERR_ARRAY_SZ         ((BIT(ERRCODE_ERRLEN_WIDTH)) * sizeof(uint32_t))
 123
 124 /* Fastpath lookup */
 125 #define CNXK_NIX_FASTPATH_LOOKUP_MEM "cnxk_nix_fastpath_lookup_mem"
 126
 127 #define CNXK_NIX_UDP_TUN_BITMASK                                               \
 128         ((1ull << (PKT_TX_TUNNEL_VXLAN >> 45)) |                               \
 129          (1ull << (PKT_TX_TUNNEL_GENEVE >> 45)))
 130
 131 /* Subtype from inline outbound error event */
 132 #define CNXK_ETHDEV_SEC_OUTB_EV_SUB 0xFFUL
 133
 134 /* SPI will be in 20 bits of tag */
 135 #define CNXK_ETHDEV_SPI_TAG_MASK 0xFFFFFUL
 136
 137 struct cnxk_fc_cfg {
 138         enum rte_eth_fc_mode mode;
 139         uint8_t rx_pause;
 140         uint8_t tx_pause;
 141 };
 142
 143 struct cnxk_eth_qconf {
 144         union {
 145                 struct rte_eth_txconf tx;
 146                 struct rte_eth_rxconf rx;
 147         } conf;
 148         struct rte_mempool *mp;
 149         uint16_t nb_desc;
 150         uint8_t valid;
 151 };
 152
 153 struct cnxk_timesync_info {
 154         uint8_t rx_ready;
 155         uint64_t rx_tstamp;
 156         uint64_t rx_tstamp_dynflag;
 157         int tstamp_dynfield_offset;
 158         rte_iova_t tx_tstamp_iova;
 159         uint64_t *tx_tstamp;
 160 } __plt_cache_aligned;
 161
 162 struct cnxk_meter_node {
 163 #define MAX_PRV_MTR_NODES 10
 164         TAILQ_ENTRY(cnxk_meter_node) next;
 165         /**< Pointer to the next flow meter structure. */
 166         uint32_t id; /**< Usr mtr id. */
 167         struct cnxk_mtr_profile_node *profile;
 168         struct cnxk_mtr_policy_node *policy;
 169         uint32_t bpf_id; /**< Hw mtr id. */
 170         uint32_t rq_num;
 171         uint32_t *rq_id;
 172         uint16_t level;
 173         uint32_t prev_id[MAX_PRV_MTR_NODES]; /**< Prev mtr id for chaining */
 174         uint32_t prev_cnt;
 175         uint32_t next_id; /**< Next mtr id for chaining */
 176         bool is_prev;
 177         bool is_next;
 178         struct rte_mtr_params params;
 179         struct roc_nix_bpf_objs profs;
 180         bool is_used;
 181         uint32_t ref_cnt;
 182 };
 183
 184 struct action_rss {
 185         enum rte_eth_hash_function func;
 186         uint32_t level;
 187         uint64_t types;
 188         uint32_t key_len;
 189         uint32_t queue_num;
 190         uint8_t *key;
 191         uint16_t *queue;
 192 };
 193
 194 struct policy_actions {
 195         uint32_t action_fate;
 196         union {
 197                 uint16_t queue;
 198                 uint32_t mtr_id;
 199                 struct action_rss *rss_desc;
 200         };
 201 };
 202
 203 struct cnxk_mtr_policy_node {
 204         TAILQ_ENTRY(cnxk_mtr_policy_node) next;
 205         /**< Pointer to the next flow meter structure. */
 206         uint32_t id;     /**< Policy id */
 207         uint32_t mtr_id; /** Meter id */
 208         struct rte_mtr_meter_policy_params policy;
 209         struct policy_actions actions[RTE_COLORS];
 210         uint32_t ref_cnt;
 211 };
 212
 213 struct cnxk_mtr_profile_node {
 214         TAILQ_ENTRY(cnxk_mtr_profile_node) next;
 215         struct rte_mtr_meter_profile profile; /**< Profile detail. */
 216         uint32_t ref_cnt;                     /**< Use count. */
 217         uint32_t id;                          /**< Profile id. */
 218 };
 219
 220 TAILQ_HEAD(cnxk_mtr_profiles, cnxk_mtr_profile_node);
 221 TAILQ_HEAD(cnxk_mtr_policy, cnxk_mtr_policy_node);
 222 TAILQ_HEAD(cnxk_mtr, cnxk_meter_node);
 223
 224 /* Security session private data */
 225 struct cnxk_eth_sec_sess {
 226         /* List entry */
 227         TAILQ_ENTRY(cnxk_eth_sec_sess) entry;
 228
 229         /* Inbound SA is from NIX_RX_IPSEC_SA_BASE or
 230          * Outbound SA from roc_nix_inl_outb_sa_base_get()
 231          */
 232         void *sa;
 233
 234         /* SA index */
 235         uint32_t sa_idx;
 236
 237         /* SPI */
 238         uint32_t spi;
 239
 240         /* Back pointer to session */
 241         struct rte_security_session *sess;
 242
 243         /* Inbound */
 244         bool inb;
 245
 246         /* Inbound session on inl dev */
 247         bool inl_dev;
 248 };
 249
 250 TAILQ_HEAD(cnxk_eth_sec_sess_list, cnxk_eth_sec_sess);
 251
 252 /* Inbound security data */
 253 struct cnxk_eth_dev_sec_inb {
 254         /* IPSec inbound max SPI */
 255         uint16_t max_spi;
 256
 257         /* Using inbound with inline device */
 258         bool inl_dev;
 259
 260         /* Device argument to force inline device for inb */
 261         bool force_inl_dev;
 262
 263         /* Active sessions */
 264         uint16_t nb_sess;
 265
 266         /* List of sessions */
 267         struct cnxk_eth_sec_sess_list list;
 268 };
 269
 270 /* Outbound security data */
 271 struct cnxk_eth_dev_sec_outb {
 272         /* IPSec outbound max SA */
 273         uint16_t max_sa;
 274
 275         /* Per CPT LF descriptor count */
 276         uint32_t nb_desc;
 277
 278         /* SA Bitmap */
 279         struct plt_bitmap *sa_bmap;
 280
 281         /* SA bitmap memory */
 282         void *sa_bmap_mem;
 283
 284         /* SA base */
 285         uint64_t sa_base;
 286
 287         /* CPT LF base */
 288         struct roc_cpt_lf *lf_base;
 289
 290         /* Crypto queues => CPT lf count */
 291         uint16_t nb_crypto_qs;
 292
 293         /* Active sessions */
 294         uint16_t nb_sess;
 295
 296         /* List of sessions */
 297         struct cnxk_eth_sec_sess_list list;
 298 };
 299
 300 struct cnxk_eth_dev {
 301         /* ROC NIX */
 302         struct roc_nix nix;
 303
 304         /* ROC NPC */
 305         struct roc_npc npc;
 306
 307         /* ROC RQs, SQs and CQs */
 308         struct roc_nix_rq *rqs;
 309         struct roc_nix_sq *sqs;
 310         struct roc_nix_cq *cqs;
 311
 312         /* Configured queue count */
 313         uint16_t nb_rxq;
 314         uint16_t nb_txq;
 315         uint16_t nb_rxq_sso;
 316         uint8_t configured;
 317
 318         /* Max macfilter entries */
 319         uint8_t dmac_filter_count;
 320         uint8_t max_mac_entries;
 321         bool dmac_filter_enable;
 322
 323         uint16_t flags;
 324         uint8_t ptype_disable;
 325         bool scalar_ena;
 326         bool ptp_en;
 327
 328         /* Pointer back to rte */
 329         struct rte_eth_dev *eth_dev;
 330
 331         /* HW capabilities / Limitations */
 332         union {
 333                 struct {
 334                         uint64_t cq_min_4k : 1;
 335                         uint64_t ipsecd_drop_re_dis : 1;
 336                 };
 337                 uint64_t hwcap;
 338         };
 339
 340         /* Rx and Tx offload capabilities */
 341         uint64_t rx_offload_capa;
 342         uint64_t tx_offload_capa;
 343         uint32_t speed_capa;
 344         /* Configured Rx and Tx offloads */
 345         uint64_t rx_offloads;
 346         uint64_t tx_offloads;
 347         /* Platform specific offload flags */
 348         uint16_t rx_offload_flags;
 349         uint16_t tx_offload_flags;
 350
 351         /* ETHDEV RSS HF bitmask */
 352         uint64_t ethdev_rss_hf;
 353
 354         /* Saved qconf before lf realloc */
 355         struct cnxk_eth_qconf *tx_qconf;
 356         struct cnxk_eth_qconf *rx_qconf;
 357
 358         /* Flow control configuration */
 359         struct cnxk_fc_cfg fc_cfg;
 360
 361         /* PTP Counters */
 362         struct cnxk_timesync_info tstamp;
 363         struct rte_timecounter systime_tc;
 364         struct rte_timecounter rx_tstamp_tc;
 365         struct rte_timecounter tx_tstamp_tc;
 366         double clk_freq_mult;
 367         uint64_t clk_delta;
 368
 369         /* Ingress policer */
 370         enum roc_nix_bpf_color precolor_tbl[ROC_NIX_BPF_PRE_COLOR_MAX];
 371         struct cnxk_mtr_profiles mtr_profiles;
 372         struct cnxk_mtr_policy mtr_policy;
 373         struct cnxk_mtr mtr;
 374
 375         /* Rx burst for cleanup(Only Primary) */
 376         eth_rx_burst_t rx_pkt_burst_no_offload;
 377
 378         /* Default mac address */
 379         uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
 380
 381         /* LSO Tunnel format indices */
 382         uint64_t lso_tun_fmt;
 383
 384         /* Per queue statistics counters */
 385         uint32_t txq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
 386         uint32_t rxq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
 387
 388         /* Security data */
 389         struct cnxk_eth_dev_sec_inb inb;
 390         struct cnxk_eth_dev_sec_outb outb;
 391 };
 392
 393 struct cnxk_eth_rxq_sp {
 394         struct cnxk_eth_dev *dev;
 395         struct cnxk_eth_qconf qconf;
 396         uint16_t qid;
 397 } __plt_cache_aligned;
 398
 399 struct cnxk_eth_txq_sp {
 400         struct cnxk_eth_dev *dev;
 401         struct cnxk_eth_qconf qconf;
 402         uint16_t qid;
 403 } __plt_cache_aligned;
 404
 405 static inline struct cnxk_eth_dev *
 406 cnxk_eth_pmd_priv(const struct rte_eth_dev *eth_dev)
 407 {
 408         return eth_dev->data->dev_private;
 409 }
 410
 411 static inline struct cnxk_eth_rxq_sp *
 412 cnxk_eth_rxq_to_sp(void *__rxq)
 413 {
 414         return ((struct cnxk_eth_rxq_sp *)__rxq) - 1;
 415 }
 416
 417 static inline struct cnxk_eth_txq_sp *
 418 cnxk_eth_txq_to_sp(void *__txq)
 419 {
 420         return ((struct cnxk_eth_txq_sp *)__txq) - 1;
 421 }
 422
 423 /* Common ethdev ops */
 424 extern struct eth_dev_ops cnxk_eth_dev_ops;
 425
 426 /* Common flow ops */
 427 extern struct rte_flow_ops cnxk_flow_ops;
 428
 429 /* Common security ops */
 430 extern struct rte_security_ops cnxk_eth_sec_ops;
 431
 432 /* Ops */
 433 int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
 434                    struct rte_pci_device *pci_dev);
 435 int cnxk_nix_remove(struct rte_pci_device *pci_dev);
 436 int cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
 437 int cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev,
 438                                     struct rte_ether_addr *mc_addr_set,
 439                                     uint32_t nb_mc_addr);
 440 int cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
 441                           struct rte_ether_addr *addr, uint32_t index,
 442                           uint32_t pool);
 443 void cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
 444 int cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
 445                           struct rte_ether_addr *addr);
 446 int cnxk_nix_promisc_enable(struct rte_eth_dev *eth_dev);
 447 int cnxk_nix_promisc_disable(struct rte_eth_dev *eth_dev);
 448 int cnxk_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
 449 int cnxk_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
 450 int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,
 451                       struct rte_eth_dev_info *dev_info);
 452 int cnxk_nix_rx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
 453                                struct rte_eth_burst_mode *mode);
 454 int cnxk_nix_tx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
 455                                struct rte_eth_burst_mode *mode);
 456 int cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 457                            struct rte_eth_fc_conf *fc_conf);
 458 int cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 459                            struct rte_eth_fc_conf *fc_conf);
 460 int cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev);
 461 int cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev);
 462 int cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev,
 463                              struct rte_eth_dev_module_info *modinfo);
 464 int cnxk_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
 465                                struct rte_dev_eeprom_info *info);
 466 int cnxk_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
 467                                   uint16_t rx_queue_id);
 468 int cnxk_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
 469                                    uint16_t rx_queue_id);
 470 int cnxk_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool);
 471 int cnxk_nix_tx_done_cleanup(void *txq, uint32_t free_cnt);
 472 int cnxk_nix_flow_ops_get(struct rte_eth_dev *eth_dev,
 473                           const struct rte_flow_ops **ops);
 474 int cnxk_nix_configure(struct rte_eth_dev *eth_dev);
 475 int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 476                             uint16_t nb_desc, uint16_t fp_tx_q_sz,
 477                             const struct rte_eth_txconf *tx_conf);
 478 int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 479                             uint16_t nb_desc, uint16_t fp_rx_q_sz,
 480                             const struct rte_eth_rxconf *rx_conf,
 481                             struct rte_mempool *mp);
 482 int cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid);
 483 int cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid);
 484 int cnxk_nix_dev_start(struct rte_eth_dev *eth_dev);
 485 int cnxk_nix_timesync_enable(struct rte_eth_dev *eth_dev);
 486 int cnxk_nix_timesync_disable(struct rte_eth_dev *eth_dev);
 487 int cnxk_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,
 488                                         struct timespec *timestamp,
 489                                         uint32_t flags);
 490 int cnxk_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,
 491                                         struct timespec *timestamp);
 492 int cnxk_nix_timesync_read_time(struct rte_eth_dev *eth_dev,
 493                                 struct timespec *ts);
 494 int cnxk_nix_timesync_write_time(struct rte_eth_dev *eth_dev,
 495                                  const struct timespec *ts);
 496 int cnxk_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta);
 497 int cnxk_nix_tsc_convert(struct cnxk_eth_dev *dev);
 498 int cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock);
 499
 500 uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev);
 501 int cnxk_nix_tm_ops_get(struct rte_eth_dev *eth_dev, void *ops);
 502 int cnxk_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev,
 503                                      uint16_t queue_idx, uint16_t tx_rate);
 504
 505 /* MTR */
 506 int cnxk_nix_mtr_ops_get(struct rte_eth_dev *dev, void *ops);
 507
 508 /* RSS */
 509 uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
 510                                 uint8_t rss_level);
 511 int cnxk_nix_reta_update(struct rte_eth_dev *eth_dev,
 512                          struct rte_eth_rss_reta_entry64 *reta_conf,
 513                          uint16_t reta_size);
 514 int cnxk_nix_reta_query(struct rte_eth_dev *eth_dev,
 515                         struct rte_eth_rss_reta_entry64 *reta_conf,
 516                         uint16_t reta_size);
 517 int cnxk_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
 518                              struct rte_eth_rss_conf *rss_conf);
 519 int cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
 520                                struct rte_eth_rss_conf *rss_conf);
 521
 522 /* Link */
 523 void cnxk_nix_toggle_flag_link_cfg(struct cnxk_eth_dev *dev, bool set);
 524 void cnxk_eth_dev_link_status_cb(struct roc_nix *nix,
 525                                  struct roc_nix_link_info *link);
 526 void cnxk_eth_dev_link_status_get_cb(struct roc_nix *nix,
 527                                      struct roc_nix_link_info *link);
 528 int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
 529 int cnxk_nix_queue_stats_mapping(struct rte_eth_dev *dev, uint16_t queue_id,
 530                                  uint8_t stat_idx, uint8_t is_rx);
 531 int cnxk_nix_stats_reset(struct rte_eth_dev *dev);
 532 int cnxk_nix_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 533 int cnxk_nix_xstats_get(struct rte_eth_dev *eth_dev,
 534                         struct rte_eth_xstat *xstats, unsigned int n);
 535 int cnxk_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
 536                               struct rte_eth_xstat_name *xstats_names,
 537                               unsigned int limit);
 538 int cnxk_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
 539                                     const uint64_t *ids,
 540                                     struct rte_eth_xstat_name *xstats_names,
 541                                     unsigned int limit);
 542 int cnxk_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids,
 543                               uint64_t *values, unsigned int n);
 544 int cnxk_nix_xstats_reset(struct rte_eth_dev *eth_dev);
 545 int cnxk_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
 546                             size_t fw_size);
 547 void cnxk_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
 548                            struct rte_eth_rxq_info *qinfo);
 549 void cnxk_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
 550                            struct rte_eth_txq_info *qinfo);
 551
 552 /* Lookup configuration */
 553 const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev);
 554 void *cnxk_nix_fastpath_lookup_mem_get(void);
 555
 556 /* Devargs */
 557 int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
 558                               struct cnxk_eth_dev *dev);
 559
 560 /* Debug */
 561 int cnxk_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
 562                          struct rte_dev_reg_info *regs);
 563 /* Security */
 564 int cnxk_eth_outb_sa_idx_get(struct cnxk_eth_dev *dev, uint32_t *idx_p);
 565 int cnxk_eth_outb_sa_idx_put(struct cnxk_eth_dev *dev, uint32_t idx);
 566 int cnxk_nix_lookup_mem_sa_base_set(struct cnxk_eth_dev *dev);
 567 int cnxk_nix_lookup_mem_sa_base_clear(struct cnxk_eth_dev *dev);
 568 __rte_internal
 569 int cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev);
 570 struct cnxk_eth_sec_sess *cnxk_eth_sec_sess_get_by_spi(struct cnxk_eth_dev *dev,
 571                                                        uint32_t spi, bool inb);
 572 struct cnxk_eth_sec_sess *
 573 cnxk_eth_sec_sess_get_by_sess(struct cnxk_eth_dev *dev,
 574                               struct rte_security_session *sess);
 575
 576 /* Other private functions */
 577 int nix_recalc_mtu(struct rte_eth_dev *eth_dev);
 578 int nix_mtr_validate(struct rte_eth_dev *dev, uint32_t id);
 579 int nix_mtr_policy_act_get(struct rte_eth_dev *eth_dev, uint32_t id,
 580                            struct cnxk_mtr_policy_node **policy);
 581 int nix_mtr_rq_update(struct rte_eth_dev *eth_dev, uint32_t id,
 582                       uint32_t queue_num, const uint16_t *queue);
 583 int nix_mtr_chain_update(struct rte_eth_dev *eth_dev, uint32_t cur_id,
 584                          uint32_t prev_id, uint32_t next_id);
 585 int nix_mtr_chain_reset(struct rte_eth_dev *eth_dev, uint32_t cur_id);
 586 struct cnxk_meter_node *nix_get_mtr(struct rte_eth_dev *eth_dev,
 587                                     uint32_t cur_id);
 588 int nix_mtr_level_update(struct rte_eth_dev *eth_dev, uint32_t id,
 589                          uint32_t level);
 590 int nix_mtr_configure(struct rte_eth_dev *eth_dev, uint32_t id);
 591 int nix_mtr_connect(struct rte_eth_dev *eth_dev, uint32_t id);
 592 int nix_mtr_destroy(struct rte_eth_dev *eth_dev, uint32_t id,
 593                     struct rte_mtr_error *error);
 594 int nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t id,
 595                                   uint32_t *prev_id, uint32_t *next_id,
 596                                   struct cnxk_mtr_policy_node *policy,
 597                                   int *tree_level);
 598
 599 /* Inlines */
 600 static __rte_always_inline uint64_t
 601 cnxk_pktmbuf_detach(struct rte_mbuf *m)
 602 {
 603         struct rte_mempool *mp = m->pool;
 604         uint32_t mbuf_size, buf_len;
 605         struct rte_mbuf *md;
 606         uint16_t priv_size;
 607         uint16_t refcount;
 608
 609         /* Update refcount of direct mbuf */
 610         md = rte_mbuf_from_indirect(m);
 611         refcount = rte_mbuf_refcnt_update(md, -1);
 612
 613         priv_size = rte_pktmbuf_priv_size(mp);
 614         mbuf_size = (uint32_t)(sizeof(struct rte_mbuf) + priv_size);
 615         buf_len = rte_pktmbuf_data_room_size(mp);
 616
 617         m->priv_size = priv_size;
 618         m->buf_addr = (char *)m + mbuf_size;
 619         m->buf_iova = rte_mempool_virt2iova(m) + mbuf_size;
 620         m->buf_len = (uint16_t)buf_len;
 621         rte_pktmbuf_reset_headroom(m);
 622         m->data_len = 0;
 623         m->ol_flags = 0;
 624         m->next = NULL;
 625         m->nb_segs = 1;
 626
 627         /* Now indirect mbuf is safe to free */
 628         rte_pktmbuf_free(m);
 629
 630         if (refcount == 0) {
 631                 rte_mbuf_refcnt_set(md, 1);
 632                 md->data_len = 0;
 633                 md->ol_flags = 0;
 634                 md->next = NULL;
 635                 md->nb_segs = 1;
 636                 return 0;
 637         } else {
 638                 return 1;
 639         }
 640 }
 641
 642 static __rte_always_inline uint64_t
 643 cnxk_nix_prefree_seg(struct rte_mbuf *m)
 644 {
 645         if (likely(rte_mbuf_refcnt_read(m) == 1)) {
 646                 if (!RTE_MBUF_DIRECT(m))
 647                         return cnxk_pktmbuf_detach(m);
 648
 649                 m->next = NULL;
 650                 m->nb_segs = 1;
 651                 return 0;
 652         } else if (rte_mbuf_refcnt_update(m, -1) == 0) {
 653                 if (!RTE_MBUF_DIRECT(m))
 654                         return cnxk_pktmbuf_detach(m);
 655
 656                 rte_mbuf_refcnt_set(m, 1);
 657                 m->next = NULL;
 658                 m->nb_segs = 1;
 659                 return 0;
 660         }
 661
 662         /* Mbuf is having refcount more than 1 so need not to be freed */
 663         return 1;
 664 }
 665
 666 static inline rte_mbuf_timestamp_t *
 667 cnxk_nix_timestamp_dynfield(struct rte_mbuf *mbuf,
 668                             struct cnxk_timesync_info *info)
 669 {
 670         return RTE_MBUF_DYNFIELD(mbuf, info->tstamp_dynfield_offset,
 671                                  rte_mbuf_timestamp_t *);
 672 }
 673
 674 static __rte_always_inline void
 675 cnxk_nix_mbuf_to_tstamp(struct rte_mbuf *mbuf,
 676                         struct cnxk_timesync_info *tstamp,
 677                         const uint8_t ts_enable, const uint8_t mseg_enable,
 678                         uint64_t *tstamp_ptr)
 679 {
 680         if (ts_enable) {
 681                 if (!mseg_enable) {
 682                         mbuf->pkt_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;
 683                         mbuf->data_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;
 684                 }
 685
 686                 /* Reading the rx timestamp inserted by CGX, viz at
 687                  * starting of the packet data.
 688                  */
 689                 *cnxk_nix_timestamp_dynfield(mbuf, tstamp) =
 690                         rte_be_to_cpu_64(*tstamp_ptr);
 691                 /* PKT_RX_IEEE1588_TMST flag needs to be set only in case
 692                  * PTP packets are received.
 693                  */
 694                 if (mbuf->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC) {
 695                         tstamp->rx_tstamp =
 696                                 *cnxk_nix_timestamp_dynfield(mbuf, tstamp);
 697                         tstamp->rx_ready = 1;
 698                         mbuf->ol_flags |= PKT_RX_IEEE1588_PTP |
 699                                           PKT_RX_IEEE1588_TMST |
 700                                           tstamp->rx_tstamp_dynflag;
 701                 }
 702         }
 703 }
 704
 705 static __rte_always_inline uintptr_t
 706 cnxk_nix_sa_base_get(uint16_t port, const void *lookup_mem)
 707 {
 708         uintptr_t sa_base_tbl;
 709
 710         sa_base_tbl = (uintptr_t)lookup_mem;
 711         sa_base_tbl += PTYPE_ARRAY_SZ + ERR_ARRAY_SZ;
 712         return *((const uintptr_t *)sa_base_tbl + port);
 713 }
 714
 715 #endif /* __CNXK_ETHDEV_H__ */