drivers/net/cnxk/cnxk_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #ifndef __CNXK_ETHDEV_H__
   5 #define __CNXK_ETHDEV_H__
   6
   7 #include <math.h>
   8 #include <stdint.h>
   9
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_kvargs.h>
  13 #include <rte_mbuf.h>
  14 #include <rte_mbuf_pool_ops.h>
  15 #include <rte_mempool.h>
  16 #include <rte_time.h>
  17
  18 #include "roc_api.h"
  19
  20 #define CNXK_ETH_DEV_PMD_VERSION "1.0"
  21
  22 /* Used for struct cnxk_eth_dev::flags */
  23 #define CNXK_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
  24
  25 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
  26  * In Tx space is always reserved for this in FRS.
  27  */
  28 #define CNXK_NIX_MAX_VTAG_INS      2
  29 #define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS)
  30
  31 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
  32 #define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + \
  33                               RTE_ETHER_CRC_LEN + \
  34                               CNXK_NIX_MAX_VTAG_ACT_SIZE)
  35
  36 #define CNXK_NIX_RX_MIN_DESC        16
  37 #define CNXK_NIX_RX_MIN_DESC_ALIGN  16
  38 #define CNXK_NIX_RX_NB_SEG_MAX      6
  39 #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
  40 /* Max supported SQB count */
  41 #define CNXK_NIX_TX_MAX_SQB 512
  42
  43 /* If PTP is enabled additional SEND MEM DESC is required which
  44  * takes 2 words, hence max 7 iova address are possible
  45  */
  46 #if defined(RTE_LIBRTE_IEEE1588)
  47 #define CNXK_NIX_TX_NB_SEG_MAX 7
  48 #else
  49 #define CNXK_NIX_TX_NB_SEG_MAX 9
  50 #endif
  51
  52 #define CNXK_NIX_TX_MSEG_SG_DWORDS                                             \
  53         ((RTE_ALIGN_MUL_CEIL(CNXK_NIX_TX_NB_SEG_MAX, 3) / 3) +                 \
  54          CNXK_NIX_TX_NB_SEG_MAX)
  55
  56 #define CNXK_NIX_RSS_L3_L4_SRC_DST                                             \
  57         (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY |     \
  58          ETH_RSS_L4_DST_ONLY)
  59
  60 #define CNXK_NIX_RSS_OFFLOAD                                                   \
  61         (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP |               \
  62          ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD |                  \
  63          CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN)
  64
  65 #define CNXK_NIX_TX_OFFLOAD_CAPA                                               \
  66         (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE |          \
  67          DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT |             \
  68          DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM |    \
  69          DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM |                 \
  70          DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO |                  \
  71          DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO |        \
  72          DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS |              \
  73          DEV_TX_OFFLOAD_IPV4_CKSUM)
  74
  75 #define CNXK_NIX_RX_OFFLOAD_CAPA                                               \
  76         (DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM |                 \
  77          DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER |            \
  78          DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |         \
  79          DEV_RX_OFFLOAD_RSS_HASH | DEV_RX_OFFLOAD_TIMESTAMP)
  80
  81 #define RSS_IPV4_ENABLE                                                        \
  82         (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_UDP |         \
  83          ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_SCTP)
  84
  85 #define RSS_IPV6_ENABLE                                                        \
  86         (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_UDP |         \
  87          ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_NONFRAG_IPV6_SCTP)
  88
  89 #define RSS_IPV6_EX_ENABLE                                                     \
  90         (ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | ETH_RSS_IPV6_UDP_EX)
  91
  92 #define RSS_MAX_LEVELS 3
  93
  94 #define RSS_IPV4_INDEX 0
  95 #define RSS_IPV6_INDEX 1
  96 #define RSS_TCP_INDEX  2
  97 #define RSS_UDP_INDEX  3
  98 #define RSS_SCTP_INDEX 4
  99 #define RSS_DMAC_INDEX 5
 100
 101 /* Default mark value used when none is provided. */
 102 #define CNXK_FLOW_ACTION_FLAG_DEFAULT 0xffff
 103
 104 /* Default cycle counter mask */
 105 #define CNXK_CYCLECOUNTER_MASK     0xffffffffffffffffULL
 106 #define CNXK_NIX_TIMESYNC_RX_OFFSET 8
 107
 108 #define PTYPE_NON_TUNNEL_WIDTH    16
 109 #define PTYPE_TUNNEL_WIDTH        12
 110 #define PTYPE_NON_TUNNEL_ARRAY_SZ BIT(PTYPE_NON_TUNNEL_WIDTH)
 111 #define PTYPE_TUNNEL_ARRAY_SZ     BIT(PTYPE_TUNNEL_WIDTH)
 112 #define PTYPE_ARRAY_SZ                                                         \
 113         ((PTYPE_NON_TUNNEL_ARRAY_SZ + PTYPE_TUNNEL_ARRAY_SZ) * sizeof(uint16_t))
 114 /* Fastpath lookup */
 115 #define CNXK_NIX_FASTPATH_LOOKUP_MEM "cnxk_nix_fastpath_lookup_mem"
 116
 117 #define CNXK_NIX_UDP_TUN_BITMASK                                               \
 118         ((1ull << (PKT_TX_TUNNEL_VXLAN >> 45)) |                               \
 119          (1ull << (PKT_TX_TUNNEL_GENEVE >> 45)))
 120
 121 struct cnxk_fc_cfg {
 122         enum rte_eth_fc_mode mode;
 123         uint8_t rx_pause;
 124         uint8_t tx_pause;
 125 };
 126
 127 struct cnxk_eth_qconf {
 128         union {
 129                 struct rte_eth_txconf tx;
 130                 struct rte_eth_rxconf rx;
 131         } conf;
 132         struct rte_mempool *mp;
 133         uint16_t nb_desc;
 134         uint8_t valid;
 135 };
 136
 137 struct cnxk_timesync_info {
 138         uint64_t rx_tstamp_dynflag;
 139         rte_iova_t tx_tstamp_iova;
 140         uint64_t *tx_tstamp;
 141         uint64_t rx_tstamp;
 142         int tstamp_dynfield_offset;
 143         uint8_t tx_ready;
 144         uint8_t rx_ready;
 145 } __plt_cache_aligned;
 146
 147 struct cnxk_eth_dev {
 148         /* ROC NIX */
 149         struct roc_nix nix;
 150
 151         /* ROC NPC */
 152         struct roc_npc npc;
 153
 154         /* ROC RQs, SQs and CQs */
 155         struct roc_nix_rq *rqs;
 156         struct roc_nix_sq *sqs;
 157         struct roc_nix_cq *cqs;
 158
 159         /* Configured queue count */
 160         uint16_t nb_rxq;
 161         uint16_t nb_txq;
 162         uint8_t configured;
 163
 164         /* Max macfilter entries */
 165         uint8_t max_mac_entries;
 166         bool dmac_filter_enable;
 167
 168         uint16_t flags;
 169         uint8_t ptype_disable;
 170         bool scalar_ena;
 171         bool ptp_en;
 172
 173         /* Pointer back to rte */
 174         struct rte_eth_dev *eth_dev;
 175
 176         /* HW capabilities / Limitations */
 177         union {
 178                 struct {
 179                         uint64_t cq_min_4k : 1;
 180                 };
 181                 uint64_t hwcap;
 182         };
 183
 184         /* Rx and Tx offload capabilities */
 185         uint64_t rx_offload_capa;
 186         uint64_t tx_offload_capa;
 187         uint32_t speed_capa;
 188         /* Configured Rx and Tx offloads */
 189         uint64_t rx_offloads;
 190         uint64_t tx_offloads;
 191         /* Platform specific offload flags */
 192         uint16_t rx_offload_flags;
 193         uint16_t tx_offload_flags;
 194
 195         /* ETHDEV RSS HF bitmask */
 196         uint64_t ethdev_rss_hf;
 197
 198         /* Saved qconf before lf realloc */
 199         struct cnxk_eth_qconf *tx_qconf;
 200         struct cnxk_eth_qconf *rx_qconf;
 201
 202         /* Flow control configuration */
 203         struct cnxk_fc_cfg fc_cfg;
 204
 205         /* PTP Counters */
 206         struct cnxk_timesync_info tstamp;
 207         struct rte_timecounter systime_tc;
 208         struct rte_timecounter rx_tstamp_tc;
 209         struct rte_timecounter tx_tstamp_tc;
 210         double clk_freq_mult;
 211         uint64_t clk_delta;
 212
 213         /* Rx burst for cleanup(Only Primary) */
 214         eth_rx_burst_t rx_pkt_burst_no_offload;
 215
 216         /* Default mac address */
 217         uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
 218
 219         /* LSO Tunnel format indices */
 220         uint64_t lso_tun_fmt;
 221
 222         /* Per queue statistics counters */
 223         uint32_t txq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
 224         uint32_t rxq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS];
 225 };
 226
 227 struct cnxk_eth_rxq_sp {
 228         struct cnxk_eth_dev *dev;
 229         struct cnxk_eth_qconf qconf;
 230         uint16_t qid;
 231 } __plt_cache_aligned;
 232
 233 struct cnxk_eth_txq_sp {
 234         struct cnxk_eth_dev *dev;
 235         struct cnxk_eth_qconf qconf;
 236         uint16_t qid;
 237 } __plt_cache_aligned;
 238
 239 static inline struct cnxk_eth_dev *
 240 cnxk_eth_pmd_priv(struct rte_eth_dev *eth_dev)
 241 {
 242         return eth_dev->data->dev_private;
 243 }
 244
 245 static inline struct cnxk_eth_rxq_sp *
 246 cnxk_eth_rxq_to_sp(void *__rxq)
 247 {
 248         return ((struct cnxk_eth_rxq_sp *)__rxq) - 1;
 249 }
 250
 251 static inline struct cnxk_eth_txq_sp *
 252 cnxk_eth_txq_to_sp(void *__txq)
 253 {
 254         return ((struct cnxk_eth_txq_sp *)__txq) - 1;
 255 }
 256
 257 /* Common ethdev ops */
 258 extern struct eth_dev_ops cnxk_eth_dev_ops;
 259
 260 /* Common flow ops */
 261 extern struct rte_flow_ops cnxk_flow_ops;
 262
 263 /* Ops */
 264 int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
 265                    struct rte_pci_device *pci_dev);
 266 int cnxk_nix_remove(struct rte_pci_device *pci_dev);
 267 int cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
 268 int cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
 269                           struct rte_ether_addr *addr, uint32_t index,
 270                           uint32_t pool);
 271 void cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
 272 int cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
 273                           struct rte_ether_addr *addr);
 274 int cnxk_nix_promisc_enable(struct rte_eth_dev *eth_dev);
 275 int cnxk_nix_promisc_disable(struct rte_eth_dev *eth_dev);
 276 int cnxk_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
 277 int cnxk_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
 278 int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,
 279                       struct rte_eth_dev_info *dev_info);
 280 int cnxk_nix_rx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
 281                                struct rte_eth_burst_mode *mode);
 282 int cnxk_nix_tx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
 283                                struct rte_eth_burst_mode *mode);
 284 int cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 285                            struct rte_eth_fc_conf *fc_conf);
 286 int cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 287                            struct rte_eth_fc_conf *fc_conf);
 288 int cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev);
 289 int cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev);
 290 int cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev,
 291                              struct rte_eth_dev_module_info *modinfo);
 292 int cnxk_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
 293                                struct rte_dev_eeprom_info *info);
 294 int cnxk_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
 295                                   uint16_t rx_queue_id);
 296 int cnxk_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
 297                                    uint16_t rx_queue_id);
 298 int cnxk_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool);
 299 int cnxk_nix_tx_done_cleanup(void *txq, uint32_t free_cnt);
 300 int cnxk_nix_flow_ops_get(struct rte_eth_dev *eth_dev,
 301                           const struct rte_flow_ops **ops);
 302 int cnxk_nix_configure(struct rte_eth_dev *eth_dev);
 303 int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 304                             uint16_t nb_desc, uint16_t fp_tx_q_sz,
 305                             const struct rte_eth_txconf *tx_conf);
 306 int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 307                             uint16_t nb_desc, uint16_t fp_rx_q_sz,
 308                             const struct rte_eth_rxconf *rx_conf,
 309                             struct rte_mempool *mp);
 310 int cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid);
 311 int cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid);
 312 int cnxk_nix_dev_start(struct rte_eth_dev *eth_dev);
 313 int cnxk_nix_timesync_enable(struct rte_eth_dev *eth_dev);
 314 int cnxk_nix_timesync_disable(struct rte_eth_dev *eth_dev);
 315 int cnxk_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,
 316                                         struct timespec *timestamp,
 317                                         uint32_t flags);
 318 int cnxk_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,
 319                                         struct timespec *timestamp);
 320 int cnxk_nix_tsc_convert(struct cnxk_eth_dev *dev);
 321
 322 uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev);
 323
 324 /* RSS */
 325 uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
 326                                 uint8_t rss_level);
 327
 328 /* Link */
 329 void cnxk_nix_toggle_flag_link_cfg(struct cnxk_eth_dev *dev, bool set);
 330 void cnxk_eth_dev_link_status_cb(struct roc_nix *nix,
 331                                  struct roc_nix_link_info *link);
 332 int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
 333 int cnxk_nix_queue_stats_mapping(struct rte_eth_dev *dev, uint16_t queue_id,
 334                                  uint8_t stat_idx, uint8_t is_rx);
 335 int cnxk_nix_stats_reset(struct rte_eth_dev *dev);
 336 int cnxk_nix_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 337 int cnxk_nix_xstats_get(struct rte_eth_dev *eth_dev,
 338                         struct rte_eth_xstat *xstats, unsigned int n);
 339 int cnxk_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
 340                               struct rte_eth_xstat_name *xstats_names,
 341                               unsigned int limit);
 342 int cnxk_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
 343                                     struct rte_eth_xstat_name *xstats_names,
 344                                     const uint64_t *ids, unsigned int limit);
 345 int cnxk_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids,
 346                               uint64_t *values, unsigned int n);
 347 int cnxk_nix_xstats_reset(struct rte_eth_dev *eth_dev);
 348 int cnxk_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
 349                             size_t fw_size);
 350 void cnxk_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
 351                            struct rte_eth_rxq_info *qinfo);
 352 void cnxk_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
 353                            struct rte_eth_txq_info *qinfo);
 354
 355 /* Lookup configuration */
 356 const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev);
 357 void *cnxk_nix_fastpath_lookup_mem_get(void);
 358
 359 /* Devargs */
 360 int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
 361                               struct cnxk_eth_dev *dev);
 362
 363 /* Debug */
 364 int cnxk_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
 365                          struct rte_dev_reg_info *regs);
 366
 367 /* Other private functions */
 368 int nix_recalc_mtu(struct rte_eth_dev *eth_dev);
 369
 370 /* Inlines */
 371 static __rte_always_inline uint64_t
 372 cnxk_pktmbuf_detach(struct rte_mbuf *m)
 373 {
 374         struct rte_mempool *mp = m->pool;
 375         uint32_t mbuf_size, buf_len;
 376         struct rte_mbuf *md;
 377         uint16_t priv_size;
 378         uint16_t refcount;
 379
 380         /* Update refcount of direct mbuf */
 381         md = rte_mbuf_from_indirect(m);
 382         refcount = rte_mbuf_refcnt_update(md, -1);
 383
 384         priv_size = rte_pktmbuf_priv_size(mp);
 385         mbuf_size = (uint32_t)(sizeof(struct rte_mbuf) + priv_size);
 386         buf_len = rte_pktmbuf_data_room_size(mp);
 387
 388         m->priv_size = priv_size;
 389         m->buf_addr = (char *)m + mbuf_size;
 390         m->buf_iova = rte_mempool_virt2iova(m) + mbuf_size;
 391         m->buf_len = (uint16_t)buf_len;
 392         rte_pktmbuf_reset_headroom(m);
 393         m->data_len = 0;
 394         m->ol_flags = 0;
 395         m->next = NULL;
 396         m->nb_segs = 1;
 397
 398         /* Now indirect mbuf is safe to free */
 399         rte_pktmbuf_free(m);
 400
 401         if (refcount == 0) {
 402                 rte_mbuf_refcnt_set(md, 1);
 403                 md->data_len = 0;
 404                 md->ol_flags = 0;
 405                 md->next = NULL;
 406                 md->nb_segs = 1;
 407                 return 0;
 408         } else {
 409                 return 1;
 410         }
 411 }
 412
 413 static __rte_always_inline uint64_t
 414 cnxk_nix_prefree_seg(struct rte_mbuf *m)
 415 {
 416         if (likely(rte_mbuf_refcnt_read(m) == 1)) {
 417                 if (!RTE_MBUF_DIRECT(m))
 418                         return cnxk_pktmbuf_detach(m);
 419
 420                 m->next = NULL;
 421                 m->nb_segs = 1;
 422                 return 0;
 423         } else if (rte_mbuf_refcnt_update(m, -1) == 0) {
 424                 if (!RTE_MBUF_DIRECT(m))
 425                         return cnxk_pktmbuf_detach(m);
 426
 427                 rte_mbuf_refcnt_set(m, 1);
 428                 m->next = NULL;
 429                 m->nb_segs = 1;
 430                 return 0;
 431         }
 432
 433         /* Mbuf is having refcount more than 1 so need not to be freed */
 434         return 1;
 435 }
 436
 437 static inline rte_mbuf_timestamp_t *
 438 cnxk_nix_timestamp_dynfield(struct rte_mbuf *mbuf,
 439                             struct cnxk_timesync_info *info)
 440 {
 441         return RTE_MBUF_DYNFIELD(mbuf, info->tstamp_dynfield_offset,
 442                                  rte_mbuf_timestamp_t *);
 443 }
 444
 445 static __rte_always_inline void
 446 cnxk_nix_mbuf_to_tstamp(struct rte_mbuf *mbuf,
 447                         struct cnxk_timesync_info *tstamp, bool ts_enable,
 448                         uint64_t *tstamp_ptr)
 449 {
 450         if (ts_enable &&
 451             (mbuf->data_off ==
 452              RTE_PKTMBUF_HEADROOM + CNXK_NIX_TIMESYNC_RX_OFFSET)) {
 453                 mbuf->pkt_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;
 454
 455                 /* Reading the rx timestamp inserted by CGX, viz at
 456                  * starting of the packet data.
 457                  */
 458                 *cnxk_nix_timestamp_dynfield(mbuf, tstamp) =
 459                         rte_be_to_cpu_64(*tstamp_ptr);
 460                 /* PKT_RX_IEEE1588_TMST flag needs to be set only in case
 461                  * PTP packets are received.
 462                  */
 463                 if (mbuf->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC) {
 464                         tstamp->rx_tstamp =
 465                                 *cnxk_nix_timestamp_dynfield(mbuf, tstamp);
 466                         tstamp->rx_ready = 1;
 467                         mbuf->ol_flags |= PKT_RX_IEEE1588_PTP |
 468                                           PKT_RX_IEEE1588_TMST |
 469                                           tstamp->rx_tstamp_dynflag;
 470                 }
 471         }
 472 }
 473
 474 #endif /* __CNXK_ETHDEV_H__ */