1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #ifndef __CNXK_ETHDEV_H__
5 #define __CNXK_ETHDEV_H__
10 #include <ethdev_driver.h>
11 #include <ethdev_pci.h>
12 #include <rte_kvargs.h>
14 #include <rte_mbuf_pool_ops.h>
15 #include <rte_mempool.h>
19 #define CNXK_ETH_DEV_PMD_VERSION "1.0"
21 /* Used for struct cnxk_eth_dev::flags */
22 #define CNXK_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
24 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
25 * In Tx space is always reserved for this in FRS.
27 #define CNXK_NIX_MAX_VTAG_INS 2
28 #define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS)
30 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
31 #define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
33 #define CNXK_NIX_RX_MIN_DESC 16
34 #define CNXK_NIX_RX_MIN_DESC_ALIGN 16
35 #define CNXK_NIX_RX_NB_SEG_MAX 6
36 #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
37 /* Max supported SQB count */
38 #define CNXK_NIX_TX_MAX_SQB 512
40 /* If PTP is enabled additional SEND MEM DESC is required which
41 * takes 2 words, hence max 7 iova address are possible
43 #if defined(RTE_LIBRTE_IEEE1588)
44 #define CNXK_NIX_TX_NB_SEG_MAX 7
46 #define CNXK_NIX_TX_NB_SEG_MAX 9
49 #define CNXK_NIX_RSS_L3_L4_SRC_DST \
50 (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY | \
53 #define CNXK_NIX_RSS_OFFLOAD \
54 (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP | \
55 ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \
56 CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN)
58 #define CNXK_NIX_TX_OFFLOAD_CAPA \
59 (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE | \
60 DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT | \
61 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
62 DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM | \
63 DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO | \
64 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
65 DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS | \
66 DEV_TX_OFFLOAD_IPV4_CKSUM)
68 #define CNXK_NIX_RX_OFFLOAD_CAPA \
69 (DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM | \
70 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER | \
71 DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
72 DEV_RX_OFFLOAD_RSS_HASH)
74 #define RSS_IPV4_ENABLE \
75 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_UDP | \
76 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_SCTP)
78 #define RSS_IPV6_ENABLE \
79 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_UDP | \
80 ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_NONFRAG_IPV6_SCTP)
82 #define RSS_IPV6_EX_ENABLE \
83 (ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | ETH_RSS_IPV6_UDP_EX)
85 #define RSS_MAX_LEVELS 3
87 #define RSS_IPV4_INDEX 0
88 #define RSS_IPV6_INDEX 1
89 #define RSS_TCP_INDEX 2
90 #define RSS_UDP_INDEX 3
91 #define RSS_SCTP_INDEX 4
92 #define RSS_DMAC_INDEX 5
94 struct cnxk_eth_qconf {
96 struct rte_eth_txconf tx;
97 struct rte_eth_rxconf rx;
99 struct rte_mempool *mp;
104 struct cnxk_eth_dev {
108 /* ROC RQs, SQs and CQs */
109 struct roc_nix_rq *rqs;
110 struct roc_nix_sq *sqs;
111 struct roc_nix_cq *cqs;
113 /* Configured queue count */
118 /* Max macfilter entries */
119 uint8_t max_mac_entries;
124 /* Pointer back to rte */
125 struct rte_eth_dev *eth_dev;
127 /* HW capabilities / Limitations */
130 uint64_t cq_min_4k : 1;
135 /* Rx and Tx offload capabilities */
136 uint64_t rx_offload_capa;
137 uint64_t tx_offload_capa;
139 /* Configured Rx and Tx offloads */
140 uint64_t rx_offloads;
141 uint64_t tx_offloads;
142 /* Platform specific offload flags */
143 uint16_t rx_offload_flags;
144 uint16_t tx_offload_flags;
146 /* ETHDEV RSS HF bitmask */
147 uint64_t ethdev_rss_hf;
149 /* Saved qconf before lf realloc */
150 struct cnxk_eth_qconf *tx_qconf;
151 struct cnxk_eth_qconf *rx_qconf;
153 /* Default mac address */
154 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
156 /* LSO Tunnel format indices */
157 uint64_t lso_tun_fmt;
160 struct cnxk_eth_rxq_sp {
161 struct cnxk_eth_dev *dev;
162 struct cnxk_eth_qconf qconf;
164 } __plt_cache_aligned;
166 struct cnxk_eth_txq_sp {
167 struct cnxk_eth_dev *dev;
168 struct cnxk_eth_qconf qconf;
170 } __plt_cache_aligned;
172 static inline struct cnxk_eth_dev *
173 cnxk_eth_pmd_priv(struct rte_eth_dev *eth_dev)
175 return eth_dev->data->dev_private;
178 static inline struct cnxk_eth_rxq_sp *
179 cnxk_eth_rxq_to_sp(void *__rxq)
181 return ((struct cnxk_eth_rxq_sp *)__rxq) - 1;
184 static inline struct cnxk_eth_txq_sp *
185 cnxk_eth_txq_to_sp(void *__txq)
187 return ((struct cnxk_eth_txq_sp *)__txq) - 1;
190 /* Common ethdev ops */
191 extern struct eth_dev_ops cnxk_eth_dev_ops;
194 int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
195 struct rte_pci_device *pci_dev);
196 int cnxk_nix_remove(struct rte_pci_device *pci_dev);
197 int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,
198 struct rte_eth_dev_info *dev_info);
199 int cnxk_nix_configure(struct rte_eth_dev *eth_dev);
200 int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
201 uint16_t nb_desc, uint16_t fp_tx_q_sz,
202 const struct rte_eth_txconf *tx_conf);
203 int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
204 uint16_t nb_desc, uint16_t fp_rx_q_sz,
205 const struct rte_eth_rxconf *rx_conf,
206 struct rte_mempool *mp);
208 uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev);
211 uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
215 void cnxk_eth_dev_link_status_cb(struct roc_nix *nix,
216 struct roc_nix_link_info *link);
217 int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
220 int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
221 struct cnxk_eth_dev *dev);
223 #endif /* __CNXK_ETHDEV_H__ */