drivers/net/cnxk/cnxk_ethdev_ops.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #include <cnxk_ethdev.h>
   6
   7 int
   8 cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)
   9 {
  10         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
  11         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
  12         int max_rx_pktlen;
  13
  14         max_rx_pktlen = (roc_nix_max_pkt_len(&dev->nix) + RTE_ETHER_CRC_LEN -
  15                          CNXK_NIX_MAX_VTAG_ACT_SIZE);
  16
  17         devinfo->min_rx_bufsize = NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN;
  18         devinfo->max_rx_pktlen = max_rx_pktlen;
  19         devinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT;
  20         devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT;
  21         devinfo->max_mac_addrs = dev->max_mac_entries;
  22         devinfo->max_vfs = pci_dev->max_vfs;
  23         devinfo->max_mtu = devinfo->max_rx_pktlen -
  24                                 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN);
  25         devinfo->min_mtu = devinfo->min_rx_bufsize - CNXK_NIX_L2_OVERHEAD;
  26
  27         devinfo->rx_offload_capa = dev->rx_offload_capa;
  28         devinfo->tx_offload_capa = dev->tx_offload_capa;
  29         devinfo->rx_queue_offload_capa = 0;
  30         devinfo->tx_queue_offload_capa = 0;
  31
  32         devinfo->reta_size = dev->nix.reta_sz;
  33         devinfo->hash_key_size = ROC_NIX_RSS_KEY_LEN;
  34         devinfo->flow_type_rss_offloads = CNXK_NIX_RSS_OFFLOAD;
  35
  36         devinfo->default_rxconf = (struct rte_eth_rxconf){
  37                 .rx_drop_en = 0,
  38                 .offloads = 0,
  39         };
  40
  41         devinfo->default_txconf = (struct rte_eth_txconf){
  42                 .offloads = 0,
  43         };
  44
  45         devinfo->default_rxportconf = (struct rte_eth_dev_portconf){
  46                 .ring_size = CNXK_NIX_RX_DEFAULT_RING_SZ,
  47         };
  48
  49         devinfo->rx_desc_lim = (struct rte_eth_desc_lim){
  50                 .nb_max = UINT16_MAX,
  51                 .nb_min = CNXK_NIX_RX_MIN_DESC,
  52                 .nb_align = CNXK_NIX_RX_MIN_DESC_ALIGN,
  53                 .nb_seg_max = CNXK_NIX_RX_NB_SEG_MAX,
  54                 .nb_mtu_seg_max = CNXK_NIX_RX_NB_SEG_MAX,
  55         };
  56         devinfo->rx_desc_lim.nb_max =
  57                 RTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max,
  58                                     CNXK_NIX_RX_MIN_DESC_ALIGN);
  59
  60         devinfo->tx_desc_lim = (struct rte_eth_desc_lim){
  61                 .nb_max = UINT16_MAX,
  62                 .nb_min = 1,
  63                 .nb_align = 1,
  64                 .nb_seg_max = CNXK_NIX_TX_NB_SEG_MAX,
  65                 .nb_mtu_seg_max = CNXK_NIX_TX_NB_SEG_MAX,
  66         };
  67
  68         devinfo->speed_capa = dev->speed_capa;
  69         devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
  70                             RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
  71         return 0;
  72 }
  73
  74 int
  75 cnxk_nix_rx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
  76                            struct rte_eth_burst_mode *mode)
  77 {
  78         ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc;
  79         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
  80         const struct burst_info {
  81                 uint64_t flags;
  82                 const char *output;
  83         } rx_offload_map[] = {
  84                 {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN Strip,"},
  85                 {DEV_RX_OFFLOAD_IPV4_CKSUM, " Inner IPv4 Checksum,"},
  86                 {DEV_RX_OFFLOAD_UDP_CKSUM, " UDP Checksum,"},
  87                 {DEV_RX_OFFLOAD_TCP_CKSUM, " TCP Checksum,"},
  88                 {DEV_RX_OFFLOAD_TCP_LRO, " TCP LRO,"},
  89                 {DEV_RX_OFFLOAD_QINQ_STRIP, " QinQ VLAN Strip,"},
  90                 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPv4 Checksum,"},
  91                 {DEV_RX_OFFLOAD_MACSEC_STRIP, " MACsec Strip,"},
  92                 {DEV_RX_OFFLOAD_HEADER_SPLIT, " Header Split,"},
  93                 {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN Filter,"},
  94                 {DEV_RX_OFFLOAD_VLAN_EXTEND, " VLAN Extend,"},
  95                 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo Frame,"},
  96                 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"},
  97                 {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
  98                 {DEV_RX_OFFLOAD_SECURITY, " Security,"},
  99                 {DEV_RX_OFFLOAD_KEEP_CRC, " Keep CRC,"},
 100                 {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP,"},
 101                 {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP Checksum,"},
 102                 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"}
 103         };
 104         static const char *const burst_mode[] = {"Vector Neon, Rx Offloads:",
 105                                                  "Scalar, Rx Offloads:"
 106         };
 107         uint32_t i;
 108
 109         PLT_SET_USED(queue_id);
 110
 111         /* Update burst mode info */
 112         rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena],
 113                          str_size - bytes);
 114         if (rc < 0)
 115                 goto done;
 116
 117         bytes += rc;
 118
 119         /* Update Rx offload info */
 120         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 121                 if (dev->rx_offloads & rx_offload_map[i].flags) {
 122                         rc = rte_strscpy(mode->info + bytes,
 123                                          rx_offload_map[i].output,
 124                                          str_size - bytes);
 125                         if (rc < 0)
 126                                 goto done;
 127
 128                         bytes += rc;
 129                 }
 130         }
 131
 132 done:
 133         return 0;
 134 }
 135
 136 int
 137 cnxk_nix_tx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
 138                            struct rte_eth_burst_mode *mode)
 139 {
 140         ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc;
 141         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 142         const struct burst_info {
 143                 uint64_t flags;
 144                 const char *output;
 145         } tx_offload_map[] = {
 146                 {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
 147                 {DEV_TX_OFFLOAD_IPV4_CKSUM, " Inner IPv4 Checksum,"},
 148                 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP Checksum,"},
 149                 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP Checksum,"},
 150                 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP Checksum,"},
 151                 {DEV_TX_OFFLOAD_TCP_TSO, " TCP TSO,"},
 152                 {DEV_TX_OFFLOAD_UDP_TSO, " UDP TSO,"},
 153                 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPv4 Checksum,"},
 154                 {DEV_TX_OFFLOAD_QINQ_INSERT, " QinQ VLAN Insert,"},
 155                 {DEV_TX_OFFLOAD_VXLAN_TNL_TSO, " VXLAN Tunnel TSO,"},
 156                 {DEV_TX_OFFLOAD_GRE_TNL_TSO, " GRE Tunnel TSO,"},
 157                 {DEV_TX_OFFLOAD_IPIP_TNL_TSO, " IP-in-IP Tunnel TSO,"},
 158                 {DEV_TX_OFFLOAD_GENEVE_TNL_TSO, " Geneve Tunnel TSO,"},
 159                 {DEV_TX_OFFLOAD_MACSEC_INSERT, " MACsec Insert,"},
 160                 {DEV_TX_OFFLOAD_MT_LOCKFREE, " Multi Thread Lockless Tx,"},
 161                 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"},
 162                 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " H/W MBUF Free,"},
 163                 {DEV_TX_OFFLOAD_SECURITY, " Security,"},
 164                 {DEV_TX_OFFLOAD_UDP_TNL_TSO, " UDP Tunnel TSO,"},
 165                 {DEV_TX_OFFLOAD_IP_TNL_TSO, " IP Tunnel TSO,"},
 166                 {DEV_TX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP Checksum,"},
 167                 {DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP, " Timestamp,"}
 168         };
 169         static const char *const burst_mode[] = {"Vector Neon, Tx Offloads:",
 170                                                  "Scalar, Tx Offloads:"
 171         };
 172         uint32_t i;
 173
 174         PLT_SET_USED(queue_id);
 175
 176         /* Update burst mode info */
 177         rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena],
 178                          str_size - bytes);
 179         if (rc < 0)
 180                 goto done;
 181
 182         bytes += rc;
 183
 184         /* Update Tx offload info */
 185         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 186                 if (dev->tx_offloads & tx_offload_map[i].flags) {
 187                         rc = rte_strscpy(mode->info + bytes,
 188                                          tx_offload_map[i].output,
 189                                          str_size - bytes);
 190                         if (rc < 0)
 191                                 goto done;
 192
 193                         bytes += rc;
 194                 }
 195         }
 196
 197 done:
 198         return 0;
 199 }
 200
 201 int
 202 cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 203                        struct rte_eth_fc_conf *fc_conf)
 204 {
 205         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 206         enum rte_eth_fc_mode mode_map[] = {
 207                                            RTE_FC_NONE, RTE_FC_RX_PAUSE,
 208                                            RTE_FC_TX_PAUSE, RTE_FC_FULL
 209                                           };
 210         struct roc_nix *nix = &dev->nix;
 211         int mode;
 212
 213         mode = roc_nix_fc_mode_get(nix);
 214         if (mode < 0)
 215                 return mode;
 216
 217         memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
 218         fc_conf->mode = mode_map[mode];
 219         return 0;
 220 }
 221
 222 static int
 223 nix_fc_cq_config_set(struct cnxk_eth_dev *dev, uint16_t qid, bool enable)
 224 {
 225         struct roc_nix *nix = &dev->nix;
 226         struct roc_nix_fc_cfg fc_cfg;
 227         struct roc_nix_cq *cq;
 228
 229         memset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));
 230         cq = &dev->cqs[qid];
 231         fc_cfg.cq_cfg_valid = true;
 232         fc_cfg.cq_cfg.enable = enable;
 233         fc_cfg.cq_cfg.rq = qid;
 234         fc_cfg.cq_cfg.cq_drop = cq->drop_thresh;
 235
 236         return roc_nix_fc_config_set(nix, &fc_cfg);
 237 }
 238
 239 int
 240 cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 241                        struct rte_eth_fc_conf *fc_conf)
 242 {
 243         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 244         enum roc_nix_fc_mode mode_map[] = {
 245                                            ROC_NIX_FC_NONE, ROC_NIX_FC_RX,
 246                                            ROC_NIX_FC_TX, ROC_NIX_FC_FULL
 247                                           };
 248         struct rte_eth_dev_data *data = eth_dev->data;
 249         struct cnxk_fc_cfg *fc = &dev->fc_cfg;
 250         struct roc_nix *nix = &dev->nix;
 251         uint8_t rx_pause, tx_pause;
 252         int rc, i;
 253
 254         if (roc_nix_is_vf_or_sdp(nix)) {
 255                 plt_err("Flow control configuration is not allowed on VFs");
 256                 return -ENOTSUP;
 257         }
 258
 259         if (fc_conf->high_water || fc_conf->low_water || fc_conf->pause_time ||
 260             fc_conf->mac_ctrl_frame_fwd || fc_conf->autoneg) {
 261                 plt_info("Only MODE configuration is supported");
 262                 return -EINVAL;
 263         }
 264
 265         if (fc_conf->mode == fc->mode)
 266                 return 0;
 267
 268         rx_pause = (fc_conf->mode == RTE_FC_FULL) ||
 269                     (fc_conf->mode == RTE_FC_RX_PAUSE);
 270         tx_pause = (fc_conf->mode == RTE_FC_FULL) ||
 271                     (fc_conf->mode == RTE_FC_TX_PAUSE);
 272
 273         /* Check if TX pause frame is already enabled or not */
 274         if (fc->tx_pause ^ tx_pause) {
 275                 if (roc_model_is_cn96_ax() && data->dev_started) {
 276                         /* On Ax, CQ should be in disabled state
 277                          * while setting flow control configuration.
 278                          */
 279                         plt_info("Stop the port=%d for setting flow control",
 280                                  data->port_id);
 281                         return 0;
 282                 }
 283
 284                 for (i = 0; i < data->nb_rx_queues; i++) {
 285                         rc = nix_fc_cq_config_set(dev, i, tx_pause);
 286                         if (rc)
 287                                 return rc;
 288                 }
 289         }
 290
 291         rc = roc_nix_fc_mode_set(nix, mode_map[fc_conf->mode]);
 292         if (rc)
 293                 return rc;
 294
 295         fc->rx_pause = rx_pause;
 296         fc->tx_pause = tx_pause;
 297         fc->mode = fc_conf->mode;
 298
 299         return rc;
 300 }
 301
 302 int
 303 cnxk_nix_flow_ops_get(struct rte_eth_dev *eth_dev,
 304                       const struct rte_flow_ops **ops)
 305 {
 306         RTE_SET_USED(eth_dev);
 307
 308         *ops = &cnxk_flow_ops;
 309         return 0;
 310 }
 311
 312 int
 313 cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr)
 314 {
 315         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 316         struct roc_nix *nix = &dev->nix;
 317         int rc;
 318
 319         /* Update mac address at NPC */
 320         rc = roc_nix_npc_mac_addr_set(nix, addr->addr_bytes);
 321         if (rc)
 322                 goto exit;
 323
 324         /* Update mac address at CGX for PFs only */
 325         if (!roc_nix_is_vf_or_sdp(nix)) {
 326                 rc = roc_nix_mac_addr_set(nix, addr->addr_bytes);
 327                 if (rc) {
 328                         /* Rollback to previous mac address */
 329                         roc_nix_npc_mac_addr_set(nix, dev->mac_addr);
 330                         goto exit;
 331                 }
 332         }
 333
 334         /* Update mac address to cnxk ethernet device */
 335         rte_memcpy(dev->mac_addr, addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 336
 337 exit:
 338         return rc;
 339 }
 340
 341 int
 342 cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr,
 343                       uint32_t index, uint32_t pool)
 344 {
 345         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 346         struct roc_nix *nix = &dev->nix;
 347         int rc;
 348
 349         PLT_SET_USED(index);
 350         PLT_SET_USED(pool);
 351
 352         rc = roc_nix_mac_addr_add(nix, addr->addr_bytes);
 353         if (rc < 0) {
 354                 plt_err("Failed to add mac address, rc=%d", rc);
 355                 return rc;
 356         }
 357
 358         /* Enable promiscuous mode at NIX level */
 359         roc_nix_npc_promisc_ena_dis(nix, true);
 360         dev->dmac_filter_enable = true;
 361         eth_dev->data->promiscuous = false;
 362         dev->dmac_filter_count++;
 363
 364         return 0;
 365 }
 366
 367 void
 368 cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index)
 369 {
 370         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 371         struct roc_nix *nix = &dev->nix;
 372         int rc;
 373
 374         rc = roc_nix_mac_addr_del(nix, index);
 375         if (rc)
 376                 plt_err("Failed to delete mac address, rc=%d", rc);
 377
 378         dev->dmac_filter_count--;
 379 }
 380
 381 int
 382 cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
 383 {
 384         uint32_t old_frame_size, frame_size = mtu + CNXK_NIX_L2_OVERHEAD;
 385         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 386         struct rte_eth_dev_data *data = eth_dev->data;
 387         struct roc_nix *nix = &dev->nix;
 388         int rc = -EINVAL;
 389         uint32_t buffsz;
 390
 391         frame_size += CNXK_NIX_TIMESYNC_RX_OFFSET * dev->ptp_en;
 392
 393         /* Check if MTU is within the allowed range */
 394         if ((frame_size - RTE_ETHER_CRC_LEN) < NIX_MIN_HW_FRS) {
 395                 plt_err("MTU is lesser than minimum");
 396                 goto exit;
 397         }
 398
 399         if ((frame_size - RTE_ETHER_CRC_LEN) >
 400             ((uint32_t)roc_nix_max_pkt_len(nix))) {
 401                 plt_err("MTU is greater than maximum");
 402                 goto exit;
 403         }
 404
 405         buffsz = data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 406         old_frame_size = data->mtu + CNXK_NIX_L2_OVERHEAD;
 407
 408         /* Refuse MTU that requires the support of scattered packets
 409          * when this feature has not been enabled before.
 410          */
 411         if (data->dev_started && frame_size > buffsz &&
 412             !(dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)) {
 413                 plt_err("Scatter offload is not enabled for mtu");
 414                 goto exit;
 415         }
 416
 417         /* Check <seg size> * <max_seg>  >= max_frame */
 418         if ((dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER) &&
 419             frame_size > (buffsz * CNXK_NIX_RX_NB_SEG_MAX)) {
 420                 plt_err("Greater than maximum supported packet length");
 421                 goto exit;
 422         }
 423
 424         frame_size -= RTE_ETHER_CRC_LEN;
 425
 426         /* Update mtu on Tx */
 427         rc = roc_nix_mac_mtu_set(nix, frame_size);
 428         if (rc) {
 429                 plt_err("Failed to set MTU, rc=%d", rc);
 430                 goto exit;
 431         }
 432
 433         /* Sync same frame size on Rx */
 434         rc = roc_nix_mac_max_rx_len_set(nix, frame_size);
 435         if (rc) {
 436                 /* Rollback to older mtu */
 437                 roc_nix_mac_mtu_set(nix,
 438                                     old_frame_size - RTE_ETHER_CRC_LEN);
 439                 plt_err("Failed to max Rx frame length, rc=%d", rc);
 440                 goto exit;
 441         }
 442
 443         if (mtu > RTE_ETHER_MTU)
 444                 dev->rx_offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
 445         else
 446                 dev->rx_offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 447 exit:
 448         return rc;
 449 }
 450
 451 int
 452 cnxk_nix_promisc_enable(struct rte_eth_dev *eth_dev)
 453 {
 454         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 455         struct roc_nix *nix = &dev->nix;
 456         int rc = 0;
 457
 458         if (roc_nix_is_vf_or_sdp(nix))
 459                 return rc;
 460
 461         rc = roc_nix_npc_promisc_ena_dis(nix, true);
 462         if (rc) {
 463                 plt_err("Failed to setup promisc mode in npc, rc=%d(%s)", rc,
 464                         roc_error_msg_get(rc));
 465                 return rc;
 466         }
 467
 468         rc = roc_nix_mac_promisc_mode_enable(nix, true);
 469         if (rc) {
 470                 plt_err("Failed to setup promisc mode in mac, rc=%d(%s)", rc,
 471                         roc_error_msg_get(rc));
 472                 roc_nix_npc_promisc_ena_dis(nix, false);
 473                 return rc;
 474         }
 475
 476         return 0;
 477 }
 478
 479 int
 480 cnxk_nix_promisc_disable(struct rte_eth_dev *eth_dev)
 481 {
 482         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 483         struct roc_nix *nix = &dev->nix;
 484         int rc = 0;
 485
 486         if (roc_nix_is_vf_or_sdp(nix))
 487                 return rc;
 488
 489         rc = roc_nix_npc_promisc_ena_dis(nix, dev->dmac_filter_enable);
 490         if (rc) {
 491                 plt_err("Failed to setup promisc mode in npc, rc=%d(%s)", rc,
 492                         roc_error_msg_get(rc));
 493                 return rc;
 494         }
 495
 496         rc = roc_nix_mac_promisc_mode_enable(nix, false);
 497         if (rc) {
 498                 plt_err("Failed to setup promisc mode in mac, rc=%d(%s)", rc,
 499                         roc_error_msg_get(rc));
 500                 roc_nix_npc_promisc_ena_dis(nix, !dev->dmac_filter_enable);
 501                 return rc;
 502         }
 503
 504         dev->dmac_filter_enable = false;
 505         return 0;
 506 }
 507
 508 int
 509 cnxk_nix_allmulticast_enable(struct rte_eth_dev *eth_dev)
 510 {
 511         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 512
 513         return roc_nix_npc_mcast_config(&dev->nix, true, false);
 514 }
 515
 516 int
 517 cnxk_nix_allmulticast_disable(struct rte_eth_dev *eth_dev)
 518 {
 519         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 520
 521         return roc_nix_npc_mcast_config(&dev->nix, false,
 522                                         eth_dev->data->promiscuous);
 523 }
 524
 525 int
 526 cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev)
 527 {
 528         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 529         struct roc_nix *nix = &dev->nix;
 530         int rc, i;
 531
 532         if (roc_nix_is_vf_or_sdp(nix))
 533                 return -ENOTSUP;
 534
 535         rc = roc_nix_mac_link_state_set(nix, true);
 536         if (rc)
 537                 goto exit;
 538
 539         /* Start tx queues  */
 540         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
 541                 rc = cnxk_nix_tx_queue_start(eth_dev, i);
 542                 if (rc)
 543                         goto exit;
 544         }
 545
 546 exit:
 547         return rc;
 548 }
 549
 550 int
 551 cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev)
 552 {
 553         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 554         struct roc_nix *nix = &dev->nix;
 555         int rc, i;
 556
 557         if (roc_nix_is_vf_or_sdp(nix))
 558                 return -ENOTSUP;
 559
 560         /* Stop tx queues  */
 561         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
 562                 rc = cnxk_nix_tx_queue_stop(eth_dev, i);
 563                 if (rc)
 564                         goto exit;
 565         }
 566
 567         rc = roc_nix_mac_link_state_set(nix, false);
 568 exit:
 569         return rc;
 570 }
 571
 572 int
 573 cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev,
 574                          struct rte_eth_dev_module_info *modinfo)
 575 {
 576         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 577         struct roc_nix_eeprom_info eeprom_info = {0};
 578         struct roc_nix *nix = &dev->nix;
 579         int rc;
 580
 581         rc = roc_nix_eeprom_info_get(nix, &eeprom_info);
 582         if (rc)
 583                 return rc;
 584
 585         modinfo->type = eeprom_info.sff_id;
 586         modinfo->eeprom_len = ROC_NIX_EEPROM_SIZE;
 587         return 0;
 588 }
 589
 590 int
 591 cnxk_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
 592                            struct rte_dev_eeprom_info *info)
 593 {
 594         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 595         struct roc_nix_eeprom_info eeprom_info = {0};
 596         struct roc_nix *nix = &dev->nix;
 597         int rc = -EINVAL;
 598
 599         if (!info->data || !info->length ||
 600             (info->offset + info->length > ROC_NIX_EEPROM_SIZE))
 601                 return rc;
 602
 603         rc = roc_nix_eeprom_info_get(nix, &eeprom_info);
 604         if (rc)
 605                 return rc;
 606
 607         rte_memcpy(info->data, eeprom_info.buf + info->offset, info->length);
 608         return 0;
 609 }
 610
 611 int
 612 cnxk_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 613 {
 614         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 615
 616         roc_nix_rx_queue_intr_enable(&dev->nix, rx_queue_id);
 617         return 0;
 618 }
 619
 620 int
 621 cnxk_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
 622                                uint16_t rx_queue_id)
 623 {
 624         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 625
 626         roc_nix_rx_queue_intr_disable(&dev->nix, rx_queue_id);
 627         return 0;
 628 }
 629
 630 int
 631 cnxk_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool)
 632 {
 633         RTE_SET_USED(eth_dev);
 634
 635         if (!strcmp(pool, rte_mbuf_platform_mempool_ops()))
 636                 return 0;
 637
 638         return -ENOTSUP;
 639 }
 640
 641 int
 642 cnxk_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
 643                         size_t fw_size)
 644 {
 645         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 646         const char *str = roc_npc_profile_name_get(&dev->npc);
 647         uint32_t size = strlen(str) + 1;
 648
 649         if (fw_size > size)
 650                 fw_size = size;
 651
 652         rte_strlcpy(fw_version, str, fw_size);
 653
 654         if (fw_size < size)
 655                 return size;
 656
 657         return 0;
 658 }
 659
 660 void
 661 cnxk_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
 662                       struct rte_eth_rxq_info *qinfo)
 663 {
 664         void *rxq = eth_dev->data->rx_queues[qid];
 665         struct cnxk_eth_rxq_sp *rxq_sp = cnxk_eth_rxq_to_sp(rxq);
 666
 667         memset(qinfo, 0, sizeof(*qinfo));
 668
 669         qinfo->mp = rxq_sp->qconf.mp;
 670         qinfo->scattered_rx = eth_dev->data->scattered_rx;
 671         qinfo->nb_desc = rxq_sp->qconf.nb_desc;
 672
 673         memcpy(&qinfo->conf, &rxq_sp->qconf.conf.rx, sizeof(qinfo->conf));
 674 }
 675
 676 void
 677 cnxk_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
 678                       struct rte_eth_txq_info *qinfo)
 679 {
 680         void *txq = eth_dev->data->tx_queues[qid];
 681         struct cnxk_eth_txq_sp *txq_sp = cnxk_eth_txq_to_sp(txq);
 682
 683         memset(qinfo, 0, sizeof(*qinfo));
 684
 685         qinfo->nb_desc = txq_sp->qconf.nb_desc;
 686
 687         memcpy(&qinfo->conf, &txq_sp->qconf.conf.tx, sizeof(qinfo->conf));
 688 }
 689
 690 /* It is a NOP for cnxk as HW frees the buffer on xmit */
 691 int
 692 cnxk_nix_tx_done_cleanup(void *txq, uint32_t free_cnt)
 693 {
 694         RTE_SET_USED(txq);
 695         RTE_SET_USED(free_cnt);
 696
 697         return 0;
 698 }
 699
 700 int
 701 cnxk_nix_dev_get_reg(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)
 702 {
 703         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 704         struct roc_nix *nix = &dev->nix;
 705         uint64_t *data = regs->data;
 706         int rc = -ENOTSUP;
 707
 708         if (data == NULL) {
 709                 rc = roc_nix_lf_get_reg_count(nix);
 710                 if (rc > 0) {
 711                         regs->length = rc;
 712                         regs->width = 8;
 713                         rc = 0;
 714                 }
 715                 return rc;
 716         }
 717
 718         if (!regs->length ||
 719             regs->length == (uint32_t)roc_nix_lf_get_reg_count(nix))
 720                 return roc_nix_lf_reg_dump(nix, data);
 721
 722         return rc;
 723 }
 724
 725 int
 726 cnxk_nix_reta_update(struct rte_eth_dev *eth_dev,
 727                      struct rte_eth_rss_reta_entry64 *reta_conf,
 728                      uint16_t reta_size)
 729 {
 730         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 731         uint16_t reta[ROC_NIX_RSS_RETA_MAX];
 732         struct roc_nix *nix = &dev->nix;
 733         int i, j, rc = -EINVAL, idx = 0;
 734
 735         if (reta_size != dev->nix.reta_sz) {
 736                 plt_err("Size of hash lookup table configured (%d) does not "
 737                         "match the number hardware can supported (%d)",
 738                         reta_size, dev->nix.reta_sz);
 739                 goto fail;
 740         }
 741
 742         /* Copy RETA table */
 743         for (i = 0; i < (int)(dev->nix.reta_sz / RTE_RETA_GROUP_SIZE); i++) {
 744                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) {
 745                         if ((reta_conf[i].mask >> j) & 0x01)
 746                                 reta[idx] = reta_conf[i].reta[j];
 747                         idx++;
 748                 }
 749         }
 750
 751         return roc_nix_rss_reta_set(nix, 0, reta);
 752
 753 fail:
 754         return rc;
 755 }
 756
 757 int
 758 cnxk_nix_reta_query(struct rte_eth_dev *eth_dev,
 759                     struct rte_eth_rss_reta_entry64 *reta_conf,
 760                     uint16_t reta_size)
 761 {
 762         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 763         uint16_t reta[ROC_NIX_RSS_RETA_MAX];
 764         struct roc_nix *nix = &dev->nix;
 765         int rc = -EINVAL, i, j, idx = 0;
 766
 767         if (reta_size != dev->nix.reta_sz) {
 768                 plt_err("Size of hash lookup table configured (%d) does not "
 769                         "match the number hardware can supported (%d)",
 770                         reta_size, dev->nix.reta_sz);
 771                 goto fail;
 772         }
 773
 774         rc = roc_nix_rss_reta_get(nix, 0, reta);
 775         if (rc)
 776                 goto fail;
 777
 778         /* Copy RETA table */
 779         for (i = 0; i < (int)(dev->nix.reta_sz / RTE_RETA_GROUP_SIZE); i++) {
 780                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) {
 781                         if ((reta_conf[i].mask >> j) & 0x01)
 782                                 reta_conf[i].reta[j] = reta[idx];
 783                         idx++;
 784                 }
 785         }
 786
 787         return 0;
 788
 789 fail:
 790         return rc;
 791 }
 792
 793 int
 794 cnxk_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
 795                          struct rte_eth_rss_conf *rss_conf)
 796 {
 797         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 798         struct roc_nix *nix = &dev->nix;
 799         uint8_t rss_hash_level;
 800         uint32_t flowkey_cfg;
 801         int rc = -EINVAL;
 802         uint8_t alg_idx;
 803
 804         if (rss_conf->rss_key && rss_conf->rss_key_len != ROC_NIX_RSS_KEY_LEN) {
 805                 plt_err("Hash key size mismatch %d vs %d",
 806                         rss_conf->rss_key_len, ROC_NIX_RSS_KEY_LEN);
 807                 goto fail;
 808         }
 809
 810         if (rss_conf->rss_key)
 811                 roc_nix_rss_key_set(nix, rss_conf->rss_key);
 812
 813         rss_hash_level = ETH_RSS_LEVEL(rss_conf->rss_hf);
 814         if (rss_hash_level)
 815                 rss_hash_level -= 1;
 816         flowkey_cfg =
 817                 cnxk_rss_ethdev_to_nix(dev, rss_conf->rss_hf, rss_hash_level);
 818
 819         rc = roc_nix_rss_flowkey_set(nix, &alg_idx, flowkey_cfg,
 820                                      ROC_NIX_RSS_GROUP_DEFAULT,
 821                                      ROC_NIX_RSS_MCAM_IDX_DEFAULT);
 822         if (rc) {
 823                 plt_err("Failed to set RSS hash function rc=%d", rc);
 824                 return rc;
 825         }
 826
 827 fail:
 828         return rc;
 829 }
 830
 831 int
 832 cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
 833                            struct rte_eth_rss_conf *rss_conf)
 834 {
 835         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 836
 837         if (rss_conf->rss_key)
 838                 roc_nix_rss_key_get(&dev->nix, rss_conf->rss_key);
 839
 840         rss_conf->rss_key_len = ROC_NIX_RSS_KEY_LEN;
 841         rss_conf->rss_hf = dev->ethdev_rss_hf;
 842
 843         return 0;
 844 }
 845
 846 int
 847 cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev,
 848                                 struct rte_ether_addr *mc_addr_set,
 849                                 uint32_t nb_mc_addr)
 850 {
 851         struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 852         struct rte_eth_dev_data *data = eth_dev->data;
 853         struct rte_ether_addr null_mac_addr;
 854         struct roc_nix *nix = &dev->nix;
 855         int rc, index;
 856         uint32_t i;
 857
 858         memset(&null_mac_addr, 0, sizeof(null_mac_addr));
 859
 860         /* All configured multicast filters should be flushed first */
 861         for (i = 0; i < dev->max_mac_entries; i++) {
 862                 if (rte_is_multicast_ether_addr(&data->mac_addrs[i])) {
 863                         rc = roc_nix_mac_addr_del(nix, i);
 864                         if (rc) {
 865                                 plt_err("Failed to flush mcast address, rc=%d",
 866                                         rc);
 867                                 return rc;
 868                         }
 869
 870                         dev->dmac_filter_count--;
 871                         /* Update address in NIC data structure */
 872                         rte_ether_addr_copy(&null_mac_addr,
 873                                             &data->mac_addrs[i]);
 874                 }
 875         }
 876
 877         if (!mc_addr_set || !nb_mc_addr)
 878                 return 0;
 879
 880         /* Check for available space */
 881         if (nb_mc_addr >
 882             ((uint32_t)(dev->max_mac_entries - dev->dmac_filter_count))) {
 883                 plt_err("No space is available to add multicast filters");
 884                 return -ENOSPC;
 885         }
 886
 887         /* Multicast addresses are to be installed */
 888         for (i = 0; i < nb_mc_addr; i++) {
 889                 index = roc_nix_mac_addr_add(nix, mc_addr_set[i].addr_bytes);
 890                 if (index < 0) {
 891                         plt_err("Failed to add mcast mac address, rc=%d",
 892                                 index);
 893                         return index;
 894                 }
 895
 896                 dev->dmac_filter_count++;
 897                 /* Update address in NIC data structure */
 898                 rte_ether_addr_copy(&mc_addr_set[i], &data->mac_addrs[index]);
 899         }
 900
 901         roc_nix_npc_promisc_ena_dis(nix, true);
 902         dev->dmac_filter_enable = true;
 903         eth_dev->data->promiscuous = false;
 904
 905         return 0;
 906 }