4 * Copyright(c) 2014-2017 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef __CHELSIO_COMMON_H
35 #define __CHELSIO_COMMON_H
37 #include "cxgbe_compat.h"
39 #include "t4_chip_type.h"
40 #include "t4fw_interface.h"
46 #define CXGBE_PAGE_SIZE RTE_PGSIZE_4K
49 MAX_NPORTS = 4, /* max # of ports */
53 T5_REGMAP_SIZE = (332 * 1024),
57 MEMWIN0_APERTURE = 2048,
58 MEMWIN0_BASE = 0x1b800,
61 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
63 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };
68 PAUSE_AUTONEG = 1 << 2
72 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
73 FEC_RS = 1 << 1, /* Reed-Solomon */
74 FEC_BASER_RS = 1 << 2, /* BaseR/Reed-Solomon */
78 u64 tx_octets; /* total # of octets in good frames */
79 u64 tx_frames; /* all good frames */
80 u64 tx_bcast_frames; /* all broadcast frames */
81 u64 tx_mcast_frames; /* all multicast frames */
82 u64 tx_ucast_frames; /* all unicast frames */
83 u64 tx_error_frames; /* all error frames */
85 u64 tx_frames_64; /* # of Tx frames in a particular range */
87 u64 tx_frames_128_255;
88 u64 tx_frames_256_511;
89 u64 tx_frames_512_1023;
90 u64 tx_frames_1024_1518;
91 u64 tx_frames_1519_max;
93 u64 tx_drop; /* # of dropped Tx frames */
94 u64 tx_pause; /* # of transmitted pause frames */
95 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
96 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
97 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
98 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
99 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
100 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
101 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
102 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
104 u64 rx_octets; /* total # of octets in good frames */
105 u64 rx_frames; /* all good frames */
106 u64 rx_bcast_frames; /* all broadcast frames */
107 u64 rx_mcast_frames; /* all multicast frames */
108 u64 rx_ucast_frames; /* all unicast frames */
109 u64 rx_too_long; /* # of frames exceeding MTU */
110 u64 rx_jabber; /* # of jabber frames */
111 u64 rx_fcs_err; /* # of received frames with bad FCS */
112 u64 rx_len_err; /* # of received frames with length error */
113 u64 rx_symbol_err; /* symbol errors */
114 u64 rx_runt; /* # of short frames */
116 u64 rx_frames_64; /* # of Rx frames in a particular range */
117 u64 rx_frames_65_127;
118 u64 rx_frames_128_255;
119 u64 rx_frames_256_511;
120 u64 rx_frames_512_1023;
121 u64 rx_frames_1024_1518;
122 u64 rx_frames_1519_max;
124 u64 rx_pause; /* # of received pause frames */
125 u64 rx_ppp0; /* # of received PPP prio 0 frames */
126 u64 rx_ppp1; /* # of received PPP prio 1 frames */
127 u64 rx_ppp2; /* # of received PPP prio 2 frames */
128 u64 rx_ppp3; /* # of received PPP prio 3 frames */
129 u64 rx_ppp4; /* # of received PPP prio 4 frames */
130 u64 rx_ppp5; /* # of received PPP prio 5 frames */
131 u64 rx_ppp6; /* # of received PPP prio 6 frames */
132 u64 rx_ppp7; /* # of received PPP prio 7 frames */
134 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
135 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
136 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
137 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
138 u64 rx_trunc0; /* buffer-group 0 truncated packets */
139 u64 rx_trunc1; /* buffer-group 1 truncated packets */
140 u64 rx_trunc2; /* buffer-group 2 truncated packets */
141 u64 rx_trunc3; /* buffer-group 3 truncated packets */
145 u32 hps; /* host page size for our PF/VF */
146 u32 eq_qpp; /* egress queues/page for our PF/VF */
147 u32 iq_qpp; /* egress queues/page for our PF/VF */
151 unsigned int ntxchan; /* # of Tx channels */
152 unsigned int tre; /* log2 of core clocks per TP tick */
153 unsigned int dack_re; /* DACK timer resolution */
154 unsigned int la_mask; /* what events are recorded by TP LA */
155 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
157 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
158 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
160 /* cached TP_OUT_CONFIG compressed error vector
161 * and passing outer header info for encapsulated packets.
166 * TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
167 * subset of the set of fields which may be present in the Compressed
168 * Filter Tuple portion of filters and TCP TCB connections. The
169 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
170 * Since a variable number of fields may or may not be present, their
171 * shifted field positions within the Compressed Filter Tuple may
172 * vary, or not even be present if the field isn't selected in
173 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
174 * places we store their offsets here, or a -1 if the field isn't
190 uint32_t vpd_cap_addr;
196 * Firmware device log.
198 struct devlog_params {
199 u32 memtype; /* which memory (EDC0, EDC1, MC) */
200 u32 start; /* start of log in firmware memory */
201 u32 size; /* size of log */
204 struct arch_specific_params {
212 struct adapter_params {
213 struct sge_params sge;
215 struct vpd_params vpd;
216 struct pci_params pci;
217 struct devlog_params devlog;
218 enum pcie_memwin drv_memwin;
220 unsigned int sf_size; /* serial flash size in bytes */
221 unsigned int sf_nsec; /* # of flash sectors */
223 unsigned int fw_vers;
224 unsigned int bs_vers;
225 unsigned int tp_vers;
226 unsigned int er_vers;
228 unsigned short mtus[NMTUS];
229 unsigned short a_wnd[NCCTRL_WIN];
230 unsigned short b_wnd[NCCTRL_WIN];
232 unsigned int mc_size; /* MC memory size */
233 unsigned int cim_la_size;
235 unsigned char nports; /* # of ethernet ports */
236 unsigned char portvec;
238 enum chip_type chip; /* chip code */
239 struct arch_specific_params arch; /* chip specific params */
241 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
244 /* Firmware Port Capabilities types.
246 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */
247 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */
250 fw_port_cap32_t pcaps; /* link capabilities */
251 fw_port_cap32_t acaps; /* advertised capabilities */
253 u32 requested_speed; /* speed (Mb/s) user has requested */
254 u32 speed; /* actual link speed (Mb/s) */
256 enum cc_pause requested_fc; /* flow control user has requested */
257 enum cc_pause fc; /* actual link flow control */
259 enum cc_fec auto_fec; /* Forward Error Correction
260 * "automatic" (IEEE 802.3)
262 enum cc_fec requested_fec; /* Forward Error Correction requested */
263 enum cc_fec fec; /* Forward Error Correction actual */
265 unsigned char autoneg; /* autonegotiating? */
267 unsigned char link_ok; /* link up? */
272 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
274 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
276 int attempts, int delay, u32 *valp);
278 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
279 int polarity, int attempts, int delay)
281 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
285 #define for_each_port(adapter, iter) \
286 for (iter = 0; iter < (adapter)->params.nports; ++iter)
288 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
289 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
290 unsigned int mask, unsigned int val);
291 void t4_intr_enable(struct adapter *adapter);
292 void t4_intr_disable(struct adapter *adapter);
293 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
294 struct link_config *lc);
295 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
296 const unsigned short *alpha, const unsigned short *beta);
297 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
298 enum dev_master master, enum dev_state *state);
299 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
300 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
301 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int reset);
302 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
303 int t4_fl_pkt_align(struct adapter *adap);
304 int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size,
305 unsigned int cache_line_size,
306 enum chip_type chip_compat);
307 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
308 unsigned int cache_line_size);
309 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
310 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
311 unsigned int vf, unsigned int nparams, const u32 *params,
313 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
314 unsigned int pf, unsigned int vf,
315 unsigned int nparams, const u32 *params,
316 const u32 *val, int timeout);
317 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
318 unsigned int vf, unsigned int nparams, const u32 *params,
320 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
321 unsigned int port, unsigned int pf, unsigned int vf,
322 unsigned int nmac, u8 *mac, unsigned int *rss_size,
323 unsigned int portfunc, unsigned int idstype);
324 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
325 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
326 unsigned int *rss_size);
327 int t4_free_vi(struct adapter *adap, unsigned int mbox,
328 unsigned int pf, unsigned int vf,
330 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
331 int mtu, int promisc, int all_multi, int bcast, int vlanex,
333 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
334 int idx, const u8 *addr, bool persist, bool add_smt);
335 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
336 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
337 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
338 bool rx_en, bool tx_en);
339 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
340 unsigned int pf, unsigned int vf, unsigned int iqid,
341 unsigned int fl0id, unsigned int fl1id);
342 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
343 unsigned int vf, unsigned int iqtype, unsigned int iqid,
344 unsigned int fl0id, unsigned int fl1id);
345 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
346 unsigned int vf, unsigned int eqid);
348 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
350 return adap->params.vpd.cclk / 1000;
353 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
356 return (us * adap->params.vpd.cclk) / 1000;
359 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
362 /* add Core Clock / 2 to round ticks to nearest uS */
363 return ((ticks * 1000 + adapter->params.vpd.cclk / 2) /
364 adapter->params.vpd.cclk);
367 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
368 int size, void *rpl, bool sleep_ok, int timeout);
369 int t4_wr_mbox_meat(struct adapter *adap, int mbox,
370 const void __attribute__((__may_alias__)) *cmd, int size,
371 void *rpl, bool sleep_ok);
373 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
374 const void *cmd, int size, void *rpl,
377 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
381 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p);
383 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
386 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
389 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
392 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
395 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
396 unsigned int data_reg, u32 *vals, unsigned int nregs,
397 unsigned int start_idx);
398 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
399 unsigned int data_reg, const u32 *vals,
400 unsigned int nregs, unsigned int start_idx);
402 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
403 int t4_read_flash(struct adapter *adapter, unsigned int addr,
404 unsigned int nwords, u32 *data, int byte_oriented);
405 int t4_flash_cfg_addr(struct adapter *adapter);
406 unsigned int t4_get_mps_bg_map(struct adapter *adapter, unsigned int pidx);
407 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx);
408 const char *t4_get_port_type_description(enum fw_port_type port_type);
409 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
410 void t4_get_port_stats_offset(struct adapter *adap, int idx,
411 struct port_stats *stats,
412 struct port_stats *offset);
413 void t4_clr_port_stats(struct adapter *adap, int idx);
414 void t4_reset_link_config(struct adapter *adap, int idx);
415 int t4_get_version_info(struct adapter *adapter);
416 void t4_dump_version_info(struct adapter *adapter);
417 int t4_get_flash_params(struct adapter *adapter);
418 int t4_get_chip_type(struct adapter *adap, int ver);
419 int t4_prep_adapter(struct adapter *adapter);
420 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
421 int t4_init_rss_mode(struct adapter *adap, int mbox);
422 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
423 int start, int n, const u16 *rspq, unsigned int nrspq);
424 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
425 unsigned int flags, unsigned int defq);
426 int t4_read_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
427 u64 *flags, unsigned int *defq);
428 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
429 unsigned int start_index, unsigned int rw);
430 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx);
431 void t4_read_rss_key(struct adapter *adap, u32 *key);
433 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
434 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
435 unsigned int qtype, u64 *pbar2_qoffset,
436 unsigned int *pbar2_qid);
438 int t4_init_sge_params(struct adapter *adapter);
439 int t4_init_tp_params(struct adapter *adap);
440 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel);
441 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
442 unsigned int t4_get_regs_len(struct adapter *adap);
443 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
444 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
445 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
446 int t4_seeprom_wp(struct adapter *adapter, int enable);
447 #endif /* __CHELSIO_COMMON_H */