drivers/net/cxgbe/base/t4_hw.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2014-2017 Chelsio Communications.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Chelsio Communications nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <netinet/in.h>
  35
  36 #include <rte_interrupts.h>
  37 #include <rte_log.h>
  38 #include <rte_debug.h>
  39 #include <rte_pci.h>
  40 #include <rte_atomic.h>
  41 #include <rte_branch_prediction.h>
  42 #include <rte_memory.h>
  43 #include <rte_tailq.h>
  44 #include <rte_eal.h>
  45 #include <rte_alarm.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev_driver.h>
  48 #include <rte_malloc.h>
  49 #include <rte_random.h>
  50 #include <rte_dev.h>
  51 #include <rte_byteorder.h>
  52
  53 #include "common.h"
  54 #include "t4_regs.h"
  55 #include "t4_regs_values.h"
  56 #include "t4fw_interface.h"
  57
  58 static void init_link_config(struct link_config *lc, unsigned int pcaps,
  59                              unsigned int acaps);
  60
  61 /**
  62  * t4_read_mtu_tbl - returns the values in the HW path MTU table
  63  * @adap: the adapter
  64  * @mtus: where to store the MTU values
  65  * @mtu_log: where to store the MTU base-2 log (may be %NULL)
  66  *
  67  * Reads the HW path MTU table.
  68  */
  69 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
  70 {
  71         u32 v;
  72         int i;
  73
  74         for (i = 0; i < NMTUS; ++i) {
  75                 t4_write_reg(adap, A_TP_MTU_TABLE,
  76                              V_MTUINDEX(0xff) | V_MTUVALUE(i));
  77                 v = t4_read_reg(adap, A_TP_MTU_TABLE);
  78                 mtus[i] = G_MTUVALUE(v);
  79                 if (mtu_log)
  80                         mtu_log[i] = G_MTUWIDTH(v);
  81         }
  82 }
  83
  84 /**
  85  * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
  86  * @adap: the adapter
  87  * @addr: the indirect TP register address
  88  * @mask: specifies the field within the register to modify
  89  * @val: new value for the field
  90  *
  91  * Sets a field of an indirect TP register to the given value.
  92  */
  93 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
  94                             unsigned int mask, unsigned int val)
  95 {
  96         t4_write_reg(adap, A_TP_PIO_ADDR, addr);
  97         val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
  98         t4_write_reg(adap, A_TP_PIO_DATA, val);
  99 }
 100
 101 /* The minimum additive increment value for the congestion control table */
 102 #define CC_MIN_INCR 2U
 103
 104 /**
 105  * t4_load_mtus - write the MTU and congestion control HW tables
 106  * @adap: the adapter
 107  * @mtus: the values for the MTU table
 108  * @alpha: the values for the congestion control alpha parameter
 109  * @beta: the values for the congestion control beta parameter
 110  *
 111  * Write the HW MTU table with the supplied MTUs and the high-speed
 112  * congestion control table with the supplied alpha, beta, and MTUs.
 113  * We write the two tables together because the additive increments
 114  * depend on the MTUs.
 115  */
 116 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
 117                   const unsigned short *alpha, const unsigned short *beta)
 118 {
 119         static const unsigned int avg_pkts[NCCTRL_WIN] = {
 120                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
 121                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
 122                 28672, 40960, 57344, 81920, 114688, 163840, 229376
 123         };
 124
 125         unsigned int i, w;
 126
 127         for (i = 0; i < NMTUS; ++i) {
 128                 unsigned int mtu = mtus[i];
 129                 unsigned int log2 = cxgbe_fls(mtu);
 130
 131                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
 132                         log2--;
 133                 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
 134                              V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
 135
 136                 for (w = 0; w < NCCTRL_WIN; ++w) {
 137                         unsigned int inc;
 138
 139                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
 140                                   CC_MIN_INCR);
 141
 142                         t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
 143                                      (w << 16) | (beta[w] << 13) | inc);
 144                 }
 145         }
 146 }
 147
 148 /**
 149  * t4_wait_op_done_val - wait until an operation is completed
 150  * @adapter: the adapter performing the operation
 151  * @reg: the register to check for completion
 152  * @mask: a single-bit field within @reg that indicates completion
 153  * @polarity: the value of the field when the operation is completed
 154  * @attempts: number of check iterations
 155  * @delay: delay in usecs between iterations
 156  * @valp: where to store the value of the register at completion time
 157  *
 158  * Wait until an operation is completed by checking a bit in a register
 159  * up to @attempts times.  If @valp is not NULL the value of the register
 160  * at the time it indicated completion is stored there.  Returns 0 if the
 161  * operation completes and -EAGAIN otherwise.
 162  */
 163 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
 164                         int polarity, int attempts, int delay, u32 *valp)
 165 {
 166         while (1) {
 167                 u32 val = t4_read_reg(adapter, reg);
 168
 169                 if (!!(val & mask) == polarity) {
 170                         if (valp)
 171                                 *valp = val;
 172                         return 0;
 173                 }
 174                 if (--attempts == 0)
 175                         return -EAGAIN;
 176                 if (delay)
 177                         udelay(delay);
 178         }
 179 }
 180
 181 /**
 182  * t4_set_reg_field - set a register field to a value
 183  * @adapter: the adapter to program
 184  * @addr: the register address
 185  * @mask: specifies the portion of the register to modify
 186  * @val: the new value for the register field
 187  *
 188  * Sets a register field specified by the supplied mask to the
 189  * given value.
 190  */
 191 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
 192                       u32 val)
 193 {
 194         u32 v = t4_read_reg(adapter, addr) & ~mask;
 195
 196         t4_write_reg(adapter, addr, v | val);
 197         (void)t4_read_reg(adapter, addr);      /* flush */
 198 }
 199
 200 /**
 201  * t4_read_indirect - read indirectly addressed registers
 202  * @adap: the adapter
 203  * @addr_reg: register holding the indirect address
 204  * @data_reg: register holding the value of the indirect register
 205  * @vals: where the read register values are stored
 206  * @nregs: how many indirect registers to read
 207  * @start_idx: index of first indirect register to read
 208  *
 209  * Reads registers that are accessed indirectly through an address/data
 210  * register pair.
 211  */
 212 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 213                       unsigned int data_reg, u32 *vals, unsigned int nregs,
 214                       unsigned int start_idx)
 215 {
 216         while (nregs--) {
 217                 t4_write_reg(adap, addr_reg, start_idx);
 218                 *vals++ = t4_read_reg(adap, data_reg);
 219                 start_idx++;
 220         }
 221 }
 222
 223 /**
 224  * t4_write_indirect - write indirectly addressed registers
 225  * @adap: the adapter
 226  * @addr_reg: register holding the indirect addresses
 227  * @data_reg: register holding the value for the indirect registers
 228  * @vals: values to write
 229  * @nregs: how many indirect registers to write
 230  * @start_idx: address of first indirect register to write
 231  *
 232  * Writes a sequential block of registers that are accessed indirectly
 233  * through an address/data register pair.
 234  */
 235 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 236                        unsigned int data_reg, const u32 *vals,
 237                        unsigned int nregs, unsigned int start_idx)
 238 {
 239         while (nregs--) {
 240                 t4_write_reg(adap, addr_reg, start_idx++);
 241                 t4_write_reg(adap, data_reg, *vals++);
 242         }
 243 }
 244
 245 /**
 246  * t4_report_fw_error - report firmware error
 247  * @adap: the adapter
 248  *
 249  * The adapter firmware can indicate error conditions to the host.
 250  * If the firmware has indicated an error, print out the reason for
 251  * the firmware error.
 252  */
 253 static void t4_report_fw_error(struct adapter *adap)
 254 {
 255         static const char * const reason[] = {
 256                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 257                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 258                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 259                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 260                 "Unexpected Event",     /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 261                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 262                 "Device Shutdown",      /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 263                 "Reserved",                     /* reserved */
 264         };
 265         u32 pcie_fw;
 266
 267         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 268         if (pcie_fw & F_PCIE_FW_ERR)
 269                 pr_err("%s: Firmware reports adapter error: %s\n",
 270                        __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);
 271 }
 272
 273 /*
 274  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 275  */
 276 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 277                          u32 mbox_addr)
 278 {
 279         for ( ; nflit; nflit--, mbox_addr += 8)
 280                 *rpl++ = htobe64(t4_read_reg64(adap, mbox_addr));
 281 }
 282
 283 /*
 284  * Handle a FW assertion reported in a mailbox.
 285  */
 286 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 287 {
 288         struct fw_debug_cmd asrt;
 289
 290         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 291         pr_warn("FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 292                 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 293                 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 294 }
 295
 296 #define X_CIM_PF_NOACCESS 0xeeeeeeee
 297
 298 /*
 299  * If the Host OS Driver needs locking arround accesses to the mailbox, this
 300  * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...
 301  */
 302 /* makes single-statement usage a bit cleaner ... */
 303 #ifdef T4_OS_NEEDS_MBOX_LOCKING
 304 #define T4_OS_MBOX_LOCKING(x) x
 305 #else
 306 #define T4_OS_MBOX_LOCKING(x) do {} while (0)
 307 #endif
 308
 309 /**
 310  * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 311  * @adap: the adapter
 312  * @mbox: index of the mailbox to use
 313  * @cmd: the command to write
 314  * @size: command length in bytes
 315  * @rpl: where to optionally store the reply
 316  * @sleep_ok: if true we may sleep while awaiting command completion
 317  * @timeout: time to wait for command to finish before timing out
 318  *           (negative implies @sleep_ok=false)
 319  *
 320  * Sends the given command to FW through the selected mailbox and waits
 321  * for the FW to execute the command.  If @rpl is not %NULL it is used to
 322  * store the FW's reply to the command.  The command and its optional
 323  * reply are of the same length.  Some FW commands like RESET and
 324  * INITIALIZE can take a considerable amount of time to execute.
 325  * @sleep_ok determines whether we may sleep while awaiting the response.
 326  * If sleeping is allowed we use progressive backoff otherwise we spin.
 327  * Note that passing in a negative @timeout is an alternate mechanism
 328  * for specifying @sleep_ok=false.  This is useful when a higher level
 329  * interface allows for specification of @timeout but not @sleep_ok ...
 330  *
 331  * Returns 0 on success or a negative errno on failure.  A
 332  * failure can happen either because we are not able to execute the
 333  * command or FW executes it but signals an error.  In the latter case
 334  * the return value is the error code indicated by FW (negated).
 335  */
 336 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,
 337                             const void __attribute__((__may_alias__)) *cmd,
 338                             int size, void *rpl, bool sleep_ok, int timeout)
 339 {
 340         /*
 341          * We delay in small increments at first in an effort to maintain
 342          * responsiveness for simple, fast executing commands but then back
 343          * off to larger delays to a maximum retry delay.
 344          */
 345         static const int delay[] = {
 346                 1, 1, 3, 5, 10, 10, 20, 50, 100
 347         };
 348
 349         u32 v;
 350         u64 res;
 351         int i, ms;
 352         unsigned int delay_idx;
 353         __be64 *temp = (__be64 *)malloc(size * sizeof(char));
 354         __be64 *p = temp;
 355         u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
 356         u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
 357         u32 ctl;
 358         struct mbox_entry entry;
 359         u32 pcie_fw = 0;
 360
 361         if (!temp)
 362                 return -ENOMEM;
 363
 364         if ((size & 15) || size > MBOX_LEN) {
 365                 free(temp);
 366                 return -EINVAL;
 367         }
 368
 369         bzero(p, size);
 370         memcpy(p, (const __be64 *)cmd, size);
 371
 372         /*
 373          * If we have a negative timeout, that implies that we can't sleep.
 374          */
 375         if (timeout < 0) {
 376                 sleep_ok = false;
 377                 timeout = -timeout;
 378         }
 379
 380 #ifdef T4_OS_NEEDS_MBOX_LOCKING
 381         /*
 382          * Queue ourselves onto the mailbox access list.  When our entry is at
 383          * the front of the list, we have rights to access the mailbox.  So we
 384          * wait [for a while] till we're at the front [or bail out with an
 385          * EBUSY] ...
 386          */
 387         t4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);
 388
 389         delay_idx = 0;
 390         ms = delay[0];
 391
 392         for (i = 0; ; i += ms) {
 393                 /*
 394                  * If we've waited too long, return a busy indication.  This
 395                  * really ought to be based on our initial position in the
 396                  * mailbox access list but this is a start.  We very rarely
 397                  * contend on access to the mailbox ...  Also check for a
 398                  * firmware error which we'll report as a device error.
 399                  */
 400                 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 401                 if (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {
 402                         t4_os_atomic_list_del(&entry, &adap->mbox_list,
 403                                               &adap->mbox_lock);
 404                         t4_report_fw_error(adap);
 405                         free(temp);
 406                         return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;
 407                 }
 408
 409                 /*
 410                  * If we're at the head, break out and start the mailbox
 411                  * protocol.
 412                  */
 413                 if (t4_os_list_first_entry(&adap->mbox_list) == &entry)
 414                         break;
 415
 416                 /*
 417                  * Delay for a bit before checking again ...
 418                  */
 419                 if (sleep_ok) {
 420                         ms = delay[delay_idx];  /* last element may repeat */
 421                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 422                                 delay_idx++;
 423                         msleep(ms);
 424                 } else {
 425                         rte_delay_ms(ms);
 426                 }
 427         }
 428 #endif /* T4_OS_NEEDS_MBOX_LOCKING */
 429
 430         /*
 431          * Attempt to gain access to the mailbox.
 432          */
 433         for (i = 0; i < 4; i++) {
 434                 ctl = t4_read_reg(adap, ctl_reg);
 435                 v = G_MBOWNER(ctl);
 436                 if (v != X_MBOWNER_NONE)
 437                         break;
 438         }
 439
 440         /*
 441          * If we were unable to gain access, dequeue ourselves from the
 442          * mailbox atomic access list and report the error to our caller.
 443          */
 444         if (v != X_MBOWNER_PL) {
 445                 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
 446                                                          &adap->mbox_list,
 447                                                          &adap->mbox_lock));
 448                 t4_report_fw_error(adap);
 449                 free(temp);
 450                 return (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);
 451         }
 452
 453         /*
 454          * If we gain ownership of the mailbox and there's a "valid" message
 455          * in it, this is likely an asynchronous error message from the
 456          * firmware.  So we'll report that and then proceed on with attempting
 457          * to issue our own command ... which may well fail if the error
 458          * presaged the firmware crashing ...
 459          */
 460         if (ctl & F_MBMSGVALID) {
 461                 dev_err(adap, "found VALID command in mbox %u: "
 462                         "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
 463                         (unsigned long long)t4_read_reg64(adap, data_reg),
 464                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 465                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 466                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 467                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 468                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 469                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 470                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 471         }
 472
 473         /*
 474          * Copy in the new mailbox command and send it on its way ...
 475          */
 476         for (i = 0; i < size; i += 8, p++)
 477                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
 478
 479         CXGBE_DEBUG_MBOX(adap, "%s: mbox %u: %016llx %016llx %016llx %016llx "
 480                         "%016llx %016llx %016llx %016llx\n", __func__,  (mbox),
 481                         (unsigned long long)t4_read_reg64(adap, data_reg),
 482                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 483                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 484                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 485                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 486                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 487                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 488                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 489
 490         t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
 491         t4_read_reg(adap, ctl_reg);          /* flush write */
 492
 493         delay_idx = 0;
 494         ms = delay[0];
 495
 496         /*
 497          * Loop waiting for the reply; bail out if we time out or the firmware
 498          * reports an error.
 499          */
 500         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 501         for (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {
 502                 if (sleep_ok) {
 503                         ms = delay[delay_idx];  /* last element may repeat */
 504                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 505                                 delay_idx++;
 506                         msleep(ms);
 507                 } else {
 508                         msleep(ms);
 509                 }
 510
 511                 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 512                 v = t4_read_reg(adap, ctl_reg);
 513                 if (v == X_CIM_PF_NOACCESS)
 514                         continue;
 515                 if (G_MBOWNER(v) == X_MBOWNER_PL) {
 516                         if (!(v & F_MBMSGVALID)) {
 517                                 t4_write_reg(adap, ctl_reg,
 518                                              V_MBOWNER(X_MBOWNER_NONE));
 519                                 continue;
 520                         }
 521
 522                         CXGBE_DEBUG_MBOX(adap,
 523                         "%s: mbox %u: %016llx %016llx %016llx %016llx "
 524                         "%016llx %016llx %016llx %016llx\n", __func__,  (mbox),
 525                         (unsigned long long)t4_read_reg64(adap, data_reg),
 526                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 527                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 528                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 529                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 530                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 531                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 532                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 533
 534                         CXGBE_DEBUG_MBOX(adap,
 535                                 "command %#x completed in %d ms (%ssleeping)\n",
 536                                 *(const u8 *)cmd,
 537                                 i + ms, sleep_ok ? "" : "non-");
 538
 539                         res = t4_read_reg64(adap, data_reg);
 540                         if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
 541                                 fw_asrt(adap, data_reg);
 542                                 res = V_FW_CMD_RETVAL(EIO);
 543                         } else if (rpl) {
 544                                 get_mbox_rpl(adap, rpl, size / 8, data_reg);
 545                         }
 546                         t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
 547                         T4_OS_MBOX_LOCKING(
 548                                 t4_os_atomic_list_del(&entry, &adap->mbox_list,
 549                                                       &adap->mbox_lock));
 550                         free(temp);
 551                         return -G_FW_CMD_RETVAL((int)res);
 552                 }
 553         }
 554
 555         /*
 556          * We timed out waiting for a reply to our mailbox command.  Report
 557          * the error and also check to see if the firmware reported any
 558          * errors ...
 559          */
 560         dev_err(adap, "command %#x in mailbox %d timed out\n",
 561                 *(const u8 *)cmd, mbox);
 562         T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
 563                                                  &adap->mbox_list,
 564                                                  &adap->mbox_lock));
 565         t4_report_fw_error(adap);
 566         free(temp);
 567         return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
 568 }
 569
 570 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 571                     void *rpl, bool sleep_ok)
 572 {
 573         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 574                                        FW_CMD_MAX_TIMEOUT);
 575 }
 576
 577 /**
 578  * t4_get_regs_len - return the size of the chips register set
 579  * @adapter: the adapter
 580  *
 581  * Returns the size of the chip's BAR0 register space.
 582  */
 583 unsigned int t4_get_regs_len(struct adapter *adapter)
 584 {
 585         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 586
 587         switch (chip_version) {
 588         case CHELSIO_T5:
 589         case CHELSIO_T6:
 590                 return T5_REGMAP_SIZE;
 591         }
 592
 593         dev_err(adapter,
 594                 "Unsupported chip version %d\n", chip_version);
 595         return 0;
 596 }
 597
 598 /**
 599  * t4_get_regs - read chip registers into provided buffer
 600  * @adap: the adapter
 601  * @buf: register buffer
 602  * @buf_size: size (in bytes) of register buffer
 603  *
 604  * If the provided register buffer isn't large enough for the chip's
 605  * full register range, the register dump will be truncated to the
 606  * register buffer's size.
 607  */
 608 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 609 {
 610         static const unsigned int t5_reg_ranges[] = {
 611                 0x1008, 0x10c0,
 612                 0x10cc, 0x10f8,
 613                 0x1100, 0x1100,
 614                 0x110c, 0x1148,
 615                 0x1180, 0x1184,
 616                 0x1190, 0x1194,
 617                 0x11a0, 0x11a4,
 618                 0x11b0, 0x11b4,
 619                 0x11fc, 0x123c,
 620                 0x1280, 0x173c,
 621                 0x1800, 0x18fc,
 622                 0x3000, 0x3028,
 623                 0x3060, 0x30b0,
 624                 0x30b8, 0x30d8,
 625                 0x30e0, 0x30fc,
 626                 0x3140, 0x357c,
 627                 0x35a8, 0x35cc,
 628                 0x35ec, 0x35ec,
 629                 0x3600, 0x5624,
 630                 0x56cc, 0x56ec,
 631                 0x56f4, 0x5720,
 632                 0x5728, 0x575c,
 633                 0x580c, 0x5814,
 634                 0x5890, 0x589c,
 635                 0x58a4, 0x58ac,
 636                 0x58b8, 0x58bc,
 637                 0x5940, 0x59c8,
 638                 0x59d0, 0x59dc,
 639                 0x59fc, 0x5a18,
 640                 0x5a60, 0x5a70,
 641                 0x5a80, 0x5a9c,
 642                 0x5b94, 0x5bfc,
 643                 0x6000, 0x6020,
 644                 0x6028, 0x6040,
 645                 0x6058, 0x609c,
 646                 0x60a8, 0x614c,
 647                 0x7700, 0x7798,
 648                 0x77c0, 0x78fc,
 649                 0x7b00, 0x7b58,
 650                 0x7b60, 0x7b84,
 651                 0x7b8c, 0x7c54,
 652                 0x7d00, 0x7d38,
 653                 0x7d40, 0x7d80,
 654                 0x7d8c, 0x7ddc,
 655                 0x7de4, 0x7e04,
 656                 0x7e10, 0x7e1c,
 657                 0x7e24, 0x7e38,
 658                 0x7e40, 0x7e44,
 659                 0x7e4c, 0x7e78,
 660                 0x7e80, 0x7edc,
 661                 0x7ee8, 0x7efc,
 662                 0x8dc0, 0x8de0,
 663                 0x8df8, 0x8e04,
 664                 0x8e10, 0x8e84,
 665                 0x8ea0, 0x8f84,
 666                 0x8fc0, 0x9058,
 667                 0x9060, 0x9060,
 668                 0x9068, 0x90f8,
 669                 0x9400, 0x9408,
 670                 0x9410, 0x9470,
 671                 0x9600, 0x9600,
 672                 0x9608, 0x9638,
 673                 0x9640, 0x96f4,
 674                 0x9800, 0x9808,
 675                 0x9820, 0x983c,
 676                 0x9850, 0x9864,
 677                 0x9c00, 0x9c6c,
 678                 0x9c80, 0x9cec,
 679                 0x9d00, 0x9d6c,
 680                 0x9d80, 0x9dec,
 681                 0x9e00, 0x9e6c,
 682                 0x9e80, 0x9eec,
 683                 0x9f00, 0x9f6c,
 684                 0x9f80, 0xa020,
 685                 0xd004, 0xd004,
 686                 0xd010, 0xd03c,
 687                 0xdfc0, 0xdfe0,
 688                 0xe000, 0x1106c,
 689                 0x11074, 0x11088,
 690                 0x1109c, 0x1117c,
 691                 0x11190, 0x11204,
 692                 0x19040, 0x1906c,
 693                 0x19078, 0x19080,
 694                 0x1908c, 0x190e8,
 695                 0x190f0, 0x190f8,
 696                 0x19100, 0x19110,
 697                 0x19120, 0x19124,
 698                 0x19150, 0x19194,
 699                 0x1919c, 0x191b0,
 700                 0x191d0, 0x191e8,
 701                 0x19238, 0x19290,
 702                 0x193f8, 0x19428,
 703                 0x19430, 0x19444,
 704                 0x1944c, 0x1946c,
 705                 0x19474, 0x19474,
 706                 0x19490, 0x194cc,
 707                 0x194f0, 0x194f8,
 708                 0x19c00, 0x19c08,
 709                 0x19c10, 0x19c60,
 710                 0x19c94, 0x19ce4,
 711                 0x19cf0, 0x19d40,
 712                 0x19d50, 0x19d94,
 713                 0x19da0, 0x19de8,
 714                 0x19df0, 0x19e10,
 715                 0x19e50, 0x19e90,
 716                 0x19ea0, 0x19f24,
 717                 0x19f34, 0x19f34,
 718                 0x19f40, 0x19f50,
 719                 0x19f90, 0x19fb4,
 720                 0x19fc4, 0x19fe4,
 721                 0x1a000, 0x1a004,
 722                 0x1a010, 0x1a06c,
 723                 0x1a0b0, 0x1a0e4,
 724                 0x1a0ec, 0x1a0f8,
 725                 0x1a100, 0x1a108,
 726                 0x1a114, 0x1a120,
 727                 0x1a128, 0x1a130,
 728                 0x1a138, 0x1a138,
 729                 0x1a190, 0x1a1c4,
 730                 0x1a1fc, 0x1a1fc,
 731                 0x1e008, 0x1e00c,
 732                 0x1e040, 0x1e044,
 733                 0x1e04c, 0x1e04c,
 734                 0x1e284, 0x1e290,
 735                 0x1e2c0, 0x1e2c0,
 736                 0x1e2e0, 0x1e2e0,
 737                 0x1e300, 0x1e384,
 738                 0x1e3c0, 0x1e3c8,
 739                 0x1e408, 0x1e40c,
 740                 0x1e440, 0x1e444,
 741                 0x1e44c, 0x1e44c,
 742                 0x1e684, 0x1e690,
 743                 0x1e6c0, 0x1e6c0,
 744                 0x1e6e0, 0x1e6e0,
 745                 0x1e700, 0x1e784,
 746                 0x1e7c0, 0x1e7c8,
 747                 0x1e808, 0x1e80c,
 748                 0x1e840, 0x1e844,
 749                 0x1e84c, 0x1e84c,
 750                 0x1ea84, 0x1ea90,
 751                 0x1eac0, 0x1eac0,
 752                 0x1eae0, 0x1eae0,
 753                 0x1eb00, 0x1eb84,
 754                 0x1ebc0, 0x1ebc8,
 755                 0x1ec08, 0x1ec0c,
 756                 0x1ec40, 0x1ec44,
 757                 0x1ec4c, 0x1ec4c,
 758                 0x1ee84, 0x1ee90,
 759                 0x1eec0, 0x1eec0,
 760                 0x1eee0, 0x1eee0,
 761                 0x1ef00, 0x1ef84,
 762                 0x1efc0, 0x1efc8,
 763                 0x1f008, 0x1f00c,
 764                 0x1f040, 0x1f044,
 765                 0x1f04c, 0x1f04c,
 766                 0x1f284, 0x1f290,
 767                 0x1f2c0, 0x1f2c0,
 768                 0x1f2e0, 0x1f2e0,
 769                 0x1f300, 0x1f384,
 770                 0x1f3c0, 0x1f3c8,
 771                 0x1f408, 0x1f40c,
 772                 0x1f440, 0x1f444,
 773                 0x1f44c, 0x1f44c,
 774                 0x1f684, 0x1f690,
 775                 0x1f6c0, 0x1f6c0,
 776                 0x1f6e0, 0x1f6e0,
 777                 0x1f700, 0x1f784,
 778                 0x1f7c0, 0x1f7c8,
 779                 0x1f808, 0x1f80c,
 780                 0x1f840, 0x1f844,
 781                 0x1f84c, 0x1f84c,
 782                 0x1fa84, 0x1fa90,
 783                 0x1fac0, 0x1fac0,
 784                 0x1fae0, 0x1fae0,
 785                 0x1fb00, 0x1fb84,
 786                 0x1fbc0, 0x1fbc8,
 787                 0x1fc08, 0x1fc0c,
 788                 0x1fc40, 0x1fc44,
 789                 0x1fc4c, 0x1fc4c,
 790                 0x1fe84, 0x1fe90,
 791                 0x1fec0, 0x1fec0,
 792                 0x1fee0, 0x1fee0,
 793                 0x1ff00, 0x1ff84,
 794                 0x1ffc0, 0x1ffc8,
 795                 0x30000, 0x30030,
 796                 0x30038, 0x30038,
 797                 0x30040, 0x30040,
 798                 0x30100, 0x30144,
 799                 0x30190, 0x301a0,
 800                 0x301a8, 0x301b8,
 801                 0x301c4, 0x301c8,
 802                 0x301d0, 0x301d0,
 803                 0x30200, 0x30318,
 804                 0x30400, 0x304b4,
 805                 0x304c0, 0x3052c,
 806                 0x30540, 0x3061c,
 807                 0x30800, 0x30828,
 808                 0x30834, 0x30834,
 809                 0x308c0, 0x30908,
 810                 0x30910, 0x309ac,
 811                 0x30a00, 0x30a14,
 812                 0x30a1c, 0x30a2c,
 813                 0x30a44, 0x30a50,
 814                 0x30a74, 0x30a74,
 815                 0x30a7c, 0x30afc,
 816                 0x30b08, 0x30c24,
 817                 0x30d00, 0x30d00,
 818                 0x30d08, 0x30d14,
 819                 0x30d1c, 0x30d20,
 820                 0x30d3c, 0x30d3c,
 821                 0x30d48, 0x30d50,
 822                 0x31200, 0x3120c,
 823                 0x31220, 0x31220,
 824                 0x31240, 0x31240,
 825                 0x31600, 0x3160c,
 826                 0x31a00, 0x31a1c,
 827                 0x31e00, 0x31e20,
 828                 0x31e38, 0x31e3c,
 829                 0x31e80, 0x31e80,
 830                 0x31e88, 0x31ea8,
 831                 0x31eb0, 0x31eb4,
 832                 0x31ec8, 0x31ed4,
 833                 0x31fb8, 0x32004,
 834                 0x32200, 0x32200,
 835                 0x32208, 0x32240,
 836                 0x32248, 0x32280,
 837                 0x32288, 0x322c0,
 838                 0x322c8, 0x322fc,
 839                 0x32600, 0x32630,
 840                 0x32a00, 0x32abc,
 841                 0x32b00, 0x32b10,
 842                 0x32b20, 0x32b30,
 843                 0x32b40, 0x32b50,
 844                 0x32b60, 0x32b70,
 845                 0x33000, 0x33028,
 846                 0x33030, 0x33048,
 847                 0x33060, 0x33068,
 848                 0x33070, 0x3309c,
 849                 0x330f0, 0x33128,
 850                 0x33130, 0x33148,
 851                 0x33160, 0x33168,
 852                 0x33170, 0x3319c,
 853                 0x331f0, 0x33238,
 854                 0x33240, 0x33240,
 855                 0x33248, 0x33250,
 856                 0x3325c, 0x33264,
 857                 0x33270, 0x332b8,
 858                 0x332c0, 0x332e4,
 859                 0x332f8, 0x33338,
 860                 0x33340, 0x33340,
 861                 0x33348, 0x33350,
 862                 0x3335c, 0x33364,
 863                 0x33370, 0x333b8,
 864                 0x333c0, 0x333e4,
 865                 0x333f8, 0x33428,
 866                 0x33430, 0x33448,
 867                 0x33460, 0x33468,
 868                 0x33470, 0x3349c,
 869                 0x334f0, 0x33528,
 870                 0x33530, 0x33548,
 871                 0x33560, 0x33568,
 872                 0x33570, 0x3359c,
 873                 0x335f0, 0x33638,
 874                 0x33640, 0x33640,
 875                 0x33648, 0x33650,
 876                 0x3365c, 0x33664,
 877                 0x33670, 0x336b8,
 878                 0x336c0, 0x336e4,
 879                 0x336f8, 0x33738,
 880                 0x33740, 0x33740,
 881                 0x33748, 0x33750,
 882                 0x3375c, 0x33764,
 883                 0x33770, 0x337b8,
 884                 0x337c0, 0x337e4,
 885                 0x337f8, 0x337fc,
 886                 0x33814, 0x33814,
 887                 0x3382c, 0x3382c,
 888                 0x33880, 0x3388c,
 889                 0x338e8, 0x338ec,
 890                 0x33900, 0x33928,
 891                 0x33930, 0x33948,
 892                 0x33960, 0x33968,
 893                 0x33970, 0x3399c,
 894                 0x339f0, 0x33a38,
 895                 0x33a40, 0x33a40,
 896                 0x33a48, 0x33a50,
 897                 0x33a5c, 0x33a64,
 898                 0x33a70, 0x33ab8,
 899                 0x33ac0, 0x33ae4,
 900                 0x33af8, 0x33b10,
 901                 0x33b28, 0x33b28,
 902                 0x33b3c, 0x33b50,
 903                 0x33bf0, 0x33c10,
 904                 0x33c28, 0x33c28,
 905                 0x33c3c, 0x33c50,
 906                 0x33cf0, 0x33cfc,
 907                 0x34000, 0x34030,
 908                 0x34038, 0x34038,
 909                 0x34040, 0x34040,
 910                 0x34100, 0x34144,
 911                 0x34190, 0x341a0,
 912                 0x341a8, 0x341b8,
 913                 0x341c4, 0x341c8,
 914                 0x341d0, 0x341d0,
 915                 0x34200, 0x34318,
 916                 0x34400, 0x344b4,
 917                 0x344c0, 0x3452c,
 918                 0x34540, 0x3461c,
 919                 0x34800, 0x34828,
 920                 0x34834, 0x34834,
 921                 0x348c0, 0x34908,
 922                 0x34910, 0x349ac,
 923                 0x34a00, 0x34a14,
 924                 0x34a1c, 0x34a2c,
 925                 0x34a44, 0x34a50,
 926                 0x34a74, 0x34a74,
 927                 0x34a7c, 0x34afc,
 928                 0x34b08, 0x34c24,
 929                 0x34d00, 0x34d00,
 930                 0x34d08, 0x34d14,
 931                 0x34d1c, 0x34d20,
 932                 0x34d3c, 0x34d3c,
 933                 0x34d48, 0x34d50,
 934                 0x35200, 0x3520c,
 935                 0x35220, 0x35220,
 936                 0x35240, 0x35240,
 937                 0x35600, 0x3560c,
 938                 0x35a00, 0x35a1c,
 939                 0x35e00, 0x35e20,
 940                 0x35e38, 0x35e3c,
 941                 0x35e80, 0x35e80,
 942                 0x35e88, 0x35ea8,
 943                 0x35eb0, 0x35eb4,
 944                 0x35ec8, 0x35ed4,
 945                 0x35fb8, 0x36004,
 946                 0x36200, 0x36200,
 947                 0x36208, 0x36240,
 948                 0x36248, 0x36280,
 949                 0x36288, 0x362c0,
 950                 0x362c8, 0x362fc,
 951                 0x36600, 0x36630,
 952                 0x36a00, 0x36abc,
 953                 0x36b00, 0x36b10,
 954                 0x36b20, 0x36b30,
 955                 0x36b40, 0x36b50,
 956                 0x36b60, 0x36b70,
 957                 0x37000, 0x37028,
 958                 0x37030, 0x37048,
 959                 0x37060, 0x37068,
 960                 0x37070, 0x3709c,
 961                 0x370f0, 0x37128,
 962                 0x37130, 0x37148,
 963                 0x37160, 0x37168,
 964                 0x37170, 0x3719c,
 965                 0x371f0, 0x37238,
 966                 0x37240, 0x37240,
 967                 0x37248, 0x37250,
 968                 0x3725c, 0x37264,
 969                 0x37270, 0x372b8,
 970                 0x372c0, 0x372e4,
 971                 0x372f8, 0x37338,
 972                 0x37340, 0x37340,
 973                 0x37348, 0x37350,
 974                 0x3735c, 0x37364,
 975                 0x37370, 0x373b8,
 976                 0x373c0, 0x373e4,
 977                 0x373f8, 0x37428,
 978                 0x37430, 0x37448,
 979                 0x37460, 0x37468,
 980                 0x37470, 0x3749c,
 981                 0x374f0, 0x37528,
 982                 0x37530, 0x37548,
 983                 0x37560, 0x37568,
 984                 0x37570, 0x3759c,
 985                 0x375f0, 0x37638,
 986                 0x37640, 0x37640,
 987                 0x37648, 0x37650,
 988                 0x3765c, 0x37664,
 989                 0x37670, 0x376b8,
 990                 0x376c0, 0x376e4,
 991                 0x376f8, 0x37738,
 992                 0x37740, 0x37740,
 993                 0x37748, 0x37750,
 994                 0x3775c, 0x37764,
 995                 0x37770, 0x377b8,
 996                 0x377c0, 0x377e4,
 997                 0x377f8, 0x377fc,
 998                 0x37814, 0x37814,
 999                 0x3782c, 0x3782c,
1000                 0x37880, 0x3788c,
1001                 0x378e8, 0x378ec,
1002                 0x37900, 0x37928,
1003                 0x37930, 0x37948,
1004                 0x37960, 0x37968,
1005                 0x37970, 0x3799c,
1006                 0x379f0, 0x37a38,
1007                 0x37a40, 0x37a40,
1008                 0x37a48, 0x37a50,
1009                 0x37a5c, 0x37a64,
1010                 0x37a70, 0x37ab8,
1011                 0x37ac0, 0x37ae4,
1012                 0x37af8, 0x37b10,
1013                 0x37b28, 0x37b28,
1014                 0x37b3c, 0x37b50,
1015                 0x37bf0, 0x37c10,
1016                 0x37c28, 0x37c28,
1017                 0x37c3c, 0x37c50,
1018                 0x37cf0, 0x37cfc,
1019                 0x38000, 0x38030,
1020                 0x38038, 0x38038,
1021                 0x38040, 0x38040,
1022                 0x38100, 0x38144,
1023                 0x38190, 0x381a0,
1024                 0x381a8, 0x381b8,
1025                 0x381c4, 0x381c8,
1026                 0x381d0, 0x381d0,
1027                 0x38200, 0x38318,
1028                 0x38400, 0x384b4,
1029                 0x384c0, 0x3852c,
1030                 0x38540, 0x3861c,
1031                 0x38800, 0x38828,
1032                 0x38834, 0x38834,
1033                 0x388c0, 0x38908,
1034                 0x38910, 0x389ac,
1035                 0x38a00, 0x38a14,
1036                 0x38a1c, 0x38a2c,
1037                 0x38a44, 0x38a50,
1038                 0x38a74, 0x38a74,
1039                 0x38a7c, 0x38afc,
1040                 0x38b08, 0x38c24,
1041                 0x38d00, 0x38d00,
1042                 0x38d08, 0x38d14,
1043                 0x38d1c, 0x38d20,
1044                 0x38d3c, 0x38d3c,
1045                 0x38d48, 0x38d50,
1046                 0x39200, 0x3920c,
1047                 0x39220, 0x39220,
1048                 0x39240, 0x39240,
1049                 0x39600, 0x3960c,
1050                 0x39a00, 0x39a1c,
1051                 0x39e00, 0x39e20,
1052                 0x39e38, 0x39e3c,
1053                 0x39e80, 0x39e80,
1054                 0x39e88, 0x39ea8,
1055                 0x39eb0, 0x39eb4,
1056                 0x39ec8, 0x39ed4,
1057                 0x39fb8, 0x3a004,
1058                 0x3a200, 0x3a200,
1059                 0x3a208, 0x3a240,
1060                 0x3a248, 0x3a280,
1061                 0x3a288, 0x3a2c0,
1062                 0x3a2c8, 0x3a2fc,
1063                 0x3a600, 0x3a630,
1064                 0x3aa00, 0x3aabc,
1065                 0x3ab00, 0x3ab10,
1066                 0x3ab20, 0x3ab30,
1067                 0x3ab40, 0x3ab50,
1068                 0x3ab60, 0x3ab70,
1069                 0x3b000, 0x3b028,
1070                 0x3b030, 0x3b048,
1071                 0x3b060, 0x3b068,
1072                 0x3b070, 0x3b09c,
1073                 0x3b0f0, 0x3b128,
1074                 0x3b130, 0x3b148,
1075                 0x3b160, 0x3b168,
1076                 0x3b170, 0x3b19c,
1077                 0x3b1f0, 0x3b238,
1078                 0x3b240, 0x3b240,
1079                 0x3b248, 0x3b250,
1080                 0x3b25c, 0x3b264,
1081                 0x3b270, 0x3b2b8,
1082                 0x3b2c0, 0x3b2e4,
1083                 0x3b2f8, 0x3b338,
1084                 0x3b340, 0x3b340,
1085                 0x3b348, 0x3b350,
1086                 0x3b35c, 0x3b364,
1087                 0x3b370, 0x3b3b8,
1088                 0x3b3c0, 0x3b3e4,
1089                 0x3b3f8, 0x3b428,
1090                 0x3b430, 0x3b448,
1091                 0x3b460, 0x3b468,
1092                 0x3b470, 0x3b49c,
1093                 0x3b4f0, 0x3b528,
1094                 0x3b530, 0x3b548,
1095                 0x3b560, 0x3b568,
1096                 0x3b570, 0x3b59c,
1097                 0x3b5f0, 0x3b638,
1098                 0x3b640, 0x3b640,
1099                 0x3b648, 0x3b650,
1100                 0x3b65c, 0x3b664,
1101                 0x3b670, 0x3b6b8,
1102                 0x3b6c0, 0x3b6e4,
1103                 0x3b6f8, 0x3b738,
1104                 0x3b740, 0x3b740,
1105                 0x3b748, 0x3b750,
1106                 0x3b75c, 0x3b764,
1107                 0x3b770, 0x3b7b8,
1108                 0x3b7c0, 0x3b7e4,
1109                 0x3b7f8, 0x3b7fc,
1110                 0x3b814, 0x3b814,
1111                 0x3b82c, 0x3b82c,
1112                 0x3b880, 0x3b88c,
1113                 0x3b8e8, 0x3b8ec,
1114                 0x3b900, 0x3b928,
1115                 0x3b930, 0x3b948,
1116                 0x3b960, 0x3b968,
1117                 0x3b970, 0x3b99c,
1118                 0x3b9f0, 0x3ba38,
1119                 0x3ba40, 0x3ba40,
1120                 0x3ba48, 0x3ba50,
1121                 0x3ba5c, 0x3ba64,
1122                 0x3ba70, 0x3bab8,
1123                 0x3bac0, 0x3bae4,
1124                 0x3baf8, 0x3bb10,
1125                 0x3bb28, 0x3bb28,
1126                 0x3bb3c, 0x3bb50,
1127                 0x3bbf0, 0x3bc10,
1128                 0x3bc28, 0x3bc28,
1129                 0x3bc3c, 0x3bc50,
1130                 0x3bcf0, 0x3bcfc,
1131                 0x3c000, 0x3c030,
1132                 0x3c038, 0x3c038,
1133                 0x3c040, 0x3c040,
1134                 0x3c100, 0x3c144,
1135                 0x3c190, 0x3c1a0,
1136                 0x3c1a8, 0x3c1b8,
1137                 0x3c1c4, 0x3c1c8,
1138                 0x3c1d0, 0x3c1d0,
1139                 0x3c200, 0x3c318,
1140                 0x3c400, 0x3c4b4,
1141                 0x3c4c0, 0x3c52c,
1142                 0x3c540, 0x3c61c,
1143                 0x3c800, 0x3c828,
1144                 0x3c834, 0x3c834,
1145                 0x3c8c0, 0x3c908,
1146                 0x3c910, 0x3c9ac,
1147                 0x3ca00, 0x3ca14,
1148                 0x3ca1c, 0x3ca2c,
1149                 0x3ca44, 0x3ca50,
1150                 0x3ca74, 0x3ca74,
1151                 0x3ca7c, 0x3cafc,
1152                 0x3cb08, 0x3cc24,
1153                 0x3cd00, 0x3cd00,
1154                 0x3cd08, 0x3cd14,
1155                 0x3cd1c, 0x3cd20,
1156                 0x3cd3c, 0x3cd3c,
1157                 0x3cd48, 0x3cd50,
1158                 0x3d200, 0x3d20c,
1159                 0x3d220, 0x3d220,
1160                 0x3d240, 0x3d240,
1161                 0x3d600, 0x3d60c,
1162                 0x3da00, 0x3da1c,
1163                 0x3de00, 0x3de20,
1164                 0x3de38, 0x3de3c,
1165                 0x3de80, 0x3de80,
1166                 0x3de88, 0x3dea8,
1167                 0x3deb0, 0x3deb4,
1168                 0x3dec8, 0x3ded4,
1169                 0x3dfb8, 0x3e004,
1170                 0x3e200, 0x3e200,
1171                 0x3e208, 0x3e240,
1172                 0x3e248, 0x3e280,
1173                 0x3e288, 0x3e2c0,
1174                 0x3e2c8, 0x3e2fc,
1175                 0x3e600, 0x3e630,
1176                 0x3ea00, 0x3eabc,
1177                 0x3eb00, 0x3eb10,
1178                 0x3eb20, 0x3eb30,
1179                 0x3eb40, 0x3eb50,
1180                 0x3eb60, 0x3eb70,
1181                 0x3f000, 0x3f028,
1182                 0x3f030, 0x3f048,
1183                 0x3f060, 0x3f068,
1184                 0x3f070, 0x3f09c,
1185                 0x3f0f0, 0x3f128,
1186                 0x3f130, 0x3f148,
1187                 0x3f160, 0x3f168,
1188                 0x3f170, 0x3f19c,
1189                 0x3f1f0, 0x3f238,
1190                 0x3f240, 0x3f240,
1191                 0x3f248, 0x3f250,
1192                 0x3f25c, 0x3f264,
1193                 0x3f270, 0x3f2b8,
1194                 0x3f2c0, 0x3f2e4,
1195                 0x3f2f8, 0x3f338,
1196                 0x3f340, 0x3f340,
1197                 0x3f348, 0x3f350,
1198                 0x3f35c, 0x3f364,
1199                 0x3f370, 0x3f3b8,
1200                 0x3f3c0, 0x3f3e4,
1201                 0x3f3f8, 0x3f428,
1202                 0x3f430, 0x3f448,
1203                 0x3f460, 0x3f468,
1204                 0x3f470, 0x3f49c,
1205                 0x3f4f0, 0x3f528,
1206                 0x3f530, 0x3f548,
1207                 0x3f560, 0x3f568,
1208                 0x3f570, 0x3f59c,
1209                 0x3f5f0, 0x3f638,
1210                 0x3f640, 0x3f640,
1211                 0x3f648, 0x3f650,
1212                 0x3f65c, 0x3f664,
1213                 0x3f670, 0x3f6b8,
1214                 0x3f6c0, 0x3f6e4,
1215                 0x3f6f8, 0x3f738,
1216                 0x3f740, 0x3f740,
1217                 0x3f748, 0x3f750,
1218                 0x3f75c, 0x3f764,
1219                 0x3f770, 0x3f7b8,
1220                 0x3f7c0, 0x3f7e4,
1221                 0x3f7f8, 0x3f7fc,
1222                 0x3f814, 0x3f814,
1223                 0x3f82c, 0x3f82c,
1224                 0x3f880, 0x3f88c,
1225                 0x3f8e8, 0x3f8ec,
1226                 0x3f900, 0x3f928,
1227                 0x3f930, 0x3f948,
1228                 0x3f960, 0x3f968,
1229                 0x3f970, 0x3f99c,
1230                 0x3f9f0, 0x3fa38,
1231                 0x3fa40, 0x3fa40,
1232                 0x3fa48, 0x3fa50,
1233                 0x3fa5c, 0x3fa64,
1234                 0x3fa70, 0x3fab8,
1235                 0x3fac0, 0x3fae4,
1236                 0x3faf8, 0x3fb10,
1237                 0x3fb28, 0x3fb28,
1238                 0x3fb3c, 0x3fb50,
1239                 0x3fbf0, 0x3fc10,
1240                 0x3fc28, 0x3fc28,
1241                 0x3fc3c, 0x3fc50,
1242                 0x3fcf0, 0x3fcfc,
1243                 0x40000, 0x4000c,
1244                 0x40040, 0x40050,
1245                 0x40060, 0x40068,
1246                 0x4007c, 0x4008c,
1247                 0x40094, 0x400b0,
1248                 0x400c0, 0x40144,
1249                 0x40180, 0x4018c,
1250                 0x40200, 0x40254,
1251                 0x40260, 0x40264,
1252                 0x40270, 0x40288,
1253                 0x40290, 0x40298,
1254                 0x402ac, 0x402c8,
1255                 0x402d0, 0x402e0,
1256                 0x402f0, 0x402f0,
1257                 0x40300, 0x4033c,
1258                 0x403f8, 0x403fc,
1259                 0x41304, 0x413c4,
1260                 0x41400, 0x4140c,
1261                 0x41414, 0x4141c,
1262                 0x41480, 0x414d0,
1263                 0x44000, 0x44054,
1264                 0x4405c, 0x44078,
1265                 0x440c0, 0x44174,
1266                 0x44180, 0x441ac,
1267                 0x441b4, 0x441b8,
1268                 0x441c0, 0x44254,
1269                 0x4425c, 0x44278,
1270                 0x442c0, 0x44374,
1271                 0x44380, 0x443ac,
1272                 0x443b4, 0x443b8,
1273                 0x443c0, 0x44454,
1274                 0x4445c, 0x44478,
1275                 0x444c0, 0x44574,
1276                 0x44580, 0x445ac,
1277                 0x445b4, 0x445b8,
1278                 0x445c0, 0x44654,
1279                 0x4465c, 0x44678,
1280                 0x446c0, 0x44774,
1281                 0x44780, 0x447ac,
1282                 0x447b4, 0x447b8,
1283                 0x447c0, 0x44854,
1284                 0x4485c, 0x44878,
1285                 0x448c0, 0x44974,
1286                 0x44980, 0x449ac,
1287                 0x449b4, 0x449b8,
1288                 0x449c0, 0x449fc,
1289                 0x45000, 0x45004,
1290                 0x45010, 0x45030,
1291                 0x45040, 0x45060,
1292                 0x45068, 0x45068,
1293                 0x45080, 0x45084,
1294                 0x450a0, 0x450b0,
1295                 0x45200, 0x45204,
1296                 0x45210, 0x45230,
1297                 0x45240, 0x45260,
1298                 0x45268, 0x45268,
1299                 0x45280, 0x45284,
1300                 0x452a0, 0x452b0,
1301                 0x460c0, 0x460e4,
1302                 0x47000, 0x4703c,
1303                 0x47044, 0x4708c,
1304                 0x47200, 0x47250,
1305                 0x47400, 0x47408,
1306                 0x47414, 0x47420,
1307                 0x47600, 0x47618,
1308                 0x47800, 0x47814,
1309                 0x48000, 0x4800c,
1310                 0x48040, 0x48050,
1311                 0x48060, 0x48068,
1312                 0x4807c, 0x4808c,
1313                 0x48094, 0x480b0,
1314                 0x480c0, 0x48144,
1315                 0x48180, 0x4818c,
1316                 0x48200, 0x48254,
1317                 0x48260, 0x48264,
1318                 0x48270, 0x48288,
1319                 0x48290, 0x48298,
1320                 0x482ac, 0x482c8,
1321                 0x482d0, 0x482e0,
1322                 0x482f0, 0x482f0,
1323                 0x48300, 0x4833c,
1324                 0x483f8, 0x483fc,
1325                 0x49304, 0x493c4,
1326                 0x49400, 0x4940c,
1327                 0x49414, 0x4941c,
1328                 0x49480, 0x494d0,
1329                 0x4c000, 0x4c054,
1330                 0x4c05c, 0x4c078,
1331                 0x4c0c0, 0x4c174,
1332                 0x4c180, 0x4c1ac,
1333                 0x4c1b4, 0x4c1b8,
1334                 0x4c1c0, 0x4c254,
1335                 0x4c25c, 0x4c278,
1336                 0x4c2c0, 0x4c374,
1337                 0x4c380, 0x4c3ac,
1338                 0x4c3b4, 0x4c3b8,
1339                 0x4c3c0, 0x4c454,
1340                 0x4c45c, 0x4c478,
1341                 0x4c4c0, 0x4c574,
1342                 0x4c580, 0x4c5ac,
1343                 0x4c5b4, 0x4c5b8,
1344                 0x4c5c0, 0x4c654,
1345                 0x4c65c, 0x4c678,
1346                 0x4c6c0, 0x4c774,
1347                 0x4c780, 0x4c7ac,
1348                 0x4c7b4, 0x4c7b8,
1349                 0x4c7c0, 0x4c854,
1350                 0x4c85c, 0x4c878,
1351                 0x4c8c0, 0x4c974,
1352                 0x4c980, 0x4c9ac,
1353                 0x4c9b4, 0x4c9b8,
1354                 0x4c9c0, 0x4c9fc,
1355                 0x4d000, 0x4d004,
1356                 0x4d010, 0x4d030,
1357                 0x4d040, 0x4d060,
1358                 0x4d068, 0x4d068,
1359                 0x4d080, 0x4d084,
1360                 0x4d0a0, 0x4d0b0,
1361                 0x4d200, 0x4d204,
1362                 0x4d210, 0x4d230,
1363                 0x4d240, 0x4d260,
1364                 0x4d268, 0x4d268,
1365                 0x4d280, 0x4d284,
1366                 0x4d2a0, 0x4d2b0,
1367                 0x4e0c0, 0x4e0e4,
1368                 0x4f000, 0x4f03c,
1369                 0x4f044, 0x4f08c,
1370                 0x4f200, 0x4f250,
1371                 0x4f400, 0x4f408,
1372                 0x4f414, 0x4f420,
1373                 0x4f600, 0x4f618,
1374                 0x4f800, 0x4f814,
1375                 0x50000, 0x50084,
1376                 0x50090, 0x500cc,
1377                 0x50400, 0x50400,
1378                 0x50800, 0x50884,
1379                 0x50890, 0x508cc,
1380                 0x50c00, 0x50c00,
1381                 0x51000, 0x5101c,
1382                 0x51300, 0x51308,
1383         };
1384
1385         static const unsigned int t6_reg_ranges[] = {
1386                 0x1008, 0x101c,
1387                 0x1024, 0x10a8,
1388                 0x10b4, 0x10f8,
1389                 0x1100, 0x1114,
1390                 0x111c, 0x112c,
1391                 0x1138, 0x113c,
1392                 0x1144, 0x114c,
1393                 0x1180, 0x1184,
1394                 0x1190, 0x1194,
1395                 0x11a0, 0x11a4,
1396                 0x11b0, 0x11b4,
1397                 0x11fc, 0x1274,
1398                 0x1280, 0x133c,
1399                 0x1800, 0x18fc,
1400                 0x3000, 0x302c,
1401                 0x3060, 0x30b0,
1402                 0x30b8, 0x30d8,
1403                 0x30e0, 0x30fc,
1404                 0x3140, 0x357c,
1405                 0x35a8, 0x35cc,
1406                 0x35ec, 0x35ec,
1407                 0x3600, 0x5624,
1408                 0x56cc, 0x56ec,
1409                 0x56f4, 0x5720,
1410                 0x5728, 0x575c,
1411                 0x580c, 0x5814,
1412                 0x5890, 0x589c,
1413                 0x58a4, 0x58ac,
1414                 0x58b8, 0x58bc,
1415                 0x5940, 0x595c,
1416                 0x5980, 0x598c,
1417                 0x59b0, 0x59c8,
1418                 0x59d0, 0x59dc,
1419                 0x59fc, 0x5a18,
1420                 0x5a60, 0x5a6c,
1421                 0x5a80, 0x5a8c,
1422                 0x5a94, 0x5a9c,
1423                 0x5b94, 0x5bfc,
1424                 0x5c10, 0x5e48,
1425                 0x5e50, 0x5e94,
1426                 0x5ea0, 0x5eb0,
1427                 0x5ec0, 0x5ec0,
1428                 0x5ec8, 0x5ed0,
1429                 0x5ee0, 0x5ee0,
1430                 0x5ef0, 0x5ef0,
1431                 0x5f00, 0x5f00,
1432                 0x6000, 0x6020,
1433                 0x6028, 0x6040,
1434                 0x6058, 0x609c,
1435                 0x60a8, 0x619c,
1436                 0x7700, 0x7798,
1437                 0x77c0, 0x7880,
1438                 0x78cc, 0x78fc,
1439                 0x7b00, 0x7b58,
1440                 0x7b60, 0x7b84,
1441                 0x7b8c, 0x7c54,
1442                 0x7d00, 0x7d38,
1443                 0x7d40, 0x7d84,
1444                 0x7d8c, 0x7ddc,
1445                 0x7de4, 0x7e04,
1446                 0x7e10, 0x7e1c,
1447                 0x7e24, 0x7e38,
1448                 0x7e40, 0x7e44,
1449                 0x7e4c, 0x7e78,
1450                 0x7e80, 0x7edc,
1451                 0x7ee8, 0x7efc,
1452                 0x8dc0, 0x8de4,
1453                 0x8df8, 0x8e04,
1454                 0x8e10, 0x8e84,
1455                 0x8ea0, 0x8f88,
1456                 0x8fb8, 0x9058,
1457                 0x9060, 0x9060,
1458                 0x9068, 0x90f8,
1459                 0x9100, 0x9124,
1460                 0x9400, 0x9470,
1461                 0x9600, 0x9600,
1462                 0x9608, 0x9638,
1463                 0x9640, 0x9704,
1464                 0x9710, 0x971c,
1465                 0x9800, 0x9808,
1466                 0x9820, 0x983c,
1467                 0x9850, 0x9864,
1468                 0x9c00, 0x9c6c,
1469                 0x9c80, 0x9cec,
1470                 0x9d00, 0x9d6c,
1471                 0x9d80, 0x9dec,
1472                 0x9e00, 0x9e6c,
1473                 0x9e80, 0x9eec,
1474                 0x9f00, 0x9f6c,
1475                 0x9f80, 0xa020,
1476                 0xd004, 0xd03c,
1477                 0xd100, 0xd118,
1478                 0xd200, 0xd214,
1479                 0xd220, 0xd234,
1480                 0xd240, 0xd254,
1481                 0xd260, 0xd274,
1482                 0xd280, 0xd294,
1483                 0xd2a0, 0xd2b4,
1484                 0xd2c0, 0xd2d4,
1485                 0xd2e0, 0xd2f4,
1486                 0xd300, 0xd31c,
1487                 0xdfc0, 0xdfe0,
1488                 0xe000, 0xf008,
1489                 0xf010, 0xf018,
1490                 0xf020, 0xf028,
1491                 0x11000, 0x11014,
1492                 0x11048, 0x1106c,
1493                 0x11074, 0x11088,
1494                 0x11098, 0x11120,
1495                 0x1112c, 0x1117c,
1496                 0x11190, 0x112e0,
1497                 0x11300, 0x1130c,
1498                 0x12000, 0x1206c,
1499                 0x19040, 0x1906c,
1500                 0x19078, 0x19080,
1501                 0x1908c, 0x190e8,
1502                 0x190f0, 0x190f8,
1503                 0x19100, 0x19110,
1504                 0x19120, 0x19124,
1505                 0x19150, 0x19194,
1506                 0x1919c, 0x191b0,
1507                 0x191d0, 0x191e8,
1508                 0x19238, 0x19290,
1509                 0x192a4, 0x192b0,
1510                 0x192bc, 0x192bc,
1511                 0x19348, 0x1934c,
1512                 0x193f8, 0x19418,
1513                 0x19420, 0x19428,
1514                 0x19430, 0x19444,
1515                 0x1944c, 0x1946c,
1516                 0x19474, 0x19474,
1517                 0x19490, 0x194cc,
1518                 0x194f0, 0x194f8,
1519                 0x19c00, 0x19c48,
1520                 0x19c50, 0x19c80,
1521                 0x19c94, 0x19c98,
1522                 0x19ca0, 0x19cbc,
1523                 0x19ce4, 0x19ce4,
1524                 0x19cf0, 0x19cf8,
1525                 0x19d00, 0x19d28,
1526                 0x19d50, 0x19d78,
1527                 0x19d94, 0x19d98,
1528                 0x19da0, 0x19dc8,
1529                 0x19df0, 0x19e10,
1530                 0x19e50, 0x19e6c,
1531                 0x19ea0, 0x19ebc,
1532                 0x19ec4, 0x19ef4,
1533                 0x19f04, 0x19f2c,
1534                 0x19f34, 0x19f34,
1535                 0x19f40, 0x19f50,
1536                 0x19f90, 0x19fac,
1537                 0x19fc4, 0x19fc8,
1538                 0x19fd0, 0x19fe4,
1539                 0x1a000, 0x1a004,
1540                 0x1a010, 0x1a06c,
1541                 0x1a0b0, 0x1a0e4,
1542                 0x1a0ec, 0x1a0f8,
1543                 0x1a100, 0x1a108,
1544                 0x1a114, 0x1a120,
1545                 0x1a128, 0x1a130,
1546                 0x1a138, 0x1a138,
1547                 0x1a190, 0x1a1c4,
1548                 0x1a1fc, 0x1a1fc,
1549                 0x1e008, 0x1e00c,
1550                 0x1e040, 0x1e044,
1551                 0x1e04c, 0x1e04c,
1552                 0x1e284, 0x1e290,
1553                 0x1e2c0, 0x1e2c0,
1554                 0x1e2e0, 0x1e2e0,
1555                 0x1e300, 0x1e384,
1556                 0x1e3c0, 0x1e3c8,
1557                 0x1e408, 0x1e40c,
1558                 0x1e440, 0x1e444,
1559                 0x1e44c, 0x1e44c,
1560                 0x1e684, 0x1e690,
1561                 0x1e6c0, 0x1e6c0,
1562                 0x1e6e0, 0x1e6e0,
1563                 0x1e700, 0x1e784,
1564                 0x1e7c0, 0x1e7c8,
1565                 0x1e808, 0x1e80c,
1566                 0x1e840, 0x1e844,
1567                 0x1e84c, 0x1e84c,
1568                 0x1ea84, 0x1ea90,
1569                 0x1eac0, 0x1eac0,
1570                 0x1eae0, 0x1eae0,
1571                 0x1eb00, 0x1eb84,
1572                 0x1ebc0, 0x1ebc8,
1573                 0x1ec08, 0x1ec0c,
1574                 0x1ec40, 0x1ec44,
1575                 0x1ec4c, 0x1ec4c,
1576                 0x1ee84, 0x1ee90,
1577                 0x1eec0, 0x1eec0,
1578                 0x1eee0, 0x1eee0,
1579                 0x1ef00, 0x1ef84,
1580                 0x1efc0, 0x1efc8,
1581                 0x1f008, 0x1f00c,
1582                 0x1f040, 0x1f044,
1583                 0x1f04c, 0x1f04c,
1584                 0x1f284, 0x1f290,
1585                 0x1f2c0, 0x1f2c0,
1586                 0x1f2e0, 0x1f2e0,
1587                 0x1f300, 0x1f384,
1588                 0x1f3c0, 0x1f3c8,
1589                 0x1f408, 0x1f40c,
1590                 0x1f440, 0x1f444,
1591                 0x1f44c, 0x1f44c,
1592                 0x1f684, 0x1f690,
1593                 0x1f6c0, 0x1f6c0,
1594                 0x1f6e0, 0x1f6e0,
1595                 0x1f700, 0x1f784,
1596                 0x1f7c0, 0x1f7c8,
1597                 0x1f808, 0x1f80c,
1598                 0x1f840, 0x1f844,
1599                 0x1f84c, 0x1f84c,
1600                 0x1fa84, 0x1fa90,
1601                 0x1fac0, 0x1fac0,
1602                 0x1fae0, 0x1fae0,
1603                 0x1fb00, 0x1fb84,
1604                 0x1fbc0, 0x1fbc8,
1605                 0x1fc08, 0x1fc0c,
1606                 0x1fc40, 0x1fc44,
1607                 0x1fc4c, 0x1fc4c,
1608                 0x1fe84, 0x1fe90,
1609                 0x1fec0, 0x1fec0,
1610                 0x1fee0, 0x1fee0,
1611                 0x1ff00, 0x1ff84,
1612                 0x1ffc0, 0x1ffc8,
1613                 0x30000, 0x30030,
1614                 0x30100, 0x30168,
1615                 0x30190, 0x301a0,
1616                 0x301a8, 0x301b8,
1617                 0x301c4, 0x301c8,
1618                 0x301d0, 0x301d0,
1619                 0x30200, 0x30320,
1620                 0x30400, 0x304b4,
1621                 0x304c0, 0x3052c,
1622                 0x30540, 0x3061c,
1623                 0x30800, 0x308a0,
1624                 0x308c0, 0x30908,
1625                 0x30910, 0x309b8,
1626                 0x30a00, 0x30a04,
1627                 0x30a0c, 0x30a14,
1628                 0x30a1c, 0x30a2c,
1629                 0x30a44, 0x30a50,
1630                 0x30a74, 0x30a74,
1631                 0x30a7c, 0x30afc,
1632                 0x30b08, 0x30c24,
1633                 0x30d00, 0x30d14,
1634                 0x30d1c, 0x30d3c,
1635                 0x30d44, 0x30d4c,
1636                 0x30d54, 0x30d74,
1637                 0x30d7c, 0x30d7c,
1638                 0x30de0, 0x30de0,
1639                 0x30e00, 0x30ed4,
1640                 0x30f00, 0x30fa4,
1641                 0x30fc0, 0x30fc4,
1642                 0x31000, 0x31004,
1643                 0x31080, 0x310fc,
1644                 0x31208, 0x31220,
1645                 0x3123c, 0x31254,
1646                 0x31300, 0x31300,
1647                 0x31308, 0x3131c,
1648                 0x31338, 0x3133c,
1649                 0x31380, 0x31380,
1650                 0x31388, 0x313a8,
1651                 0x313b4, 0x313b4,
1652                 0x31400, 0x31420,
1653                 0x31438, 0x3143c,
1654                 0x31480, 0x31480,
1655                 0x314a8, 0x314a8,
1656                 0x314b0, 0x314b4,
1657                 0x314c8, 0x314d4,
1658                 0x31a40, 0x31a4c,
1659                 0x31af0, 0x31b20,
1660                 0x31b38, 0x31b3c,
1661                 0x31b80, 0x31b80,
1662                 0x31ba8, 0x31ba8,
1663                 0x31bb0, 0x31bb4,
1664                 0x31bc8, 0x31bd4,
1665                 0x32140, 0x3218c,
1666                 0x321f0, 0x321f4,
1667                 0x32200, 0x32200,
1668                 0x32218, 0x32218,
1669                 0x32400, 0x32400,
1670                 0x32408, 0x3241c,
1671                 0x32618, 0x32620,
1672                 0x32664, 0x32664,
1673                 0x326a8, 0x326a8,
1674                 0x326ec, 0x326ec,
1675                 0x32a00, 0x32abc,
1676                 0x32b00, 0x32b38,
1677                 0x32b20, 0x32b38,
1678                 0x32b40, 0x32b58,
1679                 0x32b60, 0x32b78,
1680                 0x32c00, 0x32c00,
1681                 0x32c08, 0x32c3c,
1682                 0x33000, 0x3302c,
1683                 0x33034, 0x33050,
1684                 0x33058, 0x33058,
1685                 0x33060, 0x3308c,
1686                 0x3309c, 0x330ac,
1687                 0x330c0, 0x330c0,
1688                 0x330c8, 0x330d0,
1689                 0x330d8, 0x330e0,
1690                 0x330ec, 0x3312c,
1691                 0x33134, 0x33150,
1692                 0x33158, 0x33158,
1693                 0x33160, 0x3318c,
1694                 0x3319c, 0x331ac,
1695                 0x331c0, 0x331c0,
1696                 0x331c8, 0x331d0,
1697                 0x331d8, 0x331e0,
1698                 0x331ec, 0x33290,
1699                 0x33298, 0x332c4,
1700                 0x332e4, 0x33390,
1701                 0x33398, 0x333c4,
1702                 0x333e4, 0x3342c,
1703                 0x33434, 0x33450,
1704                 0x33458, 0x33458,
1705                 0x33460, 0x3348c,
1706                 0x3349c, 0x334ac,
1707                 0x334c0, 0x334c0,
1708                 0x334c8, 0x334d0,
1709                 0x334d8, 0x334e0,
1710                 0x334ec, 0x3352c,
1711                 0x33534, 0x33550,
1712                 0x33558, 0x33558,
1713                 0x33560, 0x3358c,
1714                 0x3359c, 0x335ac,
1715                 0x335c0, 0x335c0,
1716                 0x335c8, 0x335d0,
1717                 0x335d8, 0x335e0,
1718                 0x335ec, 0x33690,
1719                 0x33698, 0x336c4,
1720                 0x336e4, 0x33790,
1721                 0x33798, 0x337c4,
1722                 0x337e4, 0x337fc,
1723                 0x33814, 0x33814,
1724                 0x33854, 0x33868,
1725                 0x33880, 0x3388c,
1726                 0x338c0, 0x338d0,
1727                 0x338e8, 0x338ec,
1728                 0x33900, 0x3392c,
1729                 0x33934, 0x33950,
1730                 0x33958, 0x33958,
1731                 0x33960, 0x3398c,
1732                 0x3399c, 0x339ac,
1733                 0x339c0, 0x339c0,
1734                 0x339c8, 0x339d0,
1735                 0x339d8, 0x339e0,
1736                 0x339ec, 0x33a90,
1737                 0x33a98, 0x33ac4,
1738                 0x33ae4, 0x33b10,
1739                 0x33b24, 0x33b28,
1740                 0x33b38, 0x33b50,
1741                 0x33bf0, 0x33c10,
1742                 0x33c24, 0x33c28,
1743                 0x33c38, 0x33c50,
1744                 0x33cf0, 0x33cfc,
1745                 0x34000, 0x34030,
1746                 0x34100, 0x34168,
1747                 0x34190, 0x341a0,
1748                 0x341a8, 0x341b8,
1749                 0x341c4, 0x341c8,
1750                 0x341d0, 0x341d0,
1751                 0x34200, 0x34320,
1752                 0x34400, 0x344b4,
1753                 0x344c0, 0x3452c,
1754                 0x34540, 0x3461c,
1755                 0x34800, 0x348a0,
1756                 0x348c0, 0x34908,
1757                 0x34910, 0x349b8,
1758                 0x34a00, 0x34a04,
1759                 0x34a0c, 0x34a14,
1760                 0x34a1c, 0x34a2c,
1761                 0x34a44, 0x34a50,
1762                 0x34a74, 0x34a74,
1763                 0x34a7c, 0x34afc,
1764                 0x34b08, 0x34c24,
1765                 0x34d00, 0x34d14,
1766                 0x34d1c, 0x34d3c,
1767                 0x34d44, 0x34d4c,
1768                 0x34d54, 0x34d74,
1769                 0x34d7c, 0x34d7c,
1770                 0x34de0, 0x34de0,
1771                 0x34e00, 0x34ed4,
1772                 0x34f00, 0x34fa4,
1773                 0x34fc0, 0x34fc4,
1774                 0x35000, 0x35004,
1775                 0x35080, 0x350fc,
1776                 0x35208, 0x35220,
1777                 0x3523c, 0x35254,
1778                 0x35300, 0x35300,
1779                 0x35308, 0x3531c,
1780                 0x35338, 0x3533c,
1781                 0x35380, 0x35380,
1782                 0x35388, 0x353a8,
1783                 0x353b4, 0x353b4,
1784                 0x35400, 0x35420,
1785                 0x35438, 0x3543c,
1786                 0x35480, 0x35480,
1787                 0x354a8, 0x354a8,
1788                 0x354b0, 0x354b4,
1789                 0x354c8, 0x354d4,
1790                 0x35a40, 0x35a4c,
1791                 0x35af0, 0x35b20,
1792                 0x35b38, 0x35b3c,
1793                 0x35b80, 0x35b80,
1794                 0x35ba8, 0x35ba8,
1795                 0x35bb0, 0x35bb4,
1796                 0x35bc8, 0x35bd4,
1797                 0x36140, 0x3618c,
1798                 0x361f0, 0x361f4,
1799                 0x36200, 0x36200,
1800                 0x36218, 0x36218,
1801                 0x36400, 0x36400,
1802                 0x36408, 0x3641c,
1803                 0x36618, 0x36620,
1804                 0x36664, 0x36664,
1805                 0x366a8, 0x366a8,
1806                 0x366ec, 0x366ec,
1807                 0x36a00, 0x36abc,
1808                 0x36b00, 0x36b38,
1809                 0x36b20, 0x36b38,
1810                 0x36b40, 0x36b58,
1811                 0x36b60, 0x36b78,
1812                 0x36c00, 0x36c00,
1813                 0x36c08, 0x36c3c,
1814                 0x37000, 0x3702c,
1815                 0x37034, 0x37050,
1816                 0x37058, 0x37058,
1817                 0x37060, 0x3708c,
1818                 0x3709c, 0x370ac,
1819                 0x370c0, 0x370c0,
1820                 0x370c8, 0x370d0,
1821                 0x370d8, 0x370e0,
1822                 0x370ec, 0x3712c,
1823                 0x37134, 0x37150,
1824                 0x37158, 0x37158,
1825                 0x37160, 0x3718c,
1826                 0x3719c, 0x371ac,
1827                 0x371c0, 0x371c0,
1828                 0x371c8, 0x371d0,
1829                 0x371d8, 0x371e0,
1830                 0x371ec, 0x37290,
1831                 0x37298, 0x372c4,
1832                 0x372e4, 0x37390,
1833                 0x37398, 0x373c4,
1834                 0x373e4, 0x3742c,
1835                 0x37434, 0x37450,
1836                 0x37458, 0x37458,
1837                 0x37460, 0x3748c,
1838                 0x3749c, 0x374ac,
1839                 0x374c0, 0x374c0,
1840                 0x374c8, 0x374d0,
1841                 0x374d8, 0x374e0,
1842                 0x374ec, 0x3752c,
1843                 0x37534, 0x37550,
1844                 0x37558, 0x37558,
1845                 0x37560, 0x3758c,
1846                 0x3759c, 0x375ac,
1847                 0x375c0, 0x375c0,
1848                 0x375c8, 0x375d0,
1849                 0x375d8, 0x375e0,
1850                 0x375ec, 0x37690,
1851                 0x37698, 0x376c4,
1852                 0x376e4, 0x37790,
1853                 0x37798, 0x377c4,
1854                 0x377e4, 0x377fc,
1855                 0x37814, 0x37814,
1856                 0x37854, 0x37868,
1857                 0x37880, 0x3788c,
1858                 0x378c0, 0x378d0,
1859                 0x378e8, 0x378ec,
1860                 0x37900, 0x3792c,
1861                 0x37934, 0x37950,
1862                 0x37958, 0x37958,
1863                 0x37960, 0x3798c,
1864                 0x3799c, 0x379ac,
1865                 0x379c0, 0x379c0,
1866                 0x379c8, 0x379d0,
1867                 0x379d8, 0x379e0,
1868                 0x379ec, 0x37a90,
1869                 0x37a98, 0x37ac4,
1870                 0x37ae4, 0x37b10,
1871                 0x37b24, 0x37b28,
1872                 0x37b38, 0x37b50,
1873                 0x37bf0, 0x37c10,
1874                 0x37c24, 0x37c28,
1875                 0x37c38, 0x37c50,
1876                 0x37cf0, 0x37cfc,
1877                 0x40040, 0x40040,
1878                 0x40080, 0x40084,
1879                 0x40100, 0x40100,
1880                 0x40140, 0x401bc,
1881                 0x40200, 0x40214,
1882                 0x40228, 0x40228,
1883                 0x40240, 0x40258,
1884                 0x40280, 0x40280,
1885                 0x40304, 0x40304,
1886                 0x40330, 0x4033c,
1887                 0x41304, 0x413c8,
1888                 0x413d0, 0x413dc,
1889                 0x413f0, 0x413f0,
1890                 0x41400, 0x4140c,
1891                 0x41414, 0x4141c,
1892                 0x41480, 0x414d0,
1893                 0x44000, 0x4407c,
1894                 0x440c0, 0x441ac,
1895                 0x441b4, 0x4427c,
1896                 0x442c0, 0x443ac,
1897                 0x443b4, 0x4447c,
1898                 0x444c0, 0x445ac,
1899                 0x445b4, 0x4467c,
1900                 0x446c0, 0x447ac,
1901                 0x447b4, 0x4487c,
1902                 0x448c0, 0x449ac,
1903                 0x449b4, 0x44a7c,
1904                 0x44ac0, 0x44bac,
1905                 0x44bb4, 0x44c7c,
1906                 0x44cc0, 0x44dac,
1907                 0x44db4, 0x44e7c,
1908                 0x44ec0, 0x44fac,
1909                 0x44fb4, 0x4507c,
1910                 0x450c0, 0x451ac,
1911                 0x451b4, 0x451fc,
1912                 0x45800, 0x45804,
1913                 0x45810, 0x45830,
1914                 0x45840, 0x45860,
1915                 0x45868, 0x45868,
1916                 0x45880, 0x45884,
1917                 0x458a0, 0x458b0,
1918                 0x45a00, 0x45a04,
1919                 0x45a10, 0x45a30,
1920                 0x45a40, 0x45a60,
1921                 0x45a68, 0x45a68,
1922                 0x45a80, 0x45a84,
1923                 0x45aa0, 0x45ab0,
1924                 0x460c0, 0x460e4,
1925                 0x47000, 0x4703c,
1926                 0x47044, 0x4708c,
1927                 0x47200, 0x47250,
1928                 0x47400, 0x47408,
1929                 0x47414, 0x47420,
1930                 0x47600, 0x47618,
1931                 0x47800, 0x47814,
1932                 0x47820, 0x4782c,
1933                 0x50000, 0x50084,
1934                 0x50090, 0x500cc,
1935                 0x50300, 0x50384,
1936                 0x50400, 0x50400,
1937                 0x50800, 0x50884,
1938                 0x50890, 0x508cc,
1939                 0x50b00, 0x50b84,
1940                 0x50c00, 0x50c00,
1941                 0x51000, 0x51020,
1942                 0x51028, 0x510b0,
1943                 0x51300, 0x51324,
1944         };
1945
1946         u32 *buf_end = (u32 *)((char *)buf + buf_size);
1947         const unsigned int *reg_ranges;
1948         int reg_ranges_size, range;
1949         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1950
1951         /* Select the right set of register ranges to dump depending on the
1952          * adapter chip type.
1953          */
1954         switch (chip_version) {
1955         case CHELSIO_T5:
1956                 reg_ranges = t5_reg_ranges;
1957                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1958                 break;
1959
1960         case CHELSIO_T6:
1961                 reg_ranges = t6_reg_ranges;
1962                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
1963                 break;
1964
1965         default:
1966                 dev_err(adap,
1967                         "Unsupported chip version %d\n", chip_version);
1968                 return;
1969         }
1970
1971         /* Clear the register buffer and insert the appropriate register
1972          * values selected by the above register ranges.
1973          */
1974         memset(buf, 0, buf_size);
1975         for (range = 0; range < reg_ranges_size; range += 2) {
1976                 unsigned int reg = reg_ranges[range];
1977                 unsigned int last_reg = reg_ranges[range + 1];
1978                 u32 *bufp = (u32 *)((char *)buf + reg);
1979
1980                 /* Iterate across the register range filling in the register
1981                  * buffer but don't write past the end of the register buffer.
1982                  */
1983                 while (reg <= last_reg && bufp < buf_end) {
1984                         *bufp++ = t4_read_reg(adap, reg);
1985                         reg += sizeof(u32);
1986                 }
1987         }
1988 }
1989
1990 /* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */
1991 #define EEPROM_DELAY            10              /* 10us per poll spin */
1992 #define EEPROM_MAX_POLL         5000            /* x 5000 == 50ms */
1993
1994 #define EEPROM_STAT_ADDR        0x7bfc
1995
1996 /**
1997  * Small utility function to wait till any outstanding VPD Access is complete.
1998  * We have a per-adapter state variable "VPD Busy" to indicate when we have a
1999  * VPD Access in flight.  This allows us to handle the problem of having a
2000  * previous VPD Access time out and prevent an attempt to inject a new VPD
2001  * Request before any in-flight VPD request has completed.
2002  */
2003 static int t4_seeprom_wait(struct adapter *adapter)
2004 {
2005         unsigned int base = adapter->params.pci.vpd_cap_addr;
2006         int max_poll;
2007
2008         /* If no VPD Access is in flight, we can just return success right
2009          * away.
2010          */
2011         if (!adapter->vpd_busy)
2012                 return 0;
2013
2014         /* Poll the VPD Capability Address/Flag register waiting for it
2015          * to indicate that the operation is complete.
2016          */
2017         max_poll = EEPROM_MAX_POLL;
2018         do {
2019                 u16 val;
2020
2021                 udelay(EEPROM_DELAY);
2022                 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2023
2024                 /* If the operation is complete, mark the VPD as no longer
2025                  * busy and return success.
2026                  */
2027                 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2028                         adapter->vpd_busy = 0;
2029                         return 0;
2030                 }
2031         } while (--max_poll);
2032
2033         /* Failure!  Note that we leave the VPD Busy status set in order to
2034          * avoid pushing a new VPD Access request into the VPD Capability till
2035          * the current operation eventually succeeds.  It's a bug to issue a
2036          * new request when an existing request is in flight and will result
2037          * in corrupt hardware state.
2038          */
2039         return -ETIMEDOUT;
2040 }
2041
2042 /**
2043  * t4_seeprom_read - read a serial EEPROM location
2044  * @adapter: adapter to read
2045  * @addr: EEPROM virtual address
2046  * @data: where to store the read data
2047  *
2048  * Read a 32-bit word from a location in serial EEPROM using the card's PCI
2049  * VPD capability.  Note that this function must be called with a virtual
2050  * address.
2051  */
2052 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2053 {
2054         unsigned int base = adapter->params.pci.vpd_cap_addr;
2055         int ret;
2056
2057         /* VPD Accesses must alway be 4-byte aligned!
2058          */
2059         if (addr >= EEPROMVSIZE || (addr & 3))
2060                 return -EINVAL;
2061
2062         /* Wait for any previous operation which may still be in flight to
2063          * complete.
2064          */
2065         ret = t4_seeprom_wait(adapter);
2066         if (ret) {
2067                 dev_err(adapter, "VPD still busy from previous operation\n");
2068                 return ret;
2069         }
2070
2071         /* Issue our new VPD Read request, mark the VPD as being busy and wait
2072          * for our request to complete.  If it doesn't complete, note the
2073          * error and return it to our caller.  Note that we do not reset the
2074          * VPD Busy status!
2075          */
2076         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2077         adapter->vpd_busy = 1;
2078         adapter->vpd_flag = PCI_VPD_ADDR_F;
2079         ret = t4_seeprom_wait(adapter);
2080         if (ret) {
2081                 dev_err(adapter, "VPD read of address %#x failed\n", addr);
2082                 return ret;
2083         }
2084
2085         /* Grab the returned data, swizzle it into our endianness and
2086          * return success.
2087          */
2088         t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2089         *data = le32_to_cpu(*data);
2090         return 0;
2091 }
2092
2093 /**
2094  * t4_seeprom_write - write a serial EEPROM location
2095  * @adapter: adapter to write
2096  * @addr: virtual EEPROM address
2097  * @data: value to write
2098  *
2099  * Write a 32-bit word to a location in serial EEPROM using the card's PCI
2100  * VPD capability.  Note that this function must be called with a virtual
2101  * address.
2102  */
2103 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2104 {
2105         unsigned int base = adapter->params.pci.vpd_cap_addr;
2106         int ret;
2107         u32 stats_reg = 0;
2108         int max_poll;
2109
2110         /* VPD Accesses must alway be 4-byte aligned!
2111          */
2112         if (addr >= EEPROMVSIZE || (addr & 3))
2113                 return -EINVAL;
2114
2115         /* Wait for any previous operation which may still be in flight to
2116          * complete.
2117          */
2118         ret = t4_seeprom_wait(adapter);
2119         if (ret) {
2120                 dev_err(adapter, "VPD still busy from previous operation\n");
2121                 return ret;
2122         }
2123
2124         /* Issue our new VPD Read request, mark the VPD as being busy and wait
2125          * for our request to complete.  If it doesn't complete, note the
2126          * error and return it to our caller.  Note that we do not reset the
2127          * VPD Busy status!
2128          */
2129         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2130                              cpu_to_le32(data));
2131         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2132                              (u16)addr | PCI_VPD_ADDR_F);
2133         adapter->vpd_busy = 1;
2134         adapter->vpd_flag = 0;
2135         ret = t4_seeprom_wait(adapter);
2136         if (ret) {
2137                 dev_err(adapter, "VPD write of address %#x failed\n", addr);
2138                 return ret;
2139         }
2140
2141         /* Reset PCI_VPD_DATA register after a transaction and wait for our
2142          * request to complete. If it doesn't complete, return error.
2143          */
2144         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2145         max_poll = EEPROM_MAX_POLL;
2146         do {
2147                 udelay(EEPROM_DELAY);
2148                 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2149         } while ((stats_reg & 0x1) && --max_poll);
2150         if (!max_poll)
2151                 return -ETIMEDOUT;
2152
2153         /* Return success! */
2154         return 0;
2155 }
2156
2157 /**
2158  * t4_seeprom_wp - enable/disable EEPROM write protection
2159  * @adapter: the adapter
2160  * @enable: whether to enable or disable write protection
2161  *
2162  * Enables or disables write protection on the serial EEPROM.
2163  */
2164 int t4_seeprom_wp(struct adapter *adapter, int enable)
2165 {
2166         return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2167 }
2168
2169 /**
2170  * t4_fw_tp_pio_rw - Access TP PIO through LDST
2171  * @adap: the adapter
2172  * @vals: where the indirect register values are stored/written
2173  * @nregs: how many indirect registers to read/write
2174  * @start_idx: index of first indirect register to read/write
2175  * @rw: Read (1) or Write (0)
2176  *
2177  * Access TP PIO registers through LDST
2178  */
2179 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
2180                      unsigned int start_index, unsigned int rw)
2181 {
2182         int cmd = FW_LDST_ADDRSPC_TP_PIO;
2183         struct fw_ldst_cmd c;
2184         unsigned int i;
2185         int ret;
2186
2187         for (i = 0 ; i < nregs; i++) {
2188                 memset(&c, 0, sizeof(c));
2189                 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
2190                                                 F_FW_CMD_REQUEST |
2191                                                 (rw ? F_FW_CMD_READ :
2192                                                       F_FW_CMD_WRITE) |
2193                                                 V_FW_LDST_CMD_ADDRSPACE(cmd));
2194                 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
2195
2196                 c.u.addrval.addr = cpu_to_be32(start_index + i);
2197                 c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
2198                 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
2199                 if (ret == 0) {
2200                         if (rw)
2201                                 vals[i] = be32_to_cpu(c.u.addrval.val);
2202                 }
2203         }
2204 }
2205
2206 /**
2207  * t4_write_rss_key - program one of the RSS keys
2208  * @adap: the adapter
2209  * @key: 10-entry array holding the 320-bit RSS key
2210  * @idx: which RSS key to write
2211  *
2212  * Writes one of the RSS keys with the given 320-bit value.  If @idx is
2213  * 0..15 the corresponding entry in the RSS key table is written,
2214  * otherwise the global RSS key is written.
2215  */
2216 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx)
2217 {
2218         u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
2219         u8 rss_key_addr_cnt = 16;
2220
2221         /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
2222          * allows access to key addresses 16-63 by using KeyWrAddrX
2223          * as index[5:4](upper 2) into key table
2224          */
2225         if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
2226             (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))
2227                 rss_key_addr_cnt = 32;
2228
2229         t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 0);
2230
2231         if (idx >= 0 && idx < rss_key_addr_cnt) {
2232                 if (rss_key_addr_cnt > 16)
2233                         t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
2234                                      V_KEYWRADDRX(idx >> 4) |
2235                                      V_T6_VFWRADDR(idx) | F_KEYWREN);
2236                 else
2237                         t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
2238                                      V_KEYWRADDR(idx) | F_KEYWREN);
2239         }
2240 }
2241
2242 /**
2243  * t4_config_rss_range - configure a portion of the RSS mapping table
2244  * @adapter: the adapter
2245  * @mbox: mbox to use for the FW command
2246  * @viid: virtual interface whose RSS subtable is to be written
2247  * @start: start entry in the table to write
2248  * @n: how many table entries to write
2249  * @rspq: values for the "response queue" (Ingress Queue) lookup table
2250  * @nrspq: number of values in @rspq
2251  *
2252  * Programs the selected part of the VI's RSS mapping table with the
2253  * provided values.  If @nrspq < @n the supplied values are used repeatedly
2254  * until the full table range is populated.
2255  *
2256  * The caller must ensure the values in @rspq are in the range allowed for
2257  * @viid.
2258  */
2259 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
2260                         int start, int n, const u16 *rspq, unsigned int nrspq)
2261 {
2262         int ret;
2263         const u16 *rsp = rspq;
2264         const u16 *rsp_end = rspq + nrspq;
2265         struct fw_rss_ind_tbl_cmd cmd;
2266
2267         memset(&cmd, 0, sizeof(cmd));
2268         cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
2269                                      F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2270                                      V_FW_RSS_IND_TBL_CMD_VIID(viid));
2271         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2272
2273         /*
2274          * Each firmware RSS command can accommodate up to 32 RSS Ingress
2275          * Queue Identifiers.  These Ingress Queue IDs are packed three to
2276          * a 32-bit word as 10-bit values with the upper remaining 2 bits
2277          * reserved.
2278          */
2279         while (n > 0) {
2280                 int nq = min(n, 32);
2281                 int nq_packed = 0;
2282                 __be32 *qp = &cmd.iq0_to_iq2;
2283
2284                 /*
2285                  * Set up the firmware RSS command header to send the next
2286                  * "nq" Ingress Queue IDs to the firmware.
2287                  */
2288                 cmd.niqid = cpu_to_be16(nq);
2289                 cmd.startidx = cpu_to_be16(start);
2290
2291                 /*
2292                  * "nq" more done for the start of the next loop.
2293                  */
2294                 start += nq;
2295                 n -= nq;
2296
2297                 /*
2298                  * While there are still Ingress Queue IDs to stuff into the
2299                  * current firmware RSS command, retrieve them from the
2300                  * Ingress Queue ID array and insert them into the command.
2301                  */
2302                 while (nq > 0) {
2303                         /*
2304                          * Grab up to the next 3 Ingress Queue IDs (wrapping
2305                          * around the Ingress Queue ID array if necessary) and
2306                          * insert them into the firmware RSS command at the
2307                          * current 3-tuple position within the commad.
2308                          */
2309                         u16 qbuf[3];
2310                         u16 *qbp = qbuf;
2311                         int nqbuf = min(3, nq);
2312
2313                         nq -= nqbuf;
2314                         qbuf[0] = 0;
2315                         qbuf[1] = 0;
2316                         qbuf[2] = 0;
2317                         while (nqbuf && nq_packed < 32) {
2318                                 nqbuf--;
2319                                 nq_packed++;
2320                                 *qbp++ = *rsp++;
2321                                 if (rsp >= rsp_end)
2322                                         rsp = rspq;
2323                         }
2324                         *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
2325                                             V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
2326                                             V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
2327                 }
2328
2329                 /*
2330                  * Send this portion of the RRS table update to the firmware;
2331                  * bail out on any errors.
2332                  */
2333                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
2334                 if (ret)
2335                         return ret;
2336         }
2337
2338         return 0;
2339 }
2340
2341 /**
2342  * t4_config_vi_rss - configure per VI RSS settings
2343  * @adapter: the adapter
2344  * @mbox: mbox to use for the FW command
2345  * @viid: the VI id
2346  * @flags: RSS flags
2347  * @defq: id of the default RSS queue for the VI.
2348  *
2349  * Configures VI-specific RSS properties.
2350  */
2351 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
2352                      unsigned int flags, unsigned int defq)
2353 {
2354         struct fw_rss_vi_config_cmd c;
2355
2356         memset(&c, 0, sizeof(c));
2357         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
2358                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2359                                    V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
2360         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2361         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
2362                         V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
2363         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
2364 }
2365
2366 /**
2367  * init_cong_ctrl - initialize congestion control parameters
2368  * @a: the alpha values for congestion control
2369  * @b: the beta values for congestion control
2370  *
2371  * Initialize the congestion control parameters.
2372  */
2373 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
2374 {
2375         int i;
2376
2377         for (i = 0; i < 9; i++) {
2378                 a[i] = 1;
2379                 b[i] = 0;
2380         }
2381
2382         a[9] = 2;
2383         a[10] = 3;
2384         a[11] = 4;
2385         a[12] = 5;
2386         a[13] = 6;
2387         a[14] = 7;
2388         a[15] = 8;
2389         a[16] = 9;
2390         a[17] = 10;
2391         a[18] = 14;
2392         a[19] = 17;
2393         a[20] = 21;
2394         a[21] = 25;
2395         a[22] = 30;
2396         a[23] = 35;
2397         a[24] = 45;
2398         a[25] = 60;
2399         a[26] = 80;
2400         a[27] = 100;
2401         a[28] = 200;
2402         a[29] = 300;
2403         a[30] = 400;
2404         a[31] = 500;
2405
2406         b[9] = 1;
2407         b[10] = 1;
2408         b[11] = 2;
2409         b[12] = 2;
2410         b[13] = 3;
2411         b[14] = 3;
2412         b[15] = 3;
2413         b[16] = 3;
2414         b[17] = 4;
2415         b[18] = 4;
2416         b[19] = 4;
2417         b[20] = 4;
2418         b[21] = 4;
2419         b[22] = 5;
2420         b[23] = 5;
2421         b[24] = 5;
2422         b[25] = 5;
2423         b[26] = 5;
2424         b[27] = 5;
2425         b[28] = 6;
2426         b[29] = 6;
2427         b[30] = 7;
2428         b[31] = 7;
2429 }
2430
2431 #define INIT_CMD(var, cmd, rd_wr) do { \
2432         (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
2433                         F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \
2434         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
2435 } while (0)
2436
2437 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)
2438 {
2439         u32 cclk_param, cclk_val;
2440         int ret;
2441
2442         /*
2443          * Ask firmware for the Core Clock since it knows how to translate the
2444          * Reference Clock ('V2') VPD field into a Core Clock value ...
2445          */
2446         cclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2447                       V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
2448         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2449                               1, &cclk_param, &cclk_val);
2450         if (ret) {
2451                 dev_err(adapter, "%s: error in fetching from coreclock - %d\n",
2452                         __func__, ret);
2453                 return ret;
2454         }
2455
2456         p->cclk = cclk_val;
2457         dev_debug(adapter, "%s: p->cclk = %u\n", __func__, p->cclk);
2458         return 0;
2459 }
2460
2461 /* serial flash and firmware constants and flash config file constants */
2462 enum {
2463         SF_ATTEMPTS = 10,             /* max retries for SF operations */
2464
2465         /* flash command opcodes */
2466         SF_PROG_PAGE    = 2,          /* program page */
2467         SF_WR_DISABLE   = 4,          /* disable writes */
2468         SF_RD_STATUS    = 5,          /* read status register */
2469         SF_WR_ENABLE    = 6,          /* enable writes */
2470         SF_RD_DATA_FAST = 0xb,        /* read flash */
2471         SF_RD_ID        = 0x9f,       /* read ID */
2472         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2473 };
2474
2475 /**
2476  * sf1_read - read data from the serial flash
2477  * @adapter: the adapter
2478  * @byte_cnt: number of bytes to read
2479  * @cont: whether another operation will be chained
2480  * @lock: whether to lock SF for PL access only
2481  * @valp: where to store the read data
2482  *
2483  * Reads up to 4 bytes of data from the serial flash.  The location of
2484  * the read needs to be specified prior to calling this by issuing the
2485  * appropriate commands to the serial flash.
2486  */
2487 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2488                     int lock, u32 *valp)
2489 {
2490         int ret;
2491
2492         if (!byte_cnt || byte_cnt > 4)
2493                 return -EINVAL;
2494         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2495                 return -EBUSY;
2496         t4_write_reg(adapter, A_SF_OP,
2497                      V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
2498         ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2499         if (!ret)
2500                 *valp = t4_read_reg(adapter, A_SF_DATA);
2501         return ret;
2502 }
2503
2504 /**
2505  * sf1_write - write data to the serial flash
2506  * @adapter: the adapter
2507  * @byte_cnt: number of bytes to write
2508  * @cont: whether another operation will be chained
2509  * @lock: whether to lock SF for PL access only
2510  * @val: value to write
2511  *
2512  * Writes up to 4 bytes of data to the serial flash.  The location of
2513  * the write needs to be specified prior to calling this by issuing the
2514  * appropriate commands to the serial flash.
2515  */
2516 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2517                      int lock, u32 val)
2518 {
2519         if (!byte_cnt || byte_cnt > 4)
2520                 return -EINVAL;
2521         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2522                 return -EBUSY;
2523         t4_write_reg(adapter, A_SF_DATA, val);
2524         t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
2525                      V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
2526         return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2527 }
2528
2529 /**
2530  * t4_read_flash - read words from serial flash
2531  * @adapter: the adapter
2532  * @addr: the start address for the read
2533  * @nwords: how many 32-bit words to read
2534  * @data: where to store the read data
2535  * @byte_oriented: whether to store data as bytes or as words
2536  *
2537  * Read the specified number of 32-bit words from the serial flash.
2538  * If @byte_oriented is set the read data is stored as a byte array
2539  * (i.e., big-endian), otherwise as 32-bit words in the platform's
2540  * natural endianness.
2541  */
2542 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2543                   unsigned int nwords, u32 *data, int byte_oriented)
2544 {
2545         int ret;
2546
2547         if (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||
2548             (addr & 3))
2549                 return -EINVAL;
2550
2551         addr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;
2552
2553         ret = sf1_write(adapter, 4, 1, 0, addr);
2554         if (ret != 0)
2555                 return ret;
2556
2557         ret = sf1_read(adapter, 1, 1, 0, data);
2558         if (ret != 0)
2559                 return ret;
2560
2561         for ( ; nwords; nwords--, data++) {
2562                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2563                 if (nwords == 1)
2564                         t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
2565                 if (ret)
2566                         return ret;
2567                 if (byte_oriented)
2568                         *data = cpu_to_be32(*data);
2569         }
2570         return 0;
2571 }
2572
2573 /**
2574  * t4_get_exprom_version - return the Expansion ROM version (if any)
2575  * @adapter: the adapter
2576  * @vers: where to place the version
2577  *
2578  * Reads the Expansion ROM header from FLASH and returns the version
2579  * number (if present) through the @vers return value pointer.  We return
2580  * this in the Firmware Version Format since it's convenient.  Return
2581  * 0 on success, -ENOENT if no Expansion ROM is present.
2582  */
2583 static int t4_get_exprom_version(struct adapter *adapter, u32 *vers)
2584 {
2585         struct exprom_header {
2586                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
2587                 unsigned char hdr_ver[4];       /* Expansion ROM version */
2588         } *hdr;
2589         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2590                                            sizeof(u32))];
2591         int ret;
2592
2593         ret = t4_read_flash(adapter, FLASH_EXP_ROM_START,
2594                             ARRAY_SIZE(exprom_header_buf),
2595                             exprom_header_buf, 0);
2596         if (ret)
2597                 return ret;
2598
2599         hdr = (struct exprom_header *)exprom_header_buf;
2600         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2601                 return -ENOENT;
2602
2603         *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
2604                  V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
2605                  V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
2606                  V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
2607         return 0;
2608 }
2609
2610 /**
2611  * t4_get_fw_version - read the firmware version
2612  * @adapter: the adapter
2613  * @vers: where to place the version
2614  *
2615  * Reads the FW version from flash.
2616  */
2617 static int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2618 {
2619         return t4_read_flash(adapter, FLASH_FW_START +
2620                              offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
2621 }
2622
2623 /**
2624  *     t4_get_bs_version - read the firmware bootstrap version
2625  *     @adapter: the adapter
2626  *     @vers: where to place the version
2627  *
2628  *     Reads the FW Bootstrap version from flash.
2629  */
2630 static int t4_get_bs_version(struct adapter *adapter, u32 *vers)
2631 {
2632         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
2633                              offsetof(struct fw_hdr, fw_ver), 1,
2634                              vers, 0);
2635 }
2636
2637 /**
2638  * t4_get_tp_version - read the TP microcode version
2639  * @adapter: the adapter
2640  * @vers: where to place the version
2641  *
2642  * Reads the TP microcode version from flash.
2643  */
2644 static int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2645 {
2646         return t4_read_flash(adapter, FLASH_FW_START +
2647                              offsetof(struct fw_hdr, tp_microcode_ver),
2648                              1, vers, 0);
2649 }
2650
2651 /**
2652  * t4_get_version_info - extract various chip/firmware version information
2653  * @adapter: the adapter
2654  *
2655  * Reads various chip/firmware version numbers and stores them into the
2656  * adapter Adapter Parameters structure.  If any of the efforts fails
2657  * the first failure will be returned, but all of the version numbers
2658  * will be read.
2659  */
2660 int t4_get_version_info(struct adapter *adapter)
2661 {
2662         int ret = 0;
2663
2664 #define FIRST_RET(__getvinfo) \
2665         do { \
2666                 int __ret = __getvinfo; \
2667                 if (__ret && !ret) \
2668                         ret = __ret; \
2669         } while (0)
2670
2671         FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
2672         FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
2673         FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
2674         FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
2675
2676 #undef FIRST_RET
2677
2678         return ret;
2679 }
2680
2681 /**
2682  * t4_dump_version_info - dump all of the adapter configuration IDs
2683  * @adapter: the adapter
2684  *
2685  * Dumps all of the various bits of adapter configuration version/revision
2686  * IDs information.  This is typically called at some point after
2687  * t4_get_version_info() has been called.
2688  */
2689 void t4_dump_version_info(struct adapter *adapter)
2690 {
2691         /**
2692          * Device information.
2693          */
2694         dev_info(adapter, "Chelsio rev %d\n",
2695                  CHELSIO_CHIP_RELEASE(adapter->params.chip));
2696
2697         /**
2698          * Firmware Version.
2699          */
2700         if (!adapter->params.fw_vers)
2701                 dev_warn(adapter, "No firmware loaded\n");
2702         else
2703                 dev_info(adapter, "Firmware version: %u.%u.%u.%u\n",
2704                          G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers),
2705                          G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers),
2706                          G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers),
2707                          G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers));
2708
2709         /**
2710          * Bootstrap Firmware Version.
2711          */
2712         if (!adapter->params.bs_vers)
2713                 dev_warn(adapter, "No bootstrap loaded\n");
2714         else
2715                 dev_info(adapter, "Bootstrap version: %u.%u.%u.%u\n",
2716                          G_FW_HDR_FW_VER_MAJOR(adapter->params.bs_vers),
2717                          G_FW_HDR_FW_VER_MINOR(adapter->params.bs_vers),
2718                          G_FW_HDR_FW_VER_MICRO(adapter->params.bs_vers),
2719                          G_FW_HDR_FW_VER_BUILD(adapter->params.bs_vers));
2720
2721         /**
2722          * TP Microcode Version.
2723          */
2724         if (!adapter->params.tp_vers)
2725                 dev_warn(adapter, "No TP Microcode loaded\n");
2726         else
2727                 dev_info(adapter, "TP Microcode version: %u.%u.%u.%u\n",
2728                          G_FW_HDR_FW_VER_MAJOR(adapter->params.tp_vers),
2729                          G_FW_HDR_FW_VER_MINOR(adapter->params.tp_vers),
2730                          G_FW_HDR_FW_VER_MICRO(adapter->params.tp_vers),
2731                          G_FW_HDR_FW_VER_BUILD(adapter->params.tp_vers));
2732
2733         /**
2734          * Expansion ROM version.
2735          */
2736         if (!adapter->params.er_vers)
2737                 dev_info(adapter, "No Expansion ROM loaded\n");
2738         else
2739                 dev_info(adapter, "Expansion ROM version: %u.%u.%u.%u\n",
2740                          G_FW_HDR_FW_VER_MAJOR(adapter->params.er_vers),
2741                          G_FW_HDR_FW_VER_MINOR(adapter->params.er_vers),
2742                          G_FW_HDR_FW_VER_MICRO(adapter->params.er_vers),
2743                          G_FW_HDR_FW_VER_BUILD(adapter->params.er_vers));
2744 }
2745
2746 #define ADVERT_MASK (V_FW_PORT_CAP_SPEED(M_FW_PORT_CAP_SPEED) | \
2747                      FW_PORT_CAP_ANEG)
2748
2749 /**
2750  * t4_link_l1cfg - apply link configuration to MAC/PHY
2751  * @phy: the PHY to setup
2752  * @mac: the MAC to setup
2753  * @lc: the requested link configuration
2754  *
2755  * Set up a port's MAC and PHY according to a desired link configuration.
2756  * - If the PHY can auto-negotiate first decide what to advertise, then
2757  *   enable/disable auto-negotiation as desired, and reset.
2758  * - If the PHY does not auto-negotiate just reset it.
2759  * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
2760  *   otherwise do it later based on the outcome of auto-negotiation.
2761  */
2762 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
2763                   struct link_config *lc)
2764 {
2765         struct fw_port_cmd c;
2766         unsigned int mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
2767         unsigned int fc, fec;
2768
2769         lc->link_ok = 0;
2770         fc = 0;
2771         if (lc->requested_fc & PAUSE_RX)
2772                 fc |= FW_PORT_CAP_FC_RX;
2773         if (lc->requested_fc & PAUSE_TX)
2774                 fc |= FW_PORT_CAP_FC_TX;
2775
2776         fec = 0;
2777         if (lc->requested_fec & FEC_RS)
2778                 fec |= FW_PORT_CAP_FEC_RS;
2779         if (lc->requested_fec & FEC_BASER_RS)
2780                 fec |= FW_PORT_CAP_FEC_BASER_RS;
2781         if (lc->requested_fec & FEC_RESERVED)
2782                 fec |= FW_PORT_CAP_FEC_RESERVED;
2783
2784         memset(&c, 0, sizeof(c));
2785         c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
2786                                      F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
2787                                      V_FW_PORT_CMD_PORTID(port));
2788         c.action_to_len16 =
2789                 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
2790                             FW_LEN16(c));
2791
2792         if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2793                 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
2794                                              fc | fec);
2795                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2796                 lc->fec = lc->requested_fec;
2797         } else if (lc->autoneg == AUTONEG_DISABLE) {
2798                 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc |
2799                                              fec | mdi);
2800                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2801                 lc->fec = lc->requested_fec;
2802         } else {
2803                 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | fec | mdi);
2804         }
2805
2806         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2807 }
2808
2809 /**
2810  * t4_flash_cfg_addr - return the address of the flash configuration file
2811  * @adapter: the adapter
2812  *
2813  * Return the address within the flash where the Firmware Configuration
2814  * File is stored, or an error if the device FLASH is too small to contain
2815  * a Firmware Configuration File.
2816  */
2817 int t4_flash_cfg_addr(struct adapter *adapter)
2818 {
2819         /*
2820          * If the device FLASH isn't large enough to hold a Firmware
2821          * Configuration File, return an error.
2822          */
2823         if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
2824                 return -ENOSPC;
2825
2826         return FLASH_CFG_START;
2827 }
2828
2829 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
2830
2831 /**
2832  * t4_intr_enable - enable interrupts
2833  * @adapter: the adapter whose interrupts should be enabled
2834  *
2835  * Enable PF-specific interrupts for the calling function and the top-level
2836  * interrupt concentrator for global interrupts.  Interrupts are already
2837  * enabled at each module, here we just enable the roots of the interrupt
2838  * hierarchies.
2839  *
2840  * Note: this function should be called only when the driver manages
2841  * non PF-specific interrupts from the various HW modules.  Only one PCI
2842  * function at a time should be doing this.
2843  */
2844 void t4_intr_enable(struct adapter *adapter)
2845 {
2846         u32 val = 0;
2847         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2848         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2849                  G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2850
2851         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
2852                 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
2853         t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
2854                      F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
2855                      F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
2856                      F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
2857                      F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
2858                      F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
2859                      F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
2860         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
2861         t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
2862 }
2863
2864 /**
2865  * t4_intr_disable - disable interrupts
2866  * @adapter: the adapter whose interrupts should be disabled
2867  *
2868  * Disable interrupts.  We only disable the top-level interrupt
2869  * concentrators.  The caller must be a PCI function managing global
2870  * interrupts.
2871  */
2872 void t4_intr_disable(struct adapter *adapter)
2873 {
2874         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2875         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2876                  G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2877
2878         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
2879         t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
2880 }
2881
2882 /**
2883  * t4_get_port_type_description - return Port Type string description
2884  * @port_type: firmware Port Type enumeration
2885  */
2886 const char *t4_get_port_type_description(enum fw_port_type port_type)
2887 {
2888         static const char * const port_type_description[] = {
2889                 "Fiber_XFI",
2890                 "Fiber_XAUI",
2891                 "BT_SGMII",
2892                 "BT_XFI",
2893                 "BT_XAUI",
2894                 "KX4",
2895                 "CX4",
2896                 "KX",
2897                 "KR",
2898                 "SFP",
2899                 "BP_AP",
2900                 "BP4_AP",
2901                 "QSFP_10G",
2902                 "QSA",
2903                 "QSFP",
2904                 "BP40_BA",
2905                 "KR4_100G",
2906                 "CR4_QSFP",
2907                 "CR_QSFP",
2908                 "CR2_QSFP",
2909                 "SFP28",
2910                 "KR_SFP28",
2911         };
2912
2913         if (port_type < ARRAY_SIZE(port_type_description))
2914                 return port_type_description[port_type];
2915         return "UNKNOWN";
2916 }
2917
2918 /**
2919  * t4_get_mps_bg_map - return the buffer groups associated with a port
2920  * @adap: the adapter
2921  * @pidx: the port index
2922  *
2923  * Returns a bitmap indicating which MPS buffer groups are associated
2924  * with the given port.  Bit i is set if buffer group i is used by the
2925  * port.
2926  */
2927 unsigned int t4_get_mps_bg_map(struct adapter *adap, unsigned int pidx)
2928 {
2929         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2930         unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adap,
2931                                                           A_MPS_CMN_CTL));
2932
2933         if (pidx >= nports) {
2934                 dev_warn(adap, "MPS Port Index %d >= Nports %d\n",
2935                          pidx, nports);
2936                 return 0;
2937         }
2938
2939         switch (chip_version) {
2940         case CHELSIO_T4:
2941         case CHELSIO_T5:
2942                 switch (nports) {
2943                 case 1: return 0xf;
2944                 case 2: return 3 << (2 * pidx);
2945                 case 4: return 1 << pidx;
2946                 }
2947                 break;
2948
2949         case CHELSIO_T6:
2950                 switch (nports) {
2951                 case 2: return 1 << (2 * pidx);
2952                 }
2953                 break;
2954         }
2955
2956         dev_err(adap, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
2957                 chip_version, nports);
2958         return 0;
2959 }
2960
2961 /**
2962  * t4_get_tp_ch_map - return TP ingress channels associated with a port
2963  * @adapter: the adapter
2964  * @pidx: the port index
2965  *
2966  * Returns a bitmap indicating which TP Ingress Channels are associated with
2967  * a given Port.  Bit i is set if TP Ingress Channel i is used by the Port.
2968  */
2969 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx)
2970 {
2971         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
2972         unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adapter,
2973                                                           A_MPS_CMN_CTL));
2974
2975         if (pidx >= nports) {
2976                 dev_warn(adap, "TP Port Index %d >= Nports %d\n",
2977                          pidx, nports);
2978                 return 0;
2979         }
2980
2981         switch (chip_version) {
2982         case CHELSIO_T4:
2983         case CHELSIO_T5:
2984                 /* Note that this happens to be the same values as the MPS
2985                  * Buffer Group Map for these Chips.  But we replicate the code
2986                  * here because they're really separate concepts.
2987                  */
2988                 switch (nports) {
2989                 case 1: return 0xf;
2990                 case 2: return 3 << (2 * pidx);
2991                 case 4: return 1 << pidx;
2992                 }
2993                 break;
2994
2995         case CHELSIO_T6:
2996                 switch (nports) {
2997                 case 2: return 1 << pidx;
2998                 }
2999                 break;
3000         }
3001
3002         dev_err(adapter, "Need TP Channel Map for Chip %0x, Nports %d\n",
3003                 chip_version, nports);
3004         return 0;
3005 }
3006
3007 /**
3008  * t4_get_port_stats - collect port statistics
3009  * @adap: the adapter
3010  * @idx: the port index
3011  * @p: the stats structure to fill
3012  *
3013  * Collect statistics related to the given port from HW.
3014  */
3015 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
3016 {
3017         u32 bgmap = t4_get_mps_bg_map(adap, idx);
3018         u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
3019
3020 #define GET_STAT(name) \
3021         t4_read_reg64(adap, \
3022                       (is_t4(adap->params.chip) ? \
3023                        PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\
3024                        T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
3025 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
3026
3027         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
3028         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
3029         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
3030         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
3031         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
3032         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
3033         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
3034         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
3035         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
3036         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
3037         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
3038         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
3039         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
3040         p->tx_drop             = GET_STAT(TX_PORT_DROP);
3041         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
3042         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
3043         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
3044         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
3045         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
3046         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
3047         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
3048         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
3049         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
3050
3051         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
3052                 if (stat_ctl & F_COUNTPAUSESTATTX) {
3053                         p->tx_frames -= p->tx_pause;
3054                         p->tx_octets -= p->tx_pause * 64;
3055                 }
3056                 if (stat_ctl & F_COUNTPAUSEMCTX)
3057                         p->tx_mcast_frames -= p->tx_pause;
3058         }
3059
3060         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
3061         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
3062         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
3063         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
3064         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
3065         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
3066         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
3067         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
3068         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
3069         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
3070         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
3071         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
3072         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
3073         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
3074         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
3075         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
3076         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
3077         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
3078         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
3079         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
3080         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
3081         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
3082         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
3083         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
3084         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
3085         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
3086         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
3087
3088         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
3089                 if (stat_ctl & F_COUNTPAUSESTATRX) {
3090                         p->rx_frames -= p->rx_pause;
3091                         p->rx_octets -= p->rx_pause * 64;
3092                 }
3093                 if (stat_ctl & F_COUNTPAUSEMCRX)
3094                         p->rx_mcast_frames -= p->rx_pause;
3095         }
3096
3097         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
3098         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
3099         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
3100         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
3101         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
3102         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
3103         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
3104         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
3105
3106 #undef GET_STAT
3107 #undef GET_STAT_COM
3108 }
3109
3110 /**
3111  * t4_get_port_stats_offset - collect port stats relative to a previous snapshot
3112  * @adap: The adapter
3113  * @idx: The port
3114  * @stats: Current stats to fill
3115  * @offset: Previous stats snapshot
3116  */
3117 void t4_get_port_stats_offset(struct adapter *adap, int idx,
3118                               struct port_stats *stats,
3119                               struct port_stats *offset)
3120 {
3121         u64 *s, *o;
3122         unsigned int i;
3123
3124         t4_get_port_stats(adap, idx, stats);
3125         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
3126              i < (sizeof(struct port_stats) / sizeof(u64));
3127              i++, s++, o++)
3128                 *s -= *o;
3129 }
3130
3131 /**
3132  * t4_clr_port_stats - clear port statistics
3133  * @adap: the adapter
3134  * @idx: the port index
3135  *
3136  * Clear HW statistics for the given port.
3137  */
3138 void t4_clr_port_stats(struct adapter *adap, int idx)
3139 {
3140         unsigned int i;
3141         u32 bgmap = t4_get_mps_bg_map(adap, idx);
3142         u32 port_base_addr;
3143
3144         if (is_t4(adap->params.chip))
3145                 port_base_addr = PORT_BASE(idx);
3146         else
3147                 port_base_addr = T5_PORT_BASE(idx);
3148
3149         for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
3150              i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
3151                 t4_write_reg(adap, port_base_addr + i, 0);
3152         for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
3153              i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
3154                 t4_write_reg(adap, port_base_addr + i, 0);
3155         for (i = 0; i < 4; i++)
3156                 if (bgmap & (1 << i)) {
3157                         t4_write_reg(adap,
3158                                      A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
3159                                      i * 8, 0);
3160                         t4_write_reg(adap,
3161                                      A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
3162                                      i * 8, 0);
3163                 }
3164 }
3165
3166 /**
3167  * t4_fw_hello - establish communication with FW
3168  * @adap: the adapter
3169  * @mbox: mailbox to use for the FW command
3170  * @evt_mbox: mailbox to receive async FW events
3171  * @master: specifies the caller's willingness to be the device master
3172  * @state: returns the current device state (if non-NULL)
3173  *
3174  * Issues a command to establish communication with FW.  Returns either
3175  * an error (negative integer) or the mailbox of the Master PF.
3176  */
3177 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
3178                 enum dev_master master, enum dev_state *state)
3179 {
3180         int ret;
3181         struct fw_hello_cmd c;
3182         u32 v;
3183         unsigned int master_mbox;
3184         int retries = FW_CMD_HELLO_RETRIES;
3185
3186 retry:
3187         memset(&c, 0, sizeof(c));
3188         INIT_CMD(c, HELLO, WRITE);
3189         c.err_to_clearinit = cpu_to_be32(
3190                         V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
3191                         V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
3192                         V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
3193                                                 M_FW_HELLO_CMD_MBMASTER) |
3194                         V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
3195                         V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
3196                         F_FW_HELLO_CMD_CLEARINIT);
3197
3198         /*
3199          * Issue the HELLO command to the firmware.  If it's not successful
3200          * but indicates that we got a "busy" or "timeout" condition, retry
3201          * the HELLO until we exhaust our retry limit.  If we do exceed our
3202          * retry limit, check to see if the firmware left us any error
3203          * information and report that if so ...
3204          */
3205         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3206         if (ret != FW_SUCCESS) {
3207                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
3208                         goto retry;
3209                 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
3210                         t4_report_fw_error(adap);
3211                 return ret;
3212         }
3213
3214         v = be32_to_cpu(c.err_to_clearinit);
3215         master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
3216         if (state) {
3217                 if (v & F_FW_HELLO_CMD_ERR)
3218                         *state = DEV_STATE_ERR;
3219                 else if (v & F_FW_HELLO_CMD_INIT)
3220                         *state = DEV_STATE_INIT;
3221                 else
3222                         *state = DEV_STATE_UNINIT;
3223         }
3224
3225         /*
3226          * If we're not the Master PF then we need to wait around for the
3227          * Master PF Driver to finish setting up the adapter.
3228          *
3229          * Note that we also do this wait if we're a non-Master-capable PF and
3230          * there is no current Master PF; a Master PF may show up momentarily
3231          * and we wouldn't want to fail pointlessly.  (This can happen when an
3232          * OS loads lots of different drivers rapidly at the same time).  In
3233          * this case, the Master PF returned by the firmware will be
3234          * M_PCIE_FW_MASTER so the test below will work ...
3235          */
3236         if ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&
3237             master_mbox != mbox) {
3238                 int waiting = FW_CMD_HELLO_TIMEOUT;
3239
3240                 /*
3241                  * Wait for the firmware to either indicate an error or
3242                  * initialized state.  If we see either of these we bail out
3243                  * and report the issue to the caller.  If we exhaust the
3244                  * "hello timeout" and we haven't exhausted our retries, try
3245                  * again.  Otherwise bail with a timeout error.
3246                  */
3247                 for (;;) {
3248                         u32 pcie_fw;
3249
3250                         msleep(50);
3251                         waiting -= 50;
3252
3253                         /*
3254                          * If neither Error nor Initialialized are indicated
3255                          * by the firmware keep waiting till we exaust our
3256                          * timeout ... and then retry if we haven't exhausted
3257                          * our retries ...
3258                          */
3259                         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
3260                         if (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {
3261                                 if (waiting <= 0) {
3262                                         if (retries-- > 0)
3263                                                 goto retry;
3264
3265                                         return -ETIMEDOUT;
3266                                 }
3267                                 continue;
3268                         }
3269
3270                         /*
3271                          * We either have an Error or Initialized condition
3272                          * report errors preferentially.
3273                          */
3274                         if (state) {
3275                                 if (pcie_fw & F_PCIE_FW_ERR)
3276                                         *state = DEV_STATE_ERR;
3277                                 else if (pcie_fw & F_PCIE_FW_INIT)
3278                                         *state = DEV_STATE_INIT;
3279                         }
3280
3281                         /*
3282                          * If we arrived before a Master PF was selected and
3283                          * there's not a valid Master PF, grab its identity
3284                          * for our caller.
3285                          */
3286                         if (master_mbox == M_PCIE_FW_MASTER &&
3287                             (pcie_fw & F_PCIE_FW_MASTER_VLD))
3288                                 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
3289                         break;
3290                 }
3291         }
3292
3293         return master_mbox;
3294 }
3295
3296 /**
3297  * t4_fw_bye - end communication with FW
3298  * @adap: the adapter
3299  * @mbox: mailbox to use for the FW command
3300  *
3301  * Issues a command to terminate communication with FW.
3302  */
3303 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
3304 {
3305         struct fw_bye_cmd c;
3306
3307         memset(&c, 0, sizeof(c));
3308         INIT_CMD(c, BYE, WRITE);
3309         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3310 }
3311
3312 /**
3313  * t4_fw_reset - issue a reset to FW
3314  * @adap: the adapter
3315  * @mbox: mailbox to use for the FW command
3316  * @reset: specifies the type of reset to perform
3317  *
3318  * Issues a reset command of the specified type to FW.
3319  */
3320 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
3321 {
3322         struct fw_reset_cmd c;
3323
3324         memset(&c, 0, sizeof(c));
3325         INIT_CMD(c, RESET, WRITE);
3326         c.val = cpu_to_be32(reset);
3327         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3328 }
3329
3330 /**
3331  * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
3332  * @adap: the adapter
3333  * @mbox: mailbox to use for the FW RESET command (if desired)
3334  * @force: force uP into RESET even if FW RESET command fails
3335  *
3336  * Issues a RESET command to firmware (if desired) with a HALT indication
3337  * and then puts the microprocessor into RESET state.  The RESET command
3338  * will only be issued if a legitimate mailbox is provided (mbox <=
3339  * M_PCIE_FW_MASTER).
3340  *
3341  * This is generally used in order for the host to safely manipulate the
3342  * adapter without fear of conflicting with whatever the firmware might
3343  * be doing.  The only way out of this state is to RESTART the firmware
3344  * ...
3345  */
3346 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
3347 {
3348         int ret = 0;
3349
3350         /*
3351          * If a legitimate mailbox is provided, issue a RESET command
3352          * with a HALT indication.
3353          */
3354         if (mbox <= M_PCIE_FW_MASTER) {
3355                 struct fw_reset_cmd c;
3356
3357                 memset(&c, 0, sizeof(c));
3358                 INIT_CMD(c, RESET, WRITE);
3359                 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
3360                 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
3361                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3362         }
3363
3364         /*
3365          * Normally we won't complete the operation if the firmware RESET
3366          * command fails but if our caller insists we'll go ahead and put the
3367          * uP into RESET.  This can be useful if the firmware is hung or even
3368          * missing ...  We'll have to take the risk of putting the uP into
3369          * RESET without the cooperation of firmware in that case.
3370          *
3371          * We also force the firmware's HALT flag to be on in case we bypassed
3372          * the firmware RESET command above or we're dealing with old firmware
3373          * which doesn't have the HALT capability.  This will serve as a flag
3374          * for the incoming firmware to know that it's coming out of a HALT
3375          * rather than a RESET ... if it's new enough to understand that ...
3376          */
3377         if (ret == 0 || force) {
3378                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
3379                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
3380                                  F_PCIE_FW_HALT);
3381         }
3382
3383         /*
3384          * And we always return the result of the firmware RESET command
3385          * even when we force the uP into RESET ...
3386          */
3387         return ret;
3388 }
3389
3390 /**
3391  * t4_fw_restart - restart the firmware by taking the uP out of RESET
3392  * @adap: the adapter
3393  * @mbox: mailbox to use for the FW RESET command (if desired)
3394  * @reset: if we want to do a RESET to restart things
3395  *
3396  * Restart firmware previously halted by t4_fw_halt().  On successful
3397  * return the previous PF Master remains as the new PF Master and there
3398  * is no need to issue a new HELLO command, etc.
3399  *
3400  * We do this in two ways:
3401  *
3402  * 1. If we're dealing with newer firmware we'll simply want to take
3403  *    the chip's microprocessor out of RESET.  This will cause the
3404  *    firmware to start up from its start vector.  And then we'll loop
3405  *    until the firmware indicates it's started again (PCIE_FW.HALT
3406  *    reset to 0) or we timeout.
3407  *
3408  * 2. If we're dealing with older firmware then we'll need to RESET
3409  *    the chip since older firmware won't recognize the PCIE_FW.HALT
3410  *    flag and automatically RESET itself on startup.
3411  */
3412 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
3413 {
3414         if (reset) {
3415                 /*
3416                  * Since we're directing the RESET instead of the firmware
3417                  * doing it automatically, we need to clear the PCIE_FW.HALT
3418                  * bit.
3419                  */
3420                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
3421
3422                 /*
3423                  * If we've been given a valid mailbox, first try to get the
3424                  * firmware to do the RESET.  If that works, great and we can
3425                  * return success.  Otherwise, if we haven't been given a
3426                  * valid mailbox or the RESET command failed, fall back to
3427                  * hitting the chip with a hammer.
3428                  */
3429                 if (mbox <= M_PCIE_FW_MASTER) {
3430                         t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3431                         msleep(100);
3432                         if (t4_fw_reset(adap, mbox,
3433                                         F_PIORST | F_PIORSTMODE) == 0)
3434                                 return 0;
3435                 }
3436
3437                 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
3438                 msleep(2000);
3439         } else {
3440                 int ms;
3441
3442                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3443                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
3444                         if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
3445                                 return FW_SUCCESS;
3446                         msleep(100);
3447                         ms += 100;
3448                 }
3449                 return -ETIMEDOUT;
3450         }
3451         return 0;
3452 }
3453
3454 /**
3455  * t4_fl_pkt_align - return the fl packet alignment
3456  * @adap: the adapter
3457  *
3458  * T4 has a single field to specify the packing and padding boundary.
3459  * T5 onwards has separate fields for this and hence the alignment for
3460  * next packet offset is maximum of these two.
3461  */
3462 int t4_fl_pkt_align(struct adapter *adap)
3463 {
3464         u32 sge_control, sge_control2;
3465         unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
3466
3467         sge_control = t4_read_reg(adap, A_SGE_CONTROL);
3468
3469         /* T4 uses a single control field to specify both the PCIe Padding and
3470          * Packing Boundary.  T5 introduced the ability to specify these
3471          * separately.  The actual Ingress Packet Data alignment boundary
3472          * within Packed Buffer Mode is the maximum of these two
3473          * specifications.
3474          */
3475         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
3476                 ingpad_shift = X_INGPADBOUNDARY_SHIFT;
3477         else
3478                 ingpad_shift = X_T6_INGPADBOUNDARY_SHIFT;
3479
3480         ingpadboundary = 1 << (G_INGPADBOUNDARY(sge_control) + ingpad_shift);
3481
3482         fl_align = ingpadboundary;
3483         if (!is_t4(adap->params.chip)) {
3484                 sge_control2 = t4_read_reg(adap, A_SGE_CONTROL2);
3485                 ingpackboundary = G_INGPACKBOUNDARY(sge_control2);
3486                 if (ingpackboundary == X_INGPACKBOUNDARY_16B)
3487                         ingpackboundary = 16;
3488                 else
3489                         ingpackboundary = 1 << (ingpackboundary +
3490                                         X_INGPACKBOUNDARY_SHIFT);
3491
3492                 fl_align = max(ingpadboundary, ingpackboundary);
3493         }
3494         return fl_align;
3495 }
3496
3497 /**
3498  * t4_fixup_host_params_compat - fix up host-dependent parameters
3499  * @adap: the adapter
3500  * @page_size: the host's Base Page Size
3501  * @cache_line_size: the host's Cache Line Size
3502  * @chip_compat: maintain compatibility with designated chip
3503  *
3504  * Various registers in the chip contain values which are dependent on the
3505  * host's Base Page and Cache Line Sizes.  This function will fix all of
3506  * those registers with the appropriate values as passed in ...
3507  *
3508  * @chip_compat is used to limit the set of changes that are made
3509  * to be compatible with the indicated chip release.  This is used by
3510  * drivers to maintain compatibility with chip register settings when
3511  * the drivers haven't [yet] been updated with new chip support.
3512  */
3513 int t4_fixup_host_params_compat(struct adapter *adap,
3514                                 unsigned int page_size,
3515                                 unsigned int cache_line_size,
3516                                 enum chip_type chip_compat)
3517 {
3518         unsigned int page_shift = cxgbe_fls(page_size) - 1;
3519         unsigned int sge_hps = page_shift - 10;
3520         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
3521         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
3522         unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
3523
3524         t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
3525                      V_HOSTPAGESIZEPF0(sge_hps) |
3526                      V_HOSTPAGESIZEPF1(sge_hps) |
3527                      V_HOSTPAGESIZEPF2(sge_hps) |
3528                      V_HOSTPAGESIZEPF3(sge_hps) |
3529                      V_HOSTPAGESIZEPF4(sge_hps) |
3530                      V_HOSTPAGESIZEPF5(sge_hps) |
3531                      V_HOSTPAGESIZEPF6(sge_hps) |
3532                      V_HOSTPAGESIZEPF7(sge_hps));
3533
3534         if (is_t4(adap->params.chip) || is_t4(chip_compat))
3535                 t4_set_reg_field(adap, A_SGE_CONTROL,
3536                                  V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3537                                  F_EGRSTATUSPAGESIZE,
3538                                  V_INGPADBOUNDARY(fl_align_log -
3539                                                   X_INGPADBOUNDARY_SHIFT) |
3540                                 V_EGRSTATUSPAGESIZE(stat_len != 64));
3541         else {
3542                 unsigned int pack_align;
3543                 unsigned int ingpad, ingpack;
3544                 unsigned int pcie_cap;
3545
3546                 /*
3547                  * T5 introduced the separation of the Free List Padding and
3548                  * Packing Boundaries.  Thus, we can select a smaller Padding
3549                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
3550                  * Bandwidth, and use a Packing Boundary which is large enough
3551                  * to avoid false sharing between CPUs, etc.
3552                  *
3553                  * For the PCI Link, the smaller the Padding Boundary the
3554                  * better.  For the Memory Controller, a smaller Padding
3555                  * Boundary is better until we cross under the Memory Line
3556                  * Size (the minimum unit of transfer to/from Memory).  If we
3557                  * have a Padding Boundary which is smaller than the Memory
3558                  * Line Size, that'll involve a Read-Modify-Write cycle on the
3559                  * Memory Controller which is never good.
3560                  */
3561
3562                 /* We want the Packing Boundary to be based on the Cache Line
3563                  * Size in order to help avoid False Sharing performance
3564                  * issues between CPUs, etc.  We also want the Packing
3565                  * Boundary to incorporate the PCI-E Maximum Payload Size.  We
3566                  * get best performance when the Packing Boundary is a
3567                  * multiple of the Maximum Payload Size.
3568                  */
3569                 pack_align = fl_align;
3570                 pcie_cap = t4_os_find_pci_capability(adap, PCI_CAP_ID_EXP);
3571                 if (pcie_cap) {
3572                         unsigned int mps, mps_log;
3573                         u16 devctl;
3574
3575                         /* The PCIe Device Control Maximum Payload Size field
3576                          * [bits 7:5] encodes sizes as powers of 2 starting at
3577                          * 128 bytes.
3578                          */
3579                         t4_os_pci_read_cfg2(adap, pcie_cap + PCI_EXP_DEVCTL,
3580                                             &devctl);
3581                         mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
3582                         mps = 1 << mps_log;
3583                         if (mps > pack_align)
3584                                 pack_align = mps;
3585                 }
3586
3587                 /*
3588                  * N.B. T5 has a different interpretation of the "0" value for
3589                  * the Packing Boundary.  This corresponds to 16 bytes instead
3590                  * of the expected 32 bytes.  We never have a Packing Boundary
3591                  * less than 32 bytes so we can't use that special value but
3592                  * on the other hand, if we wanted 32 bytes, the best we can
3593                  * really do is 64 bytes ...
3594                  */
3595                 if (pack_align <= 16) {
3596                         ingpack = X_INGPACKBOUNDARY_16B;
3597                         fl_align = 16;
3598                 } else if (pack_align == 32) {
3599                         ingpack = X_INGPACKBOUNDARY_64B;
3600                         fl_align = 64;
3601                 } else {
3602                         unsigned int pack_align_log = cxgbe_fls(pack_align) - 1;
3603
3604                         ingpack = pack_align_log - X_INGPACKBOUNDARY_SHIFT;
3605                         fl_align = pack_align;
3606                 }
3607
3608                 /* Use the smallest Ingress Padding which isn't smaller than
3609                  * the Memory Controller Read/Write Size.  We'll take that as
3610                  * being 8 bytes since we don't know of any system with a
3611                  * wider Memory Controller Bus Width.
3612                  */
3613                 if (is_t5(adap->params.chip))
3614                         ingpad = X_INGPADBOUNDARY_32B;
3615                 else
3616                         ingpad = X_T6_INGPADBOUNDARY_8B;
3617                 t4_set_reg_field(adap, A_SGE_CONTROL,
3618                                  V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3619                                  F_EGRSTATUSPAGESIZE,
3620                                  V_INGPADBOUNDARY(ingpad) |
3621                                  V_EGRSTATUSPAGESIZE(stat_len != 64));
3622                 t4_set_reg_field(adap, A_SGE_CONTROL2,
3623                                  V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
3624                                  V_INGPACKBOUNDARY(ingpack));
3625         }
3626
3627         /*
3628          * Adjust various SGE Free List Host Buffer Sizes.
3629          *
3630          * The first four entries are:
3631          *
3632          *   0: Host Page Size
3633          *   1: 64KB
3634          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
3635          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
3636          *
3637          * For the single-MTU buffers in unpacked mode we need to include
3638          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
3639          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
3640          * Padding boundary.  All of these are accommodated in the Factory
3641          * Default Firmware Configuration File but we need to adjust it for
3642          * this host's cache line size.
3643          */
3644         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
3645         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
3646                      (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
3647                      & ~(fl_align - 1));
3648         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
3649                      (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
3650                      & ~(fl_align - 1));
3651
3652         t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
3653
3654         return 0;
3655 }
3656
3657 /**
3658  * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)
3659  * @adap: the adapter
3660  * @page_size: the host's Base Page Size
3661  * @cache_line_size: the host's Cache Line Size
3662  *
3663  * Various registers in T4 contain values which are dependent on the
3664  * host's Base Page and Cache Line Sizes.  This function will fix all of
3665  * those registers with the appropriate values as passed in ...
3666  *
3667  * This routine makes changes which are compatible with T4 chips.
3668  */
3669 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
3670                          unsigned int cache_line_size)
3671 {
3672         return t4_fixup_host_params_compat(adap, page_size, cache_line_size,
3673                                            T4_LAST_REV);
3674 }
3675
3676 /**
3677  * t4_fw_initialize - ask FW to initialize the device
3678  * @adap: the adapter
3679  * @mbox: mailbox to use for the FW command
3680  *
3681  * Issues a command to FW to partially initialize the device.  This
3682  * performs initialization that generally doesn't depend on user input.
3683  */
3684 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
3685 {
3686         struct fw_initialize_cmd c;
3687
3688         memset(&c, 0, sizeof(c));
3689         INIT_CMD(c, INITIALIZE, WRITE);
3690         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3691 }
3692
3693 /**
3694  * t4_query_params_rw - query FW or device parameters
3695  * @adap: the adapter
3696  * @mbox: mailbox to use for the FW command
3697  * @pf: the PF
3698  * @vf: the VF
3699  * @nparams: the number of parameters
3700  * @params: the parameter names
3701  * @val: the parameter values
3702  * @rw: Write and read flag
3703  *
3704  * Reads the value of FW or device parameters.  Up to 7 parameters can be
3705  * queried at once.
3706  */
3707 static int t4_query_params_rw(struct adapter *adap, unsigned int mbox,
3708                               unsigned int pf, unsigned int vf,
3709                               unsigned int nparams, const u32 *params,
3710                               u32 *val, int rw)
3711 {
3712         unsigned int i;
3713         int ret;
3714         struct fw_params_cmd c;
3715         __be32 *p = &c.param[0].mnem;
3716
3717         if (nparams > 7)
3718                 return -EINVAL;
3719
3720         memset(&c, 0, sizeof(c));
3721         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3722                                   F_FW_CMD_REQUEST | F_FW_CMD_READ |
3723                                   V_FW_PARAMS_CMD_PFN(pf) |
3724                                   V_FW_PARAMS_CMD_VFN(vf));
3725         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3726
3727         for (i = 0; i < nparams; i++) {
3728                 *p++ = cpu_to_be32(*params++);
3729                 if (rw)
3730                         *p = cpu_to_be32(*(val + i));
3731                 p++;
3732         }
3733
3734         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3735         if (ret == 0)
3736                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
3737                         *val++ = be32_to_cpu(*p);
3738         return ret;
3739 }
3740
3741 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3742                     unsigned int vf, unsigned int nparams, const u32 *params,
3743                     u32 *val)
3744 {
3745         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
3746 }
3747
3748 /**
3749  * t4_set_params_timeout - sets FW or device parameters
3750  * @adap: the adapter
3751  * @mbox: mailbox to use for the FW command
3752  * @pf: the PF
3753  * @vf: the VF
3754  * @nparams: the number of parameters
3755  * @params: the parameter names
3756  * @val: the parameter values
3757  * @timeout: the timeout time
3758  *
3759  * Sets the value of FW or device parameters.  Up to 7 parameters can be
3760  * specified at once.
3761  */
3762 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
3763                           unsigned int pf, unsigned int vf,
3764                           unsigned int nparams, const u32 *params,
3765                           const u32 *val, int timeout)
3766 {
3767         struct fw_params_cmd c;
3768         __be32 *p = &c.param[0].mnem;
3769
3770         if (nparams > 7)
3771                 return -EINVAL;
3772
3773         memset(&c, 0, sizeof(c));
3774         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3775                                   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3776                                   V_FW_PARAMS_CMD_PFN(pf) |
3777                                   V_FW_PARAMS_CMD_VFN(vf));
3778         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3779
3780         while (nparams--) {
3781                 *p++ = cpu_to_be32(*params++);
3782                 *p++ = cpu_to_be32(*val++);
3783         }
3784
3785         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
3786 }
3787
3788 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3789                   unsigned int vf, unsigned int nparams, const u32 *params,
3790                   const u32 *val)
3791 {
3792         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
3793                                      FW_CMD_MAX_TIMEOUT);
3794 }
3795
3796 /**
3797  * t4_alloc_vi_func - allocate a virtual interface
3798  * @adap: the adapter
3799  * @mbox: mailbox to use for the FW command
3800  * @port: physical port associated with the VI
3801  * @pf: the PF owning the VI
3802  * @vf: the VF owning the VI
3803  * @nmac: number of MAC addresses needed (1 to 5)
3804  * @mac: the MAC addresses of the VI
3805  * @rss_size: size of RSS table slice associated with this VI
3806  * @portfunc: which Port Application Function MAC Address is desired
3807  * @idstype: Intrusion Detection Type
3808  *
3809  * Allocates a virtual interface for the given physical port.  If @mac is
3810  * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3811  * @mac should be large enough to hold @nmac Ethernet addresses, they are
3812  * stored consecutively so the space needed is @nmac * 6 bytes.
3813  * Returns a negative error number or the non-negative VI id.
3814  */
3815 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
3816                      unsigned int port, unsigned int pf, unsigned int vf,
3817                      unsigned int nmac, u8 *mac, unsigned int *rss_size,
3818                      unsigned int portfunc, unsigned int idstype)
3819 {
3820         int ret;
3821         struct fw_vi_cmd c;
3822
3823         memset(&c, 0, sizeof(c));
3824         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3825                                   F_FW_CMD_WRITE | F_FW_CMD_EXEC |
3826                                   V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
3827         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
3828         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
3829                                      V_FW_VI_CMD_FUNC(portfunc));
3830         c.portid_pkd = V_FW_VI_CMD_PORTID(port);
3831         c.nmac = nmac - 1;
3832
3833         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3834         if (ret)
3835                 return ret;
3836
3837         if (mac) {
3838                 memcpy(mac, c.mac, sizeof(c.mac));
3839                 switch (nmac) {
3840                 case 5:
3841                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
3842                         /* FALLTHROUGH */
3843                 case 4:
3844                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
3845                         /* FALLTHROUGH */
3846                 case 3:
3847                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
3848                         /* FALLTHROUGH */
3849                 case 2:
3850                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
3851                         /* FALLTHROUGH */
3852                 }
3853         }
3854         if (rss_size)
3855                 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
3856         return G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));
3857 }
3858
3859 /**
3860  * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
3861  * @adap: the adapter
3862  * @mbox: mailbox to use for the FW command
3863  * @port: physical port associated with the VI
3864  * @pf: the PF owning the VI
3865  * @vf: the VF owning the VI
3866  * @nmac: number of MAC addresses needed (1 to 5)
3867  * @mac: the MAC addresses of the VI
3868  * @rss_size: size of RSS table slice associated with this VI
3869  *
3870  * Backwards compatible and convieniance routine to allocate a Virtual
3871  * Interface with a Ethernet Port Application Function and Intrustion
3872  * Detection System disabled.
3873  */
3874 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
3875                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
3876                 unsigned int *rss_size)
3877 {
3878         return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
3879                                 FW_VI_FUNC_ETH, 0);
3880 }
3881
3882 /**
3883  * t4_free_vi - free a virtual interface
3884  * @adap: the adapter
3885  * @mbox: mailbox to use for the FW command
3886  * @pf: the PF owning the VI
3887  * @vf: the VF owning the VI
3888  * @viid: virtual interface identifiler
3889  *
3890  * Free a previously allocated virtual interface.
3891  */
3892 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
3893                unsigned int vf, unsigned int viid)
3894 {
3895         struct fw_vi_cmd c;
3896
3897         memset(&c, 0, sizeof(c));
3898         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3899                                   F_FW_CMD_EXEC | V_FW_VI_CMD_PFN(pf) |
3900                                   V_FW_VI_CMD_VFN(vf));
3901         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
3902         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
3903
3904         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3905 }
3906
3907 /**
3908  * t4_set_rxmode - set Rx properties of a virtual interface
3909  * @adap: the adapter
3910  * @mbox: mailbox to use for the FW command
3911  * @viid: the VI id
3912  * @mtu: the new MTU or -1
3913  * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
3914  * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
3915  * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
3916  * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,
3917  *          -1 no change
3918  * @sleep_ok: if true we may sleep while awaiting command completion
3919  *
3920  * Sets Rx properties of a virtual interface.
3921  */
3922 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
3923                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
3924                   bool sleep_ok)
3925 {
3926         struct fw_vi_rxmode_cmd c;
3927
3928         /* convert to FW values */
3929         if (mtu < 0)
3930                 mtu = M_FW_VI_RXMODE_CMD_MTU;
3931         if (promisc < 0)
3932                 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
3933         if (all_multi < 0)
3934                 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
3935         if (bcast < 0)
3936                 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
3937         if (vlanex < 0)
3938                 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
3939
3940         memset(&c, 0, sizeof(c));
3941         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
3942                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3943                                    V_FW_VI_RXMODE_CMD_VIID(viid));
3944         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3945         c.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
3946                             V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
3947                             V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
3948                             V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
3949                             V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
3950         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3951 }
3952
3953 /**
3954  * t4_change_mac - modifies the exact-match filter for a MAC address
3955  * @adap: the adapter
3956  * @mbox: mailbox to use for the FW command
3957  * @viid: the VI id
3958  * @idx: index of existing filter for old value of MAC address, or -1
3959  * @addr: the new MAC address value
3960  * @persist: whether a new MAC allocation should be persistent
3961  * @add_smt: if true also add the address to the HW SMT
3962  *
3963  * Modifies an exact-match filter and sets it to the new MAC address if
3964  * @idx >= 0, or adds the MAC address to a new filter if @idx < 0.  In the
3965  * latter case the address is added persistently if @persist is %true.
3966  *
3967  * Note that in general it is not possible to modify the value of a given
3968  * filter so the generic way to modify an address filter is to free the one
3969  * being used by the old address value and allocate a new filter for the
3970  * new address value.
3971  *
3972  * Returns a negative error number or the index of the filter with the new
3973  * MAC value.  Note that this index may differ from @idx.
3974  */
3975 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
3976                   int idx, const u8 *addr, bool persist, bool add_smt)
3977 {
3978         int ret, mode;
3979         struct fw_vi_mac_cmd c;
3980         struct fw_vi_mac_exact *p = c.u.exact;
3981         int max_mac_addr = adap->params.arch.mps_tcam_size;
3982
3983         if (idx < 0)                             /* new allocation */
3984                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
3985         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
3986
3987         memset(&c, 0, sizeof(c));
3988         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
3989                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3990                                    V_FW_VI_MAC_CMD_VIID(viid));
3991         c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
3992         p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
3993                                       V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
3994                                       V_FW_VI_MAC_CMD_IDX(idx));
3995         memcpy(p->macaddr, addr, sizeof(p->macaddr));
3996
3997         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3998         if (ret == 0) {
3999                 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
4000                 if (ret >= max_mac_addr)
4001                         ret = -ENOMEM;
4002         }
4003         return ret;
4004 }
4005
4006 /**
4007  * t4_enable_vi_params - enable/disable a virtual interface
4008  * @adap: the adapter
4009  * @mbox: mailbox to use for the FW command
4010  * @viid: the VI id
4011  * @rx_en: 1=enable Rx, 0=disable Rx
4012  * @tx_en: 1=enable Tx, 0=disable Tx
4013  * @dcb_en: 1=enable delivery of Data Center Bridging messages.
4014  *
4015  * Enables/disables a virtual interface.  Note that setting DCB Enable
4016  * only makes sense when enabling a Virtual Interface ...
4017  */
4018 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
4019                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
4020 {
4021         struct fw_vi_enable_cmd c;
4022
4023         memset(&c, 0, sizeof(c));
4024         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
4025                                    F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4026                                    V_FW_VI_ENABLE_CMD_VIID(viid));
4027         c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
4028                                      V_FW_VI_ENABLE_CMD_EEN(tx_en) |
4029                                      V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
4030                                      FW_LEN16(c));
4031         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
4032 }
4033
4034 /**
4035  * t4_enable_vi - enable/disable a virtual interface
4036  * @adap: the adapter
4037  * @mbox: mailbox to use for the FW command
4038  * @viid: the VI id
4039  * @rx_en: 1=enable Rx, 0=disable Rx
4040  * @tx_en: 1=enable Tx, 0=disable Tx
4041  *
4042  * Enables/disables a virtual interface.  Note that setting DCB Enable
4043  * only makes sense when enabling a Virtual Interface ...
4044  */
4045 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
4046                  bool rx_en, bool tx_en)
4047 {
4048         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
4049 }
4050
4051 /**
4052  * t4_iq_start_stop - enable/disable an ingress queue and its FLs
4053  * @adap: the adapter
4054  * @mbox: mailbox to use for the FW command
4055  * @start: %true to enable the queues, %false to disable them
4056  * @pf: the PF owning the queues
4057  * @vf: the VF owning the queues
4058  * @iqid: ingress queue id
4059  * @fl0id: FL0 queue id or 0xffff if no attached FL0
4060  * @fl1id: FL1 queue id or 0xffff if no attached FL1
4061  *
4062  * Starts or stops an ingress queue and its associated FLs, if any.
4063  */
4064 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
4065                      unsigned int pf, unsigned int vf, unsigned int iqid,
4066                      unsigned int fl0id, unsigned int fl1id)
4067 {
4068         struct fw_iq_cmd c;
4069
4070         memset(&c, 0, sizeof(c));
4071         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4072                                   F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
4073                                   V_FW_IQ_CMD_VFN(vf));
4074         c.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |
4075                                        V_FW_IQ_CMD_IQSTOP(!start) |
4076                                        FW_LEN16(c));
4077         c.iqid = cpu_to_be16(iqid);
4078         c.fl0id = cpu_to_be16(fl0id);
4079         c.fl1id = cpu_to_be16(fl1id);
4080         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4081 }
4082
4083 /**
4084  * t4_iq_free - free an ingress queue and its FLs
4085  * @adap: the adapter
4086  * @mbox: mailbox to use for the FW command
4087  * @pf: the PF owning the queues
4088  * @vf: the VF owning the queues
4089  * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
4090  * @iqid: ingress queue id
4091  * @fl0id: FL0 queue id or 0xffff if no attached FL0
4092  * @fl1id: FL1 queue id or 0xffff if no attached FL1
4093  *
4094  * Frees an ingress queue and its associated FLs, if any.
4095  */
4096 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4097                unsigned int vf, unsigned int iqtype, unsigned int iqid,
4098                unsigned int fl0id, unsigned int fl1id)
4099 {
4100         struct fw_iq_cmd c;
4101
4102         memset(&c, 0, sizeof(c));
4103         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4104                                   F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
4105                                   V_FW_IQ_CMD_VFN(vf));
4106         c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
4107         c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
4108         c.iqid = cpu_to_be16(iqid);
4109         c.fl0id = cpu_to_be16(fl0id);
4110         c.fl1id = cpu_to_be16(fl1id);
4111         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4112 }
4113
4114 /**
4115  * t4_eth_eq_free - free an Ethernet egress queue
4116  * @adap: the adapter
4117  * @mbox: mailbox to use for the FW command
4118  * @pf: the PF owning the queue
4119  * @vf: the VF owning the queue
4120  * @eqid: egress queue id
4121  *
4122  * Frees an Ethernet egress queue.
4123  */
4124 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4125                    unsigned int vf, unsigned int eqid)
4126 {
4127         struct fw_eq_eth_cmd c;
4128
4129         memset(&c, 0, sizeof(c));
4130         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
4131                                   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4132                                   V_FW_EQ_ETH_CMD_PFN(pf) |
4133                                   V_FW_EQ_ETH_CMD_VFN(vf));
4134         c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
4135         c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
4136         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4137 }
4138
4139 /**
4140  * t4_handle_fw_rpl - process a FW reply message
4141  * @adap: the adapter
4142  * @rpl: start of the FW message
4143  *
4144  * Processes a FW message, such as link state change messages.
4145  */
4146 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
4147 {
4148         u8 opcode = *(const u8 *)rpl;
4149
4150         /*
4151          * This might be a port command ... this simplifies the following
4152          * conditionals ...  We can get away with pre-dereferencing
4153          * action_to_len16 because it's in the first 16 bytes and all messages
4154          * will be at least that long.
4155          */
4156         const struct fw_port_cmd *p = (const void *)rpl;
4157         unsigned int action =
4158                 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
4159
4160         if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
4161                 /* link/module state change message */
4162                 unsigned int speed = 0, fc = 0, i;
4163                 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
4164                 struct port_info *pi = NULL;
4165                 struct link_config *lc;
4166                 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
4167                 int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
4168                 u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
4169
4170                 if (stat & F_FW_PORT_CMD_RXPAUSE)
4171                         fc |= PAUSE_RX;
4172                 if (stat & F_FW_PORT_CMD_TXPAUSE)
4173                         fc |= PAUSE_TX;
4174                 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
4175                         speed = ETH_SPEED_NUM_100M;
4176                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
4177                         speed = ETH_SPEED_NUM_1G;
4178                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
4179                         speed = ETH_SPEED_NUM_10G;
4180                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
4181                         speed = ETH_SPEED_NUM_25G;
4182                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
4183                         speed = ETH_SPEED_NUM_40G;
4184                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
4185                         speed = ETH_SPEED_NUM_100G;
4186
4187                 for_each_port(adap, i) {
4188                         pi = adap2pinfo(adap, i);
4189                         if (pi->tx_chan == chan)
4190                                 break;
4191                 }
4192                 lc = &pi->link_cfg;
4193
4194                 if (mod != pi->mod_type) {
4195                         pi->mod_type = mod;
4196                         t4_os_portmod_changed(adap, i);
4197                 }
4198                 if (link_ok != lc->link_ok || speed != lc->speed ||
4199                     fc != lc->fc) {                    /* something changed */
4200                         if (!link_ok && lc->link_ok) {
4201                                 static const char * const reason[] = {
4202                                         "Link Down",
4203                                         "Remote Fault",
4204                                         "Auto-negotiation Failure",
4205                                         "Reserved",
4206                                         "Insufficient Airflow",
4207                                         "Unable To Determine Reason",
4208                                         "No RX Signal Detected",
4209                                         "Reserved",
4210                                 };
4211                                 unsigned int rc = G_FW_PORT_CMD_LINKDNRC(stat);
4212
4213                                 dev_warn(adap, "Port %d link down, reason: %s\n",
4214                                          chan, reason[rc]);
4215                         }
4216                         lc->link_ok = link_ok;
4217                         lc->speed = speed;
4218                         lc->fc = fc;
4219                         lc->supported = be16_to_cpu(p->u.info.pcap);
4220                 }
4221         } else {
4222                 dev_warn(adap, "Unknown firmware reply %d\n", opcode);
4223                 return -EINVAL;
4224         }
4225         return 0;
4226 }
4227
4228 void t4_reset_link_config(struct adapter *adap, int idx)
4229 {
4230         struct port_info *pi = adap2pinfo(adap, idx);
4231         struct link_config *lc = &pi->link_cfg;
4232
4233         lc->link_ok = 0;
4234         lc->requested_speed = 0;
4235         lc->requested_fc = 0;
4236         lc->speed = 0;
4237         lc->fc = 0;
4238 }
4239
4240 /**
4241  * init_link_config - initialize a link's SW state
4242  * @lc: structure holding the link state
4243  * @pcaps: link Port Capabilities
4244  * @acaps: link current Advertised Port Capabilities
4245  *
4246  * Initializes the SW state maintained for each link, including the link's
4247  * capabilities and default speed/flow-control/autonegotiation settings.
4248  */
4249 static void init_link_config(struct link_config *lc, unsigned int pcaps,
4250                              unsigned int acaps)
4251 {
4252         unsigned int fec;
4253
4254         lc->supported = pcaps;
4255         lc->requested_speed = 0;
4256         lc->speed = 0;
4257         lc->requested_fc = 0;
4258         lc->fc = 0;
4259
4260         /**
4261          * For Forward Error Control, we default to whatever the Firmware
4262          * tells us the Link is currently advertising.
4263          */
4264         fec = 0;
4265         if (acaps & FW_PORT_CAP_FEC_RS)
4266                 fec |= FEC_RS;
4267         if (acaps & FW_PORT_CAP_FEC_BASER_RS)
4268                 fec |= FEC_BASER_RS;
4269         if (acaps & FW_PORT_CAP_FEC_RESERVED)
4270                 fec |= FEC_RESERVED;
4271         lc->requested_fec = fec;
4272         lc->fec = fec;
4273
4274         if (lc->supported & FW_PORT_CAP_ANEG) {
4275                 lc->advertising = lc->supported & ADVERT_MASK;
4276                 lc->autoneg = AUTONEG_ENABLE;
4277         } else {
4278                 lc->advertising = 0;
4279                 lc->autoneg = AUTONEG_DISABLE;
4280         }
4281 }
4282
4283 /**
4284  * t4_wait_dev_ready - wait till to reads of registers work
4285  *
4286  * Right after the device is RESET is can take a small amount of time
4287  * for it to respond to register reads.  Until then, all reads will
4288  * return either 0xff...ff or 0xee...ee.  Return an error if reads
4289  * don't work within a reasonable time frame.
4290  */
4291 static int t4_wait_dev_ready(struct adapter *adapter)
4292 {
4293         u32 whoami;
4294
4295         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4296
4297         if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4298                 return 0;
4299
4300         msleep(500);
4301         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4302         if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4303                 return 0;
4304
4305         dev_err(adapter, "Device didn't become ready for access, whoami = %#x\n",
4306                 whoami);
4307         return -EIO;
4308 }
4309
4310 struct flash_desc {
4311         u32 vendor_and_model_id;
4312         u32 size_mb;
4313 };
4314
4315 int t4_get_flash_params(struct adapter *adapter)
4316 {
4317         /*
4318          * Table for non-Numonix supported flash parts.  Numonix parts are left
4319          * to the preexisting well-tested code.  All flash parts have 64KB
4320          * sectors.
4321          */
4322         static struct flash_desc supported_flash[] = {
4323                 { 0x00150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
4324         };
4325
4326         int ret;
4327         u32 flashid = 0;
4328         unsigned int part, manufacturer;
4329         unsigned int density, size;
4330
4331         /**
4332          * Issue a Read ID Command to the Flash part.  We decode supported
4333          * Flash parts and their sizes from this.  There's a newer Query
4334          * Command which can retrieve detailed geometry information but
4335          * many Flash parts don't support it.
4336          */
4337         ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
4338         if (!ret)
4339                 ret = sf1_read(adapter, 3, 0, 1, &flashid);
4340         t4_write_reg(adapter, A_SF_OP, 0);               /* unlock SF */
4341         if (ret < 0)
4342                 return ret;
4343
4344         for (part = 0; part < ARRAY_SIZE(supported_flash); part++) {
4345                 if (supported_flash[part].vendor_and_model_id == flashid) {
4346                         adapter->params.sf_size =
4347                                 supported_flash[part].size_mb;
4348                         adapter->params.sf_nsec =
4349                                 adapter->params.sf_size / SF_SEC_SIZE;
4350                         goto found;
4351                 }
4352         }
4353
4354         manufacturer = flashid & 0xff;
4355         switch (manufacturer) {
4356         case 0x20: { /* Micron/Numonix */
4357                 /**
4358                  * This Density -> Size decoding table is taken from Micron
4359                  * Data Sheets.
4360                  */
4361                 density = (flashid >> 16) & 0xff;
4362                 switch (density) {
4363                 case 0x14:
4364                         size = 1 << 20; /* 1MB */
4365                         break;
4366                 case 0x15:
4367                         size = 1 << 21; /* 2MB */
4368                         break;
4369                 case 0x16:
4370                         size = 1 << 22; /* 4MB */
4371                         break;
4372                 case 0x17:
4373                         size = 1 << 23; /* 8MB */
4374                         break;
4375                 case 0x18:
4376                         size = 1 << 24; /* 16MB */
4377                         break;
4378                 case 0x19:
4379                         size = 1 << 25; /* 32MB */
4380                         break;
4381                 case 0x20:
4382                         size = 1 << 26; /* 64MB */
4383                         break;
4384                 case 0x21:
4385                         size = 1 << 27; /* 128MB */
4386                         break;
4387                 case 0x22:
4388                         size = 1 << 28; /* 256MB */
4389                         break;
4390                 default:
4391                         dev_err(adapter, "Micron Flash Part has bad size, ID = %#x, Density code = %#x\n",
4392                                 flashid, density);
4393                         return -EINVAL;
4394                 }
4395
4396                 adapter->params.sf_size = size;
4397                 adapter->params.sf_nsec = size / SF_SEC_SIZE;
4398                 break;
4399         }
4400         default:
4401                 dev_err(adapter, "Unsupported Flash Part, ID = %#x\n", flashid);
4402                 return -EINVAL;
4403         }
4404
4405 found:
4406         /*
4407          * We should reject adapters with FLASHes which are too small. So, emit
4408          * a warning.
4409          */
4410         if (adapter->params.sf_size < FLASH_MIN_SIZE)
4411                 dev_warn(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
4412                          flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
4413
4414         return 0;
4415 }
4416
4417 static void set_pcie_completion_timeout(struct adapter *adapter,
4418                                         u8 range)
4419 {
4420         u32 pcie_cap;
4421         u16 val;
4422
4423         pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
4424         if (pcie_cap) {
4425                 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
4426                 val &= 0xfff0;
4427                 val |= range;
4428                 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
4429         }
4430 }
4431
4432 /**
4433  * t4_get_chip_type - Determine chip type from device ID
4434  * @adap: the adapter
4435  * @ver: adapter version
4436  */
4437 int t4_get_chip_type(struct adapter *adap, int ver)
4438 {
4439         enum chip_type chip = 0;
4440         u32 pl_rev = G_REV(t4_read_reg(adap, A_PL_REV));
4441
4442         /* Retrieve adapter's device ID */
4443         switch (ver) {
4444         case CHELSIO_T5:
4445                 chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4446                 break;
4447         case CHELSIO_T6:
4448                 chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4449                 break;
4450         default:
4451                 dev_err(adap, "Device %d is not supported\n",
4452                         adap->params.pci.device_id);
4453                 return -EINVAL;
4454         }
4455
4456         return chip;
4457 }
4458
4459 /**
4460  * t4_prep_adapter - prepare SW and HW for operation
4461  * @adapter: the adapter
4462  *
4463  * Initialize adapter SW state for the various HW modules, set initial
4464  * values for some adapter tunables, take PHYs out of reset, and
4465  * initialize the MDIO interface.
4466  */
4467 int t4_prep_adapter(struct adapter *adapter)
4468 {
4469         int ret, ver;
4470         u32 pl_rev;
4471
4472         ret = t4_wait_dev_ready(adapter);
4473         if (ret < 0)
4474                 return ret;
4475
4476         pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
4477         adapter->params.pci.device_id = adapter->pdev->id.device_id;
4478         adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
4479
4480         /*
4481          * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
4482          * ADAPTER (VERSION << 4 | REVISION)
4483          */
4484         ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
4485         adapter->params.chip = 0;
4486         switch (ver) {
4487         case CHELSIO_T5:
4488                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4489                 adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
4490                 adapter->params.arch.mps_tcam_size =
4491                                                 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4492                 adapter->params.arch.mps_rplc_size = 128;
4493                 adapter->params.arch.nchan = NCHAN;
4494                 adapter->params.arch.vfcount = 128;
4495                 break;
4496         case CHELSIO_T6:
4497                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4498                 adapter->params.arch.sge_fl_db = 0;
4499                 adapter->params.arch.mps_tcam_size =
4500                                                 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4501                 adapter->params.arch.mps_rplc_size = 256;
4502                 adapter->params.arch.nchan = 2;
4503                 adapter->params.arch.vfcount = 256;
4504                 break;
4505         default:
4506                 dev_err(adapter, "%s: Device %d is not supported\n",
4507                         __func__, adapter->params.pci.device_id);
4508                 return -EINVAL;
4509         }
4510
4511         adapter->params.pci.vpd_cap_addr =
4512                 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
4513
4514         ret = t4_get_flash_params(adapter);
4515         if (ret < 0) {
4516                 dev_err(adapter, "Unable to retrieve Flash Parameters, ret = %d\n",
4517                         -ret);
4518                 return ret;
4519         }
4520
4521         adapter->params.cim_la_size = CIMLA_SIZE;
4522
4523         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
4524
4525         /*
4526          * Default port and clock for debugging in case we can't reach FW.
4527          */
4528         adapter->params.nports = 1;
4529         adapter->params.portvec = 1;
4530         adapter->params.vpd.cclk = 50000;
4531
4532         /* Set pci completion timeout value to 4 seconds. */
4533         set_pcie_completion_timeout(adapter, 0xd);
4534         return 0;
4535 }
4536
4537 /**
4538  * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
4539  * @adapter: the adapter
4540  * @qid: the Queue ID
4541  * @qtype: the Ingress or Egress type for @qid
4542  * @pbar2_qoffset: BAR2 Queue Offset
4543  * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
4544  *
4545  * Returns the BAR2 SGE Queue Registers information associated with the
4546  * indicated Absolute Queue ID.  These are passed back in return value
4547  * pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
4548  * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
4549  *
4550  * This may return an error which indicates that BAR2 SGE Queue
4551  * registers aren't available.  If an error is not returned, then the
4552  * following values are returned:
4553  *
4554  *   *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
4555  *   *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
4556  *
4557  * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
4558  * require the "Inferred Queue ID" ability may be used.  E.g. the
4559  * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
4560  * then these "Inferred Queue ID" register may not be used.
4561  */
4562 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
4563                       enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
4564                       unsigned int *pbar2_qid)
4565 {
4566         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
4567         u64 bar2_page_offset, bar2_qoffset;
4568         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
4569
4570         /*
4571          * T4 doesn't support BAR2 SGE Queue registers.
4572          */
4573         if (is_t4(adapter->params.chip))
4574                 return -EINVAL;
4575
4576         /*
4577          * Get our SGE Page Size parameters.
4578          */
4579         page_shift = adapter->params.sge.hps + 10;
4580         page_size = 1 << page_shift;
4581
4582         /*
4583          * Get the right Queues per Page parameters for our Queue.
4584          */
4585         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?
4586                               adapter->params.sge.eq_qpp :
4587                               adapter->params.sge.iq_qpp);
4588         qpp_mask = (1 << qpp_shift) - 1;
4589
4590         /*
4591          * Calculate the basics of the BAR2 SGE Queue register area:
4592          *  o The BAR2 page the Queue registers will be in.
4593          *  o The BAR2 Queue ID.
4594          *  o The BAR2 Queue ID Offset into the BAR2 page.
4595          */
4596         bar2_page_offset = ((qid >> qpp_shift) << page_shift);
4597         bar2_qid = qid & qpp_mask;
4598         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
4599
4600         /*
4601          * If the BAR2 Queue ID Offset is less than the Page Size, then the
4602          * hardware will infer the Absolute Queue ID simply from the writes to
4603          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
4604          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
4605          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
4606          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
4607          * from the BAR2 Page and BAR2 Queue ID.
4608          *
4609          * One important censequence of this is that some BAR2 SGE registers
4610          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
4611          * there.  But other registers synthesize the SGE Queue ID purely
4612          * from the writes to the registers -- the Write Combined Doorbell
4613          * Buffer is a good example.  These BAR2 SGE Registers are only
4614          * available for those BAR2 SGE Register areas where the SGE Absolute
4615          * Queue ID can be inferred from simple writes.
4616          */
4617         bar2_qoffset = bar2_page_offset;
4618         bar2_qinferred = (bar2_qid_offset < page_size);
4619         if (bar2_qinferred) {
4620                 bar2_qoffset += bar2_qid_offset;
4621                 bar2_qid = 0;
4622         }
4623
4624         *pbar2_qoffset = bar2_qoffset;
4625         *pbar2_qid = bar2_qid;
4626         return 0;
4627 }
4628
4629 /**
4630  * t4_init_sge_params - initialize adap->params.sge
4631  * @adapter: the adapter
4632  *
4633  * Initialize various fields of the adapter's SGE Parameters structure.
4634  */
4635 int t4_init_sge_params(struct adapter *adapter)
4636 {
4637         struct sge_params *sge_params = &adapter->params.sge;
4638         u32 hps, qpp;
4639         unsigned int s_hps, s_qpp;
4640
4641         /*
4642          * Extract the SGE Page Size for our PF.
4643          */
4644         hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
4645         s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *
4646                  adapter->pf);
4647         sge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);
4648
4649         /*
4650          * Extract the SGE Egress and Ingess Queues Per Page for our PF.
4651          */
4652         s_qpp = (S_QUEUESPERPAGEPF0 +
4653                  (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);
4654         qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
4655         sge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4656         qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
4657         sge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4658
4659         return 0;
4660 }
4661
4662 /**
4663  * t4_init_tp_params - initialize adap->params.tp
4664  * @adap: the adapter
4665  *
4666  * Initialize various fields of the adapter's TP Parameters structure.
4667  */
4668 int t4_init_tp_params(struct adapter *adap)
4669 {
4670         int chan;
4671         u32 v;
4672
4673         v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
4674         adap->params.tp.tre = G_TIMERRESOLUTION(v);
4675         adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
4676
4677         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
4678         for (chan = 0; chan < NCHAN; chan++)
4679                 adap->params.tp.tx_modq[chan] = chan;
4680
4681         /*
4682          * Cache the adapter's Compressed Filter Mode and global Incress
4683          * Configuration.
4684          */
4685         t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4686                          &adap->params.tp.vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
4687         t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4688                          &adap->params.tp.ingress_config, 1,
4689                          A_TP_INGRESS_CONFIG);
4690
4691         /* For T6, cache the adapter's compressed error vector
4692          * and passing outer header info for encapsulated packets.
4693          */
4694         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
4695                 v = t4_read_reg(adap, A_TP_OUT_CONFIG);
4696                 adap->params.tp.rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
4697         }
4698
4699         /*
4700          * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
4701          * shift positions of several elements of the Compressed Filter Tuple
4702          * for this adapter which we need frequently ...
4703          */
4704         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
4705         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
4706         adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
4707         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
4708                                                                F_PROTOCOL);
4709
4710         /*
4711          * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
4712          * represents the presense of an Outer VLAN instead of a VNIC ID.
4713          */
4714         if ((adap->params.tp.ingress_config & F_VNIC) == 0)
4715                 adap->params.tp.vnic_shift = -1;
4716
4717         return 0;
4718 }
4719
4720 /**
4721  * t4_filter_field_shift - calculate filter field shift
4722  * @adap: the adapter
4723  * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
4724  *
4725  * Return the shift position of a filter field within the Compressed
4726  * Filter Tuple.  The filter field is specified via its selection bit
4727  * within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
4728  */
4729 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)
4730 {
4731         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
4732         unsigned int sel;
4733         int field_shift;
4734
4735         if ((filter_mode & filter_sel) == 0)
4736                 return -1;
4737
4738         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
4739                 switch (filter_mode & sel) {
4740                 case F_FCOE:
4741                         field_shift += W_FT_FCOE;
4742                         break;
4743                 case F_PORT:
4744                         field_shift += W_FT_PORT;
4745                         break;
4746                 case F_VNIC_ID:
4747                         field_shift += W_FT_VNIC_ID;
4748                         break;
4749                 case F_VLAN:
4750                         field_shift += W_FT_VLAN;
4751                         break;
4752                 case F_TOS:
4753                         field_shift += W_FT_TOS;
4754                         break;
4755                 case F_PROTOCOL:
4756                         field_shift += W_FT_PROTOCOL;
4757                         break;
4758                 case F_ETHERTYPE:
4759                         field_shift += W_FT_ETHERTYPE;
4760                         break;
4761                 case F_MACMATCH:
4762                         field_shift += W_FT_MACMATCH;
4763                         break;
4764                 case F_MPSHITTYPE:
4765                         field_shift += W_FT_MPSHITTYPE;
4766                         break;
4767                 case F_FRAGMENTATION:
4768                         field_shift += W_FT_FRAGMENTATION;
4769                         break;
4770                 }
4771         }
4772         return field_shift;
4773 }
4774
4775 int t4_init_rss_mode(struct adapter *adap, int mbox)
4776 {
4777         int i, ret;
4778         struct fw_rss_vi_config_cmd rvc;
4779
4780         memset(&rvc, 0, sizeof(rvc));
4781
4782         for_each_port(adap, i) {
4783                 struct port_info *p = adap2pinfo(adap, i);
4784
4785                 rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
4786                                        F_FW_CMD_REQUEST | F_FW_CMD_READ |
4787                                        V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
4788                 rvc.retval_len16 = htonl(FW_LEN16(rvc));
4789                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
4790                 if (ret)
4791                         return ret;
4792                 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
4793         }
4794         return 0;
4795 }
4796
4797 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
4798 {
4799         u8 addr[6];
4800         int ret, i, j = 0;
4801         struct fw_port_cmd c;
4802
4803         memset(&c, 0, sizeof(c));
4804
4805         for_each_port(adap, i) {
4806                 unsigned int rss_size = 0;
4807                 struct port_info *p = adap2pinfo(adap, i);
4808
4809                 while ((adap->params.portvec & (1 << j)) == 0)
4810                         j++;
4811
4812                 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
4813                                              F_FW_CMD_REQUEST | F_FW_CMD_READ |
4814                                              V_FW_PORT_CMD_PORTID(j));
4815                 c.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(
4816                                                 FW_PORT_ACTION_GET_PORT_INFO) |
4817                                                 FW_LEN16(c));
4818                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4819                 if (ret)
4820                         return ret;
4821
4822                 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
4823                 if (ret < 0)
4824                         return ret;
4825
4826                 p->viid = ret;
4827                 p->tx_chan = j;
4828                 p->rss_size = rss_size;
4829                 t4_os_set_hw_addr(adap, i, addr);
4830
4831                 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
4832                 p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
4833                                 G_FW_PORT_CMD_MDIOADDR(ret) : -1;
4834                 p->port_type = G_FW_PORT_CMD_PTYPE(ret);
4835                 p->mod_type = FW_PORT_MOD_TYPE_NA;
4836
4837                 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap),
4838                                  be16_to_cpu(c.u.info.acap));
4839                 j++;
4840         }
4841         return 0;
4842 }