1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
10 CPL_ACT_OPEN_REQ = 0x3,
11 CPL_SET_TCB_FIELD = 0x5,
14 CPL_TID_RELEASE = 0x1A,
15 CPL_ACT_OPEN_RPL = 0x25,
16 CPL_ABORT_RPL_RSS = 0x2D,
17 CPL_SET_TCB_RPL = 0x3A,
18 CPL_ACT_OPEN_REQ6 = 0x83,
19 CPL_SGE_EGR_UPDATE = 0xA5,
22 CPL_TX_PKT_LSO = 0xED,
28 CPL_ERR_TCAM_FULL = 3,
36 CPL_ABORT_SEND_RST = 0,
40 enum { /* TX_PKT_XT checksum types */
51 #define S_CPL_OPCODE 24
52 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)
54 #define G_TID(x) ((x) & 0xFFFFFF)
56 /* tid is assumed to be 24-bits */
57 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid))
59 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
61 /* extract the TID from a CPL command */
62 #define GET_TID(cmd) (G_TID(be32_to_cpu(OPCODE_TID(cmd))))
64 /* partitioning of TID fields that also carry a queue id */
66 #define M_TID_TID 0x3fff
67 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID)
71 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
90 #if defined(RSS_HDR_VLD) || defined(CHELSIO_FW)
91 #define RSS_HDR struct rss_header rss_hdr
97 struct work_request_hdr {
103 #define WR_HDR struct work_request_hdr wr
104 #define WR_HDR_SIZE sizeof(struct work_request_hdr)
107 #define WR_HDR_SIZE 0
112 #define V_COOKIE(x) ((x) << S_COOKIE)
113 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE)
115 /* option 0 fields */
117 #define V_DELACK(x) ((x) << S_DELACK)
119 #define S_NON_OFFLOAD 7
120 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD)
121 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U)
124 #define V_ULP_MODE(x) ((x) << S_ULP_MODE)
126 #define S_SMAC_SEL 28
127 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL)
129 #define S_TCAM_BYPASS 48
130 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS)
131 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL)
133 /* option 2 fields */
134 #define S_RSS_QUEUE 0
135 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE)
137 #define S_RSS_QUEUE_VALID 10
138 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID)
139 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U)
141 #define S_CONG_CNTRL 14
142 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL)
144 #define S_RX_CHANNEL 26
145 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL)
146 #define F_RX_CHANNEL V_RX_CHANNEL(1U)
148 #define S_T5_OPT_2_VALID 31
149 #define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID)
150 #define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U)
152 struct cpl_t6_act_open_req {
167 struct cpl_t6_act_open_req6 {
184 #define S_FILTER_TUPLE 24
185 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE)
187 struct cpl_act_open_rpl {
193 /* cpl_act_open_rpl.atid_status fields */
194 #define S_AOPEN_STATUS 0
195 #define M_AOPEN_STATUS 0xFF
196 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS)
198 #define S_AOPEN_ATID 8
199 #define M_AOPEN_ATID 0xFFFFFF
200 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID)
202 struct cpl_set_tcb_field {
211 /* cpl_set_tcb_field.word_cookie fields */
213 #define V_WORD(x) ((x) << S_WORD)
215 /* cpl_get_tcb.reply_ctrl fields */
217 #define V_QUEUENO(x) ((x) << S_QUEUENO)
219 #define S_REPLY_CHAN 14
220 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN)
222 #define S_NO_REPLY 15
223 #define V_NO_REPLY(x) ((x) << S_NO_REPLY)
225 struct cpl_set_tcb_rpl {
234 /* cpl_abort_req status command code
236 struct cpl_abort_req {
245 struct cpl_abort_rpl_rss {
252 struct cpl_abort_rpl {
261 struct cpl_tid_release {
274 struct cpl_tx_pkt_core {
283 struct cpl_tx_pkt_core c;
286 /* cpl_tx_pkt_core.ctrl0 fields */
288 #define M_TXPKT_PF 0x7
289 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF)
290 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF)
292 #define S_TXPKT_INTF 16
293 #define M_TXPKT_INTF 0xF
294 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
295 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
297 #define S_TXPKT_OPCODE 24
298 #define M_TXPKT_OPCODE 0xFF
299 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
300 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
302 /* cpl_tx_pkt_core.ctrl1 fields */
303 #define S_TXPKT_IPHDR_LEN 20
304 #define M_TXPKT_IPHDR_LEN 0x3FFF
305 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN)
306 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN)
308 #define S_TXPKT_ETHHDR_LEN 34
309 #define M_TXPKT_ETHHDR_LEN 0x3F
310 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN)
311 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN)
313 #define S_T6_TXPKT_ETHHDR_LEN 32
314 #define M_T6_TXPKT_ETHHDR_LEN 0xFF
315 #define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN)
316 #define G_T6_TXPKT_ETHHDR_LEN(x) \
317 (((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN)
319 #define S_TXPKT_CSUM_TYPE 40
320 #define M_TXPKT_CSUM_TYPE 0xF
321 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE)
322 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE)
324 #define S_TXPKT_VLAN 44
325 #define M_TXPKT_VLAN 0xFFFF
326 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN)
327 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
329 #define S_TXPKT_VLAN_VLD 60
330 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD)
331 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL)
333 #define S_TXPKT_IPCSUM_DIS 62
334 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS)
335 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL)
337 #define S_TXPKT_L4CSUM_DIS 63
338 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS)
339 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL)
341 struct cpl_tx_pkt_lso_core {
347 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
350 struct cpl_tx_pkt_lso {
352 struct cpl_tx_pkt_lso_core c;
353 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
356 /* cpl_tx_pkt_lso_core.lso_ctrl fields */
357 #define S_LSO_TCPHDR_LEN 0
358 #define M_LSO_TCPHDR_LEN 0xF
359 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN)
360 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN)
362 #define S_LSO_IPHDR_LEN 4
363 #define M_LSO_IPHDR_LEN 0xFFF
364 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN)
365 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN)
367 #define S_LSO_ETHHDR_LEN 16
368 #define M_LSO_ETHHDR_LEN 0xF
369 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN)
370 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN)
372 #define S_LSO_IPV6 20
373 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
374 #define F_LSO_IPV6 V_LSO_IPV6(1U)
376 #define S_LSO_LAST_SLICE 22
377 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE)
378 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U)
380 #define S_LSO_FIRST_SLICE 23
381 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE)
382 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U)
384 #define S_LSO_OPCODE 24
385 #define M_LSO_OPCODE 0xFF
386 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE)
387 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE)
389 #define S_LSO_T5_XFER_SIZE 0
390 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF
391 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE)
392 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE)
397 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
418 /* rx_pkt.l2info fields */
420 #define V_RXF_UDP(x) ((x) << S_RXF_UDP)
421 #define F_RXF_UDP V_RXF_UDP(1U)
424 #define V_RXF_TCP(x) ((x) << S_RXF_TCP)
425 #define F_RXF_TCP V_RXF_TCP(1U)
428 #define V_RXF_IP(x) ((x) << S_RXF_IP)
429 #define F_RXF_IP V_RXF_IP(1U)
432 #define V_RXF_IP6(x) ((x) << S_RXF_IP6)
433 #define F_RXF_IP6 V_RXF_IP6(1U)
435 /* rx_pkt.err_vec fields */
436 /* In T6, rx_pkt.err_vec indicates
437 * RxError Error vector (16b) or
438 * Encapsulating header length (8b),
439 * Outer encapsulation type (2b) and
440 * compressed error vector (6b) if CRxPktEnc is
441 * enabled in TP_OUT_CONFIG
443 #define S_T6_COMPR_RXERR_VEC 0
444 #define M_T6_COMPR_RXERR_VEC 0x3F
445 #define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC)
446 #define G_T6_COMPR_RXERR_VEC(x) \
447 (((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC)
449 /* cpl_fw*.type values */
478 ULP_TX_SC_NOOP = 0x80,
479 ULP_TX_SC_IMM = 0x81,
480 ULP_TX_SC_DSGL = 0x82,
481 ULP_TX_SC_ISGL = 0x83
484 #define S_ULPTX_CMD 24
485 #define M_ULPTX_CMD 0xFF
486 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
488 #define S_ULP_TX_SC_MORE 23
489 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE)
490 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U)
492 struct ulptx_sge_pair {
502 #if !(defined C99_NOT_SUPPORTED)
503 struct ulptx_sge_pair sge[0];
513 #define S_ULPTX_NSGE 0
514 #define M_ULPTX_NSGE 0xFFFF
515 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE)
522 /* ulp_txpkt.cmd_dest fields */
523 #define S_ULP_TXPKT_DEST 16
524 #define M_ULP_TXPKT_DEST 0x3
525 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
527 #define S_ULP_TXPKT_FID 4
528 #define M_ULP_TXPKT_FID 0x7ff
529 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID)
531 #define S_ULP_TXPKT_RO 3
532 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO)
533 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U)
535 #endif /* T4_MSG_H */